PIC32MX450 [MICROCHIP]
32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog; 32位微控制器（高达512 KB的闪存和128 KB的SRAM）与音频/图形/触摸（ HMI ） ，USB和高级模拟
| 型号： | PIC32MX450 |
| 厂家： | 
MICROCHIP |
| 描述： | 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog |
| 文件： | 总344页 (文件大小：12360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC32MX330/350/370/430/450/470
32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)
with Audio/Graphics/Touch (HMI), USB, and Advanced Analog
Operating Conditions
Timers/Output Compare/Input Capture
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz
• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow function remap
• Real-Time Clock and Calendar (RTCC) module
Core: 80 MHz/105 DMIPS MIPS32® M4K®
• MIPS16e mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
®
Clock Management
• 0.9% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast wake-up and start-up
Communication Interfaces
• USB 2.0-compliant Full-speed OTG controller
• Up to five UART modules (20 Mbps):
- Supports LIN 1.2 protocols and IrDA support
®
• Two 4-wire SPI modules (25 Mbps)
2
• Two I C modules (up to 1 Mbaud) with SMBus support
Power Management
• PPS to allow function remap
• Parallel Master Port (PMP)
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset, Brown-out Reset, and High
Voltage Detect
• 0.5 mA/MHz dynamic current (typical)
• 40 μA IPD current (typical)
Direct Memory Access (DMA)
• Four channels of hardware DMA with automatic data
size detection
• 32-bit Programmable Cyclic Redundancy Check (CRC)
• Two additional channels dedicated to USB
Audio/Graphics/Touch HMI Features
• External graphics interface with up to 34 PMP pins
Input/Output
• 15 mA or 12 mA source/sink for standard VOH/VOL and
up to 22 mA for non-standard VOH
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
2
• Audio data communication: I S, LJ, RJ, USB
2
• Audio data control interface: SPI and I C™
1
• Audio data master clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
Qualification and Class B Support
• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned
• Class B Safety Library, IEC 60730
Advanced Analog Features
• ADC Module:
- 10-bit 1 Msps rate with one Sample and Hold (S&H)
- Up to 28 analog inputs
Debugger Development Support
• In-circuit and in-application programming
®
• 4-wire MIPS Enhanced JTAG interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
- Can operate during Sleep mode
• Flexible and independent ADC trigger sources
• On-chip temperature measurement capability
• Comparators:
- Two dual-input Comparator modules
- Programmable references with 32 voltage points
Packages
Type
QFN
TQFP
VTLA
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
64
53
64
53
100
85
100
85
124
85
0.50
0.50
0.40
0.50
0.50
9x9x0.9
10x10x1
12x12x1
14x14x1
9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 1
PIC32MX330/350/370/430/450/470
TABLE 1:
PIC32MX330/350/370/430/450/470 CONTROLLER FAMILY FEATURES
Remappable Peripherals
QFN,
TQFP
PIC32MX330F064H 64
64+12
64+12
16
16
37 5/5/5
54 5/5/5
37 5/5/5
54 5/5/5
37 5/5/5
54 5/5/5
4
5
4
5
4
5
5
5
4
5
4
5
4
5
4
5
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4/0
4/0
4/0
4/0
4/0
4/0
4/0
4/0
4/2
4/2
4/2
4/2
4/2
4/2
4/2
4/2
53
85
53
85
53
85
51
83
51
83
51
83
51
83
51
83
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
Y
100 TQFP
124 VTLA
QFN,
PIC32MX330F064L
PIC32MX350F128H 64
128+12 32
128+12 32
256+12 64
256+12 64
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX350F128L
PIC32MX350F256H 64
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX350F256L
PIC32MX370F512H 64
512+12 128 37 5/5/5
512+12 128 54 5/5/5
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX370F512L
PIC32MX430F064H 64
64+12
64+12
16
16
34 5/5/5
51 5/5/5
34 5/5/5
51 5/5/5
34 5/5/5
51 5/5/5
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX430F064L
PIC32MX450F128H 64
128+12 32
128+12 32
256+12 64
256+12 64
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX450F128L
PIC32MX450F256H 64
TQFP
100 TQFP
124 VTLA
QFN,
PIC32MX450F256L
PIC32MX470F512H 64
512+12 128 34 5/5/5
512+12 128 51 5/5/5
TQFP
100 TQFP
124 VTLA
PIC32MX470F512L
Note 1:
All devices feature 12 KB of Boot Flash memory.
Four out of five timers are remappable.
Four out of five external interrupts are remappable.
2:
3:
DS60001185B-page 2
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Pin Diagrams
(1,2,3)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AN22/RPE5/PMD5/RE5
SOSCO/RPC14/T1CK/RC14
SOSCI/RPC13/RC13
RPD0/RD0
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN23/PMD6/RE6
AN27/PMD7/RE7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
RPD11/PMCS1/RD11
RPD10/PMCS2/RD10
RPD9/RD9
RPD8/RTCC/RD8
VSS
PIC32MX330F064H
PIC32MX350F128H
PIC32MX350F256H
PIC32MX370F512H
AN19/C2INC/RPG9/PMA2/RG9
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
VDD
AN5/C1INA/RPB5/RB5
AN4/C1INB/RB4
SCL1/RG2
SDA1/RG3
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
RPF6/SCK1/INT0/RF6
RPF2/RF2
PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
RPF3/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
2:
3:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See
Section 12.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 3
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1,2,3)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/RPC14/T1CK/RC14
SOSCI/RPC13/RC13
RPD0/INT0/RD0
RPD11/PMCS1/RD11
SCL1/RPD10/PMCS2/RD10
SDA1/RPD9/RD9
RPD8/RTCC/RD8
VSS
AN27/PMD7/RE7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
PIC32MX430F064H
PIC32MX450F128H
PIC32MX450F256H
PIC32MX470F512H
AN19/C2INC/RPG9/PMA2/RG9
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
VDD
AN5/C1INA/RPB5/VBUSON/RB5
AN4/C1INB/RB4
D+
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
D-
VUSB
VBUS
3V3
USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
2:
3:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See
Section 12.0 “I/O Ports” for more information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS60001185B-page 4
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1,2)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AN22/RPE5/PMD5/RE5
1
2
SOSCO/RPC14/T1CK/RC14
SOSCI/RPC13/RC13
RPD0/RD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN23/PMD6/RE6
AN27/PMD7/RE7
3
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
4
RPD11/PMCS1/RD11
RPD10/PMCS2/RD10
RPD9/RD9
5
6
7
RPD8/RTCC/RD8
VSS
PIC32MX330F064H
PIC32MX350F128H
PIC32MX350F256H
PIC32MX370F512H
8
AN19/C2INC/RPG9/PMA2/RG9
VSS
9
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
10
11
12
13
14
15
16
VDD
AN5/C1INA/RPB5/RB5
AN4/C1INB/RB4
SCL1/RG2
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
SDA1/RG3
RPF6/SCK1/INT0/RF6
RPF2/RF2
PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0
RPF3/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
2:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See
Section 12.0 “I/O Ports” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 5
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1,2)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AN22/RPE5/PMD5/RE5
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/RPC14/T1CK/RC14
AN23/PMD6/RE6
AN27/PMD7/RE7
2
3
SOSCI/RPC13/RC13
RPD0/INT0/RD0
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
RPD11/PMCS1/RD11
SCL1/RPD10/PMCS2/RD10
4
5
AN18/C2IND/RPG8/PMA3/RG8
6
SDA1/RPD9/RD9
RPD8/RTCC/RD8
7
MCLR
PIC32MX430F064H
PIC32MX450F128H
PIC32MX450F256H
PIC32MX470F512H
AN19/C2INC/RPG9/PMA2/RG9
8
VSS
VSS
VDD
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
9
10
11
12
AN5/C1INA/RPB5/VBUSON/RB5
AN4/C1INB/RB4
D+
D-
PGED3/AN3/C2INA/RPB3/RB3 13
VUSB3V3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
14
15
VBUS
PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1
USBID/RF3
PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
2:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See
Section 12.0 “I/O Ports” for more information.
DS60001185B-page 6
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1,2)
= Pins are up to 5V tolerant
100-Pin TQFP
V
SS
RG15
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
SOSCO/RPC14/T1CK/RC14
SOSCI/RPC13/RC13
RPD0/RD0
VDD
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
RPD11/PMCS1/RD11
RPD10/PMCS2/RD10
RPD9/RD9
AN27/PMD7/RE7
RPC1/RC1
RPC2/RC2
RPD8/RTCC/RD8
RPA15/RA15
RPC3/RC3
RPC4/CTED7/RC4
9
RPA14/RA14
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
PIC32MX330F064L
PIC32MX350F128L
PIC32MX350F256L
PIC32MX370F512L
OSC2/CLKO/RC15
OSC1/CLKI/RC12
MCLR
VDD
AN19/C2INC/RPG9/PMA2/RG9
TDO/RA5
VSS
TDI/CTED9/RA4
SDA2/RA3
VDD
TMS/CTED1/RA0
RPE8/RE8
SCL2/RA2
SCL1/RG2
RPE9/RE9
SDA1/RG3
AN5/C1INA/RPB5/RB5
AN4/C1INB/RB4
RPF6/SCK1/INT0/RF6
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
PGEC1/AN1/RPB1/CTED12/RB1
PGED1/AN0/RPB0/RB0
RPF7/RF7
RPF8/RF8
RPF2/RF2
RPF3/RF3
Note 1:
2:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See
Section 12.0 “I/O Ports” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 7
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1,2)
= Pins are up to 5V tolerant
100-Pin TQFP
Vss
RG15
75
74
73
72
71
70
69
68
1
2
3
4
5
6
7
8
VDD
SOSCO/RPC14/T1CK/RC14
SOSCI/RPC13/RC13
AN22/RPE5/PMD5/RE5
AN23/PMD6/RE6
RPD0/INT0/RD0
RPD11/PMCS1/RD11
AN27/PMD7/RE7
RPD10/SCK1/PMCS2/RD10
RPC1/RC1
RPD9/RD9
RPC2/RC2
RPD8/RTCC/RD8
RPC3/RC3
SDA1/RPA15/RA15
RPC4/CTED7/RC4
67
66
9
SCL1/RPA14/RA14
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN17/C1INC/RPG7/PMA4/RG7
AN18/C2IND/RPG8/PMA3/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PIC32MX430F064L
PIC32MX450F128L
PIC32MX450F256L
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
AN19/C2INC/RPG9/PMA2/RG9
PIC32MX470F512L
TDO/RA5
TDI/CTED9/RA4
SDA2/RA3
SCL2/RA2
D+
VSS
VDD
TMS/CTED1/RA0
RPE8/RE8
RPE9/RE9
D-
AN5/C1INA/RPB5/VBUSON/RB5
AN4/C1INB/RB4
VUSB
3V3
VBUS
PGED3/AN3/C2INA/RPB3/RB3
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
PGEC1/AN1/RPB1/CTED12/RB1
PGED1/AN0/RPB0/RB0
RPF8/RF8
RPF2/RF2
USBID/RF3
Note 1:
2:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral
Pin Select” for restrictions.
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNCx). See
Section 12.0 “I/O Ports” for more information.
DS60001185B-page 8
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1)
= Pins are up to 5V tolerant
124-Pin VTLA
A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51
A1
A2
A3
A4
A5
A6
A7
A8
A9
B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50
B1
B2
B3
B4
B5
B6
B7
B8
A49
B41 A48
B40 A47
B39 A46
B38 A45
B37 A44
B36 A43
PIC32MX330F064L
PIC32MX350F128L
B35 A42
PIC32MX350F256L
PIC32MX370F512L
A10 B9
A11 B10
A12 B11
B34 A41
B33 A40
B32 A39
A13 B12
A14 B13
A15
B31 A38
B30 A37
B29 A36
A16 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28
A35
A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34
Note 1: See Table 2 for the full list of pin names.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 9
PIC32MX330/350/370/430/450/470
(1,2)
TABLE 2:
PIN NAMES: PIC32MX3XXL DEVICES
Package
Bump #
Package
Bump #
Full Pin Name
Full Pin Name
A1
A2
No Connect
AN24/RPD1/RD1
AN26/RPD3/RD3
PMD13/RD13
RPD5/PMRD/RD5
PMD15/RD7
No Connect
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
B1
RG15
VSS
A3
A4
AN23/PMD6/RE6
A5
RPC1/RC1
A6
RPC3/RC3
A7
AN16/C1IND/RPG6/SCK2/PMA5/RG6
No Connect
A8
AN18/C2IND/RPG8/PMA3/RG8
AN19/C2INC/RPG9/PMA2/RG9
VDD
No Connect
A9
RPF1/PMD10/RF1
RPG0/PMD8/RG0
TRD3/CTED8/RA7
VSS
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
Note 1:
RPE8/RE8
AN5/C1INA/RPB5/RB5
PGED3/AN3/C2INA/RPB3/RB3
VDD
PMD1/RE1
TRD1/RG12
PGEC1/AN1/RPB1/CTED12/RB1
No Connect
AN20/PMD2/RE2
AN21/PMD4/RE4
No Connect
No Connect
No Connect
VDD
No Connect
B2
AN22/RPE5/PMD5/RE5
AN27/PMD7/RE7
RPC2/RC2
PGEC2/AN6/RPB6/RB6
VREF-/CVREF-/PMA7/RA9
AVDD
B3
B4
RPC4/CTED7/RC4
AN17/C1INC/RPG7/PMA4/RG7
MCLR
B5
AN8/RPB8/CTED10/RB8
CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10
B6
B7
VSS
B8
VSS
TCK/CTED2/RA1
RPF12/RF12
AN13/PMA10/RB13
AN15/RPB15/OCFB/CTED6/PMA0/RB15
VDD
B9
TMS/CTED1/RA0
RPE9/RE9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
AN4/C1INB/RB4
VSS
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
PGED1/AN0/RPB0/RB0
No Connect
RPD15/RD15
RPF5/PMA8/RF5
No Connect
PGED2/AN7/RPB7/CTED3/RB7
VREF+/CVREF+/PMA6/RA10
AVSS
No Connect
RPF3/RF3
RPF2/RF2
AN9/RPB9/CTED4/RB9
AN11/PMA12/RB11
VDD
RPF7/RF7
SDA1/RG3
SCL2/RA2
RPF13/RF13
TDI/CTED9/RA4
VDD
AN12/PMA11/RB12
AN14/RPB14/CTED5/PMA1/RB14
VSS
OSC2/CLKO/RC15
VSS
RPD14/RD14
RPA15/RA15
RPD9/RD9
RPF4/PMA9/RF4
No Connect
RPD11/PMCS1/RD11
SOSCI/RPC13/RC13
RPF8/RF8
RPF6/SCKI/INT0/RF6
SCL1/RG2
VDD
No Connect
No Connect
No Connect
SDA2/RA3
TDO/RA5
OSC1/CLKI/RC12
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select” for restrictions.
2:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O
Ports” for more information.
DS60001185B-page 10
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
(1,2)
TABLE 2:
PIN NAMES: PIC32MX3XXL DEVICES
(CONTINUED)
Package
Bump #
Package
Bump #
Full Pin Name
Full Pin Name
B35
B36
No Connect
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
VCAP
RPA14/RA14
No Connect
VDD
B37
RPD8/RTCC/RD8
RPD10/PMCS2/RD10
RPD0/RD0
B38
RPF0/PMD11/RF0
RPG1/PMD9/RG1
TRCLK/RA6
PMD0/RE0
VDD
B39
B40
SOSCO/RPC14/T1CK/RC14
VSS
B41
B42
AN25/RPD2/RD2
RPD12/PMD12/RD12
RPD4/PMWR/RD4
PMD14/RD6
B43
TRD2/RG14
TRD0/RG13
B44
B45
RPE3/CTPLS/PMD3/RE3
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select” for restrictions.
2:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O
Ports” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 11
PIC32MX330/350/370/430/450/470
Pin Diagrams (Continued)
(1)
= Pins are up to 5V tolerant
124-Pin VTLA
A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51
A1
A2
A3
A4
A5
A6
B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50
B1
B2
B3
B4
B5
A49
B41 A48
B40 A47
B39 A46
B38 A45
B37 A44
A7
A8
A9
B6
B7
B8
B36 A43
PIC32MX430F064L
PIC32MX450F128L
PIC32MX450F256L
PIC32MX470F512L
B35 A42
B34 A41
B33 A40
B32 A39
A10 B9
A11 B10
A12 B11
A13 B12
A14 B13
A15
B31 A38
B30 A37
B29 A36
A16 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28
A35
A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34
Note 1: See Table 3 for the full list of pin names.
DS60001185B-page 12
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
(1,2)
TABLE 3:
PIN NAMES: PIC32MX4XXL DEVICES
Package
Bump #
Package
Bump #
Full Pin Name
Full Pin Name
A1
A2
No Connect
AN24/RPD1/RD1
AN26/RPD3/RD3
PMD13/RD13
RPD5/PMRD/RD5
PMD15/RD7
No Connect
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
B1
RG15
A3
VSS
A4
AN23/PMD6/RE6
RPC1/RC1
RPC3/RC3
A5
A6
A7
AN16/C1IND/RPG6/SCK2/PMA5/RG6
AN18/C2IND/RPG8/PMA3/RG8
AN19/C2INC/RPG9/PMA2/RG9
VDD
No Connect
A8
No Connect
A9
RPF1/PMD10/RF1
RPG0/PMD8/RG0
TRD3/CTED8/RA7
VSS
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
Note 1:
RPE8/RE8
AN5/C1INA/RPB5/VBUSON/RB5
PGED3/AN3/C2INA/RPB3/RB3
VDD
PMD1/RE1
TRD1/RG12
PGEC1/AN1/RPB1/CTED12/RB1
No Connect
AN20/PMD2/RE2
AN21/PMD4/RE4
No Connect
No Connect
No Connect
VDD
No Connect
B2
AN22/RPE5/PMD5/RE5
AN27/PMD7/RE7
RPC2/RC2
PGEC2/AN6/RPB6/RB6
VREF-/CVREF-/PMA7/RA9
AVDD
B3
B4
RPC4/CTED7/RC4
AN17/C1INC/RPG7/PMA4/RG7
MCLR
B5
AN8/RPB8/CTED10/RB8
CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10
B6
B7
VSS
B8
VSS
TCK/CTED2/RA1
RPF12/RF12
AN13/PMA10/RB13
AN15/RPB15/OCFB/CTED6/PMA0/RB15
VDD
B9
TMS/CTED1/RA0
RPE9/RE9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
AN4/C1INB/RB4
VSS
PGEC3/AN2/C2INB/RPB2/CTED13/RB2
PGED1/AN0/RPB0/RB0
No Connect
RPD15/RD15
RPF5/PMA8/RF5
No Connect
PGED2/AN7/RPB7/CTED3/RB7
VREF+/CVREF+/PMA6/RA10
AVSS
No Connect
USBID/RF3
RPF2/RF2
AN9/RPB9/CTED4/RB9
AN11/PMA12/RB11
VDD
VBUS
D-
SCL2/RA2
RPF13/RF13
TDI/CTED9/RA4
VDD
AN12/PMA11/RB12
AN14/RPB14/CTED5/PMA1/RB14
VSS
OSC2/CLKO/RC15
VSS
RPD14/RD14
SDA1/RPA15/RA15
RPD9/RD9
RPF4/PMA9/RF4
No Connect
RPD11/PMCS1/RD11
SOSCI/RPC13/RC13
RPF8/RF8
VUSB3V3
VDD
D+
No Connect
No Connect
No Connect
SDA2/RA3
TDO/RA5
OSC1/CLKI/RC12
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select” for restrictions.
2:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O
Ports” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 13
PIC32MX330/350/370/430/450/470
(1,2)
TABLE 3:
PIN NAMES: PIC32MX4XXL DEVICES
(CONTINUED)
Package
Bump #
Package
Bump #
Full Pin Name
Full Pin Name
B35
B36
No Connect
SCL1/RPA14/RA14
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
VCAP
No Connect
VDD
B37
RPD8/RTCC/RD8
RPD10/SCK1/PMCS2/RD10
RPD0/INT0/RD0
B38
RPF0/PMD11/RF0
RPG1/PMD9/RG1
TRCLK/RA6
PMD0/RE0
B39
B40
SOSCO/RPC14/T1CK/RC14
VSS
B41
B42
AN25/RPD2/RD2
RPD12/PMD12/RD12
RPD4/PMWR/RD4
PMD14/RD6
VDD
B43
TRD2/RG14
TRD0/RG13
B44
B45
RPE3/CTPLS/PMD3/RE3
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 “Peripheral Pin
Select” for restrictions.
2:
Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O
Ports” for more information.
DS60001185B-page 14
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 27
3.0 CPU............................................................................................................................................................................................ 33
4.0 Memory Organization................................................................................................................................................................. 37
5.0 Flash Program Memory.............................................................................................................................................................. 93
6.0 Resets ........................................................................................................................................................................................ 97
7.0 Interrupt Controller ................................................................................................................................................................... 101
8.0 Oscillator Configuration............................................................................................................................................................ 109
9.0 Prefetch Cache......................................................................................................................................................................... 119
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 129
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 145
12.0 I/O Ports ................................................................................................................................................................................... 167
13.0 Timer1 ...................................................................................................................................................................................... 177
14.0 Timer2/3, Timer4/5................................................................................................................................................................... 181
15.0 Input Capture............................................................................................................................................................................ 185
16.0 Output Compare....................................................................................................................................................................... 189
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 191
18.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 199
19.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 205
20.0 Parallel Master Port (PMP)....................................................................................................................................................... 211
21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 219
22.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 229
23.0 Comparator .............................................................................................................................................................................. 237
24.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 241
25.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 243
26.0 Power-Saving Features ........................................................................................................................................................... 247
27.0 Special Features ...................................................................................................................................................................... 251
28.0 Instruction Set .......................................................................................................................................................................... 263
29.0 Development Support............................................................................................................................................................... 265
30.0 Electrical Characteristics.......................................................................................................................................................... 269
31.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 315
32.0 Packaging Information.............................................................................................................................................................. 319
The Microchip Web Site..................................................................................................................................................................... 339
Customer Change Notification Service.............................................................................................................................................. 339
Customer Support.............................................................................................................................................................................. 339
Reader Response.............................................................................................................................................................................. 340
Product Identification System ............................................................................................................................................................ 341
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 15
PIC32MX330/350/370/430/450/470
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note:
To access the documents listed below,
browse to the documentation section of
the
Microchip
web
site
(www.microchip.com).
• Section 1. “Introduction” (DS60001127)
• Section 2. “CPU” (DS60001113)
• Section 3. “Memory Organization” (DS60001115)
• Section 4. “Prefetch Cache” (DS60001119)
• Section 5. “Flash Program Memory” (DS60001121)
• Section 6. “Oscillator Configuration” (DS60001112)
• Section 7. “Resets” (DS60001118)
• Section 8. “Interrupt Controller” (DS60001108)
• Section 9. “Watchdog Timer and Power-up Timer” (DS60001114)
• Section 10. “Power-Saving Features” (DS60001130)
• Section 12. “I/O Ports” (DS60001120)
• Section 13. “Parallel Master Port (PMP)” (DS60001128)
• Section 14. “Timers” (DS60001105)
• Section 15. “Input Capture” (DS60001122)
• Section 16. “Output Compare” (DS60001111)
• Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)
• Section 19. “Comparator” (DS60001110)
• Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
• Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
• Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
• Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS60001116)
• Section 27. “USB On-The-Go (OTG)” (DS60001126)
• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
• Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
• Section 32. “Configuration” (DS60001124)
• Section 33. “Programming and Diagnostics” (DS60001129)
• Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167)
DS60001185B-page 16
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
This document contains device-specific information for
PIC32MX330/350/370/430/450/470 devices.
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the PIC32MX330/350/
370/430/450/470 family of devices.
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to the related section of
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 1-1:
PIC32MX330/350/370/430/450/470 BLOCK DIAGRAM
VCAP
OSC2/CLKO
OSC1/CLKI
OSC/SOSC
Oscillators
Power-up
Timer
VDD,VSS
MCLR
FRC/LPRC
Oscillators
Oscillator
Start-up Timer
Voltage
Regulator
PLL
Power-on
Reset
Precision
Band Gap
Reference
DIVIDERS
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Brown-out
Reset
Timing
Generation
Peripheral Bus Clocked by SYSCLK
CTMU
PORTA/CNA
Timer1-5
Priority
Interrupt
Controller
JTAG
BSCAN
PORTB/CNB
PORTC/CNC
PORTD/CND
PORTE/CNE
PORTF/CNF
PORTG/CNG
DMAC
PWM
OC1-5
USB
ICD
32
EJTAG
®
INT
®
MIPS32 M4K CPU Core
IC1-5
SPI1,2
I2C1,2
IS
DS
32
Bus Matrix
32
32
32
32
32
32
PMP
32
32
32
10-bit ADC
UART1-5
RTCC
Cache & Prefetch
Module
Peripheral Bridge
Data RAM
Remappable
Pins
128
128-bit wide
Program Flash Memory
Flash
Controller
Comparators
1-2
Note:
Not all features are available on all devices. Refer to TABLE 1: “PIC32MX330/350/370/430/450/470 Controller
Family Features” for the list of features by device.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 17
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
AN0
16
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
4
25
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
10
11
12
14
98
100
3
B14
A15
B13
A13
B11
A12
A20
B16
A23
B19
A24
B20
B23
A28
B24
A29
A7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
Analog input channels.
5
B6
6
A8
8
A9
62
64
1
A66
A67
B2
2
4
A4
49
50
51
3
76
77
78
5
A52
B42
A53
B3
External clock source input. Always associated with
OSC1 pin function.
CLKI
39
63
B34
I
ST/CMOS
Oscillator crystal output. Connects to crystal or reso-
nator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes. Always associated
with the OSC2 pin function.
CLKO
40
64
A42
O
—
Oscillator crystal input. ST buffer when configured in
RC mode; CMOS otherwise.
OSC1
OSC2
39
40
63
64
B34
A42
I
ST/CMOS
—
Oscillator crystal output. Connects to crystal or reso-
nator in Crystal Oscillator mode. Optionally functions
as CLKO in RC and EC modes.
I/O
32.768 kHz low-power oscillator crystal input; CMOS
otherwise.
SOSCI
47
48
73
74
A47
B40
I
ST/CMOS
—
SOSCO
O
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
DS60001185B-page 18
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
IC1
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
30
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
44
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
A29
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
IC2
IC3
I
Capture Input 1-5
IC4
I
IC5
I
OC1
OC2
OC3
OC4
OC5
OCFA
OCFB
O
O
O
O
O
I
Output Compare Output 1
Output Compare Output 2
Output Compare Output 3
Output Compare Output 4
Output Compare Output 5
Output Compare Fault A Input
Output Compare Fault B Input
External Interrupt 0
I
(1)
(2)
(1)
(2)
(1)
(2)
INT0
INT1
INT2
INT3
INT4
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA9
RA10
RA14
RA15
35 , 46
PPS
PPS
PPS
PPS
—
55 , 72
B30 , B39
I
PPS
PPS
PPS
PPS
17
PPS
PPS
PPS
PPS
B9
I
External Interrupt 1
I
External Interrupt 2
I
External Interrupt 3
I
External Interrupt 4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
38
A26
A39
B32
A40
B33
B51
A62
A21
B17
B36
A44
—
58
—
59
—
60
—
61
PORTA is a bidirectional I/O port
—
91
—
92
—
28
—
29
—
66
—
67
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 19
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
RB0
16
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
—
—
—
—
39
47
48
40
46
49
50
51
52
53
54
55
42
43
44
45
—
—
—
—
25
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
6
B14
A15
B13
A13
B11
A12
A20
B16
A23
B19
A24
B20
B23
A28
B24
A29
A5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
RB1
RB2
RB3
RB4
RB5
RB6
RB7
PORTB is a bidirectional I/O port
RB8
RB9
RB10
RB11
RB12
RB13
RB14
RB15
RC1
RC2
RC3
RC4
RC12
RC13
RC14
RC15
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
RD10
RD11
RD12
RD13
RD14
RD15
7
B4
8
A6
9
B5
PORTC is a bidirectional I/O port
63
73
74
64
72
76
77
78
81
82
83
84
68
69
70
71
79
80
47
48
B34
A47
B40
A42
B39
A52
B42
A53
B44
A55
B45
A56
B37
A45
B38
A46
B43
A54
B26
A31
PORTD is a bidirectional I/O port
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
DS60001185B-page 20
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RF8
RF12
RF13
RG0
RG1
60
61
62
63
64
1
93
94
98
99
100
3
B52
A64
A66
B56
A67
B2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTE is a bidirectional I/O port
2
4
A4
3
5
B3
—
—
58
59
18
19
87
88
52
51
49
50
A11
B10
B49
A60
A36
A35
B27
A32
(1)
34
33
31
32
PORTF is a bidirectional I/O port
(1)
(1)
(1)
35
55
B30
(1)
(1)
—
—
54
A37
53
40
B29
A27
B22
A61
B50
B31
A38
A7
—
—
39
—
90
—
89
(1)
RG2
37
36
4
57
(1)
RG3
56
RG6
10
RG7
5
11
B6
PORTG is a bidirectional I/O port
RG8
6
12
A8
RG9
8
14
A9
RG12
RG13
RG14
RG15
T1CK
T2CK
T3CK
T4CK
T5CK
—
96
A65
B55
B54
A2
—
97
—
95
—
1
48
PPS
PPS
PPS
PPS
74
B40
PPS
PPS
PPS
PPS
Timer1 External Clock Input
Timer2 External Clock Input
Timer3 External Clock Input
Timer4 External Clock Input
Timer5 External Clock Input
PPS
PPS
PPS
PPS
I
I
I
I
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 21
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
U1CTS
PPS
PPS
PPS
I
ST
UART1 Clear to Send
U1RTS
U1RX
U1TX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
—
UART1 Ready to Send
UART1 Receive
O
UART1 Transmit
U2CTS
PPS
PPS
PPS
I
ST
UART2 Clear to Send
U2RTS
U2RX
U2TX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
—
UART2 Ready to Send
UART2 Receive
O
UART2 Transmit
U3CTS
PPS
PPS
PPS
I
ST
UART3 Clear to Send
U3RTS
U3RX
U3TX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
—
UART3 Ready to Send
UART3 Receive
O
UART3 Transmit
U4CTS
PPS
PPS
PPS
I
ST
UART4 Clear to Send
U4RTS
U4RX
U4TX
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
—
UART4 Ready to Send
UART4 Receive
O
UART4 Transmit
(3)
U5CTS
PPS
PPS
PPS
I
ST
UART5 Clear to Send
(3)
U5RTS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
PPS
O
I
—
ST
—
UART5 Ready to Send
UART5 Receive
(3)
U5RX
(3)
U5TX
O
UART5 Transmit
(1)
(2)
(1)
(2)
(1)
(2)
SCK1
SDI1
35 , 50
PPS
55 , 70
B30 , B38
I/O
O
ST
—
Synchronous Serial Clock Input/Output for SPI1
SPI1 Data In
PPS
PPS
PPS
PPS
SDO1
PPS
I/O
ST
SPI1 Data Out
SS1
PPS
4
PPS
10
PPS
A7
O
I/O
O
—
ST
—
SPI1 Slave Synchronization for Frame Pulse I/O
Synchronous Serial Clock Input/Output for SPI2
SPI2 Data In
SCK2
SDI2
SDO2
PPS
PPS
PPS
PPS
PPS
PPS
I/O
ST
SPI2 Data Out
SS2
PPS
PPS
57, 66
56, 67
58
PPS
O
I/O
I/O
I/O
I/O
I
—
ST
ST
ST
ST
ST
ST
—
SPI2 Slave Synchronization for Frame Pulse I/O
Synchronous Serial Clock Input/Output for I2C1
Synchronous Serial Data Input/Output for I2C1
Synchronous Serial Clock Input/Output for I2C2
Synchronous Serial Data Input/Output for I2C2
JTAG Test Mode Select Pin
(1)
(2)
(2)
(1)
(2)
(2)
SCL1
SDA1
SCL2
SDA2
TMS
TCK
37 , 44
B31 , B36
(1)
(1)
36 , 43
A38 , A44
32
31
23
27
28
24
42
A39
B32
B9
59
17
38
A26
A40
B33
B37
I
JTAG Test Clock Input Pin
TDI
60
I
JTAG Test Clock Input Pin
TDO
RTCC
61
O
I
—
JTAG Test Clock Output Pin
68
ST
Real-Time Clock Alarm Output
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
DS60001185B-page 22
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
CVREF-
CVREF+
CVREFOUT
C1INA
15
16
23
11
12
5
28
29
A21
B17
A24
A12
B11
B6
I
I
Analog Comparator Voltage Reference (Low)
Analog Comparator Voltage Reference (High)
Analog Comparator Voltage Reference (Output)
Analog
34
I
20
I
C1INB
21
I
Analog
Comparator 1 Inputs
Analog
C1INC
C1IND
C2INA
11
I
4
10
A7
I
Analog
Analog
13
14
8
22
A13
B13
A9
I
C2INB
23
I
Analog
Comparator 2 Inputs
Analog
C2INC
C2IND
C1OUT
C2OUT
PMALL
PMALH
14
I
6
12
A8
I
Analog
PPS
PPS
30
29
PPS
PPS
44
PPS
PPS
A29
B24
O
O
O
O
—
—
Comparator 1 Output
Comparator 2 Output
TTL/ST Parallel Master Port Address Latch Enable Low Byte
TTL/ST Parallel Master Port Address Latch Enable High Byte
43
Parallel Master Port Address bit 0 Input (Buffered
TTL/ST
PMA0
PMA1
30
29
44
43
A29
B24
O
O
Slave modes) and Output (Master modes)
Parallel Master Port Address bit 0 Input (Buffered
TTL/ST
Slave modes) and Output (Master modes)
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMCS1
PMCS2
PMD0
PMD1
PMD2
8
14
12
11
10
29
28
50
49
42
41
35
34
71
70
71
72
93
94
98
A9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
6
A8
5
B6
4
A7
16
22
32
31
28
27
24
23
45
44
45
44
60
61
62
B17
A21
A32
B27
A28
B23
B20
A24
A46
B38
A46
B38
B52
A64
A66
Parallel Master Port data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes)
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 23
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMRD
PMWR
63
64
1
99
100
3
B56
A67
B2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
—
2
4
A4
3
5
B3
—
—
—
—
—
—
—
—
53
52
34
90
89
88
87
79
80
83
84
82
81
54
A61
B50
A60
B49
B43
A54
B45
A56
A55
B44
A37
Parallel Master Port Data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes)
Parallel Master Port Read Strobe
Parallel Master Port Write Strobe
—
(2)
VBUS
Analog USB Bus Power Monitor
USB internal transceiver supply. If the USB module is
not used, this pin must be connected to VDD.
(2)
VUSB3V3
35
55
B30
P
—
—
(2)
VBUSON
11
37
36
33
20
57
56
51
A12
B31
A38
A35
O
I/O
I/O
I
USB Host and OTG bus power control Output
(2)
D+
Analog USB D+
Analog USB D-
(2)
D-
(2)
USBID
ST
USB OTG ID Detect
Data I/O pin for Programming/Debugging
Communication Channel 1
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
16
15
18
17
13
14
25
24
27
26
22
23
B14
A15
B16
A20
A13
B13
I/O
ST
Clock Input pin for Programming/Debugging
Communication Channel 1
I
I/O
I
ST
ST
ST
ST
ST
Data I/O Pin for Programming/Debugging
Communication Channel 2
Clock Input Pin for Programming/Debugging
Communication Channel 2
Data I/O Pin for Programming/Debugging
Communication Channel 3
I/O
I
Clock Input Pin for Programming/Debugging
Communication Channel 3
TCK
27
23
28
24
59
60
61
62
63
38
17
60
61
91
97
96
95
92
A26
B9
I
ST
ST
ST
—
—
—
—
—
—
JTAG Test Clock Input Pin
JTAG Test Mode Select Pin
JTAG Test Data Input Pin
JTAG Test Data Output Pin
Trace clock
TMS
I
TDI
A40
B33
B51
B55
A65
B54
A62
I
TDO
O
O
O
O
O
O
TRCLK
TRD0
TRD1
TRD2
TRD3
Trace Data bit 0
Trace Data bit 1
Trace Data bit 2
Trace Data bit 3
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
DS60001185B-page 24
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
64-pin
QFN/
TQFP
Pin Name
Description
100-pin
TQFP
124-pin
VTLA
CTED1
CTED2
CTED3
CTED4
CTED5
CTED6
CTED7
CTED8
CTED9
CTED10
CTED11
CTED12
CTED13
—
—
18
22
29
30
—
—
—
21
23
15
14
17
38
27
33
43
44
9
B9
I
I
I
I
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
CTMU External Edge Input 1
A26
B16
B19
B24
A29
B5
CTMU External Edge Input 2
CTMU External Edge Input 3
CTMU External Edge Input 4
CTMU External Edge Input 5
CTMU External Edge Input 6
CTMU External Edge Input 7
CTMU External Edge Input 8
CTMU External Edge Input 9
CTMU External Edge Input 10
CTMU External Edge Input 11
CTMU External Edge Input 12
CTMU External Edge Input 13
92
60
32
34
24
23
A62
A40
A23
A24
A15
B13
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
MCLR
7
13
B7
I/P
ST
Positive supply for analog modules. This pin must be
connected at all times.
AVDD
AVSS
19
20
30
31
A22
B18
P
P
P
P
Ground reference for analog modules
Positive supply for peripheral logic and I/O pins
Capacitor for Internal Voltage Regulator
Ground reference for logic and I/O pins
B1, A10, A14,
B21, A30,
A41, A48,
A59, B53
10, 26, 38, 2, 16, 37,
VDD
VCAP
VSS
P
P
P
—
—
—
57
46, 62, 86
56
85
B48
A3, B8, B12,
A25, B25,
A43, B41,
A63
15, 36, 45,
65, 75
9, 25, 41
VREF+
VREF-
16
15
29
28
B17
A21
I
I
Analog Analog Voltage Reference (High) Input
Analog Analog Voltage Reference (Low) Input
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: This pin is available on PIC32MX3XX devices only.
2: This pin is available on PIC32MX4XX devices only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 25
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 26
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 32-BIT MCUS
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to the related section of
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance (low-
ESR) capacitor and have resonance frequency in
the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
2.1
Basic Connection Requirements
Getting started with the PIC32MX330/350/370/430/
450/470 family of 32-bit Microcontrollers (MCUs)
requires attention to a minimal set of device pin con-
nections before proceeding with development. The fol-
lowing is a list of pin names, which must always be
connected:
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in par-
allel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implement-
ing a decade pair of capacitances as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• All VDD and VSS pins (see 2.2 “Decoupling Capac-
itors”)
• All AVDD and AVSS pins, even if the ADC module is
not used (see 2.2 “Decoupling Capacitors”)
• VCAP pin (see 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the decou-
pling capacitors are first in the power chain. Equally
important is to keep the trace length between the
capacitor and the power pins to a minimum thereby
reducing PCB track inductance.
• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins, used for In-Circuit Serial Pro-
gramming (ICSP™) and debugging purposes (see
2.5 “ICSP Pins”)
• OSC1 and OSC2 pins, when external oscillator
source is used (see 2.8 “External Oscillator Pins”)
The following pin may be required, as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 27
PIC32MX330/350/370/430/450/470
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
VDD
• Device Reset
• Device programming and debugging
R
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
R1
MCLR
(1)
C
VUSB3V3
PIC32
VDD
VSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
(2)
Connect
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(2)
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
Note 1: If the USB module is not used, this pin must be
connected to VDD.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
VDD
R(1)
Where:
R1(2)
FCNV
MCLR
f = -------------
(i.e., ADC conversion rate/2)
2
PIC32
JP
C(3)
1
f = -----------------------
2 LC
2
1
---------------------
L =
2f C
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2.2.1
BULK CAPACITORS
2: R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
3: The capacitor can be sized to prevent uninten-
tional Resets from brief glitches or to extend
the device Reset period during POR.
2.3
Capacitor on Internal Voltage
Regulator (VCAP)
2.3.1
INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu-
lator output. The VCAP pin must not be connected to
VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to Section 30.0 “Electrical
Characteristics” for additional information on CEFC
specifications.
DS60001185B-page 28
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
2.5
ICSP Pins
2.7
Trace
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
The trace pins can be connected to a hardware
trace-enabled programmer to provide a compressed
real-time instruction trace. When used for trace, the
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
be dedicated for this use. The trace hardware
requires a 22 Ohm series resistor between the trace
pins and the trace connector.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
2.8
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator cir-
cuit close to the respective oscillator pins, not exceed-
ing one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) DS50001765
• “MPLAB® ICD 3 Design Advisory” DS50001764
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS50001616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS50001749
2.6
JTAG
Oscillator
Secondary
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Guard Trace
Guard Ring
Main Oscillator
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete compo-
nents are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC character-
istics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2.9
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 29
PIC32MX330/350/370/430/450/470
2.10 Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-4 and Figure 2-5.
FIGURE 2-4:
CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION
PIC32MX430F064L
Current Source
CTMU
To AN6
To AN7
To AN8
To AN9
To AN11
To AN0
To AN1
AN0
AN1
R1
C1
R1
C2
R1
R1
C3
R1
C4
C5
ADC
Read the Touch Sensors
R2
C1
R2
C2
R2
C3
R2
C4
R2
C5
Microchip
mTouch™
Library
AN9
To AN5
Process Samples
AN11
R3
C1
R3
C2
R3
C3
R3
C4
R3
C5
User
Application
Display Data
LCD Controller
Display
PMD<7:0>
PMWR
Microchip
Graphics
Library
Parallel
Master
Port
Frame
Buffer
LCD
Panel
Controller
FIGURE 2-5:
AUDIO PLAYBACK APPLICATION
PMD<7:0>
USB
Host
PMP
USB
Display
PMWR
3
PIC32MX450F256L
Stereo Headphones
Speaker
2
I S
Audio
Codec
REFCLKO
3
SPI
3
MMC SD
SDI
DS60001185B-page 30
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 2-6:
LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH
PROJECTED CAPACITIVE TOUCH
PIC32MX430F064L
ANx
CTMU
ADC
Microchip mTouch™
GFX Libraries
LCD Display
Projected Capacitive
Touch Overlay
DMA
PMP
SRAM
External Frame Buffer
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 31
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 32
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e® Code Compression:
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVEand RESTOREmacro instructions for
setting up and tearing down stack frames
within subroutines
3.0
CPU
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web site
(www.microchip.com/PIC32). Resources
for the MIPS32® M4K® Processor Core
are available at http://www.mips.com.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
Mechanism:
• Simple Dual Bus Interface:
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous Multiply/Divide Unit (MDU):
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
The the MIPS32® M4K® Processor Core is the heart of
the PIC32MX330/350/370/430/450/470 device proces-
sor. The CPU fetches instructions, decodes each
instruction, fetches source operands, executes each
instruction and writes the results of instruction
execution to the proper destinations.
3.1
Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32® Enhanced Architecture (Release 2):
• Power Control:
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAITinstruction)
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace:
- Support for single stepping
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAITinstruction
- Virtual instruction and data address/value
- Breakpoints
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
®
®
FIGURE 3-1:
MIPS32 M4K PROCESSOR CORE BLOCK DIAGRAM
CPU
EJTAG
MDU
TAP
Off-chip Debug Interface
Execution Core
(RF/ALU/Shift)
FMT
Dual Bus Interface
Bus Interface
Bus Matrix
System
Co-processor
Power
Management
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 33
PIC32MX330/350/370/430/450/470
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
3.2
Architecture Overview
The MIPS32® M4K® processor core includes a Multi-
ply/Divide Unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline oper-
ates in parallel with the Integer Unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.
The MIPS32® M4K® processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt) oper-
and to determine how many times the operation must
pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
• MIPS16e® Support
• Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The MIPS32® M4K® processor core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit General Purpose Registers (GPRs)
used for integer operations and address calculation.
One additional register file shadow set (containing
thirty-two registers) is added to minimize context
switching overhead during interrupt/exception process-
ing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation
latency in the pipeline.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a sub-
sequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZand CLOinstructions
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner
®
®
TABLE 3-1:
MIPS32 M4K PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/
DIVIDE UNIT LATENCIES AND REPEAT RATES
Op code
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
32 bits
16 bits
32 bits
8 bits
1
2
1
2
MUL
2
1
3
2
DIV/DIVU
12
19
26
33
11
18
25
32
16 bits
24 bits
32 bits
DS60001185B-page 34
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e®, is also available by accessing the CP0
registers, listed in Table 3-2.
In addition to the HI/LO targeted operations, the
MIPS32® architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADDinstruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUBinstruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
TABLE 3-2:
COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0-6
7
Reserved
Reserved in the PIC32MX330/350/370/430/450/470 family core.
HWREna
BadVAddr(1)
Count(1)
Reserved
Compare(1)
Status(1)
IntCtl(1)
SRSCtl(1)
SRSMap(1)
Cause(1)
EPC(1)
Enables access via the RDHWRinstruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
8
9
10
11
Reserved in the PIC32MX330/350/370/430/450/470 family core.
Timer interrupt control.
12
12
12
12
13
14
15
15
16
16
16
16
17-22
23
24
25-29
30
31
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
PRId
Processor identification and revision.
Exception vector base register.
EBASE
Config
Configuration register.
Config1
Configuration register 1.
Config2
Configuration register 2.
Config3
Configuration register 3.
Reserved
Debug(2)
DEPC(2)
Reserved
ErrorEPC(1)
DESAVE(2)
Reserved in the PIC32MX330/350/370/430/450/470 family core.
Debug control and exception status.
Program counter at last debug exception.
Reserved in the PIC32MX330/350/370/430/450/470 family core.
Program counter at last error.
Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 35
PIC32MX330/350/370/430/450/470
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
®
®
TABLE 3-3:
Exception
MIPS32 M4K PROCESSOR CORE EXCEPTION TYPES
Description
Reset
DSS
Assertion MCLR or a Power-on Reset (POR).
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
DIB
Assertion of unmasked hardware or software interrupt signal.
EJTAG debug hardware instruction break matched.
Fetch address alignment error. Fetch reference to protected address.
Instruction fetch bus error.
AdEL
IBE
DBp
EJTAG breakpoint (execution of SDBBPinstruction).
Execution of SYSCALLinstruction.
Sys
Bp
Execution of BREAKinstruction.
RI
Execution of a reserved instruction.
CpU
CEU
Ov
Execution of a coprocessor instruction for a coprocessor that is not enabled.
Execution of a CorExtend instruction when CorExtendis not enabled.
Execution of an arithmetic instruction that overflowed.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
Load address alignment error. Load reference to protected address.
Store address alignment error. Store to protected address.
Load or store bus error.
Tr
DDBL/DDBS
AdEL
AdES
DBE
DDBL
EJTAG data hardware breakpoint matched in load data compare.
3.3
Power Management
3.4
EJTAG Debug Support
The MIPS® M4K® processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
The MIPS® M4K® processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the soft-
ware debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the M4K® core provides a Debug mode that is entered
after a debug exception (derived from a hardware
breakpoint, single-step exception, etc.) is taken and
continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 26.0
“Power-Saving Features”.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX330/350/370/430/450/470 family core is in
the clock tree and clocking registers. The PIC32MX
family uses extensive use of local gated-clocks to
reduce this dynamic power consumption.
DS60001185B-page 36
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
4.1
Memory Layout
4.0
MEMORY ORGANIZATION
PIC32MX330/350/370/430/450/470 microcontrollers
implement two address schemes: virtual and physical.
All hardware resources, such as program memory,
data memory and peripherals, are located at their
respective physical addresses. Virtual addresses are
exclusively used by the CPU to fetch and execute
instructions as well as access peripherals. Physical
addresses are used by bus master peripherals, such as
DMA and the Flash controller, that access memory
independently of the CPU.
Note:
This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/470
family of devices. It is not intended to be a
comprehensive reference source.For
detailed information, refer to Section 3.
“Memory Organization” (DS60001115)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 microcontrollers
provide 4 GB of unified virtual memory address space.
All memory regions, including program, data memory,
SFRs and Configuration registers, reside in this
address space at their respective unique addresses.
The program and data memories can be optionally par-
titioned into user and kernel memories. In addition, the
data memory can be made executable, allowing
PIC32MX330/350/370/430/450/470 devices to execute
from data memory.
The memory maps for the PIC32MX330/350/370/430/
450/470 devices are illustrated in Figure 4-1 through
Figure 4-3.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 37
PIC32MX330/350/370/430/450/470
FIGURE 4-1:
MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY
Virtual
Physical
Memory Map(1)
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
Program Flash(2)
Reserved
RAM(2)
0xBD010000
0xBD00FFFF
0xBD000000
0xA0004000
0xA0003FFF
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC03000
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D010000
0x9D00FFFF
0x1F800000
Program Flash(2)
Reserved
Reserved
0x9D000000
0x1D010000
0x1D00FFFF
0x80004000
0x80003FFF
Program Flash(2)
0x1D000000
RAM(2)
Reserved
RAM(2)
0x80000000
0x00000000
0x00004000
0x00003FFF
0x00000000
Reserved
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-
tion code provided by end-user development tools (refer to the specific development tool
documentation for information).
DS60001185B-page 38
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 4-2:
MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY
Virtual
Physical
Memory Map(1)
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
Program Flash(2)
Reserved
RAM(2)
0xBD020000
0xBD01FFFF
0xBD000000
0xA0008000
0xA0007FFF
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC03000
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D020000
0x9D01FFFF
0x1F800000
Program Flash(2)
Reserved
Reserved
0x9D000000
0x1D020000
0x1D01FFFF
0x80008000
0x80007FFF
Program Flash(2)
0x1D000000
RAM(2)
Reserved
RAM(2)
0x80000000
0x00000000
0x00008000
0x00007FFF
0x00000000
Reserved
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-
tion code provided by end-user development tools (refer to the specific development tool
documentation for information).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 39
PIC32MX330/350/370/430/450/470
FIGURE 4-3:
MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY
Virtual
Physical
Memory Map(1)
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
Program Flash(2)
Reserved
RAM(2)
0xBD040000
0xBD03FFFF
0xBD000000
0xA0010000
0xA000FFFF
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC03000
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D040000
0x9D03FFFF
0x1F800000
Program Flash(2)
Reserved
Reserved
0x9D000000
0x1D040000
0x1D03FFFF
0x80010000
0x8000FFFF
Program Flash(2)
0x1D000000
RAM(2)
Reserved
RAM(2)
0x80000000
0x00000000
0x00010000
0x0000FFFF
0x00000000
Reserved
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-
tion code provided by end-user development tools (refer to the specific development tool
documentation for information).
DS60001185B-page 40
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 4-4:
MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY
Virtual
Physical
Memory Map(1)
Memory Map(1)
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
Program Flash(2)
Reserved
RAM(2)
0xBD080000
0xBD07FFFF
0xBD000000
0xA0020000
0xA001FFFF
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC03000
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FF0
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D080000
0x9D07FFFF
0x1F800000
Program Flash(2)
Reserved
Reserved
0x9D000000
0x1D080000
0x1D07FFFF
0x80020000
0x8001FFFF
Program Flash(2)
0x1D000000
RAM(2)
Reserved
RAM(2)
0x80000000
0x00000000
0x00020000
0x0001FFFF
0x00000000
Reserved
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa-
tion code provided by end-user development tools (refer to the specific development tool
documentation for information).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 41
4.2
Special Function Register Maps
Table 4-1 through Table 4-39 contain the peripheral address maps for the PIC32MX330/350/370/430/450/470 devices.
TABLE 4-1:
BUS MATRIX REGISTER MAP
Bits
31/15 30/14 29/13
28/12 27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
BMXCHEDMA
—
—
—
—
—
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 041F
(1)
2000 BMXCON
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMXWSDRM
—
—
—
—
—
—
—
BMXARB<2:0>
—
0047
0000
0000
0000
0000
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
—
—
—
—
—
—
(1)
(1)
2010 BMXDKPBA
BMXDKPBA<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2020 BMXDUDBA
BMXDUDBA<15:0>
31:16
15:0
—
—
(1)
2030 BMXDUPBA
2040 BMXDRMSZ
BMXDUPBA<15:0>
31:16
15:0
BMXDRMSZ<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
BMXPUPBA<19:16>
(1)
2050 BMXPUPBA
2060 BMXPFMSZ
2070 BMXBOOTSZ
BMXPUPBA<15:0>
31:16
15:0
BMXPFMSZ<31:0>
BMXBOOTSZ<31:0>
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information.
TABLE 4-2:
INTERRUPT REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
TPC<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
—
—
SS0
0000
1000 INTCON
1010 INTSTAT
INT3EP INT2EP INT1EP INT0EP 0000
31:16
15:0
—
—
—
—
0000
0000
0000
0000
—
SRIPL<2:0>
VEC<5:0>
31:16
15:0
1020
1030
1040
1050
1060
1070
1080
1090
10A0
10B0
10C0
10D0
10E0
IPTMR
IFS0
IFS1
IFS2
IEC0
IEC1
IEC2
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPTMR<31:0>
31:16 FCEIF
15:0 IC3EIF
31:16 U3RXIF
RTCCIF FSCMIF
T3IF INT2IF
AD1IF
OC2IF
OC5IF
IC2IF
IC5IF
IC2EIF
U2TXIF
I2C1SIF
—
IC5EIF
T2IF
T5IF
INT1IF
U2EIF
U1TXIF
—
INT4IF
OC1IF
OC4IF
IC1IF
IC4IF
IC4EIF
T1IF
T4IF
INT3IF OC3IF
CS1IF CS0IF
IC3IF 0000
CTIF 0000
IC1EIF
INT0IF
PMPIF
U3EIF I2C2MIF I2C2SIF
I2C2BIF
U2RXIF
I2C1BIF
—
SPI2TXIF SPI2RXIF SPI2EIF
PMPEIF
CNGIF CNFIF CNEIF 0000
(2)
15:0
31:16
15:0
CNDIF
—
CNCIF
—
CNBIF
—
CNAIF
—
I2C1MIF
—
U1RXIF
—
U1EIF
—
SPI1TXIF SPI1RXIF SPI1EIF USBIF
CMP2IF CMP1IF 0000
0000
U4TXIF U4RXIF U4EIF U3TXIF 0000
—
U5RXIF
IC4IE
—
—
—
—
—
(1)
(1)
(1)
—
—
—
—
DMA3IF
DMA2IF
IC5IE
DMA1IF
IC5EIE
T2IE
DMA0IF
T5IE
CTMUIF U5TXIF
U5EIF
31:16 FCEIE RTCCIE FSCMIE
AD1IE
OC2IE
OC5IE
INT4IE
OC1IE
OC4IE
IC1IE
IC4EIE
T1IE
T4IE
INT3IE OC3IE
CS1IE CS0IE
IC3IE 0000
CTIE 0000
15:0 IC3EIE
31:16 U3RXIE
T3IE
INT2IE
IC2IE
IC2EIE
U2TXIE
I2C1SIE
—
INT1IE
U2EIE
U1TXIE
—
IC1EIE
INT0IE
PMPIE
U3EIE I2C2MIE I2C2SIE
I2C2BIE
U2RXIE
I2C1BIE
—
SPI2TXIE SPI2RXIE SPI2EIE
PMPEIE
CNGIE CNFIE CNEIE 0000
(2)
15:0
31:16
15:0
CNDIE
—
CNCIE
—
CNBIE
—
CNAIE
—
I2C1MIE
—
U1RXIE
—
U1EIE
—
SPI1TXIE SPI1RXIE SPI1EIE USBIE
CMP2IE CMP1IE 0000
0000
U4TXIE U4RXIE U4EIE U3TXIE 0000
—
U5RXIE
—
—
—
—
—
—
(1)
(1)
(1)
—
—
—
—
DMA3IE
DMA2IE
DMA1IE
DMA0IE CTMUIE U5TXIE
U5EIE
31:16
15:0
—
—
—
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT4IP<2:0>
IC4IP<2:0>
AD1IP<2:0>
IC5IP<2:0>
INT0IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
OC4IP<2:0>
T4IP<2:0>
OC5IP<2:0>
T5IP<2:0>
CS1IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
OC4IS<1:0>
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
INT4IS<1:0>
IC4IS<1:0>
AD1IS<1:0>
IC5IS<1:0>
—
31:16
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This bit is available on PIC32MX3XXFXXXL devices only.
TABLE 4-2:
INTERRUPT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CMP1IP<2:0>
RTCCIP<2:0>
U1IP<2:0>
CMP1IS<1:0>
RTCCIS<1:0>
U1IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
10F0
1100
1110
1120
1130
1140
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
FSCMIP<2:0>
FSCMIS<1:0>
(2)
(2)
31:16
15:0
SPI1IP<2:0>
SPI1IS<1:0>
USBIP<2:0>
SPI2IP<2:0>
CNIP<2:0>
U4IP<2:0>
USBIS<1:0>
SPI2IS<1:0>
CNIS<1:0>
CMP2IP<2:0>
PMPIP<2:0>
I2C1IP<2:0>
U3IP<2:0>
U2IP<2:0>
DMA0IP<2:0>
U5IP<2:0>
—
CMP2IS<1:0>
PMPIS<1:0>
I2C1IS<1:0>
U3IS<1:0>
31:16
15:0
31:16
15:0
U4IS<1:0>
I2C2IP<2:0>
DMA1IP<2:0>
CTMUIP<2:0>
—
I2C2IS<1:0>
DMA1IS<1:0>
CTMUIS<1:0>
U2IS<1:0>
31:16
15:0
DMA0IS<1:0>
U5IS<1:0>
31:16
15:0
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
DMA2IP<2:0>
DMA2IS<1:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This bit is available on PIC32MX3XXFXXXL devices only.
TABLE 4-3:
TIMER1 THROUGH TIMER5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
ON
—
—
—
—
—
SIDL
—
—
TWDIS
—
—
TWIP
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSYNC
—
—
TCS
—
—
—
—
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0600 T1CON
0610 TMR1
0620 PR1
0800 T2CON
0810 TMR2
0820 PR2
0A00 T3CON
0A10 TMR3
0A20 PR3
0C00 T4CON
0C10 TMR4
0C20 PR4
0E00 T5CON
0E10 TMR5
0E20 PR5
15:0
31:16
15:0
TCKPS<1:0>
—
—
TMR1<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR1<15:0>
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
T32
—
—
—
—
—
TCS
—
—
—
—
31:16
15:0
TMR2<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR2<15:0>
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
TCS
—
—
—
—
31:16
15:0
TMR3<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR3<15:0>
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
T32
—
—
—
—
—
TCS
—
—
—
—
31:16
15:0
TMR4<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR4<15:0>
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
TCS
—
—
—
—
31:16
15:0
TMR5<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR5<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-4:
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1)
2000 IC1CON
15:0
31:16
15:0
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
2010 IC1BUF
IC1BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
2200 IC2CON
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2210 IC2BUF
IC2BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
2400 IC3CON
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2410 IC3BUF
IC3BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
2600 IC4CON
ON
SIDL
FEDGE
C32
ICTMR
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2610 IC4BUF
IC4BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
2800 IC5CON
ON
SIDL
FEDGE
C32
ICTMR
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2810 IC5BUF
IC5BUF<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more informa-
tion.
TABLE 4-5:
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
3000 OC1CON
3010 OC1R
3020 OC1RS
3200 OC2CON
3210 OC2R
3220 OC2RS
3400 OC3CON
3410 OC3R
3420 OC3RS
3600 OC4CON
3610 OC4R
3620 OC4RS
3800 OC5CON
3810 OC5R
3820 OC5RS
ON
SIDL
OC32
OCFLT OCTSEL
OCM<2:0>
31:16
15:0
OC1R<31:0>
OC1RS<31:0>
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
SIDL
OC32
OCFLT OCTSEL
OCM<2:0>
31:16
15:0
OC2R<31:0>
31:16
15:0
OC2RS<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
SIDL
OC32
OCFLT OCTSEL
OCM<2:0>
31:16
15:0
OC3R<31:0>
31:16
15:0
OC3RS<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
SIDL
OC32
OCFLT OCTSEL
OCM<2:0>
31:16
15:0
OC4R<31:0>
31:16
15:0
OC4RS<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
SIDL
OC32
OCFLT OCTSEL
OCM<2:0>
31:16
15:0
OC5R<31:0>
31:16
15:0
OC5RS<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-6:
I2C1 AND I2C2 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
A10M
—
—
DISSLW
—
—
SMEN
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
0000
BFFF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
BFFF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
5000 I2C1CON
5010 I2C1STAT
5020 I2C1ADD
5030 I2C1MSK
5040 I2C1BRG
5050 I2C1TRN
5060 I2C1RCV
5100 I2C2CON
5110 I2C2STAT
5120 I2C2ADD
5130 I2C2MSK
5140 I2C2BRG
5150 I2C2TRN
5160 I2C2RCV
SCLREL STRICT
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 ACKSTAT TRSTAT
—
BCL
—
GCSTAT ADD10
IWCOL
—
I2COV
—
D_A
—
P
S
R_W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Mask Register
31:16
15:0
—
—
—
—
—
—
Baud Rate Generator Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
Receive Register
31:16
15:0
—
—
—
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
SIDL
—
SCLREL STRICT
A10M
—
DISSLW
—
SMEN
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0 ACKSTAT TRSTAT
—
BCL
—
GCSTAT ADD10
IWCOL
—
I2COV
—
D_A
—
P
S
R_W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address Mask Register
31:16
15:0
—
—
—
—
—
Baud Rate Generator Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmit Register
31:16
15:0
—
—
—
—
Receive Register
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and
INV Registers” for more information.
TABLE 4-7:
UART1 THROUGH UART5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
IREN
—
—
RTSMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
(1)
6000 U1MODE
UEN<1:0>
WAKE
LPBACK ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
(1)
6010 U1STA
UTXISEL<1:0>
UTXINV URXEN UTXBRK UTXEN
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA FFFF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
6020 U1TXREG
6030 U1RXREG
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
(1)
6040 U1BRG
Baud Rate Generator Prescaler
—
ON
—
—
—
—
—
SIDL
—
—
IREN
—
—
RTSMD
—
—
—
—
—
—
—
—
—
31:16
15:0
(1)
6200 U2MODE
UEN<1:0>
WAKE
LPBACK ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
(1)
6210 U2STA
UTXISEL<1:0>
UTXINV URXEN UTXBRK UTXEN
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA FFFF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
6220 U2TXREG
6230 U2RXREG
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
(1)
6240 U2BRG
Baud Rate Generator Prescaler
—
ON
—
—
—
—
—
SIDL
—
—
IREN
—
—
RTSMD
—
—
—
—
—
—
—
—
—
31:16
15:0
(1)
6400 U3MODE
UEN<1:0>
WAKE
LPBACK ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
(1)
6410 U3STA
UTXISEL<1:0>
UTXINV URXEN UTXBRK UTXEN
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA FFFF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
6420 U3TXREG
6430 U3RXREG
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
(1)
6440 U3BRG
Baud Rate Generator Prescaler
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more informa-
tion.
TABLE 4-7:
UART1 THROUGH UART5 REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
ON
—
—
—
—
—
SIDL
—
—
IREN
—
—
RTSMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
15:0
(1)
6600 U4MODE
UEN<1:0>
WAKE
LPBACK ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
(1)
6610 U4STA
UTXISEL<1:0>
UTXINV URXEN UTXBRK UTXEN
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA FFFF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
6620 U4TXREG
6630 U4RXREG
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
(1)
6640 U4BRG
Baud Rate Generator Prescaler
—
ON
—
—
—
—
—
SIDL
—
—
IREN
—
—
RTSMD
—
—
—
—
—
—
—
—
—
31:16
15:0
(1)
6800 U5MODE
UEN<1:0>
WAKE
LPBACK ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
(1)
6810 U5STA
UTXISEL<1:0>
UTXINV URXEN UTXBRK UTXEN
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA FFFF
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
6820 U5TXREG
6830 U5RXREG
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
(1)
6840 U5BRG
Baud Rate Generator Prescaler
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more informa-
tion.
TABLE 4-8:
SPI2 AND SPI2 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW
FRMCNT<2:0>
MCLKSEL
SSEN
—
—
CKP
—
—
MSTEN
—
—
—
—
SPIFE
ENHBUF 0000
5800 SPI1CON
15:0
31:16
15:0
ON
—
—
—
—
SIDL
—
DISSDO MODE32 MODE16
RXBUFELM<4:0>
SMP
CKE
DISSDI
STXISEL<1:0>
TXBUFELM<4:0>
SRXISEL<1:0>
0000
0000
SPI1STAT
SPI1BUF
SPI1BRG
5810
5820
5830
—
—
FRMERR SPIBUSY
—
—
SPITUR
SRMT
SPIROV SPIRBE
—
SPITBE
—
—
SPITBF SPIRBF 19EB
31:16
15:0
0000
0000
DATA<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
—
—
0000
0000
0000
31:16
—
—
—
—
—
—
—
SPI1CON2
5840
SPI
SGNEXT
FRM
ERREN
SPI
ROVEN
SPI
AUD
MONO
15:0
—
—
IGNROV IGNTUR AUDEN
—
AUDMOD<1:0>
SPIFE
SRXISEL<1:0>
0000
TUREN
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW
FRMCNT<2:0>
MCLKSEL
SSEN
—
—
CKP
—
—
MSTEN
—
—
—
ENHBUF 0000
SPI2CON
SPI2STAT
SPI2BUF
SPI2BRG
5A00
5A10
5A20
5A30
15:0
31:16
15:0
ON
—
—
—
—
SIDL
—
DISSDO MODE32 MODE16
RXBUFELM<4:0>
SMP
CKE
DISSDI
STXISEL<1:0>
TXBUFELM<4:0>
0000
0000
—
—
FRMERR SPIBUSY
—
—
SPITUR
SRMT
SPIROV SPIRBE
—
SPITBE
—
SPITBF SPIRBF 19EB
31:16
15:0
0000
0000
DATA<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
—
—
—
—
—
—
SPI2CON2
5A40
SPI
SGNEXT
FRM
ERREN
SPI
ROVEN
SPI
AUD
MONO
15:0
—
—
IGNROV IGNTUR AUDEN
—
AUDMOD<1:0>
0000
TUREN
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV
Registers” for more information.
TABLE 4-9:
ADC REGISTER MAP
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLRASAM
—
—
—
—
—
ASAM
—
—
SAMP
—
—
0000
(1)
9000 AD1CON1
9010 AD1CON2
9020 AD1CON3
—
FORM<2:0>
SSRC<2:0>
DONE 0000
31:16
15:0
—
—
—
CSCNA
—
—
—
—
—
—
—
—
BUFS
—
—
—
—
—
ALTS
—
0000
0000
0000
0000
0000
0000
(1)
(1)
VCFG<2:0>
OFFCAL
—
SMPI<3:0>
BUFM
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
ADRC
SAMC<4:0>
CH0SB<4:0>
—
ADCS<7:0>
31:16 CH0NB
CH0NA
—
—
—
—
—
CH0SA<4:0>
—
(1)
9040 AD1CHS
9050 AD1CSSL
15:0
—
—
—
—
—
—
—
—
—
—
31:16
CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 CSSL25 CSSL24 CSSL23 CSSL22 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 0000
(1)
15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0 0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
9070 ADC1BUF0
9080 ADC1BUF1
9090 ADC1BUF2
90A0 ADC1BUF3
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
90F0 ADC1BUF8
9100 ADC1BUF9
9110 ADC1BUFA
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 1 (ADC1BUF1<31:0>)
ADC Result Word 2 (ADC1BUF2<31:0>)
ADC Result Word 3 (ADC1BUF3<31:0>)
ADC Result Word 4 (ADC1BUF4<31:0>)
ADC Result Word 5 (ADC1BUF5<31:0>)
ADC Result Word 6 (ADC1BUF6<31:0>)
ADC Result Word 7 (ADC1BUF7<31:0>)
ADC Result Word 8 (ADC1BUF8<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>)
ADC Result Word A (ADC1BUFA<31:0>)
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
details.
TABLE 4-9:
ADC REGISTER MAP (CONTINUED)
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
9120 ADC1BUFB
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
ADC Result Word B (ADC1BUFB<31:0>)
ADC Result Word C (ADC1BUFC<31:0>)
ADC Result Word D (ADC1BUFD<31:0>)
ADC Result Word E (ADC1BUFE<31:0>)
ADC Result Word F (ADC1BUFF<31:0>)
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
details.
TABLE 4-10: DMA GLOBAL REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
3000 DMACON
3010 DMASTAT
3020 DMAADDR
SUSPEND DMABUSY
—
—
31:16
15:0
—
—
—
—
—
—
RDWR
DMACH<2:0>
31:16
15:0
DMAADDR<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-11: DMA CRC REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
BYTO<1:0>
WBO
—
—
BITO
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
—
PLEN<4:0>
CRCEN CRCAPP CRCTYP
CRCCH<2:0>
31:16
15:0
DCRCDATA<31:0>
DCRCXOR<31:0>
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-12: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FFF8
3060 DCH0CON
3070 DCH0ECON
3080 DCH0INT
3090 DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
3110 DCH0DAT
3120 DCH1CON
3130 DCH1ECON
3140 DCH1INT
3150 DCH1SSA
3160 DCH1DSA
15:0 CHBUSY
CHCHNS CHEN
—
CHAED CHCHN CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT PATEN
SIRQEN AIRQEN
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FFF8
31:16
15:0
CHDSA<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
15:0 CHBUSY
CHCHNS CHEN
—
CHAED CHCHN CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT PATEN
SIRQEN AIRQEN
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
0000
0000
0000
31:16
15:0
CHDSA<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-12: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FFF8
3170 DCH1SSIZ
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
3200 DCH2INT
3210 DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
15:0 CHBUSY
CHCHNS CHEN
—
CHAED CHCHN CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT PATEN
SIRQEN AIRQEN
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
CHDSA<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-12: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
3280 DCH2CPTR
3290 DCH2DAT
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
0000
0000
0000
00FF
FFF8
31:16
—
—
—
—
—
32A0 DCH3CON
32B0 DCH3ECON
32C0 DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3300 DCH3DSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350 DCH3DAT
15:0 CHBUSY
CHCHNS CHEN
—
CHAED CHCHN CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT PATEN
SIRQEN AIRQEN
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
CHDSA<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-13: COMPARATOR REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
COE
—
—
CPOL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COUT
—
—
—
—
—
—
—
—
—
—
—
CREF
—
—
—
—
—
—
—
—
—
—
—
—
0000
E1C3
0000
E1C3
0000
A000 CM1CON
A010 CM2CON
A060 CMSTAT
EVPOL<1:0>
CCH<1:0>
31:16
15:0
—
—
—
ON
—
COE
—
CPOL
—
COUT
—
EVPOL<1:0>
CREF
—
—
CCH<1:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
SIDL
—
—
C3OUT
C2OUT
C1OUT 0000
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-14: COMPARATOR VOLTAGE REFERENCE REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
9800 CVRCON
ON
CVROE
CVRR
CVRSS
CVR<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-15: FLASH CONTROLLER REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
(1)
F400 NVMCON
WR
WREN
WRERR LVDERR LVDSTAT
NVMOP<3:0>
31:16
15:0
F410 NVMKEY
NVMKEY<31:0>
NVMADDR<31:0>
NVMDATA<31:0>
31:16
15:0
(1)
F420 NVMADDR
31:16
15:0
F430 NVMDATA
31:16
15:0
NVMSRC
F440
NVMSRCADDR<31:0>
ADDR
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
TABLE 4-16: SYSTEM CONTROL REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
(2)
(2)
31:16
15:0
—
—
—
PLLODIV<2:0>
FRCDIV<2:0>
—
SOSCRDY PBDIVRDY
PBDIV<1:0>
PLLMULT<2:0>
x1xx
OSCCON
F000
(4)
(4)
COSC<2:0>
—
—
—
NOSC<2:0>
CLKLOCK ULOCK
SLOCK
—
SLPEN
—
CF
—
UFRCEN
—
SOSCEN OSWEN xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
F010 OSCTUN
—
TUN<5:0>
0000
0000
0000
31:16
15:0
—
RODIV<14:0>
REFOCON
REFOTRIM
F020
F030
ON
—
SIDL
OE
RSLP
—
DIVSWEN ACTIVE
—
—
—
—
ROSEL<3:0>
31:16
15:0
ROTRIM<8:0>
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
0000 WDTCON
—
—
—
—
SWDTPS<4:0>
WDTWINEN WDTCLR 0000
31:16
15:0
HVDR
—
—
—
—
—
SWR
—
—
—
—
—
—
—
—
WDTO
—
—
SLEEP
—
—
IDLE
—
—
BOR
—
—
0000
F600
RCON
(2)
CMR
—
VREGS
—
EXTR
—
POR xxxx
0000
SWRST 0000
0000
31:16
15:0
—
—
F610 RSWRST
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
CFGCON
F200
IOLOCK PMDLOCK
—
—
—
—
—
JTAGEN
TDOEN 000B
0000
TROEN
—
31:16
15:0
(3)
SYSKEY
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
SYSKEY<31:0>
—
F230
F240
F250
F260
F270
F280
F290
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CVRMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
AD1MD 0000
0000
CTMUMD
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
CMP2MD CMP1MD 0000
31:16
15:0
—
OC5MD OC4MD
OC3MD
IC3MD
—
OC2MD
IC2MD
—
OC1MD 0000
—
IC5MD
—
IC4MD
—
IC1MD
—
0000
0000
0000
31:16
15:0
—
—
T5MD
—
T4MD
—
T3MD
—
T2MD
I2C1MD
U2MD
—
T1MD
(5)
31:16
15:0
—
USB1MD
I2C1MD 0000
U1MD 0000
PMPMD 0000
(4)
—
SPI2MD SPI1MD
U5MD
—
U4MD
—
U3MD
—
31:16
15:0
—
—
—
—
—
—
—
—
—
REFOMD RTCCMD 0000
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2
“CLR, SET, and INV Registers” for more information.
2:
3:
4:
5:
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
This register does not have associated CLR, SET, INV registers.
This bit is available on 100-pin devices only.
This bit is available on PIC32MX4XX devices only.
TABLE 4-17: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
FSRSSEL<2:0>
31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY
15:0
—
—
—
—
—
—
—
—
—
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
2FF0 DEVCFG3
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
USERID<15:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPLLODIV<2:0>
FPLLIDIV<2:0>
(1)
(1)
15:0 UPLLEN
UPLLIDIV<2:0>
—
FPLLMUL<2:0>
31:16
15:0
—
—
FWDTWINSZ<1:0> FWDTEN WINDIS
—
WDTPS<4:0>
FCKSM<1:0>
FPBDIV<1:0>
CP
OSCIOFNC POSCMOD<1:0>
IESO
—
—
—
—
FSOSCEN
—
—
—
FNOSC<2:0>
31:16
15:0
—
—
—
—
—
—
—
BWP
—
—
—
PWP<7:4>
PWP<3:0>
—
ICESEL<1:0>
JTAGEN
DEBUG<1:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This bit is available on PIC32MX4XX devices only.
TABLE 4-18: DEVICE AND REVISION ID SUMMARY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
VER<3:0>
DEVID<27:16>
xxxx
xxxx
F220
DEVID
DEVID<15:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
Reset values are dependent on the device variant.
TABLE 4-19: PORTA REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L,
PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0060
0000
6000 ANSELA
ANSELA10 ANSELA9
31:16
—
—
6010
TRISA
15:0 TRISA15 TRISA14
TRISA10 TRISA9
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 xxxx
31:16
15:0
—
RA15
—
—
RA14
—
—
RA10
—
—
RA9
—
—
RA7
—
—
RA6
—
—
RA5
—
—
RA4
—
—
RA3
—
—
RA2
—
—
RA1
—
—
RA0
—
0000
xxxx
0000
6020 PORTA
31:16
6030
6040
LATA
15:0 LATA15
31:16
LATA14
—
LATA10
—
LATA9
—
LATA7
—
LATA6
—
LATA5
—
LATA4
—
LATA3
—
LATA2
—
LATA1
—
LATA0 xxxx
0000
ODCA0 xxxx
0000
—
—
ODCA
15:0 ODCA15 ODCA14
31:16
—
—
ODCA7
—
ODCA6
—
ODCA5
—
ODCA4
—
ODCA3
—
ODCA2
—
ODCA1
—
—
—
—
—
—
6050 CNPUA
6060 CNPDA
6070 CNCONA
6080 CNENA
15:0 CNPUA15 CNPUA14
31:16
15:0 CNPDA15 CNPDA14
CNPUA10 CNPUA9
CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 xxxx
0000
CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
CNPDA10 CNPDA9
31:16
15:0
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0 CNIEA15 CNIEA14
CNIEA10 CNIEA9
CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
6090 CNSTATA
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
—
—
—
—
STATA15 STATA14
STATA10 STATA9
STATA7 STATA6 STATA5 STATA4 STATA3 STATA2 STATA1 STATA0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-20: PORTB REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6100 ANSELB
15:0 ANSELB15 ANSELB14 ANSELB13 ANSELB12 ANSELB11 ANSELB10 ANSELB9 ANSELB8 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
TRISB4
—
—
—
—
—
0000
6110
6120 PORTB
6130 LATB
TRISB
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5
TRISB3 TRISB2 TRISB1 TRISB0 xxxx
31:16
15:0
—
RB15
—
—
RB14
—
—
RB13
—
—
RB12
—
—
RB11
—
—
RB10
—
—
RB9
—
—
RB8
—
—
RB7
—
—
RB6
—
—
RB5
—
—
RB3
—
—
RB2
—
—
RB1
—
—
RB0
—
0000
xxxx
0000
RB4
—
31:16
15:0 LATB15
31:16
LATB14
—
LATB13
—
LATB12
—
LATB11
—
LATB10
—
LATB9
—
LATB8
—
LATB7
—
LATB6
—
LATB5
—
LATB4
—
LATB3
—
LATB2
—
LATB1
—
LATB0 xxxx
0000
—
—
6150 CNPUB
6160 CNPDB
6170 CNCONB
6180 CNENB
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 xxxx
31:16 0000
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6190 CNSTATB
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
xxxx
STATB15 STATB14 STATB13 STATB12 STATB11 STATB10 STATB9 STATB8 STATB7 STATB6 STATB5 STATB4 STATB3 STATB2 STATB1 STATB0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-21: PORTC REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L,
PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
F000
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
0000
0000
xxxx
0000
xxxx
6200 ANSELC
6210 TRISC
6220 PORTC
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
TRISC15
—
TRISC14
TRISC13
—
TRISC12
TRISC4
—
TRISC3
—
TRISC2
—
TRISC1
—
31:16
15:0
—
—
RC15
—
RC14
RC13
—
RC12
RC4
—
RC3
—
RC2
—
RC1
—
31:16
15:0
—
—
6230
6240
LATC
LATC15
—
LATC14
LATC13
—
LATC12
LATC4
—
LATC3
—
LATC2
—
LATC1
—
31:16
15:0
—
—
ODCC
—
—
—
—
ODCC4
—
ODCC3
—
ODCC2
—
ODCC1
—
31:16
—
—
—
—
6250 CNPUC
6260 CNPDC
6270 CNCONC
6280 CNENC
6290 CNSTATC
15:0 CNPUC15
31:16
15:0 CNPDC15
CNPUC14
CNPUC13
—
CNPUC12
CNPUC4 CNPUC3 CNPUC2 CNPUC1
—
—
—
—
—
—
—
CNPDC14
CNPDC13
—
CNPDC12
CNPDC4 CNPDC3 CNPDC2 CNPDC1
31:16
15:0
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
31:16
15:0
—
—
—
—
—
CNIEC15
—
CNIEC14
—
CNIEC13
—
CNIEC12
—
CNIEC4
—
CNIEC3
—
CNIEC2
—
CNIEC1
—
31:16
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12
CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-22: PORTC REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H,
PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
TRISC15
—
—
—
TRISC13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
0000
0000
xxxx
0000
xxxx
6210 TRISC
6220 PORTC
TRISC14
TRISC12
31:16
15:0
—
—
RC15
—
RC14
RC13
—
RC12
31:16
15:0
—
—
6230
LATC
LATC15
—
LATC14
LATC13
—
LATC12
31:16
—
—
6250 CNPUC
6260 CNPDC
6270 CNCONC
6280 CNENC
6290 CNSTATC
15:0 CNPUC15
31:16
15:0 CNPDC15
CNPUC14
CNPUC13
—
CNPUC12
—
—
—
CNPDC14
CNPDC13
—
CNPDC12
31:16
15:0
—
ON
—
—
—
—
SIDL
—
—
31:16
15:0
—
CNIEC15
—
CNIEC14
—
CNIEC13
—
CNIEC12
—
31:16
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-23: PORTD REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L,
PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
00E0
0000
6300 ANSELD
6310 TRISD
5320 PORTD
ANSELD3 ANSELD2 ANSELD1
31:16
—
—
—
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 xxxx
31:16
15:0
—
RD15
—
—
RD14
—
—
RD13
—
—
RD12
—
—
RD11
—
—
RD10
—
—
RD9
—
—
RD8
—
—
RD7
—
—
RD6
—
—
RD5
—
—
RD4
—
—
RD3
—
—
RD2
—
—
RD1
—
—
RD0
—
0000
xxxx
0000
31:16
6330
6340
LATD
15:0 LATD15
31:16
LATD14
—
LATD13
—
LATD12
—
LATD11
—
LATD10
—
LATD9
—
LATD8
—
LATD7
—
LATD6
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0 xxxx
0000
ODCD0 xxxx
0000
—
—
ODCD
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6350 CNPUD
6360 CNPDD
6370 CNCOND
6380 CNEND
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 xxxx
31:16 0000
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0 CNIED15 CNIED14 CNIED13 CNIED12 CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6390 CNSTATD
CNS
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
xxxx
TATD15 STATD14 STATD13 STATD12 STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-24: PORTD REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H,
PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, PIC32MX470F512H DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
00E0
0000
6300 ANSELD
6310 TRISD
5320 PORTD
ANSELD3 ANSELD2 ANSELD1
31:16
15:0
—
—
—
—
—
—
—
TRISD3
—
—
TRISD2
—
—
TRISD1
—
TRISD11 TRISD10
TRISD9
—
TRISD8
—
TRISD7
—
TRISD6
—
TRISD5
—
TRISD4
—
TRISD0 xxxx
31:16
15:0
—
RD11
—
—
RD10
—
—
RD0
—
0000
xxxx
0000
RD9
—
RD8
—
RD7
—
RD6
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
31:16
15:0
6330
LATD
LATD11
—
LATD10
—
LATD9
—
LATD8
—
LATD7
—
LATD6
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0 xxxx
0000
ODCD0 xxxx
0000
31:16
15:0
—
6340 ODCD
6350 CNPUD
6360 CNPDD
6370 CNCOND
6380 CNEND
ODCD11
—
ODCD10
—
ODCD9
—
ODCD8
—
ODCD7
—
ODCD6
—
ODCD5
—
ODCD4
—
—
—
—
31:16
15:0
—
—
—
—
CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 xxxx
0000
CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0
CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
6390 CNSTATD
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
xxxx
STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-25: PORTE REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L,
PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, PIC32MX470F512L DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSELE2
—
—
—
—
—
—
—
0000
00F4
0000
6400 ANSELE
6410 TRISE
6420 PORTE
ANSELE7 ANSELE6 ANSELE5 ANSELE4
31:16
15:0
—
TRISE7
—
—
TRISE6
—
—
TRISE5
—
—
TRISE4
—
—
TRISE9 TRISE8
TRISE3
—
TRISE2
—
TRISE1 TRISE0 xxxx
31:16
15:0
—
RE9
—
—
RE8
—
—
RE1
—
—
RE0
—
0000
xxxx
0000
RE7
—
RE6
—
RE5
—
RE4
—
RE3
—
RE2
—
31:16
15:0
6440
6440
LATE
LATE9
—
LATE8
—
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0 xxxx
0000
ODCE0 xxxx
0000
31:16
15:0
—
ODCE
ODCE9
—
ODCE8
—
—
—
—
—
ODCE3
—
—
ODCE1
—
31:16
15:0
—
—
—
—
—
—
6450 CNPUE
6460 CNPDE
6470 CNCONE
6480 CNENE
CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 xxxx
0000
CNPDE9 CNPDE8 CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0
CNIEE9 CNIEE8 CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 xxxx
31:16
—
—
—
—
—
—
—
—
—
—
0000
6490 CNSTATE
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
xxxx
STATE9 STATE8 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-26: PORTE REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H,
PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSELE2
—
—
—
—
—
—
—
0000
00F4
0000
6400 ANSELE
6410 TRISE
6420 PORTE
ANSELE7 ANSELE6 ANSELE5 ANSELE4
31:16
15:0
—
TRISE7
—
—
TRISE6
—
—
TRISE5
—
—
TRISE4
—
—
TRISE3
—
TRISE2
—
TRISE1 TRISE0 xxxx
31:16
15:0
—
RE1
—
—
RE0
—
0000
xxxx
0000
RE7
—
RE6
—
RE5
—
RE4
—
RE3
—
RE2
—
31:16
15:0
6440
6440
LATE
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0 xxxx
0000
ODCE0 xxxx
0000
31:16
15:0
—
ODCE
—
—
—
—
ODCE3
—
—
ODCE1
—
31:16
15:0
—
—
—
—
—
—
6450 CNPUE
6460 CNPDE
6470 CNCONE
6480 CNENE
CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 xxxx
0000
CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0
—
—
—
CNIEE7
—
CNIEE6
—
CNIEE5
—
CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 xxxx
31:16
—
—
—
—
—
0000
6490 CNSTATE
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
—
xxxx
STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-27: PORTF REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, AND PIC32MX370F512L DEVICES
ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
—
—
TRISF7
—
—
TRISF6
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
TRISF2
—
—
TRISF1
—
—
0000
6510 TRISF
6520 PORTF
TRISF13 TRISF12
TRISF0 xxxx
31:16
15:0
—
RF13
—
—
RF12
—
—
RF0
—
0000
xxxx
0000
RF8
—
RF7
—
RF6
—
RF5
—
RF4
—
RF3
—
RF2
—
RF1
—
31:16
15:0
6530
LATF
LATF13
—
LATF12
—
LATF8
—
LATF7
—
LATF6
—
LATF5
—
LATF4
—
LATF3
—
LATF2
—
LATF1
—
LATF0 xxxx
0000
ODCF0 xxxx
0000
31:16
15:0
—
6540 ODCF
6550 CNPUF
6560 CNPDF
6570 CNCONF
6580 CNENF
ODCF13 ODCF12
ODCF8
—
ODCF7
—
ODCF6
—
ODCF5
—
ODCF4
—
ODCF3
—
ODCF2
—
ODCF1
—
31:16
15:0
—
—
—
CNPUF13 CNPUF12
CNPUF8 CNPUF7 CNPUF6 CNPUF5 CNPUF4 CNPDF3 CNPUF2 CNPUF1 CNPUF0 xxxx
0000
CNPDF8 CNPDF7 CNPDF6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
CNPDF13 CNPDF12
31:16
15:0
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0
CNIEF13 CNIEF12
CNIEF8 CNIEF7 CNIEF6 CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
0000
6590 CNSTATF
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
xxxx
STATF13 STATF12
STATF8 STATF7 STATF6 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-28: PORTF REGISTER MAP FOR PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES
ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
TRISF2
—
—
TRISF1
—
—
0000
6510 TRISF
6520 PORTF
TRISF13 TRISF12
TRISF0 xxxx
31:16
15:0
—
RF13
—
—
RF12
—
—
RF0
—
0000
xxxx
0000
RF8
—
RF5
—
RF4
—
RF3
—
RF2
—
RF1
—
31:16
15:0
6530
6540
LATF
LATF13
—
LATF12
—
LATF8
—
LATF5
—
LATF4
—
LATF3
—
LATF2
—
LATF1
—
LATF0 xxxx
0000
ODCF0 xxxx
0000
31:16
15:0
—
ODCF
ODCF13 ODCF12
ODCF8
—
ODCF5
—
ODCF4
—
ODCF3
—
ODCF2
—
ODCF1
—
31:16
15:0
—
—
—
6550 CNPUF
6560 CNPDF
6570 CNCONF
6580 CNENF
CNPUF13 CNPUF12
CNPUF8
—
CNPUF5 CNPUF4 CNPDF3 CNPUF2 CNPUF1 CNPUF0 xxxx
0000
CNPDF5 CNPFF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
CNPDF13 CNPDF12
CNPDF8
—
31:16
15:0
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
31:16
15:0
—
CNIEF13 CNIEF12
CNIEF8
—
CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 xxxx
31:16
—
—
—
—
—
—
—
—
0000
6590 CNSTATF
CN
CN
CN
STATF8
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
xxxx
STATF13 STATF12
STATF5 STATF4 STATF3 STATF2 STATF1 STATF0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-29: PORTF REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, AND PIC32MX370F512H DEVICES
ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF6
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
TRISF2
—
—
TRISF1
—
—
0000
6510 TRISF
6520 PORTF
TRISF0 xxxx
31:16
15:0
—
—
RF0
—
0000
xxxx
0000
—
RF6
—
RF5
—
RF4
—
RF3
—
RF2
—
RF1
—
31:16
15:0
—
6530
6540
LATF
—
LATF6
—
LATF5
—
LATF4
—
LATF3
—
LATF2
—
LATF1
—
LATF0 xxxx
0000
ODCF0 xxxx
0000
31:16
15:0
—
—
ODCF
—
ODCF6
—
ODCF5
—
ODCF4
—
ODCF3
—
ODCF2
—
ODCF1
—
31:16
15:0
—
—
6550 CNPUF
6560 CNPDF
6570 CNCONF
6580 CNENF
—
CNPUF6 CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 CNPUF0 xxxx
0000
CNPDF6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
SIDL
—
31:16
15:0
—
CNIEF6 CNIEF5 CNIEF4
CNIEF3 CNIEF2 CNIEF1 CNIEF0 xxxx
31:16
—
—
—
—
—
—
—
—
0000
6590 CNSTATF
CN
CN
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
—
—
xxxx
STATF6 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-30: PORTF REGISTER MAP FOR PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES
ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF1
—
—
0000
6510 TRISF
6520 PORTF
TRISF0 xxxx
31:16
15:0
—
—
RF0
—
0000
xxxx
0000
—
RF5
—
RF4
—
RF3
—
RF1
—
31:16
15:0
—
6530
LATF
—
LATF5
—
LATF4
—
LATF3
—
LATF1
—
LATF0 xxxx
0000
ODCF0 xxxx
0000
31:16
15:0
—
—
6540 ODCF
6550 CNPUF
6560 CNPDF
6570 CNCONF
6580 CNENF
—
ODCF5
—
ODCF4
—
ODCF3
—
ODCF1
—
31:16
15:0
—
—
—
CNPUF5 CNPUF4 CNPUF3
CNPUF1 CNPUF0 xxxx
0000
CNPDF1 CNPDF0 xxxx
31:16
15:0
—
—
—
—
—
—
—
CNPDF5 CNPDF4 CNPDF3
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
SIDL
—
31:16
15:0
—
CNIEF5 CNIEF4 CNIEF3
CNIEF1 CNIEF0 xxxx
31:16
—
—
—
—
—
—
0000
6590 CNSTATF
CN
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
—
—
—
—
xxxx
STATF5 STATF4 STATF3
STATF1 STATF0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-31: PORTG REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L,
PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
01C0
0000
6600 ANSELG
6610 TRISG
6620 PORTG
ANSELG9 ANSELG8 ANSELG7 ANSELG6
31:16
—
TRISG9
—
—
TRISG8
—
—
TRISG7
—
—
TRISG6
—
15:0 TRISG15 TRISG14 TRISG13 TRISG12
TRISG3 TRISG2 TRISG1 TRISG0 xxxx
31:16
15:0
—
RG15
—
—
RG14
—
—
RG13
—
—
RG12
—
—
RG3
—
—
RG2
—
—
RG1
—
—
RG0
—
0000
xxxx
0000
RG9
—
RG8
—
RG7
—
RG6
—
31:16
6630
LATG
15:0 LATG15
31:16
LATG14
—
LATG13
—
LATG12
—
LATG9
—
LATG8
—
LATG7
—
LATG6
—
LATG3
—
LATG2
—
LATG1
—
LATG0 xxxx
0000
—
—
6640 ODCG
6650 CNPUG
6660 CNPDG
6670 CNCONG
6680 CNENG
15:0 ODCG15 ODCG14 ODCG13 ODCG12
31:16
15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12
31:16
15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12
—
—
—
—
ODCG3 ODCG2 ODCG1 ODCG0 xxxx
0000
CNPUG3 CNPUG2 CNPUG1 CNPUG0 xxxx
0000
CNPDG3 CNPDG2 CNPDG1 CNPDG0 xxxx
—
—
—
—
—
—
—
—
—
—
—
—
CNPUG9 CNPUG8 CNPUG7 CNPUG6
—
—
—
—
—
—
—
—
—
—
—
—
CNPDG9 CNPDG8 CNPDG7 CNPDG6
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
—
—
—
—
15:0 CNIEG15 CNIEG14 CNIEG13 CNIEG12
CNIEG9
—
CNIEG8
—
CNIEG7
—
CNIEG6
—
CNIEG3 CNIEG2 CNIEG1 CNIEG0 xxxx
31:16
—
—
—
—
—
—
—
—
0000
6690 CNSTATG
CN
CN
CN
CN
CN
STATG9
CN
STATG8
CN
STATG7
CN
STATG6
CN
CN
CN
CN
15:0
—
—
—
—
xxxx
STATG15 STATG14 STATG13 STATG12
STATG3 STATG2 STATG1 STATG0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-32: PORTG REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H,
PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
01C0
0000
6600 ANSELG
6610 TRISG
6620 PORTG
ANSELG9 ANSELG8 ANSELG7 ANSELG6
31:16
15:0
—
TRISG9
—
—
TRISG8
—
—
TRISG7
—
—
TRISG6
—
TRISG3 TRISG2 TRISG1 TRISG0 xxxx
31:16
15:0
—
RG3
—
—
RG2
—
—
RG1
—
—
RG0
—
0000
xxxx
0000
RG9
—
RG8
—
RG7
—
RG6
—
31:16
15:0
6630
LATG
LATG9
—
LATG8
—
LATG7
—
LATG6
—
LATG3
—
LATG2
—
LATG1
—
LATG0 xxxx
0000
31:16
15:0
—
6640 ODCG
6650 CNPUG
6660 CNPDG
6670 CNCONG
6680 CNENG
—
—
—
—
ODCG3 ODCG2 ODCG1 ODCG02 xxxx
0000
CNPUG3 CNPUG2 CNPUG1 CNPUG0 xxxx
0000
CNPDG3 CNPDG2 CNPDG1 CNPDG0 xxxx
31:16
15:0
—
—
—
—
—
—
—
—
CNPUG9 CNPUG8 CNPUG7 CNPUG6
31:16
15:0
—
—
—
—
—
—
—
—
CNPDG9 CNPDG8 CNPDG7 CNPDG6
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
31:16
15:0
—
—
—
—
CNIEG9
—
CNIEG8
—
CNIEG7
—
CNIEG6
—
CNIEG3 CNIEG2 CNIEG1 CNIEG0 xxxx
31:16
—
—
—
—
0000
6690 CNSTATG
CN
STATG9
CN
STATG8
CN
STATG7
CN
STATG6
CN
CN
CN
CN
15:0
—
—
—
—
—
—
—
—
xxxx
STATG3 STATG2 STATG1 STATG0
Legend:
x= Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
FA04
FA08
FA0C
FA10
FA18
FA1C
FA20
FA24
FA28
FA2C
FA30
FA34
FA38
FA48
INT1R
INT2R
INT3R
INT4R
T2CKR
T3CKR
T4CKR
T5CKR
IC1R
INT1R<3:0>
31:16
15:0
—
—
INT2R<3:0>
31:16
15:0
—
INT3R<3:0>
31:16
15:0
—
—
INT4R<3:0>
31:16
15:0
—
—
T2CKR<3:0>
31:16
15:0
—
—
T3CKR<3:0>
31:16
15:0
—
—
T4CKR<3:0>
31:16
15:0
—
—
T5CKR<3:0>
31:16
15:0
—
—
IC1R<3:0>
31:16
15:0
—
—
IC2R
IC2R<3:0>
31:16
15:0
—
—
IC3R
IC3R<3:0>
31:16
15:0
—
—
IC4R
IC4R<3:0>
31:16
15:0
—
—
IC5R
IC5R<3:0>
31:16
15:0
—
—
OCFAR
OCFBR
OCFAR<3:0>
31:16
15:0
—
—
FA4C
OCFBR<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
FA50
U1RXR
U1RXR<3:0>
31:16
15:0
—
—
FA54 U1CTSR
U1CTSR<3:0>
31:16
15:0
—
—
FA58
U2RXR
U2RXR<3:0>
31:16
15:0
—
—
FA5C U2CTSR
U2CTSR<3:0>
31:16
15:0
—
—
FA60
U3RXR
U3RXR<3:0>
31:16
15:0
—
—
FA64 U3CTSR
U3CTSR<3:0>
31:16
15:0
—
—
FA68
U4RXR
U4RXR<3:0>
31:16
15:0
—
—
FA6C U4CTSR
U4CTSR<3:0>
31:16
15:0
—
—
FA70
U5RXR
U5RXR<3:0>
31:16
15:0
—
—
FA74 U5CTSR
U5CTSR<3:0>
31:16
15:0
—
—
FA84
FA88
FA90
FA94
SDI1R
SS1R
SDI2R
SS2R
SDI1R<3:0>
31:16
15:0
—
—
SS1R<3:0>
31:16
15:0
—
—
SDI2R<3:0>
31:16
15:0
—
—
SS2R<3:0>
31:16
15:0
—
—
FAD0 REFCLKIR
Legend:
REFCLKIR<3:0>
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
(1)
(1)
FB38 RPA14R
FB3C RPA15R
FB40 RPB0R
FB44 RPB1R
FB48 RPB2R
FB4C RPB3R
FB54 RPB5R
FB58 RPB6R
FB5C RPB7R
FB60 RPB8R
FB64 RPB9R
RPA14<3:0>
31:16
15:0
—
RPA15<3:0>
31:16
15:0
—
—
RPB0<3:0>
31:16
15:0
—
—
—
RPB1<3:0>
31:16
15:0
—
RPB2<3:0>
31:16
15:0
—
—
RPB3<3:0>
31:16
15:0
—
—
RPB5<3:0>
31:16
15:0
—
—
RPB6<3:0>
31:16
15:0
—
—
RPB7<3:0>
31:16
15:0
—
—
RPB8<3:0>
31:16
15:0
—
—
RPB9<3:0>
31:16
15:0
—
—
FB68 RPB10R
FB78 RPB14R
FB7C RPB15R
RPB10<3:0>
31:16
15:0
—
—
RPB14<3:0>
31:16
15:0
—
—
RPB15<3:0>
31:16
15:0
—
—
—
(1)
FB84 RPC1R
FB88 RPC2R
FB8C RPC3R
FB90 RPC4R
RPC1<3:0>
31:16
15:0
—
(1)
(1)
(1)
RPC2<3:0>
31:16
15:0
—
—
—
RPC3<3:0>
31:16
15:0
—
RPC4<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
(1)
(1)
FBB4 RPC13R
FBB8 RPC14R
FBC0 RPD0R
FBC4 RPD1R
FBC8 RPD2R
FBCC RPD3R
FBD0 RPD4R
FBD4 RPD5R
FBE0 RPD8R
FBE4 RPD9R
FBE8 RPD10R
FBEC RPD11R
FBF0 RPD12R
FBF8 RPD14R
FBFC RPD15R
RPC13<3:0>
31:16
15:0
—
RPC14<3:0>
31:16
15:0
—
—
RPD0<3:0>
31:16
15:0
—
—
RPD1<3:0>
31:16
15:0
—
—
RPD2<3:0>
31:16
15:0
—
—
RPD3<3:0>
31:16
15:0
—
—
RPD4<3:0>
31:16
15:0
—
—
RPD5<3:0>
31:16
15:0
—
—
RPD8<3:0>
31:16
15:0
—
—
RPD9<3:0>
31:16
15:0
—
—
RPD10<3:0>
31:16
15:0
—
—
RPD11<3:0>
31:16
15:0
—
—
(1)
(1)
(1)
RPD12<3:0>
31:16
15:0
—
—
RPD14<3:0>
31:16
15:0
—
—
RPD15<3:0>
31:16
15:0
—
—
—
(1)
FC0C RPE3R
FC14 RPE5R
FC20 RPE8R
RPE3<3:0>
31:16
15:0
—
(1)
RPE5<3:0>
31:16
15:0
—
—
(1)
RPE8<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
(1)
FC24 RPE9R
FC40 RPF0R
FC44 RPF1R
FC48 RPF2R
FC4C RPF3R
FC50 RPF4R
FC54 RPF5R
FC58 RPF6R
RPE9<3:0>
31:16
15:0
—
—
RPF0<3:0>
31:16
15:0
—
RPF1<3:0>
31:16
15:0
—
—
RPF2<3:0>
31:16
15:0
—
—
RPF3<3:0>
31:16
15:0
—
—
RPF4<3:0>
31:16
15:0
—
—
RPF5<3:0>
31:16
15:0
—
—
RPF6<3:0>
31:16
15:0
—
—
(1)
(1)
FC5C RPF7R
FC60 RPF8R
RPF7<3:0>
31:16
15:0
—
—
RPF8<3:0>
31:16
15:0
—
—
(1)
(1)
FC70 RPF12R
FC74 RPF13R
RPF12<3:0>
31:16
15:0
—
—
RPF13<3:0>
31:16
15:0
—
—
—
(1)
FC80 RPG0R
FC84 RPG1R
FC98 RPG6R
FC9C RPG7R
FCA0 RPG8R
FCA4 RPG9R
RPG0<3:0>
31:16
15:0
—
(1)
RPG1<3:0>
31:16
15:0
—
—
—
RPG6<3:0>
31:16
15:0
—
RPG7<3:0>
31:16
15:0
—
—
RPG8<3:0>
31:16
15:0
—
—
RPG9<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not available on 64-pin devices.
TABLE 4-35: PARALLEL MASTER PORT REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
ALP
—
—
CS2P
—
—
CS1P
—
—
—
—
—
WRSP
—
—
0000
7000 PMCON
7010 PMMODE
7020 PMADDR
7030 PMDOUT
7040 PMDIN
7050 PMAEN
7060 PMSTAT
ADRMUX<1:0>
PMPTTL PTWREN PTRDEN
CSF<1:0>
RDSP 0000
31:16
15:0
—
—
—
—
—
MODE16
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
BUSY
—
IRQM<1:0>
INCM<1:0>
MODE<1:0>
WAITB<1:0>
WAITM<3:0>
WAITE<1:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
CS2
CS1
ADDR<13:0>
31:16
15:0
DATAOUT<31:0>
DATAIN<31:0>
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTEN<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IBF
IBOV
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
OB3E
OB2E
OB1E
OB0E BFBF
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-36: PREFETCH REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000
(1)
4000 CHECON
DCSZ<1:0>
PREFEN<1:0>
PFMWS<2:0>
0007
31:16 CHEWEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
00xx
(1)
4010 CHEACC
CHEIDX<3:0>
15:0
31:16
15:0
—
LTAGBOOT
LTAG<23:16>
LVALID
xxx0
xxx2
(1)
4020 CHETAG
LTAG<15:4>
LLOCK
LTYPE
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
(1)
4030 CHEMSK
4040 CHEW0
4050 CHEW1
4060 CHEW2
4070 CHEW3
4080 CHELRU
4090 CHEHIT
40A0 CHEMIS
40C0 CHEPFABT
LMASK<15:5>
—
—
—
31:16
15:0
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
CHELRU<24:16>
31:16
15:0
CHELRU<15:0>
CHEHIT<31:0>
31:16
15:0
31:16
15:0
CHEMIS<31:0>
31:16
15:0
CHEPFABT<31:0>
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more
information.
TABLE 4-37: RTCC REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
CAL<9:0>
0000
RTCWREN RTCSYNC HALFSEC RTCOE 0000
0200 RTCCON
0210 RTCALRM
0220 RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
—
—
—
—
—
—
RTSECSEL RTCCLKON
—
—
—
—
31:16
—
—
—
—
—
—
0000
0000
xxxx
xx00
xxxx
xx00
xxxx
xx00
00xx
xx0x
15:0 ALRMEN CHIME
PIV
ALRMSYNC
AMASK<3:0>
HR01<3:0>
ARPT<7:0>
31:16
15:0
HR10<3:0>
MIN10<3:0>
—
MIN01<3:0>
SEC10<3:0>
YEAR10<3:0>
DAY10<3:0>
HR10<3:0>
SEC01<3:0>
YEAR01<3:0>
DAY01<3:0>
HR01<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
MONTH10<3:0>
MONTH01<3:0>
WDAY01<3:0>
MIN01<3:0>
—
—
—
31:16
15:0
MIN10<3:0>
—
SEC10<3:0>
SEC01<3:0>
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
MONTH10<3:0>
MONTH01<3:0>
WDAY01<3:0>
DAY10<3:0>
DAY01<3:0>
—
—
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-38: CTMU REGISTER MAP
Bits
24/8
31/15
30/14
29/13
28/12
27/11
26/10
25/9
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 EDG1MOD EDG1POL
EDG2STAT
0000
0000
EDG1SEL<3:0>
CTMUSIDL TGEN
EDG1STAT EDG2MOD EDG2POL
CTTRIG
EDG2SEL<3:0>
ITRIM<5:0>
—
—
A200 CTMUCON
15:0
ON
—
EDGEN EDGSEQEN IDISSEN
IRNG<1:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for
more information.
TABLE 4-39: USB REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIF
—
—
—
—
ACTVIF
—
—
—
—
—
—
—
—
—
—
—
0000
(2)
5040 U1OTGIR
5050 U1OTGIE
5060 U1OTGSTAT
5070 U1OTGCON
T1MSECIF LSTATEIF
SESVDIF SESENDIF
VBUSVDIF 0000
0000
VBUSVDIE 0000
0000
VBUSVD 0000
0000
31:16
15:0
—
—
—
—
—
IDIE
—
T1MSECIE LSTATEIE
ACTVIE
—
SESVDIE SESENDIE
31:16
15:0
—
—
—
—
LSTATE
—
—
—
—
(3)
ID
—
SESVD SESEND
31:16
15:0
—
—
—
—
—
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
31:16
15:0
—
UACTPND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
5080
5200
U1PWRC
(4)
USLPGRD USBBUSY
USUSPEND USBPWR 0000
31:16
—
IDLEIF
—
—
TRNIF
—
—
—
0000
(2)
U1IR
URSTIF 0000
DETACHIF 0000
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF ATTACHIF RESUMEIF
SOFIF
—
UERRIF
—
—
—
—
—
0000
5210
5220
U1IE
URSTIE 0000
DETACHIE 0000
STALLIE ATTACHIE RESUMEIE
IDLEIE
—
TRNIE
—
SOFIE
—
UERRIE
31:16
15:0
—
BTSEF
—
—
BMXEF
—
—
DMAEF
—
—
CRC5EF
EOFEF
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
(2)
U1EIR
BTOEF
—
DFN8EF CRC16EF
PIDEF
—
31:16
15:0
—
—
5230
5240
5250
U1EIE
CRC5EE
EOFEE
—
BTSEE
—
BMXEE
—
DMAEE
—
BTOEE
—
DFN8EE CRC16EE
PIDEE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIR
—
—
PPBI
—
—
—
—
(3)
U1STAT
ENDPT<3:0>
—
31:16
—
—
SE0
—
—
PKTDIS
TOKBUSY
—
—
—
U1CON
USBEN 0000
SOFEN 0000
15:0
—
—
—
—
—
—
—
—
JSTATE
USBRST HOSTEN RESUME PPBRST
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPDEN
—
—
—
DEVADDR<6:0>
—
—
—
—
—
—
0000
0000
0000
0000
5260
5270
U1ADDR
U1BDTP1
31:16
15:0
—
—
—
—
—
BDTPTRL<7:1>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See
Section 12.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
2:
3:
4:
TABLE 4-39: USB REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
(3)
(3)
5280 U1FRML
FRML<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRMH<2:0>
—
5290 U1FRMH
31:16
15:0
52A0
52B0
52C0
52D0
52E0
5300
5310
5320
5330
5340
5350
5360
5370
5380
U1TOK
U1SOF
U1BDTP2
U1BDTP3
U1CNFG1
U1EP0
PID<3:0>
EP<3:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNT<7:0>
31:16
15:0
—
BDTPTRH<7:0>
31:16
15:0
—
—
BDTPTRU<7:0>
31:16
15:0
—
UTEYE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USBSIDL
—
—
—
—
—
—
—
—
—
—
UOEMON
UASUSPND 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
31:16
15:0
—
—
LSPD
—
RETRYDIS
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EP1
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP2
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP3
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP4
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP5
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP6
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP7
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
U1EP8
—
EPCONDIS EPRXEN EPTXEN EPSTALL
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See
Section 12.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
2:
3:
4:
TABLE 4-39: USB REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
5390
53A0
53B0
53C0
53D0
53E0
53F0
U1EP9
U1EP10
U1EP11
U1EP12
U1EP13
U1EP14
U1EP15
EPCONDIS EPRXEN EPTXEN EPSTALL
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See
Section 12.2 “CLR, SET, and INV Registers” for more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
2:
3:
4:
PIC32MX330/350/370/430/450/470
4.3
Control Registers
Register 4-1 through Register 4-8 are used for setting
the RAM and Flash memory partitions for data and
code.
REGISTER 4-1:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
R/W-1
U-0
U-0
BMX
CHEDMA
R/W-1
31:24
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
R/W-1
BMX
ERRIXI
U-0
R/W-1
BMX
ERRICD
U-0
R/W-1
BMX
ERRDS
U-0
R/W-1
BMX
ERRIS
U-0
BMX
ERRDMA
U-0
23:16
15:8
7:0
U-0
—
U-0
—
R/W-1
BMX
WSDRM
U-0
—
—
U-0
—
U-0
—
R/W-0
—
R/W-0
—
R/W-1
U-0
U-0
—
—
—
—
BMXARB<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-27 Unimplemented: Read as ‘0’
bit 26 BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit
1= Enable program Flash memory (data) cacheability for DMA accesses
(requires cache to have data caching enabled)
0= Disable program Flash memory (data) cacheability for DMA accesses
(hits are still read from the cache, but misses do not update the cache)
bit 25-21 Unimplemented: Read as ‘0’
bit 20
bit 19
bit 18
bit 17
bit 16
BMXERRIXI: Enable Bus Error from IXI bit
1= Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0= Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1= Enable bus error exceptions for unmapped address accesses initiated from ICD
0= Disable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA: Bus Error from DMA bit
1= Enable bus error exceptions for unmapped address accesses initiated from DMA
0= Disable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1= Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0= Disable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1= Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0= Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7 Unimplemented: Read as ‘0’
bit 6
BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1= Data RAM accesses from CPU have one wait state for address setup
0= Data RAM accesses from CPU have zero wait states for address setup
Unimplemented: Read as ‘0’
bit 5-3
bit 2-0
BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111= Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011= Reserved (using these Configuration modes will produce undefined behavior)
010= Arbitration Mode 2
001= Arbitration Mode 1 (default)
000= Arbitration Mode 0
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 87
PIC32MX330/350/370/430/450/470
REGISTER 4-2:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
BMXDKPBA<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXDKPBA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 9-0
BMXDKPBA<9:0>: Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
DS60001185B-page 88
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 4-3:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
24/16/8/0
25/17/9/1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
BMXDUDBA<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXDUDBA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM, the value
must be greater than BMXDKPBA.
bit 9-0
BMXDUDBA<9:0>: Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 89
PIC32MX330/350/370/430/450/470
REGISTER 4-4:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
BMXDUPBA<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXDUPBA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.
bit 9-0
BMXDUPBA<9:0>: Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
DS60001185B-page 90
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 4-5:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXDRMSZ: DATA RAM SIZE REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
31:24
23:16
15:8
7:0
BMXDRMSZ<31:24>
R
R
BMXDRMSZ<23:16>
R
R
BMXDRMSZ<15:8>
R
R
BMXDRMSZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits
Static value that indicates the size of the Data RAM in bytes:
0x00004000 = device has 16 KB RAM
0x00008000 = device has 32 KB RAM
0x00010000 = device has 64 KB RAM
0x00020000 = device has 128 KB RAM
REGISTER 4-6:
Bit Bit
BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
BMXPUPBA<19:16>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
R-0
BMXPUPBA<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BMXPUPBA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
bit 10-0 BMXPUPBA<10:0>: Read-Only bits
Value is always ‘0’, which forces 2 KB increments
Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXPFMSZ.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 91
PIC32MX330/350/370/430/450/470
REGISTER 4-7:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
31:24
23:16
15:8
7:0
BMXPFMSZ<31:24>
R
R
BMXPFMSZ<23:16>
R
R
BMXPFMSZ<15:8>
R
R
BMXPFMSZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits
Static value that indicates the size of the PFM in bytes:
0x00010000 = device has 64 KB Flash
0x00020000 = device has 128 KB Flash
0x00040000 = device has 256 KB Flash
0x00080000 = device has 512 KB Flash
REGISTER 4-8:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
31:24
23:16
15:8
7:0
BMXBOOTSZ<31:24>
R
R
BMXBOOTSZ<23:16>
R
R
BMXBOOTSZ<15:8>
R
R
BMXBOOTSZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits
Static value that indicates the size of the Boot PFM in bytes:
0x00003000 = device has 12 KB Boot Flash
DS60001185B-page 92
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
PIC32MX330/350/370/430/450/470 devices contain an
5.0
FLASH PROGRAM MEMORY
internal Flash program memory for executing user
code. There are three methods by which the user can
program this memory:
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 5. “Flash
Program Memory” (DS60001121) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS60001121) in the “PIC32 Family
Reference Manual”.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32
Flash
Programming
Specification”
(DS60001145), which can be downloaded from the
Microchip web site.
Note:
On PIC32MX330/350/370/430/450/470
devices, the Flash page size is 4 KB and
the row size is 512 bytes (1024 IW and
128 IW, respectively).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 93
PIC32MX330/350/370/430/450/470
5.1
Control Registers
REGISTER 5-1:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
NVMCON: PROGRAMMING CONTROL REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
26/18/10/2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
—
R/W-0
WR
U-0
R/W-0
WREN
U-0
R-0
R-0
R-0
U-0
U-0
U-0
WRERR(1) LVDERR(1) LVDSTAT(1)
—
R/W-0
—
R/W-0
—
R/W-0
U-0
U-0
R/W-0
—
—
—
—
NVMOP<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
WR: Write Control bit
This bit is writable when WREN = 1and the unlock sequence is followed.
1= Initiate a Flash operation. Hardware clears this bit when the operation completes
0= Flash operation complete or inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable writes to WR bit and enables LVD circuit
0= Disable writes to WR bit and disables LVD circuit
This is the only bit in this register reset by a device Reset.
WRERR: Write Error bit(1)
This bit is read-only and is automatically set by hardware.
1= Program or erase sequence did not complete successfully
0= Program or erase sequence completed normally
bit 12
bit 11
LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set by hardware.
1= Low-voltage detected (possible data corruption, if WRERR is set)
0= Voltage level is acceptable for programming
LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set, and cleared, by hardware.
1= Low-voltage event active
0= Low-voltage event NOT active
bit 10-4 Unimplemented: Read as ‘0’
bit 3-0
NVMOP<3:0>: NVM Operation bits
These bits are writable when WREN = 0.
1111= Reserved
•
•
•
0111= Reserved
0110= No operation
0101= Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected
0100= Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011= Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010= No operation
0001= Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000= No operation
Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).
DS60001185B-page 94
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 5-2:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
31:24
23:16
15:8
7:0
NVMKEY<31:24>
W-0
W-0
NVMKEY<23:16>
W-0
W-0
NVMKEY<15:8>
W-0
W-0
NVMKEY<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read
Note 1: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-3:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
NVMADDR: FLASH ADDRESS REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
NVMADDR<31:24>
R/W-0
R/W-0
NVMADDR<23:16>
R/W-0
R/W-0
NVMADDR<15:8>
R/W-0
R/W-0
NVMADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: Flash Address bits
Bulk/Chip/PFM Erase: Address is ignored.
Page Erase: Address identifies the page to erase.
Row Program: Address identifies the row to program.
Word Program: Address identifies the word to program.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 95
PIC32MX330/350/370/430/450/470
REGISTER 5-4:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
NVMDATA: FLASH PROGRAM DATA REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
NVMDATA<31:24>
R/W-0
R/W-0
NVMDATA<23:16>
R/W-0
R/W-0
NVMDATA<15:8>
R/W-0
R/W-0
NVMDATA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMDATA<31:0>: Flash Programming Data bits
Note 1: The bits in this register are only reset by a Power-on Reset (POR).
REGISTER 5-5:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
NVMSRCADDR<31:24>
R/W-0
R/W-0
NVMSRCADDR<23:16>
R/W-0
R/W-0
NVMSRCADDR<15:8>
R/W-0
R/W-0
NVMSRCADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
DS60001185B-page 96
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
6.0
RESETS
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 7. “Resets”
(DS60001118) in the “PIC32 Family
Reference Manual”, which is available
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Master Clear Reset pin
• SWR: Software Reset
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• CMR: Configuration Mismatch Reset
• HVDR: High Voltage Detect Reset
from
the
Microchip
web
site
(www.microchip.com/PIC32).
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
MCLR
WDTR
Glitch Filter
Sleep or Idle
WDT
Time-out
Voltage
Regulator
Enabled
POR
Power-up
Timer
SYSRST
VDD
VDD Rise
Detect
BOR
Brown-out
Reset
Configuration
Mismatch
Reset
CMR
SWR
Brown-out
Reset
Software Reset
VCAP
HVDR
HVD Detect
and Reset
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 97
PIC32MX330/350/370/430/450/470
6.1
Control Registers
REGISTER 6-1:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
RCON: RESET CONTROL REGISTER
Bit Bit Bit
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
R/W-0
HVDR
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
—
R/W-0
—
R/W-0, HS
—
R/W-0, HS
—
R/W-0, HS
—
R/W-0, HS
—
R/W-0, HS
CMR
R/W-1, HS
BOR(1)
VREGS
R/W-1, HS
POR(1)
U-0
EXTR
SWR
—
WDTO
SLEEP
IDLE
Legend:
HS = Set by hardware
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29 HVDR: High Voltage Detect Reset Flag bit
1= High Voltage Detect (HVD) Reset has occurred
0= HVD Reset has not occurred
bit 28-10 Unimplemented: Read as ‘0’
bit 9
bit 8
bit 7
bit 6
CMR: Configuration Mismatch Reset Flag bit
1= Configuration mismatch Reset has occurred
0= Configuration mismatch Reset has not occurred
VREGS: Voltage Regulator Standby Enable bit
1= Regulator is enabled and is on during Sleep mode
0= Regulator is disabled and is off during Sleep mode
EXTR: External Reset (MCLR) Pin Flag bit
1= Master Clear (pin) Reset has occurred
0= Master Clear (pin) Reset has not occurred
SWR: Software Reset Flag bit
1= Software Reset was executed
0= Software Reset as not executed
bit 5
bit 4
Unimplemented: Read as ‘0’
WDTO: Watchdog Timer Time-out Flag bit
1= WDT Time-out has occurred
0= WDT Time-out has not occurred
bit 3
bit 2
bit 1
bit 0
SLEEP: Wake From Sleep Flag bit
1= Device was in Sleep mode
0= Device was not in Sleep mode
IDLE: Wake From Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
BOR: Brown-out Reset Flag bit(1)
1= Brown-out Reset has occurred
0= Brown-out Reset has not occurred
POR: Power-on Reset Flag bit(1)
1= Power-on Reset has occurred
0= Power-on Reset has not occurred
Note 1: User software must clear this bit to view next detection.
DS60001185B-page 98
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 6-2:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
RSWRST: SOFTWARE RESET REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
W-0, HC
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SWRST(1)
Legend:
HC = Cleared by hardware
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 31-1 Unimplemented: Read as ‘0’
bit 0
SWRST: Software Reset Trigger bit(1)
1= Enable software Reset event
0= No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 99
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 100
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The PIC32MX330/350/370/430/450/470 interrupt mod-
ule includes the following features:
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
• Up to 76 interrupt sources
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 8. “Interrupt
Controller” (DS60001108) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
• Up to 46 interrupt vectors
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Dedicated shadow set configurable for any priority level
(see the FSRSSEL<2:0> bits (DEVCFG3<18:16>) in
27.0 “Special Features” for more information)
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
PIC32MX330/350/370/430/450/470 devices generate
interrupt requests in response to interrupt events from
peripheral modules. The interrupt control module exists
externally to the CPU logic and prioritizes the interrupt
events before presenting them to the CPU.
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Vector Number
Priority Level
Interrupt Controller
CPU Core
Shadow Set Number
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 101
PIC32MX330/350/370/430/450/470
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Bit Location
Vector
#
Persistent
Interrupt
Interrupt Source(1)
IRQ #
Flag
Enable
Priority
Sub-priority
Highest Natural Order Priority
CT – Core Timer Interrupt
CS0 – Core Software Interrupt 0
CS1 – Core Software Interrupt 1
INT0 – External Interrupt
T1 – Timer1
0
0
IFS0<0>
IFS0<1>
IFS0<2>
IFS0<3>
IFS0<4>
IFS0<5>
IFS0<6>
IFS0<7>
IFS0<8>
IFS0<9>
IEC0<0>
IEC0<1>
IEC0<2>
IEC0<3>
IEC0<4>
IEC0<5>
IEC0<6>
IEC0<7>
IEC0<8>
IEC0<9>
IPC0<4:2>
IPC0<12:10>
IPC0<20:18>
IPC0<28:26>
IPC1<4:2>
IPC0<1:0>
IPC0<9:8>
No
No
1
1
2
2
IPC0<17:16>
IPC0<25:24>
IPC1<1:0>
No
3
3
No
4
4
No
IC1E – Input Capture 1 Error
IC1 – Input Capture 1
OC1 – Output Compare 1
INT1 – External Interrupt 1
T2 – Timer2
5
5
IPC1<12:10>
IPC1<12:10>
IPC1<20:18>
IPC1<28:26>
IPC2<4:2>
IPC1<9:8>
Yes
Yes
No
6
5
IPC1<9:8>
7
6
IPC1<17:16>
IPC1<25:24>
IPC2<1:0>
8
7
No
9
8
No
IC2E – Input Capture 2
IC2 – Input Capture 2
OC2 – Output Compare 2
INT2 – External Interrupt 2
T3 – Timer3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
9
IFS0<10> IEC0<10>
IFS0<11> IEC0<11>
IFS0<12> IEC0<12>
IFS0<13> IEC0<13>
IFS0<14> IEC0<14>
IFS0<15> IEC0<15>
IFS0<16> IEC0<16>
IFS0<17> IEC0<17>
IFS0<18> IEC0<18>
IFS0<19> IEC0<19>
IFS0<20> IEC0<20>
IFS0<21> IEC0<21>
IFS0<22> IEC0<22>
IFS0<23> IEC0<23>
IFS0<24> IEC0<24>
IFS0<25> IEC0<25>
IFS0<26> IEC0<26>
IFS0<27> IEC0<27>
IFS0<28> IEC0<28>
IFS0<29> IEC0<29>
IFS0<30> IEC0<30>
IFS0<31> IEC0<31>
IPC2<12:10>
IPC2<12:10>
IPC2<20:18>
IPC2<28:26>
IPC3<4:2>
IPC2<9:8>
Yes
Yes
No
9
IPC2<9:8>
10
11
12
13
13
14
15
16
17
17
18
19
20
21
21
22
23
24
25
26
27
28
29
30
30
30
31
31
31
32
32
32
33
IPC2<17:16>
IPC2<25:24>
IPC3<1:0>
No
No
IC3E – Input Capture 3
IC3 – Input Capture 3
OC3 – Output Compare 3
INT3 – External Interrupt 3
T4 – Timer4
IPC3<12:10>
IPC3<12:10>
IPC3<20:18>
IPC3<28:26>
IPC4<4:2>
IPC3<9:8>
Yes
Yes
No
IPC3<9:8>
IPC3<17:16>
IPC3<25:24>
IPC4<1:0>
No
No
IC4E – Input Capture 4 Error
IC4 – Input Capture 4
OC4 – Output Compare 4
INT4 – External Interrupt 4
T5 – Timer5
IPC4<12:10>
IPC4<12:10>
IPC4<20:18>
IPC4<28:26>
IPC5<4:2>
IPC4<9:8>
Yes
Yes
No
IPC4<9:8>
IPC4<17:16>
IPC4<25:24>
IPC5<1:0>
No
No
IC5E – Input Capture 5 Error
IC5 – Input Capture 5
OC5 – Output Compare 5
AD1 – ADC1 Convert done
FSCM – Fail-Safe Clock Monitor
IPC5<12:10>
IPC5<12:10>
IPC5<20:18>
IPC5<28:26>
IPC6<4:2>
IPC5<9:8>
Yes
Yes
No
IPC5<9:8>
IPC5<17:16>
IPC5<25:24>
IPC6<1:0>
Yes
No
RTCC – Real-Time Clock and Calendar 30
IPC6<12:10>
IPC6<20:18>
IPC6<28:26>
IPC7<4:2>
IPC6<9:8>
No
FCE – Flash Control Event
CMP1 – Comparator Interrupt
CMP2 – Comparator Interrupt
USB – USB Interrupts
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IPC6<17:16>
IPC6<25:24>
IPC7<1:0>
No
IFS1<0>
IFS1<1>
IFS1<2>
IFS1<3>
IFS1<4>
IFS1<5>
IFS1<6>
IFS1<7>
IFS1<8>
IFS1<9>
IEC1<0>
IEC1<1>
IEC1<2>
IEC1<3>
IEC1<4>
IEC1<5>
IEC1<6>
IEC1<7>
IEC1<8>
IEC1<9>
No
No
IPC7<12:10>
IPC7<20:18>
IPC7<20:18>
IPC7<20:18>
IPC7<28:26>
IPC7<28:26>
IPC7<28:26>
IPC8<4:2>
IPC7<9:8>
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SPI1E – SPI1 Fault
IPC7<17:16>
IPC7<17:16>
IPC7<17:16>
IPC7<25:24>
IPC7<25:24>
IPC7<25:24>
IPC8<1:0>
SPI1RX – SPI1 Receive Done
SPI1TX – SPI1 Transfer Done
U1E – UART1 Fault
U1RX – UART1 Receive Done
U1TX – UART1 Transfer Done
I2C1B – I2C1 Bus Collision Event
I2C1S – I2C1 Slave Event
I2C1M – I2C1 Master Event
CNA – PORTA Input Change Interrupt
IFS1<10> IEC1<10>
IFS1<11> IEC1<11>
IFS1<12> IEC1<12>
IPC8<4:2>
IPC8<1:0>
IPC8<4:2>
IPC8<1:0>
IPC8<12:10>
IPC8<9:8>
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX330/350/370/430/450/470 Controller
Family Features” for the list of available peripherals.
DS60001185B-page 102
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
Vector
#
Persistent
Interrupt
Interrupt Source(1)
IRQ #
Flag
Enable
Priority
Sub-priority
CNB – PORTB Input Change Interrupt
CNC – PORTC Input Change Interrupt
CND – PORTD Input Change Interrupt
CNE – PORTE Input Change Interrupt
CNF – PORTF Input Change Interrupt
CNG – PORTG Input Change Interrupt
PMP – Parallel Master Port
PMPE – Parallel Master Port Error
SPI2E – SPI2 Fault
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
33
33
33
33
33
33
34
34
35
35
35
36
36
36
37
37
37
38
38
38
39
39
39
40
40
40
41
42
43
44
45
IFS1<13> IEC1<13>
IFS1<14> IEC1<14>
IFS1<15> IEC1<15>
IFS1<16> IEC1<16>
IFS1<17> IEC1<17>
IFS1<18> IEC1<18>
IFS1<19> IEC1<19>
IFS1<20> IEC1<20>
IFS1<21> IEC1<21>
IFS1<22> IEC1<22>
IFS1<23> IEC1<23>
IFS1<24> IEC1<24>
IFS1<25> IEC1<25>
IFS1<26> IEC1<26>
IFS1<27> IEC1<27>
IFS1<28> IEC1<28>
IFS1<29> IEC1<29>
IFS1<30> IEC1<30>
IFS1<31> IEC1<31>
IPC8<12:10>
IPC8<12:10>
IPC8<12:10>
IPC8<12:10>
IPC8<12:10>
IPC8<12:10>
IPC8<20:18>
IPC8<20:18>
IPC8<28:26>
IPC8<28:26>
IPC8<28:26>
IPC9<4:2>
IPC8<9:8>
IPC8<9:8>
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
IPC8<9:8>
IPC8<9:8>
IPC8<9:8>
IPC8<9:8>
IPC8<17:16>
IPC8<17:16>
IPC8<25:24>
IPC8<25:24>
IPC8<25:24>
IPC9<1:0>
SPI2RX – SPI2 Receive Done
SPI2TX – SPI2 Transfer Done
U2E – UART2 Error
U2RX – UART2 Receiver
IPC9<4:2>
IPC9<1:0>
U2TX – UART2 Transmitter
I2C2B – I2C2 Bus Collision Event
I2C2S – I2C2 Slave Event
I2C2M – I2C2 Master Event
U3E – UART3 Error
IPC9<4:2>
IPC9<1:0>
IPC9<12:10>
IPC9<12:10>
IPC9<12:10>
IPC9<20:18>
IPC9<20:18>
IPC9<20:18>
IPC9<28:26>
IPC9<28:26>
IPC9<28:26>
IPC10<4:2>
IPC10<4:2>
IPC10<4:2>
IPC10<12:10>
IPC9<9:8>
IPC9<9:8>
IPC9<9:8>
IPC9<17:16>
IPC9<17:16>
IPC9<17:16>
IPC9<25:24>
IPC9<25:24>
IPC9<25:24>
IPC10<1:0>
IPC10<1:0>
IPC10<1:0>
IPC10<9:8>
U3RX – UART3 Receiver
U3TX – UART3 Transmitter
U4E – UART4 Error
IFS2<0>
IFS2<1>
IFS2<2>
IFS2<3>
IFS2<4>
IFS2<5>
IFS2<6>
IFS2<7>
IFS2<8>
IFS2<9>
IEC2<0>
IEC2<1>
IEC2<2>
IEC2<3>
IEC2<4>
IEC2<5>
IEC2<6>
IEC2<7>
IEC2<8>
IEC2<9>
U4RX – UART4 Receiver
U4TX – UART4 Transmitter
U5E – UART5 Error
U5RX – UART5 Receiver
U5TX – UART5 Transmitter
CTMU – CTMU Event
DMA0 – DMA Channel 0
IPC10<20:18> IPC10<17:16>
IPC10<28:26> IPC10<25:24>
DMA1 – DMA Channel 1
DMA2 – DMA Channel 2
IFS2<10> IEC2<10>
IFS2<11> IEC2<11> IPC11<12:10>
Lowest Natural Order Priority
IPC11<4:2>
IPC11<1:0>
IPC11<9:8>
DMA3 – DMA Channel 3
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX330/350/370/430/450/470 Controller
Family Features” for the list of available peripherals.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 103
PIC32MX330/350/370/430/450/470
7.1
Interrupts Control Registers
REGISTER 7-1:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
INTCON: INTERRUPT CONTROL REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SS0
U-0
—
U-0
—
U-0
—
R/W-0
MVEC
R/W-0
INT4EP
U-0
R/W-0
R/W-0
R/W-0
—
TPC<2:0>
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
INT3EP
INT2EP
INT1EP
INT0EP
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16 SS0: Single Vector Shadow Register Set bit
1= Single vector is presented with a shadow register set
0= Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1= Interrupt controller configured for multi vectored mode
0= Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111= Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110= Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101= Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100= Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011= Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010= Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001= Interrupts of group priority 1 start the Interrupt Proximity timer
000= Disables Interrupt Proximity timer
bit 7-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Polarity Control bit
1= Rising edge
0= Falling edge
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt 3 Edge Polarity Control bit
1= Rising edge
0= Falling edge
INT2EP: External Interrupt 2 Edge Polarity Control bit
1= Rising edge
0= Falling edge
INT1EP: External Interrupt 1 Edge Polarity Control bit
1= Rising edge
0= Falling edge
INT0EP: External Interrupt 0 Edge Polarity Control bit
1= Rising edge
0= Falling edge
DS60001185B-page 104
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 7-2:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
INTSTAT: INTERRUPT STATUS REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
SRIPL<2:0>(1)
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VEC<5:0>(1)
R/W-0
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL<2:0>: Requested Priority Level bits(1)
000-111= The priority level of the latest interrupt presented to the CPU
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
VEC<5:0>: Interrupt Vector bits(1)
00000-11111= The interrupt vector that is presented to the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-3:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
IPTMR<31:24>
R/W-0
R/W-0
IPTMR<23:16>
R/W-0
R/W-0
IPTMR<15:8>
R/W-0
R/W-0
IPTMR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 105
PIC32MX330/350/370/430/450/470
REGISTER 7-4:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
IFSx: INTERRUPT FLAG STATUS REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
IFS31
R/W-0
IFS23
R/W-0
IFS15
R/W-0
IFS7
R/W-0
IFS30
R/W-0
IFS22
R/W-0
IFS14
R/W-0
IFS6
R/W-0
IFS29
R/W-0
IFS21
R/W-0
IFS13
R/W-0
IFS5
R/W-0
IFS28
R/W-0
IFS20
R/W-0
IFS12
R/W-0
IFS4
R/W-0
IFS27
R/W-0
IFS19
R/W-0
IFS11
R/W-0
IFS3
R/W-0
IFS26
R/W-0
IFS18
R/W-0
IFS10
R/W-0
IFS2
R/W-0
IFS25
R/W-0
IFS17
R/W-0
IFS9
R/W-0
IFS1
R/W-0
IFS24
R/W-0
IFS16
R/W-0
IFS8
R/W-0
IFS0
31:24
23:16
15:8
7:0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IFS31-IFS0: Interrupt Flag Status bits
1= Interrupt request has occurred
0= No interrupt request has occurred
Note 1: This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.
REGISTER 7-5:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
R/W-0
IEC31
R/W-0
R/W-0
IEC30
R/W-0
R/W-0
IEC29
R/W-0
R/W-0
IEC28
R/W-0
R/W-0
IEC27
R/W-0
R/W-0
IEC26
R/W-0
R/W-0
IEC25
R/W-0
IEC17
R/W-0
IEC9
R/W-0
IEC1
R/W-0
IEC24
R/W-0
IEC16
R/W-0
IEC8
R/W-0
IEC0
31:24
23:16
15:8
7:0
IEC23
R/W-0
IEC22
R/W-0
IEC21
R/W-0
IEC20
R/W-0
IEC19
R/W-0
IEC18
R/W-0
IEC15
R/W-0
IEC14
R/W-0
IEC13
R/W-0
IEC12
R/W-0
IEC11
R/W-0
IEC10
R/W-0
IEC7
IEC6
IEC5
IEC4
IEC3
IEC2
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IEC31-IEC0: Interrupt Enable bits
1= Interrupt is enabled
0= Interrupt is disabled
Note 1: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.
DS60001185B-page 106
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 7-6:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit Bit Bit Bit Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
IP3<2:0>
R/W-0
IS3<1:0>
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IP2<2:0>
R/W-0
IS2<1:0>
U-0
—
U-0
—
U-0
—
R/W-0
IP1<2:0>
R/W-0
IS1<1:0>
IS0<1:0>
U-0
—
U-0
—
U-0
—
R/W-0
IP0<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP3<2:0>: Interrupt Priority bits
111= Interrupt priority is 7
•
•
•
010= Interrupt priority is 2
001= Interrupt priority is 1
000= Interrupt is disabled
bit 25-24 IS3<1:0>: Interrupt Subpriority bits
11= Interrupt subpriority is 3
10= Interrupt subpriority is 2
01= Interrupt subpriority is 1
00= Interrupt subpiority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP2<2:0>: Interrupt Priority bits
111= Interrupt priority is 7
•
•
•
010= Interrupt priority is 2
001= Interrupt priority is 1
000= Interrupt is disabled
bit 17-16 IS2<1:0>: Interrupt Subpriority bits
11= Interrupt subpriority is 3
10= Interrupt subpriority is 2
01= Interrupt subpriority is 1
00= Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’
bit 12-10 IP1<2:0>: Interrupt Priority bits
111= Interrupt priority is 7
•
•
•
010= Interrupt priority is 2
001= Interrupt priority is 1
000= Interrupt is disabled
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 107
PIC32MX330/350/370/430/450/470
REGISTER 7-6:
IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 9-8
IS1<1:0>: Interrupt Subpriority bits
11= Interrupt subpriority is 3
10= Interrupt subpriority is 2
01= Interrupt subpriority is 1
00= Interrupt subpriority is 0
bit 7-5
bit 4-2
Unimplemented: Read as ‘0’
IP0<2:0>: Interrupt Priority bits
111= Interrupt priority is 7
•
•
•
010= Interrupt priority is 2
001= Interrupt priority is 1
000= Interrupt is disabled
bit 1-0
IS0<1:0>: Interrupt Subpriority bits
11= Interrupt subpriority is 3
10= Interrupt subpriority is 2
01= Interrupt subpriority is 1
00= Interrupt subpriority is 0
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
DS60001185B-page 108
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The PIC32MX330/350/370/430/450/470 oscillator
system has the following modules and features:
8.0
OSCILLATOR
CONFIGURATION
• A Total of four external and internal oscillator
options as clock sources
Note 1: This data sheet summarizes the
features of the PIC32MX330/350/370/
430/450/470 family of devices. It is not
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-Chip user-selectable divisor postscaler on
select oscillator sources
intended to be
a
comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 6. “Oscillator Configuration”
(DS60001112) in the “PIC32 Family
Reference Manual”, which is available
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Dedicated On-Chip PLL for USB peripheral
A block diagram of the oscillator system is provided in
Figure 8-1.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 109
PIC32MX330/350/370/430/450/470
FIGURE 8-1:
PIC32MX330/350/370/430/450/470 FAMILY CLOCK DIAGRAM
(5)
USB PLL
USB Clock (48 MHz)
UFIN
div 2
div x
PLL x24
UFRCEN
UFIN 4 MHz
UPLLIDIV<2:0>
UPLLEN
ROTRIM<8:0>
(M)
REFCLKI
OE
POSC
FRC
REFCLKO
To SPI
LPRC
SOSC
PBCLK
M
512
System USB PLL
2 N + ---------
4 MHz FIN 5 MHz
SYSCLK
FIN
div x
PLL
RODIV<4:0>
(N)
ROSEL<3:0>
FPLLIDIV<2:0>
COSC<2:0>
PLLMULT<2:0>
div y
XTPLL, HSPLL,
ECPLL, FRCPLL
PLLODIV<2:0>
Primary Oscillator
(POSC)
(3)
OSC1
C1
Peripherals
Postscaler
div x
POSC (XT, HS, EC)
FRC
To Internal
Logic
(2)
F
PBCLK (TPB)
R
XTAL
(1)
P
R
Enable
(1)
S
R
PBDIV<1:0>
(3)
C2
(4)
div 16
OSC2
FRC/16
FRCDIV
div 2
To ADC
CPU and Select Peripherals
SYSCLK
FRC
Oscillator
8 MHz typical
Postscaler
FRCDIV<2:0>
TUN<5:0>
LPRC
Oscillator
LPRC
SOSC
31.25 kHz typical
Secondary Oscillator (SOSC)
SOSCO
SOSCI
32.768 kHz
SOSCEN and FSOSCEN
Clock Control Logic
FSCM INT
Fail-Safe
Clock
Monitor
FSCM Event
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0>
OSWEN
WDT, PWRT
Timer1, RTCC
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP, with a value of 1 M
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M
3. Refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual” for help in determining the
best oscillator components.
4. PBCLK out is available on the OSC2 pin in certain clock modes.
5. USB PLL is available on PIC32MX4XX devices only.
DS60001185B-page 110
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
8.1
Control Registers
REGISTER 8-1:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
OSCCON: OSCILLATOR CONTROL REGISTER
Bit Bit Bit Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
R/W-y
R/W-y
PLLODIV<2:0>
R/W-y
R/W-y
R/W-0
R/W-y
R/W-y
R/W-0
FRCDIV<2:0>
R/W-y
R/W-1
R/W-y
R/W-y
31:24
23:16
15:8
7:0
—
U-0
—
—
R-0
R-1
R/W-y
SOSCRDY PBDIVRDY
PBDIV<1:0>
R-0
PLLMULT<2:0>
R/W-y
U-0
R-0
R-0
COSC<2:0>
R-0
U-0
—
R/W-0
—
R/W-0
CF
NOSC<2:0>
R/W-y
R-0
R/W-0
R/W-0
UFRCEN(1)
R/W-0
CLKLOCK ULOCK(1)
SLOCK
SLPEN
SOSCEN
OSWEN
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV<2:0>: Output Divider for PLL
111= PLL output divided by 256
110= PLL output divided by 64
101= PLL output divided by 32
100= PLL output divided by 16
011= PLL output divided by 8
010= PLL output divided by 4
001= PLL output divided by 2
000= PLL output divided by 1
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111= FRC divided by 256
110= FRC divided by 64
101= FRC divided by 32
100= FRC divided by 16
011= FRC divided by 8
010= FRC divided by 4
001= FRC divided by 2 (default setting)
000= FRC divided by 1
bit 23
bit 22
Unimplemented: Read as ‘0’
SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1= Indicates that the Secondary Oscillator is running and is stable
0= Secondary Oscillator is still warming up or is turned off
bit 21
PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1= PBDIV<1:0> bits can be written
0= PBDIV<1:0> bits cannot be written
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits
11= PBCLK is SYSCLK divided by 8 (default)
10= PBCLK is SYSCLK divided by 4
01= PBCLK is SYSCLK divided by 2
00= PBCLK is SYSCLK divided by 1
Note 1: This bit is available on PIC32MX4XX devices only.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 111
PIC32MX330/350/370/430/450/470
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits
111= Clock is multiplied by 24
110= Clock is multiplied by 21
101= Clock is multiplied by 20
100= Clock is multiplied by 19
011= Clock is multiplied by 18
010= Clock is multiplied by 17
001= Clock is multiplied by 16
000= Clock is multiplied by 15
bit 15
Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111= Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits
110= Internal Fast RC (FRC) Oscillator divided by 16
101= Internal Low-Power RC (LPRC) Oscillator
100= Secondary Oscillator (SOSC)
011= Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)
010= Primary Oscillator (POSC) (XT, HS or EC)
001= Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000= Internal Fast RC (FRC) Oscillator
bit 11
Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
111= Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits
110= Internal Fast RC Oscillator (FRC) divided by 16
101= Internal Low-Power RC (LPRC) Oscillator
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010= Primary Oscillator (XT, HS or EC)
001= Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000= Internal Fast Internal RC Oscillator (FRC)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
bit 7
CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):
1= Clock and PLL selections are locked
0= Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):
Clock and PLL selections are never locked and may be modified.
bit 6
ULOCK: USB PLL Lock Status bit(1)
1= Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0= Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
bit 5
bit 4
SLOCK: PLL Lock Status bit
1= PLL module is in lock or PLL module start-up timer is satisfied
0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled
SLPEN: Sleep Mode Enable bit
1= Device will enter Sleep mode when a WAITinstruction is executed
0= Device will enter Idle mode when a WAITinstruction is executed
Note 1: This bit is available on PIC32MX4XX devices only.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001185B-page 112
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 3
bit 2
bit 1
bit 0
CF: Clock Fail Detect bit
1= FSCM has detected a clock failure
0= No clock failure has been detected
UFRCEN: USB FRC Clock Enable bit(1)
1= Enable FRC as the clock source for the USB clock source
0= Use the Primary Oscillator or USB PLL as the USB clock source
SOSCEN: Secondary Oscillator (SOSC) Enable bit
1= Enable Secondary Oscillator
0= Disable Secondary Oscillator
OSWEN: Oscillator Switch Enable bit
1= Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: This bit is available on PIC32MX4XX devices only.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 113
PIC32MX330/350/370/430/450/470
REGISTER 8-2:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
OSCTUN: FRC TUNING REGISTER
Bit Bit Bit
Bit
Bit
Bit
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
—
R-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-6 Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits(1)
100000= Center frequency -12.5%
100001=
•
•
•
111111=
000000= Center frequency. Oscillator runs at minimal frequency (8 MHz)
000001=
•
•
•
011110=
011111= Center frequency +12.5%
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note:
Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
DS60001185B-page 114
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 8-3:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
24/16/8/0
25/17/9/1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
RODIV<14:8>(3)
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV<7:0>(3)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
RSLP(2)
ON
—
SIDL
OE
—
DIVSWEN
ACTIVE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ROSEL<3:0>(1)
—
—
—
—
Legend:
HC = Hardware Clearable HS = Hardware Settable
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-16 RODIV<14:0>: Reference Clock Divider bits(1)
This value selects the Reference Clock Divider bits. See Figure 8-1 for more information.
bit 15
ON: Output Enable bit
1= Reference Oscillator Module enabled
0= Reference Oscillator Module disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Peripheral Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
OE: Reference Clock Output Enable bit
1= Reference clock is driven out on REFCLKO pin
0= Reference clock is not driven out on REFCLKO pin
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1= Reference Oscillator Module output continues to run in Sleep
0= Reference Oscillator Module output is disabled in Sleep
bit 10
bit 9
Unimplemented: Read as ‘0’
DIVSWEN: Divider Switch Enable bit
1= Divider switch is in progress
0= Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit
1= Reference clock request is active
0= Reference clock request is not active
bit 7-4
Unimplemented: Read as ‘0’
Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
2: This bit is ignored when the ROSEL<3:0> bits = 0000or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 115
PIC32MX330/350/370/430/450/470
REGISTER 8-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 3-0
ROSEL<3:0>: Reference Clock Source Select bits(1)
1111= Reserved; do not use
•
•
•
1001= Reserved; do not use
1000= REFCLKI
0111= System PLL output
0110= USB PLL output
0101= SOSC
0100= LPRC
0011= FRC
0010= POSC
0001= PBCLK
0000= SYSCLK
Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
2: This bit is ignored when the ROSEL<3:0> bits = 0000or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to ‘1’.
DS60001185B-page 116
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 8-4:
REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
ROTRIM<8:1>
R/W-0
U-0
—
U-0
—
U-0
U-0
U-0
—
U-0
—
U-0
—
ROTRIM<0>
—
—
U-0
U-0
U-0
U-0
—
U-0
—
U-0
U-0
U-0
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
—
U-0
—
U-0
—
—
—
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits
111111111= 511/512 divisor added to RODIV value
111111110= 510/512 divisor added to RODIV value
•
•
•
100000000= 256/512 divisor added to RODIV value
•
•
•
000000010= 2/512 divisor added to RODIV value
000000001= 1/512 divisor added to RODIV value
000000000= 0/512 divisor added to RODIV value
bit 22-0 Unimplemented: Read as ‘0’
Note 1: While the ON bit (REFOCON<15>) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is
also set to ‘1’.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 117
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 118
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Prefetch cache increases performance for applications
9.0
PREFETCH CACHE
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 4. “Prefetch
Cache” (DS60001119) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
9.1
Features
• 16 fully associative lockable cache lines
• 16-byte cache lines
• Up to four cache lines allocated to data
• Two cache lines with address mask to hold
repeated instructions
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Pseudo LRU replacement policy
• All cache lines are software writable
• 16-byte parallel memory fetch
• Predictive instruction prefetch
A simplified block diagram of the Prefetch Cache
module is illustrated in Figure 9-1.
FIGURE 9-1:
PREFETCH CACHE MODULE BLOCK DIAGRAM
CTRL
FSM
Cache Line
Tag Logic
CTRL
Bus Control
Cache Control
Prefetch Control
Hit LRU
Cache
Line
Address
Encode
RDATA
Miss LRU
Hit Logic
Prefetch
Prefetch
RDATA
CTRL
PFM
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 119
PIC32MX330/350/370/430/450/470
9.2
Control Registers
REGISTER 9-1:
CHECON: CACHE CONTROL REGISTER
Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Range
Bit
Bit
Bit
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/W-0
—
CHECOH
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
DCSZ<1:0>
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
PREFEN<1:0>
PFMWS<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Write ‘0’; ignore read
bit 16
CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1= Invalidate all data and instruction lines
0= Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Write ‘0’; ignore read
bit 9-8
DCSZ<1:0>: Data Cache Size in Lines bits
11= Enable data caching with a size of 4 Lines
10= Enable data caching with a size of 2 Lines
01= Enable data caching with a size of 1 Line
00= Disable data caching
Changing these bits induce all lines to be reinitialized to the “invalid” state.
bit 7-6
bit 5-4
Unimplemented: Write ‘0’; ignore read
PREFEN<1:0>: Predictive Prefetch Enable bits
11= Enable predictive prefetch for both cacheable and non-cacheable regions
10= Enable predictive prefetch for non-cacheable regions only
01= Enable predictive prefetch for cacheable regions only
00= Disable predictive prefetch
bit 3
Unimplemented: Write ‘0’; ignore read
bit 2-0
PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits
111= Seven Wait states
110= Six Wait states
101= Five Wait states
100= Four Wait states
011= Three Wait states
010= Two Wait states
001= One Wait state
000= Zero Wait state
DS60001185B-page 120
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 9-2:
Bit Bit
CHEACC: CACHE ACCESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
CHEWEN
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
23:16
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
15:8
—
U-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
7:0
—
CHEIDX<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
CHEWEN: Cache Access Enable bits for registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and
CHEW3
1= The cache line selected by CHEIDX<3:0> is writeable
0= The cache line selected by CHEIDX<3:0> is not writeable
bit 30-4 Unimplemented: Write ‘0’; ignore read
bit 3-0 CHEIDX<3:0>: Cache Line Index bits
The value selects the cache line for reading or writing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 121
PIC32MX330/350/370/430/450/470
REGISTER 9-3:
CHETAG: CACHE TAG REGISTER
Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Range
Bit
Bit
Bit
Bit
Bit
24/16/8/0
R/W-0
LTAGBOOT
R/W-x
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
LTAG<19:12>
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
LTAG<11:4>
R/W-x
R/W-0
R/W-0
R/W-1
U-0
LTAG<3:0>
LVALID
LLOCK
LTYPE
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
LTAGBOOT: Line TAG Address Boot bit
1= The line is in the 0x1D000000 (physical) area of memory
0= The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Write ‘0’; ignore read
bit 23-4 LTAG<19:0>: Line TAG Address bits
LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range and
position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,
(system) physical addresses, and PFM physical addresses.
bit 3
bit 2
bit 1
bit 0
LVALID: Line Valid bit
1= The line is valid and is compared to the physical address for hit detection
0= The line is not valid and is not compared to the physical address for hit detection
LLOCK: Line Lock bit
1= The line is locked and will not be replaced
0= The line is not locked and can be replaced
LTYPE: Line Type bit
1= The line caches instruction words
0= The line caches data words
Unimplemented: Write ‘0’; ignore read
DS60001185B-page 122
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 9-4:
CHEMSK: CACHE TAG MASK REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LMASK<10:3>
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
LMASK<2:0>
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Write ‘0’; ignore read
bit 15-5 LMASK<10:0>: Line Mask bits
1= Enables mask logic to force a match on the corresponding bit position in LTAG<19:0> bits
(CHETAG<23:4>) and the physical address.
0= Only writeable for values of CHEIDX<3:0> bits (CHEACC<3:0>) equal to 0x0A and 0x0B.
Disables mask logic.
bit 4-0
Unimplemented: Write ‘0’; ignore read
REGISTER 9-5:
Bit Bit
CHEW0: CACHE WORD 0
Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
Range 31/23/15/7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEW0<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEW0<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEW0<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEW0<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 123
PIC32MX330/350/370/430/450/470
REGISTER 9-6:
Bit Bit
CHEW1: CACHE WORD 1
Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
Range 31/23/15/7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEW1<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEW1<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEW1<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEW1<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
REGISTER 9-7:
Bit Bit
CHEW2: CACHE WORD 2
Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Bit
Bit
Bit
Bit
24/16/8/0
Range 31/23/15/7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEW2<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEW2<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEW2<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEW2<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
DS60001185B-page 124
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 9-8:
Bit Bit
CHEW3: CACHE WORD 3
Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
Range 31/23/15/7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEW3<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEW3<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEW3<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEW3<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
Note:
This register is a window into the cache data array and is readable only if the device is not code-protected.
REGISTER 9-9:
Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
CHELRU: CACHE LRU REGISTER
Bit Bit Bit
Bit
Bit
Bit
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
CHELRU<24>
R-0
31:24
23:16
15:8
7:0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU<23:16>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU<15:8>
R-0
R-0
CHELRU<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Write ‘0’; ignore read
bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits
Indicates the pseudo-LRU state of the cache.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 125
PIC32MX330/350/370/430/450/470
REGISTER 9-10: CHEHIT: CACHE HIT STATISTICS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEHIT<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEHIT<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEHIT<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEHIT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEHIT<31:0>: Cache Hit Count bits
Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a
cacheable region. Non-cacheable accesses do not modify this value.
REGISTER 9-11: CHEMIS: CACHE MISS STATISTICS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEMIS<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEMIS<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEMIS<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEMIS<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEMIS<31:0>: Cache Miss Count bits
Incremented each time the processor issues an instruction fetch from a cacheable region that misses the
prefetch cache. Non-cacheable accesses do not modify this value.
DS60001185B-page 126
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 9-12: CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
CHEPFABT<31:24>
R/W-x
R/W-x
R/W-x
23:16
CHEPFABT<23:16>
R/W-x
R/W-x
R/W-x
15:8
CHEPFABT<15:8>
R/W-x
R/W-x
R/W-x
7:0
CHEPFABT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits
Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load
or store.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 127
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 128
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
• Automatic word-size detection:
10.0 DIRECT MEMORY ACCESS
- Transfer granularity, down to byte level
(DMA) CONTROLLER
- Bytes need not be word-aligned at source
and destination
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS60001117) in the “PIC32 Family
Reference Manual”, which is available
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA requests:
from
the
Microchip
web
site
- A DMA request can be selected from any of
the peripheral interrupt sources
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as Peripheral Bus (PBUS) devices: SPI, UART, PMP,
etc.) or memory itself.
- Destination full or half full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA debug support features:
Following are some of the key features of the DMA
controller module:
- Most recent address accessed by a DMA
channel
• Four identical channels, each featuring:
- Auto-increment source and destination
address registers
- Most recent DMA channel to transfer data
• CRC Generation module:
- Source and destination pointers
- CRC module can be assigned to any of the
available channels
- Memory to memory and memory to
peripheral transfers
- CRC module is highly configurable
FIGURE 10-1:
DMA BLOCK DIAGRAM
INT Controller
System IRQ
Peripheral Bus
Address Decoder
Channel 0 Control
Channel 1 Control
I
0
I
I
Device Bus + Bus Arbitration
Y
Bus Interface
1
2
I
Global Control
(DMACON)
Channel n Control
n
Channel Priority
Arbitration
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 129
PIC32MX330/350/370/430/450/470
10.1 Control Registers
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
27/19/11/3
26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
U-0
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
SUSPEND DMABUSY
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: DMA On bit(1)
1= DMA module is enabled
0= DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12
SUSPEND: DMA Suspend bit
1= DMA transfers are suspended to allow CPU uninterrupted access to data bus
0= DMA operates normally
bit 11
DMABUSY: DMA Module Busy bit(4)
1= DMA module is active
0= DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 130
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-2: DMASTAT: DMA STATUS REGISTER
Bit Bit Bit Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Bit
Bit
Bit
24/16/8/0
Range 31/23/15/7
U-0
U-0
U-0
U-0
U-0
—
U-0
U-0
U-0
31:24
—
—
—
—
—
—
—
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
U-0
—
23:16
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
15:8
—
—
—
—
—
—
—
R-0
—
U-0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
7:0
—
RDWR
DMACH<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
RDWR: Read/Write Status bit
1= Last DMA bus access was a read
0= Last DMA bus access was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
DMAADDR<31:24>
R-0
R-0
R-0
23:16
DMAADDR<23:16>
R-0
R-0
R-0
15:8
DMAADDR<15:8>
R-0
R-0
R-0
7:0
DMAADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DMAADDR<31:0>: DMA Module Address bits
These bits contain the address of the most recent DMA access.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 131
PIC32MX330/350/370/430/450/470
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WBO(1)
U-0
U-0
—
U-0
—
R/W-0
BITO
U-0
31:24
23:16
15:8
7:0
BYTO<1:0>
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
—
U-0
R/W-0
R/W-0
R/W-0
PLEN<4:0>
R/W-0
R/W-0
R/W-0
—
—
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
CRCEN
CRCAPP(1) CRCTYP
—
—
CRCCH<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
11= Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10= Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01= Endian byte swap on word boundaries (i.e., reverse source byte order)
00= No swapping (i.e., source byte order)
bit 27
WBO: CRC Write Byte Order Selection bit(1)
1= Source data is written to the destination re-ordered as defined by BYTO<1:0>
0= Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
BITO: CRC Bit Order Selection bit(4)
When CRCTYP (DCRCCON<15>) = 1(CRC module is in IP Header mode):
1= The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0= The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON<15>) = 0(CRC module is in LFSR mode):
1= The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0= The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8 PLEN<4:0>: Polynomial Length bits(1)
When CRCTYP (DCRCCON<15>) = 1(CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0(CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7
CRCEN: CRC Enable bit
1= CRC module is enabled and channel transfers are routed through the CRC module
0= CRC module is disabled and channel transfers proceed normally
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
DS60001185B-page 132
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6
CRCAPP: CRC Append Mode bit(1)
1= The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0= The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5
CRCTYP: CRC Type Selection bit
1= The CRC module will calculate an IP header checksum
0= The CRC module will calculate a LFSR CRC
bit 4-3
bit 2-0
Unimplemented: Read as ‘0’
CRCCH<2:0>: CRC Channel Select bits
111= CRC is assigned to Channel 7
110= CRC is assigned to Channel 6
101= CRC is assigned to Channel 5
100= CRC is assigned to Channel 4
011= CRC is assigned to Channel 3
010= CRC is assigned to Channel 2
001= CRC is assigned to Channel 1
000= CRC is assigned to Channel 0
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 133
PIC32MX330/350/370/430/450/470
REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
DCRCDATA<31:24>
R/W-0
R/W-0
R/W-0
23:16
DCRCDATA<23:16>
R/W-0
R/W-0
R/W-0
15:8
DCRCDATA<15:8>
R/W-0
R/W-0
R/W-0
7:0
DCRCDATA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1(CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0(CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 10-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
DCRCXOR<31:24>
R/W-0
R/W-0
R/W-0
23:16
DCRCXOR<23:16>
R/W-0
R/W-0
R/W-0
15:8
DCRCXOR<15:8>
R/W-0
R/W-0
R/W-0
7:0
DCRCXOR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
When CRCTYP (DCRCCON<15>) = 1(CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON<15>) = 0(CRC module is in LFSR mode):
1= Enable the XOR input to the Shift register
0= Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
DS60001185B-page 134
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
CHBUSY
R/W-0
CHEN(2)
U-0
U-0
U-0
U-0
—
U-0
U-0
—
R/W-0
CHCHNS(1)
R/W-0
—
—
—
—
R/W-0
R/W-0
R/W-0
U-0
R-0
R/W-0
CHAED
CHCHN
CHAEN
—
CHEDET
CHPRI<1:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
CHBUSY: Channel Busy bit
1= Channel is active or has been enabled
0= Channel is inactive or has been disabled
bit 14-9 Unimplemented: Read as ‘0’
bit 8
bit 7
bit 6
bit
CHCHNS: Chain Channel Selection bit(1)
1= Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0= Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
CHEN: Channel Enable bit(2)
1= Channel is enabled
0= Channel is disabled
CHAED: Channel Allow Events If Disabled bit
1= Channel start/abort events will be registered, even if the channel is disabled
0= Channel start/abort events will be ignored if the channel is disabled
CHCHN: Channel Chain Enable bit
1= Allow channel to be chained
0= Do not allow channel to be chained
bit 4
CHAEN: Channel Automatic Enable bit
1= Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0= Channel is disabled on block transfer complete
bit 3
bit 2
Unimplemented: Read as ‘0’
CHEDET: Channel Event Detected bit
1= An event has been detected
0= No events have been detected
bit 1-0
CHPRI<1:0>: Channel Priority bits
11= Channel has priority 3 (highest)
10= Channel has priority 2
01= Channel has priority 1
00= Channel has priority 0
Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 135
PIC32MX330/350/370/430/450/470
REGISTER 10-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ<7:0>(1)
R/W-1
CHSIRQ<7:0>(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
S = Settable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)
11111111= Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
00000001= Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000= Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)
11111111= Interrupt 255 will initiate a DMA transfer
•
•
•
00000001= Interrupt 1 will initiate a DMA transfer
00000000= Interrupt 0 will initiate a DMA transfer
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CFORCE: DMA Forced Transfer bit
1= A DMA transfer is forced to begin when this bit is written to a ‘1’
0= This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1= A DMA transfer is aborted when this bit is written to a ‘1’
0= This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1= Abort transfer and clear CHEN on pattern match
0= Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1= Start channel cell transfer if an interrupt matching CHSIRQ occurs
0= Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1= Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0= Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
DS60001185B-page 136
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
R/W-0
CHSDIE
U-0
R/W-0
CHSHIE
U-0
R/W-0
CHDDIE
U-0
R/W-0
CHDHIE
U-0
R/W-0
CHBCIE
U-0
R/W-0
CHCCIE
U-0
R/W-0
CHTAIE
U-0
R/W-0
CHERIE
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
CHSDIE: Channel Source Done Interrupt Enable bit
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
1= Interrupt is enabled
0= Interrupt is disabled
CHSHIE: Channel Source Half Empty Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHDDIE: Channel Destination Done Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHDHIE: Channel Destination Half Full Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHTAIE: Channel Transfer Abort Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
CHERIE: Channel Address Error Interrupt Enable bit
1= Interrupt is enabled
0= Interrupt is disabled
bit 15-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
CHSDIF: Channel Source Done Interrupt Flag bit
1= Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0= No interrupt is pending
CHSHIF: Channel Source Half Empty Interrupt Flag bit
1= Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0= No interrupt is pending
CHDDIF: Channel Destination Done Interrupt Flag bit
1= Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0= No interrupt is pending
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 137
PIC32MX330/350/370/430/450/470
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)
bit 4
CHDHIF: Channel Destination Half Full Interrupt Flag bit
1= Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0= No interrupt is pending
bit 3
CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1= A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0= No interrupt is pending
bit 2
bit 1
bit 0
CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1= A cell transfer has been completed (CHCSIZ bytes have been transferred)
0= No interrupt is pending
CHTAIF: Channel Transfer Abort Interrupt Flag bit
1= An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0= No interrupt is pending
CHERIF: Channel Address Error Interrupt Flag bit
1= A channel address error has been detected
Either the source or the destination address is invalid.
0= No interrupt is pending
DS60001185B-page 138
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
CHSSA<31:24>
R/W-0
R/W-0
CHSSA<23:16>
R/W-0
R/W-0
CHSSA<15:8>
R/W-0
R/W-0
CHSSA<7:0>
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 31-0
CHSSA<31:0> Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
CHDSA<31:24>
R/W-0
R/W-0
R/W-0
23:16
CHDSA<23:16>
R/W-0
R/W-0
R/W-0
15:8
CHDSA<15:8>
R/W-0
R/W-0
R/W-0
7:0
CHDSA<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits
Channel destination start address.
Note: This must be the physical address of the destination.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 139
PIC32MX330/350/370/430/450/470
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSSIZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSSIZ<15:0>: Channel Source Size bits
1111111111111111= 65,535 byte source size
•
•
•
0000000000000010= 2 byte source size
0000000000000001= 1 byte source size
0000000000000000= 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHDSIZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010= 2 byte destination size
0000000000000001= 1 byte destination size
0000000000000000= 65,536 byte destination size
DS60001185B-page 140
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHSPTR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits
1111111111111111= Points to byte 65,535 of the source
•
•
•
0000000000000001= Points to byte 1 of the source
0000000000000000= Points to byte 0 of the source
Note 1: When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHDPTR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits
1111111111111111= Points to byte 65,535 of the destination
•
•
•
0000000000000001= Points to byte 1 of the destination
0000000000000000= Points to byte 0 of the destination
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 141
PIC32MX330/350/370/430/450/470
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHCSIZ<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111= 65,535 bytes transferred on an event
•
•
•
0000000000000010= 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000= 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR<15:8>
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHCPTR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits
1111111111111111= 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001= 1 byte has been transferred since the last event
0000000000000000= 0 bytes have been transferred since the last event
Note 1: When in Pattern Detect mode, this register is reset on a pattern detect.
DS60001185B-page 142
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Bit
24/16/8/0
Range 31/23/15/7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
—
—
—
—
—
—
—
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
23:16
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
15:8
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7:0
CHPDAT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 CHPDAT<7:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 143
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 144
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The clock generator provides the 48 MHz clock
11.0 USB ON-THE-GO (OTG)
required for USB full-speed and low-speed communi-
cation. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 27. “USB
On-The-Go (OTG)” (DS60001126) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC32 USB module includes the following
features:
• USB Full-speed support for host and device
• Low-speed host support
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded host, full-speed
device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
• USB OTG support
• Integrated signaling resistors
• Integrated analog comparators for VBUS
monitoring
• Integrated USB transceiver
• Transaction handshaking performed by hardware
• Endpoint buffering anywhere in system RAM
• Integrated DMA to access system RAM and Flash
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA control-
ler, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG
module is presented in Figure 11-1.
Note:
The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible
for
investigating
and
satisfying any applicable licensing
obligations.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 145
PIC32MX330/350/370/430/450/470
FIGURE 11-1:
PIC32MX430/450/470 USB INTERFACE DIAGRAM
USBEN
FRC
USB Suspend
Oscillator
8 MHz Typical
CPU Clock Not POSC
Sleep
TUN<5:0>(4)
Primary Oscillator
(POSC)
(5)
UFIN
PLL
Div x
Div 2
UFRCEN(3)
OSC1
UPLLEN(6)
UPLLIDIV(6)
USB Suspend
To Clock Generator for Core and Peripherals
Sleep or Idle
OSC2
(PB Out)(1)
USB Module
USB
SRP Charge
SRP Discharge
Voltage
Bus
Comparators
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
D-(2)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(8)
(8)
VBUSON
Transceiver Power 3.3V
VUSB3V3
Note 1: PB clock is only available on this pin for select EC modes.
2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.
DS60001185B-page 146
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
11.1 Control Registers
REGISTER 11-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
U-0
U-0
—
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
U-0
—
R/WC-0, HS
IDIF
T1MSECIF LSTATEIF
ACTVIF
SESVDIF SESENDIF
VBUSVDIF
Legend:
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IDIF: ID State Change Indicator bit
1= Change in ID state detected
0= No change in ID state detected
T1MSECIF: 1 Millisecond Timer bit
1= 1 millisecond timer has expired
0= 1 millisecond timer has not expired
LSTATEIF: Line State Stable Indicator bit
1= USB line state has been stable for 1 ms, but different from last time
0= USB line state has not been stable for 1 ms
ACTVIF: Bus Activity Indicator bit
1= Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0= Activity has not been detected
SESVDIF: Session Valid Change Indicator bit
1= VBUS voltage has dropped below the session end level
0= VBUS voltage has not dropped below the session end level
SESENDIF: B-Device VBUS Change Indicator bit
1= A change on the session end input was detected
0= No change on the session end input was detected
bit 1
bit 0
Unimplemented: Read as ‘0’
VBUSVDIF: A-Device VBUS Change Indicator bit
1= Change on the session valid input detected
0= No change on the session valid input detected
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 147
PIC32MX330/350/370/430/450/470
REGISTER 11-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
—
U-0
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
—
R/W-0
IDIE
R/W-0
R/W-0
R/W-0
ACTVIE
R/W-0
R/W-0
U-0
—
R/W-0
VBUSVDIE
T1MSECIE LSTATEIE
SESVDIE SESENDIE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IDIE: ID Interrupt Enable bit
1= ID interrupt enabled
0= ID interrupt disabled
T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1= 1 millisecond timer interrupt enabled
0= 1 millisecond timer interrupt disabled
LSTATEIE: Line State Interrupt Enable bit
1= Line state interrupt enabled
0= Line state interrupt disabled
ACTVIE: Bus Activity Interrupt Enable bit
1= ACTIVITY interrupt enabled
0= ACTIVITY interrupt disabled
SESVDIE: Session Valid Interrupt Enable bit
1= Session valid interrupt enabled
0= Session valid interrupt disabled
SESENDIE: B-Session End Interrupt Enable bit
1= B-session end interrupt enabled
0= B-session end interrupt disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1= A-VBUS valid interrupt enabled
0= A-VBUS valid interrupt disabled
DS60001185B-page 148
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-3: U1OTGSTAT: USB OTG STATUS REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
—
U-0
U-0
—
U-0
—
U-0
U-0
—
31:24
23:16
15:8
7:0
—
—
—
—
U-0
—
U-0
—
U-0
U-0
—
U-0
U-0
U-0
—
U-0
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
ID
U-0
—
R-0
U-0
—
R-0
R-0
U-0
—
R-0
LSTATE
SESVD
SESEND
VBUSVD
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
ID: ID Pin State Indicator bit
1= No cable is attached or a type B cable has been plugged into the USB receptacle
0= A “type A” OTG cable has been plugged into the USB receptacle
bit 6
bit 5
Unimplemented: Read as ‘0’
LSTATE: Line State Stable Indicator bit
1= USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms
0= USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms
bit 4
bit 3
Unimplemented: Read as ‘0’
SESVD: Session Valid Indicator bit
1= VBUS voltage is above Session Valid on the A or B device
0= VBUS voltage is below Session Valid on the A or B device
bit 2
SESEND: B-Device Session End Indicator bit
1= VBUS voltage is below Session Valid on the B device
0= VBUS voltage is above Session Valid on the B device
bit 1
bit 0
Unimplemented: Read as ‘0’
VBUSVD: A-Device VBUS Valid Indicator bit
1= VBUS voltage is above Session Valid on the A device
0= VBUS voltage is below Session Valid on the A device
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 149
PIC32MX330/350/370/430/450/470
REGISTER 11-4: U1OTGCON: USB OTG CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5
28/20/12/4
27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OTGEN
R/W-0
R/W-0
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
VBUSCHG VBUSDIS
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DPPULUP: D+ Pull-Up Enable bit
1= D+ data line pull-up resistor is enabled
0= D+ data line pull-up resistor is disabled
DMPULUP: D- Pull-Up Enable bit
1= D- data line pull-up resistor is enabled
0= D- data line pull-up resistor is disabled
DPPULDWN: D+ Pull-Down Enable bit
1= D+ data line pull-down resistor is enabled
0= D+ data line pull-down resistor is disabled
DMPULDWN: D- Pull-Down Enable bit
1= D- data line pull-down resistor is enabled
0= D- data line pull-down resistor is disabled
VBUSON: VBUS Power-on bit
1= VBUS line is powered
0= VBUS line is not powered
OTGEN: OTG Functionality Enable bit
1= DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
0= DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
VBUSCHG: VBUS Charge Enable bit
1= VBUS line is charged through a pull-up resistor
0= VBUS line is not charged through a resistor
VBUSDIS: VBUS Discharge Enable bit
1= VBUS line is discharged through a pull-down resistor
0= VBUS line is not discharged through a resistor
DS60001185B-page 150
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
R-0
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
UACTPND
USLPGRD USBBUSY
USUSPEND USBPWR
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 UACTPND: USB Activity Pending bit
1= USB bus activity has been detected; but an interrupt is pending, it has not been generated yet
0= An interrupt is not pending
bit 6-5 Unimplemented: Read as ‘0’
bit 4
USLPGRD: USB Sleep Entry Guard bit
1= Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0= USB module does not block Sleep entry
bit 3
USBBUSY: USB Module Busy bit(1)
1= USB module is active or disabled, but not ready to be enabled
0= USB module is not active and is ready to be enabled
Note: When USBPWR = 0and USBBUSY = 1, status from all other registers is invalid and writes to all
USB module registers produce undefined results.
bit 2
bit 1
Unimplemented: Read as ‘0’
USUSPEND: USB Suspend Mode bit
1= USB module is placed in Suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0= USB module operates normally
bit 0
USBPWR: USB Operation Enable bit
1= USB module is turned on
0= USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 151
PIC32MX330/350/370/430/450/470
REGISTER 11-6: U1IR: USB INTERRUPT REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
29/21/13/5
28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
31:24
23:16
15:8
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R-0
R/WC-0, HS
(5)
URSTIF
7:0
STALLIF ATTACHIF(1) RESUMEIF(2)
IDLEIF
TRNIF(3)
SOFIF
UERRIF(4)
(6)
DETACHIF
Legend:
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIF: STALL Handshake Interrupt bit
1= In Host mode a STALL handshake was received during the handshake phase of the transaction
In Device mode a STALL handshake was transmitted during the handshake phase of the transaction
0= STALL handshake has not been sent
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
ATTACHIF: Peripheral Attach Interrupt bit(1)
1= Peripheral attachment was detected by the USB module
0= Peripheral attachment was not detected
RESUMEIF: Resume Interrupt bit(2)
1= K-State is observed on the D+ or D- pin for 2.5 µs
0= K-State is not observed
IDLEIF: Idle Detect Interrupt bit
1= Idle condition detected (constant Idle state of 3 ms or more)
0= No Idle condition detected
TRNIF: Token Processing Complete Interrupt bit(3)
1= Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0= Processing of current token not complete
SOFIF: SOF Token Interrupt bit
1= SOF token received by the peripheral or the SOF threshold reached by the host
0= SOF token was not received nor threshold reached
UERRIF: USB Error Condition Interrupt bit(4)
1= Unmasked error condition has occurred
0= Unmasked error condition has not occurred
URSTIF: USB Reset Interrupt bit (Device mode)(5)
1= Valid USB Reset has occurred
0= No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)(6)
1= Peripheral detachment was detected by the USB module
0= Peripheral detachment was not detected
Note 1: This bit is valid only if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.
DS60001185B-page 152
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Bit
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
31:24
23:16
15:8
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URSTIE(2)
7:0
STALLIE
ATTACHIE RESUMEIE
IDLEIE
TRNIE
SOFIE
UERRIE(1)
(3)
DETACHIE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STALLIE: STALL Handshake Interrupt Enable bit
1= STALL interrupt enabled
0= STALL interrupt disabled
ATTACHIE: ATTACH Interrupt Enable bit
1= ATTACH interrupt enabled
0= ATTACH interrupt disabled
RESUMEIE: RESUME Interrupt Enable bit
1= RESUME interrupt enabled
0= RESUME interrupt disabled
IDLEIE: Idle Detect Interrupt Enable bit
1= Idle interrupt enabled
0= Idle interrupt disabled
TRNIE: Token Processing Complete Interrupt Enable bit
1= TRNIF interrupt enabled
0= TRNIF interrupt disabled
SOFIE: SOF Token Interrupt Enable bit
1= SOFIF interrupt enabled
0= SOFIF interrupt disabled
UERRIE: USB Error Interrupt Enable bit(1)
1= USB Error interrupt enabled
0= USB Error interrupt disabled
URSTIE: USB Reset Interrupt Enable bit(2)
1= URSTIF interrupt enabled
0= URSTIF interrupt disabled
DETACHIE: USB Detach Interrupt Enable bit(3)
1= DATTCHIF interrupt enabled
0= DATTCHIF interrupt disabled
Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
2: Device mode.
3: Host mode.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 153
PIC32MX330/350/370/430/450/470
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
CRC5EF(4)
R/WC-0, HS
7:0
BTSEF
BMXEF
DMAEF(1)
BTOEF(2)
DFN8EF
CRC16EF
PIDEF
EOFEF(3,5)
Legend:
WC = Write ‘1’ to clear
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
BTSEF: Bit Stuff Error Flag bit
1= Packet rejected due to bit stuff error
0= Packet accepted
BMXEF: Bus Matrix Error Flag bit
1= The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid.
0= No address error
DMAEF: DMA Error Flag bit(1)
1= USB DMA error condition detected
0= No DMA error
BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1= Bus turnaround time-out has occurred
0= No bus turnaround time-out
DFN8EF: Data Field Size Error Flag bit
1= Data field received is not an integral number of bytes
0= Data field received is an integral number of bytes
CRC16EF: CRC16 Failure Flag bit
1= Data packet rejected due to CRC16 error
0= Data packet accepted
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.
DS60001185B-page 154
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED)
bit 1
CRC5EF: CRC5 Host Error Flag bit(4)
1= Token packet rejected due to CRC5 error
0= Token packet accepted
EOFEF: EOF Error Flag bit(3,5)
1= EOF error condition detected
0= No EOF error condition
bit 0
PIDEF: PID Check Failure Flag bit
1= PID check failed
0= PID check passed
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 155
PIC32MX330/350/370/430/450/470
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
—
—
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRC5EE(1)
EOFEE(2)
R/W-0
7:0
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
PIDEE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
BTSEE: Bit Stuff Error Interrupt Enable bit
1= BTSEF interrupt enabled
0= BTSEF interrupt disabled
BMXEE: Bus Matrix Error Interrupt Enable bit
1= BMXEF interrupt enabled
0= BMXEF interrupt disabled
DMAEE: DMA Error Interrupt Enable bit
1= DMAEF interrupt enabled
0= DMAEF interrupt disabled
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1= BTOEF interrupt enabled
0= BTOEF interrupt disabled
DFN8EE: Data Field Size Error Interrupt Enable bit
1= DFN8EF interrupt enabled
0= DFN8EF interrupt disabled
CRC16EE: CRC16 Failure Interrupt Enable bit
1= CRC16EF interrupt enabled
0= CRC16EF interrupt disabled
CRC5EE: CRC5 Host Error Interrupt Enable bit(1)
1= CRC5EF interrupt enabled
0= CRC5EF interrupt disabled
EOFEE: EOF Error Interrupt Enable bit(2)
1= EOF interrupt enabled
0= EOF interrupt disabled
bit 0
PIDEE: PID Check Failure Interrupt Enable bit
1= PIDEF interrupt enabled
0= PIDEF interrupt disabled
Note 1: Device mode.
2: Host mode.
Note:
For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
DS60001185B-page 156
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-10: U1STAT: USB STATUS REGISTER
Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-x
R-x
R-x
R-x
R-x
DIR
R-x
U-0
—
U-0
—
ENDPT<3:0>
PPBI
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111= Endpoint 15
1110= Endpoint 14
•
•
•
0001= Endpoint 1
0000= Endpoint 0
bit 3
bit 2
DIR: Last BD Direction Indicator bit
1= Last transaction was a transmit transfer (TX)
0= Last transaction was a receive transfer (RX)
PPBI: Ping-Pong BD Pointer Indicator bit
1= The last transaction was to the ODD BD bank
0= The last transaction was to the EVEN BD bank
bit 1-0 Unimplemented: Read as ‘0’
Note:
The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is
invalid when U1IR<TRNIF> = 0.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 157
PIC32MX330/350/370/430/450/470
REGISTER 11-11: U1CON: USB CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6
29/21/13/5
28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-x
R-x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PKTDIS(4)
USBEN(4)
SOFEN(5)
7:0
JSTATE
SE0
USBRST HOSTEN(2) RESUME(3) PPBRST
TOKBUSY(1,5)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 6
bit 5
JSTATE: Live Differential Receiver JSTATE flag bit
1= JSTATE detected on the USB
0= No JSTATE detected
SE0: Live Single-Ended Zero flag bit
1= Single Ended Zero detected on the USB
0= No Single Ended Zero detected
PKTDIS: Packet Transfer Disable bit(4)
1= Token and packet processing disabled (set upon SETUP token received)
0= Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1= Token being executed by the USB module
0= No token being executed
bit 4
bit 3
bit 2
USBRST: Module Reset bit(5)
1= USB reset generated
0= USB reset terminated
HOSTEN: Host Mode Enable bit(2)
1= USB host capability enabled
0= USB host capability disabled
RESUME: RESUME Signaling Enable bit(3)
1= RESUME signaling activated
0= RESUME signaling disabled
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and
then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to
the RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
DS60001185B-page 158
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED)
bit 1
PPBRST: Ping-Pong Buffers Reset bit
1= Reset all Even/Odd buffer pointers to the EVEN BD banks
0= Even/Odd buffer pointers not being Reset
bit 0
USBEN: USB Module Enable bit(4)
1= USB module and supporting circuitry enabled
0= USB module and supporting circuitry disabled
SOFEN: SOF Enable bit(5)
1= SOF token sent every 1 ms
0= SOF token disabled
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and
then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to
the RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 159
PIC32MX330/350/370/430/450/470
REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
—
—
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
—
—
R/W-0
R/W-0
LSPDEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DEVADDR<6:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 LSPDEN: Low Speed Enable Indicator bit
1= Next token command to be executed at Low Speed
0= Next token command to be executed at Full Speed
bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits
REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FRML<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
DS60001185B-page 160
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
FRMH<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
REGISTER 11-15: U1TOK: USB TOKEN REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PID<3:0>(1)
EP<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-4 PID<3:0>: Token Type Indicator bits(1)
0001= OUT (TX) token type transaction
1001= IN (RX) token type transaction
1101= SETUP (TX) token type transaction
Note: All other values are reserved and must not be used.
bit 3-0 EP<3:0>: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.
Note 1: All other values are reserved and must not be used.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 161
PIC32MX330/350/370/430/450/470
REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 CNT<7:0>: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010= 16-byte packet
00010010= 8-byte packet
REGISTER 11-17: U1BDTP1: USB BDT PAGE 1 REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
BDTPTRL<15:9>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-1 BDTPTRL<15:9>: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
bit 0
Unimplemented: Read as ‘0’
DS60001185B-page 162
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-18: U1BDTP2: USB BDT PAGE 2 REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRH<23:16>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 BDTPTRH<23:16>: BDT Base Address bits
This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
REGISTER 11-19: U1BDTP3: USB BDT PAGE 3 REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BDTPTRU<31:24>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 BDTPTRU<31:24>: BDT Base Address bits
This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location
of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 163
PIC32MX330/350/370/430/450/470
REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
UASUSPND
UTEYE
UOEMON
USBSIDL
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
UTEYE: USB Eye-Pattern Test Enable bit
1= Eye-Pattern Test enabled
0= Eye-Pattern Test disabled
bit 6
UOEMON: USB OE Monitor Enable bit
1= OE signal active; it indicates intervals during which the D+/D- lines are driving
0= OE signal inactive
bit 5
bit 4
Unimplemented: Read as ‘0’
USBSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 3-1
bit 0
Unimplemented: Read as ‘0’
UASUSPND: Automatic Suspend Enable bit
1= USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(U1PWRC<1>) in Register 11-5.
0= USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock
DS60001185B-page 164
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
—
—
—
—
—
R/W-0
LSPD
R/W-0
RETRYDIS
U-0
—
R/W-0
R/W-0
R/W-0
EPTXEN
R/W-0
EPSTALL
R/W-0
EPHSHK
EPCONDIS EPRXEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1= Direct connection to a low-speed device enabled
0= Direct connection to a low-speed device disabled; hub required with PRE_PID
bit 6
RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1= Retry NAK’d transactions disabled
0= Retry NAK’d transactions enabled; retry done in hardware
bit 5
bit 4
Unimplemented: Read as ‘0’
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1and EPRXEN = 1:
1= Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0= Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
bit 3
bit 2
bit 1
bit 0
EPRXEN: Endpoint Receive Enable bit
1= Endpoint n receive enabled
0= Endpoint n receive disabled
EPTXEN: Endpoint Transmit Enable bit
1= Endpoint n transmit enabled
0= Endpoint n transmit disabled
EPSTALL: Endpoint Stall Status bit
1= Endpoint n was stalled
0= Endpoint n was not stalled
EPHSHK: Endpoint Handshake Enable bit
1= Endpoint Handshake enabled
0= Endpoint Handshake disabled (typically used for isochronous endpoints)
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 165
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 166
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC® MCU to monitor and control
12.0 I/O PORTS
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 12. “I/O
Ports” (DS60001120) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up and pull-down
• Monitor selective inputs and generate interrupt
when change in pin state is detected
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
SYSCLK
D
Q
ODC
CK
EN
Q
WR ODC
RD TRIS
1
0
I/O Cell
0
1
D
D
Q
Q
1
0
TRIS
LAT
CK
EN
WR TRIS
Output Multiplexers
Q
Q
I/O Pin
CK
EN
WR LAT
WR PORT
RD LAT
1
0
RD PORT
Q
Q
D
Q
Q
D
Sleep
CK
CK
SYSCLK
Synchronization
Peripheral Input
R
Peripheral Input Buffer
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 167
PIC32MX330/350/370/430/450/470
12.1.3
I/O PORT WRITE/READ TIMING
12.1 Parallel I/O (PIO) Ports
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP.
All port pins have ten registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an
output. If the data direction bit is a ‘1’, then the pin is an
input. All port pins are defined as inputs after a Reset.
Reads from the latch (LATx) read the latch. Writes to
the latch write the latch. Reads from the port (PORTx)
read the port pins, while writes to the port pins write the
latch.
12.1.4
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
allows the PIC32MX330/350/370/430/450/470 devices
to generate interrupt requests to the processor in
response to a change-of-state on selected input pins.
This feature can detect input change-of-states even in
Sleep mode, when the clocks are disabled. Every I/O
port pin can be selected (enabled) for generating an
interrupt request on a change-of-state.
12.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx, and TRISx registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
Five control registers are associated with the CN func-
tionality of each I/O port. The CNENx registers contain
the CN interrupt enable control bits for each of the input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
The open-drain feature allows the generation of out-
puts higher than VDD (e.g., 5V) on any desired 5V-tol-
erant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
The CNSTATx register indicates whether a change
occurred on the corresponding pin since the last read
of the PORTx bit.
Each I/O pin also has a weak pull-up and every I/O
pin has a weak pull-down connected to it. The pull-
ups act as a current source or sink source connected
to the pin, and eliminate the need for external
resistors when push-button or keypad devices are
connected. The pull-ups and pull-downs are enabled
separately using the CNPUx and the CNPDx
registers, which contain the control bits for each of the
pins. Setting any of the control bits enables the weak
pull-ups and/or pull-downs for the corresponding pins.
See the “Pin Diagrams” section for the available pins
and their functionality.
12.1.2
CONFIGURING ANALOG AND
DIGITAL PORT PINS
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs must have their corresponding ANSEL
and TRIS bits set. In order to use port pins for I/O
functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
Note:
Pull-ups and pull-downs on change notifi-
cation pins should always be disabled
when the port pin is configured as a digital
output.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
An additional control register (CNCONx) is shown in
Register 12-3.
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
Comparator module.
12.2 CLR, SET, and INV Registers
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
DS60001185B-page 168
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When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
12.3 Peripheral Pin Select
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The chal-
lenge is even greater on low pin-count devices. In an
application where more than one peripheral needs to
be assigned to a single pin, inconvenient workarounds
in application code or a complete redesign may be the
only option.
12.3.3
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral pin select features are controlled through
two sets of SFRs: one to map peripheral inputs, and
one to map outputs. Because they are separately con-
trolled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable
function pin without constraint.
Peripheral pin select configuration provides an
alternative to these choices by enabling peripheral set
selection and their placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, users can better tailor the device to
their entire application, rather than trimming the
application to fit the device.
The association of a peripheral to a peripheral-select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
The peripheral pin select configuration feature oper-
ates over a fixed subset of digital I/O pins. Users may
independently map the input and/or output of most dig-
ital peripherals to these I/O pins. Peripheral pin select
is performed in software and generally does not require
the device to be reprogrammed. Hardware safeguards
are included that prevent accidental or spurious
changes to the peripheral mapping once it has been
established.
12.3.4
INPUT MAPPING
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. That is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The [pin name]R registers, where [pin
name] refers to the peripheral pins listed in Table 12-1,
are used to configure peripheral input mapping (see
Register 12-1). Each register contains sets of 4 bit
fields. Programming these bit fields with an appropriate
value maps the RPn pin with the corresponding value to
that peripheral. For any given device, the valid range of
values for any bit field is shown in Table 12-1.
12.3.1
AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
peripheral pin select feature include the designation
“RPn” in their full pin designation, where “RP”
designates a remappable peripheral and “n” is the
remappable port number.
For example, Figure 12-2 illustrates the remappable
pin selection for the U1RX input.
FIGURE 12-2:
REMAPPABLE INPUT
EXAMPLE FOR U1RX
12.3.2
AVAILABLE PERIPHERALS
The peripherals managed by the peripheral pin select
are all digital-only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
U1RXR<3:0>
0
RPA2
RPB6
RPA4
1
In comparison, some digital-only peripheral modules
are never included in the peripheral pin select feature.
This is because the peripheral’s function requires spe-
cial I/O circuitry on a specific port and cannot be easily
connected to multiple pins. These modules include I2C
among others. A similar requirement excludes all mod-
ules with analog inputs, such as the Analog-to-Digital
Converter (ADC).
U1RX input
to peripheral
2
n
A key difference between remappable and non-remap-
pable peripherals is that remappable peripherals are
not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
RPn
Note:
For input only, peripheral pin select functionality
does not have priority over TRISx settings.
Therefore, when configuring RPn pin for input,
the corresponding bit in the TRISx register must
also be configured for input (set to ‘1’).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 169
PIC32MX330/350/370/430/450/470
TABLE 12-1: INPUT PIN SELECTION
[pin name]R Value to
RPn Pin Selection
Peripheral Pin
[pin name]R SFR
[pin name]R bits
0000= RPD2
0001= RPG8
0010= RPF4
0011= RPD10
0100= RPF1
0101= RPB9
INT3
T2CK
IC3
INT3R
T2CKR
IC3R
INT3R<3:0>
T2CKR<3:0>
IC3R<3:0>
0110= RPB10
0111= RPC14
1000= RPB5
1001= Reserved
1010= RPC1(3)
1011= RPD14(3)
1100= RPG1(3)
1101= RPA14(3)
1110= Reserved
1111= RPF2(1)
U1RX
U2RX
U5CTS
U1RXR
U2RXR
U5CTSR
U1RXR<3:0>
U2RXR<3:0>
U5CTSR<3:0>
REFCLKI
REFCLKIR
REFCLKIR<3:0>
0000= RPD3
0001= RPG7
0010= RPF5
0011= RPD11
0100= RPF0
INT4
T5CK
IC4
INT4R
T5CKR
IC4R
INT4R<3:0>
T5CKR<3:0>
IC4R<3:0>
0101= RPB1
0110= RPE5
0111= RPC13
1000= RPB3
U3RX
U4CTS
SDI1
U3RXR
U4CTSR
SDI1R
U3RXR<3:0>
U4CTSR<3:0>
SDI1R<3:0>
1001= Reserved
1010= RPC4(3)
1011= RPD15(3)
1100= RPG0(3)
1101= RPA15(3)
1110= RPF2(1)
1111= RPF7(2)
SDI2
SDI2R
SDI2R<3:0>
0000= RPD9
0001= RPG6
0010= RPB8
0011= RPB15
0100= RPD4
0101= RPB0
INT2
T4CK
IC2
INT2R
T4CKR
IC2R
INT2R<3:0>
T4CKR<3:0>
IC2R<3:0>
0110= RPE3
0111= RPB7
IC5
IC5R
IC5R<3:0>
1000= Reserved
1001= RPF12(3)
1010= RPD12(3)
1011= RPF8(3)
1100= RPC3(3)
1101= RPE9(3)
1110= Reserved
1111= RPB2
U1CTS
U2CTS
U1CTSR
U2CTSR
U2CTSR<3:0>
U2CTSR<3:0>
SS1
SS1R
SS1R<3:0>
Note 1: This selection is not available on 64-pin USB devices.
2: This selection is only available on 100-pin General Purpose devices.
3: This selection is not available on 64-pin USB and General Purpose devices.
DS60001185B-page 170
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 12-1: INPUT PIN SELECTION (CONTINUED)
[pin name]R Value to
RPn Pin Selection
Peripheral Pin
[pin name]R SFR
[pin name]R bits
0000= RPD1
0001= RPG9
0010= RPB14
0011= RPD0
0100= RPD8
0101= RPB6
INT1
T3CK
IC1
INT1R
T3CKR
IC1R
INT1R<3:0>
T3CKR<3:0>
IC1R<3:0>
0110= RPD5
0111= RPB2
U3CTS
U4RX
U5RX
SS2
U3CTSR
U4RXR
U5RXR
SS2R
U3CTSR<3:0>
U4RXR<3:0>
U5RXR<3:0>
SS2R<3:0>
1000= RPF3(2)
1001= RPF13(3)
1010= Reserved
1011= RPF2(1)
1100= RPC2
1101= RPE8(3)
1110= Reserved
1111= Reserved
OCFA
OCFAR
OCFAR<3:0>
Note 1: This selection is not available on 64-pin USB devices.
2: This selection is only available on 100-pin General Purpose devices.
3: This selection is not available on 64-pin USB and General Purpose devices.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 171
PIC32MX330/350/370/430/450/470
12.3.5
OUTPUT MAPPING
12.3.6.1
Control Register Lock
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a
particular pin dictates the peripheral output to be
mapped. The RPnR registers (Register 12-2) are
used to control output mapping. Like the [pin name]R
registers, each register contains sets of 4 bit fields.
The value of the bit field corresponds to one of the
peripherals, and that peripheral’s output is mapped
to the pin (see Table 12-2 and Figure 12-3).
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these regis-
ters, they must be unlocked in hardware. The regis-
ter lock is controlled by the IOLOCK Configuration bit
(CFGCON<13>). Setting IOLOCK prevents writes to
the control registers; clearing IOLOCK allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference
Manual” for details.
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
12.3.6.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3<29>) blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure
does not execute, and the peripheral pin select control
registers cannot be written to. The only way to clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
FIGURE 12-3:
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPA0
RPA0R<3:0>
Default
U1TX Output
0
1
2
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
U1RTS Output
RPA0
Output Data
14
15
12.3.6
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32 devices include two features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
DS60001185B-page 172
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 12-2: OUTPUT PIN SELECTION
RPnR Value to Peripheral
Selection
RPn Port Pin
RPnR SFR
RPnR bits
Group 1 Selections
0000= No Connect
0001= U3TX
RPD2
RPG8
RPD2R
RPG8R
RPF4R
RPD10R
RPF1R
RPB9R
RPB10R
RPC14R
RPB5R
RPC1R
RPD14R
RPG1R
RPA14R
RPD3R
RPG7R
RPF5R
RPD11R
RPF0R
RPB1R
RPE5R
RPC13R
RPB3R
RPF3R
RPC4R
RPD15R
RPG0R
RPA15R
RPD2R<3:0>
RPG8R<3:0>
RPF4R<3:0>
RPD10R<3:0>
RPF1R<3:0>
RPB9R<3:0>
RPB10R<3:0>
RPC14R<3:0>
RPB5R<3:0>
RPC1R<3:0>
RPD14R<3:0>
RPG1R<3:0>
RPA14R<3:0>
RPD3R<3:0>
RPG7R<3:0>
RPF5R<3:0>
RPD11R<3:0>
RPF0R<3:0>
RPB1R<3:0>
RPE5R<3:0>
RPC13R<3:0>
RPB3R<3:0>
RPF3R<3:0>
RPC4R<3:0>
RPD15R<3:0>
RPG0R<3:0>
RPA15R<3:0>
0010= U4RTS
0011= Reserved
0100= Reserved
0101= Reserved
0110= SDO2
0111= Reserved
1000= Reserved
1001= Reserved
1010= Reserved
1011= OC3
RPF4
RPD10
RPF1
RPB9
RPB10
RPC14
RPB5
RPC1(4)
RPD14(5)
RPG1(4)
RPA14(4)
RPD3
1100= Reserved
1101= C2OUT
1110= Reserved
1111= Reserved
0000= No Connect
0001= U2TX
RPG7
0010= Reserved
0011= U1TX
RPF5
RPD11
RPF0
0100= U5RTS
0101= Reserved
0110= SDO2
RPB1
0111= Reserved
1000= SDO1
RPE5
RPC13
1001= Reserved
1010= Reserved
1011= OC4
RPB3
RPF3(2)
RPC4(4)
RPD15(5)
RPG0(4)
RPA15(4)
1100= Reserved
1101= Reserved
1110= Reserved
1111= Reserved
Note 1: This selection is not available on USB devices.
2: This selection is only available on 64-pin General Purpose devices.
3: This selection is only available on 100-pin General Purpose devices.
4: This selection is only available on 100-pin USB and General Purpose devices.
5: This selection is not available on 64-pin USB devices.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 173
PIC32MX330/350/370/430/450/470
TABLE 12-2: OUTPUT PIN SELECTION (CONTINUED)
RPnR Value to Peripheral
Selection
RPn Port Pin
RPnR SFR
RPnR bits
0000= No Connect
RPD9
RPG6
RPD9R
RPG6R
RPB8R
RPB15R
RPD4R
RPB0R
RPE3R
RPB7R
RPB2R
RPF12R
RPD12R
RPF8R
RPC3R
RPE9R
RPD1R
RPG9R
RPB14R
RPD0R
RPD8R
RPB6R
RPD5R
RPF3R
RPF6R
RPF13R
RPC2R
RPE8R
RPF2R
RPD9R<3:0>
RPG6R<3:0>
RPB8R<3:0>
RPB15R<3:0>
RPD4R<3:0>
RPB0R<3:0>
RPE3R<3:0>
RPB7R<3:0>
RPB2R<3:0>
RPF12R<3:0>
RPD12R<3:0>
RPF8R<3:0>
RPC3R<3:0>
RPE9R<3:0>
RPD1R<3:0>
RPG9R<3:0>
RPB14R<3:0>
RPD0R<3:0>
RPD8R<3:0>
RPB6R<3:0>
RPD5R<3:0>
RPF3R<3:0>
RPF6R<3:0>
RPF13R<3:0>
RPC2R<3:0>
RPE8R<3:0>
RPF2R<3:0>
0001= U3RTS
0010= U4TX
RPB8
0011= REFCLKO
0100= U5TX
RPB15
RPD4
0101= Reserved
0110= Reserved
0111= SS1
RPB0
RPE3
1000= SDO1
RPB7
1001= Reserved
1010= Reserved
1011= OC5
RPB2
RPF12(4)
RPD12(4)
RPF8(5)
RPC3(4)
RPE9(4)
RPD1
1100= Reserved
1101= C1OUT
1110= Reserved
1111= Reserved
0000= No Connect
0001= U2RTS
0010= Reserved
0011= U1RTS
0100= U5TX
0101= Reserved
0110= SS2
0111= Reserved
1000= SDO1
RPG9
RPB14
RPD0
RPD8
RPB6
RPD5
RPF3(3)
RPF6(1)
RPF13(4)
RPC2(4)
RPE8(4)
RPF2(5)
1001= Reserved
1010= Reserved
1011= OC2
1100= OC1
1101= Reserved
1110= Reserved
1111= Reserved
Note 1: This selection is not available on USB devices.
2: This selection is only available on 64-pin General Purpose devices.
3: This selection is only available on 100-pin General Purpose devices.
4: This selection is only available on 100-pin USB and General Purpose devices.
5: This selection is not available on 64-pin USB devices.
DS60001185B-page 174
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
12.4 Control Registers
REGISTER 12-1: [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
[pin name]R<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 12-1 for
input pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
REGISTER 12-2: RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RPnR<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits
See Table 12-2 for output pin selection values.
Note:
Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 175
PIC32MX330/350/370/430/450/470
REGISTER 12-3: CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – G)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
R/W-0
ON
U-0
—
U-0
—
R/W-0
SIDL
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Change Notice (CN) Control ON bit
1= CN is enabled
0= CN is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Control bit
1= CPU Idle Mode halts CN operation
0= CPU Idle does not affect CN operation
bit 12-0 Unimplemented: Read as ‘0’
DS60001185B-page 176
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
This family of PIC32 devices features one synchronous/
asynchronous 16-bit timer that can operate as a free-run-
13.0 TIMER1
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
ning interval timer for various timing applications and
counting external events. This timer can also be used
with the Low-Power Secondary Oscillator (SOSC) for
Real-Time Clock (RTC) applications. The following
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
13.1 Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
PR1
Equal
16-bit Comparator
TSYNC
1
0
Sync
TMR1
Reset
0
T1IF
Event Flag
1
Q
Q
D
TGATE
TCS
TGATE
ON
SOSCO/T1CK
x1
Prescaler
SOSCEN(1)
Gate
Sync
10
00
1, 8, 64, 256
SOSCI
PBCLK
2
TCKPS<1:0>
Note 1: The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit
in Configuration Word, DEVCFG1.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 177
PIC32MX330/350/370/430/450/470
13.2 Control Register
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
R/W-0
TGATE
U-0
—
R/W-0
SIDL
R/W-0
R/W-0
TWDIS
R/W-0
R-0
U-0
U-0
U-0
TWIP
U-0
—
—
—
U-0
R/W-0
R/W-0
U-0
—
—
TCKPS<1:0>
—
TSYNC
TCS
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1)
1= Timer is enabled
0= Timer is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue operation when device enters Idle mode
0= Continue operation even in Idle mode
bit 12
bit 11
TWDIS: Asynchronous Timer Write Disable bit
1= Writes to TMR1 are ignored until pending write operation completes
0= Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1= Asynchronous write to TMR1 register in progress
0= Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8 Unimplemented: Read as ‘0’
bit 7
TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
TCKPS<1:0>: Timer Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
bit 3
Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 178
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 2
TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1= External clock input is synchronized
0= External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer Clock Source Select bit
1= External clock from TxCKI pin
0= Internal peripheral clock
Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 179
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 180
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
14.0 TIMER2/3, TIMER4/5
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 14.
“Timers” (DS60001105) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The 32-bit timers can operate in three modes:
• Synchronous internal 32-bit timer
• Synchronous internal 32-bit gated timer
• Synchronous external 32-bit timer
Note:
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to repre-
sent Timer2 through 5 in 16-bit modes. In
32-bit modes, ‘x’ represents Timer2 or 4;
‘y’ represents Timer3 or 5.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
14.1 Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a free-
running interval timer for various timing applications
and counting external events. The following modes are
supported:
• ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
registers
• Synchronous internal 16-bit timer
• Synchronous internal 16-bit gated timer
• Synchronous external 16-bit timer
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event Trigger(1)
Comparator x 16
PRx
Equal
Reset
0
1
TxIF Event Flag
TGATE
TCS
Q
Q
D
TGATE
ON
TxCK
x1
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
Gate
Sync
10
PBCLK
00
3
TCKPS
Note 1:
The ADC event trigger is available on Timer3 only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 181
PIC32MX330/350/370/430/450/470
(1)
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
Reset
TMRy
TMRx
Sync
LS Half Word
MS Half Word
ADC Event Trigger(2)
32-bit Comparator
Equal
PRy
PRx
0
1
TyIF Event Flag
Q
Q
D
TGATE
TCS
TGATE
ON
TxCK
x1
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
Gate
Sync
10
00
PBCLK
3
TCKPS
Note 1:
2:
In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in registers,
TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
ADC event trigger is available only on the Timer2/3 pair.
DS60001185B-page 182
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
14.2 Control Register
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
—
U-0
—
U-0
U-0
—
U-0
U-0
—
—
—
—
—
R/W-0
ON(1,3)
R/W-0
TGATE(3)
U-0
—
R/W-0
U-0
—
U-0
U-0
—
U-0
U-0
—
SIDL(4)
R/W-0
—
—
R/W-0
R/W-0
R/W-0
T32(2)
U-0
—
R/W-0
TCS(3)
U-0
—
TCKPS<2:0>(3)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Timer On bit(1,3)
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit(4)
1= Discontinue operation when device enters Idle mode
0= Continue operation even in Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 6-4
TCKPS<2:0>: Timer Input Clock Prescale Select bits(3)
111= 1:256 prescale value
110= 1:64 prescale value
101= 1:32 prescale value
100= 1:16 prescale value
011= 1:8 prescale value
010= 1:4 prescale value
001= 1:2 prescale value
000= 1:1 prescale value
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is available only on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 183
PIC32MX330/350/370/430/450/470
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(2)
1= Odd numbered and even numbered timers form a 32-bit timer
0= Odd numbered and even numbered timers form a separate 16-bit timer
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timer Clock Source Select bit(3)
1= External clock from TxCK pin
0= Internal peripheral clock
bit 0
Unimplemented: Read as ‘0’
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is available only on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
DS60001185B-page 184
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
• Simple capture event modes
15.0 INPUT CAPTURE
- Capture timer value on every falling edge of
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 15. “Input
Capture” (DS60001122) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
• Capture timer value on every edge (rising and
falling)
• Capture timer value on every edge (rising and
falling), specified edge first.
• Prescaler capture event modes
- Capture timer value on every 4th rising
edge of input at ICx pin
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
Other operational features include:
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
Interrupt optionally generated after 1, 2, 3 or 4
buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM<2:0>
FEDGE
Specified/Every
Edge Mode
110
Prescaler Mode
(16th Rising Edge)
101
100
TMR2 TMR3
C32/ICTMR
Prescaler Mode
(4th Rising Edge)
To CPU
CaptureEvent
FIFO CONTROL
ICxBUF
011
010
001
Rising Edge Mode
Falling Edge Mode
ICx pin
FIFO
ICI<1:0>
/N
ICM<2:0>
Edge Detection
Mode
Set Flag ICxIF
(In IFSx Register)
Sleep/Idle
Wake-up Mode
001
111
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 185
PIC32MX330/350/370/430/450/470
15.1 Control Register
REGISTER 15-1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
R/W-0
ICTMR
U-0
—
R/W-0
SIDL
R/W-0
U-0
U-0
U-0
—
R/W-0
FEDGE
R/W-0
ICM<2:0>
R/W-0
C32
R/W-0
—
—
R/W-0
R-0
R-0
R/W-0
ICI<1:0>
ICOV
ICBNE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
r = Reserved bit
bit 31-16
bit 15
Unimplemented: Read as ‘0’
ON: Input Capture Module Enable bit(1)
1= Module enabled
0= Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Control bit
1= Halt in CPU Idle mode
0= Continue to operate in CPU Idle mode
bit 12-10
bit 9
Unimplemented: Read as ‘0’
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1= Capture rising edge first
0= Capture falling edge first
bit 8
C32: 32-bit Capture Select bit
1= 32-bit timer resource capture
0= 16-bit timer resource capture
bit 7
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
0= Timer3 is the counter source for capture
1= Timer2 is the counter source for capture
bit 6-5
ICI<1:0>: Interrupt Control bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
bit 3
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1= Input capture buffer is not empty; at least one more capture value can be read
0= Input capture buffer is empty
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 186
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 15-1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED)
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110= Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101= Prescaled Capture Event mode – every sixteenth rising edge
100= Prescaled Capture Event mode – every fourth rising edge
011= Simple Capture Event mode – every rising edge
010= Simple Capture Event mode – every falling edge
001= Edge Detect mode – every edge (rising and falling)
000= Input Capture module is disabled
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 187
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 188
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The Output Compare module (OCMP) is used to gen-
erate a single pulse or a train of pulses in response to
16.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 16. “Output
Compare” (DS60001111) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
selected time base events. For all modes of operation,
the OCMP module compares the values stored in the
OCxR and/or the OCxRS registers to the value in the
selected timer. When a match occurs, the OCMP
module generates an event based on the selected
mode of operation.
The following are some of the key features:
• Multiple Output Compare Modules in a device
• Programmable interrupt generation on compare
event
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
(1)
OCxIF
(1)
OCxRS
Output
Logic
(1)
S
R
Q
(1)
OCxR
OCx
Output Enable
Logic
Output
Enable
3
OCM<2:0>
Mode Select
(2)
OCFA or OCFB
Comparator
0
1
0
OCTSEL
1
16
16
Timer2
Rollover
Timer3
Timer3
Rollover
Timer2
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 189
PIC32MX330/350/370/430/450/470
16.1 Control Register
REGISTER 16-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
U-0
U-0
—
R/W-0
SIDL
R/W-0
OC32
U-0
U-0
U-0
—
U-0
U-0
—
—
—
—
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OCFLT(2)
OCTSEL
OCM<2:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Output Compare Peripheral On bit(1)
1= Output Compare peripheral is enabled
0= Output Compare peripheral is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue operation when CPU enters Idle mode
0= Continue operation in Idle mode
bit 12-6 Unimplemented: Read as ‘0’
bit 5
OC32: 32-bit Compare Mode bit
1= OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source
0= OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4
OCFLT: PWM Fault Condition Status bit(2)
1= PWM Fault condition has occurred (cleared in HW only)
0= No PWM Fault condition has occurred
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for this OCMP module
0= Timer2 is the clock source for this OCMP module
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx; Fault pin enabled
110= PWM mode on OCx; Fault pin disabled
101= Initialize OCx pin low; generate continuous output pulses on OCx pin
100= Initialize OCx pin low; generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high; compare event forces OCx pin low
001= Initialize OCx pin low; compare event forces OCx pin high
000= Output compare peripheral is disabled but continues to draw current
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.
DS60001185B-page 190
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters (ADC), etc.
The PIC32 SPI module is compatible with Motorola®
SPI and SIOP interfaces.
17.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the
features of the PIC32MX330/350/370/
430/450/470 family of devices. It is not
intended to be
a
comprehensive
reference source. To complement the
information in this data sheet, refer to
Some of the key features of the SPI module are:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data width
• Separate SPI FIFO buffers for receive and transmit
Section
23.
“Serial
Peripheral
Interface (SPI)” (DS60001106) in the
“PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during CPU Sleep and Idle mode
• Audio Codec Support:
- I2S protocol
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Left-justified
- Right-justified
- PCM
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
FIFOs Share Address SPIxBUF
SPIxRXB FIFO
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
MCLKSEL
Shift
Control
Slave Select
Clock
Control
Edge
Select
and Frame
Sync Control
SSx/FSYNC
SCKx
REFCLK
Baud Rate
Generator
PBCLK
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
MSTEN
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 191
PIC32MX330/350/370/430/450/470
17.1 Control Registers
REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-0
FRMEN
R/W-0
MCLKSEL(2)
R/W-0
R/W-0
R/W-0
R/W-0
MSSEN
U-0
R/W-0
FRMSYPW
U-0
R/W-0
R/W-0
FRMCNT<2:0>
R/W-0
R/W-0
31:24
23:16
15:8
7:0
FRMSYNC FRMPOL
U-0
U-0
U-0
—
R/W-0
ENHBUF(2)
R/W-0
CKE(3)
R/W-0
—
U-0
—
—
R/W-0
—
R/W-0
SPIFE
R/W-0
R/W-0
SIDL
R/W-0
MSTEN
R/W-0
ON(1)
R/W-0
—
R/W-0
CKP(4)
DISSDO
R/W-0
MODE32
R/W-0
MODE16
R/W-0
SMP
R/W-0
SSEN
DISSDI
STXISEL<1:0>
SRXISEL<1:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
bit 30
bit 29
bit 28
FRMEN: Framed SPI Support bit
1= Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0= Framed SPI support is disabled
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1= Frame sync pulse input (Slave mode)
0= Frame sync pulse output (Master mode)
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1= Frame pulse is active-high
0= Frame pulse is active-low
MSSEN: Master Mode Slave Select Enable bit
1= Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0= Slave select SPI support is disabled.
bit 27
FRMSYPW: Frame Sync Pulse Width bit
1= Frame sync pulse is one character wide
0= Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in FRAMED_SYNC mode.
111= Reserved; do not use
110= Reserved; do not use
101= Generate a frame sync pulse on every 32 data characters
100= Generate a frame sync pulse on every 16 data characters
011= Generate a frame sync pulse on every 8 data characters
010= Generate a frame sync pulse on every 4 data characters
001= Generate a frame sync pulse on every 2 data characters
000= Generate a frame sync pulse on every data character
bit 23
MCLKSEL: Master Clock Enable bit(2)
1= REFCLK is used by the Baud Rate Generator
0= PBCLK is used by the Baud Rate Generator
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
DS60001185B-page 192
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 22-18 Unimplemented: Read as ‘0’
bit 17
bit 16
bit 15
SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1= Frame synchronization pulse coincides with the first bit clock
0= Frame synchronization pulse precedes the first bit clock
ENHBUF: Enhanced Buffer Enable bit(2)
1= Enhanced Buffer mode is enabled
0= Enhanced Buffer mode is disabled
ON: SPI Peripheral On bit(1)
1= SPI Peripheral is enabled
0= SPI Peripheral is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue operation when CPU enters in Idle mode
0= Continue operation in Idle mode
bit 12
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by the module. Pin is controlled by associated PORT register
0= SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32
MODE16
Communication
1
1
0
0
1
0
1
0
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
When AUDEN = 0:
MODE32
MODE16
Communication
32-bit
16-bit
1
0
0
x
1
0
8-bit
bit 9
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8
bit 7
bit 6
CKE: SPI Clock Edge Select bit(3)
1= Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0= Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1= SSx pin used for Slave mode
0= SSx pin not used for Slave mode, pin controlled by port function.
CKP: Clock Polarity Select bit(4)
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 193
PIC32MX330/350/370/430/450/470
REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 5
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
bit 4
DISSDI: Disable SDI bit
1= SDI pin is not used by the SPI module (pin is controlled by PORT function)
0= SDI pin is controlled by the SPI module
bit 3-2
STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11= Interrupt is generated when the buffer is not full (has one or more empty elements)
10= Interrupt is generated when the buffer is empty by one-half or more
01= Interrupt is generated when the buffer is completely empty
00= Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0
SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11= Interrupt is generated when the buffer is full
10= Interrupt is generated when the buffer is full by one-half or more
01= Interrupt is generated when the buffer is not empty
00= Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value
of CKP.
DS60001185B-page 194
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 17-2: SPIxCON2: SPI CONTROL REGISTER 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
27/19/11/3
26/18/10/2 25/17/9/1 24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
R/W-0
—
U-0
—
—
U-0
—
—
R/W-0
—
R/W-0
—
R/W-0
—
R/W-0
—
R/W-0
SPISGNEXT
R/W-0
AUDEN(1)
FRMERREN
U-0
SPIROVEN
R/W-0
AUDMONO(1,2)
SPITUREN IGNROV IGNTUR
U-0
U-0
U-0
R/W-0
AUDMOD<1:0>(1,2)
R/W-0
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1= Data from RX FIFO is sign extended
0= Data from RX FIFO is not sign extened
bit 14-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
FRMERREN: Enable Interrupt Events via FRMERR bit
1= Frame Error overflow generates error events
0= Frame Error does not generate error events
SPIROVEN: Enable Interrupt Events via SPIROV bit
1= Receive overflow generates error events
0= Receive overflow does not generate error events
SPITUREN: Enable Interrupt Events via SPITUR bit
1= Transmit Underrun Generates Error Events
0= Transmit Underrun Does Not Generates Error Events
IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1= A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
0= A ROV is a critical error which stop SPI operation
bit 8
IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1= A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0= A TUR is a critical error which stop SPI operation
bit 7
AUDEN: Enable Audio CODEC Support bit(1)
1= Audio protocol enabled
0= Audio protocol disabled
bit 6-5
bit 3
Unimplemented: Read as ‘0’
AUDMONO: Transmit Audio Data Format bit(1,2)
1= Audio data is mono (Each data word is transmitted on both left and right channels)
0= Audio data is stereo
bit 2
Unimplemented: Read as ‘0’
AUDMOD<1:0>: Audio Protocol Mode bit(1,2)
bit 1-0
11= PCM/DSP mode
10= Right Justified mode
01= Left Justified mode
00= I2S mode
Note 1: This bit can only be written when the ON bit = 0.
2: This bit is only valid for AUDEN = 1.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 195
PIC32MX330/350/370/430/450/470
REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
31:24
23:16
15:8
7:0
RXBUFELM<4:0>
U-0
U-0
U-0
R-0
R-0
—
—
—
TXBUFELM<4:0>
U-0
U-0
U-0
R/C-0, HS
U-0
U-0
—
R-0
—
—
—
FRMERR SPIBUSY
—
SPITUR
R-0
R-0
R/W-0
R-0
U-0
R-1
U-0
—
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
SPITBF
SPIRBF
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR: SPI Frame Error status bit
1= Frame error detected
0= No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY: SPI Activity Status bit
1= SPI peripheral is currently busy with some transactions
0= SPI peripheral is currently idle
bit 10-9 Unimplemented: Read as ‘0’
bit 8
SPITUR: Transmit Under Run bit
1= Transmit buffer has encountered an underrun condition
0= Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7
bit 6
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1= When SPI module shift register is empty
0= When SPI module shift register is not empty
SPIROV: Receive Overflow Flag bit
1= A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0= No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5
bit 4
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1= RX FIFO is empty (CRPTR = SWPTR)
0= RX FIFO is not empty (CRPTR SWPTR)
Unimplemented: Read as ‘0’
DS60001185B-page 196
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER (CONTINUED)
bit 3
SPITBE: SPI Transmit Buffer Empty Status bit
1= Transmit buffer, SPIxTXB is empty
0= Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
Unimplemented: Read as ‘0’
bit 2
bit 1
SPITBF: SPI Transmit Buffer Full Status bit
1= Transmit not yet started, SPITXB is full
0= Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
SPIRBF: SPI Receive Buffer Full Status bit
bit 0
1= Receive buffer, SPIxRXB is full
0= Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 197
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 198
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 illustrates the
I2C module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
18.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
Note 1: This data sheet summarizes the
features of the PIC32MX330/350/370/
430/450/470 family of devices. It is not
intended to be
a
comprehensive
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit
addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
reference source. To complement the
information in this data sheet, refer to
Section 24. “Inter-Integrated Circuit™
(I2C™)” (DS60001116) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Provides support for address bit masking
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 199
PIC32MX330/350/370/430/450/470
2
FIGURE 18-1:
I C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSB
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSB
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
PBCLK
I2CxBRG
DS60001185B-page 200
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
18.1 Control Registers
2
REGISTER 18-1: I2CXCON: I C™ CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
R/W-0
GCEN
U-0
R/W-0
SIDL
R/W-0
ACKDT
R/W-1, HC
SCLREL
R/W-0, HC
ACKEN
R/W-0
STRICT
R/W-0, HC
RCEN
R/W-0
A10M
R/W-0, HC
PEN
R/W-0
DISSLW
R/W-0, HC
RSEN
R/W-0
SMEN
R/W-0, HC
SEN
—
R/W-0
STREN
Legend:
HC = Cleared in Hardware
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: I2C Enable bit(1)
1= Enables the I2C module and configures the SDA and SCL pins as serial port pins
0= Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
STRICT: Strict I2C Reserved Address Rule Enable bit
1= Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0= Strict I2C Reserved Address Rule not enabled
bit 10
bit 9
bit 8
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
SMEN: SMBus Input Levels bit
1= Enable I/O pin thresholds compliant with SMBus specification
0= Disable SMBus input thresholds
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 201
PIC32MX330/350/370/430/450/470
2
REGISTER 18-1: I2CXCON: I C™ CONTROL REGISTER (CONTINUED)
bit 7
bit 6
bit 5
bit 4
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0= Start condition not in progress
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 202
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
2
REGISTER 18-2: I2CXSTAT: I C™ STATUS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0, HSC
ACKSTAT
R/C-0, HS
IWCOL
R-0, HSC
TRSTAT
R/C-0, HS
I2COV
U-0
U-0
U-0
R/C-0, HS
BCL
R-0, HSC
R_W
R-0, HSC
GCSTAT
R-0, HSC
RBF
R-0, HSC
ADD10
R-0, HSC
TBF
—
—
—
R-0, HSC
R/C-0, HSC
P
R/C-0, HSC
S
D_A
Legend:
HS = Set in hardware
W = Writable bit
‘1’ = Bit is set
HSC = Hardware set/cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared C = Clearable bit
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit
(when operating as I2C™ master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 203
PIC32MX330/350/370/430/450/470
2
REGISTER 18-2: I2CXSTAT: I C™ STATUS REGISTER (CONTINUED)
bit 4
bit 3
bit 2
bit 1
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete, I2CxRCV is full
0= Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS60001185B-page 204
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The primary features of the UART module are:
19.0 UNIVERSAL ASYNCHRONOUS
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 21.
“Universal Asynchronous Receiver
Transmitter (UART)” (DS60001107) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
• Hardware auto-baud feature
• Hardware flow control option
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates ranging from 76 bps to 20 Mbps at
80 MHz
• 8-level deep First-In-First-Out (FIFO) transmit
data buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Support for interrupt-only on address detect
(9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
The UART module is one of the serial I/O modules
available in PIC32MX330/350/370/430/450/470 family
devices. The UART is a full-duplex, asynchronous
communication channel that communicates with
peripheral devices and personal computers through
protocols, such as RS-232, RS-485, LIN and IrDA®.
The module also supports the hardware flow control
option, with UxCTS and UxRTS pins, and also includes
an IrDA encoder and decoder.
Figure 19-1 illustrates a simplified block diagram of the
UART.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
UxRTS/BCLKx
UxCTS
Hardware Flow Control
UARTx Receiver
UxRX
UxTX
UARTx Transmitter
Note:
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 205
PIC32MX330/350/370/430/450/470
19.1 Control Registers
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
R/W-0
WAKE
U-0
R/W-0
SIDL
R/W-0
ABAUD
R/W-0
IREN
R/W-0
RXINV
R/W-0
RTSMD
R/W-0
BRGH
U-0
—
R/W-0
R/W-0
—
UEN<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
LPBACK
PDSEL<1:0>
STSEL
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: UARTx Enable bit(1)
1= UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
control bits
0= UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue operation when device enters Idle mode
0= Continue operation in Idle mode
bit 12
bit 11
IREN: IrDA Encoder and Decoder Enable bit
1= IrDA is enabled
0= IrDA is disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin is in Simplex mode
0= UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
bit 6
WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1= Wake-up enabled
0= Wake-up disabled
LPBACK: UARTx Loopback Mode Select bit
1= Loopback mode is enabled
0= Loopback mode is disabled
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 206
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0= Baud rate measurement disabled or completed
bit 4
RXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= High-Speed mode – 4x baud clock enabled
0= Standard Speed mode – 16x baud clock enabled
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Selection bit
1= 2 Stop bits
0= 1 Stop bit
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 207
PIC32MX330/350/370/430/450/470
REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
ADM_EN
R/W-0
31:24
23:16
15:8
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<7:0>
R/W-0
R/W-0
R/W-0
UTXINV
R/W-0
R/W-0
URXEN
R-1
R/W-0
UTXBRK
R-0
R/W-0
UTXEN
R-0
R-0
R-1
TRMT
R-0
UTXISEL<1:0>
UTXBF
R/W-0
R/W-0
R/W-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24 ADM_EN: Automatic Address Detect Mode Enable bit
1= Automatic Address Detect mode is enabled
0= Automatic Address Detect mode is disabled
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11= Reserved, do not use
10= Interrupt is generated and asserted while the transmit buffer is empty
01= Interrupt is generated and asserted when all characters have been transmitted
00= Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13
UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):
1= IrDA encoded UxTX Idle state is ‘1’
0= IrDA encoded UxTX Idle state is ‘0’
bit 12
bit 11
URXEN: Receiver Enable bit
1= UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0= UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.
UTXBRK: Transmit Break bit
1= Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion
0= Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit
1= UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0= UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is con-
trolled by port.
bit 9
bit 8
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register is Empty bit (read-only)
1= Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
DS60001185B-page 208
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bit
11= Reserved; do not use
10= Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)
01= Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)
00= Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Data is being received
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character
0= Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to empty state.
1= Receive buffer has overflowed
0= Receive buffer has not overflowed
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 209
PIC32MX330/350/370/430/450/470
19.2 Timing Diagrams
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1
Char 2-4
Char 11-13
Char 5-10
Read to
UxRXREG
Start 1
Stop Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
Stop
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS60001185B-page 210
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Key features of the PMP module include:
20.0 PARALLEL MASTER PORT
• 8-bit,16-bit interface
(PMP)
• Up to 16 programmable address lines
• Up to two Chip Select lines
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS60001128) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
• Programmable strobe options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
• Address auto-increment/auto-decrement
• Programmable address/data multiplexing
• Programmable polarity on control signals
• Parallel Slave Port support
- Legacy addressable
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable Wait states
• Operate during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
• Freeze option for in-circuit debugging
Note:
On 64-pin devices, data pins PMD<15:8>
are not available in 16-bit Master modes.
FIGURE 20-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Control Lines
PMA<0>
PMALL
Parallel
Master Port
PMA<1>
PMALH
Flash
EEPROM
Up to 16-bit Address
PMA<13:2>
SRAM
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
FIFO
Buffer
Microcontroller
LCD
PMD<7:0>
PMD<15:8>
(1)
8-bit/16-bit Data (with or without multiplexed addressing)
Note:
On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 211
PIC32MX330/350/370/430/450/470
20.1
Control Registers
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
Bit
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
—
R/W-0
—
R/W-0
—
—
—
R/W-0
ON(1)
R/W-0
U-0
R/W-0
SIDL
R/W-0
ALP(2)
R/W-0
PMPTTL
U-0
R/W-0
PTWREN
R/W-0
WRSP
R/W-0
PTRDEN
R/W-0
RDSP
—
R/W-0
ADRMUX<1:0>
R/W-0
CS2P(2)
R/W-0
CS1P(2)
CSF<1:0>(2)
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Parallel Master Port Enable bit(1)
1= PMP enabled
0= PMP disabled, no off-chip access performed
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11= Lower 8 bits of address are multiplexed on PMD<15:0> pins; upper 8 bits are not used
10= All 16 bits of address are multiplexed on PMD<15:0> pins
01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and
PMA<14>
00= Address and data appear on separate pins
bit 10
bit 9
PMPTTL: PMP Module TTL Input Buffer Select bit
1= PMP module uses TTL input buffers
0= PMP module uses Schmitt Trigger input buffer
PTWREN: Write Enable Strobe Port Enable bit
1= PMWR/PMENB port enabled
0= PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1= PMRD/PMWR port enabled
0= PMRD/PMWR port disabled
bit 7-6
CSF<1:0>: Chip Select Function bits(2)
11= Reserved
10= PMCS1 function as Chip Select
01= PMCS1 functions as address bit 14
00= PMCS1 function as address bit 14
bit 5
ALP: Address Latch Polarity bit(2)
1= Active-high (PMALL and PMALH)
0= Active-low (PMALL and PMALH)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
DS60001185B-page 212
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 4
CS2P: Chip Select 0 Polarity bit(2)
1= Active-high (PMCS2)
0= Active-low (PMCS2)
bit 3
CS1P: Chip Select 0 Polarity bit(2)
1= Active-high (PMCS1)
0= Active-low (PMCS1)
bit 2
bit 1
Unimplemented: Read as ‘0’
WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Write strobe active-high (PMWR)
0= Write strobe active-low (PMWR)
For Master mode 1 (PMMODE<9:8> = 11):
1= Enable strobe active-high (PMENB)
0= Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Read Strobe active-high (PMRD)
0= Read Strobe active-low (PMRD)
For Master mode 1 (PMMODE<9:8> = 11):
1= Read/write strobe active-high (PMRD/PMWR)
0= Read/write strobe active-low (PMRD/PMWR)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 213
PIC32MX330/350/370/430/450/470
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
BUSY
R/W-0
WAITB<1:0>(1)
IRQM<1:0>
INCM<1:0>
MODE<1:0>
R/W-0
R/W-0
R/W-0
WAITM<3:0>(1)
R/W-0
R/W-0
R/W-0
WAITE<1:0>(1)
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
BUSY: Busy bit (Master mode only)
1= Port is busy
0= Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11= Reserved, do not use
10= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11(Addressable Slave mode only)
01= Interrupt generated at the end of the read/write cycle
00= No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11= Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00only)
10= Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
01= Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
00= No increment or decrement of address
bit 10
Unimplemented: Read as ‘0’
bit 9-8
MODE<1:0>: Parallel Port Mode Select bits
11= Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<15:0>)
10= Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<15:0>)
01= Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<15:0>, and PMA<1:0>)
00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<15:0>)
bit 7-6
WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)
11= Data wait of 4 TPB; multiplexed address phase of 4 TPB
10= Data wait of 3 TPB; multiplexed address phase of 3 TPB
01= Data wait of 2 TPB; multiplexed address phase of 2 TPB
00= Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1TPBCLK cycle, WAITE = 0TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
DS60001185B-page 214
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2
WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)
1111= Wait of 16 TPB
•
•
•
0001= Wait of 2 TPB
0000= Wait of 1 TPB (default)
bit 1-0
WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11= Wait of 4 TPB
10= Wait of 3 TPB
01= Wait of 2 TPB
00= Wait of 1 TPB (default)
For Read operations:
11= Wait of 3 TPB
10= Wait of 2 TPB
01= Wait of 1 TPB
00= Wait of 0 TPB (default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1TPBCLK cycle, WAITE = 0TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 215
PIC32MX330/350/370/430/450/470
REGISTER 20-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
CS2
R/W-0
R/W-0
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15:8
7:0
ADDR<13:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14
CS2: Chip Select 2 bit
1= Chip Select 2 is active
0= Chip Select 2 is inactive (pin functions as PMA<14>)
bit 14
CS1: Chip Select 1 bit
1= Chip Select 1 is active
0= Chip Select 1 is inactive (pin functions as PMA<14>)
bit 13-0 ADDR<13:0>: Destination Address bits
DS60001185B-page 216
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 20-4: PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
Bit
24/16/8/0
U-0
U-0
—
U-0
U-0
U-0
U-0
—
U-0
U-0
—
31:24
23:16
15:8
7:0
—
—
—
—
—
U-0
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
—
—
U-0
R/W-0
PTEN14
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
PTEN<10:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN14: PMCS1 Strobe Enable bits
1= PMA14 functions as either PMA14 or PMCS1(1)
0= PMA14 functions as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits
1= PMA<10:2> function as PMP address lines
0= PMA<10:2> function as port I/O
bit 1-0
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0= PMA1 and PMA0 pads functions as port I/O
Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX<1:0> in the PMCON register.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 217
PIC32MX330/350/370/430/450/470
REGISTER 20-5: PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R-0
R/W-0, HSC
IBOV
R/W-0, HSC
OBUF
U-0
—
U-0
—
R-0
R-0
R-0
R-0
IBF
R-1
IB3F
R-1
IB2F
R-1
IB1F
R-1
IB0F
R-1
U-0
U-0
OBE
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
HSC = Set by Hardware; Cleared by Software
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
IBF: Input Buffer Full Status bit
1= All writable input buffer registers are full
0= Some or all of the writable input buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1= A write attempt to a full input byte buffer occurred (must be cleared in software)
0= No overflow occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 IBxF: Input Buffer ‘x’ Status Full bits
1= Input Buffer contains data that has not been read (reading buffer will clear this bit)
0= Input Buffer does not contain any unread data
bit 7
bit 6
OBE: Output Buffer Empty Status bit
1= All readable output buffer registers are empty
0= Some or all of the readable output buffer registers are full
OBUF: Output Buffer Underflow Status bit
1= A read occurred from an empty output byte buffer (must be cleared in software)
0= No underflow occurred
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
OBxE: Output Buffer ‘x’ Status Empty bits
1= Output buffer is empty (writing data to the buffer will clear this bit)
0= Output buffer contains data that has not been transmitted
DS60001185B-page 218
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Some of the key features of this module include:
21.0 REAL-TIME CLOCK AND
• Time: hours, minutes and seconds
• 24-hour format (military time)
CALENDAR (RTCC)
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 29. “Real-
Time Clock and Calendar (RTCC)”
(DS60001125) in the “PIC32 Family
Reference Manual”, which is available
• Visibility of one-half second period
• Provides calendar: Weekday, date, month and
year
• Alarm intervals are configurable for half of a
second, one second, 10 seconds, one minute, 10
minutes, one hour, one day, one week, one month
and one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat: Chime
• Year range: 2000 to 2099
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Leap year correction
• BCD format for smaller firmware overhead
• Optimized for long-term battery operation
• Fractional second synchronization
• User calibration of the clock crystal frequency with
auto-adjust
The PIC32 RTCC module is intended for applications in
which accurate time must be maintained for extended
periods of time with minimal or no CPU intervention.
Low-power optimization provides extended battery
lifetime while keeping track of time.
• Calibration range: 0.66 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Requirements: External 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on
RTCC pin
FIGURE 21-1:
RTCC BLOCK DIAGRAM
CAL<9:0>
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
RTCTIME
HR, MIN, SEC
RTCVAL
RTCC Timer
Alarm
RTCDATE
YEAR, MONTH, DAY, WDAY
Event
Comparator
ALRMTIME
HR, MIN, SEC
Compare Registers
with Masks
ALRMVAL
ALRMDATE
MONTH, DAY, WDAY
Repeat Counter
Set RTCC Flag
0
RTCC Interrupt Logic
Alarm Pulse
1
RTCC
Seconds Pulse
RTSECSEL
RTCOE
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 219
PIC32MX330/350/370/430/450/470
21.1 Control Registers
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1 24/16/8/0
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
—
R/W-0
CAL<9:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL<7:0>
U-0
R/W-0
ON(1,2)
R/W-0
U-0
—
R/W-0
SIDL
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
U-0
—
R-0
R/W-0
R-0
R-0
R/W-0
RTSECSEL(3) RTCCLKON
—
RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
0111111111= Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
0000000001= Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000= No adjustment
1111111111= Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000= Minimum negative adjustment, subtracts 512 clock pulses every one minute
ON: RTCC On bit(1,2)
bit 15
1= RTCC module is enabled
0= RTCC module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Disables the PBCLK to the RTCC when CPU enters in Idle mode
0= Continue normal operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7
RTSECSEL: RTCC Seconds Clock Output Select bit(3)
1= RTCC Seconds Clock is selected for the RTCC pin
0= RTCC Alarm Pulse is selected for the RTCC pin
bit 6
RTCCLKON: RTCC Clock Enable Status bit
1= RTCC Clock is actively running
0= RTCC Clock is not running
bit 5-4
Unimplemented: Read as ‘0’
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1(RTCCON<0>) for the output to be active.
4: The RTCWREN bit can be set only when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note:
This register is reset only on a Power-on Reset (POR).
DS60001185B-page 220
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
bit 3
RTCWREN: RTC Value Registers Write Enable bit(4)
1= RTC Value registers can be written to by the user
0= RTC Value registers are locked out from being written to by the user
bit 2
RTCSYNC: RTCC Value Registers Read Synchronization bit
1= RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read
If the register is read twice and results in the same data, the data can be assumed to be valid
0= RTC Value registers can be read without concern about a rollover ripple
bit 1
bit 0
HALFSEC: Half-Second Status bit(5)
1= Second half period of a second
0= First half period of a second
RTCOE: RTCC Output Enable bit
1= RTCC clock output enabled – clock presented onto an I/O
0= RTCC clock output disabled
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1(RTCCON<0>) for the output to be active.
4: The RTCWREN bit can be set only when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note:
This register is reset only on a Power-on Reset (POR).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 221
PIC32MX330/350/370/430/450/470
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5
28/20/12/4
27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
R/W-0
—
R/W-0
—
—
R-0
—
R/W-0
—
R/W-0
AMASK<3:0>(3)
R/W-0
—
R/W-0
—
R/W-0
R/W-0
PIV(2)
R/W-0
ALRMEN(1,2) CHIME(2)
ALRMSYNC(3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT<7:0>(3)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12
ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
CHIME: Chime Enable bit(2)
1= Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0= Chime is disabled – ARPT<7:0> stops once it reaches 0x00
PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
ALRMSYNC: Alarm Sync bit(3)
1= ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain
0= ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
clocks away from a half-second rollover
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3)
0000= Every half-second
0001= Every second
0010= Every 10 seconds
0011= Every minute
0100= Every 10 minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29, once every four years)
1010= Reserved; do not use
1011= Reserved; do not use
11xx= Reserved; do not use
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note:
This register is reset only on a Power-on Reset (POR).
DS60001185B-page 222
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits(3)
11111111= Alarm will trigger 256 times
•
•
•
00000000= Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note:
This register is reset only on a Power-on Reset (POR).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 223
PIC32MX330/350/370/430/450/470
REGISTER 21-3: RTCTIME: RTC TIME VALUE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
23:16
15:8
7:0
HR10<3:0>
HR01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
MIN10<3:0>
MIN01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
SEC10<3:0>
SEC01<3:0>
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
Note:
This register is only writable when RTCWREN = 1(RTCCON<3>).
DS60001185B-page 224
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 21-4: RTCDATE: RTC DATE VALUE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
23:16
15:8
7:0
YEAR10<3:0>
YEAR01<3:0>
R/W-x
R/W-x
MONTH10<3:0>
MONTH01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
DAY10<3:0>
DAY01<3:0>
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
WDAY01<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note:
This register is only writable when RTCWREN = 1(RTCCON<3>).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 225
PIC32MX330/350/370/430/450/470
REGISTER 21-5: ALRMTIME: ALARM TIME VALUE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
31:24
23:16
15:8
7:0
HR10<3:0>
HR01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
MIN10<3:0>
MIN01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
SEC10<3:0>
SEC01<3:0>
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0
Unimplemented: Read as ‘0’
DS60001185B-page 226
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 21-6: ALRMDATE: ALARM DATE VALUE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5
28/20/12/4
27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MONTH10<3:0>
MONTH01<3:0>
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAY10<1:0>
DAY01<3:0>
U-0
U-0
U-0
U-0
R/W-x
R/W-x
—
—
—
—
WDAY01<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 227
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 228
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The 10-bit Analog-to-Digital Converter (ADC) includes
the following features:
22.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
• Successive Approximation Register (SAR)
conversion
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 17. “10-bit
Analog-to-Digital Converter (ADC)”
(DS60001104) in the “PIC32 Family
Reference Manual”, which is available
• Up to 1 Msps conversion speed
• Up to 28 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample and Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable buffer fill modes
from
the
Microchip
web
site
(www.microchip.com/PIC32).
• Eight conversion result format options
• Operation during CPU Sleep and Idle modes
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A block diagram of the 10-bit ADC is illustrated in
Figure 22-1. The 10-bit ADC has up to 28 analog input
pins, designated AN0-AN27. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
FIGURE 22-1:
ADC1 MODULE BLOCK DIAGRAM
(1)
VREF+
(1)
VREF-
(3)
AVDD
AVSS
CTMUI
AN0
AN27
VCFG<2:0>
(3)
IVREF
ADC1BUF0
ADC1BUF1
ADC1BUF2
(2)
(4)
CTMUT
Open
VREFH
VREFL
S&H
Channel
Scan
+
-
CH0SB<4:0>
SAR ADC
CH0SA<4:0>
CSCNA
AN1
ADC1BUFE
ADC1BUFF
VREFL
CH0NA CH0NB
Alternate
Input Selection
Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.
2: Connected to the CTMU module. See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more
information.
3: See Section 24.0 “Comparator Voltage Reference (CVREF)” for more information.
4: This selection is only used with CTMU capacitive and time measurement.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 229
PIC32MX330/350/370/430/450/470
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC(1)
Div 2
1
0
TAD
ADCS<7:0>
8
ADC Conversion
Clock Multiplier
(2)
TPB
2, 4,..., 512
Note 1: See Section 30.0 “Electrical Characteristics” for the exact FRC clock value.
2: Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information.
DS60001185B-page 230
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
22.1
Control Registers
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1 24/16/8/0
U-0
U-0
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
—
—
U-0
—
—
U-0
—
U-0
—
—
R/W-0
—
R/W-0
—
R/W-0
R/W-0
ON(1)
R/W-0
R/W-0
SIDL
R/W-0
—
R/W-0
—
R/W-0
FORM<2:0>
R/W-0, HSC
SAMP(2)
U-0
R/W-0
R/C-0, HSC
DONE(3)
SSRC<2:0>
CLRASAM
—
ASAM
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: ADC Operating Mode bit(1)
1= ADC module is operating
0= ADC module is not operating
bit 14
bit 13
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 FORM<2:0>: Data Output Format bits
011= Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010= Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001= Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000= Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
111= Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110= Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101= Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100= Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
bit 7-5
SSRC<2:0>: Conversion Trigger Source Select bits
111= Internal counter ends sampling and starts conversion (auto convert)
110= Reserved
101= Reserved
100= Reserved
011= CTMU ends sampling and starts conversion
010= Timer 3 period match ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing SAMP bit ends sampling and starts conversion
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 231
PIC32MX330/350/370/430/450/470
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 4
CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)
1= Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.
0= Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3
bit 2
Unimplemented: Read as ‘0’
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
0= Sampling begins when SAMP bit is set
bit 1
bit 0
SAMP: ADC Sample Enable bit(2)
1= The ADC sample and hold amplifier is sampling
0= The ADC sample/hold amplifier is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.
DONE: Analog-to-Digital Conversion Status bit(3)
1= Analog-to-digital conversion is done
0= Analog-to-digital conversion is not done or has not started
Clearing this bit will not affect any operation in progress.
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this
bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
DS60001185B-page 232
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 22-2: AD1CON2: ADC CONTROL REGISTER 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1 24/16/8/0
U-0
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
R/W-0
—
R/W-0
—
R/W-0
—
—
U-0
—
—
—
U-0
—
U-0
R/W-0
OFFCAL
R/W-0
R/W-0
CSCNA
R/W-0
VCFG<2:0>
U-0
—
R/W-0
—
R/W-0
R-0
R/W-0
R/W-0
BUFS
—
SMPI<3:0>
BUFM
ALTS
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
VREFH
VREFL
000
001
010
011
1xx
AVDD
External VREF+ pin
AVDD
AVss
AVSS
External VREF- pin
External VREF- pin
AVSS
External VREF+ pin
AVDD
bit 12
OFFCAL: Input Offset Calibration Mode Select bit
1= Enable Offset Calibration mode
Positive and negative inputs of the sample and hold amplifier are connected to VREFL
0= Disable Offset Calibration mode
The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL
bit 11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Input Scan Select bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
Only valid when BUFM = 1.
1= ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0= ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111= Interrupts at the completion of conversion for each 16th sample/convert sequence
1110= Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001= Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000= Interrupts at the completion of conversion for each sample/convert sequence
bit 1
bit 0
BUFM: ADC Result Buffer Mode Select bit
1= Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8
0= Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
ALTS: Alternate Input Sample Mode Select bit
1= Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and
Sample A input multiplexer settings for all subsequent samples
0= Always use Sample A input multiplexer settings
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 233
PIC32MX330/350/370/430/450/470
REGISTER 22-3: AD1CON3: ADC CONTROL REGISTER 3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1 24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ADRC
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
R/W-0
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
R/W-0
R/W
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ADRC: ADC Conversion Clock Source bit
1= Clock derived from FRC
0= Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111=31 TAD
•
•
•
00001=1TAD
00000=0TAD (Not allowed)
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111=TPB • 2 • (ADCS<7:0> + 1) = 512 • TPB = TAD
•
•
•
00000001=TPB • 2 • (ADCS<7:0> + 1) = 4 • TPB = TAD
00000000=TPB • 2 • (ADCS<7:0> + 1) = 2 • TPB = TAD
Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.
2: This bit is not used if the ADRC bit (AD1CON3<15>) = 1.
DS60001185B-page 234
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 22-4: AD1CHS: ADC INPUT SELECT REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1 24/16/8/0
R/W-0
CH0NB
R/W-0
CH0NA
U-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
CH0SB<4:0>
U-0
U-0
R/W-0
—
—
CH0SA<4:0>
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
U-0
—
—
—
—
—
—
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
CH0NB: Negative Input Select bit for Sample B
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREFL
bit 30-29 Unimplemented: Read as ‘0’
bit 28-24 CH0SB<4:0>: Positive Input Select bits for Sample B
11110= Channel 0 positive input is Open(1)
11101= Channel 0 positive input is CTMU temperature sensor (CTMUT)(2)
(3)
11100= Channel 0 positive input is IVREF
11011= Channel 0 positive input is AN27
•
•
•
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
bit 23
CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(3)
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREFL
bit 22-21 Unimplemented: Read as ‘0’
bit 20-16 CH0SA<4:0>: Positive Input Select bits for Sample A Multiplexer Setting
11110= Channel 0 positive input is Open(1)
11101= Channel 0 positive input is CTMU temperature sensor (CTMUT)(2)
(3)
11100= Channel 0 positive input is IVREF
11011= Channel 0 positive input is AN27
•
•
•
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
bit 15-0
Unimplemented: Read as ‘0’
Note 1: This selection is only used with CTMU capacitive and time measurement.
2: See Section 25.0 “Charge Time Measurement Unit (CTMU)” for more information.
3: See Section 24.0 “Comparator Voltage Reference (CVREF)” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 235
PIC32MX330/350/370/430/450/470
REGISTER 22-5: AD1CSSL: ADC INPUT SCAN SELECT REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
R/W-0
CSSL30
R/W-0
R/W-0
CSSL29
R/W-0
R/W-0
CSSL28
R/W-0
R/W-0
CSSL27
R/W-0
R/W-0
CSSL26
R/W-0
R/W-0
CSSL25
R/W-0
R/W-0
CSSL24
R/W-0
31:24
23:16
15:8
7:0
R/W-0
CSSL23
R/W-0
CSSL21
R/W-0
CSSL21
R/W-0
CSSL20
R/W-0
CSSL19
R/W-0
CSSL18
R/W-0
CSSL17
R/W-0
CSSL16
R/W-0
CSSL15
R/W-0
CSSL14
R/W-0
CSSL13
R/W-0
CSSL12
R/W-0
CSSL11
R/W-0
CSSL10
R/W-0
CSSL9
R/W-0
CSSL8
R/W-0
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CSSL<30:0>: ADC Input Pin Scan Selection bits(1,2)
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: CSSL = ANx, where x = 0-27; CSSL30 selects Vss for scan; CSSL29 selects CTMU input for scan;
CSSL28 selects IVREF for scan.
2: On devices with less than 28 analog inputs, all CSSLx bits can be selected; however, inputs selected for
scan without a corresponding input on the device will convert to VREFL.
DS60001185B-page 236
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The Analog Comparator module contains two compar-
ators that can be configured in a variety of ways.
23.0
COMPARATOR
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 19.
“Comparator” (DS60001110) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Following are some of the key features of this module:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be Inverted
• Selectable interrupt generation
A block diagram of the comparator module is provided
in Figure 23-1.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 23-1:
COMPARATOR BLOCK DIAGRAM
CCH<1:0>
C1INB
C1INC
C1IND
COE
CMP1
C1OUT
CREF
CMSTAT<C1OUT>
CM1CON<COUT>
CPOL
C1INA
CCH<1:0>
To CTMU module
(Pulse Generator)
C2INB
C2INC
C2IND
COE
CMP2
C2OUT
CREF
CMSTAT<C2OUT>
CM2CON<COUT>
CPOL
C2INA
(1)
CVREF
IVREF (1.2V)
Note 1: Internally connected. See Section 24.0 “Comparator Voltage Reference (CVREF)” for more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 237
PIC32MX330/350/370/430/450/470
23.1
Control Registers
REGISTER 23-1: CMXCON: COMPARATOR CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
U-0
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
U-0
—
U-0
—
—
U-0
—
—
R-0
R/W-0
ON(1)
R/W-1
R/W-0
COE
R/W-1
R/W-0
CPOL(2)
U-0
U-0
—
R/W-0
—
R/W-1
COUT
R/W-1
U-0
U-0
EVPOL<1:0>
—
CREF
—
—
CCH<1:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator ON bit(1)
1= Module is enabled. Setting this bit does not affect the other bits in this register
0= Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
bit 14
bit 13
COE: Comparator Output Enable bit
1= Comparator output is driven on the output CxOUT pin
0= Comparator output is not driven on the output CxOUT pin
CPOL: Comparator Output Inversion bit(2)
1= Output is inverted
0= Output is not inverted
bit 12-9 Unimplemented: Read as ‘0’
bit 8
COUT: Comparator Output bit
1= Output of the Comparator is a ‘1’
0= Output of the Comparator is a ‘0’
bit 7-6
EVPOL<1:0>: Interrupt Event Polarity Select bits
11= Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10= Comparator interrupt is generated on a high-to-low transition of the comparator output
01= Comparator interrupt is generated on a low-to-high transition of the comparator output
00= Comparator interrupt generation is disabled
bit 5
bit 4
Unimplemented: Read as ‘0’
CREF: Comparator Positive Input Configure bit
1= Comparator non-inverting input is connected to the internal CVREF
0= Comparator non-inverting input is connected to the CXINA pin
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CCH<1:0>: Comparator Negative Input Select bits for Comparator
11= Comparator inverting input is connected to the IVREF
10= Comparator inverting input is connected to the CxIND pin
01= Comparator inverting input is connected to the CxINC pin
00= Comparator inverting input is connected to the CxINB pin
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
DS60001185B-page 238
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 23-2: CMSTAT: COMPARATOR STATUS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
—
U-0
—
U-0
—
R/W-0
SIDL
U-0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
—
C2OUT
C1OUT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in IDLE Control bit
1= All Comparator modules are disabled in IDLE mode
0= All Comparator modules continue to operate in the IDLE mode
bit 12-2 Unimplemented: Read as ‘0’
bit 1
C2OUT: Comparator Output bit
1= Output of Comparator 2 is a ‘1’
0= Output of Comparator 2 is a ‘0’
bit 0
C1OUT: Comparator Output bit
1= Output of Comparator 1 is a ‘1’
0= Output of Comparator 1 is a ‘0’
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 239
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 240
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
The CVREF module is a 16-tap, resistor ladder network
24.0 COMPARATOR VOLTAGE
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
REFERENCE (CVREF)
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 20. “Comparator
A block diagram of the module is illustrated in
Figure 24-1. The resistor ladder is segmented to
provide two ranges of voltage reference values and has
a power-down function to conserve power when the
reference is not being used. The module’s supply refer-
ence can be provided from either device VDD/VSS or an
external voltage reference. The CVREF output is avail-
able for the comparators and typically available for pin
output.
Voltage
Reference
(CVREF)”
(DS60001109) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The CVREF module has the following features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
FIGURE 24-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
AVDD
CVRSRC
8R
CVREF
CVR<3:0>
R
CVREN
R
R
R
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR
VREF-
AVSS
8R
CVRSS = 1
CVRSS = 0
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 241
PIC32MX330/350/370/430/450/470
24.1 Control Register
REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
31:24
23:16
15:8
7:0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
R/W-0
ON(1)
U-0
U-0
U-0
U-0
U-0
—
U-0
—
U-0
—
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVROE
CVRR
CVRSS
CVR<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Comparator Voltage Reference On bit(1)
1= Module is enabled
Setting this bit does not affect other bits in the register.
0= Module is disabled and does not consume current.
Clearing this bit does not affect the other bits in the register.
bit 14-7 Unimplemented: Read as ‘0’
bit 6
CVROE: CVREFOUT Enable bit
1= Voltage level is output on CVREFOUT pin
0= Voltage level is disconnected from CVREFOUT pin
bit 5
CVRR: CVREF Range Selection bit
1= 0 to 0.67 CVRSRC, with CVRSRC/24 step size
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: CVREF Source Selection bit
1= Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS60001185B-page 242
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
on-chip analog modules, the CTMU can be used for
high resolution time measurement, measure capaci-
tance, measure relative changes in capacitance or
generate output pulses with a specific time delay. The
CTMU is ideal for interfacing with capacitive-based
sensors.
25.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
Note 1: This data sheet summarizes the fea-
tures of the PIC32MX330/350/370/430/
450/470 family of devices. It is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to
Section 37. “Charge Time Measure-
ment Unit (CTMU)” (DS60001167) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
The CTMU module includes the following key features:
• Up to 13 channels available for capacitive or time
measurement input
• On-chip precision current source
• 16-edge input trigger sources
• Selection of edge or level-sensitive inputs
• Polarity control for each edge source
• Control of edge sequence
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Control of response to edges
• High precision time measurement
• Time delay of external or internal signal asynchro-
nous to system clock
• Integrated temperature sensing diode
• Control of current source during auto-sampling
• Four current source ranges
The Charge Time Measurement Unit (CTMU) is a flex-
ible analog module that has a configurable current
source with a digital configuration circuit built around it.
The CTMU can be used for differential time measure-
ment between pulse sources and can be used for gen-
erating an asynchronous pulse. By working with other
• Time measurement resolution of one nanosecond
A block diagram of the CTMU is shown in Figure 25-1.
FIGURE 25-1:
CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2
CTMUICON
ITRIM<5:0>
IRNG<1:0>
Current Source
CTED1
Edge
Control
Logic
•
•
•
ADC
Trigger
CTMU
Control
Logic
EDG1STAT
EDG2STAT
TGEN
CTED13
Current
Control
Timer1
OC1
IC1-IC3
Pulse
Generator
CTMUP
CTPLS
CMP1-CMP2
PBCLK
CTMUI
(To ADC S&H capacitor)
CTMUT
(To ADC)
C2INB
Temperature
Sensor
CDelay
Comparator 2
External capacitor
for pulse generation
Current Control Selection
TGEN
EDG1STAT, EDG2STAT
CTMUT
0
0
1
1
EDG1STAT = EDG2STAT
EDG1STAT EDG2STAT
EDG1STAT EDG2STAT
EDG1STAT = EDG2STAT
CTMUI
CTMUP
No Connect
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 243
PIC32MX330/350/370/430/450/470
25.1 Control Register
REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER
Bit
Range
Bit
Bit
Bit
Bit
Bit
Bit
Bit
25/17/9/1
Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
31:24
23:16
15:8
7:0
EDG1MOD EDG1POL
EDG1SEL<3:0>
R/W-0
EDG2STAT EDG1STAT
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
R/W-0
CTTRIG
R/W-0
EDG2MOD EDG2POL
EDG2SEL<3:0>
R/W-0
R/W-0
ON
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
CTMUSIDL TGEN(1)
EDGEN EDGSEQEN IDISSEN(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM<5:0>
IRNG<1:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31
EDG1MOD: Edge1 Edge Sampling Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
bit 30
EDG1POL: Edge 1 Polarity Select bit
1= Edge1 programmed for a positive edge response
0= Edge1 programmed for a negative edge response
bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits
1111= C3OUT pin is selected
1110= C2OUT pin is selected
1101= C1OUT pin is selected
1100= IC3 Capture Event is selected
1011= IC2 Capture Event is selected
1010= IC1 Capture Event is selected
1001= CTED8 pin is selected
1000= CTED7 pin is selected
0111= CTED6 pin is selected
0110= CTED5 pin is selected
0101= CTED4 pin is selected
0100= CTED3 pin is selected
0011= CTED1 pin is selected
0010= CTED2 pin is selected
0001= OC1 Compare Event is selected
0000= Timer1 Event is selected
bit 25
EDG2STAT: Edge2 Status bit
Indicates the status of Edge2 and can be written to control edge source
1= Edge2 has occurred
0= Edge2 has not occurred
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
DS60001185B-page 244
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 24
EDG1STAT: Edge1 Status bit
Indicates the status of Edge1 and can be written to control edge source
1= Edge1 has occurred
0= Edge1 has not occurred
bit 23
bit 22
EDG2MOD: Edge2 Edge Sampling Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
EDG2POL: Edge 2 Polarity Select bit
1= Edge2 programmed for a positive edge response
0= Edge2 programmed for a negative edge response
bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits
1111= C3OUT pin is selected
1110= C2OUT pin is selected
1101= C1OUT pin is selected
1100= PBCLK clock is selected
1011= IC3 Capture Event is selected
1010= IC2 Capture Event is selected
1001= IC1 Capture Event is selected
1000= CTED13 pin is selected
0111= CTED12 pin is selected
0110= CTED11 pin is selected
0101= CTED10 pin is selected
0100= CTED9 pin is selected
0011= CTED1 pin is selected
0010= CTED2 pin is selected
0001= OC1 Compare Event is selected
0000= Timer1 Event is selected
bit 17-16 Unimplemented: Read as ‘0’
bit 15
ON: ON Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
CTMUSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
TGEN: Time Generation Enable bit(1)
1= Enables edge delay generation
0= Disables edge delay generation
EDGEN: Edge Enable bit
1= Edges are not blocked
0= Edges are blocked
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 245
PIC32MX330/350/370/430/450/470
REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 10
EDGSEQEN: Edge Sequence Enable bit
1= Edge1 must occur before Edge2 can occur
0= No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit(2)
1= Analog current source output is grounded
0= Analog current source output is not grounded
bit 8
CTTRIG: Trigger Control bit
1= Trigger output is enabled
0= Trigger output is disabled
bit 7-2
ITRIM<5:0>: Current Source Trim bits
011111= Maximum positive change from nominal current
011110
•
•
•
000001= Minimum positive change from nominal current
000000= Nominal current output specified by IRNG<1:0>
111111= Minimum negative change from nominal current
•
•
•
100010
100001= Maximum negative change from nominal current
bit 1-0
IRNG<1:0>: Current Range Select bits(3)
11= 100 times base current
10= 10 times base current
01= Base current level
00= 1000 times base current(4)
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to ‘1110’ to select
C2OUT.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 30-41) in Section 30.0 “Electrical
Characteristics” for current values.
4: This bit setting is not available for the CTMU temperature diode.
DS60001185B-page 246
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
• LPRC Idle mode: the system clock is derived from
26.0 POWER-SAVING FEATURES
the LPRC. Peripherals continue to operate, but
can optionally be individually disabled. This is the
lowest power mode for the device with a clock
running.
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “Power-
Saving Features” (DS60001130) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
26.3 Power-Saving Operation
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
26.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
This section describes power-saving features for the
PIC32MX330/350/370/430/450/470. The PIC32 devices
offer a total of nine methods and modes, organized into
two categories, that allow the user to balance power
consumption with device performance. In all of the
methods and modes described in this section, power-
saving is controlled by software.
Sleep mode includes the following characteristics:
• The CPU is Halted.
26.1 Power Saving with CPU Running
• The system clock source is typically shutdown.
See Section 26.3.3 “Peripheral Bus Scaling
Method” for specific information.
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the PBCLK and by individually disabling
modules. These methods are grouped into the
following categories:
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• The BOR circuit remains operative during Sleep
mode.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
peripherals that use an external clock input or the
internal LPRC oscillator (e.g., RTCC, Timer1 and
Input Capture).
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
26.2 CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate. Peripherals continue to operate, but can
optionally be individually disabled.
• The USB module can override the disabling of the
Posc or FRC. Refer to the USB section for
specific details.
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
• SOSC Idle mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
can optionally be individually disabled.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 247
PIC32MX330/350/370/430/450/470
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
The processor will wake or exit from Idle mode on the
following events:
• On any form of device Reset.
• On a WDT time-out.
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
26.3.2
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripher-
als to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
26.3.3
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as the USB, Interrupt Controller, DMA,
and the bus matrix are clocked directly from SYSCLK.
As a result, they are not affected by PBCLK divisor
changes.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral tim-
ing. For example, assume the UART is
configured for 9600 baud with a PB clock
ratio of 1:1 and a POSC of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input frequency to the baud clock is cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing cal-
culation required for a peripheral should
be performed with the new PB clock fre-
quency instead of scaling the previous
value based on a change in the PB divisor
ratio.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator start-
up delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
DS60001185B-page 248
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
To disable a peripheral, the associated PMDx bit must
26.4 Peripheral Module Disable
be set to ‘1’. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 26-1 for
more information.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
Note:
Disabling a peripheral module while it’s
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.
TABLE 26-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS
Peripheral(1)
PMDx bit Name(1)
Register Name and Bit Location
ADC1
CTMU
AD1MD
CTMUMD
CVRMD
CMP1MD
CMP2MD
IC1MD
IC2MD
IC3MD
IC4MD
IC5MD
OC1MD
OC2MD
OC3MD
OC4MD
OC5MD
T1MD
PMD1<0>
PMD1<8>
PMD1<12>
PMD2<0>
PMD2<1>
PMD3<0>
PMD3<1>
PMD3<2>
PMD3<3>
PMD3<4>
PMD3<16>
PMD3<17>
PMD3<18>
PMD3<19>
PMD3<20>
PMD4<0>
PMD4<1>
PMD4<2>
PMD4<3>
PMD4<4>
PMD5<0>
PMD5<1>
PMD5<2>
PMD5<3>
PMD5<4>
PMD5<8>
PMD5<9>
PMD5<16>
PMD5<17>
PMD5<24>
PMD6<0>
PMD6<1>
PMD6<16>
Comparator Voltage Reference
Comparator 1
Comparator 2
Input Capture 1
Input Capture 2
Input Capture 3
Input Capture 4
Input Capture 5
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Output Compare 5
Timer1
Timer2
T2MD
Timer3
T3MD
Timer4
T4MD
Timer5
T5MD
UART1
U1MD
UART2
U2MD
UART3
U3MD
UART4
U4MD
UART5
U5MD
SPI1
SPI1MD
SPI2MD
I2C1MD
I2C2MD
USBMD
RTCCMD
REFOMD
PMPMD
SPI2
I2C1
I2C2
USB(2)
RTCC
Reference Clock Output
PMP
Note 1: Not all modules and associated PMDx bits are available on all devices. See TABLE 1: “PIC32MX330/350/
370/430/450/470 Controller Family Features” for the lists of available peripherals.
2: Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 249
PIC32MX330/350/370/430/450/470
26.4.1
CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32
devices include two features to prevent alterations to
enabled or disabled peripherals:
• Control register lock sequence
• Configuration bit select lock
26.4.1.1
Control Register Lock
Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the PMDLOCK Configuration bit (CFGCON<12>). Set-
ting PMDLOCK prevents writes to the control registers;
clearing PMDLOCK allows writes.
To set or clear PMDLOCK, an unlock sequence must
be executed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference
Manual” for details.
26.4.1.2
Configuration Bit Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3<28>) blocks the PMDLOCK bit from being
cleared after it has been set once. If PMDLOCK
remains set, the register unlock procedure does not
execute, and the peripheral pin select control registers
cannot be written to. The only way to clear the bit and
re-enable PMD functionality is to perform a device
Reset.
DS60001185B-page 250
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
27.1 Configuration Bits
27.0 SPECIAL FEATURES
The Configuration bits can be programmed using the
following registers to select various device
configurations.
Note 1: This data sheet summarizes the
features of the PIC32MX330/350/370/
430/450/470 family of devices. However,
it is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog Timer and
• DEVCFG0: Device Configuration Word 0
• DEVCFG1: Device Configuration Word 1
• DEVCFG2: Device Configuration Word 2
• DEVCFG3: Device Configuration Word 3
• CFGCON: Configuration Control Register
Power-up
Section
Timer”
32.
(DS60001114),
“Configuration”
(DS60001124)
“Programming
and
and
Section
Diagnostics”
33.
In addition, the DEVID register (Register 27-6)
provides device and revision information.
(DS60001129) in the “PIC32 Family
Reference Manual”, which are available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
PIC32MX330/350/370/430/450/470 devices include
several features intended to maximize application flex-
ibility and reliability and minimize cost through elimina-
tion of external components. These are:
• Flexible device configuration
• Watchdog Timer (WDT)
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)
REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
r-0
—
r-1
r-1
—
r-1
r-1
—
r-1
R/P
CP
r-1
r-1
—
r-1
—
r-1
—
R/P
BWP
R/P
31:24
23:16
15:8
7:0
R/P
R/P
R/P
—
R/P
—
R/P
—
R/P
—
R/P
PWP<7:0>
r-1
—
r-1
—
r-1
—
r-1
—
PWP<3:0>
r-1
r-1
r-1
R/P
R/P
R/P
JTAGEN(1)
R/P
R/P
—
—
—
ICESEL<1:0>
DEBUG<1:0>
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 31
bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Reserved: Write ‘0’
Prevents boot and program Flash memory from being read or modified by an external pro-
gramming device.
1= Protection is disabled
0= Protection is enabled
bit 27-25 Reserved: Write ‘1’
Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 251
PIC32MX330/350/370/430/450/470
REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1= Boot Flash is writable
0= Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution. The PWP bits
represent the one’s compliment of the number of write protected program Flash memory pages.
11111111= Disabled
11111110= 0xBD00_0FFF
11111101= 0xBD00_1FFF
11111100= 0xBD00_2FFF
11111011= 0xBD00_3FFF
11111010= 0xBD00_4FFF
11111001= 0xBD00_5FFF
11111000= 0xBD00_6FFF
11110111= 0xBD00_7FFF
11110110= 0xBD00_8FFF
11110101= 0xBD00_9FFF
11110100= 0xBD00_AFFF
11110011= 0xBD00_BFFF
11110010= 0xBD00_CFFF
11110001= 0xBD00_DFFF
11110000= 0xBD00_EFFF
11101111= 0xBD00_FFFF
.
.
.
01111111= 0xBD07_FFFF
bit 11-5 Reserved: Write ‘1’
bit 4-3
ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits
11= PGEC1/PGED1 pair is used
10= PGEC2/PGED2 pair is used
01= PGEC3/PGED3 pair is used
00= Reserved
bit 2
JTAGEN: JTAG Enable bit(1)
1= JTAG is enabled
0= JTAG is disabled
bit 1-0
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
1x= Debugger is disabled
0x= Debugger is enabled
Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.
DS60001185B-page 252
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 27-2: DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
r-1
—
r-1
—
r-1
—
r-1
r-1
—
r-1
—
r-1
R/P
R/P
31:24
23:16
15:8
7:0
—
R/P
FWDTWINSZ<1:0>
R/P
R/P
R/P
R/P
R/P
R/P
FWDTEN
R/P
WINDIS
R/P
—
R/P
WDTPS<4:0>
R/P
R/P
r-1
—
r-1
—
R/P
R/P
FCKSM<1:0>
FPBDIV<1:0>
OSCIOFNC
R/P
POSCMOD<1:0>
R/P
r-1
R/P
r-1
R/P
R/P
IESO
—
FSOSCEN
—
FNOSC<2:0>
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Reserved: Write ‘1’
bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits
11= Window size is 25%
10= Window size is 37.5%
01= Window size is 50%
00= Window size is 75%
bit 23
bit 22
bit 21
FWDTEN: Watchdog Timer Enable bit
1= Watchdog Timer is enabled and cannot be disabled by software
0= Watchdog Timer is not enabled; it can be enabled in software
WINDIS: Watchdog Timer Window Enable bit
1= Watchdog Timer is in non-Window mode
0= Watchdog Timer is in Window mode
Reserved: Write ‘1’
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100= 1:1048576
10011= 1:524288
10010= 1:262144
10001= 1:131072
10000= 1:65536
01111= 1:32768
01110= 1:16384
01101= 1:8192
01100= 1:4096
01011= 1:2048
01010= 1:1024
01001= 1:512
01000= 1:256
00111= 1:128
00110= 1:64
00101= 1:32
00100= 1:16
00011= 1:8
00010= 1:4
00001= 1:2
00000= 1:1
All other combinations not shown result in operation = 10100
Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 253
PIC32MX330/350/370/430/450/470
REGISTER 27-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11= PBCLK is SYSCLK divided by 8
10= PBCLK is SYSCLK divided by 4
01= PBCLK is SYSCLK divided by 2
00= PBCLK is SYSCLK divided by 1
bit 11
bit 10
Reserved: Write ‘1’
OSCIOFNC: CLKO Enable Configuration bit
1= CLKO output disabled
0= CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11or 00)
bit 9-8
bit 7
POSCMOD<1:0>: Primary Oscillator Configuration bits
11= Primary Oscillator disabled
10= HS Oscillator mode selected
01= XT Oscillator mode selected
00= External Clock mode selected
IESO: Internal External Switchover bit
1= Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0= Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
bit 5
Reserved: Write ‘1’
FSOSCEN: Secondary Oscillator Enable bit
1= Enable Secondary Oscillator
0= Disable Secondary Oscillator
bit 4-3
bit 2-0
Reserved: Write ‘1’
FNOSC<2:0>: Oscillator Selection bits
111= Fast RC Oscillator with divide-by-N (FRCDIV)
110= FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010= Primary Oscillator (XT, HS, EC)(1)
001= Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000= Fast RC Oscillator (FRC)
Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
DS60001185B-page 254
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 27-3: DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
r-1
r-1
—
r-1
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
r-1
—
31:24
23:16
15:8
7:0
—
—
—
R/P
r-1
r-1
r-1
r-1
R/P
R/P
—
—
—
—
FPLLODIV<2:0>
R/P
UPLLIDIV<2:0>(1)
R/P
R/P
UPLLEN(1)
r-1
r-1
r-1
R/P
R/P
R/P
R/P
—
—
R/P
—
r-1
R/P-1
R/P-1
—
FPLLMUL<2:0>
FPLLIDIV<2:0>
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 31-19 Reserved: Write ‘1’
bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits
111= PLL output divided by 256
110= PLL output divided by 64
101= PLL output divided by 32
100= PLL output divided by 16
011= PLL output divided by 8
010= PLL output divided by 4
001= PLL output divided by 2
000= PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit(1)
1= Disable and bypass USB PLL
0= Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits(1)
111= 12x divider
110= 10x divider
101= 6x divider
100= 5x divider
011= 4x divider
010= 3x divider
010= 3x divider
001= 2x divider
000= 1x divider
bit 7
Reserved: Write ‘1’
bit 6-4
FPLLMUL<2:0>: PLL Multiplier bits
111= 24x multiplier
110= 21x multiplier
101= 20x multiplier
100= 19x multiplier
011= 18x multiplier
010= 17x multiplier
001= 16x multiplier
000= 15x multiplier
bit 3
Reserved: Write ‘1’
Note 1: This bit is available on PIC32MX4XX devices only.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 255
PIC32MX330/350/370/430/450/470
REGISTER 27-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 2-0
FPLLIDIV<2:0>: PLL Input Divider bits
111= 12x divider
110= 10x divider
101= 6x divider
100= 5x divider
011= 4x divider
010= 3x divider
001= 2x divider
000= 1x divider
Note 1: This bit is available on PIC32MX4XX devices only.
DS60001185B-page 256
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 27-4: DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7
30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/P
R/P
R/P
R/P
U-0
—
U-0
—
U-0
U-0
—
31:24
23:16
15:8
7:0
FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY
—
U-0
U-0
U-0
U-0
U-0
R/P
R/P
FSRSSEL<2:0>
R/P
R/P
—
R/P
—
R/P
—
R/P
—
R/P
—
R/P
R/P
R/P
R/P
R/P
USERID<15:8>
R/P
R/P
R/P
R/P
R/P
R/P
USERID<7:0>
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 31
bit 30
bit 29
bit 28
FVBUSONIO: USB VBUS_ON Selection bit
1= VBUSON pin is controlled by the USB module
0= VBUSON pin is controlled by the port function
FUSBIDIO: USB USBID Selection bit
1= USBID pin is controlled by the USB module
0= USBID pin is controlled by the port function
IOL1WAY: Peripheral Pin Select Configuration bit
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
PMDL1WAY: Peripheral Module Disable Configuration bit
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
bit 27-19 Unimplemented: Read as ‘0’
bit 18-16 FSRSSEL<2:0>: Shadow Register Set Priority Select bit
These bits assign an interrupt priority to a shadow register.
111= Shadow register set used with interrupt priority 7
110= Shadow register set used with interrupt priority 6
101= Shadow register set used with interrupt priority 5
100= Shadow register set used with interrupt priority 4
011= Shadow register set used with interrupt priority 3
010= Shadow register set used with interrupt priority 2
001= Shadow register set used with interrupt priority 1
000= Shadow register set used with interrupt priority 0
bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 257
PIC32MX330/350/370/430/450/470
REGISTER 27-5: CFGCON: CONFIGURATION CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5
28/20/12/4
27/19/11/3 26/18/10/2 25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
31:24
23:16
15:8
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
U-0
U-0
—
U-0
IOLOCK(1) PMDLOCK(1)
—
—
—
U-0
U-0
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
—
—
—
—
JTAGEN
TROEN
—
TDOEN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13
IOLOCK: Peripheral Pin Select Lock bit(1)
1= Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
0= Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
bit 12
PMDLOCK: Peripheral Module Disable bit(1)
1= Peripheral module is locked. Writes to PMD registers is not allowed.
0= Peripheral module is not locked. Writes to PMD registers is allowed.
bit 11-4 Unimplemented: Read as ‘0’
bit 3
JTAGEN: JTAG Port Enable bit
1= Enable the JTAG port
0= Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1= Enable trace outputs and start trace clock (trace probe must be present)
0= Disable trace outputs and stop trace clock
bit 1
bit 0
Unimplemented: Read as ‘0’
TDOEN: TDO Enable for 2-Wire JTAG
1= 2-wire JTAG protocol uses TDO
0= 2-wire JTAG protocol does not use TDO
Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Reference Manual” for details.
DS60001185B-page 258
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 27-6: DEVID: DEVICE AND REVISION ID REGISTER
Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
Bit
26/18/10/2
Bit
Bit
25/17/9/1 24/16/8/0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
31:24
23:16
15:8
7:0
VER<3:0>(1)
DEVID<27:24>(1)
R
R
R
R
R
R
R
R
R
R
R
DEVID<23:16>(1)
R
R
DEVID<15:8>(1)
R
R
DEVID<7:0>(1)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 VER<3:0>: Revision Identifier bits(1)
bit 27-0 DEVID<27:0>: Device ID(1)
Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 259
PIC32MX330/350/370/430/450/470
The following are some of the key features of the WDT
module:
27.2 Watchdog Timer (WDT)
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX330/350/370/430/450/
470.
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 27-1:
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
PWRT
LPRC
Oscillator
1
Clock
25-bit Counter
25
WDTCLR = 1
WDT Enable
Wake
Device Reset
NMI (Wake-up)
0
1
WDT Counter Reset
WDT Enable
Reset Event
Power Save
Decoder
FWDTPS<4:0> (DEVCFG1<20:16>)
DS60001185B-page 260
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
REGISTER 27-7: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
25/17/9/1
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
U-0
31:24
23:16
15:8
7:0
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
U-0
—
—
—
—
—
—
—
R/W-0
ON(1,2)
U-0
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
U-0
—
R-y
—
—
R-y
R-y
R-y
R-y
R/W-0
R/W-0
—
SWDTPS<4:0>
WDTWINEN WDTCLR
x = Bit is unknown
Legend:
y = Values set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ON: Watchdog Timer Enable bit(1,2)
1= Enables the WDT if it is not enabled by the device configuration
0= Disable the WDT if it was enabled in software
bit 14-7 Unimplemented: Read as ‘0’
bit 6-2
SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits.
bit 1
WDTWINEN: Watchdog Timer Window Enable bit
1= Enable windowed Watchdog Timer
0= Disable windowed Watchdog Timer
bit 0
WDTCLR: Watchdog Timer Reset bit
1= Writing a ‘1’ will clear the WDT
0= Software cannot force this bit to a ‘0’
Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2012-2013 Microchip Technology Inc.
Preliminary
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PIC32MX330/350/370/430/450/470
27.3 On-Chip Voltage Regulator
27.4 Programming and Diagnostics
PIC32MX330/350/370/430/450/470 devices provide a
complete range of programming and diagnostic fea-
tures that can increase the flexibility of any application
using them. These features allow system designers to
include:
All PIC32MX330/350/370/430/450/470 devices’ core
and digital logic are designed to operate at a nominal
1.8V. To simplify system designs, most devices in the
PIC32MX330/350/370/430/450/470 family incorporate
an on-chip regulator providing the required core logic
voltage from VDD.
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
A low-ESR capacitor (such as tantalum) must be
connected to the VCAP pin (see Figure 27-2). This
helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Section 30.1 “DC Characteristics”.
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
Note:
It is important that the low-ESR capacitor
is placed as close as possible to the VCAP
pin.
• JTAG boundary scan testing for device and board
diagnostics
PIC32 devices incorporate two programming and diag-
nostic modules, and a trace controller, that provide a
range of functions to the application developer.
27.3.1
HIGH VOLTAGE DETECT (HVD)
The HVD module monitors the core voltage at the VCAP
pin. If a voltage above the required level is detected on
VCAP, the I/O pins are disabled and the device is held
in Reset as long as the HVD condition persists. See
parameter HV10 (VHVD) in Table 30-11 in Section 30.1
“DC Characteristics” for more information.
FIGURE 27-3:
BLOCK DIAGRAM OF
PROGRAMMING,
DEBUGGING AND TRACE
PORTS
27.3.2
ON-CHIP REGULATOR AND POR
PGEC1
PGED1
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
ICSP™
Controller
PGEC3
PGED3
27.3.3
ON-CHIP REGULATOR AND BOR
PIC32MX330/350/370/430/450/470 devices also have
a simple brown-out capability. If the voltage supplied to
the regulator is inadequate to maintain a regulated
level, the regulator Reset circuitry will generate a
Brown-out Reset. This event is captured by the BOR
flag bit (RCON<1>). The brown-out voltage levels are
specific in Section 30.1 “DC Characteristics”.
ICESEL
TDI
TDO
TCK
TMS
JTAG
Core
Controller
FIGURE 27-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
JTAGEN DEBUG<1:0>
3.3V(1)
TRCLK
TRD0
TRD1
TRD2
TRD3
PIC32
VDD
Instruction Trace
Controller
VCAP
VSS
(2,3)
CEFC
(10 F typ)
DEBUG<1:0>
Note 1: These are typical operating voltages. Refer to
Section 30.1 “DC Characteristics” for the full
operating ranges of VDD.
2: It is important that the low-ESR capacitor is
placed as close as possible to the VCAP pin.
3: The typical voltage on the VCAP pin is 1.8V.
DS60001185B-page 262
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
28.0 INSTRUCTION SET
The PIC32MX330/350/370/430/450/470 family instruc-
tion set complies with the MIPS32® Release 2 instruc-
tion set architecture. The PIC32 device family does not
support the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.mips.com for
more information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 263
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 264
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
29.1 MPLAB Integrated Development
Environment Software
29.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
- MPLAB ICD 3
IAR C Compilers
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 265
PIC32MX330/350/370/430/450/470
29.2 MPLAB C Compilers for Various
Device Families
29.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
29.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
29.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS60001185B-page 266
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
29.7 MPLAB SIM Software Simulator
29.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
29.10 PICkit 3 In-Circuit Debugger/
Programmer and
29.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2012-2013 Microchip Technology Inc.
Preliminary
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PIC32MX330/350/370/430/450/470
29.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
29.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
29.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS60001185B-page 268
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2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX330/350/370/430/450/470 electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX330/350/370/430/450/470 devices are listed below. Exposure to these
maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these
or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias.............................................................................................................-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +6.0V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on D+ or D- pin with respect to VUSB3V3 ..................................................................... -0.3V to (VUSB3V3 + 0.3V)
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s).......................................................................................................................200 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................200 mA
Maximum output current sourced/sunk by any 4x I/O pin.......................................................................................15 mA
Maximum output current sourced/sunk by any 8x I/O pin.......................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................150 mA
Maximum current sourced by all ports (Note 2)....................................................................................................150 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
4: All specifications in this section are Preliminary, with the exception of the Power-Down Current for
PIC32MX350/450 devices, which are Advance Information (see Table 30-7).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 269
PIC32MX330/350/370/430/450/470
30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS VS. VOLTAGE
Max. Frequency
VDD Range
(in Volts)
Temp. Range
(in °C)
Characteristic
PIC32MX330/350/370/430/450/470
DC5
2.3-3.6V(1)
2.3-3.6V(1)
-40°C to +85°C
-40°C to +105°C
80 MHz
80 MHz
DC5b
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 30-10 for VBORMIN values.
TABLE 30-2: THERMAL OPERATING CONDITIONS
Rating
Industrial Temperature Devices
Symbol
Min.
Typical
Max.
Unit
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
V-temp Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+105
°C
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
Notes
Package Thermal Resistance, 64-pin QFN (9x9x0.9 mm)
Package Thermal Resistance, 64-pin TQFP (10x10x1 mm)
Package Thermal Resistance, 100-pin TQFP (12x12x1 mm)
Package Thermal Resistance, 100-pin TQFP (14x14x1 mm)
Package Thermal Resistance, 124-pin VTLA
JA
JA
JA
JA
JA
28
47
43
43
21
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS60001185B-page 270
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max. Units
Conditions
Operating Voltage
DC10
DC12
VDD
VDR
Supply Voltage
2.3
—
—
3.6
—
V
V
—
—
RAM Data Retention Voltage
(Note 1)
1.75
DC16
DC17
VPOR
SVDD
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
1.75
—
—
2.1
V
—
—
VDD Rise Rate
0.00005
0.115 V/s
to Ensure Internal
Power-on Reset Signal
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2012-2013 Microchip Technology Inc.
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DS60001185B-page 271
PIC32MX330/350/370/430/450/470
TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERIS-
TICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Parameter
Typical(3) Maximum
Units
Conditions
No.
Operating Current (IDD)(1,2)
DC20
DC21
DC22
DC23
DC24
DC25
DC26
2.5
6
4
mA
mA
mA
mA
mA
mA
µA
4 MHz
9
10 MHz (Note 4)
20 MHz (Note 4)
40 MHz (Note 4)
60 MHz (Note 4)
80 MHz
11
17
32
45
60
—
21
30
40
100
+25ºC, 3.3V
LPRC (31 kHz) (Note 4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating (ON bit = 0), but the associated PMD bit is clear
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1)statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
DS60001185B-page 272
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Parameter
Typical(2)
No.
Maximum
Units
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1)
DC30a
DC31a
DC32a
DC33a
DC34a
DC34b
DC37a
DC37b
DC37c
1
3
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
4 MHz
5
10 MHz (Note 3)
20 MHz (Note 3)
40 MHz (Note 3)
60 MHz (Note 3)
80 MHz
5
7
8
13
18
24
—
—
—
11
15
100
250
380
-40°C
+25°C
+85°C
LPRC (31 kHz)
(Note 3)
3.3V
Note 1: The test conditions for IIDLE measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode (CPU core is halted), program Flash memory Wait states = 7, Program Cache
and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 273
PIC32MX330/350/370/430/450/470
TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTER-
ISTICS
Param.
No.
Typical(2) Maximum Units
Conditions
PIC32MX330/430 Devices Only
Power-Down Current (IPD) (Note 1)
DC40k
DC40l
12
21
16
28
A
A
A
µA
-40°C
+25°C
+85°C
+105ºC
Base Power-Down Current
DC40n
DC40m
128
261
167
419
Module Differential Current
DC41e
DC42e
DC43d
6.7
—
—
—
A
A
A
3V
3V
3V
Watchdog Timer Current: IWDT (Note 3)
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
ADC: IADC (Notes 3,4)
29.1
1000
PIC32MX350/450 Devices Only (Note 5)
Power-Down Current (IPD) (Note 1)
DC40k
DC40l
12
26
19
42
A
A
A
µA
-40°C
+25°C
+85°C
+105ºC
Base Power-Down Current
DC40n
DC40m
220
468
352
749
Module Differential Current
DC41e
DC42e
DC43d
6.7
—
—
—
A
A
A
3V
3V
3V
Watchdog Timer Current: IWDT (Note 3)
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
ADC: IADC (Notes 3,4)
29.1
1000
Note 1: The test conditions for IPD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are dis-
abled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
• Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0)
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: The Power-Down Current specifications for PIC32MX350/450 devices is Advance Information.
DS60001185B-page 274
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Symb.
Characteristics
Min.
Typ.(1)
Max.
Units
Conditions
Input Low Voltage
I/O Pins with PMP
I/O Pins
VIL
DI10
VSS
VSS
VSS
—
—
—
0.15 VDD
0.2 VDD
0.3 VDD
V
V
V
DI18
DI19
SDAx, SCLx
SMBus disabled
(Note 4)
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
Input High Voltage
VIH
DI20
I/O Pins not 5V-tolerant(5)
0.65 VDD
—
—
VDD
5.5
V
V
(Note 4,6)
(Note 4,6)
I/O Pins 5V-tolerant with
PMP(5)
I/O Pins 5V-tolerant(5)
0.25 VDD + 0.8V
0.65 VDD
0.65 VDD
—
—
5.5
5.5
V
V
DI28
DI29
SDAx, SCLx
SMBus disabled
(Note 4,6)
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V VPIN 5.5
(Note 4,6)
DI30
DI31
ICNPU Change Notification
50
—
250
50
400
—
A VDD = 3.3V, VPIN = VSS
Pull-up Current
(Note 6)
ICNPD Change Notification
µA VDD = 3.3V, VPIN = VDD
Pull-down Current(4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V tolerant pins.
6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the user-
selectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32
device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided
that the external load does not exceed the minimum value of ICNPU. For External “input” logic inputs that
require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use
an external pull-up resistor rather than the internal pull-ups of the PIC32 device.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD
+ 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the spec-
ified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD +
0.3), injection current = 0.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 275
PIC32MX330/350/370/430/450/470
TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
DC CHARACTERISTICS
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Symb.
Characteristics
Min.
Typ.(1)
Max.
Units
Conditions
Input Leakage Current
(Note 3)
IIL
DI50
I/O Ports
—
—
—
—
+1
+1
A VSS VPIN VDD,
Pin at high-impedance
DI51
Analog Input Pins
A VSS VPIN VDD,
Pin at high-impedance
DI55
DI56
MCLR(2)
OSC1
—
—
—
—
+1
+1
A VSS VPIN VDD
A VSS VPIN VDD,
XT and HS modes
Pins with Analog functions.
Exceptions: [N/A] = 0 mA
max
Digital 5V tolerant desig-
mA nated pins. Exceptions:
[N/A] = 0 mA max
Input Low Injection
Current
DI60a IICL
0
—
-5(7,10)
Digital non-5V tolerant desig-
nated pins. Exceptions:
[N/A] = 0 mA max
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V tolerant pins.
6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the user-
selectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32
device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided
that the external load does not exceed the minimum value of ICNPU. For External “input” logic inputs that
require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use
an external pull-up resistor rather than the internal pull-ups of the PIC32 device.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD
+ 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the spec-
ified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD +
0.3), injection current = 0.
DS60001185B-page 276
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Symb.
Characteristics
Min.
Typ.(1)
Max.
Units
Conditions
Pins with Analog functions.
Exceptions: [SOSCI] = 0 mA
max.
Digital 5V tolerant desig-
Input High Injection
Current
nated pins (VIH < 5.5V)(9)
Exceptions: [All] = 0 mA
max.
.
DI60b IICH
0
—
—
+5(8,9,10) mA
Digital non-5V tolerant desig-
nated pins. Exceptions:
[N/A] = 0 mA max.
DI60c IICT Total Input Injection
Current (sum of all I/O
-20(11)
+20(11)
mA Absolute instantaneous sum
of all ± input injection cur-
rents from all I/O pins
and control pins)
( | IICL + | IICH | ) IICT
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V tolerant pins.
6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the user-
selectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32
device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided
that the external load does not exceed the minimum value of ICNPU. For External “input” logic inputs that
require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use
an external pull-up resistor rather than the internal pull-ups of the PIC32 device.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD
+ 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the spec-
ified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD +
0.3), injection current = 0.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 277
PIC32MX330/350/370/430/450/470
TABLE 30-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param. Symbol
Characteristic
Min.
Typ. Max. Units
Conditions
Output Low Voltage
I/O Pins:
IOL 9 mA, VDD = 3.3V
4x Sink Driver Pins - All I/O
output pins not defined as 8x
Sink Driver pins
—
—
—
—
—
0.4
0.4
—
V
V
V
V
V
DO10 VOL
Output Low Voltage
I/O Pins:
8x Sink Driver Pins - RC15,
RD2, RD10, RF6, RG6
—
IOL 15 mA, VDD = 3.3V
IOH -10 mA, VDD = 3.3V
IOH -15 mA, VDD = 3.3V
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Source Driver pins
2.4
DO20 VOH
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15,
RD2, RD10, RF6, RG6
2.4
—
1.5(1)
2.0(1)
—
—
—
—
IOH -14 mA, VDD = 3.3V
IOH -12 mA, VDD = 3.3V
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Sink Driver pins
3.0(1)
—
—
IOH -7 mA, VDD = 3.3V
DO20A VOH1
1.5(1)
2.0(1)
3.0(1)
—
—
—
—
—
—
IOH -22 mA, VDD = 3.3V
IOH -18 mA, VDD = 3.3V
IOH -10 mA, VDD = 3.3V
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15,
RD2, RD10, RF6, RG6
V
Note 1: Parameters are characterized, but not tested.
DS60001185B-page 278
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-10: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.(1) Typical Max. Units
2.0 2.3
Conditions
VBOR
BOR Event on VDD transition
high-to-low
—
V
—
BO10
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
TABLE 30-11: ELECTRICAL CHARACTERISTICS: HVD
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.(1)
Characteristics
Min. Typical Max. Units
2.5
Conditions
VHVD
High Voltage Detect on VCAP
pin
—
—
V
—
HV10
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 279
PIC32MX330/350/370/430/450/470
TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min. Typical(1) Max. Units
Conditions
Program Flash Memory(3)
Cell Endurance
D130
D131
D132
D134
EP
20,000
2.3
—
—
—
—
—
3.6
3.6
—
E/W
V
—
—
—
VPR
VDD for Read
VPEW
TRETD
VDD for Erase or Write
Characteristic Retention
2.3
V
20
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
—
TWW
TRW
TPE
TCE
Word Write Cycle Time
Row Write Cycle Time(2)
Page Erase Cycle Time
Chip Erase Cycle Time
44
2.8
22
86
—
3.3
—
59
3.8
29
µs
ms
ms
ms
—
—
—
—
D136
D137
—
116
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 8 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
TABLE 30-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATE
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +105°C for V-temp
Required Flash Wait States
SYSCLK
Units
Conditions
0 Wait State
1 Wait State
2 Wait States
0-30
31-60
61-80
MHz
MHz
MHz
—
—
—
DS60001185B-page 280
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-14: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Input Offset Voltage
Min. Typical Max.
Units
Comments
D300
VIOFF
—
0
±7.5
—
±25
VDD
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
D303
CMRR
TRESP
Common Mode Rejection Ratio
Response Time
55
—
—
—
dB
ns
Max VICM = (VDD - 1)V
(Note 2)
150
400
AVDD = VDD,
AVSS = VSS
(Notes 1,2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305
D312
IVREF
TSET
Internal Voltage Reference
1.14
—
1.2
—
1.26
10
V
—
—
Internal Voltage Reference
µs
Setting time (Note 3)
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2: These parameters are characterized but not tested.
3: Settling time measured while CVRR = 1and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
TABLE 30-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics
Min. Typical Max. Units
10
Comments
D321
CEFC
External Filter Capacitor Value
8
—
F Capacitor must be low series
resistance (1 ohm). Typical
voltage on the VCAP pin is
1.8V.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 281
PIC32MX330/350/370/430/450/470
30.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX330/350/370/430/450/470 AC characteristics
and timing parameters.
FIGURE 30-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics
Min. Typical(1) Max. Units
Conditions
In XT and HS modes when an
DO50
COSCO
OSC2 pin
—
—
15
pF external crystal is used to drive
OSC1
DO56
DO58
CIO
CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-2:
EXTERNAL CLOCK TIMING
OS30
OS31
OS20
OSC1
OS31
OS30
DS60001185B-page 282
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
OS10
FOSC
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
80
80
MHz EC (Note 4)
MHz ECPLL (Note 3)
OS11
OS12
Oscillator Crystal Frequency
3
4
—
—
10
10
MHz XT (Note 4)
MHz XTPLL
(Notes 3,4)
OS13
OS14
10
10
—
—
25
25
MHz HS (Note 5)
MHz HSPLL
(Notes 3,4)
OS15
OS20
32
—
32.768
—
100
—
kHz SOSC (Note 4)
TOSC
TOSC = 1/FOSC = TCY (Note 2)
—
See parameter
OS10 for FOSC
value
OS30
OS31
OS40
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
—
0.05 x TOSC
—
ns
ns
EC (Note 4)
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
EC (Note 4)
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
1024
TOSC (Note 4)
OS41
OS42
TFSCM
GM
Primary Clock Fail Safe
Time-out Period
—
—
2
—
—
ms (Note 4)
External Oscillator
Transconductance
12
mA/V VDD = 3.3V,
TA = +25°C
(Note 4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
3: PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
4: This parameter is characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 283
PIC32MX330/350/370/430/450/470
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics(1)
Min.
Typical
Max. Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
3.92
—
5
MHz ECPLL, HSPLL, XTPLL,
FRCPLL modes
OS51
FSYS
On-Chip VCO System
60
—
120
MHz
—
Frequency
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability(2)
(Period Jitter or Cumulative)
—
—
—
2
ms
%
—
-0.25
+0.25
Measured over 100 ms
period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
DCLK
EffectiveJitter = --------------------------------------------------------------
SYSCLK
---------------------------------------------------------
CommunicationClock
For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
DCLK
DCLK
EffectiveJitter = ------------- = -------------
1.41
40
-----
20
TABLE 30-19: INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
AC CHARACTERISTICS
-40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
Characteristics
Min. Typical Max.
Units
Conditions
No.
Internal FRC Accuracy @ 8.00 MHz(1)
F20b FRC -0.9
—
+0.9
%
—
Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
Characteristics
Min. Typical Max.
Units
Conditions
No.
LPRC @ 31.25 kHz(1)
F21 LPRC
Note 1: Change of LPRC frequency as VDD changes.
-15
—
+15
%
—
DS60001185B-page 284
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(2)
Min.
Typical(1)
Max.
Units
Conditions
DO31
TIOR
Port Output Rise Time
Port Output Fall Time
—
—
—
—
10
2
5
5
15
10
15
10
—
—
ns
ns
VDD < 2.5V
VDD > 2.5V
VDD < 2.5V
VDD > 2.5V
—
DO32
TIOF
5
ns
5
ns
DI35
DI40
TINP
INTx Pin High or Low Time
—
—
ns
TRBP
CNx High or Low Time (input)
TSYSCLK
—
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 285
PIC32MX330/350/370/430/450/470
FIGURE 30-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
SY10
(TOST)
(Note 1)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
DS60001185B-page 286
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PIC32MX330/350/370/430/450/470
FIGURE 30-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(SY10)
TABLE 30-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
—
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
TSYSDLY System Delay Period:
Time Required to Reload Device
—
400
600
s
SY02
—
s +
8 SYSCLK
cycles
—
—
—
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
—
SY20
SY30
TMCLR
TBOR
MCLR Pulse Width (low)
BOR Pulse Width (low)
2
—
1
—
—
s
s
—
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 287
PIC32MX330/350/370/430/450/470
FIGURE 30-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 30-1 for load conditions.
(1)
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(2)
Min.
Typical Max. Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK Synchronous, [(12.5 ns or 1 TPB)/N]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter TA15
High Time with prescaler
+ 25 ns
10
Asynchronous,
ns
—
with prescaler
TxCK
Synchronous, [(12.5 ns or 1 TPB)/N]
ns Must also meet
parameter TA15
Low Time
with prescaler
+ 25 ns
Asynchronous,
10
ns
—
with prescaler
TxCK
Synchronous,
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
ns VDD > 2.7V
ns VDD < 2.7V
Input Period with prescaler
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
Asynchronous,
with prescaler
20
50
32
ns VDD > 2.7V
(Note 3)
ns VDD < 2.7V
(Note 3)
OS60 FT1
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
100 kHz
—
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
—
1
TPB
—
Note 1: Timer1 is a Type A.
2: This parameter is characterized, but not tested in manufacturing.
3: N = Prescale Value (1, 8, 64, 256).
DS60001185B-page 288
Preliminary
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PIC32MX330/350/370/430/450/470
TABLE 30-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Max. Units
Conditions
TB10 TTXH
TB11 TTXL
TB15 TTXP
TxCK
High Time prescaler
Synchronous, with [(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns Must also meet N = prescale
parameter
TB15
value
(1, 2, 4, 8,
16, 32, 64,
256)
TxCK
Low Time prescaler
Synchronous, with [(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns Must also meet
parameter
TB15
TxCK
Input
Period
Synchronous, with [(Greater of [(25 ns or
—
—
1
ns VDD > 2.7V
ns VDD < 2.7V
prescaler
2 TPB)/N] + 30 ns
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
TB20 TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
—
TPB
—
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 30-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics(1)
Min.
Max. Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
—
ns
ns
ns
Must also
meet
parameter
IC15.
N = prescale
value (1, 4, 16)
IC11
IC15
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
Must also
meet
parameter
IC15.
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns
—
Note 1: These parameters are characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 289
PIC32MX330/350/370/430/450/470
FIGURE 30-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
OC10
OC11
TCCF
TCCR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter DO32
See parameter DO31
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
Note: Refer to Figure 30-1 for load conditions.
OCx is tri-stated
TABLE 30-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param
Symbol
No.
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
OC20
TFD
Fault Input to PWM I/O Change
Fault Input Pulse Width
—
—
—
50
—
ns
ns
—
—
TFLT
50
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS60001185B-page 290
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SCKx Output Low Time
(Note 3)
SP10
SP11
SP20
SP21
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCK/2
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
—
SCKx Output High Time
(Note 3)
—
TSCK/2
—
SCKx Output Fall Time
(Note 4)
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
SCKx Output Rise Time
(Note 4)
—
—
—
—
—
—
—
SDOx Data Output Fall Time
(Note 4)
—
SDOx Data Output Rise Time
(Note 4)
—
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
10
—
—
—
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
—
15
20
—
SP40
SP41
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
to SCKx Edge
—
—
ns
—
10
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 291
PIC32MX330/350/370/430/450/470
FIGURE 30-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP20
LSb
MSb
Bit 14 - - - - - -1
SDOX
SDIX
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
TSCL
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
SP11
SP20
SP21
SP30
SCKx Output Low Time (Note 3) TSCK/2
SCKx Output High Time (Note 3) TSCK/2
—
—
—
—
—
—
—
—
—
—
ns
ns
—
—
TSCH
TSCF
TSCR
TDOF
SCKx Output Fall Time (Note 4)
SCKx Output Rise Time (Note 4)
—
—
—
ns See parameter DO32
ns See parameter DO31
ns See parameter DO32
SDOx Data Output Fall Time
(Note 4)
SP31
SP35
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns See parameter DO31
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
—
—
—
15
20
—
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
SP36
SP40
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
—
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
15
20
15
20
—
—
—
—
—
—
—
—
ns
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
VDD > 2.7V
VDD < 2.7V
SP41
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL
to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS60001185B-page 292
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2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SP72
SCKX
(CKP = 1)
SP35
MSb
LSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2) Max. Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
TSCK/2
TSCK/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
—
—
ns See parameter DO32
ns See parameter DO31
ns See parameter DO32
ns See parameter DO31
ns VDD > 2.7V
SCKx Input Rise Time
—
SDOx Data Output Fall Time (Note 4)
SDOx Data Output Rise Time (Note 4)
—
—
SP35 TSCH2DOV, SDOx Data Output Valid after
—
TSCL2DOV SCKx Edge
—
ns VDD < 2.7V
SP40 TDIV2SCH, Setup Time of SDIx Data Input
10
ns
ns
ns
ns
ns
—
—
—
—
—
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input
10
175
—
—
—
—
—
—
25
—
TSCL2DIL to SCKx Edge
SP50 TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
SP51 TSSH2DOZ SSx to SDOx Output
High-Impedance (Note 3)
5
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK + 20
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 293
PIC32MX330/350/370/430/450/470
FIGURE 30-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
MSb
Bit 14 - - - - - -1
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
TSCL
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SP70
SP71
SP72
SP73
SP30
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
TSCK/2
TSCK/2
—
—
—
5
—
—
10
10
—
ns
ns
ns
ns
—
—
—
—
TSCH
TSCF
TSCR
TDOF
SCKx Input Rise Time
—
5
SDOx Data Output Fall Time
—
—
ns See parameter DO32
(Note 4)
SP31
SP35
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns See parameter DO31
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
10
—
—
—
20
30
—
ns VDD > 2.7V
ns VDD < 2.7V
SP40
SP41
SP50
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
ns
ns
ns
—
—
—
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL
10
—
—
—
—
to SCKx Edge
TSSL2SCH, SSx to SCKx or SCKx Input
175
TSSL2SCL
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
DS60001185B-page 294
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance
5
—
25
ns
—
(Note 4)
SP52
SP60
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
—
ns
ns
—
—
TSSL2DOV SDOx Data Output Valid after
—
25
SSx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 295
PIC32MX330/350/370/430/450/470
FIGURE 30-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
DS60001185B-page 296
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.(1)
Max.
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
—
—
—
1 MHz mode
(Note 2)
THI:SCL Clock High Time 100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
—
—
—
1 MHz mode
(Note 2)
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
300
300
100
ns
ns
ns
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode
(Note 2)
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
1000
300
ns
ns
ns
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode
(Note 2)
300
TSU:DAT Data Input
100 kHz mode
400 kHz mode
250
100
100
—
—
—
ns
ns
ns
—
—
Setup Time
1 MHz mode
(Note 2)
THD:DAT Data Input
100 kHz mode
400 kHz mode
0
0
0
—
s
s
s
Hold Time
0.9
0.3
1 MHz mode
(Note 2)
TSU:STA Start Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode
1 MHz mode
(Note 2)
THD:STA Start Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
After this period, the
first clock pulse is
generated
Hold Time
400 kHz mode
1 MHz mode
(Note 2)
TSU:STO Stop Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
—
Setup Time
400 kHz mode
1 MHz mode
(Note 2)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
ns
ns
ns
—
1 MHz mode
(Note 2)
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: The typical value for this parameter is 104 ns.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 297
PIC32MX330/350/370/430/450/470
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics
Min.(1)
Max.
Units
Conditions
IM40
TAA:SCL Output Valid
from Clock
100 kHz mode
400 kHz mode
—
—
—
3500
1000
350
ns
ns
ns
—
—
—
1 MHz mode
(Note 2)
IM45
TBF:SDA Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
—
—
s
s
s
The amount of time the
bus must be free
before a new
1 MHz mode
(Note 2)
transmission can start
IM50
IM51
CB
Bus Capacitive Loading
Pulse Gobbler Delay
—
400
312
pF
ns
—
TPGD
52
See Note 3
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: The typical value for this parameter is 104 ns.
DS60001185B-page 298
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 299
PIC32MX330/350/370/430/450/470
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Max. Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
—
—
—
—
—
s
s
s
s
s
s
PBCLK must operate at a
minimum of 800 kHz
1.3
0.5
4.0
0.6
0.5
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
—
IS11
THI:SCL
Clock High Time 100 kHz mode
400 kHz mode
PBCLK must operate at a
minimum of 800 kHz
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
—
(Note 1)
IS20
IS21
IS25
IS26
IS30
IS31
IS33
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
300
300
100
ns
ns
ns
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode
(Note 1)
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
1000
300
ns
ns
ns
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode
(Note 1)
300
TSU:DAT Data Input
100 kHz mode
400 kHz mode
250
100
100
—
—
—
ns
ns
ns
—
—
Setup Time
1 MHz mode
(Note 1)
THD:DAT Data Input
100 kHz mode
400 kHz mode
0
0
0
—
ns
s
s
Hold Time
0.9
0.3
1 MHz mode
(Note 1)
TSU:STA Start Condition
100 kHz mode
400 kHz mode
4700
600
—
—
—
ns
ns
ns
Only relevant for Repeated
Start condition
Setup Time
1 MHz mode
(Note 1)
250
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
4000
600
—
—
—
ns
ns
ns
After this period, the first
clock pulse is generated
1 MHz mode
(Note 1)
250
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
4000
600
—
—
—
ns
ns
ns
—
1 MHz mode
600
(Note 1)
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS60001185B-page 300
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Characteristics
Min.
Max. Units
Conditions
IS34
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
4000
600
—
—
ns
ns
ns
—
1 MHz mode
250
(Note 1)
IS40
IS45
IS50
TAA:SCL
Output Valid from 100 kHz mode
0
0
0
3500
1000
350
ns
ns
ns
—
Clock
400 kHz mode
1 MHz mode
(Note 1)
TBF:SDA Bus Free Time
100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
—
—
s
s
s
The amount of time the bus
must be free before a new
transmission can start
1 MHz mode
(Note 1)
CB
Bus Capacitive Loading
—
400
pF
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 301
PIC32MX330/350/370/430/450/470
TABLE 30-34: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS(5)
Param.
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
No.
Device Supply
AD01
AVDD
Module VDD Supply
Module VSS Supply
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
AD02
AVSS
VSS
—
VSS + 0.3
Reference Inputs
AD05
AD05a
AD06
AD07
VREFH
Reference Voltage High AVSS + 2.0
2.5
—
—
—
—
AVDD
3.6
V
V
V
V
(Note 1)
VREFH = AVDD (Note 3)
(Note 1)
VREFL
VREF
Reference Voltage Low
AVSS
2.0
VREFH – 2.0
AVDD
Absolute Reference
(Note 3)
Voltage (VREFH – VREFL)
AD08
IREF
Current Drain
—
250
—
400
3
A ADC operating
A ADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span
VREFL
—
—
VREFH
V
V
—
—
AD13
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
AVDD/2
AD14
AD15
VIN
Absolute Input Voltage
Leakage Current
AVSS – 0.3
—
—
AVDD + 0.3
V
—
+/- 0.001 +/-0.610
A VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
AD17
RIN
Recommended
—
—
5K
(Note 1)
Impedance of Analog
Voltage Source
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr
Resolution
10 data bits
—
bits
—
AD21c INL
Integral Nonlinearity
> -1
> -1
< 1
< 1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL
Differential Nonlinearity
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR
AD24n EOFF
Gain Error
> -1
> -1
—
—
—
—
< 1
< 1
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Offset Error
Monotonicity
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c
—
—
Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 30-10 for VBORMIN values.
DS60001185B-page 302
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-34: ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS(5)
Param.
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
No.
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr
Resolution
10 data bits
—
bits (Note 3)
AD21d INL
Integral Nonlinearity
> -1
> -1
> -4
> -2
—
< 1
< 1
< 4
< 2
—
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL
AD23d GERR
AD24d EOFF
Differential Nonlinearity
Gain Error
—
—
—
—
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2,3)
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
Offset Error
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d
—
Monotonicity
—
Guaranteed
Dynamic Performance
AD31b SINAD
Signal to Noise and
Distortion
55
9
58
—
—
dB (Notes 3,4)
bits (Notes 3,4)
AD34b ENOB
Effective Number of Bits
9.5
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 30-10 for VBORMIN values.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 303
PIC32MX330/350/370/430/450/470
TABLE 30-35: 10-BIT CONVERSION RATE PARAMETERS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS(2)
Sampling
Time
TAD
Min.
RS
Max.
ADC Input
ADC Speed
VDD
ADC Channels Configuration
Min.
AN0-AN14 1 Msps to 400 65 ns
ksps(1)
132 ns
500 3.0V to 3.6V
VREF- VREF+
CHX
SHA
ANx
ADC
Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V
VREF- VREF+
or
or
AVSS AVDD
CHX
SHA
ANx
ADC
ANx or VREF-
AN15-AN27 400 ksps(1)
154 ns 1000 ns 500 3.0V to 3.6V
VREF- VREF+
CHX
SHA
ANx
ADC
Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
DS60001185B-page 304
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1) Max.
Units
Conditions
Clock Parameters
AD50
TAD
ADC Clock Period(2)
65
—
—
ns
—
See Table 30-35
—
Conversion Rate
AD55
AD56
TCONV
FCNV
Conversion Time
—
—
12 TAD
—
—
1000
400
—
Throughput Rate
ksps AVDD = 3.0V to 3.6V
ksps AVDD = 2.5V to 3.6V
(Sampling Speed)(4)
—
—
AD57
TSAMP
Sample Time
1 TAD
—
—
TSAMP must be 132 ns
Timing Parameters
AD60
TPCS
Conversion Start from Sample
—
1.0 TAD
—
—
Auto-Convert Trigger
(SSRC<2:0> = 111)
not selected
Trigger(3)
AD61
AD62
AD63
TPSS
TCSS
TDPU
Sample Start from Setting
Sample (SAMP) bit
0.5 TAD
—
—
0.5 TAD
—
1.5 TAD
—
—
s
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(3)
—
2
Time to Stabilize Analog Stage
—
from ADC Off to ADC On(3)
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.
4: Refer to Table 30-35 for detailed conditions.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 305
PIC32MX330/350/370/430/450/470
FIGURE 30-18:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING
CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
TSAMP
AD55
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)”
(DS60001104) in the “PIC32 Family Reference Manual”.
– Software clears ADxCON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 9.
3
4
5
6
7
8
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
DS60001185B-page 306
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-19:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
eoc
TSAMP
TSAMP
AD55
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
– Software sets ADxCON. ADON to start AD operation.
– Sampling starts after discharge period.
TSAMP is described in Section 17. “10-bit Analog-to-Digital
Converter (ADC)” (DS60001104) in the
– Convert bit 0.
1
2
5
6
7
8
– One TAD for end of conversion.
– Begin conversion of next channel.
– Sample for time specified by SAMC<4:0>.
“PIC32 Family Reference Manual”
– Convert bit 9.
– Convert bit 8.
3
4
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 307
PIC32MX330/350/370/430/450/470
FIGURE 30-20:
PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4
PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 30-37: PARALLEL SLAVE PORT REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Para
Symbol
m.No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
PS1 TdtV2wr Data In Valid before WR or CS
Inactive (setup time)
20
—
—
ns
—
H
PS2 TwrH2dt WR or CS Inactive to Data-In
Invalid (hold time)
40
—
0
—
—
—
—
60
10
ns
ns
ns
—
—
—
I
PS3 TrdL2dt RD and CS Active to Data-Out
Valid
V
PS4 TrdH2dtI RD Activeor CS Inactive to
Data-Out Invalid
PS5 Tcs
CS Active Time
WR Active Time
RD Active Time
TPB + 40
TPB + 25
TPB + 25
—
—
—
—
—
—
ns
ns
ns
—
—
—
PS6
PS7
TWR
TRD
Note 1: These parameters are characterized, but not tested in manufacturing.
DS60001185B-page 308
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-21:
PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
PM4
Address
PMA<13:18>
PMD<7:0>
PM6
Data
Address<7:0>
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 30-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
PM1
PM2
TLAT
PMALL/PMALH Pulse Width
—
—
1 TPB
2 TPB
—
—
—
—
—
—
TADSU
Address Out Valid to PMALL/
PMALH Invalid (address setup
time)
PM3
PM4
TADHOLD PMALL/PMALH Invalid to
Address Out Invalid (address
hold time)
—
5
1 TPB
—
—
—
—
ns
—
—
TAHOLD
PMRD Inactive to Address Out
Invalid
(address hold time)
PM5
PM6
TRD
PMRD Pulse Width
—
1 TPB
—
—
—
—
ns
—
—
TDSU
PMRD or PMENB Active to Data
In Valid (data setup time)
15
PM7
TDHOLD PMRD or PMENB Inactive to
Data In Invalid (data hold time)
—
80
—
ns
—
Note 1: These parameters are characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 309
PIC32MX330/350/370/430/450/470
FIGURE 30-22:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
Address
PMA<13:18>
PM2 + PM3
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PMWR
PM11
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 30-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
PMWR Pulse Width
Min.
Typ.
Max.
Units
Conditions
PM11
TWR
—
—
1 TPB
2 TPB
—
—
—
—
—
—
PM12 TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup
time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data
Out Invalid (data hold time)
—
1 TPB
—
—
—
Note 1: These parameters are characterized, but not tested in manufacturing.
DS60001185B-page 310
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
TABLE 30-40: OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.
Max.
Units
Conditions
USB313 VUSB3V3 USB Voltage
3.0
—
3.6
V
Voltage on VUSB3V3
must be in this range
for proper USB
operation
USB315 VILUSB
USB316 VIHUSB
USB318 VDIFS
Input Low Voltage for USB Buffer
—
2.0
—
—
—
—
0.8
—
V
V
V
—
—
Input High Voltage for USB Buffer
Differential Input Sensitivity
0.2
The difference
between D+ and D-
must exceed this value
while VCM is met
USB319 VCM
USB320 ZOUT
USB321 VOL
Differential Common Mode Range
Driver Output Impedance
Voltage Output Low
0.8
28.0
0.0
—
—
—
2.5
44.0
0.3
V
V
—
—
14.25 k load
connected to 3.6V
USB322 VOH
Voltage Output High
2.8
—
3.6
V
14.25 k load
connected to ground
Note 1: These parameters are characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 311
PIC32MX330/350/370/430/450/470
TABLE 30-41: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions:2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
CTMU CURRENT SOURCE
CTMUI1
CTMUI2
CTMUI3
CTMUI4
IOUT1
IOUT2
IOUT3
IOUT4
Base Range(1)
10x Range(1)
100x Range(1)
1000x Range(1)
—
—
—
—
—
0.55
5.5
—
—
—
—
—
µA CTMUICON<9:8> = 01
µA CTMUICON<9:8> = 10
µA CTMUICON<9:8> = 11
µA CTMUICON<9:8> = 00
55
550
0.598
CTMUFV1 VF
Temperature Diode Forward
Voltage(1,2)
V
V
V
TA = +25ºC,
CTMUICON<9:8> = 01
—
—
0.658
0.721
—
—
TA = +25ºC,
CTMUICON<9:8> = 10
TA = +25ºC,
CTMUICON<9:8> = 11
CTMUFV2 VFVR
Temperature Diode Rate of
Change(1,2)
—
—
—
-1.92
-1.74
-1.56
—
—
—
mV/ºC CTMUICON<9:8> = 01
mV/ºC CTMUICON<9:8> = 10
mV/ºC CTMUICON<9:8> = 11
Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000).
2: Parameters are characterized but not tested in manufacturing. Measurements taken with the following
conditions:
•
•
•
•
•
VREF+ = AVDD = 3.3V
ADC module configured for conversion speed of 500 ksps
All PMD bits are cleared (PMDx = 0)
Executing a while(1)statement
Device operating from the FRC with no PLL
DS60001185B-page 312
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
FIGURE 30-23:
EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
Trf
TTsetup TThold
Trf
TDO
TRST*
TTRST*low
TTDOout
TTDOzstate
Undefined
Defined
Trf
TABLE 30-42: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +105°C for V-temp
Param.
No.
Symbol
Description(1)
TCK Cycle Time
Min.
Max. Units
Conditions
EJ1
TTCKCYC
TTCKHIGH
TTCKLOW
TTSETUP
25
10
10
5
—
—
—
—
ns
ns
ns
ns
—
—
—
—
EJ2
EJ3
EJ4
TCK High Time
TCK Low Time
TAP Signals Setup Time Before
Rising TCK
EJ5
EJ6
EJ7
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
5
ns
ns
ns
—
—
—
TTDOOUT
TDO Output Delay Time from
Falling TCK
—
—
TTDOZSTATE TDO 3-State Delay Time from
Falling TCK
5
EJ8
EJ9
TTRSTLOW
TRF
TRST Low Time
25
—
—
—
ns
ns
—
—
TAP Signals Rise/Fall Time, All
Input and Output
Note 1: These parameters are characterized, but not tested in manufacturing.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 313
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 314
Preliminary
2012-2013 Microchip Technology Inc.
31.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 31-1:
VOH – 4x DRIVER PINS
FIGURE 31-3:
VOL – 4x DRIVER PINS
3.3V
3.3V
Absolute Maximum
Absolute Maximum
FIGURE 31-2:
VOH – 8x DRIVER PINS
FIGURE 31-4:
VOL – 8x DRIVER PINS
3.3V
3.3V
Absolute Maximum
Absolute Maximum
FIGURE 31-5:
TYPICAL IPD CURRENT @ VDD = 3.3V
PIC32MX330/430 DEVICES
FIGURE 31-7:
TYPICAL IIDLE CURRENT @ VDD = 3.3V
PIC32MX330/430 DEVICES
FIGURE 31-6:
TYPICAL IPD CURRENT @ VDD = 3.3V
PIC32MX350/450 DEVICES
FIGURE 31-8:
TYPICAL IIDLE CURRENT @ VDD = 3.3V
PIC32MX350/450 DEVICES
FIGURE 31-9:
TYPICAL IDD CURRENT @ VDD = 3.3V
PIC32MX330/430 DEVICES
FIGURE 31-11:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 31-10:
TYPICAL IDD CURRENT @ VDD = 3.3V
PIC32MX350/450 DEVICES
FIGURE 31-12:
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
FIGURE 31-13:
TYPICAL CTMU TEMPERATURE DIODE
FORWARD VOLTAGE
VF = 0.721
VF = 0.658
VF = 0.598
PIC32MX330/350/370/430/450/470
32.0 PACKAGING INFORMATION
32.1 Package Marking Information
64-Lead TQFP (10x10x1 mm)
Example
PIC32MX330F
064H-I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e
3
0510017
100-Lead TQFP (14x14x1 mm)
Example
PIC32MX330F
064L-I/PF
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e
3
100-Lead TQFP (12x12x1 mm)
Example
PIC32MX330F
064L-I/PT
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 319
PIC32MX330/350/370/430/450/470
32.1 Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX330F
064H-I/MR
e
3
0510017
124-Lead VTLA (9x9x0.9 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX430F
064l-I/TL
e
3
0510017
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS60001185B-page 320
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
32.2 Package Details
The following sections give the technical details of the packages.
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2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 321
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001185B-page 322
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
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2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 323
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001185B-page 324
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
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2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 325
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001185B-page 326
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 327
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS60001185B-page 328
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 329
PIC32MX330/350/370/430/450/470
DS60001185B-page 330
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 331
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 332
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
APPENDIX A: REVISION HISTORY
Revision A (July 2012)
This is the initial released version of the document.
Revision B (April 2013)
Note:
The status of this data sheet was updated
to Preliminary; however, any electrical
specifications listed for PIC32MX370/470
devices is to be considered Advance
Information and is marked accordingly.
This revision includes the following updates, as shown
in Table A-1.
TABLE A-1:
MAJOR SECTION UPDATES
Section
Update Description
“32-bit Microcontrollers (up to 512 SRAM was changed from 32 KB to 64 KB.
KB Flash and 128 KB SRAM) with
Audio/Graphics/Touch (HMI), USB,
and Advanced Analog”
Data Memory (KB) was changed from 32 to 64 for the following devices (see
Table 1):
• PIC32MX350F256H
• PIC32MX350F256L
• PIC32MX450F256H
• PIC32MX450F256L
The following devices were added:
• PIC32MX370F512H
• PIC32MX370F512L
• PIC32MX470F512H
• PIC32MX470F512L
4.0 “Memory Organization”
The Memory Map for Devices with 256 KB of Program Memory was updated
(see Figure 4-3).
The Memory Map for Devices with 512 KB of Program Memory was added
(see Figure 4-4).
7.0 “Interrupt Controller”
Updated the Interrupt IRQ, Vector and Bit Locations (see Table 7-1).
20.0 “Parallel Master Port (PMP)”
Added the CS2 bit and updated the ADDR bits in the Parallel Port Address
register (see Register 20-3).
27.0 “Special Features”
Updated the PWP bit in the Device Configuration Word 3 register (see
Register 27-4).
30.0 “Electrical Characteristics”
Note 2 in the DC Characteristics: Operating Current (IDD) were updated (see
Table 30-5).
Note 1 in the DC Characteristics: Idle Current (IIDLE) were updated (see
Table 30-6).
Note 1 in the DC Characteristics: Power-down Current (IPD) were updated
(see Table 30-7).
Updated Program Memory values for parameters D135 (TWW), D136 (TRW),
and D137 (TPE and TCE) (see Table 30-12).
31.0 “DC and AC Device
Characteristics Graphs”
New IDD, IIDLE, and IPD current graphs were added for PIC32MX330/430
devices and PIC32MX350/450 devices.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 333
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 334
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
INDEX
CPU Module ................................................................. 27, 33
CTMU
Registers .................................................................. 244
Customer Change Notification Service............................. 339
Customer Notification Service .......................................... 339
Customer Support............................................................. 339
A
AC Characteristics ............................................................ 282
10-Bit Conversion Rate Parameters ......................... 304
ADC Specifications ................................................... 302
Analog-to-Digital Conversion Requirements............. 305
EJTAG Timing Requirements ................................... 313
Internal FRC Accuracy.............................................. 284
Internal RC Accuracy................................................ 284
OTG Electrical Specifications ................................... 311
Parallel Master Port Read Requirements ................. 309
Parallel Master Port Write......................................... 310
Parallel Master Port Write Requirements.................. 310
Parallel Slave Port Requirements............................. 308
PLL Clock Timing...................................................... 284
Analog-to-Digital Converter (ADC).................................... 229
Assembler
D
DC and AC Characteristics
Graphs and Tables................................................... 315
DC Characteristics............................................................ 270
I/O Pin Input Specifications ...................................... 275
I/O Pin Output Specifications.................................... 278
Idle Current (IIDLE).................................................... 273
Power-Down Current (IPD)........................................ 274
Program Memory...................................................... 280
Temperature and Voltage Specifications.................. 271
Development Support....................................................... 265
Direct Memory Access (DMA) Controller.......................... 129
MPASM Assembler................................................... 266
B
Block Diagrams
E
ADC Module.............................................................. 229
Comparator I/O Operating Modes............................. 237
Comparator Voltage Reference ................................ 241
Connections for On-Chip Voltage Regulator............. 262
CPU ............................................................................ 33
CTMU Configurations
Electrical Characteristics .................................................. 269
AC............................................................................. 282
Errata.................................................................................. 15
External Clock
Timer1 Timing Requirements ................................... 288
Timer2, 3, 4, 5 Timing Requirements ....................... 289
Timing Requirements ............................................... 283
Time Measurement........................................... 243
DMA.......................................................................... 129
I2C Circuit ................................................................. 200
Input Capture ............................................................ 185
Interrupt Controller.................................................... 101
JTAG Programming, Debugging and Trace Ports .... 262
Output Compare Module........................................... 189
PMP Pinout and Connections to External Devices... 211
Prefetch Module........................................................ 119
Reset System.............................................................. 97
RTCC........................................................................ 219
SPI Module ............................................................... 191
Timer1....................................................................... 177
Timer2/3/4/5 (16-Bit)................................................. 181
Typical Multiplexed Port Structure ............................ 167
UART ........................................................................ 205
WDT and Power-up Timer ........................................ 260
Brown-out Reset (BOR)
F
Flash Program Memory ...................................................... 93
RTSP Operation ......................................................... 93
H
High Voltage Detect (HVD)................................. 98, 262, 279
I
I/O Ports ........................................................................... 167
Parallel I/O (PIO) ...................................................... 168
Write/Read Timing.................................................... 168
Input Change Notification ................................................. 168
Instruction Set................................................................... 263
Inter-Integrated Circuit (I2C .............................................. 199
Internal Voltage Reference Specifications........................ 281
Internet Address ............................................................... 339
Interrupt Controller............................................................ 101
IRG, Vector and Bit Location.................................... 102
and On-Chip Voltage Regulator................................ 262
C
M
C Compilers
MPLAB C18 .............................................................. 266
Charge Time Measurement Unit. See CTMU.
Clock Diagram .................................................................. 110
Comparator
Specifications............................................................ 281
Comparator Module .......................................................... 237
Comparator Voltage Reference (CVref............................. 241
Configuration Bit ............................................................... 251
Configuring Analog Port Pins............................................ 168
CPU
Memory Maps
Devices with 128 KB of Program Memory.................. 39
Devices with 256 KB of Program Memory.................. 40
Devices with 512 KB of Program Memory.................. 41
Devices with 64 KB of Program Memory.................... 38
Memory Organization ......................................................... 37
Layout......................................................................... 37
Microchip Internet Web Site.............................................. 339
MPLAB ASM30 Assembler, Linker, Librarian................... 266
MPLAB Integrated Development Environment Software.. 265
MPLAB PM3 Device Programmer .................................... 268
MPLAB REAL ICE In-Circuit Emulator System ................ 267
MPLINK Object Linker/MPLIB Object Librarian................ 266
Architecture Overview................................................. 34
Coprocessor 0 Registers ............................................ 35
Core Exception Types................................................. 36
EJTAG Debug Support ............................................... 36
Power Management.................................................... 36
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 335
PIC32MX330/350/370/430/450/470
ALRMDATESET (ALRMDATE Set).......................... 227
O
ALRMTIME (Alarm Time Value) ............................... 226
ALRMTIMECLR (ALRMTIME Clear) ........................ 227
ALRMTIMEINV (ALRMTIME Invert) ......................... 227
ALRMTIMESET (ALRMTIME Set)............................ 227
BMXBOOTSZ (Boot Flash (IFM) Size ........................ 92
BMXCON (Bus Matrix Configuration) ......................... 87
BMXDKPBA (Data RAM Kernel Program
Base Address).................................................... 88
BMXDRMSZ (Data RAM Size Register)..................... 91
BMXDUDBA (Data RAM User Data Base Address)... 89
BMXDUPBA (Data RAM User Program
Oscillator Configuration.....................................................109
Output Compare................................................................189
P
Packaging .........................................................................319
Details.......................................................................321
Marking .....................................................................319
Parallel Master Port (PMP) ...............................................211
PIC32 Family USB Interface Diagram...............................146
Pinout I/O Descriptions (table) ............................................18
Power-on Reset (POR)
Base Address).................................................... 90
BMXPFMSZ (Program Flash (PFM) Size).................. 92
BMXPUPBA (Program Flash (PFM) User Program
Base Address).................................................... 91
CHEACC (Cache Access) ........................................ 121
CHECON (Cache Control)........................................ 120
CHEHIT (Cache Hit Statistics).................................. 126
CHELRU (Cache LRU)............................................. 125
CHEMIS (Cache Miss Statistics) .............................. 126
CHEMSK (Cache TAG Mask)................................... 123
CHETAG (Cache TAG)............................................. 122
CHEW0 (Cache Word 0) .......................................... 123
CHEW1 (Cache Word 1) .......................................... 124
CHEW2 (Cache Word 2) .......................................... 124
CHEW3 (Cache Word 3) .......................................... 125
CM1CON (Comparator 1 Control) ............................ 238
CMSTAT (Comparator Control Register).................. 239
CNCONx (Change Notice Control for PORTx)......... 176
CTMUCON (CTMU Control)..................................... 244
CVRCON (Comparator Voltage Reference Control) 242
DCHxCON (DMA Channel x Control)....................... 135
DCHxCPTR (DMA Channel x Cell Pointer) .............. 142
DCHxCSIZ (DMA Channel x Cell-Size).................... 142
DCHxDAT (DMA Channel x Pattern Data) ............... 143
DCHxDPTR (Channel x Destination Pointer) ........... 141
DCHxDSA (DMA Channel x Destination
Start Address)................................................... 139
DCHxDSIZ (DMA Channel x Destination Size) ........ 140
DCHxECON (DMA Channel x Event Control) .......... 136
DCHxINT (DMA Channel x Interrupt Control)........... 137
DCHxSPTR (DMA Channel x Source Pointer) ......... 141
DCHxSSA (DMA Channel x Source Start Address) . 139
DCHxSSIZ (DMA Channel x Source Size) ............... 140
DCRCCON (DMA CRC Control)............................... 132
DCRCDATA (DMA CRC Data)................................. 134
DCRCXOR (DMA CRCXOR Enable) ....................... 134
DEVCFG0 (Device Configuration Word 0................. 251
DEVCFG1 (Device Configuration Word 1................. 253
DEVCFG2 (Device Configuration Word 2................. 255
DEVCFG3 (Device Configuration Word 3................. 257
DEVID (Device and Revision ID).............................. 259
DMAADDR (DMA Address)...................................... 131
DMAADDR (DMR Address)...................................... 131
DMACON (DMA Controller Control) ......................... 130
DMASTAT (DMA Status).......................................... 131
I2CxCON (I2C Control)............................................. 201
I2CxSTAT (I2C Status)............................................. 203
ICxCON (Input Capture x Control)............................ 186
IFSx (Interrupt Flag Status) ...................................... 106
INTCON (Interrupt Control)....................................... 104
INTSTAT (Interrupt Status)....................................... 105
IPCx (Interrupt Priority Control) ................................ 107
IPTMR Interrupt Proximity Timer)............................. 105
and On-Chip Voltage Regulator................................262
Power-Saving Features.....................................................247
CPU Halted Methods ................................................247
Operation ..................................................................247
with CPU Running.....................................................247
Prefetch Cache .................................................................119
R
Reader Response .............................................................340
Real-Time Clock and Calendar (RTCC)............................219
Register Map
ADC ............................................................................52
Bus Matrix...................................................................42
Comparator.................................................................58
Comparator Voltage Reference ..................................58
CTMU..........................................................................83
Device and Revision ID Summary ..............................61
Device Configuration Word Summary.........................61
DMA Channel 0-3 .......................................................55
DMA CRC ...................................................................54
DMA Global.................................................................54
Flash Controller...........................................................59
I2C1 and I2C2.............................................................48
Input Capture 1-5........................................................46
Interrupt.......................................................................43
Output Compare1-5 ....................................................47
Parallel Master Port ....................................................81
Peripheral Pin Select Input .........................................76
Peripheral Pin Select Output.......................................78
PORTA........................................................................62
PORTB........................................................................63
PORTC .................................................................64, 65
PORTD .................................................................66, 67
PORTE..................................................................68, 69
PORTF......................................................70, 71, 72, 73
PORTG .................................................................74, 75
Prefetch.......................................................................82
RTCC..........................................................................83
SPI1 and SPI2 ............................................................51
System Control ...........................................................60
Timer1-5......................................................................45
UART1-5.....................................................................49
USB.............................................................................84
Registers
[pin name]R (Peripheral Pin Select Input).................175
AD1CHS (ADC Input Select) ....................................235
AD1CON1 (A/D Control 1)........................................227
AD1CON1 (ADC Control 1) ..............................227, 231
AD1CON2 (ADC Control 2) ......................................233
AD1CON3 (ADC Control 3) ......................................234
AD1CSSL (ADC Input Scan Select) .........................236
ALRMDATE (Alarm Date Value)...............................227
ALRMDATECLR (ALRMDATE Clear).......................227
DS60001185B-page 336
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
NVMADDR (Flash Address) ....................................... 95
T
NVMCON (Programming Control) .............................. 94
NVMDATA (Flash Program Data)............................... 96
NVMKEY (Programming Unlock)................................ 95
NVMSRCADDR (Source Data Address)..................... 96
OCxCON (Output Compare x Control) ..................... 190
OSCCON (Oscillator Control) ................................... 111
PFABT (Prefetch Cache Abort Statistics) ................. 127
PMADDR (Parallel Port Address) ............................. 216
PMAEN (Parallel Port Pin Enable)............................ 217
PMCON (Parallel Port Control)................................. 212
PMMODE (Parallel Port Mode)................................. 214
PMSTAT (Parallel Port Status (Slave Modes Only).. 218
REFOCON (Reference Oscillator Control) ............... 115
REFOTRIM (Reference Oscillator Trim)................... 117
RPnR (Peripheral Pin Select Output)........................ 175
RSWRST (Software Reset) ........................................ 99
RTCCON (RTC Control) ........................................... 220
RTCDATE (RTC Date Value) ................................... 225
RTCTIME (RTC Time Value).................................... 224
SPIxCON (SPI Control)............................................. 192
SPIxCON2 (SPI Control 2)........................................ 195
SPIxSTAT (SPI Status)............................................. 196
T1CON (Type A Timer Control) ................................ 178
TxCON (Type B Timer Control) ................................ 183
U1ADDR (USB Address) .......................................... 160
U1BDTP1 (USB BDT Page 1) .................................. 162
U1BDTP2 (USB BDT Page 2) .................................. 163
U1BDTP3 (USB BDT Page 3) .................................. 163
U1CNFG1 (USB Configuration 1)............................. 164
U1CON (USB Control).............................................. 158
U1EIE (USB Error Interrupt Enable) ......................... 156
U1EIR (USB Error Interrupt Status).......................... 154
U1EP0-U1EP15 (USB Endpoint Control) ................. 165
U1FRMH (USB Frame Number High)....................... 161
U1FRML (USB Frame Number Low)........................ 160
U1IE (USB Interrupt Enable)..................................... 153
U1IR (USB Interrupt)................................................. 152
U1OTGCON (USB OTG Control) ............................. 150
U1OTGIE (USB OTG Interrupt Enable).................... 148
U1OTGIR (USB OTG Interrupt Status)..................... 147
U1OTGSTAT (USB OTG Status).............................. 149
U1PWRC (USB Power Control)................................ 151
U1SOF (USB SOF Threshold).................................. 162
U1STAT (USB Status) .............................................. 157
U1TOK (USB Token) ................................................ 161
WDTCON (Watchdog Timer Control) ....................... 261
Resets................................................................................. 97
Revision History................................................................ 333
RTCALRM (RTC ALARM Control).................................... 222
Timer1 Module.................................................................. 177
Timer2/3, Timer4/5 Modules............................................. 181
Timing Diagrams
10-Bit Analog-to-Digital Conversion
(ASAM = 0, SSRC<2:0> = 000)........................ 306
10-Bit Analog-to-Digital Conversion (ASAM = 1,
SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 307
EJTAG...................................................................... 313
External Clock .......................................................... 282
I/O Characteristics.................................................... 285
I2Cx Bus Data (Master Mode).................................. 296
I2Cx Bus Data (Slave Mode).................................... 299
I2Cx Bus Start/Stop Bits (Master Mode)................... 296
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 299
Input Capture (CAPx) ............................................... 289
OCx/PWM................................................................. 290
Output Compare (OCx) ............................................ 290
Parallel Master Port Read ........................................ 309
Parallel Master Port Write......................................... 310
Parallel Slave Port.................................................... 308
SPIx Master Mode (CKE = 0) ................................... 291
SPIx Master Mode (CKE = 1) ................................... 292
SPIx Slave Mode (CKE = 0)..................................... 293
SPIx Slave Mode (CKE = 1)..................................... 294
Timer1, 2, 3, 4, 5 External Clock .............................. 288
UART Reception....................................................... 210
UART Transmission (8-bit or 9-bit Data) .................. 210
Timing Requirements
CLKO and I/O........................................................... 285
Timing Specifications
I2Cx Bus Data Requirements (Master Mode)........... 297
I2Cx Bus Data Requirements (Slave Mode)............. 300
Input Capture Requirements .................................... 289
Output Compare Requirements................................ 290
Simple OCx/PWM Mode Requirements ................... 290
SPIx Master Mode (CKE = 0) Requirements............ 291
SPIx Master Mode (CKE = 1) Requirements............ 292
SPIx Slave Mode (CKE = 1) Requirements.............. 294
SPIx Slave Mode Requirements (CKE = 0).............. 293
U
UART................................................................................ 205
USB On-The-Go (OTG).................................................... 145
V
VCAP pin............................................................................ 262
Voltage Regulator (On-Chip) ............................................ 262
W
Watchdog Timer (WDT).................................................... 260
WWW Address ................................................................. 339
WWW, On-Line Support ..................................................... 15
S
Serial Peripheral Interface (SPI) ....................................... 191
Software Simulator (MPLAB SIM)..................................... 267
Special Features............................................................... 251
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 337
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 338
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
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• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
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software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
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program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
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CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 339
PIC32MX330/350/370/430/450/470
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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PIC32MX330/350/370/430/450/470
DS60001185B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS60001185B-page 340
Preliminary
2012-2013 Microchip Technology Inc.
PIC32MX330/350/370/430/450/470
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Example:
PIC32 MX 3XX F 064 H T - 80 I / PT - XXX
PIC32MX330F064H-80I/PT:
General purpose PIC32,
32-bit RISC MCU,
64 KB program memory,
64-pin, Industrial temperature,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
3XX = General purpose microcontroller family
4XX = General purpose microcontroller family
Flash Memory Family
F
= Flash program memory
Program Memory Size 064 = 6 4KB
128 = 128KB
256 = 256KB
512 = 512KB
Pin Count
H
L
= 64-pin
= 100-pin
Speed
80 = 80 MHz
Temperature Range
I
V
= -40°C to +85°C (Industrial)
= -40°C to +105°C (V-Temp)
Package
Pattern
PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
TL = 124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array)
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 341
PIC32MX330/350/370/430/450/470
NOTES:
DS60001185B-page 342
Preliminary
2012-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
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hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-154-9
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2012-2013 Microchip Technology Inc.
Preliminary
DS60001185B-page 343
Worldwide Sales and Service
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11/29/12
DS60001185B-page 344
Preliminary
2012-2013 Microchip Technology Inc.
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