PL123-09SI [MICROCHIP]
Low Skew Zero Delay Buffer;
| 型号： | PL123-09SI |
| 厂家： | 
MICROCHIP |
| 描述： | Low Skew Zero Delay Buffer |
| 文件： | 总9页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PL123-05/-09
Low Skew Zero Delay Buffer
FEATURES
DESCRIPTION
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
Frequency Range 10MHz to 134 MHz
Output Options:
o
o
5 outputs PL123-05
9 outputs PL123-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
CLKA2
CLKA1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLKA4
VDD
REF
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
PLL
Mux
CLKA3
REF
CLKA1
CLKA2
VDD
1
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
2
3
4
5
6
7
8
CLKB1
CLKB2
CLKB3
CLKB4
S1
S2
Selector
GND
GND
Inputs
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
(PL123-09 Only)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 1
PL123-05/-09
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
PL123-09
PL123-05
Name
Type
Description
TSSOP-16L
SOP-16L
SOP-8L
REF[1]
1
2
1
2
1
3
2
6
4
-
I
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
VDD connection
CLKA1[2]
CLKA2[2]
VDD
O
O
P
P
O
O
I
3
3
4,13
5,12
6
4,13
5,12
6
GND
GND connection
CLKB1[2]
CLKB2[2]
S2[3]
Buffered clock output, Bank B
Buffered clock output, Bank B
Selector input
7
7
-
8
8
-
S1[3]
9
9
-
I
Selector input
CLKB3[2]
CLKB4[2]
CLKA3[2]
CLKA4[2]
10
11
14
15
10
11
14
15
-
O
O
O
O
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
-
5
7
Buffered clock output. Internal feedback
on this pin.
CLKOUT[2]
16
16
8
O
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123-09
CLOCK A1–A4
CLOCK B1–B4
S2
S1
CLKOUT
Output Source
PLL Shutdown
(Bank A)
(Bank B)
0
0
1
1
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
Driven
Reference
PLL
Driven
Driven
INPUT / OUTPUT SKEW CONTROL
The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 2
PL123-05/-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20
To CMOS Input
50 line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 3
PL123-05/-09
Low Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ........................... VSS – 0.5V to 4.6V
Storage Temperature ........................ –65°C to 150°C
Junction Temperature………………………….. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)…………..> 2000V
OPERATING CONDITIONS
Parameter
Description
Min.
3.0
0
Max.
3.6
70
Unit
VDD
Supply Voltage
V
Commercial Operating Temperature (ambient temperature)
C
C
TA
CL
Industrial Operating Temperature (ambient temperature)
-40
85
Load Capacitance, below 100 MHz
Load Capacitance, above 100 MHz
Input Capacitance
―
―
―
30
10
7
pF
pF
pF
CIN
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
250
ms
ELECTRICAL CHARACTERISTICS
Test Conditions
Min.
Max.
Unit
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
VIL
VIH
IIL
–
2.5
–
0.8
–
V
V
VIN = 0V
VIN = VDD
50
100
µA
µA
IIH
–
IOL = 8 mA
IOL = 12 mA
IOH = –8 mA
IOL = –12 mA
66.67MHz with unloaded outputs
Commercial Temp.
66.67MHz with unloaded outputs
Industrial Temp.
VOL
VOH
Output LOW Voltage[4]
Output HIGH Voltage[4]
–
2.4
–
0.4
–
V
V
32
45
mA
mA
Supply Current
(Unloaded Outputs)
IDD
–
Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 4
PL123-05/-09
Low Skew Zero Delay Buffer
[5]
SWITCHING CHARACTERISTICS
Parameter Name
Test Conditions
Min.
Typ. Max. Unit
30-pF load
10
10
40
45
–
–
–
100
134
60
MHz
MHz
%
t1
Output Frequency
10-pF load
Duty Cycle [4] = t2 ÷ t1
Duty Cycle [4] = t2 ÷ t1
Rise Time [4]
Rise Time [4] (High Drive)
Fall Time [4]
Measured at 1.4V, FOUT = 66.67MHz
Measured at 1.4V, FOUT <50MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
50
50
–
55
%
2.5
1.5
2.5
1.5
250
ns
t3
t4
–
–
ns
–
–
ns
Fall Time [4] (High Drive)
–
–
ns
t5
Output to Output Skew
–
–
ps
Delay, REF Rising Edge to
CLKOUT Rising Edge [4]
t6A
Measured at VDD/2
–
0
±350
ps
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL bypass
t6B
t7
1
–
1
–
–
5
0
8.5
700
–
ns
ps
CLKOUT Rising Edge [4]
Device to Device Skew [4]
mode, PL123-09 only.
Measured at VDD/2 on the CLKOUT pin
Measured between 0.8V and 2.0V using Test
Circuit #2
t8
Output Slew Rate [4]
Cycle to Cycle Jitter [4]
PLL Lock Time [4]
–
V/ns
ps
tJ
Measured at 66.67 MHz, loaded outputs
75
–
200
1
Stable power supply, valid clock presented on
REF pin
tLOCK
ms
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded outputs.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 5
PL123-05/-09
Low Skew Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
1.4V
1.4V
All Outputs Rise/Fall Time
2.0V
3.3V
0V
2.0V
0.8V
OUTPUT
0.8V
t3
t4
Output-Output Skew
OUTPUT
1.4V
OUTPUT
1.4V
t5
Input-Output Propagation Delay
INPUT
VDD/2
OUTPUT
VDD/2
t6
Device-Device Skew
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
VDD/2
t7
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 6
PL123-05/-09
Low Skew Zero Delay Buffer
TEST CIRCUITS
Test Circuit #1
Test Circuit #2
1KΩ
VDD
VDD
0.1 F
0.1 F
0.1 F
0.1 F
CLK
OUTPUTS
GND
OUTPUTS
1KΩ
CLOAD
10 pF
VDD
GND
VDD
GND
GND
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 7
PL123-05/-09
Low Skew Zero Delay Buffer
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOP-16L and TSSOP-16L ( mm )
SOP
TSSOP
E
H
Symbol
Min.
Max.
Min.
Max.
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
-
1.20
0.15
0.30
0.20
5.10
4.50
0.05
0.19
0.09
4.90
4.30
D
A
H
L
6.40 BSC
0.45
A1
0.75
C
e
0.65 BSC
1.27 BSC
L
B
e
SOP 8L
Dimension in MM
Symbol
Min.
1.35
0.10
1.25
0.33
0.19
4.80
3.80
5.80
0.40
Max.
1.75
0.25
1.50
0.53
0.27
5.00
4.00
6.20
0.89
A
A1
A2
B
C
D
E
H
L
e
E
H
D
A2
A
A1
C
L
B
1.27 BSC
e
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 8
PL123-05/-09
Low Skew Zero Delay Buffer
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL123-0x(H) X X - X
Part Number
H=High Drive
None = Standard Drive
None=Tubes
R=Tape & Reel
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Package Type
O=TSSOP
S=SOP
Part/Order Number
Marking*
(Commercial)
Part/Order Number
(Industrial)
Marking*
(Industrial)
Package Option
(Commercial)
PL123-05SC
PL123-05SI
8-Pin SOP Tube
P12305
SC
LLLLL
P12305
SI
LLLLL
8-Pin SOP (Tape
and Reel)
PL123-05SC-R
PL123-05HSC
PL123-05HSC-R
PL123-05SI-R
PL123-05HSI
PL123-05HSI-R
8-Pin SOP Tube
P12305H
SC
LLLLL
P12305H
SI
LLLLL
8-Pin SOP (Tape
and Reel)
16-Pin TSSOP
Tube
16-Pin TSSOP
(Tape and Reel)
16-Pin TSSOP
Tube
PL123-09OC
PL123-09OI
P12309
OC
LLLLL
P12309
OI
LLLLL
PL123-09OC-R
PL123-09HOC
PL123-09OI-R
PL123-09HOI
P12309H
OC
LLLLL
P12309H
OI
LLLLL
16-Pin TSSOP
(Tape and Reel)
PL123-09HOC-R
PL123-09SC
PL123-09HOI-R
PL123-09SI
16-Pin SOP Tube
P12309
SC
LLLLL
P12309
SI
LLLLL
16-Pin SOP (Tape
and Reel)
PL123-09SC-R
PL123-09HSC
PL123-09HSC-R
PL123-09SI-R
PL123-09HSI
PL123-09HSI-R
16-Pin SOP Tube
P12309H
SC
LLLLL
P12309H
SI
LLLLL
16-Pin SOP (Tape
and Reel)
*Note: LLLLL designates lot number
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Mic rel
is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or syste ms without the express
written approval of the President of Micrel Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13
Page 9
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