PL585-P8-358OC-R [MICROCHIP]

IC CLK BUFFER LVPECL 16TSSOP;


型号：	PL585-P8-358OC-R
厂家：	MICROCHIP
描述：	IC CLK BUFFER LVPECL 16TSSOP
文件：	总7页 (文件大小：422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

PIN CONFIGURATION

FEATURES



< 0.5ps RMS phase jitter (12kHz to 20MHz)

at 622.08MHz (LVPECL/LVDS)

30ps max peak to peak period jitter

Ultra Low-Power Consumption



XIN

VCON

XOUT

VDDANA

VDDDIG

VDDBUF



< 90mA @622MHz PECL output

<10A at Power Down (PDB) Mode

Input Frequency:



DNC



Fundamental Crystal: 19MHz to 44MHz

Output Frequency:

19MHz to 800MHz output.

OE/PDB

DNC



Output types: LVPECL, LVDS, or LVCMOS.

High Linearity VCXO: <10% linearity

Pullability: ±150 ppm

Programmable OE input polarity,

о Programmable Hi-Z or Active Low disabled

state (CMOS output only)

GNDANA

GNDDIG

GNDBUF

VDDBUF

DNC

TSSOP-16L



Power Supply: 3.3V, ±10%

Operating Temperature Ranges:

 Commercial: 0C to 70C

 Industrial: -40C to 85C

Available in TSSOP package



OUTPUT ENABLE CONTROL

DESCRIPTION

OE Options

(Programmable)

Conventional

Polarity

The PL585 is a Dual LC core monolithic IC VCXO,

capable of maintaining sub-picoseconds RMS phase

jitter, while covering a wide frequency output range

up to 800MHz, without the use of external

components. The high performance and high

frequency output is achieved using a low cost

fundamental crystal of between 19MHz and 44 MHz.

The PL585 is designed to address the demanding

requirements of high performance applications such

Fiber Channel, serial ATA, Ethernet, SAN,

SONET/SDH, etc.

State

0 (Default)

Output enabled

Tri-state

Output enabled

Reverse

Polarity

1 (Default)

BLOCK DIAGRAM

OE/PDB

XIN/REF

XOUT

Xtal

Osc

LF – HF

LCVCOs

PD/CP

Pre-scalar

Varicap

VCON

M Divider

P Divider

Programmable Function

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 1

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

PIN ASSIGNMENT

Name

Pin #

Type

Description

XIN

VCON

DNC

Crystal input connection.

Analog voltage control pin.

Do Not Connect.

3, 5, 9

This pin may be programmed as output enable (OE), or power-down

(PDB) pin. This pin incorporates an Internal pull-up resistor of 60KΩ for

OE, and PDB, operations.

OE/PDB

GND_ANA

GND_DIG

GND_BUF

GND connection for analog circuitry.

GND connection for digital circuitry.

GND connection for buffer circuitry.

True Output buffer.

Complementary Output buffer.

VDD connection for buffer circuitry.

VDD connection for digital circuitry.

VDD connection for analog circuitry.

Output connection to crystal.

VDD_BUF

VDD_DIG

VDD_ANA

XOUT

11, 13

OPTION SELECTION TABLE

PL585 is a fully programmable VCXO IC. However, for ordering convenience, the following part numbers have

been created for when simple multiplication is used, for your convenienc e. When other features of the IC are

exercised (i.e. reverse polarity on OE, power down, etc.), another 3-digit code is used to identify the functionality.

Input Crystal

Frequency Range (MHz)

Multiplication

Factor

Output Frequency Range (MHz)

Part #

Low Limit

675.00

533.33

450.00

400.00

337.50

266.67

225.00

200.00

168.75

133.33

112.50

100.00

84.375

65.625

High Limit

800.00

675.00

533.33

450.00

400.00

337.50

266.67

225.00

200.00

168.75

133.33

112.50

100.00

84.375

X20

X16

X14

X12

X10

33.750000 ~ 40.000000

33.333333 ~ 42.187500

32.142857 ~ 38.095238

33.333333 ~ 37.500000

33.750000 ~ 40.000000

33.333333 ~ 42.187500

32.142857 ~ 38.095238

33.333333 ~ 37.500000

33.750000 ~ 40.000000

33.333333 ~ 42.187500

32.142857 ~ 38.095238

33.333333 ~ 37.500000

33.750000 ~ 40.000000

32.812500 ~ 42.187500

PL585-P8-020

PL585-P8-168

PL585-P8-148

PL585-P8-128

PL585-P8-108

PL585-P8-088

PL585-P8-078

PL585-P8-068

PL585-P8-058

PL585-P8-048

PL585-P8-358

PL585-P8-038

PL585-P8-258

PL585-P8-028

X3.5

X2.5

Common functionality for packaged parts in the above table: OE function active high polarity. Please inform your

Sales representative for active low OE functionality.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 2

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

OE Options

FUNCTIONAL DESCRIPTION

State

(Programmable)

Conventional

Polarity

PL585 family of products is an advanced,

0 (Default)

Output enabled

Tri-state

Output enabled

programmable LCVCO VCXO IC that is designed to

meet the most stringent performance specifications

for phase noise, jitter, and power consumption.

Reverse

Polarity

1 (Default)

There are two main types of VCOs, a) Ring

In addition, The OE feature can be programmed to

allow the output to float (Hi Z), or to operate in the

‘Active low’ mode, for CMOS outputs. The

programming control for the OE options is shown

below:

Oscillator, b) LC Tank oscillator. An LCVCO is made

up of LC tank oscillator. Although a Ring Oscillator

has very good performance, and has a good tuning

range, its phase noise and jitter performance, in

particular at higher frequencies, degrades.

OE Pin

Osc

PLL

Output

On the other hand, an LCVCO has an outstanding

phase noise and jitter performance, even at higher

frequencies. PL585 family of products takes

advantage of this state of the art technology, and

incorporates the LC tank on-chip, for optimal

performance.

Hi Z

Active ‘0’

(CMOS Only)

Normal Operation (Default)

Note: Typical enable time is <50ns plus one clock period.

PL585 family of products exhibit very low phase

noise/phase jitter and peak to peak jitter, wide tuning

range, and very low-power. All members of the

PL585 family accept a low-cost fundamental crystal

input of 19MHz to 44MHz, and its flexible core is

capable of producing any output frequency between

19MHz to 800MHz.

The OE pin incorporates a 60KΩ resistor to either

pull-up or pull-down to the default state when the OE

pin is left open.

Power-Down Control (PDB)

When activated, this programmable feature ‘Disables

the VCO, the oscillator circuitry, counters, and all

other active circuitry. PDB activation disables all

outputs and the IC consumes <15µA of power, in the

power down mode, to conserve power. The PDB

input incorporates a 10MΩ pull up resistor for

normal operating condition.

PLL Programming

The PLL in the PL585 family is fully programmable.

Micrel programming software is used to configure and

program the IC.

OE (Output Enable)

The PDB feature can be programmed to allow the

output to float (Hi Z), or to operate in the ‘Active low’

mode, in CMOS output. The logic for PDB is shown

below:

The OE pin in PL585 family, through programming,

can be configured to support OE pin activation with a

logic ‘1’ or logic ’0’, to provide you with the desired

enable polarity.

PDB Pin

Osc.

PLL

Output

Off

Hi Z

Active ‘0’

(CMOS Only)

Off

Normal Operation (Default)

Note: Typical enable time is <10ms.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 3

(Preliminary) PL585-XX

19 MHz to 800MHz Low Phase-Noise VCXO

ELECTRICAL SPECIFICATIONS

1. ABSOLUTE MAXIMUM RATINGS

PARAMETERS

SYMBOL

MIN

MAX

UNITS

Supply Voltage

V_DD

V_I

4.6

V_DD+0.5

150

Input Voltage, dc

-0.5

-65

-40

Output Voltage

V_O

T_S

Storage Temperature

C

Ambient Operating Temperature (industrial temperature)*

Ambient Operating Temperature (commercial temperature)

Junction Temperature

T_AI

T_AC

T_J

125

ESD Protection, Human Body Model

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to

commercial grade only.

2. GENERAL ELECTRICAL SPECIFICATIONS

PARAMETERS

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Supply Current, Dynamic

I_DDQ

LVPECL, 622.08MHz, 3.3V

Supply Current, PDB

Enabled

PDB = 0, 3.3V

OE logic 0 to logic 1, Ta=25º C.

Add one clock period to this

measurement for a usable clock

output.

Output Enable Time

t_OE

Power Up Time

T_PU

V_DD

t_PU

PDB logic 0 to logic 1, Ta=25º C.

3.63

100

Operating Voltage

Power Up Ramp Rate

Auto-Calibration Time

2.97

0.1

3.3

Time for V_DDto reach 90% V_DD.

Power ramp must be monotonic.

t_AC

At power up

Output Clock Duty Cycle

@ 50% of output waveform

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 4

(Preliminary) PL585-XX

19 MHz to 800MHz Low Phase-Noise VCXO

3. VOLTAGE CONTROLLED CRYSTAL OSCILLATOR

PARAMETERS

VCXO Pullability

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

VCON=1.65V, 1.65V

XTAL C₁>10fF and C₀/C₁<250

ppm

150

VCXO Tuning Characteristic

Pull Range Linearity

100

ppm/V

VCON Pin Input Impedance

VCON Modulation BW

MΩ

kHz

0V  VCON  3.3V, -3dB

4. CRYSTAL SPECIFICATIONS

PARAMETERS

SYMBOL

F_XIN

CONDITIONS

MIN

TYP

MAX UNITS

Crystal Resonator Frequency

Crystal Cload

Parallel Fundamental Mode

MHz

C_{L_Crystal}V_DD= 3.3V, VCON = 1.65V

C_{0_Crystal}

8.5

Shunt Capacitance

Crystal Pullability

3.5

C₀/C₁

AT cut

250

AT cut , up to 40MHz

AT cut , up to 44MHz

Ω

Recommended ESR

R_E

5. JITTER SPECIFICATIONS

PARAMETERS

FREQUENCY

CONDITIONS

MIN

TYP

MAX UNITS

RMS Phase Jitter

622.08MHz

12kHz to 20MHz, XIN=38.88MHz

0.5

10K cycles, LVPECL (-88)

XIN=38.88MHz

Period Jitter, Pk-to-Pk

10K cycles, LVCMOS (-27),

XIN=26.5625MHz

212.5MHz

6. PHASE NOISE SPECIFICATIONS

Freq.

(MHz)

10Hz

100Hz

PARAMETERS

UNITS

1KHz 10KHz 100KHz 1MHz 10MHz

155.52

622.08

-56

-47

-86

-77

-112

-101

-123

-111

-127

-114

136

147

Phase Noise, relative

to carrier (typical)

dBc/Hz

-127

-145

Note: Phase Noise measured at VCON = 1.65V

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 5

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

7. LVPECL OUTPUTS (Q, QB)

PARAMETERS

Output High Voltage

Output Low Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Q, QB

V_OH

V_OL

2.275 2.350 2.420

1.490 1.600 1.680

Standard LVPECL Termination,

V_DD= 3.3V

Output Frequency

F_out

t_r, t_f

V_pp

3.3V

800

500

930

MHz

Output Rise, Fall Times

Output Voltage Swing

20% - 80% of output waveform

Q, QB

300

800

550

LVPECL Levels Test Circuit

LVPECL Transistion Time Waveform

DUTY CYCLE

OUT

VDD

45 - 55%

55 - 45%

50?

2.0V

OUT

80%

50%

20%

OUT

t_R

t_F

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination Considerations

Decoupling and Power Supply Considerations

- Keep traces short!

- Place decoupling capacitors as close as possible to

the V_DDpin(s) to limit noise from the power supply

- Trace = Inductor. With a capacitive load this

equals ringing!

- Multiple V_DDpins should be decoupled separately

for best performance.

- Long trace = Transmission Line. Without proper

termination this will cause reflections (looks like

ringing).

- Addition of a ferrite bead in series with V_DDcan

help prevent noise from other board sources

- Design long traces (<1 inch) as “striplines” or

“microstrips” with defined impedance.

- Value of decoupling capacitor is frequency

dependant. Typical values to use are 0.1F for

designs using frequencies < 50MHz and 0.01F for

designs using frequencies > 50MHz.

- Match trace at one side to avoid reflections

bouncing back and forth.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 6

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)

TSSOP-16L

Dimension in MM

Symbol

Min.

Max.

1.20

0.15

0.30

0.20

5.10

4.50

6.60

0.75

0.05

0.19

0.09

4.90

4.30

6.20

0.45

0.65 BSC

ORDERING INFORMATION

For part ordering, please contact our Sales Department:

2180 Fortune Drive, San Jose, CA 95131, USA

Tel: (408) 944-0800 Fax: (408) 474-1000

PART NUMBER

The order number for this device is a combination of the following:

Part number, Package type, Thickness and Operating temperature range

PL585-XX-XXX XX

Part

Number

Temperature Range

C = Commercial (0°C to

70°C)

Programming

Code

I = Industrial (-45°C to

+85°C)

Packaging

Option

O = TSSOP

Part Number/Order Number

Marking^†

Package Option

P585-XX

XXX(I)

LLLLL

PL585-XX-XXXOC

PL585-XX-XXOC-R

16-Pin TSSOP (Tube)

16-Pin TSSOP (Tape and Reel)

†

Marking Notes:

1) The “ I” after the 3 digit programming code will be marked for Industrial Temperature grade products only. Commercial

grade products will not have a character in this position.

Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Micrel

is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be

responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.

LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express

written approval of the President of Micrel Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 7

PL585-P8-358OC-R [MICROCHIP]

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