SST26VF040AT-104E/MFVAO

SST26VF040A

2.5V/3.0V 4-Mbit Serial Quad I/O™ (SQI™) Flash Memory

• Security ID:

Features

- One-Time-Programmable (OTP) 2-Kbyte

• Single Voltage Read and Write Operations:

Secure ID:

- 2.7V-3.6V or 2.3V-3.6V

- 128-bit unique, factory preprogrammed

identifier

• Serial Interface Architecture:

- Nibble-wide multiplexed I/O’s with SPI-like

- User-programmable area

serial command structure:

• Temperature Range:

- Mode 0 and Mode 3

- Industrial: -40°C to +85°C

- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol

- Extended: -40°C to +125°C

• High-Speed Clock Frequency:

• Automotive AEC-Q100 Qualified

- 2.7V-3.6V: 104 MHz maximum (Industrial)

• Packages Available:

- 2.3V-3.6V: 80 MHz maximum (Industrial and

- 8-contact WDFN (6 mm x 5 mm)

Extended)

- 8-lead SOIC (3.90 mm)

• Burst Modes:

• All Devices are RoHS Compliant

- Continuous linear burst

- 8/16/32/64-byte linear burst with wrap-around

Product Description

• Superior Reliability:

The Serial Quad I/O™ (SQI™) family of Flash memory

- Endurance: 100,000 cycles (minimum)

devices features a six-wire, 4-bit I/O interface that

- Greater than 100 years data retention

allows for low-power, high-performance operation in a

• Low-Power Consumption:

low pin count package. SST26VF040A also supports

- Active Read current: 15 mA (typical @

104 MHz)

full command-set compatibility to traditional Serial

Peripheral Interface (SPI) protocol. System designs

using SQI Flash devices occupy less board space and

ultimately lower system costs.

- Standby Current: 15 µA (typical)

• Fast Erase Time:

- Sector/Block Erase: 20 ms (typical), 25 ms

(maximum)

All members of the 26 Series, SQI family are manufac-

tured with proprietary, high-performance CMOS Super-

Flash^®technology. The split-gate cell design and

thick-oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

- Chip Erase: 40 ms (typical), 50 ms

(maximum)

• Page-Program:

SST26VF040A significantly improves performance and

reliability, while lowering power consumption. These

devices write (Program or Erase) with a single-power

supply of 2.3V-3.6V. The total energy consumed is a

function of the applied voltage, current and time of

application. Since for any given voltage range, the

SuperFlash technology uses less current to program

and has a shorter erase time, the total energy

consumed during any erase or program operation is

less than alternative Flash memory technologies.

- 256 bytes per page in x1 or x4 mode

• End-of-Write Detection:

- Software polling the BUSY bit in STATUS

register

• Flexible Erase Capability:

- Uniform 4-Kbyte sectors

- Uniform 32-Kbyte overlay blocks

- Uniform 64-Kbyte overlay blocks

• Write-Suspend:

See Figure 2-1 for pin assignments.

- Suspend program or erase operation to

access another block/sector

• Software Reset (RST) mode

• Software Write Protection:

- Write protection through Block Protection bits

in STATUS register

 2020-2021 Microchip Technology Inc.

DS20006292B-page 1

SST26VF040A

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Website; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our website at www.microchip.com to receive the most current information on all of our products.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 2

SST26VF040A

1.0

BLOCK DIAGRAM

FIGURE 1-1:

FUNCTIONAL BLOCK DIAGRAM

OTP

®

SuperFlash

X - Decoder

Address

Memory

Buffers

and

Latches

Y - Decoder

Page Buffer,

I/O Buffers

and

Control Logic

Data Latches

Serial Interface

WP# HOLD# SCK CE# SIO [3:0] RESET#

 2020-2021 Microchip Technology Inc.

DS20006292B-page 3

SST26VF040A

2.0

PIN DESCRIPTION

FIGURE 2-1:

PIN DESCRIPTIONS

PIN ASSIGNMENT FOR 8-CONTACT WDFN

PIN ASSIGNMENT FOR 8-LEAD SOIC

1

2

8

7

CE#

VDD

CE#

1

2

8

7

VDD

SO/SIO1

WP#/SIO2

Vss

RESET#/HOLD#/SIO3

SO/SIO1

RESET#/HOLD#/SIO3

Top View

SCK

3

4

6

5

WP#/SIO2

Vss

3

4

6

5

SCK

SI/SIO0

TABLE 2-1:

Symbol

SCK

PIN DESCRIPTION

Pin Name

Functions

Serial Clock

Provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock

input, while output data is shifted out on the falling edge of the clock input.

SIO[3:0]

Serial Data

Input/Output

Transfer commands, addresses, or data serially into the device or data out of

the device. Inputs are latched on the rising edge of the serial clock. Data is

shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)

command instruction configures these pins for Quad I/O mode.

SI

Serial Data Input

for SPI mode

Transfer commands, addresses or data serially into the device. Inputs are

latched on the rising edge of the serial clock. SI is the default state after a

Power-on Reset or hardware Reset.

SO

Serial Data Output Transfer data serially out of the device. Data is shifted out on the falling edge of

for SPI mode

the serial clock. SO is the default state after a Power-on Reset or hardware

Reset.

CE#

WP#

HOLD#

Chip Enable

The device is enabled by a high-to-low transition on CE#. CE# must remain low

for the duration of any command sequence; or in the case of write operations,

for the command/data input sequence.

Write-Protect

Hold

The WP# pin is used in conjunction with the WPEN and IOC bits in the Configu-

ration register to prohibit write operations to the Block Protection register. This

pin only works in SPI, single-bit and dual-bit Read mode.

Temporarily stops serial communication with the SPI Flash memory while the

device is selected. This pin only works in SPI, single-bit and dual-bit Read mode

and must be tied high when not in use.

RESET#

VDD

Reset

Reset the operation and internal logic of the device.

Provide power supply voltage.

Power Supply

Ground

VSS

Note:

The exposed pad on the bottom side of WDFN package is internally not connected. It can externally be

soldered to ground for better device attachment to the board.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 4

SST26VF040A

SQI Flash memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between

the two modes is the state of the SCK signal when the

bus host is in Standby mode and no data is being trans-

ferred. The SCK signal is low for Mode 0 and SCK sig-

nal is high for Mode 3. For both modes, the Serial Data

I/O (SIO[3:0]) is sampled at the rising edge of the SCK

clock signal for input, and driven after the falling edge

of the SCK clock signal for output. The traditional SPI

protocol uses separate input (SI) and output (SO) data

signals as shown in Figure 4-1. The SQI protocol uses

four multiplexed signals, SIO[3:0], for both data in and

data out, as shown in Figure 4-2. This means the SQI

protocol quadruples the traditional bus transfer speed

at the same clock frequency, without the need for more

pins on the package.

3.0

MEMORY ORGANIZATION

The SST26VF040A SQI memory array is organized in

uniform, 4-Kbyte erasable sectors with the following

erasable blocks: with 32-Kbyte overlay erasable blocks

and 64-Kbyte overlay erasable blocks.

4.0

DEVICE OPERATION

SST26VF040A supports both Serial Peripheral

Interface (SPI) bus protocol and a 4-bit multiplexed SQI

bus protocol. To provide backward compatibility to

traditional SPI Serial Flash devices, the device’s initial

state after a Power-on Reset is SPI mode which

supports multi-I/O (x1/x2/x4) read/write commands. A

command instruction configures the device to SQI

mode. The dataflow in the SQI mode is similar to the

SPI mode, except it uses four multiplexed I/O signals

for command, address, and data sequence.

FIGURE 4-1:

SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

CE#

MODE 3

SCK

MODE 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SI

Don’t Care

MSB

High-Impedance

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB

SO

FIGURE 4-2:

SQI SERIAL QUAD I/O PROTOCOL

CE#

MODE 3

MODE 0

CLK

MODE 0

SIO[3:0]

C1 C0 A5 A4 A3 A2 A1 A0

H0 L0 H1 L1 H2 L2 H3 L3

MSB

 2020-2021 Microchip Technology Inc.

DS20006292B-page 5

SST26VF040A

4.1

Device Protection

4.2

Hardware Write Protection

SST26VF040A offers a software write protection

scheme that allows group protection of selected blocks

in memory array. The Write Protection Pin (WP#)

enables or disables the lock-down (BPL bit) of the

STATUS register. In addition, the Lock-Down

Protection Settings command also prevents any

changes to the block protection setting (BP0, BP1 and

BP2) during device operation. To avoid inadvertent

writes during power-up, the device is write-protected by

default after a Power-on Reset cycle.

The hardware Write Protection pin (WP#) is used in

conjunction with the WPEN and IOC bits in the

Configuration register to enable the lock-down function

of the BPL bit (bit 7) in the STATUS register and the

Configuration register. The WP# pin function only

works in SPI Single-Bit and Dual-Bit Read mode when

the IOC bit in the Configuration register is set to ‘0’. The

WP# pin function is disabled when the WPEN bit in the

Configuration register is ‘0’. This allows installation of

the device in a system with a grounded WP# pin while

still enabling write to the BP bits in the STATUS

register.

4.1.1

GROUP BLOCK PROTECTION

The Block Protection bits (BP0, BP1, BP2, and BPL) in

the STATUS register provide write protection to the

memory array and the STATUS register. See Table 4-4

for the Block Protection description.

The factory default setting at power-up of the WPEN bit

is ‘0’, disabling the Write-Protect function of the

WP# pin after power-up. WPEN is a nonvolatile bit;

once the bit is set to ‘1’, the Write-Protect function of

the WP# pin continues to be enabled after power-up.

The WP# pin only protects the BPL bit in the STATUS

register and Configuration register from changes.

Therefore, if the WP# pin is set to low while an internal

write is in progress, it will have no effect on the write

command. The IOC bit takes priority over the WPEN bit

in the Configuration register. When the IOC bit is ‘1’, the

function of the WP# pin is disabled and the WPEN bit

serves no function. When WP# is driven low and IOC

bit = 0, the execution of the Write STATUS Register

(WRSR) instruction to change the BP bits in the STATUS

register is determined by the value of the BPL bit (see

Table 4-1). When WP# is high, the lock-down function

of the BPL bit is disabled.

4.1.2

VOLATILE LOCK PROTECTION

To prevent changes to the Block Protection settings,

use the Lock-Down Protection Settings (LDPS)

command to enable Volatile Lock Protection. Once

Volatile Lock Protection is enabled, the Block

Protection settings cannot be changed. To avoid

inadvertent lock-down, the WREN command must be

executed prior to the LDPS command. To reset Volatile

Lock Protection, performing a hardware Reset or

power cycle on the device is required. The Volatile Lock

Protection status may be read from the Configuration

register.

TABLE 4-1:

WRITE PROTECTION LOCK-DOWN STATES

WRSR Instruction to Change BP0,

WRSR Instruction to

Change Configuration

Register

VLP

WP#

IOC

WPEN

BPL

BP1, BP2, BP3 Bits in STATUS

Register

0

1

L

H

L

H

0

1

X

0

1

X

0

1

X

0

1

X

0

1

X

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Note: X = “Don’t care”

 2020-2021 Microchip Technology Inc.

DS20006292B-page 6

SST26VF040A

SST26VF040A ships with the IOC bit set to ‘0’ and the

HOLD# pin function enabled. The HOLD# pin is always

disabled in SQI mode and only works in SPI Single-bit

and Dual-bit Read mode.

4.3

Security ID

SST26VF040A offers a 2-Kbyte Security ID (Sec ID)

feature. The Security ID space is divided into two parts:

one factory-programmed, 128-bit segment, and one

user-programmable segment.

The factory-programmed segment is programmed

during part manufacture with a unique number and

cannot be changed. The user-programmable segment

is left unprogrammed for the customer to program as

desired.

To activate the Hold mode, CE# must be in active-low

state. The Hold mode begins when the SCK active-low

state coincides with the falling edge of the HOLD#

signal. The Hold mode ends when the HOLD# signal’s

rising edge coincides with the SCK active-low state.

If the falling edge of the HOLD# signal does not

coincide with the SCK active-low state, then the device

enters Hold mode when the SCK next reaches the

active-low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK

active-low state, then the device exits Hold mode when

the SCK next reaches the active-low state. See

Figure 4-3.

Use the Program Security ID (PSID) command to

program the Security ID using the address shown in

Table 5-5. The Security ID can be locked using the

Lockout Security ID (LSID) command. This prevents

any future write operations to the Security ID.

The factory-programmed portion of the Security ID can

not be programmed by the user; neither the

factory-programmed nor user-programmable areas

can be erased.

Once the device enters Hold mode, SO will be in

high-impedance state while SI and SCK can be VIL or

VIH.

If CE# is driven active-high during a Hold condition, it

resets the internal logic of the device. As long as

HOLD# signal is low, the memory remains in the Hold

condition. To resume communication with the device,

HOLD# must be driven active-high, and CE# must be

driven active-low.

4.4

Hold Operation

The HOLD# pin pauses active serial sequences

without resetting the clocking sequence. This pin is

active after every power-up and only operates

during SPI Single-bit and Dual-bit modes.

FIGURE 4-3:

HOLD CONDITION WAVEFORM

SCK

HOLD#

Active

Hold

Active

Hold

Active

4.5.1

HARDWARE RESET OPERATION

4.5

Reset Operation

To configure the RESET#/HOLD#/SIO3 pin as a

RESET# pin, bit 6 of the Configuration register must be

set to ‘1’. The factory default setting of bit 6 is

‘0’-HOLD# pin enabled. This is a nonvolatile bit, so the

register value at power-up will be the value prior to

power-down. Driving the RESET# pin high puts the

device in normal operating mode. The RESET# pin

must be driven low for a minimum of TRST time to reset

the device. The SIO1 pin (SO) is in high-impedance

state while the device is in Reset. A successful Reset

operation will reset the protocol to SPI mode, STATUS

register bits will become as follows: BUSY = 0,

WEL = 0, BP0 = 1, BP1 = 1, BP2 = 1 and BPL = 0;

reset the burst length to 8 bytes. Reset during an active

program or erase operation aborts the operation and

data of the targeted address range may be corrupted or

lost due to the aborted erase or program operation.

If the RST#/HOLD#SIO3 pin is used as a Reset pin,

RST# pin provides a hardware method for resetting the

device. SST26VF040A supports both hardware and

software Reset operation. Hardware Reset is only

allowed using SPI x1 and x2 protocol. Software Reset

commands 66H and 99H are supported in all protocols.

See Table 4-2 and for Figure 4-4 for hardware and

software Reset functionality.

Note:

A device Reset during an active program

or erase operation aborts the operation

and data of the targeted address range

may be corrupted or lost due to the

aborted erase or program operation.

Depending on the prior operation, the Reset timing may

vary. Recovery from a write operation requires more

latency time than recovery from other operations.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 7

SST26VF040A

Once the Reset Enable and Reset commands are

successfully executed, the device returns to normal

operation Read mode and then does the following:

resets the protocol to SPI mode, resets the burst length

to 8 bytes, STATUS register bits BUSY = 0, WEL = 0;

and clears bit 1 (IOC) in the Configuration register to its

default state.

4.5.2

SOFTWARE RESET OPERATION

The Reset operation requires the Reset Enable

command, 66H, followed by the Reset command, 99H.

Note:

Any command other than the Reset com-

mand after the Reset Enable command

will disable the Reset Enable.

FIGURE 4-4:

PERFORMING SOFTWARE RESET DURING READ

Device requires Software Reset

while performing Read.

Issue either a Reset Quad I/O command

(0xFF instruction) or a Software Reset

command (0x66 instruction followed by

0x99 instruction) to exit mode Read.

Was the previous

Instruction a

mode Read with

M[7:0]=AXH

Yes

No

Issue Software Reset command (0x66

instruction followed by 0x99 instruction)

to reset the device.

Device is Reset.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 8

SST26VF040A

TABLE 4-2:

REGISTER SETTINGS AFTER HARDWARE AND SOFTWARE RESET

After Power Cycle

After Hardware Reset

After Software Reset

Status Register Bits

Busy Bit

0

1

0

1

0

WEL Bit

0

BP0 Bit

Unchanged

BP1 Bit

BP2 Bit

BPL Bit

Configuration Register Bits

IOC Bit

0

VLP Bit

0

Unchanged

0

SEC Bit

Unchanged

0

Unchanged

0

WSE Bit

WSP Bit

0

RSTHLD Bit

WPEN Bit

Unchanged

4.6

STATUS Register

The software STATUS register provides status on

whether the Flash memory array is available for any

read or write operation, whether the device is

write-enabled, and the state of the memory write

protection. During an internal erase or program

operation, the STATUS register may be read only to

determine the completion of an operation in progress.

Table 4-3 describes the function of each bit in the

software STATUS register.

TABLE 4-3:

SOFTWARE STATUS REGISTER

Function

Default at

Power-Up

Bit

Name

Read/Write

0

BUSY 1= Internal write operation is in progress

0= No internal write operation is in progress

0

R

1

WEL

1= Device is memory write-enabled

0

R

0= Device is not memory write-enabled

2

3

4

5

6

7

BP0

BP1

BP2

BP3

RES

BPL

Indicate current level of block write protection (see Table 4-4)

Reserved

1

0

R/W

R

1= BP3, BP2, BP1, BP0 are read-only bits

0= BP3, BP2, BP1, BP0 are read/writable

R/W

 2020-2021 Microchip Technology Inc.

DS20006292B-page 9

SST26VF040A

4.6.1

BUSY

4.6.3

BLOCK PROTECTION (BP3, BP2,

BP1, BP0)

The BUSY bit determines whether there is an internal

erase or program operation in progress. A ‘1’ for the

BUSY bit indicates the device is busy with an operation

in progress. A ‘0’ indicates the device is ready for the

next valid operation.

The Block Protection (BP3, BP2, BP1, BP0) bits define

the size of the memory area, as defined in Table 4-4, to

be software-protected against any memory write (pro-

gram or erase) operations.

The Write STATUS Register (WRSR) instruction is used

to program the BP3, BP2, BP1 and BP0 bits as long as

WP# pin is high or the Block Protect Lock (BPL) bit is

‘0’. Chip Erase can only be executed if Block Protection

bits are ‘0’. After power-up, BP3, BP2, BP1 and BP0

are set to defaults specified in Table 4-4.

4.6.2

WRITE ENABLE LATCH (WEL)

The Write Enable Latch bit indicates the status of the

internal memory Write Enable Latch. If the Write

Enable Latch bit is set to ‘1’, it indicates the device is

write-enabled. If the bit is set to ‘0’ (Reset), it indicates

the device is not write-enabled and does not accept

any memory write (program/erase) commands. The

Write Enable Latch bit is automatically reset under the

following conditions:

4.6.4

BLOCK PROTECTION LOCK-DOWN

(BPL)

WP# pin driven low (VIL), IO bit = 0and WPEN bit = 1

enable the Block Protection Lock-Down (BPL) bit.

When BPL is set to ‘1’, it prevents any further alteration

of the BPL, BP3, BP2, BP1, and BP0 bits. When the

WP# pin is driven high (VIH), the BPL bit has no effect

and its value is “don’t care”. After power-up and

hardware Reset, the BPL bit is reset to ‘0’.

• Power-Up

• Write Disable (WRDI) instruction completion

• Page Program instruction completion

• Sector Erase instruction completion

• Block Erase instructions (32-Kbyte and 64-Kbyte)

completion

• Chip Erase instruction completion

• Write STATUS Register instruction completion

• Software or hardware Reset

• Lock-Down Protection Setting instruction comple-

tion

• Program Security ID instruction completion

• Lockout Security ID instruction completion

• Write-Suspend instruction

• SPI Quad Page program instruction completion

TABLE 4-4:

SOFTWARE STATUS REGISTER BLOCK PROTECTION

STATUS Register Bit

Protected Memory Address

Protected Level

BP3

BP2

BP1

BP0

8 Mbit

None

Upper 1/8

Upper 1/4

Upper 1/2

All

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

70000H-7FFFFH

60000H-7FFFFH

40000H-7FFFFH

00000H-7FFFFH

All

Note 1: X = “Don’t care” (Reserved) default is ‘0’.

2: Default at power-up for BP3, BP2, BP1 and BP0 is ‘0111’.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 10

SST26VF040A

4.7

Configuration Register

The Configuration register is a Read/Write register that

stores a variety of configuration information. See

Table 4-5 for the function of each bit in the register.

TABLE 4-5:

Bit

CONFIGURATION REGISTER

Name Function

Default at

Power-Up

Read/Write

(R/W)

0

1

Reserved

IOC

R

I/O Configuration

0⁽¹⁾

R/W

1= WP# and RST# or HOLD# pins disabled

0= WP# and RST# or HOLD# pins enabled

2

VLP

Volatile Lock Protection

0⁽¹⁾

R

1 = Locks Protection bit setting of BP0, BP1, BP2, BP3

of STATUS register

0= Protection bit BP0, BP1, BP2, BP3 setting not

locked by VLP bit

3

4

5

6

7

SEC

WSE

WSP

Security ID Status

1= Security ID space locked

0= Security ID space not locked

0⁽²⁾

R

Write Suspend Erase Status

1= Erase suspended

0= Erase is not suspended

0

Write Suspend Program Status

1= Program suspended

0= Program is not suspended

0

R

RSTHLD RST# pin or HOLD# Pin Enable

1= RST# pin enabled

0⁽³⁾

R/W

0= HOLD# pin enabled

WPEN

Write Protection Pin (WP#) Enable

1 = WP# enabled

0⁽³⁾

0 = WP# disabled

Note 1: Default at power-up or after hardware Reset is ‘0’.

2: The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security

ID instruction, otherwise default at power-up is ‘0’.

3: Factory default setting. This is a nonvolatile bit, default at power-up will be the setting prior to

power-down.

4.7.1

I/O CONFIGURATION (IOC)

4.7.2

VOLATILE LOCK PROTECTION

(VLP)

The I/O Configuration (IOC) bit reconfigures the I/O

pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the

Configuration register. When IOC bit is ‘0’ the WP# pin

and HOLD# pin or RST# pin are enabled (SPI or Dual

configuration setup). When the IOC bit is set to ‘1’ the

SIO2 and SIO3 pins are enabled (SPI Quad I/O config-

uration setup). The IOC bit must be set to ‘1’ before

issuing the following SPI commands: SQOR (6BH),

SQIOR (EBH), SPI Quad page program (32H) and

RBSPI (ECH). Without setting the IOC bit to ‘1’, those

SPI commands are not valid. The I/O Configuration bit

does not apply when in SQI mode. The default at

power-up and after hardware/software Reset is ‘0’.

The Volatile Lock Protection (VLP) bit is a volatile bit

which is set to ‘1’ when a lock-down protection settings

(LDPS) command is executed. When VLP bit is set

to ‘1’, it locks the protection bit BP0, BP1, BP2, BP3

settings of the STATUS register. The VLP bit can be

cleared to ‘0’ only by performing a hardware Reset or

by performing a power cycle.

4.7.3

SECURITY ID STATUS (SEC)

The Security ID Status (SEC) bit indicates when the

Security ID space is locked to prevent a write com-

mand. The SEC bit is ‘1’ after the host issues a Lockout

SID command. Once the host issues a Lockout SID

command, the SEC bit can never be reset to ‘0’.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 11

SST26VF040A

4.7.4

WRITE SUSPEND ERASE STATUS

(WSE)

The Write Suspend Erase status (WSE) indicates when

an erase operation is suspended. The WSE bit is ‘1’

after the host issues a suspend command during an

erase operation. Once the suspended erase resumes,

the WSE bit is reset to ‘0’.

4.7.5

WRITE SUSPEND PROGRAM

STATUS (WSP)

The Write Suspend Program status (WSP) bit indicates

when a program operation is suspended. The WSP

is ‘1’ after the host issues a suspend command during

the program operation. Once the suspended program

operation resumes, the WSP bit is reset to ‘0’.

4.7.6

RESET/HOLD ENABLE (RSTHLD)

The Reset/Hold Enable (RSTHLD) bit is a nonvolatile

bit that configures the RST#/HOLD#/SIO3 pin to be

either the RST# pin or the Hold# pin when not config-

ured as an I/O. There is latency associated with writing

to the RSTHLD bit. Poll the BUSY bit in the STATUS

register or wait TCONFIG for the completion of the

internal, self-timed write operation.

4.7.7

WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that enables the WP# pin. The Write-Protect (WP#)

pin and the Write-Protect Enable (WPEN) bit control

the programmable hardware write-protect feature.

Setting the WP# pin to low, and the WPEN bit to ‘1’,

enables hardware write protection. To disable

hardware write protection, set either the WP# pin to

high or the WPEN bit to ‘0’. There is latency associated

with writing to the WPEN bit. Poll the BUSY bit in the

STATUS register or wait TCONFIG for the completion

of the internal, self-timed write operation. When the

chip is hardware write-protected, only write operations

to the BPL bit in the STATUS register and Configuration

register are disabled. See Section 4.2 “Hardware

Write Protection” and Table 4-1 for more information

about the functionality of the WPEN bit.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 12

SST26VF040A

5.0

INSTRUCTIONS

Instructions are used to read, write (erase and pro-

gram), and configure the SST26VF040A. The com-

plete list of the instructions is provided in Table 5-1.

TABLE 5-1:

Instruction

DEVICE OPERATION INSTRUCTIONS

Op

Mode

Address

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Description

Code

Cycle

(2,3)

(3)

(4)

Cycle(s)

(1)

SPI

SQI

Configuration

NOP

No Operation

Reset Enable

00H

66H

99H

38H

FFH

05H

X

0

1

0

RSTEN

RST

0

Reset Memory

Enable Quad I/O

Reset Quad I/O

EQIO

RSTQIO

0

X

0

(5)

104 MHz/80 MHz

RDSR

Read STATUS

Register

1 to ∞

1 to 2

X

WRSR

RDCR

Write STATUS

Register

01H

35H

X

Read Configuration

Register

0

1

1 to ∞

X

Read

READ

Read Memory

03H

0BH

X

3

0

1

3

1

1 to ∞

40 MHz

104 MHz/80 MHz

80 MHz

High-Speed Read Memory at

Read

Higher Speed

(6)

SDOR

SPI Dual Output Read

SPI Dual I/O Read

3BH

BBH

6BH

X

(7,8)

SDIOR

(9)

SQOR

SPI Quad Output

Read

(10)

SQIOR

SB

SPI Quad I/O Read

Set Burst Length

EBH

C0H

0CH

X

3

0

3

0

3

1 to ∞

1

X

104 MHz/80 MHz

RBSQI

SQI nB Burst with

Wrap

n to ∞

RBSPI

SPI nB Burst with

Wrap

ECH

X

3

n to ∞

Identification

®

JEDEC ID JEDEC ID Read

Quad J-ID Quad I/O J-ID Read

9FH

AFH

5AH

X

0

3

0

1

3 to ∞

1 to ∞

X

104 MHz/80 MHz

SFDP

Serial Flash Discover-

able Parameters

 2020-2021 Microchip Technology Inc.

DS20006292B-page 13

SST26VF040A

TABLE 5-1:

DEVICE OPERATION INSTRUCTIONS (CONTINUED)

Op

Code

Cycle

Mode

Address

Cycle(s)

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Instruction

Description

(2,3)

(3)

(4)

(1)

SPI

SQI

Write

WREN

WRDI

Write Enable

06H

04H

20H

X

0

3

0

Write Disable

4-Kbyte

Sector

Erase

Erase 4 Kbyte of

Memory Array

(11)

32-Kbyte

Block

Erase

Erase 32 Kbyte of

Block Memory Array

52H

D8H

X

3

0

(12)

64-Kbyte

Block

Erase 64 Kbyte of

Block Memory Array

(13)

Erase

104 MHz/80 MHz

Chip Erase Erase Full Memory

Array

60H or

C7H

X

0

3

0

Page

Program

To Program 1 to 256

Data Bytes

02H

32H

B0H

30H

1 to 256

SPI Quad

SPI Quad Page

Program

1 to 256

(9)

PP

WRSU

WRRE

Suspends

Program/Erase

X

0

Resume

Program/Erase

Protection

LDPS

Lock-Down

Protection Settings

8DH

88H

X

0

RSID

Read Security ID

2

1

3

0

1 to 1024

1 to 256

X

104 MHz/80 MHz

PSID

LSID

Program User

Security ID Area

A5H

85H

X

Lockout Security ID

Programming

X

0

 2020-2021 Microchip Technology Inc.

DS20006292B-page 14

SST26VF040A

TABLE 5-1:

Instruction

DEVICE OPERATION INSTRUCTIONS (CONTINUED)

Op

Code

Cycle

Mode

Address

Cycle(s)

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Description

(2,3)

(3)

(4)

(1)

SPI

SQI

Power-Saving

DPD

Deep Power-Down

Mode

B9H

ABH

X

0

3

0

104 MHz/80 MHz

RDPD

Release from Deep

Power-Down and

Read ID

1 to ∞

Note 1: Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.

2: Address bits above the Most Significant bit of each density can be VIL or VIH.

3: Address, Dummy/Mode bits, and data cycles are two clock periods in SQI and eight clock periods in SPI mode.

4: The maximum frequency for all instructions is up to 104 MHz from 2.7V-3.6V and up to 80 MHz from 2.3V-3.6V

unless otherwise noted. For extended temperature (125°C) the maximum frequency is up to 80 MHz.

5: The Read STATUS register is continuous with ongoing clock cycles until terminated by a low-to-high transition

on CE#.

6: Data cycles are four clock periods.

7: The maximum frequency for SDIOR is up to 80 MHz from 2.3V-3.6V.

8: Address, Dummy/Mode bits, and data cycles are four clock periods.

9: Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.

10: Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the

command.

11: 4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

12: 32-Kbyte Block Erase addresses: use AMS-A15, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

13: 64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are “don’t care” but must be set either at

VIL or VIH.

Once the Reset Enable and Reset commands are

successfully executed, the device returns to normal

5.1

No Operation (NOP)

The No Operation command only cancels a Reset

Enable command. NOP has no impact on any other

command.

operation Read mode and then does the following:

resets the protocol to SPI mode, resets the burst length

to 8 bytes, clears BUSY bit and WEL bit in the STATUS

register to their default states, and clears IOC bit,

WSE bit and WSP bit in the Configuration register to its

default state. A device Reset during an active program

or erase operation aborts the operation, which can

cause the data of the targeted address range to be

corrupted or lost. Depending on the prior operation, the

Reset timing may vary. Recovery from a write operation

requires more latency time than recovery from other

operations. See Table 8-2 for Reset timing parameters.

5.2

Reset Enable (RSTEN) and Reset

(RST)

The Reset operation is used as a system (software)

Reset that puts the device in normal operating Ready

mode. This operation consists of two commands:

Reset Enable (RSTEN) followed by Reset (RST).

To reset SST26VF040A, the host drives CE# low,

sends the Reset Enable command (66H), and drives

CE# high. Next, the host drives CE# low again, sends

the Reset command (99H), and drives CE# high, see

Figure 5-1.

The Reset operation requires the Reset Enable

command followed by the Reset command. Any

command other than the Reset command after the

Reset Enable command will disable the Reset Enable.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 15

SST26VF040A

FIGURE 5-1:

RESET SEQUENCE

T

CPH

CE#

CLK

MODE 3

MODE 0

MODE 3

MODE 0

SIO[3:0]

C1 C0

C3 C2

Note: C[1:0] = 66H; C[3:2] = 99H

Initiate the READ instruction by executing an 8-bit

command, 03H, followed by address bits A[23:0].

CE# must remain active-low for the duration of the

Read cycle. See Figure 5-2 for the Read sequence.

5.3

Read (40 MHz)

The READ instruction, 03H, is supported in SPI bus

protocol only with clock frequencies up to 40 MHz.

This command is not supported in SQI bus protocol.

The device outputs the data starting from the specified

address location, then continuously streams the data

output through all addresses until terminated by a

low-to-high transition on CE#. The internal Address

Pointer will automatically increment until the highest

memory address is reached. Once the highest memory

address is reached, the Address Pointer will

automatically return to the beginning (wrap-around) of

the address space.

FIGURE 5-2:

READ SEQUENCE (SPI)

CE#

MODE 3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

70

MODE 0

SCK

03

ADD.

MSB

High-Impedance

ADD.

SI

MSB

N

OUT

N+1

OUT

N+2

OUT

N+3

OUT

N+4

D

OUT

D

SO

MSB

 2020-2021 Microchip Technology Inc.

DS20006292B-page 16

SST26VF040A

5.4

Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables

the Flash device for SQI bus operation. Upon comple-

tion of the instruction, all instructions thereafter are

expected to be 4-bit multiplexed input/output (SQI

mode) until a power cycle or a Reset Quad I/O instruc-

tion is executed. See Figure 5-3.

FIGURE 5-3:

ENABLE QUAD I/O SEQUENCE

CE#

SCK

MODE 3

MODE 0

0

1

2

3

4

5

6

7

38

SIO0

SIO[3:1]

Note: SIO[3:1] must be driven VIH.

To execute a Reset Quad I/O operation, the host drives

CE# low, sends the Reset Quad I/O command cycle

(FFH) then drives CE# high. Execute the instruction in

either SPI (8 clocks) or SQI (2 clocks) command

cycles. For SPI, SIO[3:1] are “don’t care” for this

command, but should be driven to VIH or VIL. See

Figures 5-4 and 5-5.

5.5

Reset Quad I/O (RSTQIO)

The Reset Quad I/O instruction, FFH, resets the device

to 1-bit SPI protocol operation or exits the Set Mode

configuration during a read sequence. This command

allows the Flash device to return to the default I/O state

(SPI) without a power cycle, and executes in either

1-bit or 4-bit mode. If the device is in the Set Mode con-

figuration, while in SQI High-Speed Read mode, the

RSTQIO command will only return the device to a state

where it can accept new command instruction. An addi-

tional RSTQIO is required to reset the device to SPI

mode.

FIGURE 5-4:

RESET QUAD I/O SEQUENCE (SPI)

CE#

SCK

SIO0

MODE 3

MODE 0

0

1

2

3

4

5

6

7

FF

SIO[3:1]

Note: SIO[3:1] must be driven VIH.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 17

SST26VF040A

FIGURE 5-5:

RESET QUAD I/O SEQUENCE (SQI)

CE#

MODE 3

MODE 0

0

1

F

SCK

SIO[3:0]

F

Initiate High-Speed Read by executing an 8-bit

command, 0BH, followed by address bits A[23:0] and a

dummy byte. CE# must remain active-low for the

duration of the High-Speed Read cycle. See Figure 5-6

for the High-Speed Read sequence for SPI bus

protocol.

5.6

High-Speed Read

The High-Speed Read instruction, 0BH, is supported in

both SPI bus protocol and SQI protocol. This instruc-

tion supports frequencies of up to 104 MHz from

2.7V-3.6V and up to 80 MHz from 2.3V-3.6V. On

power-up, the device is set to use SPI.

FIGURE 5-6:

HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

CE#

MODE 3

0

1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

80

71 72

SCK

MODE 0

0B

ADD.

X

SI/SIO0

N

OUT

MSB

N+1

N+2

N+3

D

OUT

N+4

High-Impedance

SO/SIO1

D

OUT

In SQI protocol, the host drives CE# low then sends

one High-Speed Read command cycle, 0BH, followed

by three address cycles, a Set Mode configuration

cycle, and two dummy cycles. Each cycle is two nibbles

(clocks) long, Most Significant nibble first.

When M[7:0] = AXH, the device expects the next

continuous instruction to be another read command,

0BH, and does not require the opcode to be entered

again. The host may initiate the next read cycle by

driving CE# low, then sending the 4-bit input for

address A[23:0], followed by the Set Mode

Configuration bits M[7:0], and two dummy cycles. After

the two dummy cycles, the device outputs the data

starting from the specified address location. There are

no restrictions on address location access.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the

specified address location. The device continually

streams data output through all addresses until

terminated by a low-to-high transition on CE#. The

internal Address Pointer automatically increments until

the highest memory address is reached, at which point

the Address Pointer returns to address location

000000H. During this operation, blocks that are

read-locked will output data 00H.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. While in

the Set Mode configuration, the RSTQIO command will

only return the device to a state where it can accept a

new command instruction. An additional RSTQIO is

required to reset the device to SPI mode. See

Figure 5-10 for the SPI Quad I/O Mode Read sequence

when M[7:0] = AXH.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SQI High-Speed Read

command.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 18

SST26VF040A

FIGURE 5-7:

HIGH-SPEED READ SEQUENCE (SQI)

CE#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

20

21

MODE 3

SCK

MODE 0

MSN

LSN

L0

C0 C1 A5 A4 A3 A2

A0

X

H0

H8 L8

M1 M0

Mode

SIO[3:0]

A1

Command

Address

Dummy

Data Byte 0

Data Byte 7

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH

5.7

SPI Quad Output Read

The SPI Quad Output Read instruction supports fre-

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

quencies of up to 104 MHz from 2.7V-3.6V and up to

80 MHz from 2.3V-3.6V. SST26VF040A requires the

IOC bit in the Configuration register to be set to ‘1’ prior

to executing the command. Initiate SPI Quad Output

Read by executing an 8-bit command, 6BH, followed

by address bits A[23:0] and a dummy byte. CE# must

remain active-low for the duration of the SPI Quad

Mode Read. See Figure 5-8 for the SPI Quad Output

Read sequence.

FIGURE 5-8:

SPI QUAD OUTPUT READ

CE#

MODE 3

MODE 0

31 32

0

1

2

3

4

5

6

7

8

15 16

23 24

39 40 41

SCK

6BH

A[23:16] A[15:8] A[7:0]

Address

b4 b0

SIO0

X

b4 b0

Data

OP Code

Dummy Byte 0

Byte N

SIO1

SIO2

SIO3

b5 b1

b6 b2

b5 b1

b6 b2

b7 b3

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble

 2020-2021 Microchip Technology Inc.

DS20006292B-page 19

SST26VF040A

5.8

SPI Quad I/O Read

The SPI Quad I/O Read (SQIOR) instruction supports

frequencies of up to 104 MHz from 2.7V-3.6V and up to

80 MHz from 2.3V-3.6V. SST26VF040A requires the

IOC bit in the Configuration register to be set to ‘1’ prior

to executing the command. Initiate SQIOR by execut-

ing an 8-bit command, EBH. The device then switches

to 4-bit I/O mode for address bits A[23:0], followed by

the Set Mode Configuration bits M[7:0], and two

dummy bytes. CE# must remain active-low for the

duration of the SPI Quad I/O Read. See Figure 5-9 for

the SPI Quad I/O Read sequence.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Quad I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another read com-

mand, EBH, and does not require the opcode to be

entered again. The host may set the next SQIOR cycle

by driving CE# low, then sending the 4-bit wide input for

address A[23:0], followed by the Set Mode Configura-

tion bits M[7:0], and two dummy cycles. After the two

dummy cycles, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

Following the dummy bytes, the device outputs data

from the specified address location. The device

continually streams data output through all addresses

until terminated by a low-to-high transition on CE#. The

internal Address Pointer automatically increments until

the highest memory address is reached, at which point

the Address Pointer returns to the beginning of the

address space.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. See

Figure 5-10 for the SPI Quad I/O Mode Read sequence

when M[7:0] = AXH.

FIGURE 5-9:

CE#

SPI QUAD I/O READ SEQUENCE

MODE 3

16

0

1

2

3

4

5

6

7

8 9 10 11 12 13 14 15

18 19 20 21 22

17

23

MODE 0

SCK

SIO0

SIO1

SIO2

SIO3

EBH

b4 b0

b5 b1

b6 b2

A20 A16 A12 A8

A21 A17 A13 A9

A22 A18 A14 A10

A23 A19 A15 A11

X

b4 b0

b5 b1

b6 b2

b7 b3

A4 A0 M4 M0

A5 A1 M5 M1

A6 A2 M6 M2

X

LSN

MSN

b7 b3

A7 A3 M7 M3

Set

Data

Dummy

Address

Byte 1

Mode

Byte 0

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble

 2020-2021 Microchip Technology Inc.

DS20006292B-page 20

SST26VF040A

FIGURE 5-10:

BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH

CE#

SCK

SIO0

SIO1

SIO2

SIO3

9

0

1 2

3

4

5 6 7 8

11 12 13

10

b4 b0 b4

b5 b1 b5

b6 b2 b6

M4

M5

M6

X

b4 b0

b5 b1

b6 b2

b0

b1

b2

A20 A16 A12 A8 A4

A21 A17 A13 A9 A5

A22 A18 A14 A10 A6

A0

A1

A2

M0

M1

M2

LSN

MSN

b7 b3 b7

M7

X

b7 b3

b3

A23 A19 A15 A11 A7

A3

M3

Set

Mode

Data Data

Byte Byte

Data

Address

Dummy

Byte 0

N

N+1

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble

5.9

Set Burst

The Set Burst command specifies the number of bytes

to be output during a Read Burst command before the

device wraps around. It supports both SPI and SQI pro-

tocols. To set the burst length the host drives CE# low,

sends the Set Burst command cycle (C0H) and one

data cycle, then drives CE# high. After power-up or

Reset, the burst length is set to eight bytes (00H). See

Table 5-2 for burst length data and Figures 5-11 and

5-12 for the sequences.

TABLE 5-2:

BURST LENGTH DATA

Burst Length

High Nibble (H0)

Low Nibble (L0)

8 Bytes

16 Bytes

32 Bytes

64 Bytes

0h

1h

2h

3h

FIGURE 5-11:

SET BURST LENGTH SEQUENCE (SQI)

CE#

MODE 3

MODE 0

0

1

2

3

SCK

SIO[3:0]

C1 C0 H0 L0

MSN LSN

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = C0H

 2020-2021 Microchip Technology Inc.

DS20006292B-page 21

SST26VF040A

FIGURE 5-12:

SET BURST LENGTH SEQUENCE (SPI)

CE#

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MODE 3

MODE 0

SCK

SIO0

C0

D

IN

SIO[3:1]

Note:

SIO[3:1] must be driven VIH.

5.10 SQI Read Burst with Wrap (RBSQI)

5.11 SPI Read Burst with Wrap (RBSPI)

SQI Read Burst with Wrap is similar to High-Speed

Read in SQI mode, except data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SQI Read Burst operation, drive

CE# low then send the Read Burst command cycle

(0CH), followed by three address cycles, and then

three dummy cycles. Each cycle is two nibbles (clocks)

long, Most Significant nibble first.

SPI Read Burst with Wrap (RBSPI) is similar to SPI

Quad I/O Read except the data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SPI Read Burst with Wrap opera-

tion, drive CE# low, then send the Read Burst com-

mand cycle (ECH), followed by three address cycles,

and then three dummy cycles.

After the dummy cycle, the device outputs data on the

falling edge of the SCK signal starting from the

specified address location. The data output stream is

continuous through all addresses until terminated by a

low-to-high transition on CE#.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the

specified address location. The data output stream is

continuous through all addresses until terminated by a

low-to-high transition on CE#.

During RBSPI, the internal Address Pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight bytes, and the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During RBSQI, the internal Address Pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight bytes, and the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During this operation, blocks that are read-locked will

output data 00H.

During this operation, blocks that are read-locked will

output data 00H.

TABLE 5-3:

BURST ADDRESS RANGES

Burst Length

Burst Address Ranges

8 Bytes

16 Bytes

32 Bytes

64 Bytes

00-07H, 08-0FH, 10-17H, 18-1FH...

00-0FH, 10-1FH, 20-2FH, 30-3FH...

00-1FH, 20-3FH, 40-5FH, 60-7FH...

00-3FH, 40-7FH, 80-BFH, C0-FFH

 2020-2021 Microchip Technology Inc.

DS20006292B-page 22

SST26VF040A

Following the dummy byte, SST26VF040A outputs

data from SIO[1:0] starting from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

5.12 SPI Dual Output Read

The SPI Dual Output Read instruction supports

frequencies of up to 104 MHz from 2.7V-3.6V and up to

80 MHz from 2.3V-3.6V. Initiate SPI Dual Output Read

by executing an 8-bit command, 3BH, followed by

address bits A[23:0] and a dummy byte. CE# must

remain active-low for the duration of the SPI Dual

Output Read operation. See Figure 5-13 for the SPI

Dual Output Read sequence.

FIGURE 5-13:

FAST READ, DUAL-OUTPUT SEQUENCE

Note:

MSB = Most Significant Bit

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. See

Figure 5-15 for the SPI Dual I/O Read sequence when

M[7:0] = AXH.

5.13 SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) instruction supports up

to 80 MHz frequency. Initiate SDIOR by executing an

8-bit command, BBH. The device then switches to 2-bit

I/O mode for address bits A[23:0], followed by the Set

Mode Configuration bits M[7:0]. CE# must remain

active-low for the duration of the SPI Dual I/O Read.

See Figure 5-14 for the SPI Dual I/O Read sequence.

Following the Set Mode Configuration bits, the

SST26VF040A outputs data from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Dual I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another SDIOR

command, BBH, and does not require the opcode to be

entered again. The host may set the next SDIOR cycle

by driving CE# low, then sending the 2-bit wide input for

address A[23:0], followed by the Set Mode

Configuration bits M[7:0]. After the Set Mode

Configuration bits, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 23

SST26VF040A

FIGURE 5-14:

SPI DUAL I/O READ SEQUENCE

CE#

MODE 3

MODE 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

17

18 19 20 21 22

23

SCK

SIO0

SIO1

BBH

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

2

3

0

1

6

7

4

5

A[23:16]

A[15:8]

A[7:0]

M[7:0]

CE#(cont’)

SCK(cont’)

23 2425 26 27 28 29 30 31 32 33 34 35 36 37 38

I/O Switches from Input to Output

39

SIO0(cont’)

SIO1(cont’)

4

0

6

4

2

0

6

4

2

0

6

4

2

0

6

7

6

2

MSB

7

MSB

7

MSB

7

5

7

5

3

1

5

3

1

5

3

1

3

1

Byte 0

Byte 1

Byte 2

Byte 3

Note:

MSB = Most Significant Bit

FIGURE 5-15:

BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH

CE#

SCK

MODE 3

8

0 1

2

3

4 5

6

7

9

10 11 12 13 14

15

MODE 0

I/O Switch

SIO0

SIO1

4

0

4

5

0

1

6

7

4

5

2

3

0

1

6

7

4

5

2

3

0

1

6

7

4

6

2

6

7

2

3

MSB

7

5

7

5

3

1

A[23:16]

A[15:8]

A[7:0]

M[7:0]

CE#(cont’)

24

15 16 17 18 19 20 21 22 23

26 27 28 29 30

31

25

SCK(cont’)

SIO0(cont’)

SIO1(cont’)

I/O Switches from Input to Output

4

2

0

6

4

2

0

6

4

2

3

0

1

6

4

5

2

3

0

6

7

6

MSB

7

MSB

7

MSB

7

5

3

1

5

3

1

5

1

Byte 0

Byte 1

Byte 2

Byte 3

Note:

MSB = Most Significant Bit, LSB = Least Significant Bit

 2020-2021 Microchip Technology Inc.

DS20006292B-page 24

SST26VF040A

Immediately

following

the

command

cycle,

5.14 JEDEC ID Read (SPI Protocol)

SST26VF040A output data on the falling edge of the

SCK signal. The data output stream is continuous until

terminated by a low-to-high transition on CE#. The

device outputs three bytes of data: manufacturer,

device type, and device ID, see Table 5-4. See

Figure 5-16 for instruction sequence.

Using traditional SPI protocol, the JEDEC ID Read

instruction identifies the device as SST26VF040A and

the manufacturer as Microchip. To execute a JEDEC ID

operation the host drives CE# low then sends the

JEDEC ID command cycle (9FH).

TABLE 5-4:

Product

SST26VF040A

FIGURE 5-16:

DEVICE ID DATA OUTPUT

Device ID

Manufacturer ID (Byte 1)

Device Type (Byte 2)

Device ID (Byte 3)

BFH

26H

14H

JEDEC ID SEQUENCE (SPI)

CE#

MODE 3

MODE 0

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCK

SI

9F

High-Impedance

26

Device ID

BF

SO

MSB

Immediately following the command cycle and one

dummy cycle, SST26VF040A outputs data on the

falling edge of the SCK signal. The data output stream

5.15 Read Quad J-ID Read (SQI

Protocol)

The Read Quad J-ID Read instruction identifies the

device as SST26VF040A and manufacturer as

Microchip. To execute a Quad J-ID operation the host

drives CE# low and then sends the Quad J-ID

command cycle (AFH). Each cycle is two nibbles

(clocks) long, Most Significant nibble first.

is continuous until terminated by

a low-to-high

transition of CE#. The device outputs three bytes of

data: manufacturer, device type, and device ID, see

Table 5-4. See Figure 5-17 for instruction sequence.

FIGURE 5-17:

QUAD J-ID READ SEQUENCE

CE#

N

0

1

2

3

4

5

6

7

8

9

10

11

12

13

MODE 3

SCK

MODE 0

MSN

LSN

C0 C1

X

H0 L0

BFH

L1

H0 L0 H1 L1

BFH

26H

HN LN

N

H2 L2

SIO[3:0]

H1

26H

Dummy

Device ID

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = AFH

 2020-2021 Microchip Technology Inc.

DS20006292B-page 25

SST26VF040A

Initiate SFDP by executing an 8-bit command, 5AH,

followed by address bits A[23:0] and a dummy byte.

CE# must remain active-low for the duration of the

SFDP cycle. For the SFDP sequence, see Figure 5-18.

5.16 Serial Flash Discoverable

Parameters (SFDP)

The Serial Flash Discoverable Parameters (SFDP)

contain information describing the characteristics of the

device. This allows device-independent, JEDEC

ID-independent, and forward/backward-compatible

software support for all future Serial Flash device

families. See Table 11-1 for address and data values.

FIGURE 5-18:

SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE

CE#

MODE 3

0

1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

71 72

80

SCK

MODE 0

5A

ADD.

X

SI

N

OUT

N+1

N+2

N+3

D

OUT

N+4

D

OUT

High-Impedance

SO

D

OUT

MSB

To execute a Sector Erase operation, the host drives

CE# low, then sends the Sector Erase command cycle

(20H) and three address cycles, and then drives CE#

high. Address bits [AMS:A₁₂] (AMS = Most Significant

Address) determine the sector address (SA_X); the

remaining address bits can be VIL or VIH. To identify the

completion of the internal, self-timed, write operation,

poll the BUSY bit in the STATUS register, or wait TSE.

See Figures 5-19 and 5-20 for the Sector Erase

sequence.

5.17 Sector Erase

The Sector Erase instruction clears all bits in the

selected 4-KByte sector to ‘1’, but it does not change a

protected memory area. Prior to any write operation,

the Write Enable (WREN) instruction must be executed.

FIGURE 5-19:

4-KBYTE SECTOR ERASE SEQUENCE – SQI MODE

CE#

MODE 3

MODE 0

0

1

2

4

6

SCK

SIO[3:0]

C1 C0 A5 A4 A3 A2 A1 A0

MSN LSN

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H

 2020-2021 Microchip Technology Inc.

DS20006292B-page 26

SST26VF040A

FIGURE 5-20:

4-KBYTE SECTOR ERASE SEQUENCE (SPI)

CE#

MODE 3

0

1

2

3

4

5

6

7

8

15 16

23

31

24

MODE 0

SCK

20

ADD.

MSB

ADD.

SI

MSB

High-Impedance

SO

The 64-Kbyte Block Erase instruction is initiated by

executing an 8-bit command D8H, followed by address

bits [A23:A0]. Address bits [AMS:A16] (AMS = Most

Significant Address) are used to determine block

address (BAX), remaining address bits can be VIL or

VIH. CE# must be driven high before the instruction is

executed. The user may poll the BUSY bit in the

software STATUS register or wait TBE for the

completion of the internal self-timed 32-Kbyte Block

Erase or 64-Kbyte Block Erase cycles. See

Figures 5-21 and 5-22 for the 32-Kbyte Block Erase

sequence and Figures 5-23 and 5-24 for the 64-Kbyte

Block Erase sequence.

5.18 32-Kbyte Block Erase and

64-Kbyte Block Erase

The 32-Kbyte Block Erase instruction clears all bits in

the selected 32-Kbyte block to FFH. The 64-Kbyte

Block Erase instruction clears all bits in the selected

64-Kbyte block to FFH. A 32-Kbyte Block Erase or

64-Kbyte Block Erase instruction applied to a protected

memory area will be ignored. Prior to any block erase

operation, the Write Enable (WREN) instruction must be

executed. CE# must remain active-low for the duration

of any command sequence. The 32-Kbyte Block Erase

instruction is initiated by executing an 8-bit command

52H, followed by address bits [A23:A0]. Address bits

[AMS:A15] (AMS = Most Significant Address) are used

to determine block address (BAX), remaining address

bits can be VIL or VIH. CE# must be driven high before

the instruction is executed.

FIGURE 5-21:

32-KBYTE BLOCK-ERASE SEQUENCE (SQI)

CE#

SCK

MODE 3

MODE 0

0

1

2

4

6

SIO[3:0]

C1 C0 A5 A4 A3 A2 A1 A0

MSN LSN

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 52H

 2020-2021 Microchip Technology Inc.

DS20006292B-page 27

SST26VF040A

FIGURE 5-22:

32-KBYTE BLOCK-ERASE SEQUENCE (SPI)

CE#

MODE 3

0

1

2

3

4

5

6

7

8

15 16

23

31

24

MODE 0

SCK

52

ADDR

MSB

ADDR

SI

MSB

High-Impedance

SO

FIGURE 5-23:

64-KBYTE BLOCK-ERASE SEQUENCE (SQI)

CE#

MODE 3

MODE 0

0

1

2

4

6

SCK

SIO[3:0]

C1 C0 A5 A4 A3 A2 A1 A0

MSN

LSN

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = D8H

FIGURE 5-24:

64-KBYTE BLOCK-ERASE SEQUENCE (SPI)

CE#

MODE 3

0

1

2

3

4

5

6

7

8

15 16

23

31

24

MODE 0

SCK

D8

ADDR

MSB

ADDR

SI

MSB

High-Impedance

SO

 2020-2021 Microchip Technology Inc.

DS20006292B-page 28

SST26VF040A

To execute a Chip Erase operation, the host drives CE#

low, sends the Chip Erase command cycle (C7H or

60H), then drives CE# high. Poll the BUSY bit in the

5.19 Chip Erase

The Chip Erase instruction clears all bits in the device

to ‘1’. The Chip Erase instruction is ignored if any of the

memory area is protected. Prior to any write operation,

execute the WRENinstruction.

STATUS register, or wait TSCE for the completion of the

,

internal, self-timed, write operation. See Figures 5-25

and 5-26 for the Chip Erase sequence.

FIGURE 5-25:

CHIP ERASE SEQUENCE (SQI)

CE#

MODE 3

0

1

SCK

MODE 0

SIO[3:0]

C1 C0

Note:

C[1:0] = C7H

FIGURE 5-26:

CHIP ERASE SEQUENCE (SPI)

CE#

MODE 3

0

1 2 3 4 5 6 7

SCK

MODE 0

C7

High-Impedance

SI

MSB

SO

 2020-2021 Microchip Technology Inc.

DS20006292B-page 29

SST26VF040A

When executing Page Program, the memory range for

the SST26VF040A is divided into 256-byte page

boundaries. The device handles shifting of more than

256 bytes of data by maintaining the last 256 bytes of

data as the correct data to be programmed. If the target

address for the Page Program instruction is not the

beginning of the page boundary (A[7:0] are not all

zero), and the number of bytes of data input exceeds or

overlaps the end of the address of the page boundary,

the excess data inputs wrap-around and will be

programmed at the start of that target page.

5.20 Page Program

The Page Program instruction programs up to

256 bytes of data in the memory, and supports both SPI

and SQI protocols. The data for the selected page

address must be in the erased state (FFH) before

initiating the Page Program operation. A Page Program

applied to a protected memory area will be ignored.

Prior to the program operation, execute the WREN

instruction.

To execute a Page Program operation, the host drives

CE# low then sends the Page Program command cycle

(02H), three address cycles followed by the data to be

programmed, then drives CE# high. The programmed

data must be between 1 to 256 bytes and in whole-byte

increments; sending less than a full byte will cause the

partial byte to be ignored. Poll the BUSY bit in the

STATUS register, or wait TPP for the completion of the

internal, self-timed, write operation. See Figures 5-27

and 5-28 for the Page Program sequence.

FIGURE 5-27:

PAGE-PROGRAM SEQUENCE (SQI)

CE#

MODE 3

0

2

4

6

8

10

12

SCK

MODE 0

SIO[3:0]

C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2

HN LN

MSN LSN

Data Byte 0

Data Byte 1 Data Byte 2

Data Byte 255

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble

FIGURE 5-28:

PAGE-PROGRAM SEQUENCE (SPI)

CE#

MODE 3

MODE 0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39

SCK

SI

02

ADD.

MSB

ADD.

LSB

Data Byte 0

LSB

MSB

LSB

SO

High-Impedance

CE#(cont’)

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCK(cont’)

SI(cont’)

Data Byte 255

Data Byte 1

Data Byte 2

MSB

LSB

SO(cont’)

High-Impedance

 2020-2021 Microchip Technology Inc.

DS20006292B-page 30

SST26VF040A

When executing SPI Quad Page Program, the memory

range for the SST26VF040A is divided into 256-byte

page boundaries. The device handles shifting of more

than 256 bytes of data by maintaining the last

256 bytes of data as the correct data to be

programmed. If the target address for the SPI Quad

Page Program instruction is not the beginning of the

page boundary (A[7:0] are not all zero), and the of

bytes of data input exceeds or overlaps the end of the

address of the page boundary, the excess data inputs

wrap-around and will be programmed at the start of that

target page.

5.21 SPI Quad Page Program

The SPI Quad Page Program instruction programs up

to 256 bytes of data in the memory. The data for the

selected page address must be in the erased state

(FFH) before initiating the SPI Quad Page Program

operation. A SPI Quad Page Program applied to a

protected memory area will be ignored. SST26VF040A

requires the ICO bit in the Configuration register to be

set to ‘1’ prior to executing the command. Prior to the

program operation, execute the WRENinstruction.

To execute a SPI Quad Page Program operation, the

host drives CE# low then sends the SPI Quad Page

Program command cycle (32H), three address cycles

followed by the data to be programmed, then drives

CE# high. The programmed data must be between 1 to

256 bytes and in whole-byte increments. The com-

mand cycle is eight clocks long, the address and data

cycles are each two clocks long, Most Significant bit

first. Poll the BUSY bit in the STATUS register, or wait

TPP for the completion of the internal, self-timed, write

operation. See Figure 5-29.

FIGURE 5-29:

SPI QUAD PAGE-PROGRAM SEQUENCE

CE#

MODE 3

MODE 0

16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0

17

SCK

SIO0

SIO1

32H

A20A16A12 A8

A4 A0 b4 b0 b4 b0

b4 b0

b5 b1

b6 b2

b7 b3

A13

b5 b1

A21 A17

A9

A5 A1 b5 b1

b6 b2

A22 A18A14A10

A6 A2 b6 b2

SIO2

SIO3

MSN LSN

b7 b3

A23 A19 A15 A11

A7 A3 b7 b3

Data Data

Data

Byte

255

Address

Byte 0 Byte 1

The Write Resume command is ignored until any write

operation (Program or Erase) initiated during the Write

Suspend is complete. The device requires a minimum

of 500 µs between each Write Suspend command.

5.22 Write Suspend and Write Resume

Write Suspend allows the interruption of Sector Erase,

32-Kbyte Block Erase, 64-Kbyte Block Erase, SPI

Quad Page Program, or Page Program operations in

order to erase, program or read data in another portion

of memory. The original operation can be continued

with the Write Resume command. This operation is

supported in both SQI and SPI protocols.

Only one write operation can be suspended at a time;

if an operation is already suspended, the device will

ignore the Write Suspend command. Write Suspend

during Chip Erase is ignored; Chip Erase is not a valid

command while a write is suspended.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 31

SST26VF040A

5.23 Write Suspend During Sector

Erase or Block Erase

5.26 Read Security ID

The Read Security ID operation is supported in both

SPI and SQI modes. To execute a Read Security ID

(SID) operation in SPI mode, the host drives CE# low,

sends the Read Security ID command cycle (88H), two

address cycles, and then one dummy cycle. To execute

a Read Security ID operation in SQI mode, the host

drives CE# low and then sends the Read Security ID

command, two address cycles, and three dummy

cycles.

Issuing a Write Suspend instruction during Sector

Erase or 32-Kbyte Block Erase or 64-Kbyte Block

Erase allows the host to program or read any sector

that was not being erased. The device will ignore any

programming commands pointing to the suspended

sector(s). Any attempt to read from the suspended sec-

tor(s) will output unknown data because the Sector or

32-Kbyte Block Erase or 64-Kbyte Block Erase will be

incomplete.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal, starting from the speci-

fied address location. The data output stream is contin-

uous through all SID addresses until terminated by a

low-to-high transition on CE#. See Table 5-5 for the

Security ID address range.

To execute a Write Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Configuration

register indicates that the erase has been suspended

by changing the WSE bit from ‘0’ to ‘1’, but the device

will not accept another command until it is ready. To

determine when the device will accept

command, poll the BUSY bit in the STATUS register or

wait TWS.

a new

5.27 Program Security ID

The Program Security ID instruction programs one to

2032 bytes of data in the user-programmable, Security

ID space. This Security ID space is one-time-program-

mable (OTP). The device ignores a Program Security

ID instruction pointing to an invalid or protected

address, see Table 5-5. Prior to the program operation,

execute WREN.

5.24 Write Suspend During Page

Programming or SPI Quad Page

Programming

Issuing a Write Suspend instruction during Page

Programming allows the host to erase or read any

sector that is not being programmed. Erase commands

pointing to the suspended sector(s) will be ignored. Any

attempt to read from the suspended page will output

unknown data because the program will be incomplete.

To execute a Program SID operation, the host drives

CE# low, sends the Program Security ID command

cycle (A5H), two address cycles, the data to be pro-

grammed, then drives CE# high. The programmed data

must be between 1 to 256 bytes and in whole-byte

increments.

To execute a Write Suspend operation, the host drives

CE# low, sends the Write Suspend command cycle

(B0H), then drives CE# high. The Configuration regis-

ter indicates that the programming has been sus-

pended by changing the WSP bit from ‘0’ to ‘1’, but the

device will not accept another command until it is ready.

To determine when the device will accept a new com-

mand, poll the BUSY bit in the STATUS register or wait

TWS.

The device handles shifting of more than 256 bytes of

data by maintaining the last 256 bytes of data as the

correct data to be programmed. If the target address for

the Program Security ID instruction is not the beginning

of the page boundary, and the number of data input

exceeds or overlaps the end of the address of the page

boundary, the excess data inputs wrap-around and will

be programmed at the start of that target page.

The Program Security ID operation is supported in both

SPI and SQI mode. To determine the completion of the

internal, self-timed Program SID operation, poll the

BUSY bit in the software STATUS register, or wait

TPSID for the completion of the internal self-timed

Program Security ID operation.

5.25 Write Resume

Write Resume restarts a write command that was sus-

pended, and changes the suspend Status bit in the

Configuration register (WSE or WSP) back to ‘0’.

To execute a Write Resume operation, the host drives

CE# low, sends the Write Resume command cycle

(30H), then drives CE# high. To determine if the inter-

nal, self-timed write operation is completed, poll the

BUSY bit in the STATUS register, or wait the specified

time TSE, TBE or TPP for Sector-Erase, Block-Erase, or

Page-Programming, respectively. The total write time

before suspend and after resume will not exceed the

uninterrupted write times TSE, TBE or TPP.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 32

SST26VF040A

TABLE 5-5:

PROGRAM SECURITY ID

Program Security ID

Address Range

Unique ID Preprogrammed at Factory

User-Programmable

0000-000FH

0010H-07FFH

These commands function in both SPI and SQI modes.

The STATUS register may be read at any time, even

during a write operation. When a write is in progress,

poll the BUSY bit before sending any new commands

to assure that the new commands are properly

received by the device.

5.28 Lockout Security ID

The Lockout Security ID instruction prevents any future

changes to the Security ID, and is supported in both

SPI and SQI modes. Prior to the operation, execute

WREN.

To execute a Lockout SID, the host drives CE# low,

sends the Lockout Security ID command cycle (85H),

then drives CE# high. Poll the BUSY bit in the software

STATUS register, or wait TPSID for the completion of the

Lockout Security ID operation.

To read the STATUS or Configuration registers, the

host drives CE# low, then sends the Read STATUS

Register command cycle (05H) or the Read Configura-

tion Register command (35H). A dummy cycle is

required in SQI mode. Immediately after the command

cycle, the device outputs data on the falling edge of the

SCK signal. The data output stream continues until ter-

minated by a low-to-high transition on CE#. See

Figures 5-30 and 5-31 for the instruction sequence.

5.29 Read STATUS Register (RDSR)

and Read Configuration Register

(RDCR)

The Read STATUS Register (RDSR) and Read Config-

uration Register (RDCR) commands output the con-

tents of the STATUS and Configuration registers.

FIGURE 5-30:

READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE

(SQI)

CE#

MODE 3

0

2

4

6

8

SCK _{MODE 0}

MSN LSN

SIO[3:0]

C1 C0

X

H0 L0 H0 L0

H0 L0

Dummy STATUS ByteSTATUS Byte

STATUS Byte

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 05H or 35H

FIGURE 5-31:

READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE

(SPI)

CE#

MODE 3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SCK

MODE 0

05 or 35H

High-Impedance

SI

MSB

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SO

MSB

STATUS or Configuration

Register Out

 2020-2021 Microchip Technology Inc.

DS20006292B-page 33

SST26VF040A

5.30 Write STATUS Register (WRSR)

The Write STATUS Register (WRSR) command writes

new values to the STATUS register and Configuration

register. To execute a Write STATUS Register opera-

tion, the host drives CE# low, then sends the Write

STATUS Register command cycle (01H), and one or

two cycles of data, and then drives CE# high. The first

cycle of data points to the STATUS register, the second

points to the Configuration register. See Figures 5-32

and 5-33.

FIGURE 5-32:

WRITE STATUS REGISTER SEQUENCE (SQI)

CE#

SCK

3

MODE 3

MODE 0

0

1

2

4

5

MSN LSN

SIO[3:0]

C1 C0 H0 L0 H0 L0

STATUS Configura-

Command

Byte

tion

Byte

Note:

MSN = Most Significant Nibble; LSN = Least Significant Nibble, XX = “Don’t Care”, C[1:0] = 01H

FIGURE 5-33:

WRITE STATUS REGISTER SEQUENCE (SPI)

CE#

0

1

2

3

4

5

6

7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

MODE 3

MODE 0

SCK

STATUS

Register

Configuration

Register

06

01

7 6 5 4

MSB

3

2

1 0 7 6 5 4

3 2 1 0

SI

MSB

High-Impedance

MSB

SO

Note:

XX = “Don’t Care”

 2020-2021 Microchip Technology Inc.

DS20006292B-page 34

SST26VF040A

5.31 Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write

Enable Latch bit in the STATUS register to ‘1’, allowing

write operations to occur. The WRENinstruction must be

executed prior to any of the following operations:

Sector Erase, 32-Kbyte Block Erase or 64-Kbyte Block

Erase, Chip Erase, Page Program, Program Security

ID, Lockout Security ID, Lock-Down Protection

Settings, SPI Quad Page program, and Write STATUS

register. To execute a Write Enable the host drives CE#

low then sends the Write Enable command cycle (06H)

then drives CE# high. See Figures 5-34 and 5-35 for

the WRENinstruction sequence.

FIGURE 5-34:

WRITE ENABLE SEQUENCE (SQI)

CE#

MODE 3

MODE 0

0

1

SCK

SIO[3:0]

0

6

FIGURE 5-35:

WRITE ENABLE SEQUENCE (SPI)

CE#

MODE 3

0

1 2 3 4 5 6 7

SCK

MODE 0

06

High-Impedance

SI

MSB

SO

 2020-2021 Microchip Technology Inc.

DS20006292B-page 35

SST26VF040A

5.32 Write Disable (WRDI)

The Write Disable (WRDI) instruction sets the Write

Enable Latch bit in the STATUS register to ‘0’, prevent-

ing write operations. The WRDI instruction is ignored

during any internal write operations. Any write opera-

tion started before executing WRDI will complete. Drive

CE# high before executing WRDI.

To execute a Write Disable, the host drives CE# low,

sends the Write Disable command cycle (04H), then

drives CE# high. See Figures 5-36 and 5-37.

FIGURE 5-36:

WRITE DISABLE (WRDI) SEQUENCE (SQI)

CE#

SCK

MODE 3

MODE 0

0

1

SIO[3:0]

0

4

FIGURE 5-37:

WRITE DISABLE (WRDI) SEQUENCE (SPI)

CE#

MODE 3

0

1

2

3

4 5 6 7

SCK

MODE 0

04

SI

MSB

High-Impedance

SO

 2020-2021 Microchip Technology Inc.

DS20006292B-page 36

SST26VF040A

5.33 Lock-Down Protection Settings

(LDPS)

The Lock-Down Protection Settings instruction

prevents changes to the Block Protection bits (BP0,

BP1, BP2, BP3) of the STATUS register during device

operation. Lock-Down resets after power cycling or

hardware Reset; this allows the Block Protection

settings to be changed. Execute WREN before

initiating the Lock-Down Protection Settings

instruction. To execute

a Lock-Down Protection

Settings command, the host drives CE# low, then

sends the Lock-Down Protection Settings command

cycle (8DH), then drive CE# high. Executing the LDPS

instruction will set the VLP bit in the Configuration

register.

FIGURE 5-38:

LOCK-DOWN PROTECTION SETTINGS (SQI)

CE#

SCK

MODE 3

MODE 0

0

1

SIO[3:0]

C1 C0

Note:

C[1:0] = 8DH

FIGURE 5-39:

LOCK-DOWN PROTECTION SETTINGS (SPI)

CE#

SCK

SIO0

MODE 3

MODE 0

0

1

2

3

4

5

6

7

8D

SIO[3:1]

 2020-2021 Microchip Technology Inc.

DS20006292B-page 37

SST26VF040A

Enter Deep Power-Down mode by initiating the Deep

Power-Down (DPD) instruction (B9H) while driving CE#

low. CE# must be driven high before executing the DPD

instruction. After CE# is driven high, it requires a delay

of TDPD before the standby current ISB is reduced to

deep power-down current IDPD. See Table 5-6 for Deep

Power-Down timing. If the device is busy performing an

internal erase or program operation, initiating a Deep

Power-Down instruction will not place the device in

Deep Power-Down mode. See Figures 5-40 and 5-41

for the DPDinstruction sequence.

5.34 Deep Power-Down

The Deep Power-Down (DPD) instruction puts the

device in the lowest power consumption mode – the

Deep Power-Down mode. The Deep Power-Down

instruction is ignored during an internal write operation.

While the device is in Deep Power-Down mode, all

instructions will be ignored except for the Release

Deep Power-Down instruction.

TABLE 5-6:

Symbol

TDPD

DEEP POWER-DOWN

Parameter

Min.

—

Max.

3

Units

µs

CE# High to Deep Power-Down

CE# High to Standby Mode

TSBR

—

10

µs

FIGURE 5-40:

DEEP POWER-DOWN (DPD) SEQUENCE – SQI MODE

T

CE#

SCK

DPD

MODE 3

MODE 0

1

0

B

MSN

9

LSN

SIO[3:0]

Standby Mode Deep Power-Down Mode

Note:

MSN = Most Significant Nibble; LSN = Least Significant Nibble

FIGURE 5-41:

DEEP POWER-DOWN (DPD) SEQUENCE – SPI MODE

CE#

T

DPD

MODE 3

MODE 0

0

1

2

3

4 5 6 7

SCK

B9

SI

MSB

High-Impedance

SO

Standby Mode Deep Power-Down Mode

 2020-2021 Microchip Technology Inc.

DS20006292B-page 38

SST26VF040A

To execute RDPD and read the Device ID, the host

drives CE# low then sends the Deep Power-Down

command cycle (ABH), three dummy clock cycles, and

then drives CE# high. The device outputs the Device ID

on the falling edge of the SCK signal following the

dummy cycles. The data output stream is continuous

until terminated by a low-to-high transition on CE, and

will return to Standby mode and be ready for the next

instruction after TSBR. See Figures 5-42 and 5-43 for

the command sequence.

5.35 Release from Deep Power-Down

and Read ID

Release from Deep Power-Down (RDPD) and Read ID

instruction exits Deep Power-Down mode. To exit Deep

Power-Down mode, execute the RDPD. During this

command, the host drives CE# low, then sends the

Deep Power-Down command cycle (ABH), and then

drives CE# high. The device will return to Standby

mode and be ready for the next instruction after TSBR.

FIGURE 5-42:

RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE – SQI MODE

T

SBR

CE#

MODE 3

0

1

SCK _{MODE 0}

Op Code

C1 C0

MSN LSN

X

D1 D0

Device ID

SIO[3:0]

Standby Mode

Deep Power-Down Mode

Note:

C[1:0] = ABH

FIGURE 5-43:

RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE – SPI MODE

T

SBR

CE#

MODE 3

1

2

3

4

5

6

15 16

23 24

32 33

0

7

8

40

SCK _{MODE 0}

Op Code

AB

XX

SIO[3:0]

Device ID

Standby Mode

Deep Power-Down Mode

 2020-2021 Microchip Technology Inc.

DS20006292B-page 39

SST26VF040A

6.0

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings ^(†)

Temperature under bias..........................................................................................................................-55°C to +125°C

Storage temperature...............................................................................................................................-65°C to +150°C

DC voltage on any pin to ground potential...........................................................................................-0.5V to VDD+0.5V

Transient voltage (<20 ns) on any pin to ground potential...................................................................-2.0V to VDD+2.0V

Package power dissipation capability (TA = 25°C)....................................................................................................1.0W

Surface mount solder reflow temperature.......................................................................................260°C for 10 seconds

Output short circuit current⁽¹⁾..................................................................................................................................50 mA

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note 1: Output shorted for no more than one second. No more than one output shorted at a time.

TABLE 6-1:

OPERATING RANGE

6.1

Power-Up Specifications

Range

Ambient Temp.

-40°C to +85°C

-40°C to +125°C

VDD

All functionalities and DC specifications are specified

for a VDD ramp rate of greater than 1V per 100 ms

(0V to 3.0V in less than 300 ms). See Table 6-3 and

Figure 6-1 for more information.

Industrial

Extended⁽¹⁾

2.3V-3.6V

Note 1: Maximum operating frequency for

Extended temperature is 80 MHz.

When VDD drops from the operating voltage to below

the minimum VDD threshold at power-down, all opera-

tions are disabled and the device does not respond to

commands. Data corruption may result if a power-down

occurs while a write registers, program, or erase oper-

ation is in progress. See Figure 6-2.

(1)

TABLE 6-2:

AC CONDITIONS OF TEST

Input Rise/Fall Time

3 ns

Output Load

CL = 30 pF

Note 1: See Figure 8-6.

TABLE 6-3:

Symbol

RECOMMENDED SYSTEM POWER-UP/POWER-DOWN TIMINGS

Parameter

Minimum

Maximum

Units

Condition

(1)

TPU-READ

VDD Minimum to Read Operation

VDD Minimum to Write Operation

Power-Down Duration

VDD Off

100

—

µs

ms

V

(1)

TPU-WRITE

(1)

TPD

—

VOFF

0.3

0V recommended

Note 1: This parameter is measured only for initial qualification and after a design or process change that could

affect this parameter.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 40

SST26VF040A

FIGURE 6-1:

V_DD

POWER-UP TIMING DIAGRAM

V_DDMax

Chip selection is not allowed.

Commands may not be accepted or properly

interpreted by the device.

V_DDMin

T_PU-READ

T_PU-WRITE

Device fully accessible

Time

FIGURE 6-2:

POWER-DOWN AND VOLTAGE DROP DIAGRAM

V_DD

V_DDMax

No Device Access Allowed

V_DDMin

T_PU

Device

Access

Allowed

V_OFF

T_PD

Time

 2020-2021 Microchip Technology Inc.

DS20006292B-page 41

SST26VF040A

7.0

DC CHARACTERISTICS

TABLE 7-1:

DC OPERATING CHARACTERISTICS (VDD = 2.3V-3.6V)

Limits

Symbol

Parameter

Min.

Typical Max.

Unit

Test Conditions

IDDR1

IDDR2

Read Current

—

8

15

mA

VDD = VDD Max,

CE# = 0.1 VDD/0.9 VDD@40 MHz,

SO = Open

Read Current

—

20

mA

VDD = VDD Max,

CE# = 0.1 VDD/0.9 VDD@104 MHz,

SO = Open

IDDW

I_SB1

I_SB2

I_DPD1

I_DPD2

ILI

Program and Erase Current

Standby Current

—

15

—

8

25

30

50

20

30

2

mA

µA

V

VDD Max

CE# =VDD, VIN=VDD or VSS

CE# =VDD, VIN=VDD or VSS at 125°C

CE# = VDD, VIN=VDD or VSS

CE# = VDD, VIN=VDD or VSS at 125°C

VIN = GND to VDD, VDD=VDD Max

VOUT = GND to VDD, VDD = VDD Max

VDD = VDD Min

Standby Curent

—

Deep Power-Down Current

Input Leakage Current

Output Leakage Current

Input Low Voltage

—

ILO

—

2

VIL

—

0.8

—

0.2

—

VIH

Input High Voltage

0.7 VDD

—

V

VDD = VDD Max

VOL

VOH

Output Low Voltage

Output High Voltage

V

IOL = 100 µA, VDD = VDD Min

IOH = -100 µA, VDD = VDD Min

VDD-0.2

V

TABLE 7-2:

Capacitance (TA = 25°C, f = 1 MHz, Other Pins Open)

Parameter

Description

Test Condition

Maximum

(1)

COUT

Output Pin Capacitance

Input Capacitance

VOUT = 0V

VIN = 0V

8 pF

6 pF

(1)

CIN

Note 1: This parameter is measured only for initial qualification and after a design or process change that could

affect this parameter.

TABLE 7-3:

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Minimum Specification

Unit

Test Method

(1)

NEND

Endurance

100,000

100

Cycles

Years

mA

JEDEC Standard A117 and AEC-Q100-005

JEDEC Standard A103 and AEC-Q100-005

JEDEC Standard 78 and AEC-Q100-004

(1)

TDR

ILTH

Data Retention

Latch Up

(1)

100 + IDD

Note 1: This parameter is measured only for initial qualification and after a design or process change that could

affect this parameter.

TABLE 7-4:

Symbol

WRITE TIMING PARAMETERS (VDD = 2.3V-3.6V)

Parameter Minimum

Maximum

Unit

TSE

Sector Erase

Block Erase

—

25

50

1.5

25

ms

µs

TBE

TSCE

Chip Erase

(1)

TPP

Page Program

Program Security ID

TPSID

TWS

Write Suspend Latency

TCONFIG

Configuration Register Write Latency

ms

 2020-2021 Microchip Technology Inc.

DS20006292B-page 42

SST26VF040A

TABLE 7-4:

Symbol

WRITE TIMING PARAMETERS (VDD = 2.3V-3.6V) (CONTINUED)

Parameter Minimum Maximum

Unit

Note 1: Estimate for typical conditions less than 256 bytes: Programming Time (µs) = 55 + (3.75 x # of bytes).

 2020-2021 Microchip Technology Inc.

DS20006292B-page 43

SST26VF040A

8.0

AC CHARACTERISTICS

(1)

TABLE 8-1:

Symbol

AC OPERATING CHARACTERISTICS (VDD = 2.3V-3.6V)

Limits - 40 MHz Limits - 80 MHz⁽²⁾Limits - 104 MHz

Parameter

Units

Min.

Max.

Min.

Max.

Min.

Max.

FCLK

Serial Clock Frequency

Serial Clock Period

—

11

0.1

8

40

25

—

19

—

8

—

5.5

0.1

5

80

12.5

—

4.5

0.1

5

104

9.6

—

12

—

8

MHz

ns

TCLK

TSCKH

TSCKL

TSCKR

Serial Clock High Time

Serial Clock Low Time

ns

—

ns

(3)

Serial Clock Rise Time (slew rate)

Serial Clock Fall Time (slew rate)

CE# Active Setup Time

CE# Active Hold Time

—

V/ns

ns

(3)

TSCKF

—

(4)

TCES

TCEH

TCHS

TCHH

TCPH

TCHZ

TCLZ

THLS

THHS

THLH

THHH

THZ

—

(4)

8

5

—

5

ns

(4)

CE# Not Active Setup Time

CE# Not Active Hold Time

CE# High Time

8

5

—

5

ns

8

5

—

5

ns

25

—

0

12.5

—

0

—

12

—

0

ns

CE# High-to-High Z Output

SCK Low-to-Low Z Output

HOLD# Low Setup Time

HOLD# High Setup Time

HOLD# Low Hold Time

HOLD# High Hold Time

HOLD# Low-to-High Z Output

HOLD# High-to-Low Z Output

Data In Setup Time

12.5

—

ns

8

5

—

5

ns

8

5

—

5

ns

8

5

—

5

ns

8

5

—

5

ns

—

3

—

3

8

—

3

ns

TLZ

8

ns

TDS

—

8/5⁽⁵⁾

—

8/5⁽⁵⁾

ns

TDH

Data In Hold Time

4

—

4

ns

TOH

Output Hold from SCK Change

Output Valid from SCK

0

—

0

ns

TV

—

8/5⁽⁵⁾

—

ns

Note 1: Maximum operating frequency for 2.7V-3.6V is 104 MHz and for 2.3V-3.6V is 80 MHz.

2: Maximum frequency for 125°C is 80 MHz.

3: Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements.

4: Relative to SCK.

5: 30 pF/10 pF

 2020-2021 Microchip Technology Inc.

DS20006292B-page 44

SST26VF040A

FIGURE 8-1:

HOLD TIMING DIAGRAM

CE#

T

HLS

HHS

HHH

SCK

T

HLH

T

HZ

T

LZ

SO

SI

HOLD#

FIGURE 8-2:

SERIAL INPUT TIMING DIAGRAM

T

CPH

CE#

T

CHH

T

CEH

T

CES

T

CHS

T

SCKF

SCK

T

DH

DS

T

SCKR

SIO[3:0]

LSB

MSB

FIGURE 8-3:

SERIAL OUTPUT TIMING DIAGRAM

CE#

T

SCKH

SCKL

SCK

T

OH

T

CLZ

CHZ

SIO[3:0]

MSB

LSB

T

V

 2020-2021 Microchip Technology Inc.

DS20006292B-page 45

SST26VF040A

FIGURE 8-4:

RESET TIMING DIAGRAM

T

CPH

CE#

CLK

MODE 3

MODE 0

MODE 3

MODE 0

SIO[3:0]

C1 C0

C3 C2

Note:

C[1:0] = 66H; C[3:2] = 99H

TABLE 8-2:

RESET TIMING PARAMETERS

TR(I)

Parameter

Minimum

Maximum

Units

ns

TRECR Reset to Read (non-data operation)

TRECP Reset Recovery from Program or Suspend

TRECE Reset Recovery from Erase

—

20

100

1

µs

—

ms

ns

TRST

TRHZ

Reset Pulse Width (Hardware Reset)

Reset to High Z Output

100

—

105

ns

FIGURE 8-5:

HARDWARE RESET TIMING DIAGRAM

CE#

T

RECR

RECP

RECE

SCK

T

RST

RST#

T

RHZ

SO

SI

 2020-2021 Microchip Technology Inc.

DS20006292B-page 46

SST26VF040A

FIGURE 8-6:

AC INPUT/OUTPUT REFERENCE WAVEFORMS

V

IHT

V

HT

INPUT

REFERENCE POINTS

OUTPUT

V

LT

V

ILT

AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measurement reference

points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10%  90%) are <3 ns.

Note:

VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

 2020-2021 Microchip Technology Inc.

DS20006292B-page 47

SST26VF040A

9.0

9.1

PACKAGING INFORMATION

Package Marking

8-Lead SOIC (3.90 mm)

Example

26F040A

26F016B

SN1929

SM

e

3

1503343

343

8-Lead WDFN (5x6 mm)

Example

26F040A

MF

e

3

1929343

1^stLine Marking Codes

Part Number

SST26VF040A

SOIC

WDFN

26F040A

Legend: XX...X Part number or part number code

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

Note: For very small packages with no room for the Pb-free JEDEC^®designator

e

3

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 48

SST26VF040A

9.2

Packaging Diagrams

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

2X

0.10 C A–B

D

A

D

NOTE 5

N

E

2

E1

2

E1

E

2X

0.10 C A–B

2X

0.10 C A–B

1

2

NOTE 1

e

NX b

0.25

C A–B D

B

NOTE 5

TOP VIEW

0.10 C

C

A2

A

SEATING

PLANE

8X

SIDE VIEW

A1

h

R0.13

h

H

0.23

L

SEE VIEW C

(L1)

VIEW A–A

VIEW C

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2

 2020-2021 Microchip Technology Inc.

DS20006292B-page 49

SST26VF040A

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

Molded Package Thickness

Standoff

Overall Width

A

-

1.75

-

0.25

A2

A1

E

1.25

0.10

§

6.00 BSC

Molded Package Width

Overall Length

E1

D

3.90 BSC

4.90 BSC

Chamfer (Optional)

Foot Length

h

L

0.25

0.40

-

0.50

1.27

Footprint

L1

1.04 REF

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0°

0.17

0.31

5°

-

8°

c

b

0.25

0.51

15°

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.15mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2

 2020-2021 Microchip Technology Inc.

DS20006292B-page 50

SST26VF040A

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

SILK SCREEN

C

Y1

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

E

C

X1

Y1

1.27 BSC

5.40

Contact Pad Spacing

Contact Pad Width (X8)

Contact Pad Length (X8)

0.60

1.55

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev F

 2020-2021 Microchip Technology Inc.

DS20006292B-page 51

SST26VF040A

8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

(DATUM A)

(DATUM B)

NOTE 1

2X

0.15 C

1

2

2X

0.15 C

TOP VIEW

A1

0.10 C

C

A

SEATING

PLANE

A3

SIDE VIEW

0.08 C

C A B

0.10

D2

e

1

2

0.10

C A B

NOTE 1

E2

K

N

8 X b

0.10

0.05

C A B

C

SEE DETAIL A

BOTTOM VIEW

Microchip Technology Drawing C04-210B Sheet 1 of 2

 2020-2021 Microchip Technology Inc.

DS20006292B-page 52

SST26VF040A

8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

(DATUM A)

L

e/2

e

DETAIL A

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Terminal Length

N

8

e

1.27 BSC

0.75

0.02

0.20 REF

5.00 BSC

4.00 BSC

6.00 BSC

3.40 BSC

0.42

A

A1

A3

D

D2

E

E2

b

L

0.70

0.00

0.80

0.05

0.35

0.50

0.20

0.48

0.70

-

0.60

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-210B Sheet 2 of 2

 2020-2021 Microchip Technology Inc.

DS20006292B-page 53

SST26VF040A

8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C

X2

E

X1

Y2

Y1

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

1.27 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C

3.50

4.10

5.70

Contact Pad Width (X8)

Contact Pad Length (X8)

X1

Y1

0.45

1.10

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2210A

 2020-2021 Microchip Technology Inc.

DS20006292B-page 54

SST26VF040A

10.0 REVISION HISTORY

Revision B (July 2021)

Added note to Table 2-1. Updated Figure 5-13. Added

Product Identification System (Automotive). Updated

SOIC package drawing.

Revision A (January 2020)

Initial release of the document.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 55

SST26VF040A

THE MICROCHIP WEBSITE

CUSTOMER SUPPORT

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers should contact their distributor, representa-

tive or Field Application Engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included in

the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the website

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registra-

tion instructions.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 56

SST26VF040A

PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE)

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

–XXX

X

/XX

PART NO.

Device

Valid Combinations:

Temperature Package

Tape and Reel

Indicator

Operating

Frequency

a)

b)

c)

d)

SST26VF040A-104I/SN

SST26VF040AT-104I/SN

SST26VF040A-104I/MF

SST26VF040AT-104I/MF

Device:

SST26VF040A = 4 Mbit, 2.5V/3.0V, SQI Flash memory

WP#/Hold# pin enable at power-up

e)

f)

g)

h)

SST26VF040A-80E/SN

SST26VF040AT-80E/SN

SST26VF040A-80E/MF

SST26VF040AT-80E/MF

Tape and Reel Blank

=

Standard packaging (tube or tray)

Tape and Reel

(1)

Indicator:

T

Operating

Frequency

104

80

=

104 MHz

80 MHz

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Temperature

Range:

I

E

= -40C to +85C (Industrial)

= -40C to +125C (Extended)

Package:

SN

MF

= SOIC (3.90 mm Body), 8-lead

= WDFN (6 mm x 5 mm Body), 8-lead

 2020-2021 Microchip Technology Inc.

DS20006292B-page 57

SST26VF040A

PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE)

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

–XXX

X

/XX

XXX^(2,3)

PART NO.

Device

Valid Combinations:

Temperature Package

Tape and Reel

Indicator

Operating

Frequency

Variant

a)

b)

c)

d)

SST26VF040A-80E/SN70SVAO

SST26VF040A-80E/MF70SVAO

SST26VF040AT-80E/SN70SVAO

SST26VF040AT-80E/MF70SVAO

Device:

SST26VF040A = 4 Mbit, 2.5V/3.0V, SQI Flash memory

WP#/Hold# pin enable at power-up

Tape and Reel Blank

=

Standard packaging (tube or tray)

Tape and Reel

(1)

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Indicator:

T

Operating

Frequency

104

80

=

104 MHz

80 MHz

Temperature

Range:

I

E

= -40C to +85C (AEC-Q100 Grade 3)

= -40C to +125C (AEC-Q100 Grade 1)

2: The VAO/VXX automotive variants have

been designed, manufactured, tested

and qualified in accordance with

AEC-Q100 requirements for automotive

applications.

Package:

SN

MF

= SOIC (3.90 mm Body), 8-lead

= WDFN (6 mm x 5 mm Body), 8-lead

3: For customers requesting a PPAP, a cus-

tomer-specific part number will be gener-

(2,3)

ated and provided.

A PPAP is not

Variant

:

VAO

VXX

= Standard Automotive

= Customer Specific Automotive

provided for VAO part numbers.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 58

SST26VF040A

11.0 APPENDIX

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 1 OF 13)

Bit

Address

Data

Comments

Address

SFDP Header

SFDP Header: 1^stDWORD

00H

01H

02H

03H

A7:A0

A15:A8

A23:A16

A31:A24

53H

46H

44H

50H

SFDP Signature

SFDP Signature = 50444653H

SFDP Header: 2^ndDWORD

04H

05H

06H

07H

A7:A0

A15:A8

A23:A16

A31:A24

06H

01H

02H

FFH

SFDP Minor Revision Number

SFDP Major Revision Number

Number of Parameter Headers (NPH) = 3

Unused. Contains FF and cannot be changed.

Parameter Headers

JEDEC Flash Parameter Header: 1^stDWORD

Parameter ID LSB Number

When this field is set to 00H, it indicates a JEDEC-specified header. For

vendor-specified headers, this field must be set to the vendor’s manufacturer

ID.

08H

09H

A7:A0

00H

06H

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters in

existing Reserved locations. Minor revisions do NOT change overall struc-

ture of SFDP. Minor revision starts at 00H.

A15:A8

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to locations

that are NOT currently Reserved. Major revisions would require code

(BIOS/firmware) or hardware change to get previously defined discoverable

parameters. Major revision starts at 01H.

0AH

0BH

A23:A16

A31:A24

01H

10H

Parameter Table Length

Number of DWORDs that are in the Parameter table.

JEDEC Flash Parameter Header: 2^ndDWORD

0CH

0DH

0EH

0FH

A7:A0

A15:A8

A23:A16

A31:A24

30H

00H

FFH

Parameter Table Pointer (PTP)

A 24-bit address that specifies the start of this header’s Parameter table in

the SFDP structure. The address must be DWORD-aligned.

Parameter ID MSB Number

JEDEC Sector Map Parameter Header: 3^rdDWORD

Parameter ID LSB Number

Sector Map Function specific table is assigned 81H.

10H

11H

A7:A0

81H

00H

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters in

existing Reserved locations. Minor revisions do NOT change overall struc-

ture of SFDP. Minor revision starts at 00H.

A15:A8

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to locations

that are NOT currently Reserved. Major revisions would require code

(BIOS/firmware) or hardware change to get previously defined discoverable

parameters. Major revision starts at 01H.

12H

13H

A23:A16

A31:A24

01H

02H

Parameter Table Length

Number of DWORDs that are in the Parameter table.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 59

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 2 OF 13)

Bit

Address

Data

Comments

JEDEC Sector Map Parameter Header: 4^thDWORD

14H

15H

16H

17H

A7:A0

A15:A8

A23:A16

A31:A24

00H

01H

00H

FFH

Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this header’s Parameter table in the

SFDP structure. The address must be DWORD-aligned.

Parameter ID MSB Number

Microchip (Vendor) Parameter Header: 5^thDWORD

ID Number

Manufacture ID (vendor specified header)

18H

A7:A0

BFH

19H

1AH

1BH

A15:A8

A23:A16

A31:A24

00H

01H

13H

Parameter Table Minor Revision Number

Parameter Table Major Revision Number, Revision 1.0

Parameter Table Length, 19 Double Words

Microchip (Vendor) Parameter Header: 6^thDWORD

1CH

1DH

1EH

1FH

A7:A0

A15:A8

A23:A16

A31:A24

00H

02H

00H

01H

Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this header’s Parameter table in the

SFDP structure. The address must be DWORD-aligned.

Used to indicate bank number (vendor specific).

JEDEC Flash Parameter Table

JEDEC Flash Parameter Table: 1^stDWORD

Block/Sector Erase Sizes

00: Reserved

A1:A0

A2

01: 4-Kbyte Erase

10: Reserved

11: Use this setting only if the 4-Kbyte erase is unavailable.

Write Granularity

0: Single-byte programmable devices or buffer programmable devices with

buffer is less than 64 bytes (32 words).

1: For buffer programmable devices when the buffer size is 64 bytes

(32 words) or larger.

30H

FDH

Volatile STATUS Register

0: Target Flash has nonvolatile Status bit. Write/Erase commands do not

require STATUS register to be written on every power-on.

1: Target Flash has volatile Status bits.

A3

A4

Write Enable Opcode Select for Writing to Volatile STATUS Register

0: 0x50. Enables a STATUS register write when bit 3 is set to ‘1’.

1: 0x06 Enables a STATUS register write when bit 3 (A3) is set to ‘1’.

A7:A5

Unused. Contains 111band cannot be changed.

31H

A15:A8

20H

4-Kbyte Erase Opcode

 2020-2021 Microchip Technology Inc.

DS20006292B-page 60

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 3 OF 13)

Bit

Address

Data

Comments

Supports (1-1-2) Fast Read

A16

0: (1-1-2) Fast Read NOT supported

1: (1-1-2) Fast Read supported

Address Bytes

Number of bytes used in addressing Flash array read, write and erase

00: 3-Byte only addressing

A18:A17

01: 3- or 4-Byte addressing (e.g., defaults to 3-Byte mode; enters 4-Byte

mode on command)

10: 4-Byte only addressing

11: Reserved

Supports Double Transfer Rate (DTR) Clocking

Indicates the device supports some type of double transfer rate clocking.

0: DTR NOT supported

A19

A20

1: DTR Clocking supported

Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output

data Fast Read.

32H

F1H

0: (1-2-2) Fast Read NOT supported

1: (1-2-2) Fast Read supported

Supports (1-4-4) Fast Read

Device supports single input opcode, quad input address, and quad output

data Fast Read

0: (1-4-4) Fast Read NOT supported

1: (1-4-4) Fast Read supported

A21

A22

Supports (1-1-4) Fast Read

Device supports single input opcode & address and quad output data Fast

Read.

0: (1-1-4) Fast Read NOT supported

1: (1-1-4) Fast Read supported

A23

Unused. Contains ‘1’ cannot be changed.

33H

A31:A24

FFH

Unused. Contains FF cannot be changed.

JEDEC Flash Parameter Table: 2^ndDWORD

34H

35H

36H

37H

A7:A0

A15:A8

A23:A16

A31:A24

FFH

3FH

00H

Flash Memory Density

SST26VF040A = 003FFFFFH

JEDEC Flash Parameter Table: 3^rdDWORD

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed before

valid output

A4:A0

00100b: 4 dummy clocks (16 dummy bits) are needed with a Quad Input

Address Phase instruction.

38H

39H

44H

Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode

Bits

010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode,

quad input address and quad output data Fast Read instruction.

A7:A5

(1-4-4) Fast Read Opcode

Opcode for single input opcode, quad input address and quad output data

Fast Read instruction.

A15:A8

EBH

 2020-2021 Microchip Technology Inc.

DS20006292B-page 61

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 4 OF 13)

Bit

Address

Data

Comments

(1-1-4) Fast Read Number of Wait states (dummy clocks) needed before

valid output

01000b: 8 dummy bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

A20:A16

3AH

08H

(1-1-4) Fast Read Number of Mode Bits

A23:A21

A31:A24

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

(1-1-4) Fast Read Opcode

Opcode for single input opcode & address and quad output data Fast Read

3BH

6BH

instruction.

JEDEC Flash Parameter Table: 4^thDWORD

(1-1-2) Fast Read Number of Wait states (dummy clocks) needed before

valid output

A4:A0

01000b: 8 dummy clocks are needed with a single input opcode, address

and dual output data Fast Read instruction.

3CH

08H

(1-1-2) Fast Read Number of Mode Bits

A7:A5

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

(1-1-2) Fast Read Opcode

3DH

3EH

3FH

A15:A8

3BH

80H

BBH

Opcode for single input opcode & address and dual output data Fast Read

instruction.

(1-2-2) Fast Read Number of Wait states (dummy clocks) needed before

valid output

00000b: 0 clocks of dummy cycle.

A20:A16

A23:A21

A31:A24

(1-2-2) Fast Read Number of Mode Bits (in clocks)

100b: 4 clocks of mode bits are needed.

(1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address, and dual output data

Fast Read instruction.

JEDEC Flash Parameter Table: 5^thDWORD

Supports (2-2-2) Fast Read

Device supports dual input opcode & address and dual output data Fast

Read.

0: (2-2-2) Fast Read NOT supported

1: (2-2-2) Fast Read supported

A0

A3:A1

A4

Reserved. Bits default to all 1’s.

40H

FEH

Supports (4-4-4) Fast Read

Device supports Quad input opcode & address and quad output data Fast

Read.

0: (4-4-4) Fast Read NOT supported

1: (4-4-4) Fast Read supported

A7:A5

A15:A8

A23:A16

A31:A24

Reserved. Bits default to all 1’s.

41H

42H

43H

FFH

JEDEC Flash Parameter Table: 6^thDWORD

44H

45H

A7:A0

FFH

Reserved. Bits default to all 1’s.

A15:A8

 2020-2021 Microchip Technology Inc.

DS20006292B-page 62

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 5 OF 13)

Bit

Address

Data

Comments

(2-2-2) Fast Read Number of Wait states (dummy clocks) needed before

valid output

00000b: No dummy bit is needed

A20:A16

A23:A21

A31:A24

46H

00H

(2-2-2) Fast Read Number of Mode Bits

000b: No mode bits are needed

(2-2-2) Fast Read Opcode

Opcode for dual input opcode & address and dual output data Fast Read (not

47H

FFH

supported).

JEDEC Flash Parameter Table: 7^thDWORD

48H

49H

A7:A0

FFH

Reserved. Bits default to all 1’s.

A15:A8

(4-4-4) Fast Read Number of Wait states (dummy clocks) needed before

valid output

00100b: 4 clocks dummy are needed with a quad input opcode & address

and quad output data Fast Read instruction.

A20:A16

4AH

44H

(4-4-4) Fast Read Number of Mode Bits

A23:A21

A31:A24

010b: 2 clocks mode bits are needed with a quad input opcode & address

and quad output data Fast Read instruction.

(4-4-4) Fast Read Opcode

Opcode for quad input opcode/address, quad output data Fast Read.

4BH

0BH

JEDEC Flash Parameter Table: 8^thDWORD

Sector Type 1 Size

4CH

4DH

4EH

4FH

A7:A0

A15:A8

A23:A16

A31:A24

0CH

20H

0FH

D8H

4-Kbyte, Sector/Block size = 2^Nbytes

Sector Type 1 Opcode

Opcode used to erase the number of bytes specified by Sector Type 1 Size.

Sector Type 2 Size

32-Kbyte, Sector/Block size = 2^Nbytes

Sector Type 2 Opcode

Opcode used to erase the number of bytes specified by Sector Type 2 Size.

JEDEC Flash Parameter Table: 9^thDWORD

Sector Type 3 Size

50H

51H

52H

53H

A7:A0

A15:A8

A23:A16

A31:A24

10H

D8H

00H

64-Kbyte, Sector/Block size = 2^Nbytes

Sector Type 3 Opcode

Opcode used to erase the number of bytes specified by Sector Type 3 Size.

Sector Type 4 Size

64-Kbyte, Sector/Block size = 2^Nbytes

Sector Type 4 Opcode

Opcode used to erase the number of bytes specified by Sector Type 4 Size.

JEDEC Flash Parameter Table: 10^thDWORD

Multiplier from typical erase time to maximum erase time.

Maximum time = 2*(count +1)*Typical erase time

Count = 0

A3:A0 = 0000b

A3:A0

A7:A4

Erase Type 1 Erase, Typical time

Typical time = (count+1)*units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

10:9 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A8:A4 count = 18 = 10010b

54H

20H

A10:A9 unit = 1 ms = 00b

 2020-2021 Microchip Technology Inc.

DS20006292B-page 63

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 6 OF 13)

Bit

Address

Data

Comments

A10:A8

A15:A11

A17:A16

A23:A18

A24

A10:A8 = 001b

Erase Type 2 Erase, Typical time

Typical time = (count+1)*units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

17:16 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A15:A11 count = 18 = 10010b

55H

91H

A17:A16 unit = 1 ms = 00b

A17:A16 = 00b

Erase Type 3 Erase, Typical time

Typical time = (count+1)*units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

24:23 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A22:A18 count = 18 = 10010b

56H

57H

48H

24H

A24:A23 unit = 1ms = 00b

A24 = 0b

Erase Type 4 Erase, Typical time

Typical time = (count+1)*units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

31:30 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A29:A25 count = 18 = 10010b

A31:A25

A31:A30 unit = 1 ms = 00b

JEDEC Flash Parameter Table: 11^thDWORD

Multiplier from typical program time to maximum program time

Maximum time = 2*(count +1)*Typical program time

Count = 0

A3:A0 = 0000b

A3:A0

A7:A4

58H

80H

Page Size

Page size = 2^N bytes

N = 8

A7:A4 = 1000b

Page Program Typical time,

Program time = (count+1)*units

13 units (0b: 8 µs, 1b: 64 µs)

A12:A8 count = 11 = 01111b

A13 unit = 64 µs = 1b

A31:A8

59H

6FH

Byte Program Typical time, first byte

Typical time = (count+1)*units

18 units (0b: 1 µs, 1b: 8 µs)

A17:A14 count = 5 = 0101b

A18 = 8 µs = 1b

A15:A14

A18:A16

A23:A19

A18:A16 = 101b

Byte Program Typical time, additional byte

Typical time = (count+1)*units

23 units (0b: 1 µs, 1b: 8 µs)

A22:A19 count = 0011b

5AH

1DH

A23 = 1 µs = 0b

 2020-2021 Microchip Technology Inc.

DS20006292B-page 64

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 7 OF 13)

Bit

Address

Data

Comments

Chip Erase Typical time

Typical time = (count+1)*units

A30:A24

16 ms to 512 ms, 256 ms to 8192 ms, 4s to 128s, 64s to 2048s

A28:A24 count = 1 = 00001b

A30:A29 units = 16 ms = 00b

5AH

81H

Reserved

A31 = 1b

A31

JEDEC Flash Parameter Table: 12^thDWORD

Prohibited Operations During Program Suspend

xxx0b: May not initiate a new erase anywhere

xxx1b: May not initiate a new erase in the program suspended page

size

xx0xb: May not initiate a new page program anywhere

xx1xb: May not initiate a new page program in program suspended page

size

A3:A0

x0xxb: Refer to the data sheet

x1xxb: May not initiate a read in the program suspended page size

0xxxb: Additional erase or program restrictions apply

1xxxb: The erase and program restrictions in bits 1:0 are sufficient

5CH

EDH

Prohibited Operation During Erase Suspend

xxx0b: May not initiate a new erase anywhere

xxx1b: May not initiate a new erase in the erase suspended page size

xx0xb: May not initiate a new page program anywhere

xx1xb: May not initiate a new page program in erase suspended erase

type size

A7:A4

x0xxb: Refer to the data sheet

x1xxb: May not initiate a read in the erase suspended page size

0xxxb: Additional erase or program restrictions apply

1xxxb: The erase and program restrictions in bits 5:4 are sufficient

A8

Reserved = 1b

Program Resume to Suspend Interval

The device requires this typical amount of time to make progress on the

program operation before allowing another suspend.

Interval = 500 µs

A12:A9

Program resume to suspend interval = (count+1)*64 µs

A12:A9 = 7 = 0111b

Suspend in-progress program max latency

Maximum time required by the Flash device to suspend an in-progress

program and be ready to accept another command which accesses the

Flash array.

5DH

0FH

A15:A13

Max. latency = 25 µs

program max. latency =(count+1)*units

units (00b: 128 ns, 01b: 1 µs, 10b: 8 µs, 11b: 64 µs)

A17:A13 = count = 24 = 11000b

A19:A18 = 1 µs = 01b

A19:A16

A23:A20

0111b

Erase Resume to Suspend Interval

The device requires this typical amount of time to make progress on the

erase operation before allowing another suspend.

Interval = 500 µs

5EH

77H

Erase resume to suspend interval = (count+1)*64 µs

A23:A20 = 7 = 0111b

 2020-2021 Microchip Technology Inc.

DS20006292B-page 65

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 8 OF 13)

Bit

Address

Data

Comments

Suspend in-progress erase max. latency

Maximum time required by the Flash device to suspend an in-progress erase

and be ready to accept another command which accesses the Flash array.

Max. latency = 25 µs

A30:A24

Erase max. latency = (count+1)*units

units (00b: 128 ns, 01b: 1µs, 10b: 8 µs, 11b: 64 µs)

A28:A24= count = 24 = 11000b

5FH

38H

A30:A29 = 1 µs = 01b

Suspend/Resume supported

0: supported

A31

1: not supported

JEDEC Flash Parameter Table: 13^thDWORD

60H

61H

62H

63H

A7:A0

A15:A8

A23:A16

A31:A24

30H

B0H

30H

B0H

Program Resume Instruction

Program Suspend Instruction

Resume Instruction

Suspend Instruction

JEDEC Flash Parameter Table: 14^thDWORD

A1:A0

Reserved = 11b

STATUS Register Polling Device Busy

111101b: Use of legacy polling is supported by reading the STATUS register

with 05h instruction and checking WIP bit [0] (0= ready, 1= busy)

64H

65H

F7H

A9H

A7:A2

Exit Deep Power-Down to next operation delay – 10 µs

Delay = (count+1)*unit

A12:A8 = count = 9 = 01001b

A14:A8

A14:A13 units = 01b = 1 µs

Exit Power-Down Instruction – ABH= 10101011b

A15 = 1b

A15

A22:A16

A23

A22:A16 = 1010101b

66H

67H

D5H

5CH

Enter Power-Down Instruction – B9H = 10111001b

A23 = 1b

A30:A24

A30:A24 = 1011100

Deep Power-Down Supported

0: supported

A31

1: not supported

JEDEC Flash Parameter Table: 15^thDWORD

4-4-4 mode disable sequences

A3:A0

Xxx1b: issue FF instruction

1xxxb: issue the Soft Reset 66/99 sequence

68H

69H

29H

C2H

4-4-4 mode enable sequences

X_xx1xb: issue instruction 38H

A7:A4

A8

4-4-4 mode enable sequences

A8 = 0

0-4-4 mode supported

0: not supported

1: supported

A9

0-4-4 Mode Exit Method

A15:A10

X1_xxxx: Mode Bit[7:0] Not = AXh

1x_xxxx: Reserved = 1

 2020-2021 Microchip Technology Inc.

DS20006292B-page 66

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 9 OF 13)

Bit

Address

Data

Comments

0-4-4 Mode Entry Method

X1xxb: M[7:0] = AXh

1xxxb: Reserved = 1

A19:A16

A22:A20

6AH

6BH

5CH

FFH

Quad Enable Requirements (QER)

101b: Quad Enable is bit 1 of the Configuration register.

HOLD and Reset Disable

0: feature is not supported

A23

A31:A24

Reserved bits = 0xFF

JEDEC Flash Parameter Table: 16^thDWORD

Volatile or Nonvolatile Register and Write Enable Instructions for STATUS

Register 1

Xx1_xxxxb: STATUS Register 1 contains a mix of volatile and nonvolatile

bits. The 06h instruction is used to enable writing to the register.

X1x_xxxxb: Reserved = 1

A6:A0

6C

6D

F0H

30H

1xx_xxxxb: Reserved = 1

A7

Reserved =1b

Soft Reset and Rescue Sequence Support

X1_xxxxb: Reset Enable instruction 66h is issued followed by Reset

instruction 99h.

A13:A8

1x_xxxxb: exit 0-4-4 mode is required prior to other Reset sequences.

Exit 4-Byte Addressing

Not supported

A15:A14

A23:A16

Exit 4-Byte Addressing

Not supported

A21:A14 = 00000000b

A23 and A22 are Reserved bits which are = 1

6E

6F

C0H

80H

Enter 4-Byte Addressing

Not supported

A31:A24

1xxx_xxxx: Reserved = 1

JEDEC Sector Map Parameter Table

A7:A2 = Reserved = 111111b

A1 = Descriptor Type = Map = 1b

A0 = Last map = 1b

100H

A7:A0

FFH

101H

102H

103H

104H

A15:A8

A23:A16

A31:A24

A7:A0

00H

FFH

F7H

Configuration ID = 00h

Region Count = 1 Region

Reserved = FFh

Region 0 supports 4-Kbyte erase, 32-Kbyte erase and 64-Kbyte erase

A3:A0 = 0111b

A7:A4 = Reserved = 1111b

105H

A15:A8

FFH

Region 0 Size

For 4 Mbit device

Count = 4 Mbit/256 bytes = 2048

Value = count - 1 = 2047

A31:A8 = 0007FFh

106H

107H

A23:A16

A31:A24

07H

00H

 2020-2021 Microchip Technology Inc.

DS20006292B-page 67

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 10 OF 13)

Bit

Address

Data

Comments

SST26VF040A (Vendor) Parameter Table

SST26VF040A Identification

200H

201H

A7:A0

BFH

26H

Manufacturer ID

Memory Type

A15:A8

Device ID

SST26VF040A = 14H

202H

203H

A23:A16

A31:A24

14H

FFH

Reserved. Bits default to all 1’s.

SST26VF040A Interface

Interfaces Supported

000: SPI only

001: Power-up default is SPI; Quad can be enabled/disabled

010: Reserved

●

A2:A0

●

111: Reserved

Supports Enable Quad

0: not supported

1: supported

A3

A6:A4

A7

204H

B9H

Supports Hold#/RST# Function

000: Hold#

001: RST#

010: HOLD/RST#

011: I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read

Supports Software Reset

0: not supported

1: supported

Supports Quad Reset

0: not supported

1: supported

A8

A10:A9

A13:A11

Reserved. Bits default to all 1’s.

Byte-Program or Page-Program (256 Bytes)

011: Byte Program/Page Program in SPI and Quad Page Program once

Quad is enabled

205H

DFH

Program-Erase Suspend Supported

0: Not Supported

1: Program/Erase Suspend Supported

A14

A15

Deep Power-Down Mode Supported

0: Not Supported

1: Deep Power-Down Mode Supported

 2020-2021 Microchip Technology Inc.

DS20006292B-page 68

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 11 OF 13)

Bit

Address

Data

Comments

OTP Capable (Security ID) Supported

A16

A17

A18

0: not supported

1: supported

Supports Block Group Protect

0: not supported

1: supported

Supports Independent Block Protect

0: not supported

206H

F3H

1: supported

Supports Independent Nonvolatile Lock (Block or Sector becomes

OTP)

0: not supported

1: supported

A19

A23:A20

A31:A24

A7:A0

Reserved. Bits default to all 1’s.

207H

208H

209H

20AH

20BH

FFH

30H

F2H

60H

F3H

VDD Minimum Supply Voltage

2.30V (F230)

A15:A8

A23:A16

A31:A24

VDD Maximum Supply Voltage

3.60V (F360H)

Typical Time-out for Byte Program: 50 µs

20CH

A7:A0

32H

Typical time-out for Byte Program is in µs. Represented by conversion of the

actual time from the decimal to hexadecimal number.

20DH

20EH

A15:A8

FFH

0AH

Reserved. Bits default to all 1’s.

A23:A16

Typical Time-out for Page Program: 1.0 ms (xxH*(0.1 ms)

Typical Time-out for Sector Erase/Block Erase: 18 ms

20FH

210H

211H

A31:A24

A7:A0

12H

23H

46H

Typical time-out for Sector/Block-Erase is in ms. Represented by conversion

of the actual time from the decimal to hexadecimal number.

Typical Time-out for Chip Erase: 35 ms

Typical time-out for Chip Erase is in ms. Represented by conversion of the

actual time from the decimal to hexadecimal number.

Maximum Time-out for Byte Program: 70 µs

Typical time-out for Byte Program is in µs. Represented by conversion of the

actual time from the decimal to hexadecimal number.

A15:A8

212H

213H

A23:A16

A31:A24

FFH

0FH

Reserved. Bits default to all 1’s.

Maximum Time-out for Page Program: 1.5 ms

Typical time-out for Page Program in xxH*(0.1 ms) ms

Maximum Time-out for Sector Erase/Block Erase: 25 ms

Maximum time-out for Sector/Block Erase in ms

214H

215H

216H

A7:A0

A15:A8

A23:A16

19H

32H

0FH

Maximum Time-out for Chip Erase: 50 ms.

Maximum time-out for Chip Erase in ms.

Maximum Time-out for Program Security ID: 1.5 ms

Maximum time-out for Program Security ID in xxH*(0.1 ms) ms

Maximum Time-out for Write Protection Enable Latency: 25 ms

Maximum time-out for Write Protection Enable Latency is in ms. Repre-

sented by conversion of the actual time from the decimal to hexadecimal

number.

217H

218H

A31:A24

A7:A0

19H

Maximum Time-out for Write Suspend Latency: 25 µs

Maximum time-out for Write Suspend Latency is in µs. Represented by con-

version of the actual time from the decimal to hexadecimal number.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 69

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 12 OF 13)

Bit

Address

Data

Comments

Maximum Time to Deep Power-Down

3 µs = 03H

219H

21AH

A15:A8

03H

0AH

Maximum Time-out from Deep Power-Down mode to Standby mode

10 µs = 0AH

A23:A16

21BH

21CH

21DH

21EH

21FH

A31:A24

A7:A0

FFH

Reserved. Bits default to all 1’s.

A15:A8

A23:A16

A31:A24

Supported Instructions

220H

221H

222H

223H

224H

225H

226H

227H

228H

229H

22AH

22BH

22CH

22DH

22EH

22FH

230H

231H

232H

233H

234H

235H

236H

237H

238H

239H

23AH

23BH

A7:A0

A15:A8

A23:A16

A31:A24

A7:A0

00H

66H

99H

38H

FFH

05H

01H

35H

06H

04H

02H

32H

B0H

30H

FFH

88H

A5H

85H

C0H

9FH

AFH

5AH

B9H

ABH

No Operation

Reset Enable

Reset Memory

Enable Quad I/O

Reset Quad I/O

A15:A8

A23:A16

A31:A24

A7:A0

Read STATUS Register

Write STATUS Register

Read Configuration Register

Write Enable

A15:A8

A23:A16

A31:A24

A7:A0

Write Disable

Byte Program or Page Program

SPI Quad Page Program

Suspends Program/Erase

Resumes Program/Erase

Reserved

A15:A8

A23:A16

A31:A24

A7:A0

Reserved

A15:A8

A23:A16

A31:A24

A7:A0

Reserved

Read Security ID

Program User Security ID Area

Lockout Security ID Programming

Set Burst Length

JEDEC-ID

A15:A8

A23:A16

A31:A24

A7:A0

Quad J-ID

A15:A8

A23:A16

A31:A24

SFDP

Deep Power-Down Mode

Release Deep Power-Down Mode

(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy clocks)

needed before valid output

A4:A0

00110b: 6 clocks of dummy cycle

23CH

23DH

06H

(1-4-4) SPI nB Burst with Wrap Number of Mode Bits

000b: Set Mode bits are not supported

A7:A5

A15:A8

ECH

(1-4-4) SPI nB Burst with Wrap Opcode

 2020-2021 Microchip Technology Inc.

DS20006292B-page 70

SST26VF040A

TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 13 OF 13)

Bit

Address

Data

Comments

(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy clocks)

needed before valid output

00110b: 6 clocks of dummy cycle

A20:A16

23EH

23FH

06H

0CH

A23:A21

A31:A24

000b: Set Mode bits are not supported

(4-4-4) SQI nB Burst with Wrap Opcode

(1-1-1) Read Memory Number of Wait states (dummy clocks) needed

before valid output

A4:A0

00000b: Wait states/dummy clocks are not supported

240H

241H

242H

00H

03H

08H

(1-1-1) Read Memory Number of Mode Bits

000b: Mode bits are not supported

A7:A5

A15:A8

(1-1-1) Read Memory Opcode

(1-1-1) Read Memory at Higher Speed Number of Wait states (dummy

clocks) needed before valid output

01000: 8 clocks (8 bits) of dummy cycle

A20:A16

(1-1-1) Read Memory at Higher Speed Number of Mode Bits

000b: Mode bits are not supported

A23:A21

243H

244H

245H

246H

247H

248H

A31:A24

A7:A0

0BH

FFH

(1-1-1) Read Memory at Higher Speed Opcode

Reserved. Bits default to all 1’s.

A15:A8

A23:A16

A31:A24

A7:A0

Reserved. Bits default to all 1’s.

Security ID size in bytes

Example: If the size is 2 Kbytes, this field would be 07FFH

Security ID Range

249H

A15:A8

07H

Unique ID

0000H-000FH

(preprogrammed at factory)

User-programmable

0010H-07FFH

24AH

24BH

A23:A16

A31:A24

FFH

Reserved. Bits default to all 1’s.

 2020-2021 Microchip Technology Inc.

DS20006292B-page 71

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specifications contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip

devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications

contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished

without violating Microchip's intellectual property rights.

•

Microchip is willing to work with any customer who is concerned about the integrity of its code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not

mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are

committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection

feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or

other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication is provided for the sole

purpose of designing with and using Microchip products. Infor-

mation regarding device applications and the like is provided

only for your convenience and may be superseded by updates.

It is your responsibility to ensure that your application meets

with your specifications.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A. and

other countries.

THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION INCLUDING BUT NOT

LIMITED TO ANY IMPLIED WARRANTIES OF NON-

INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A

PARTICULAR PURPOSE OR WARRANTIES RELATED TO

ITS CONDITION, QUALITY, OR PERFORMANCE.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions

Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight

Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,

Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-

Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-

RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-

TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND

WHATSOEVER RELATED TO THE INFORMATION OR ITS

USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS

BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES

ARE FORESEEABLE. TO THE FULLEST EXTENT

ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON

ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION

OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF

ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP

FOR THE INFORMATION. Use of Microchip devices in life sup-

port and/or safety applications is entirely at the buyer's risk, and

the buyer agrees to defend, indemnify and hold harmless

Microchip from any and all damages, claims, suits, or expenses

resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights

unless otherwise stated.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,

BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,

CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,

Dynamic Average Matching, DAM, ECAN, Espresso T1S,

EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,

INICnet, Intelligent Paralleling, Inter-Chip Connectivity,

JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,

MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,

NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,

PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,

Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,

simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,

SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total

Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,

ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks

of Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

Reserved.

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

ISBN: 978-1-5224-8560-5

 2020-2021 Microchip Technology Inc.

DS20006292B-page 72

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4485-5910

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-72400

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS20006292B-page 73

 2020-2021 Microchip Technology Inc.

02/28/20


型号：	SST26VF040AT-104E/MFVAO
厂家：	MICROCHIP
描述：	2.5V/3.0V 4-Mbit Serial Quad I/Oâ¢ (SQIâ¢) Flash Memory
文件：	总73页 (文件大小：781K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST26VF040AT-104E/MFVAO [MICROCHIP]

相关型号：

SST26VF040AT-104E/MFVXX

SST26VF040AT-104E/SNVAO

SST26VF040AT-104E/SNVXX

SST26VF040AT-104I/MFVAO

SST26VF040AT-104I/MFVXX

SST26VF040AT-104I/SNVAO

SST26VF040AT-104I/SNVXX

SST26VF040AT-80E/MF70SVAO

SST26VF040AT-80E/MFVAO

SST26VF040AT-80E/MFVXX

SST26VF040AT-80E/SN70SVAO

SST26VF040AT-80E/SNVAO