SST39VF1601C-70-4C-MAQE [MICROCHIP]
1M X 16 FLASH 2.7V PROM, 70 ns, PBGA48, 4 X 6 MM, 0.50 MM HEIGHT, ROHS COMPLIANT, MO-207CB-4, WFBGA-48;
| 型号： | SST39VF1601C-70-4C-MAQE |
| 厂家： | 
MICROCHIP |
| 描述： | 1M X 16 FLASH 2.7V PROM, 70 ns, PBGA48, 4 X 6 MM, 0.50 MM HEIGHT, ROHS COMPLIANT, MO-207CB-4, WFBGA-48 可编程只读存储器 内存集成电路 闪存 |
| 文件： | 总39页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
The SST39VF1601C / SST39VF1602C devices are 1M x16 CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared with alternate
approaches. The SST39VF1601C / SST39VF1602C write (Program or Erase)
with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pin-
outs for x16 memories.
Features
• Organized as 1M x16: SST39VF1601C/1602C
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– 2.7-3.6V
– 70 ns
• Superior Reliability
• Fast Erase and Word-Program:
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Automatic Write Timing
– Internal VPP Generation
• Hardware Block-Protection/WP# Input Pin
• End-of-Write Detection
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• Sector-Erase Capability
– Uniform 2 KWord sectors
• CMOS I/O Compatibility
• Block-Erase Capability
• JEDEC Standard
– Flexible block architecture; one 8-, two 4-, one 16-, and
thirty one 32-KWord blocks
– Flash EEPROM Pinouts and command sets
• Chip-Erase Capability
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• All devices are RoHS compliant
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Product Description
The SST39VF1601C and SST39VF1602C devices are 1M x16 CMOS Multi-Purpose Flash Plus
(MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF160xC writes (Program or Erase) with a 2.7-3.6V
power supply. These devices conform to JEDEC standard pinouts for x16 memories.
Featuring high performance Word-Program, the SST39VF1601C/1602C devices provide a typical
Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling, or the RY/BY# pin to indi-
cate the completion of Program operation. To protect against inadvertent write, they have on-chip hard-
ware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum
of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST39VF1601C/1602C devices are suited for applications that require convenient and economi-
cal updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF1601C/1602C are offered in 48-lead
TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4 for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
2
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Block Diagram
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
I/O Buffers and Data Latches
DQ - DQ
Control Logic
RESET#
RY/BY#
15
0
1380 B1.0
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
3
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Pin Assignments
A16
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
V
DQ15
SS
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
1380 48-tsop P01.0
Figure 2: Pin Assignments for 48-Lead TSOP
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
4
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
TOP VIEW (balls facing down)
SST39VF1601C/1602C
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15 V
SS
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC A19 DQ5 DQ12
V
DQ4
DD
RY/BY#WP# A18 NC DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E F G H
1380 48-tfbga B3K P02.0
Figure 3: Pin Assignments for 48-Ball TFBGA
TOP VIEW (balls facing down)
SST39WF160xC
6
5
4
3
2
1
A2
A1
A0
A4
A3
A6 A17 NC NC WE# RST# A9 A11
A7 WP# RY/BY# A10 A13 A14
A5 A18
A8 A12 A15
DQ4 DQ11 A16
CE# DQ8 DQ10
V
OE# DQ9 A19
NC DQ5 DQ6 DQ7
SS
DQ0 DQ1 DQ2 DQ3
V
DQ12 DQ13 DQ14 DQ15 V
DD SS
A B C D E F G H J K L
1380 48-wfbga MAQ P03.0
Figure 4: Pin Assignments for 48-Ball WFBGA
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
5
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Table 1: Pin Description
Symbol
AMS1-A0
Pin Name
Functions
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
CE#
OE#
WE#
VDD
Reset
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
VSS
NC
No Connection
Ready/Busy#
Unconnected pins.
RY/BY#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25018
1. AMS = Most significant address
AMS = A19
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
6
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Table 2: Top / Bottom Boot Block Address
Bottom Boot Block Address SST39VF1601C
Top Boot Block Address SST39VF1602C
Size
(KWord)
Size
#
Address Range
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
4
34
8
FE000H-FFFFFH
FD000H-FDFFFH
FC000H-FCFFFH
F8000H-FBFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
04000H-07FFFH
03000H-03FFFH
02000H-02FFFH
00000H-01FFFH
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
4
4
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
4
0
0
8
T2.25018
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
7
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF1601C/1602C also have the Auto Low Power mode which puts the device in a near
standby mode after data has been accessed with a valid Read operation. This reduces the IDD active
read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD
active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition used to initiate another Read cycle, with
no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF1601C/1602C is controlled by CE# and OE#, both have to be low
for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details (Figure 6).
Word-Program Operation
The SST39VF1601C/1602C are programmed on a word-by-word basis. Before programming, the sec-
tor where the word exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
word address and word data. During the Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figures 7 and 8 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 22 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to
perform additional tasks. Any commands issued during the internal Program operation are ignored.
During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF1601C/1602C offer both Sector-Erase and Block-Erase mode.
The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—thirty-one 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord
blocks. See Figure 5 for top and bottom boot device block addresses. The Sector-Erase operation is
initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector
address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte com-
mand sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Tog-
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
8
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
gle Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any
commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any
attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence,
WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF1601C/1602C provide a Chip-Erase operation, which allows the user to erase the entire
memory array to the ‘1’ state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF1601C/1602C provide two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
9
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data# Polling (DQ7)
When the SST39VF1601C/1602C are in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.
Table 3: Write Operation Status
Status
Normal Operation
DQ7
DQ7#
0
DQ6
Toggle
Toggle
1
DQ2
No Toggle
Toggle
RY/BY#
Standard Program
Standard Erase
0
0
1
Erase-Suspend Mode Read from Erase-
Suspended Sector/Block
1
Toggle
Read from Non-Erase-
Suspended Sector/Block
Program
Data
Data
Data
N/A
1
0
DQ7#
Toggle
T3.0 25018
Note: DQ7 and DQ2 require a valid address when reading status information.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
10
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Data Protection
The SST39VF1601C/1602C provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF1602C supports top hardware block protection, which protects the top 8 KWord block of
the device. The SST39VF1601C supports bottom hardware block protection, which protects the bot-
tom 8KWord block of the device. The Boot Block address ranges are described in Table 4. Program
and Erase operations are prevented on the 8 KWord when WP# is low. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase
operations on that block.
Table 4: Boot Block Address Ranges
Product
Address Range
00000H - 01FFFH
FE000H - FFFFFH
Bottom Boot Block
SST39VF1601C
Top Boot Block
SST39VF1602C
T4.0 25018
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place (see Figure 18).
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF1601C/1602C provide the JEDEC approved Software Data Protection scheme for all
data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of
the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, pro-
viding optimal protection from inadvertent Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are
shipped with the Software Data Protection permanently enabled. See Table 7 for the specific software
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
11
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
command codes. During SDP command sequence, invalid commands will abort the device to read
mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39VF1601C/1602C also contain the CFI information to describe the characteristics of the
device. In order to enter the CFI Query mode, the system writes a three-byte sequence, same as prod-
uct ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence.
Additionally, the system can use the one-byte sequence with 55H on the Address and 89H on the Data
Bus to enter the CFI Query mode. Once the device enters the CFI Query mode, the system can read
CFI data at the addresses given in Tables 8 through 10. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF1601C, SST39VF1602C, and
manufacturer as SST. This mode may be accessed software operations. Users may use the Software
Product Identification operation to identify the part (i.e., using the device ID) when using multiple man-
ufacturers in the same socket. For details, see Table 7 for software operation, Figure 14 for the Soft-
ware ID Entry and Read timing diagram and Figure 24 for the Software ID Entry command sequence
flowchart.
Table 5: Product Identification
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST39VF1601C
SST39VF1602C
0001H
0001H
234FH
234EH
T5.2 25018
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
12
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig-
ure 25 for flowcharts.
Security ID
The SST39VF1601C/1602C devices offer a 136 Word Security ID space. The Secure ID space is
divided into two segments—one factory programmed segment and one user programmed segment.
The first segment is programmed and locked at SST with a random 128-bit number. The user segment,
with a 128 word space, is left un-programmed for the customer to program as desired.
To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com-
mand should be executed. Refer to Table 7 for more details.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
13
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Operations
Table 6: Operation Modes Selection
Mode
Read
Program
Erase
CE#
VIL
VIL
OE#
VIL
VIH
VIH
WE# DQ
Address
AIN
AIN
VIH
VIL
VIL
DOUT
DIN
X1
VIL
Sector or block address, XXH for Chip-
Erase
Standby
Write Inhibit
VIH
X
X
X
VIL
X
X
X
VIH
High Z
High Z/ DOUT
High Z/ DOUT
X
X
X
Product Identification
Software Mode
VIL
VIL
VIH
See Table 7
T6.0 25018
1. X can be VIL or VIH, but no other value.
Table 7: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
3rd Bus
4th Bus
5th Bus
Write Cycle Write Cycle
6th Bus
Write Cycle Write Cycle Write Cycle
Data
Data Addr Data Addr
Data Addr Data
2
2
1
2
1
2
1
2
Addr1
Addr1
Data2 Addr1
Word-Program
Sector-Erase
Block-Erase
555H
555H
555H
555H
AAH 2AAH 55H 555H A0H WA3 Data
4
4
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX
50H
30H
Chip-Erase
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Erase-Suspend
Erase-Resume
Query Sec ID5
XXXH B0H
XXXH 30H
555H
555H
AAH 2AAH 55H 555H 88H
AAH 2AAH 55H 555H A5H WA6 Data
User Security ID
Word-Program
User Security ID
Program Lock-
Out
555H
555H
AAH 2AAH 55H 555H 85H XXH6 0000
H
Software ID
Entry7,8
AAH 2AAH 55H 555H 90H
CFI Query Entry
CFI Query Entry
555H
55H
AAH 2AAH 55H 555H 98H
98H
Software ID
Exit9,10
555H
AAH 2AAH 55H 555H F0H
/CFI Exit/Sec ID
Exit
Software ID
Exit9,10
XXH
F0H
/CFI Exit/Sec ID
Exit
T7.6 25018
1. Address format A10-A0 (Hex). Addresses A11-A19 can be VIL or VIH, but no other value, for Command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address; AMS = A19
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
14
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1601C Device ID = 234FH, is read with A0 = 1, SST39VF1602C Device ID = 234EH, is read with A0 = 1,
A
MS = Most significant address; AMS = A19
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000008H-000087H.
Table 8: CFI Query Identification String1
Address
10H
Data
Data
0051H Query Unique ASCII string “QRY”
11H
0052H
12H
0059H
13H
0002H Primary OEM command set
14H
0000H
15H
0000H Address for Primary Extended Table
16H
0000H
17H
0000H Alternate OEM command set (00H = none exists)
18H
0000H
19H
0000H Address for Alternate OEM extended Table (00H = none exits)
0000H
1AH
T8.1 25018
1. Refer to CFI publication 100 for more details.
Table 9: System Interface Information
Address
Data
0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
Data
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H VPP min. (00H = no VPP pin)
0000H VPP max. (00H = no VPP pin)
0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
0000H Maximum time out for buffer program 2N times typical
0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T9.3 25018
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
15
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Table 10:Device Geometry Information
Address
Data
Data
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
0000H
0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
0000H
0005H Number of Erase Sector/Block sizes supported by device
0000H Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100)
0000H
0040H
0000H
0001H Erase Block Region 2 Information
0000H
0020H
0000H
0000H Erase Block Region 3 Information
0000H
0080H
0000H
001EH Erase Block Region 4 Information
0000H
0000H
0001H
T10.0 25018
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
16
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 11:Operating Range
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
T11.1 25018
Table 12:AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T12.1 25018
1. See Figures 20 and 21
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100
ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware
reset is required. The recommended VDD power-up to RESET# high time should be greater than 100
µs to ensure a proper reset.
10 0 µs
T
PU-READ
V
min
V
DD
DD
0V
V
IH
RESET#
T
50 ns
RHR
CE#
1380 F24.0
Figure 5: Power-Up Diagram
Table 13:DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
IDD
Power Supply Current
VDD=VDD Max
Read3
18
mA
CE#=VIL, OE#=WE#=VIH, all I/Os
open
Program and Erase
Standby VDD Current
Auto Low Power
35
20
20
mA
µA
µA
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
ISB
IALP
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
WP#=GND to VDD or RST#=GND to
VDD
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
IOH=-100 µA, VDD=VDD Min
T13.8 25018
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 20
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
18
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Table 14:Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T14.0 25018
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 15:Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T15.0 25018
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 16:Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
1
TDR
1
ILTH
100 + IDD
JEDEC Standard 78
T16.2 25018
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
19
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
AC Characteristics
Table 17:Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
TOE
TCLZ
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
ns
TOLZ
TCHZ
ns
1
1
20
20
ns
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T17.3 25018
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-
Erase operations.
Table 18:Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
TBP
Word-Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
TWPH
WE# Pulse Width
ns
1
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
ms
ns
TBE
Block-Erase
25
TSCE
Chip-Erase
50
1,2
TBY
TBR
RY/BY# Delay Time
Bus Recovery Time
90
1
0
µs
T18.1 25018
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
20
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
T
OH
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1380 F03.0
Note: AMS = Most significant address
AMS = A19
Figure 6: Read Cycle Timing Diagram
T
BP
555
2AA
555
ADDR
ADDRESSES
T
AH
T
WP
WE#
T
T
WPH
AS
OE#
T
CH
CE#
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1380 F25.0
Note: WP# must be held in proper logic state (VIL
or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 7: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
21
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESSES
T
AH
T
CP
WE#
T
CPH
T
AS
OE#
T
CH
CE#
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1380 F26.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 8: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
19-0
T
CE
CE#
T
T
OES
OEH
OE#
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1380 F27.0
Figure 9: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
22
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
OEH
T
OES
T
OE
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1380 F07.0
Note: AMS = Most significant address
AMS = A19
Figure 10:Toggle Bits Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESSES
CE#
OE#
WE#
T
OEH
T
T
BR
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX10
XX80
VALID
1380 F31.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 11:WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
23
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
BE
555
2AA
BA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX30
XX80
VALID
1380 F32.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 12:WE# Controlled Block-Erase Timing Diagram
T
SIX-BYTE CODE FOR SECTOR-ERASE
555 555 2AA
SE
555
2AA
SA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX50
XX80
VALID
1380 F28.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 18).
SAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 13:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
24
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Three-Byte Sequence for Software ID Entry
555
2AA
555
0000
0001
ADDRESS
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX90
SW2
Device ID
00BF
DQ
15-0
1380 F11.0
Note: Device ID = 234BH for SST39VF1601C and 234AH for SST39VF1602C.
WP# must be held in proper logic state (VIL or VIH) 1µs after the command sequence.
X can VIL or VIH but no other value.
Figure 14:Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS
CE#
555
2AA
555
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
XXAA
SW0
XX55
SW1
XX98
SW2
15-0
1380 F12.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs after the command sequence.
X can VIL or VIH but no other value.
Figure 15:CFI Query Entry and Read
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
25
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS
555
2AA
555
DQ
XXAA
XX55
XXF0
15-0
T
IDA
CE#
OE#
WE#
T
WP
T
WHP
SW0
SW1
SW2
1380 F13.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can VIL or VIH but no other value.
Figure 16:Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
555
2AA
555
MS-0
CE#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX88
SW2
DQ
15-0
1380 F20.0
Note: AMS = Most signifi-
cant address
AMS = A19
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can VIL or VIH but no other value.
Figure 17:Sec ID Entry
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
26
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
RY/BY#
0V
T
RP
RST#
T
RHR
CE#/OE#
1380 F29.0
Figure 18:RST# Timing Diagram (When no internal operation is in progress)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
1380 F30.0
Figure 19:RST# Timing Diagram (During Program or Erase operation)
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1380F14.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Mea-
surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise
and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 20:AC Input/Output Reference Waveforms
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
27
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
TO TESTER
TO DUT
CL
1380 F15.0
Figure 21:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
28
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
X can be V or V , but no other value
IL IH
1380 F16.0
Figure 22:Word-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
29
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Toggle Bit
Data# Polling
RY/BY#
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
Read RY/BY#
BP
T
T
SCE, SE
or T
BE
Read same
word
No
Is DQ =
7
Is
No
true data
Program/Erase
Completed
RY/BY# = 1
Yes
Yes
No
Does DQ
match
Program/Erase
Completed
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1380 F17.1
Figure 23:Wait Options
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
30
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XX98H
Address: 55H
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Read CFI data
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read CFI data
Read Sec ID
Read Software ID
X can be V or V , but no other value
IL IH
1380 F21.0
Figure 24:Software ID/CFI Entry Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
31
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V , but no other value
IL IH
1380 F18.0
Figure 25:Software ID/CFI Exit Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
32
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
X can be V or V , but no other value
IL IH
1380 F19.0
Figure 26:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
33
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Product Ordering Information
SST 39 VF 1601C
-
70
-
4I
-
EKE
-
XX XX XXXXX
-
XX
-
XX
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Q = 48 balls (66 possible positions)
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
MA = WFBGA (4mm x 6mm, 0.5mm
pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compli-
ant”.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
34
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Valid Combinations for SST39VF1601C
SST39VF1601C-70-4C-EKE
SST39VF1601C-70-4I-EKE
SST39VF1601C-70-4C-B3KE SST39VF1601C-70-4C-MAQE
SST39VF1601C-70-4I-B3KE
SST39VF1601C-70-4I-MAQE
Valid Combinations for SST39VF1602C
SST39VF1602C-70-4C-EKE
SST39VF1602C-70-4I-EKE
SST39VF1602C-70-4C-B3KE
SST39VF1602C-70-4I-B3KE
SST39VF1602C-70-4C-MAQE
SST39VF1602C-70-4I-MAQE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combi-
nations.
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
35
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Packaging Diagrams
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Figure 27:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
36
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
TOP VIEW
8.00 0.10
BOTTOM VIEW
5.60
0.45 0.05
0.80
(48X)
6
5
6
5
4
3
2
1
4.00
4
3
6.00 0.10
2
1
0.80
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 28:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
37
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
5.00
6.00
0.08
0.50
0.32 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.08
2.50
0.50
A
B
C
D
E
F
G
H
J
K
L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR
0.73 max.
0.636 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-MAQ-4x6-32mic-2.0
Figure 29:48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 6mm x 8mm
SST Package Code: MAQ
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
38
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
A Microchip Technology Company
Data Sheet
Table 19:Revision History
Number
00
Description
Date
Apr 2008
Sep 2008
•
•
•
•
Initial release
01
Corrected typo in Hardware Block Protection on page 4.
Corrected typo in table title, Table 5 page 8
02
03
Jan 2009
Aug 2009
Changed 1V per 100 µs to 1V per 100 ms in Power Up Specifications
on page 12
•
•
Changed from Preliminary Specification to Data Sheet
Clarified RY/BY# pin timing by updating Features, Figures 7, 8, 9, 11,
12, 13, 18, 19, and 23, and Tables 3 and 18.
04
A
May 2010
May 2011
•
•
•
•
•
Added information for MAQE package
Updated SST address information on page 33.
Applied new document format
Released document under letter revision system
Updated spec number S71380 to DS-25018
ISBN:978-1-61341-181-0
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-
nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office(s) location and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS-25018A
05/11
39
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