SST39VF402C-70-4C-B3KE [MICROCHIP]
4 Mbit (x16) Multi-Purpose Flash Plus;
| 型号： | SST39VF402C-70-4C-B3KE |
| 厂家： | 
MICROCHIP |
| 描述： | 4 Mbit (x16) Multi-Purpose Flash Plus |
| 文件： | 总38页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 256K x16
CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high per-
formance CMOS SuperFlash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and manufacturability compared
with alternate approaches. SST39LF401C/402C write (Program or Erase) with a
3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply.
These devices conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 256K x16
• Security-ID Feature
– 128 bits; User: 128 words
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– 2.7-3.6V for SST39VF401C/402C
– 3.0-3.6V for SST39LF401C/402C
– 70 ns for SST39VF401C/402C
– 55 ns for SST39LF401C/402C
• Superior Reliability
• Fast Erase and Word-Program:
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Automatic Write Timing
– Internal VPP Generation
• Hardware Block-Protection/WP# Input Pin
• End-of-Write Detection
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• Sector-Erase Capability
– Uniform 2 KWord sectors
• CMOS I/O Compatibility
• Block-Erase Capability
• JEDEC Standard
– Flexible block architecture; one 8-, two 4-, one 16-, and
seven 32-KWord blocks
– Flash EEPROM Pinouts and command sets
• Chip-Erase Capability
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• All devices are RoHS compliant
www.microchip.com
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Product Description
The SST39VF401C/402C and SST39LF401C/402C devices are 256K x16 CMOS Multi-Purpose Flash
Plus (MPF+) manufactured with proprietary, high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. SST39LF401C/402C write (Program or Erase) with a 3.0-3.6V
power supply. SST39VF401C/402C write with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pinouts for x16 memories.
Featuring high performance Word-Program, the SST39VF401C/402C and SST39LF401C/402C
devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,
or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent
write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39VF401C/402C and SST39LF401C/402C devices are suited for applications that require
convenient and economical updating of program, configuration, or data memory. For all system appli-
cations, they significantly improve performance and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses less current to program and has a shorter erase
time, the total energy consumed during any Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while lowering the cost for program, data, and con-
figuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF401C/402C and SST39LF401C/402C
are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4
for pin assignments.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Block Diagrams
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
WP#
I/O Buffers and Data Latches
DQ - DQ
Control Logic
RESET#
RY/BY#
15
0
25053 B1.0
Figure 1: Functional Block Diagram
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Pin Assignment
A16
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
V
DQ15
SS
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RST#
NC
WP#
RY/BY#
NC
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A17
A7
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
1434 48-tsop EK P1.0
Figure 2: Pin Assignments for 48-Lead TSOP
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15 V
SS
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC
RY/BY#WP# NC
A7 A17 A6
NC DQ5 DQ12
V
DQ4
DD
NC DQ2 DQ10 DQ11 DQ3
A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E F G H
25053 48-tfbga B3K P2.0
Figure 3: Pin Assignments for 48-Ball TFBGA
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
4
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
TOP VIEW (balls facing down)
6
A2
A1
A0
A4
A3
A6 A17 NC NC WE# RST# A9 A11
A7 WP# RY/BY# A10 A13 A14
5
4
3
2
1
A5 NC
A8 A12 A15
DQ4 DQ11 A16
CE# DQ8 DQ10
V
OE# DQ9 NC
NC DQ5 DQ6 DQ7
SS
DQ0 DQ1 DQ2 DQ3
V
DQ12 DQ13 DQ14 DQ15 V
DD SS
A B C D E F G H J K L
25053 48-wfbga MAQ P3.0
Figure 4: Pin Assignments for 48-Ball WFBGA
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
CE#
OE#
WE#
VDD
Reset
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
Chip Enable
Output Enable
Write Enable
Power Supply
To control the Write operations.
To provide power supply voltage: 2.7-3.6V for SST39VF401C/402C or 3.0-3.6V
for SST39LF401C/402C
VSS
Ground
NC
No Connection
Ready/Busy#
Unconnected pins.
RY/BY#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.2 25053
1. AMS = Most significant address
AMS = A17
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Table 2: Top / Bottom Boot Block Address
Bottom Boot Block Address
SST39VF401C/SST39LF401C
Top Boot Block Address
SST39VF402C/SST39LF402C
Size
Size
#
Address Range
(KWord)
#
Address Range
(KWord)
18
17
16
15
14
13
12
11
10
9
8
3E000H-3FFFFH
3D000H-3DFFFH
3C000H-3CFFFH
38000H-3BFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
10
9
8
7
6
5
4
3
2
1
0
32
32
32
32
32
32
32
16
4
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
04000H-07FFFH
03000H-03FFFH
02000H-02FFFH
00000H-01FFFH
4
4
16
32
32
32
32
32
32
32
4
8
8
T2.25053
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
6
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF401C/402C and SST39LF401C/402C also have the Auto Low Power mode which puts
the device in a near standby mode after data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 5 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device
exits the Auto Low Power mode with any address transition or control signal transition used to initiate
another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power
mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF401C/402C and SST39LF401C/402C is controlled by CE# and OE#,
both have to be low for the system to obtain data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).
Word-Program Operation
The SST39VF401C/402C and SST39LF401C/402C are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be fully erased. The Program operation is accom-
plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF401C/402C and SST39LF401C/402C offer both Sector-Erase and
Block-Erase mode.
The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—seven 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.
See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (50H) and sector address
(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector
or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle
Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#
should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF401C/402C and SST39LF401C/402C provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF401C/402C and SST39LF401C/402C provide two software means to detect the comple-
tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detec-
tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera-
tion.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
8
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-
put, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data# Polling (DQ7)
When the SST39VF401C/402C and SST39LF401C/402C are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately follow-
ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on
the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal
Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)
pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for
a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.
Table 3: Write Operation Status
Status
DQ7
DQ7#
0
DQ6
Toggle
Toggle
1
DQ2
No Toggle
Toggle
RY/BY#
Normal Operation
Standard Program
Standard Erase
0
0
1
Erase-Suspend
Mode
Read from Erase-Sus-
pended Sector/Block
1
Toggle
Read from Non-Erase-
Suspended Sector/Block
Data
Data
Data
N/A
1
0
Program
DQ7#
Toggle
T3.0 25053
Note: DQ7 and DQ2 require a valid address when reading status information.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
9
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Data Protection
The SST39VF401C/402C and SST39LF401C/402C provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF402C/SST39LF402C support top hardware block protection, which protects the top 8
KWord block of the device. The SST39VF401C/SST39LF401C support bottom hardware block protec-
tion, which protects the bottom 8KWord block of the device. The Boot Block address ranges are
described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.
If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,
enabling Program and Erase operations on that block.
Table 4: Boot Block Address Ranges
Product
Address Range
00000H - 01FFFH
3E000H - 3FFFFH
Bottom Boot Block
SST39VF401C/SST39LF401C
Top Boot Block
SST39VF402C/SST39LF402C
T4.0 25053
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place (see Figure 18).
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF401C/402C and SST39LF401C/402C provide the JEDEC approved Software Data Pro-
tection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the
Program operation, providing optimal protection from inadvertent Write operations, e.g., during the
system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.
These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
the specific software command codes. During SDP command sequence, invalid commands will abort
the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value,
during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF401C/402C and SST39LF401C/402C also contain the CFI information to describe the
characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte
sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in
the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the
Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI
Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system
must write the CFI Exit command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF401C / SST39VF402C /
SST39LF401C / SST39LF402C, and manufacturer as Microchip. This mode may be accessed soft-
ware operations. Users may use the Software Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for
software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the
Software ID Entry command sequence flowchart.
Table 5: Product Identification
Address
Data
Manufacturer’s ID
0000H
BFH
Device ID
SST39VF401C/SST39LF401C
SST39VF402C/SST39LF402C
0001H
0001H
2321H
2322H
T5.2 25053
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig-
ure 25 for flowcharts.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
11
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Security ID
The SST39VF401C/402C and SST39LF401C/402C devices offer a 136 Word Security ID space. The
Secure ID space is divided into two segments—one factory programmed segment and one user pro-
grammed segment. The first segment is programmed and locked at the factory with a random 128-bit
number. The user segment, with a 128 word space, is left un-programmed for the customer to program
as desired.
To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com-
mand should be executed. Refer to Table 7 for more details.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
12
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Operations
Table 6: Operation Modes Selection
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector or block address, XXH for Chip-
Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 7
T6.0 25053
1. X can be VIL or VIH, but no other value.
Table 7: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
3rd Bus
4th Bus
5th Bus
Write Cycle Write Cycle
6th Bus
Write Cycle Write Cycle Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
Word-Program
Sector-Erase
Block-Erase
555H
555H
555H
555H
AAH 2AAH 55H 555H A0H WA3
Data
4
4
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX
50H
30H
Chip-Erase
AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Erase-Suspend
Erase-Resume
Query Sec ID5
XXXH B0H
XXXH 30H
555H
555H
AAH 2AAH 55H 555H 88H
AAH 2AAH 55H 555H A5H WA6
User Security ID
Word-Program
Data
User Security ID
Program Lock-
Out
555H
555H
AAH 2AAH 55H 555H 85H XXH6 0000
H
Software ID
Entry7,8
AAH 2AAH 55H 555H 90H
CFI Query Entry
555H
55H
AAH 2AAH 55H 555H 98H
98H
CFI Query Entry
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
555H
AAH 2AAH 55H 555H F0H
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
XXH
F0H
T7.6 25053
1. Address format A10-A0 (Hex). Addresses A11-A17 can be VIL or VIH, but no other value, for Command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address; AMS = A17
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
13
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
Microchip ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; Microchip Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF401C/SST39LF401C Device ID = 233BH, is read with A0 = 1, SST39VF402C/SST39LF402C Device ID =
233AH, is read with A0 = 1,
AMS = Most significant address; AMS = A17
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000008H-000087H.
Table 8: CFI Query Identification String1
Address
10H
Data
Data
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
11H
12H
13H
Primary OEM command set
14H
15H
Address for Primary Extended Table
16H
17H
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T8.1 25053
1. Refer to CFI publication 100 for more details.
Table 9: System Interface Information
Address
Data
Data
1BH
0027H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H
0000H
0003H
0000H
0004H
0005H
0001H
0000H
0001H
0001H
VPP min. (00H = no VPP pin)
VPP max. (00H = no VPP pin)
Typical time out for Word-Program 2N µs (23 = 8 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T9.3 25053
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
14
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Table 10: Device Geometry Information
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
Data
Data
0013H
0001H
0000H
0000H
0000H
0005H
0000H
0000H
0040H
0000H
0001H
0000H
0020H
0000H
0000H
0000H
0080H
0000H
0007H
0000H
0000H
0001H
Device size = 2N Bytes
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Erase Block Region 1 Information (Refer to the CFI specification or CFI publication
100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
T10.0 25053
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
15
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 11: Operating Range
Range
Ambient Temp
VDD
Commercial
0°C to +70°C
2.7-3.6V for SST39VF401C/402C or
3.0-3.6V for SST39LF401C/402C
Industrial
-40°C to +85°C
2.7-3.6V for SST39VF401C/402C or
3.0-3.6V for SST39LF401C/402C
T11.0 25053
Table 12: AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T12.1 25053
1. See Figures 20 and 21
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
16
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100
ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware
reset is required. The recommended VDD power-up to RESET# high time should be greater than 100
µs to ensure a proper reset.
1 00 µs
T
PU-READ
V
min
V
DD
DD
0V
V
IH
RESET#
T
5 0ns
RHR
CE#
25053 F24.0
Figure 5: Power-Up Diagram
Table 13: DC Operating Characteristics VDD = 3.0-3.6V for SST39LF401C/402C and 2.7-
3.6V for SST39VF401C/402C1
Limits
Symbol Parameter
Min
Max
Units Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
DD=VDD Max
IDD
Power Supply Current
V
Read3
18
30
20
mA
mA
µA
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
Program and Erase
Standby VDD Current
ISB
CE#=VIHC, VDD=VDD Max
RST#=VDD 0.3, WP#=VDD 0.3,
WE#=VDD 0.3
IALP
Auto Low Power
20
µA
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
WP#=GND to VDD or RST#=GND to VDD
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD VDD+0.3
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS) VDD-0.3 VDD+0.3
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
0.2
V
IOL=100 µA, VDD=VDD Min
VDD-0.2
V
IOH=-100 µA, VDD=VDD Min
T13.8 25053
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 20
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
17
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Table 14: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T14.0 25053
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 15: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T15.0 25053
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 16: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T16.2 25053
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
18
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
AC Characteristics
Table 17: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF401C/402C and
2.7-3.6V for SST39VF401C/402C
SST39VF401C/402C
SST39LF401C/402C
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
55
Chip Enable Access Time
Address Access Time
70
70
35
55
55
30
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
0
0
ns
ns
1
TCHZ
TOHZ
20
20
15
15
ns
1
ns
1
TOH
0
0
ns
1
TRP
500
50
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
20
µs
T17.3 25053
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
Table 18: Program/Erase Cycle Timing Parameters
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
10
TAS
0
30
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
25
50
90
0
ns
TSE
ms
ms
ms
ns
TBE
Block-Erase
TSCE
Chip-Erase
1,2
TBY
RY/BY# Delay Time
Bus Recovery Time
1
TBR
µs
T18.1 25053
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
19
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
T
OH
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
25053 F03.0
Note: AMS = Most significant address
AMS = A17
Figure 6: Read Cycle Timing Diagram
T
BP
555
2AA
555
ADDR
ADDRESSES
T
AH
T
WP
WE#
T
T
WPH
AS
OE#
T
CH
CE#
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
25053 F25.0
Note: WP# must be held in proper logic state (VIL
or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 7: WE# Controlled Program Cycle Timing Diagram
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
20
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESSES
T
AH
T
CP
CE#
T
T
CPH
AS
OE#
T
CH
WE#
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
25053 F26.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after
the command sequence.
X can be VIL or VIH, but no other value.
Figure 8: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
17-0
T
CE
CE#
T
T
OES
OEH
OE#
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
25053 F27.0
Figure 9: Data# Polling Timing Diagram
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
21
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
OEH
T
OES
T
OE
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
25053 F07.0
Note: AMS = Most significant address
AMS = A17
Figure 10:Toggle Bits Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESSES
CE#
OE#
WE#
T
OEH
T
T
BR
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX10
XX80
VALID
25053 F31.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 11:WE# Controlled Chip-Erase Timing Diagram
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
22
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
BE
555
2AA
BA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX30
XX80
VALID
25053 F32.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 12:WE# Controlled Block-Erase Timing Diagram
T
SIX-BYTE CODE FOR SECTOR-ERASE
555 555 2AA
SE
555
2AA
SA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX50
XX80
VALID
25053 F28.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
SAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 13:WE# Controlled Sector-Erase Timing Diagram
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
23
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Three-Byte Sequence for Software ID Entry
ADDRESS
CE#
555
2AA
555
0000
0001
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX90
SW2
Device ID
DQ
00BF
15-0
25053 F11.0
Note: Device ID = 233BH for SST39VF401C/SST39LF401C and 233AH for SST39VF401C/SST39LF401C
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 14:Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS
CE#
555
2AA
555
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
XXAA
SW0
XX55
SW1
XX98
SW2
15-0
25053 F12.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 15:CFI Query Entry and Read
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
24
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESS
XXAA
XX55
XXF0
DQ
15-0
T
IDA
CE#
OE#
WE#
T
WP
T
WHP
SW0
SW1
SW2
25053 F13.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 16:Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
555
2AA
555
MS-0
CE#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX88
SW2
DQ
15-0
25053 F20.0
Note: AMS = Most significant address
AMS = A17
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 17:Sec ID Entry
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
RY/BY#
0V
T
RP
RST#
T
RHR
CE#/OE#
25053 F29.0
Figure 18:RST# Timing Diagram (When no internal operation is in progress)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
25053 F30.0
Figure 19:RST# Timing Diagram (During Program or Erase operation)
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
25053 F14.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Measure-
ment reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and
fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 20:AC Input/Output Reference Waveforms
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
TO TESTER
TO DUT
CL
25053 F15.0
Figure 21:A Test Load Example
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
25053 F16.0
Note: X can VIL or VIH, but no other value.
Figure 22:Word-Program Algorithm
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Toggle Bit
Data# Polling
RY/BY#
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
Read RY/BY#
BP
T
T
SCE, SE
or T
BE
Read same
word
No
Is DQ =
7
Is
No
true data
Program/Erase
Completed
RY/BY# = 1
Yes
Yes
No
Does DQ
match
Program/Erase
Completed
6
Program/Erase
Completed
Yes
Program/Erase
Completed
25053 F17.0
Figure 23:Wait Options
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Software Product ID
Entry
Command Sequence
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XX98H
Address: 55H
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Read CFI data
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read CFI data
Read Sec ID
Read Software ID
25053 F21.0
Note: X can VIL or VIH, but no other value.
Figure 24:Software ID/CFI Entry Command Flowcharts
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
25053 F18.0
Note: X can be VIL or VIH, but no other value.
Figure 25:Software ID/CFI Exit Command Flowcharts
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
25053 F19.0
Note: X can be VIL or VIH, but no other value.
Figure 26:Erase Command Sequence
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Product Ordering Information
SST 39 VF 401C
XX XX XXXX
-
70
XX
-
4C
-
EKE
-
-
-
XX
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Q = 48 balls (66 possible positions)
PackageType
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
MA = WFBGA (4mm x 6mm, 0.5mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
55 = 55 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
40 = 4 Mbit
Voltage
V = 2.7-3.6V
L = 3.0-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
non-Pb solder devices are “RoHS Compliant”.
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Valid Combinations for SST39VF401C
SST39VF401C-70-4C-EKE
SST39VF401C-70-4C-B3KE
SST39VF401C-70-4C-MAQE
SST39VF401C-70-4I-MAQE
SST39VF401C-70-4I-EKE
SST39VF401C-70-4I-B3KE
Valid Combinations for SST39VF402C
SST39VF402C-70-4C-EKE
SST39VF402C-70-4C-B3KE
SST39VF402C-70-4C-MAQE
SST39VF402C-70-4I-MAQE
SST39VF402C-70-4I-EKE
SST39VF402C-70-4I-B3KE
Valid Combinations for SST39LF401C
SST39LF401C-55-4C-EKE
SST39LF401C-55-4C-B3KE
SST39LF401C-55-4C-MAQE
SST39LF402C-55-4C-MAQE
Valid Combinations for SST39LF402C
SST39LF402C-55-4C-EKE
SST39LF402C-55-4C-B3KE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your Micro-
chip sales representative to confirm availability of valid combinations and to determine availability of new
combinations.
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Packaging Diagrams
48-Lead Thin Small Outline Package (EKE/F) - [TSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48-tsop-EK-8
Note:
1. Complies with JE
DEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Microchip Technology Drawing C04-14036A Sheet 1 of 1
Figure 27:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
Package Code: EK
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
48-Lead Thin Fine-Pitch Ball Grid Array (B3KE/F) - 6x8 mm Body [TFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48-tfbga-B3K-6x8-450mic-5
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
Microchip Technology Drawing C04-14035A Sheet 1 of 1
Figure 28:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
Package Code: B3K
©2014 Silicon Storage Technology, Inc.
DS20005053B
04/14
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
48-Lead Very, Very Thin Find-Pitch Ball Grid Array (MAQE/F) - 4x6 mm Body [WFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48-wfbga-MAQ-4x6-32mic-2.0
Note:
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
Microchip Technology Drawing C04-14039A Sheet 1 of 1
Figure 29:48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm
Package Code: MAQ
©2014 Silicon Storage Technology, Inc.
DS20005053B
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
Table 19: Revision History
Number
Description
Date
A
B
Oct 2011
Apr 2014
•
•
•
•
Initial release
Updated product description on page 1 and 2 to correct a typo
Clarified the voltage information on page 1.
Updated package drawing to the new format in “Packaging Diagrams” on
page 35
ISBN:978-1-63276-111-8
© 2014 Microchip Technology Inc.
SST, Silicon Storage Technology, the SST logo, SuperFlash, and MTP are registered trademarks of Microchip Technology, Inc.
MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Microchip Technology, Inc. All other trademarks and registered trade-
marks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
Microchip makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions
of Sale.
For sales office locations and information, please see www.microchip.com.
www.microchip.com
©2014 Silicon Storage Technology, Inc.
DS20005053B
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