SST49LF008A-33-4C-WHE [MICROCHIP]
1M X 8 FLASH 3V PROM, 120 ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, MO-142BA, TSOP1-32;
| 型号： | SST49LF008A-33-4C-WHE |
| 厂家： | 
MICROCHIP |
| 描述： | 1M X 8 FLASH 3V PROM, 120 ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, MO-142BA, TSOP1-32 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总45页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
The SST49LF008A flash memory devices are designed to be read-compatible
with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application.
These devices provide protection for the storage and update of code and data in
addition to adding system design flexibility through five general purpose inputs.
Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH)
Interface mode for in-system programming and Parallel Programming (PP) mode
for fast factory programming of PC-BIOS applications.
Features
• Firmware Hub for Intel 8xx Chipsets
• Two Operational Modes
– Firmware Hub Interface (FWH) Mode for
• 8 Mbit SuperFlash memory array for code/data
In-System operation
storage
– Parallel Programming (PP) Mode for fast
production programming
– 1024K x8
• Firmware Hub Hardware Interface Mode
• Flexible Erase Capability
– 5-signal communication interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Writedetection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance:100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Parallel Programming (PP) Mode
• Low Power Consumption
– 11-pin multiplexed address and
8-pin data I/O interface
– Supports fast In-System or PROM programming for
manufacturing
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
• CMOS and PCI I/O Compatibility
• Packages Available
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 40-lead TSOP (10mm x 20mm)
– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Product Description
The SST49LF008A flash memory devices are designed to be read-compatible with the Intel® 82802
Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage
and update of code and data in addition to adding system design flexibility through five general pur-
pose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface
mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of
PC-BIOS applications.
The SST49LF008A flash memory devices are manufactured with SST’s proprietary, high performance
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate approaches. The SST49LF008A devices signifi-
cantly improve performance and reliability, while lowering power consumption.
The SST49LF008A devices write (Program or Erase) with a single 3.0-3.6V power supply. They use
less energy during Erase and Program than alternative flash memory technologies. The total energy
consumed is a function of the applied voltage, current and time of application. Since for any given volt-
age range, the SuperFlash technology uses less current to program and has a shorter Erase time, the
total energy consumed during any Erase or Program operation is less than alternative flash memory
technologies. The SST49LF008A products provide a maximum Byte-Program time of 20 µsec. The
entire memory can be erased and programmed byte-by-byte typically in 15 seconds when using status
detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation.
The SuperFlash technology provides fixed Erase and Program times independent of the number of
Erase/Program cycles performed. Therefore the system software or hardware does not have to be cal-
ibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alterna-
tive flash memory technologies, whose Erase and Program time increase with accumulated Erase/
Program cycles.
To protect against inadvertent write, the SST49LF008A devices employ hardware and software data
(SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is
rated at greater than 100 years.
To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead
TSOP package. In addition, the SST49LF008A is offered in 32-lead PLCC and 40-lead TSOP pack-
ages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions.
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
2
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Functional Block Diagram
TBL#
WP#
INIT#
SuperFlash
Memory
X-Decoder
FWH[3:0]
CLK
FWH
Interface
Address Buffers Latches
Control Logic
FWH4
Y-Decoder
ID[3:0]
FGPI[4:0]
R/C#
I/O Buffers and Data Latches
A[10:0]
Programmer
Interface
DQ[7:0]
OE#
WE#
IC
RST#
1161 B1.2
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
3
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Pin Assignments
NC
NC
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE# (INIT#)
WE# (FWH4)
V
(V
)
DD
DD
V
(V
SS SS
)
DQ7 (RES)
DQ6 (RES)
DQ5 (RES)
DQ4 (RES)
DQ3 (FWH3)
IC (IC)
A10 (FGPI4)
R/C# (CLK)
Standard Pinout
Top View
V
(V
DD DD
)
NC
9
V
(V
)
SS
SS
Die Up
RST# (RST#)
A9 (FGPI3)
A8 (FGPI2)
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
10
11
12
13
14
15
16
DQ2 (FWH2)
DQ1 (FWH1)
DQ0 (FWH0)
A0 (ID0)
A1 (ID1)
A2 (ID2)
A3 (ID3)
A4 (TBL#)
1161 32-tsop P1.0
( ) Designates FWH Mode
Figure 2: Pin Assignments for 32-lead TSOP (8mm x 14mm)
4
3
2
1
32 31 30
29
5
A7(FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
IC (IC)
(V
6
28
27
26
25
24
23
22
21
V
)
SS SS
7
NC
8
NC
32-lead PLCC
Top View
9
V
(V )
DD DD
10
11
12
13
A2 (ID2)
OE# (INIT#)
WE# (FWH4)
NC
A1 (ID1)
A0 (ID0)
DQ0 (FWH0)
DQ7 (RES)
14 15 16 17 18 19 20
1161 32-plcc P2.3
( ) Designates FWH Mode
Figure 3: Pin Assignments for 32-lead PLCC
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
4
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
V
NC (NC)
IC (IC)
NC (NC)
NC (NC)
NC (NC)
SS
DD
(FWH4) WE#
(INIT#) OE#
(NC) NC
(RES) DQ7
(RES) DQ6
(RES) DQ5
(RES) DQ4
(NC) NC
NC (NC)
A10 (FGPI4)
NC (NC)
R/C# (CLK)
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
V
DD
NC (NC)
RST# (RST#)
NC (NC)
V
V
SS
SS
Die Up
(FWH3) DQ3
(FWH2) DQ2
(FWH1) DQ1
(FWH0) DQ0
(ID0) A0
(ID1) A1
(ID2) A2
(ID3) A3
NC (NC)
A9 (FGPI3)
A8 (FGPI2)
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
( ) Designates FWH Mode
1232 40-tsop P1.0
Figure 4: Pin Assignments for 40-lead TSOP
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
5
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Table 1: Pin Description
Interface
Symbol Pin Name
10-A0 Address
Type1 PP FWH Functions
A
I
X
Inputs for low-order addresses during Read and Write opera-
tions. Addresses are internally latched during a Write cycle. For
the programming interface, these addresses are latched by R/
C# and share the same pins as the high-order address inputs.
DQ7-DQ0 Data
I/O
X
To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The
outputs are in tri-state when OE# is high.
OE#
WE#
IC
Output Enable
I
I
I
X
X
X
To gate the data output buffers
To control the Write operations
Write Enable
Interface
Configuration
Pin
X
This pin determines which interface is operational. When held
high, programmer mode is enabled and when held low, FWH
mode is enabled. This pin must be setup at power-up or before
return from reset and not change during device operation. This pin
is internally pulled- down with a resistor between 20-100 K
INIT#
Initialize
I
I
X
X
This is the second reset pin for in-system use. This pin is inter-
nally combined with the RST# pin; If this pin or RST# pin is
driven low, identical operation is exhibited.
ID[3:0]
Identification
Inputs
These four pins are part of the mechanism that allows multiple
parts to be attached to the same bus. The strapping of these
pins is used to identify the component.The boot device must
have ID[3:0]=0000 and it is recommended that all subsequent
devices should use sequential up-count strapping. These pins
are internally pulled-down with a resistor between 20-100 K
FGPI[4:0] General Pur-
pose Inputs
I
I
X
X
These individual inputs can be used for additional board flexibil-
ity. The state of these pins can be read through GPI_REG regis-
ter. These inputs should be at their desired state before the start
of the PCI clock cycle during which the read is attempted, and
should remain in place until the end of the Read cycle. Unused
GPI pins must not be floated.
TBL#
Top Block Lock
When low, prevents programming to the Boot Block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
FWH[3:0] FWH I/Os
I/O
X
X
X
X
X
I/O Communications
CLK
Clock
I
I
I
I
To provide a clock input to the control unit
Input Communications
FWH4
RST#
WP#
FWH Input
Reset
X
X
To reset the operation of the device
Write Protect
When low, prevents programming to all but the highest address-
able blocks. When WP# is high it disables hardware write protec-
tion for these blocks. This pin cannot be left unconnected.
R/C#
Row/Column
Select
I
Select For the Programming interface, this pin determines whether
the address pins are pointing to the row addresses, or to the column
addresses.
RES
VDD
VSS
NC
Reserved
X
X
X
X
These pins must be left unconnected.
Power Supply
Ground
PWR
PWR
I
X
X
X
To provide power supply (3.0-3.6V)
Circuit ground (OV reference) All VSS pins must be grounded.
No Connection
Unconnected pins
T1.4 25085
1. I = Input, O = Output
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
6
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Device Memory Map
0FFFFFH
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
TBL#
Boot Block
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
WP# for
Block 0 14
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
4 KByte Sector 15
Block 0
(64 KByte)
4 KByte Sector 2
4 KByte Sector 1
4 KByte Sector 0
002000H
001000H
000000H
1161 F08.0
Figure 5: Device Memory Map for SST49LF008A
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
7
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible
between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low fre-
quency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you
use a socket for programming purposes add an additional 1-10 µF next to each socket.
The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must
remain stable at VIH for the entire duration of the Erase and Program operations for non-Boot Block
sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the
entire duration of the Erase and Program operations.
Product Identification
The product identification mode identifies the device as the SST49LF008A and manufacturer as SST.
Table 2: Product Identification
JEDEC ID
Address
Byte
Data
Location
Manufacturer’s ID
Device ID
0000H
BFH
FFBC0000H
SST49LF008A
0001H
5AH
FFBC0001H
T2.7 25085
Mode Selection
The SST49LF008A flash memory devices can operate in two distinct interface modes: the Firmware
Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration
pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP
mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be con-
figured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In
FWH mode, the device is configured to interface with its host using Intel’s Firmware Hub proprietary
protocol. Communication between Host and the SST49LF008A occurs via the 4-bit I/O communication
signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11-bit address and
an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by
control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the
row addresses are mapped to the lower internal addresses. See the Device Memory Map in Figure 5
for address assignments.
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
8
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Firmware Hub (FWH) Mode
Device Operation
The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations
of the SST49LF008A. Operations such as Memory Read and Memory Write uses Intel FWH propriety
protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-
Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only avail-
able in PP Mode.
The device enters standby mode when FWH4 is high and no internal operation is in progress. The
device is in ready mode when FWH4 is low and no activity is on the FWH bus.
Firmware Hub Interface Cycles
Addresses and data are transferred to and from the SST49LF008A by a series of “fields,” where each
field contains 4 bits of data. SST49LF008A supports only single-byte Read and Write, and all fields are
one clock cycle in length. Field sequences and contents are strictly defined for Read and Write opera-
tions. Addresses in this section refer to addresses as seen from the SST49LF008A’s “point of view,”
some calculation will be required to translate these to the actual locations in the memory map (and
vice versa) if multiple memory devices are used on the bus. Tables 3 and 4 list the field sequences for
Read and Write cycles.
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
9
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Table 3: FWH Read Cycle
Clock
Cycle
Field
Name
Field Contents FWH[3:0]
FWH[3:0]1
Direction Comments
1
START
1101
IN
FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transitions high) should be recog-
nized. The START field contents indicate a FWH memory
Read cycle.
2
IDSEL
IMADDR
IMSIZE
TAR0
0000 to 1111
YYYY
IN
IN
IN
IN
Indicates which FWH device should respond. If the to IDSEL (ID
select) field matches the value ID[3:0], then that particular device will
respond to the whole bus cycle.
3-9
10
11
These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are trans-
ferred most-significant nibble first.
0000 (1 byte)
1111
A field of this size indicates how many bytes will be or trans-
ferred during multi-byte operations. The SST49LF008A will only
support single-byte operation. IMSIZE=0000b
In this clock cycle, the master (Intel ICH) has driven the bus
then Float then float to all ‘1’s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround cycle.”
12
13
TAR1
1111 (float)
Float
The SST49LF008A takes control of the bus during this cycle.
then OUT During the next clock cycle, it will be driving “sync data.”
RSYNC 0000 (READY)
OUT
During this clock cycle, the FWH will generate a “ready-sync”
(RSYNC) indicating that the least-significant nibble of the least-
significant byte will be available during the next clock cycle.
14
15
16
DATA
DATA
TAR0
YYYY
YYYY
1111
OUT
OUT
OUT
YYYY is the least-significant nibble of the least-significant data byte.
YYYY is the most-significant nibble of the least-significant data byte.
In this clock cycle, the SST49LF008A has driven the bus to all
then Float ones and then floats the bus prior to the next clock cycle. This
is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then The master (Intel ICH) resumes control of the bus during this
IN
cycle.
T3.3 25085
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
FWH4
STR
IDS
IMADDR
IMS
TAR
RSYNC
DATA
TAR
FWH[3:0]
1161 F09.0
Figure 6: Single-Byte Read Waveforms
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
10
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Table 4: FWH Write Cycle
Clock
Cycle
Field
Name
Field Contents
FWH[3:0]1
FWH[3:0]
Direction
Comments
1
START
1110
IN
FWH4 must be active (low) for the part to respond. Only
the last start field (before FWH4 transitions high) should
be recognized. The START field contents indicate a FWH
memory Read cycle.
2
IDSEL
0000 to 1111
IN
Indicates which SST49LF008A device should respond.
If the IDSEL (ID select) field matches the value
ID[3:0], then that particular device will respond to the
whole bus cycle.
3-9
10
11
IMADDR
IMSIZE
DATA
YYYY
0000 (1 byte)
YYYY
IN
IN
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
This size field indicates how many bytes will be trans-
ferred during multi-byte operations. The FWH only
supports single-byte writes. IMSIZE=0000b
This field is the least-significant nibble of the data byte.
This data is either the data to be programmed into the
flash memory or any valid flash command.
12
13
DATA
TAR0
YYYY
1111
IN
This field is the most-significant nibble of the data byte.
IN then Float
In this clock cycle, the master (Intel ICH) has driven the
then float bus to all ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus “turn-
around cycle.”
14
TAR1
1111 (float)
Float then OUT The SST49LF008A takes control of the bus during this
cycle. During the next clock cycle it will be driving the
“sync” data.
15
16
RSYNC
TAR0
0000
1111
OUT
The SST49LF008A outputs the values 0000, indicating
that it has received data or a flash command.
OUT then Float In this clock cycle, the SST49LF008A has driven the bus
to all then float ‘1’s and then floats the bus prior to the
next clock cycle. This is the first part of the bus “turn-
around cycle.”
17
TAR1
1111 (float)
Float then IN The master (Intel ICH) resumes control of the bus during this
cycle.
T4.4 25085
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
FWH4
STR
IDS
IMADDR
IMS
DATA
TAR
RSYNC
TAR
FWH[3:0]
1161 F10.0
Figure 7: Write Waveforms
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
11
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Abort Mechanism
If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated
and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’
(ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the
data may be incorrectly altered.
Response To Invalid Fields
During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences.
The response to specific invalid fields or sequences is as follows:
Address out of range:
The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will
be decoded by SST49LF008A.
Address A22 has the special function of directing reads and writes to the flash core (A22=1) or to the
register space (A22=0).
Invalid IMSIZE field:
If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no
operation will be attempted. The SST49LF008A will not generate any kind of response in this situation.
Invalid-size fields for a Read/Write cycle are anything but 0000b.
Device Memory Hardware Write Protection
The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of
device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte)
at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remain-
ing sectors in the flash memory.
An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors.
When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot
Block Locking register. The WP# pin serves the same function for the remaining sectors of the device
memory. The TBL# and WP# pins write protection functions operate independently of one another.
Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or
Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase
operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.
TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot
Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Lock-
ing register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional
effect, even though the register may indicate that the block is no longer locked.
WP# is internally OR’ed with the Block Locking register. When WP# is low, the blocks are hardware
write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking regis-
ters. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even
though the register may indicate that the block is no longer locked.
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
12
8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function inter-
nally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initial-
ization.
During a Read operation, driving INIT# or RST# pins low deselects the device and places the output
drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration
of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase
operation. See Table 19, Reset Timing Parameters for more information. A device reset during an
active Program or Erase will abort the operation and memory contents may become invalid due to data
being altered or corrupted from an incomplete Erase or Program operation.
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is incorpo-
rated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the
system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to read the accessed location an additional two (2)
times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is
valid.
Data# Polling (DQ7)
When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7 will pro-
duce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. Proper status will not be given using Data# Polling if the address is in the invalid
range.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop.
Multiple Device Selection
The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID
strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as
0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.).
The SST49LF008A will compare the strapping values, if there is a mismatch, the device will ignore the
remainder of the cycle and go into standby mode. For further information regarding FWH device map-
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
ping and paging, please refer to the Intel 82801(ICH) I/O Controller Hub documentation. Since there is
no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recom-
mended.
Registers
There are three types of registers available on the SST49LF008A, the General Purpose Inputs regis-
ter, Block Locking registers and the JEDEC ID registers. These registers appear at their respective
address location in the 4 GByte system memory map. Unused register locations will read as 00H.
Attempts to read or write to any registers during internal Write operations will be ignored.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on
the SST49LF008A. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is
brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There
is no default value since this is a pass-through register. The GPI register for the boot device appears at
FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the
boot device. Register is not available for read when the device is in Erase/Program operation. See
Table 5 for the GPI_REG bits and function.
Table 5: General Purpose Inputs Register
Pin #
Bit
7:5
4
Function
32-PLCC
32-TSOP
40-TSOP
Reserved
-
-
-
FGPI[4]
30
6
7
Reads status of general
purpose input pin
3
2
1
0
FGPI[3]
Reads status of general
purpose input pin
3
4
5
6
11
12
13
14
15
16
17
18
FGPI[2]
Reads status of general
purpose input pin
FGPI[1]
Reads status of general
purpose input pin
FGPI[0]
Reads status of general
purpose input pin
T5.3 25085
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Data Sheet
Block Locking Registers
SST49LF008A provides software controlled lock protection through a set of Block Locking registers.
The Block Locking Registers are read/write registers and it is accessible through standard addressable
memory locations specified in Table 6. Unused register locations will read as 00H.
Table 6: Block Locking Registers for SST49LF008A1
Register
Block Size
64K
Protected Memory Address Range
0FFFFFH - 0F0000H
0EFFFFH - 0E0000H
0DFFFFH - 0D0000H
0CFFFFH - 0C0000H
0BFFFFH - 0B0000H
0AFFFFH - 0A0000H
09FFFFH - 090000H
08FFFFH - 080000H
07FFFFH - 070000H
06FFFFH - 060000H
05FFFFH - 050000H
04FFFFH - 040000H
03FFFFH - 030000H
02FFFFH - 020000H
01FFFFH -010000H
00FFFFH - 000000H
Memory Map Register Address
FFBF0002H
T_BLOCK_LK
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
T_MINUS08_LK
T_MINUS09_LK
T_MINUS10_LK
T_MINUS11_LK
T_MINUS12_LK
T_MINUS13_LK
T_MINUS14_LK
T_MINUS15_LK
64K
FFBE0002H
FFBD0002H
FFBC0002H
FFBB0002H
FFBA0002H
FFB90002H
64K
64K
64K
64K
64K
64K
FFB80002H
64K
FFB70002H
64K
FFB60002H
64K
FFB50002H
64K
FFB40002H
64K
FFB30002H
64K
FFB20002H
64K
FFB10002H
64K
FFB00002H
T6.4 25085
1. Default value at power up is 01H
Table 7: Block Locking Register Bits
Reserved Bit [7..2] Lock-Down Bit [1] Write-Lock Bit [0] Lock Status
000000
000000
000000
000000
0
0
1
1
0
1
0
1
Full Access
Write Locked (Default State at Power-Up)
Locked Open (Full Access Locked Down)
Write Locked Down
T7.3 25085
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8 Mbit Firmware Hub
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Data Sheet
Write Lock
The Write-Lock bit, bit 0, controls the lock state described in Table 7. The default Write status of all
blocks after power-up is write locked. When bit 0 of the Block Locking register is set, Program and
Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect
the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is
sampled at the beginning of the operation.
The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot
Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking regis-
ter does not indicate the state of the TBL# pin.
The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is
low, it overrides the software locking scheme. The Block Locking register does not indicate the state of
the WP# pin.
Lock Down
The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 7. When in the FWH
interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the
Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The
Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock
Down status of a particular block can be determined by reading the corresponding Lock-Down bit.
Once a block’s Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and
the block is locked down in its current state of write accessibility.
JEDEC ID Registers
The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte
system memory map, and will appear elsewhere if the device is not the boot device. Register is not
available for read when the device is in Erase/Program operation. Unused register location will read as
00H. Refer to the relevant application note for details. See Table 2 for the device ID code.
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Data Sheet
Parallel Programming Mode
Device Operation
Commands are used to initiate the memory operation functions of the device. The data portion of the
software command sequence is latched on the rising edge of WE#. During the software command
sequence the row address is latched on the falling edge of R/C# and the column address is latched on
the rising edge of R/C#.
Reset
Read
A VIL on RST# pin initiates a device reset.
The Read operation of the SST49LF008A device is controlled by OE#. OE# is the output control and is
used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further
details.
Byte-Program Operation
The SST49LF008A device is programmed on a byte-by-byte basis. Before programming, one must
ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-
Program operation is initiated by executing a four-byte command load sequence for Software Data
Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation,
the row address (A10-A0) is latched on the falling edge of R/C# and the column Address (A21-A11) is
latched on the rising edge of R/C#. The data bus is latched in the rising edge of WE#. The Program
operation, once initiated, will be completed, within 20 µs. See Figure 14 for Program operation timing
diagram, Figure 17 for timing waveforms, and Figure 25 for its flowchart. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the
host is free to perform additional tasks. Any commands written during the internal Program operation
will be ignored.
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Data Sheet
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated
by executing a six-byte command load sequence for Software Data Protection with Sector-Erase com-
mand (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit
methods. See Figure 18 for Sector-Erase timing waveforms. Any commands written during the Sector-
Erase operation will be ignored.
Block-Erase Operation
The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for
the SST49LF008A. The Block-Erase operation is initiated by executing a six-byte command load
sequence for Software Data Protection with Block-Erase command (50H) and block address. The
internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Figure 19 for timing waveforms. Any commands
written during the Block-Erase operation will be ignored.
Chip-Erase
The SST49LF008A device provides a Chip-Erase operation only in PP Mode, which allows the user to
erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command
sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal
Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the
only valid read is Toggle Bit or Data# Polling. See Table 9 for the command sequence, Figure 20 for
timing diagram, and Figure 28 for the flowchart. Any commands written during the Chip-Erase opera-
tion will be ignored.
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7 will pro-
duce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program
operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse.
See Figure 15 for Data# Polling timing diagram and Figure 26 for a flowchart. Proper status will not be
given using Data# Polling if the address is in the invalid range.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is
valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 16 for Toggle Bit tim-
ing diagram and Figure 26 for a flowchart.
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Table 8: Operation Modes Selection (PP Mode)
Mode
RST# OE# WE# DQ
VIL DOUT
Address
AIN
Read
VIH
VIH
Program
Erase
VIL DIN
VIL X1
AIN
VIH VIH
VIH VIH
Sector or Block address, XXH for Chip-
Erase
Reset
VIL
VIH
X
X
X
X
High Z
X
X
X
Write Inhibit
VIL
High Z/DOUT
High Z/DOUT
X
VIH
VIH
Product Identification
VIL
Manufacturer’s ID (BFH) A18-A1=VIL, A0=VIL
Device ID2
A18-A1=VIL, A0=VIH
VIH
T8.6 25085
1. X can be VIL or VIH, but no other value.
2. Device ID = 5AH for SST49LF008A
Data Protection
The SST49LF008A device provides both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadver-
tent writes during power-up or power-down.
Software Data Protection (SDP)
SST49LF008A provides the JEDEC approved Software Data Protection scheme for all data alteration
operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-
byte sequences. The three-byte load sequence is used to initiate the Program operation, providing
optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF008A device is
shipped with the Software Data Protection permanently enabled. See Table 9 for the specific software
command codes. During SDP command sequence, invalid commands will abort the device to Read
mode, within TRC.
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Data Sheet
Software Command Sequence
Table 9: Software Command Sequence
1st1
2nd1
3rd1
4th1
5th1
6th1
Command
Sequence
Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr2 Data Addr2 Data Addr2 Data Addr2 Data Addr2
Data Addr2 Data
Byte-Program
Sector-Erase
Block-Erase
Chip-Erase6
5555H AAH 2AAAH 55H 5555H A0H BA3 Data
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX
30H
50H
5
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit9
Software ID Exit9
XXH F0H
5555H AAH 2AAAH 55H 5555H F0H
T9.6 25085
1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to
complete a command sequence.
2. Address format A14-A0 (Hex), Addresses A21-A15 can be VIL or VIH, but no other value, for the Command sequence in
PP Mode.
3. BA = Program Byte address
4. SAX for Sector-Erase Address
5. BAX for Block-Erase Address
6. Chip-Erase is supported in PP Mode only
7. SST Manufacturer’s ID = BFH, is read with A0=0,
With A19-A1 = 0; 49LF008A Device ID = 5AH, is read with A0 = 1.
8. The device does not remain in Software Product ID mode if powered down.
9. Both Software ID Exit operations are equivalent.
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8 Mbit Firmware Hub
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Data Sheet
Electrical Specifications
The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as
defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 12 for the DC voltage
and current specifications. Refer to the tables on pages 24 through 29 for the AC timing specifications for
Clock, Read/Write, and Reset operations.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential1 . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA=25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Do not violate processor or chipset limitations on the INIT# pin.
2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI
outputs.
Table 10:Operating Range
Range
Ambient Temp
VDD
Commercial
0°C to +85°C
3.0-3.6V
T10.1 25085
Table 11:AC Conditions of Test1,2
Input Rise/Fall Time
Output Load
3ns
CL = 30 pF
T11.1 25085
1. See Figures 23 and 24
2. FWH interface signals use PCI load test conditions
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Data Sheet
DC Characteristics
Table 12:DC Operating Characteristics (All Interfaces)
Limits
Unit
s
Symbol Parameter
IDD Active VDD Current
Min
Max
Test Conditions1
LCLK (FWH mode) and Address Input (PP
mode)=VILT/VIHT at f=33 MHz (FWH mode) or 1/TRC
min (PP Mode)
All other inputs=VIL or VIH
Read
Write2
12
24
mA All outputs = open, VDD=VDD Max
mA See Note3
ISB
Standby VDD Current
(FWH Interface)
100
µA LCLK (FWH mode) and Address Input (PP
mode)=VILT/VIHT
at f=33 MHz (FWH mode) or 1/TRC min (PP Mode)
LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD
,
VDD=VDD Max, All other inputs 0.9 VDD or 0.1
VDD
4
IRY
Ready Mode VDD Cur-
rent
10
mA LCLK (FWH mode) and Address Input (PP
mode)=VILT/VIHT
(FWH Interface)
at f=33 MHz (FWH mode) or 1/TRC min (PP Mode)
LFRAME#=VIL, f=33 MHz, VDD=VDD Max
All other inputs 0.9 VDD or 0.1 VDD
II
Input Current for IC,
ID [3:0] pins
200
µA VIN=GND to VDD, VDD=VDD Max
ILI
Input Leakage Current
1
1
µA VIN=GND to VDD, VDD=VDD Max
µA VOUT=GND to VDD, VDD=VDD Max
ILO
Output Leakage Cur-
rent
5
VIHI
INIT# Input High Volt-
age
1.0
-0.5
-0.5
VDD+0.
5
V
V
V
V
V
V
VDD=VDD Max
5
VILI
VIL
INIT# Input Low Volt-
age
0.4
VDD=VDD Min
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.3
VDD
VDD=VDD Min
0.5
VDD
VDD+0.
5
VDD=VDD Max
VIH
VOL
VOH
0.1
VDD
IOL=1500µA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
0.9
VDD
T12.10 25085
1. Test conditions apply to PP mode.
2. IDD active while Erase or Program is in progress.
3. For PP Mode: OE# = WE# = VIH; For FWH mode: f = 1/TRC min, LFRAME# = VIH, CE# = VIL.
4. The device is in Ready Mode when no activity is on the FWH bus.
5. Do not violate processor or chipset specification regarding INIT# voltage.
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8 Mbit Firmware Hub
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Data Sheet
Table 13:Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T13.2 25085
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter
Table 14:Pin Impedance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
Pin Inductance
1
CIN
VIN = 0V
12 pF
2
LPIN
20 nH
T14.4 25085
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. Refer to PCI spec.
Table 15:Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
Years JEDEC Standard A103
1
TDR
1
ILTH
100 + IDD
mA
JEDEC Standard 78
T15.3 25085
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 16:Clock Timing Parameters
Symbol
TCYC
THIGH
TLOW
-
Parameter
Min
30
11
11
1
Max
Units
ns
CLK Cycle Time
CLK High Time
ns
CLK Low Time
ns
CLK Slew Rate (peak-to-peak)
RST# or INIT# Slew Rate
4
V/ns
mV/ns
-
50
T16.1 25085
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8 Mbit Firmware Hub
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Data Sheet
T
cyc
T
high
0.6 V
DD
T
low
0.5 V
DD
0.4 V
(minimum)
p-to-p
DD
0.4 V
DD
0.3 V
DD
0.2 V
DD
1161 F11.0
Figure 8: CLK Waveform
AC Characteristics (FWH Mode)
Table 17:Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol
TCYC
TSU
Parameter
Min
30
7
Max
Units
ns
Clock Cycle Time
Data Set Up Time to Clock Rising
Clock Rising to Data Hold Time
Clock Rising to Data Valid
Byte Programming Time
Sector-Erase Time
ns
TDH
0
ns
1
TVAL
2
11
20
ns
TBP
µs
TSE
25
ms
ms
ms
ns
TBE
Block-Erase Time
25
TSCE
TON
TOFF
Chip-Erase Time
100
Clock Rising to Active (Float to Active Delay)
Clock Rising to Inactive (Active to Float Delay)
2
28
ns
T17.3 25085
1. Minimum and maximum times have different loads. See PCI spec.
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8 Mbit Firmware Hub
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Data Sheet
Table 18:AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode)
Limits
Symbol Parameter
Min
Max
Units Test Conditions
IOH(AC) Switching Current High
-12 VDD
-17.1(VDD-VOUT
mA 0 < VOUT 0.3VDD
mA 0.3VDD < VOUT < 0.9VDD
0.7VDD < VOUT <VDD
)
Equation C1
-32 VDD
(Test Point)
mA VOUT=0.7VDD
IOL(AC) Switching Current Low
16 VDD
26.7 VOUT
Equation D1
mA VDD >VOUT 0.6VDD
mA 0.6VDD > VOUT > 0.1VDD
0.18VDD > VOUT > 0
(Test Point)
38 VDD
mA VOUT=0.18VDD
mA -3 < VIN -1
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-25+(VIN+1)/0.015
ICH
25+(VIN-VDD-1)/0.015
mA VDD+4 > VIN VDD+1
V/ns 0.2VDD-0.6VDD load
slewr2
slewf2
1
1
4
4
V/ns 0.6VDD-0.2VDD load
T18.3 25085
1. See PCI spec.
2. PCI specification output load is used.
Table 19:Reset Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol
TPRST
TKRST
TRSTP
TRSTF
Parameter
Min
1
Max
Units
ms
µs
VDD stable to Reset Low
Clock Stable to Reset Low
RST# Pulse Width
100
100
ns
RST# Low to Output Float
RST# High to FWH4 Low
RST# Low to reset during Sector-/Block-Erase or Program
48
10
ns
1
TRST
1
µs
TRSTE
µs
T19.5 25085
1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
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8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
V
DD
T
PRST
T
CLK
T
KRST
RSTP
RST#/INIT#
Sector-/Block-Erase
or Program operation
aborted
T
RSTE
T
T
RSTF
RST
FWH[3:0]
FWH4
1161 F12.0
Figure 9: Reset Timing Diagram
V
V
TH
TL
CLK
V
TEST
T
VAL
FWH [3:0]
(Valid Output Data)
FWH [3:0]
(Float Output Data)
T
ON
T
OFF
1161 F13.0
Figure 10:Output Timing Parameters
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8 Mbit Firmware Hub
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Data Sheet
V
V
TH
TL
V
CLK
TEST
T
SU
T
DH
FWH [3:0]
(Valid Input Data)
Inputs
Valid
V
MAX
1161 F14.0
Figure 11:Input Timing Parameters
Table 20:Interface Measurement Condition Parameters
Symbol
Value
0.6 VDD
0.2 VDD
0.4 VDD
0.4 VDD
1 V/ns
Units
1
VTH
V
V
V
V
1
VTL
VTEST
1
VMAX
Input Signal Edge Rate
T20.3 25085
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met
with no more overdrive than this.
VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may
use different voltage values, but must correlate results back to these parameters.
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8 Mbit Firmware Hub
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Data Sheet
AC Characteristics (PP Mode)
Table 21:Read Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TRC
Parameter
Min
270
1
Max
Units
ns
Read Cycle Time
TRST
TAS
RST# High to Row Address Setup
R/C# Address Set-up Time
R/C# Address Hold Time
Address Access Time
µs
45
ns
TAH
45
ns
TAA
120
60
ns
TOE
Output Enable Access Time
OE# Low to Active Output
OE# High to High-Z Output
Output Hold from Address Change
ns
TOLZ
TOHZ
TOH
0
0
ns
35
ns
ns
T21.2 25085
Table 22:Program/Erase Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TRST
TAS
Parameter
Min
1
Max
Units
µs
RST# High to Row Address Setup
R/C# Address Setup Time
R/C# Address Hold Time
R/C# to Write Enable High Time
OE# High Setup Time
OE# High Hold Time
OE# to Data# Polling Delay
OE# to Toggle Bit Delay
WE# Pulse Width
50
50
50
20
20
ns
TAH
ns
TCWH
TOES
TOEH
TOEP
TOET
TWP
ns
ns
ns
40
40
ns
ns
100
100
50
ns
TWPH
TDS
WE# Pulse Width High
Data Setup Time
ns
ns
TDH
Data Hold Time
5
ns
TIDA
TBP
Software ID Access and Exit Time
Byte Programming Time
Sector-Erase Time
150
20
ns
µs
TSE
25
ms
ms
TBE
Block-Erase Time
25
TSCE
Chip-Erase Time
100
ms
T22.2 25085
Table 23:Reset Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol
TPRST
TRSTP
TRSTF
Parameter
Min
1
Max
Units
ms
ns
VDD stable to Reset Low
RST# Pulse Width
100
RST# Low to Output Float
48
ns
1
TRST
RST# High to Row Address Setup
RST# Low to reset during Sector-/Block-Erase or Program
RST# Low to reset during Chip-Erase
1
µs
TRSTE
TRSTC
10
50
µs
µs
T23.1 25085
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.
©2011 Silicon Storage Technology, Inc.
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8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
V
DD
T
PRST
Row Address
Addresses
R/C#
T
RSTP
RST#
Sector-/Block-Erase
or Program operation
aborted
T
RSTE
T
RSTC
Chip-Erase
aborted
T
T
RST
RSTF
DQ
7-0
1161 F15.0
Figure 12:Reset Timing Diagram (PP Mode)
T
RSTP
RST#
Addresses
R/C#
T
T
RST
RC
Row Address
Column Address
Row Address
Column Address
T
T
T
T
AH
AS
AH
AS
V
IH
WE#
OE#
T
AA
T
T
OH
OE
T
OHZ
T
OLZ
High-Z
High-Z
Data Valid
DQ
7-0
1161 F16.0
Figure 13:Read Cycle Timing Diagram (PP Mode)
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
T
RSTP
RST#
Addresses
R/C#
T
RST
Row Address
Column Address
T
T
T
T
AH
AS
AH
AS
T
T
OEH
CWH
OE#
T
OES
T
T
WPH
WP
WE#
T
T
DH
DS
DQ
7-0
Data Valid
1161 F17.0
Figure 14:Write Cycle Timing Diagram (PP Mode)
Row
Column
Addresses
R/C#
WE#
OE#
T
OEP
DQ
D
D#
D#
D
7
1161 F18.0
Figure 15:Data# Polling Timing Diagram (PP Mode)
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8 Mbit Firmware Hub
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Data Sheet
Addresses
Row
Column
R/C#
WE#
OE#
T
OET
D
D
DQ
6
1161 F19.0
Figure 16:Toggle Bit Timing Diagram (PP Mode)
Four-Byte Code for Byte-Program
Addresses
5555
2AAA
5555
BA
R/C#
OE#
T
T
WP WPH
T
BP
WE#
Internal Program Starts
SB0
AA
SB1
55
SB2
A0
SB3
Data
DQ
7-0
BA = Byte-Program Address
1161 F20.0
Figure 17:Byte-Program Timing Diagram (PP Mode)
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Six-Byte code for
Sector-Erase Operation
Addresses
5555
2AAA
5555
5555
2AAA
SA
X
R/C#
OE#
T
WP
T
SE
T
WPH
WE#
SB0
AA
SB1
55
SB2
80
SB3
AA
SB4
55
SB5 Internal Erasure Starts
30
DQ
7-0
1161 F21.0
SA = Sector Address
X
Figure 18:Sector-Erase Timing Diagram (PP Mode)
Six-Byte code for
Block-Erase Operation
Addresses
5555
2AAA
5555
5555
2AAA
BA
X
R/C#
OE#
WE#
T
WP
T
BE
T
WPH
Internal Erasure Starts
SB0
AA
SB1
SB2
80
SB3
AA
SB4
55
SB5
50
55
DQ
7-0
1161 F22.0
Figure 19:Block-Erase Timing Diagram (PP Mode)
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Six-Byte code for Chip-Erase Operation
Addresses
5555
2AAA
5555
5555
2AAA
5555
R/C#
OE#
T
WP
T
SCE
T
WPH
WE#
SB0
AA
SB1
55
SB2
80
SB3
AA
SB4
55
SB5
10
Internal Erasure Starts
DQ
7-0
1161 F23.0
Figure 20:Chip-Erase Timing Diagram (PP Mode)
Three-byte sequence for
Software ID Entry
Addresses
5555
2AAA
5555
0000
0001
R/C#
OE#
WE#
T
T
IDA
WP
T
WPH
T
AA
AA
SW0
55
90
BF
DQ
7-0
Device ID
SW1
SW2
1161 F24.2
Device ID = 5AH for SST49LF008A
Figure 21:Software ID Entry and Read (PP Mode)
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Three-Byte Sequence for
Software ID Exit and Reset
Addresses
5555
2AAA
5555
R/C#
OE#
WE#
T
WP
T
T
WPH
IDA
SW0
AA
SW1
SW2
F0
55
DQ
7-0
1161 F25.0
Figure 22:Software ID Exit and Reset (PP Mode)
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1161 F26.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Mea-
surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise
and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 23:AC Input/Output Reference Waveforms (PP Mode)
TO TESTER
TO DUT
C
L
1161 F27.0
Figure 24:A Test Load Example (PP Mode)
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Start
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1161 F28.0
Figure 25:Byte-Program Algorithm
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8 Mbit Firmware Hub
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Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Byte-
Program/Erase
Initiated
Byte-
Program/Erase
Initiated
Byte-
Program/Erase
Initiated
Read DQ
7
Read byte
Wait T
,
BP
T
T
SCE, BE
T
or SE
Read same
byte
Is DQ =
7
No
true data
Program/Erase
Completed
Yes
No
Does DQ
match
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1161 F29.0
Figure 26:Wait Options
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit
Reset Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: F0H
Address: XXH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Wait T
IDA
Write data: 90H
Address: 5555H
Write data: F0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1161 F30.0
Figure 27:Software Product Command Flowcharts
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8 Mbit Firmware Hub
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Data Sheet
Chip-Erase
Block-Erase
Sector-Erase
Command Sequence
Command Sequence
Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 80H
Address: 5555H
Write data: 80H
Address: 5555H
Write data: 80H
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 10H
Address: 5555H
Write data: 50H
Write data: 30H
Address: BA
Address: SA
X
X
Wait Options
Wait Options
Wait Options
Chip erased
to FFH
Block erased
to FFH
Sector erased
to FFH
1161 F31.0
Figure 28:Erase Command Sequence
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Product Ordering Information
SST 49 LF 008A
-
33
-
4C
-
EIE
-
XX XX XXXX
-
XX
-
XX
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
H = 32 leads
I = 40 leads
Package Type
N = PLCC
W = TSOP (type 1, die up, 8mm x
14mm)
E = TSOP (type 1, die up, 10mm x
20mm)
Operating Temperature
C = Commercial = 0°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Serial Access Clock Frequency
33 = 33 MHz
Version
A = Second Version
Device Density
008 = 8 Mbit
Voltage Range
L = 3.0-3.6V
Product Series
49 = Firmware Hub for Intel 8xx Chip-
sets
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST49LF008A
SST49LF008A-33-4C-WHE
SST49LF008A-33-4C-NHE
SST49LF008A-33-4C-EIE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combi-
nations.
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Packaging Diagrams
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.453
.447
.112
.106
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30°
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
Figure 29:32-lead Plastic Lead Chip Carrier (PLCC)
SST Package Code: NH
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8 Mbit Firmware Hub
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Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0°- 5°
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
32-tsop-WH-7
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Figure 30:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
SST Package Code: WH
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8 Mbit Firmware Hub
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Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
10.10
9.90
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
40-tsop-EI-7
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Figure 31:40-lead Thin Small Outline Package (TSOP) 10mm x 20mm
SST Package Code: EI
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8 Mbit Firmware Hub
SST49LF008A
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Data Sheet
Table 24:Revision History
Revision
Draft Changes
Date
06
July 2001
•
•
2002 Data Book
Changed Transient Voltage from -1.0V to VDD +1.0V to -2.0V to VDD
+2.0V to match Intel FWH spec per IBM requirement.
•
•
•
•
Added footnote for Transient Voltage.
Updated footnote for Output Short Circuit Current.
Updated Data# Polling description
Corrected the values in Table 5 on page 14: General Purpose Inputs
Register
•
•
•
•
•
•
Added note to Table 12 on page 23: DC Operating Characteristics
Added 40-lead TSOP for SST49LF008A only
Corrected the IDD Test Conditions in Table 12 on page 23
2004 Data Book
07
08
June 2003
Dec 2003
Updated document status to Data Sheet
09
10
Oct 2004
Nov 2004
Removed 2 Mbit and 3 Mbit devices - refer to EOL Product Data Sheet
S71161(01)
•
Removed 32-PLCC (NH/NHE) Package and associated MPNs for the 4
Mbit device
refer to EOL Product Data Sheet S71161(03).
•
•
•
Clarified the Solder Temperature Profile under “Absolute Maximum
Stress Ratings” on page 22
11
Mar 2006
Removed 4 Mbit WH/WHE device - refer to EOL Product Data Sheet
S71161(03)
Added statement that non-Pb devices are RoHS compliant to Features
section
•
•
•
•
•
•
Updated Surface Mount Solder Reflow Temperature information
Removed leaded part numbers
Applied new formatting
A
Oct 2011
Applied new document format
Released document under letter revision system
Updated Spec number from S71161 to DS25085
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
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8 Mbit Firmware Hub
SST49LF008A
A Microchip Technology Company
Data Sheet
ISBN:978-1-61341-713-3
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-
nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25085A
10/11
45
相关型号：
SST49LF016C-33-4C-NHE
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MICROCHIP
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