SST85LD1001T-60-RI-LBTE [MICROCHIP]
Micro Peripheral IC;
| 型号： | SST85LD1001T-60-RI-LBTE |
| 厂家： | 
MICROCHIP |
| 描述： | Micro Peripheral IC |
| 文件： | 总36页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 MByte/ 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
The SST85LD0512 / SST85LD1001T / SST85LD1002U NANDrive™ solid-state drive (SSD)
combines a NAND controller and 512 MBytes / 1 GByte / 2 GBytes of NAND flash in a multi-
chip package. It provides complete ATA/IDE hard disk drive functionality in a small package
for easy, space-saving mounting to a system motherboard. This makes the SST85LD0512 /
SST85LD1001T / SST85LD1002U NANDrive SSD the ideal data storage solution for mobile
and embedded electronic products that require smaller and more reliable storage.
Features
• Industry Standard ATA/IDE Bus Interface
• Endurance
– 100 Million write cycles for NANDrive with advanced
NAND management technology
– Host Interface: 16-bit access
– Supports up to PIO Mode-6
– Supports up to Multi-word DMA Mode-4
– Supports up to Ultra DMA Mode-4
• Data Retention
– 10 years
• Low Power, 3.3V Power Supply
• Pre-programmed Embedded Firmware
• 5.0V or 3.3V Host Interface Through VDDQ Pins
– Executes industry standard ATA/IDE commands
– Implements dynamic wear-leveling algorithms to sub-
stantially increase the longevity of flash media
– Embedded Flash File System
• Low Current Operation:
– Active mode: 85 mA Typical
– Sleep mode: 160 µA Typical
• Robust Built-in ECC
• Power Management Unit
• Multi-tasking Technology Enables Fast
Sustained Write Performance (Host-to-Flash)
– Up to 20 MByte/sec
– Immediate disabling of unused circuitry without host
intervention
– Zero wake-up latency
• Expanded Data Protection
• Fast Sustained Read Performance (Flash-to-Host)
– WP#/PD# pin configurable by firmware for
prevention of data overwrites
– Up to 30 MByte/sec
• Industrial Temperature Range
• 20-byte Unique ID for Enhanced Security
– Factory Pre-programmed 10-byte Unique ID
– User-Programmable 10-byte ID
– -40°C to +85°C for industrial operation
• LBGA package
– 12mm x 24mm
• Integrated Voltage Detector
• All Devices are RoHS Compliant
– Prevents data loss due to unexpected power-down or
brownout.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
www.sst.com
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Product Description
The SST85LD0512, SST85LD1001T and SST85LD1002U NANDrive™ solid-state drives (SSD) are
high-performance, fully-integrated, embedded flash solid state drives. They combine an integrated ATA
Controller and either 512 MByte, 1 GByte, or 2 GByte of NAND Flash in a multi-chip package. These
products are ideal for industrial grade solid state mass storage applications offering new and expanded
functionality while enabling cost effective designs.
ATA-based solid state mass storage technology is widely used in portable and desktop computers,
digital cameras, music players, handheld data collection scanners, cellular phones, PCS phones,
PDAs, handy terminals, personal communicators, robotics, audio recorders, monitoring devices, and
set-top boxes.
SST NANDrive is a single device, solid state drive designed for embedded ATA/IDE protocol systems
and supports standard ATA/IDE protocol with up to PIO Mode-6, Multi-word DMA Mode-4 and Ultra
DMA Mode-4 interface. The built in microcontroller and file management firmware communicates with
ATA standard interfaces; thereby eliminating the need for additional or proprietary software such as
Flash File System (FFS) and Memory Technology Driver (MTD) software.
The SST85LD0512 / SST85LD1001T / SST85LD1002U NANDrives provide complete IDE Hard Disk
Drive functionality and compatibility in a 12mm x 24mm BGA package for easy, space saving mounting
to a system motherboard. It is a perfect solution for portable, consumer electronic products requiring
smaller and more reliable data storage.
The NANDrive provides a WP#/PD# pin to protect critical information stored in the flash media from
unauthorized overwrites.
The NANDrive is pre-programmed with a 10-byte unique serial ID. For even greater system security,
the user has the option of programming an additional 10 Bytes of ID space to create a unique, 20-byte
ID.
NANDrive SSD is available with advanced NAND management technology, a NAND memory manage-
ment technology that enhances data security, significantly improves endurance, and accurately pre-
dicts the minimum life span of NAND flash devices. Advanced NAND management technology
combines NAND controller hardware error correction, advanced wear leveling algorithms, and bad
block management to extend the life of the product.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
2
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
General Description
Each NANDrive contains an integrated ATA Controller and one or more NAND Flash dice in a LBGA
package. Refer to Figure 1 for the NANDrive block diagram.
Performance-optimized NANDrive
The heart of the NANDrive is the ATA Flash Disk Controller which translates standard ATA signals into
flash media data and control signals. The following components contribute to the NANDrive’s operation.
Microcontroller Unit (MCU)
The MCU translates ATA/IDE commands into data and control signals required for flash media operation.
Internal Direct Memory Access (DMA)
The NANDrive uses internal DMA allowing instant data transfer from buffer to flash media. This imple-
mentation eliminates microcontroller overhead associated with the traditional, firmware-based
approach, thereby increasing the data transfer rate.
Power Management Unit (PMU)
The power management unit controls the power consumption of the NANDrive. The PMU dramatically
reduces the power consumption of the NANDrive by putting the part of the circuitry that is not in opera-
tion into sleep mode.
SRAM Buffer
A key contributor to the NANDrive performance is an SRAM buffer. The buffer optimizes the host’s
data transfer to and from the flash media.
Embedded Flash File System
The embedded flash file system is an integral part of the NANDrive. It contains MCU firmware that per-
forms the following tasks:
1. Translates host side signals into flash media writes and reads.
2. Provides dynamic flash media wear leveling to spread the flash writes to increase the lon-
gevity of flash media.
3. Keeps track of data file structures.
Error Correction Code (ECC)
High performance is achieved through optimized hardware error detection and correction.
Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed for manufacturing error reporting. Always pro-
vide SCI interface access to PCB design to aid in design validation.
Multi-tasking Interface
The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read,
Program, and Erase operations to multiple flash media devices.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
3
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Advanced NAND Management Technology
Advanced NAND management technology balances the wear on erased blocks with an advanced
wear-leveling scheme which provides a minimum of 100 million product write cycles. Advanced NAND
management technology tracks the number of program/erase cycles within a group. When the host
updates data, higher priority is given to the less frequently written erase blocks; thereby, evenly distrib-
uting host writes within a wear-leveling group.
Advanced NAND management technology enhances NANDrive security with password protection and
four independent protection zones which can be set to Read-only or Hidden.
Functional Blocks
NANDrive
NAND Controller
MCU
Embedded
Flash
File System
SRAM Buffer
HOST
ATA/IDE
BUS
ECC
NAND
Flash
Internal
DMA
PMU
SCI
1382 B1.1
Figure 1: NANDrive Block Diagram
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
4
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Pin Assignments
The signal/pin assignments are listed in Figure 2. Low active signals have a “#” suffix. Pin types are
Input, Output, or Input/Output. Signals whose source is the host are designated as inputs while signals
that the NANDrive sources are outputs.
The NANDrive functions in ATA mode, which is compatible with IDE hard disk drives.
TOP VIEW (balls facing down)
10
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
9
8
7
6
5
4
3
2
1
DASP# VDD
SCIDOUT D9
D11
D10
D14 IOWR#
VSS PDIAG# CSEL VDDQ
IOCS16# A2 CS3FX# DNU
DNU
D13
VSS
D15
D12
DNU
DNU
SCIDIN SCICLK D8
POR#
VSS
DNU
DNU
DNU
DNU
DNU DNU WP#/PD# GND
VSS
DNU
DNU
DNU
DNU
DNU
DNU
VDD
VDD
DNU
DNU
DNU RESET# D7
VSS
D2
D6
D4
IORDY VSS
DMARQ A1
DNU
DNU
DNU
DNU
D5
D3
D1
CS1FX# DNU
DNU
DNU
DNU
DNU
DNU
DNU
VREG VDDQ
D0 IORD#
INTRQ DMACK# A0
VDD
DNU
DNU
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1382 91-lbz P1.3
Figure 2: Pin Assignments for 91-Ball LBGA
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
5
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 1: Pin Assignments (1 of 3)
Pin No.
Pin
I/O
Symbol
Type Type Name and Functions
91-TFBGA
Host Side Interface
A2
K8
K3
L2
H8
G9
G8
H7
F9
F8
E8
F7
F4
H4
E3
H3
F3
G3
F2
G2
K2
J3
A1
I
I1Z A[2:0] are used to select one of eight registers in the Task File.
A0
D15
D14
D13
D12
D11
D10
D9
D8
I/O I1Z/O2 D[15:0] Data bus
D7
D6
D5
D4
D3
D2
D1
D0
DMACK#
DMARQ
CS1FX#
CS3FX#
I
I2U DMA Acknowledge - input from host
O1 DMA Request to host
O
L3
L8
CS1FX# is the chip select for the task file registers
I
I
I2Z
CS3FX# is used to select the alternate status register and the Device
Control register.
CSEL
L9
I1U This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is configured
as a Master. When the pin is open, this device is configured as a
Slave. The pin setting should remain the same from Power-on to
Power-down.
IORD#: This is an I/O Read Strobe generated by the host. When Ultra
DMA mode is not active, this signal gates I/O data from the device.
HDMARDY#: In Ultra DMA mode when DMA Read is active, this sig-
nal is asserted by the host to indicate that the host is ready to receive
Ultra DMA data-in bursts. The host may negate HDMARDY# to pause
an Ultra DMA transfer.
IORD#
H2
I
I2Z
HSTROBE: When DMA Write is active, this signal is the data-out
strobe generated by the host. Both the rising and falling edges of
HSTROBE cause data to be latched by the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data-out burst.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
6
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 1: Pin Assignments (Continued) (2 of 3)
Pin No.
Pin
Type Type Name and Functions
IOWR#: This is an I/O Write Strobe generated by the host. When Ultra
I/O
Symbol
91-TFBGA
DMA mode is not active, this signal is used to clock I/O data into the
device.
IOWR#
H9
I
I2Z
STOP: When Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst
IORDY: When Ultra DMA mode DMA Write is not active and the
device is not ready to respond to a data transfer request, this signal is
negated to extend the Host transfer cycle. However, it is never
negated by this controller.
DDMARDY#: When Ultra DMA mode DMA Write is active, this signal
is asserted by the host to indicate that the device is ready to receive
IORDY
J4
J8
O
I2Z Ultra DMA data-in bursts. The device may negate DDMARDY# to
pause an Ultra DMA transfer.
DSTROBE: When Ultra DMA mode DMA Read is active, this signal is
the data-out strobe generated by the device. Both the rising and falling
edges of DSTROBE cause data to be latched by the host. The device
may stop generating DSTROBE edges to pause an Ultra DMA data-
out burst.
IOCS16#
O
O
O2 This output signal is asserted low when the device is indicating a word
data transfer cycle.
INTRQ
PDIAG#
DASP#
J2
K9
D9
O1 This signal is the active high Interrupt Request to the host.
I/O I1U/O1 The Pass Diagnostic signal in the Master/Slave handshake protocol.
I/O I1U/O6 The Drive Active/Slave Present signal in the Master/Slave handshake
protocol.
RESET#
E4
F6
I
I
I2U This input pin is the active low hardware reset from the host.
WP#/PD#
I3U The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The Write
Protect or Power-down modes can be selected through the host com-
mand. The Write Protect mode is the factory default setting.
Serial Communication Interface (SCI)
SCIDOUT
D8
D7
E7
O
I
O4 SCI interface data output
I3U SCI interface data input
I3U SCI interface clock
SCIDIN
SCICLK
I
Miscellaneous
VSS
G4, G6, G7,
K4, K6, K7, PWR
J9
Ground
VDD
E9, K5,
PWR
VDD (3.3V)
L5, M2
VDDQ
E2, M9
J7
PWR
I
VDDQ (5V/3.3V) for Host interface
POR#
Analog Power-on Reset (POR). Active Low
Input1
VREG
D2
O
External capacitor pin
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
7
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 1: Pin Assignments (Continued) (3 of 3)
Pin No.
Pin
I/O
Symbol
Type Type Name and Functions
91-TFBGA
DNU
D3, D4, D5,
D6, E5,E6,
F5, G5, L4,
L6, L7, M3,
M4,M5,
Do not use.
M6,M7, M8,
N2, N3, N4,
N5, N6, N7,
N8, N9, R9,
R10,T9,
T10,A1, A2,
A9, A10,B1,
B9,B10, R1,
R2, T1, T2
T1.4 1382
1. Analog input for supply voltage detection
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
8
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Capacity Specification
Table 2 shows the default capacity and specific settings for heads, sectors, and cylinders. Users can
change the default settings in the drive ID table using the Identity-Drive command. If the total number of
bytes is less than the default, the remaining space could be used as spares to increase the flash drive
endurance. It should also be noted that if the total flash drive capacity exceeds the total default number of
bytes, the flash drive endurance will be reduced.
Table 2: Default NANDrive Settings
Capacity
512 MByte
1 GByte
Total Bytes
512,483,328
1,024,966,656
2,048,385,024
Cylinders
993
Heads
16
Sectors
63
Max LBA
1,000,944
2,001,888
4,000,752
1986
16
63
2 GByte
3969
16
63
T2.6 1382
Table 3: Sustained Performance
Product
Write Performance
Up to 5 MByte/sec
Up to 10 MByte/sec
Up to 20 MByte/sec
Read Performance
Up to 17 MByte/sec
Up to 30 MByte/sec
Up to 30 MByte/sec
SST85LD0512-60-RI-LBTE
SST85LD1001T-60-RI-LBTE
SST85LD1002U-60-RI-LBTE
T3.1382
Table 4: Supported ATA Modes
Products
PIO
MWDMA
Up to Mode-4
UltraDMA
Up to Mode-4
SST85LD0512-60-RI-LBTE
SST85LD1001T-60-RI-LBTE
SST85LD1002U-60-RI-LBTE
Up to Mode-6
T4.1382
Table 5: Advanced NAND Management Technology Write Cycles
Write Cycles per
Group
Number of Groups Wear-leveling
Product
per Product
Group Size
128 MBytes
256 MBytes
512 MBytes
Cluster Size
2 KBytes
SST85LD0512-60-RI-LBTE 100M
SST85LD1001T-60-RI-LBTE 100M
SST85LD1002U-60-RI-LBTE 100M
4
4
4
4 KBytes
8 KBytes
T5.1382
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
9
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Configurable Write Protect/Power-down Modes
The WP#/PD# pin can be used for either Write Protect mode or Power-down mode, but only one mode
is active at any time. Either mode can be selected through the host command, Set-WP#/PD#-Mode.
Once the mode is set with this command, the device will stay in the configured mode until the next time
this command is issued. Power-off or reset will not change the configured mode.
Write Protect Mode
When the device is configured in the Write Protect mode, the WP#/PD# pin offers extended data pro-
tection. This feature can be either selected through a jumper or host logic to protect the stored data
from inadvertent system writes or erases, and viruses. The Write Protect feature protects the full
address space of the data stored on the flash media.
In the Write Protect mode, the WP#/PD# pin should be asserted prior to issuing the destructive com-
mands: Erase-Sector, Format-Track, Write-DMA, Write-Multiple, Write-Multiple-without-Erase, Write-
Sector(s), Write-Sector-without-Erase, or Write-Verify. This will force the NANDrive to reject any
destructive commands from the ATA interface. All destructive commands will return 51H in the Status
register and 04H in the Error register signifying an invalid command. All non-destructive commands
will be executed normally.
Power-down Mode
When configuring the device in Power-down mode, if the WP#/PD# pin is asserted during a command,
the NANDrive completes the current command and returns to the standby mode immediately to save
power. Afterwards, the device will not accept any other commands. Only a Power-on Reset (POR) or
hardware reset will bring the device to normal operation with the WP#/PD# pin de-asserted.
Power-on initialization and Capacity Expansion
NANDrive is self-initialized during the first power-up. As soon as the power is applied to the NANDrive
it reports busy for typically up to five seconds while performing bad blocks search and low level format.
This initialization is a one time event.
During the first self-initialization, the NANDrive firmware scans all connected flash media devices and
reads their device ID. If the device ID matches the listed flash media devices, the NANDrive performs
drive recognition based on the algorithm provided by the flash media suppliers, including setting up the
bad block table, executing all the necessary handshaking routines for flash media support, and, finally,
performing the low-level format.
If the drive initialization fails, and a visual inspection is unable to determine the problem, SST provides
a comprehensive interface for manufacturing flow debug. This interface not only allows debug of the
failure and manual reset of the initialization process, but also allows customization of user definable
options.
ATA/IDE Interface
The ATA interface can be used for NANDrive manufacturing support. SST provides an example of a
DOS-based solution (an executable routine) for manufacturing debug and rework.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
10
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Serial Communication Interface (SCI)
For additional manufacturing flexibility, the SCI bus can be used for manufacturing error reporting. The
SCI consists of 3 active signals: SCIDOUT, SCIDIN, and SCICLK. Always provide SCI interface access
to PCB design to aid in design validation.
Lifetime Expectancy
NANDrive is available with two endurance options—standard NANDrive and NANDrive with advanced
NAND management technology.
NANDrive with Advanced NAND Management Technology
NANDrive with advanced NAND management technology significantly extends the life of a product
with its extensive ECC, advanced wear-leveling, and data scan and Refresh (DSR) algorithms. Each
NANDrive device is partitioned into four wear-leveling groups. See Table 5 for the group size of each
product.
Each NANDrive wear-leveling group can receive at least 100 million write cycles from the host. With
four wear-leveling groups in each product, 400 million write cycles per product is possible when host
writes are evenly distributed across groups.
For applications where data security is essential, NANDrive with advanced NAND management tech-
nology offers two additional protection features—protection zones and password protections.
Protection zones - Up to four independent protection zones can be enabled as either Read-only or Hid-
den (Read/Write protected). If the zones are not enabled, the data is unprotected (default configura-
tion).
Password Protection - Requires a customer-unique password to access information within the pro-
tected zones.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
11
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Power-on and Brown-out Reset Characteristics
Please contact SST to obtain NANDrive reference design schematics including the POR# circuit for
industrial NANDrive offerings.
T
T
R
F
10%
10%
90%
90%
V
/POR#
DD
1382 F01.0
Figure 3: Power-on and Brown-out Reset Timing
Table 6: Power-on and Brown-out Reset Timing
Item
Symbol
TR
Min
Max
Units
ms
V
DD/POR# Rise Time1
250
250
VDD/POR# Fall Time2
TF
ms
T6.0 1382
1. VDD Rise Time should be faster than or equal to POR# Rise Time.
2. VDD Fall Time should be slower than or equal to POR# Fall Time.
I/O Transfer Function
The default operation for the NANDrive is 16-bit. However, if the host issues a Set-Feature command
to enable 8-bit mode, the NANDrive permits 8-bit data access.
The following table defines the function of various operations.
Table 7: I/O Function
Function Code
Invalid Mode
CS3FX#
VIL
CS1FX# A0-A2 IORD# IOWR#
D15-D8
Undefined
High Z
X
D7-D0
Undefined
High Z
Data In
Data Out
In
VIL
VIH
VIL
VIL
VIL
VIL
VIH
VIH
X
X
X
X
Standby Mode
VIH
X
X
Task File Write
VIH
1-7H
1-7H
0
VIH
VIL
VIH
VIL
VIH
VIL
VIL
VIH
VIL
VIH
VIL
VIH
Task File Read
VIH
High Z
In1
Out1
Data Register Write
Data Register Read
Control Register Write
Alt Status Read
VIH
VIH
0
Out
VIL
6H
6H
X
Control In
VIL
High Z
Status Out
T7.0 1382
1. If 8-bit data transfer mode is enabled.
In 8-bit data transfer mode, High Byte is undefined for Data Out. For Data In, X can be VIH or VIL, but no other value.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
12
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Software Interface
NANDrive Command Description
This section defines the software requirements and the format of the commands the host sends to the
NANDrive. Commands are issued to the NANDrive by loading the required registers in the command block
with the supplied parameters, and then writing the command code to the Command register. With the
exception of commands listed in Sections “Idle - 97H or E3H”, “Set-Sleep-Mode - 99H or E6H”, and “Set-
WP#/PD#-Mode - 8BH”, NANDrive complies with ATA-6 Specifications.
NANDrive Command Set
Table 8 summarizes the NANDrive command set.
Table 8: NANDrive Command Set (1 of 2)
Command
Code
E5H or 98H
90H
FR1
-
SC2
-
SN3
-
CY4
-
DH5
D8
D
Y
LBA6
Check-Power-Mode
Execute-Drive-Diagnostic
Erase-Sector(s)
Flush-Cache
-
-
-
-
-
-
C0H
-
Y
Y
-
Y
-
Y
-
E7H
-
-
D
Y8
D
D
D
Y
Format-Track
50H
-
Y7
-
-
Y
-
Y
-
Identify-Drive
ECH
-
-
Idle
E3H or 97H
E1H or 95H
91H
-
Y
-
-
-
-
Idle-Immediate
Initialize-Drive-Parameters
NOP
-
-
-
-
-
Y
-
-
-
-
00H
-
-
-
D
D
Y
-
Read-Buffer
E4H
-
-
-
-
-
Read-DMA
C8H or C9H
C4H
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Read-Multiple
-
Y
Read-Sector(s)
Read-Verify-Sector(s)
Recalibrate
20H or 21H
40H or 41H
1XH
-
Y
-
Y
-
D
D
D
D
D
D
D
D
Y
Request-Sense
Security-Disable-Password
Security-Erase-Prepare
Security-Erase-Unit
Security-Freeze-Lock
Security-Set-Password
Security-Unlock
Seek
03H
-
-
-
-
-
F6H
-
-
-
-
-
F3H
-
-
-
-
-
F4H
-
-
-
-
-
F5H
-
-
-
-
-
F1H
-
-
-
-
-
F2H
-
-
-
-
-
7XH
-
-
Y
-
Y
-
Y
-
Set-Features
EFH
Y
Y
-
-
D
D
D
D
D
SMART
B0H
Y
Y
-
Y
-
Y
-
-
Set-Multiple-Mode
Set-Sleep-Mode
Set-WP#/PD#-Mode
C6H
-
E6H or 99H
8BH
-
-
-
-
Y
-
-
-
-
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
13
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 8: NANDrive Command Set (Continued) (2 of 2)
Command
Code
E2H or 96H
E0H or 94H
87H
FR1
SC2
-
SN3
-
CY4
-
DH5
D
D
Y
LBA6
Standby
-
-
-
-
-
-
-
-
-
-
-
Standby-Immediate
Translate-Sector
Write-Buffer
-
-
-
-
Y
-
Y
-
Y
-
Y
-
E8H
D
Y
Write-DMA
CAH or CBH
C5H
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Write-Multiple
Y
Write-Multiple-Without-Erase
Write-Sector(s)
Write-Sector(s)-Without-Erase
Write-Verify
CDH
Y
30H or 31H
38H
Y
Y
3CH
Y
Y
T8.1 1382
1. FR - Features register
2. SC - Sector Count register
3. SN - Sector Number register
4. CY - Cylinder registers
5. DH - Drive/Head register
6. LBA - Logical Block Address mode supported (see command descriptions for use)
7. Y - The register contains a valid parameter for this command.
8. For the Drive/Head register:Y means both the NANDrive and Head parameters are used;
D means only the NANDrive parameter is valid and not the Head parameter.
Identify-Drive - ECH
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
ECH
X
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
The Identify-Drive command enables the host to receive parameter information from the NANDrive.
This command has the same protocol as the Read-Sector(s) command. The parameter words in the
buffer have the arrangement and meanings defined in Table 9. All reserved bits or words are zero.
Table 9 gives the definition for each field in the Identify-Drive information.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
14
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 9: Identify-Drive Information (1 of 2)
Word
Address
Default
Value1
Total
Bytes
Data Field Type Information
General configuration bit
0
1
044AH
bbbbH2
0000H
bbbbH2
0000H
XXXXH
bbbbH2
bbbbH3
xxxxH
2
2
Default number of cylinders
Reserved
2
2
3
2
Default number of heads
4
2
Reserved
5
2
Vendor Unique
6
2
Default number of sectors per track
Number of sectors per device (Word 7 = MSW, Word 8 = LSW)
Vendor Unique
7-8
9
4
2
10-14
15-19
20
eeeeH4
ddddH5
0002H
xxxxH
10
10
2
User-programmable serial number in ASCII
SST preset, unique ID in ASCII
Buffer type
21
2
Vendor Unique
22
xxxxH
2
Vendor Unique
23-26
27-46
47
aaaaH6
ccccH7
8001H
0000H
0B00H
0000H
0200H
0000H
0007H
nnnnH
nnnnH
nnnnH
nnnnH
010X
8
Firmware revision in ASCII. Big Endian Byte Order in Word
User Definable Model number
Maximum number of sectors on Read/Write-Multiple command
Reserved
40
2
48
2
49
2
Capabilities
50
2
Reserved
51
2
PIO data transfer cycle timing mode
Reserved
52
2
53
2
Translation parameters are valid
Current numbers of cylinders
Current numbers of heads
54
2
55
2
56
2
Current sectors per track
57-58
59
4
Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW)
Multiple sector setting
2
60-61
62
nnnnH
0000H
0x07H
0003H
0078H
0078H
0078H
0078H
0000H
007EH
0019H
706BH
400CH
4
Total number of sectors addressable in LBA mode
Reserved
2
63
2
DMA data transfer is supported in NANDrive
Advanced PIO Transfer mode supported
120 ns cycle time support for Multi-word DMA Mode-2
120 ns cycle time support for Multi-word DMA Mode-2
PIO Mode-4 supported
64
2
65
2
66
2
67
2
68
2
PIO Mode-4 supported
69-79
80
22
2
Reserved
ATA major version number
81
2
ATA minor version number
82
2
Features/command sets supported
Features/command sets supported
83
2
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
15
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 9: Identify-Drive Information (Continued) (2 of 2)
Word
Address
Default
Value1
Total
Bytes
Data Field Type Information
Features/command sets supported
Features/command sets enabled
UDMA modes
84
85-87
88
4000H
xxxxH
xx1FH
xxxxH
xxxxH
0000H
xxxxH
0000H
0000H
xx2H
2
6
2
89
2
Time required for security erase unit completion
Time required for enhanced security erase unit completion
Reserved
90
2
91-127
128
74
2
Security Status
129-159
160-162
163
62
6
Vendor unique bytes
Reserved
2
CF Advanced True IDE Timing Mode capabilities and settings
Reserved
164-255
0000H
184
T9.4 1382
1. XXXX = This field is subject to change by the host or the device.
2. bbbb - default value set by controller. The selections could be user programmable.
3. n - calculated data based on product configuration
4. eeee - the default value is ‘0000000000’
5. dddd - unique number of each device
6. aaaa - any unique SST firmware revision
7. cccc - default value is “xxxMB NANDrive” or “xxxGB NANDrive” where xxx is the flash drive capacity.
The user has an option to change the model number during manufacturing.
Word 0: General Configuration
This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a
transfer rate greater than 10 MByte/sec and is not MFM encoded.
Word 1: Default Number of Cylinders
This field contains the number of translated cylinders in the default translation mode. This value will be
the same as the number of cylinders.
Word 3: Default Number of Heads
This field contains the number of translated heads in the default translation mode.
Word 6: Default Number of Sectors per Track
This field contains the number of sectors per track in the default translation mode.
Word 7-8: Number of Sectors
This field contains the number of sectors per NANDrive. This double word value is also the first invalid
address in LBA translation mode. This field is only required by CF feature set support.
Word 10-19: Serial Number
The contents of this field are right justified and padded with spaces (20H). The right-most ten bytes are
a SST preset, unique ID. The left-most ten bytes are a user-programmable value with a default value of
spaces.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
16
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 20: Buffer Type
This field defines the buffer capability:
0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and
the NANDrive.
Word 23-26: Firmware Revision
This field contains the revision of the firmware for this product.
Word 27-46: Model Number
This field is reserved for the model number for this product.
Word 47: Read-/Write-Multiple Sector Count
This field contains the maximum number of sectors that can be read or written per interrupt using the
Read-Multiple or Write-Multiple commands. Only a value of ‘1’ is supported.
Word 49: Capabilities
Bit
Function
13
Standby Timer
0: forces sleep mode when host is inactive.
11
9
IORDY Support
1: NANDrive supports PIO Mode-4.
LBA support
1: NANDrive supports LBA mode addressing.
8
DMA Support
1: DMA mode is supported.
Word 51: PIO Data Transfer Cycle Timing Mode
This field defines the mode for PIO data transfer. NANDrive supports up to PIO Mode-4.
Word 53: Translation Parameters Valid
Bit
0
Function
1: words 54-58 are valid and reflect the current number of cylinders, heads and sectors.
1: words 64-70 are valid to support PIO Mode-3 and 4.
1: words 88 are valid to support Ultra DMA data transfer.
1
2
Word 54-56: Current Number of Cylinders, Heads, Sectors/Track
These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in
the current translation mode.
Word 57-58: Current Capacity
This field contains the product of the current cylinders times heads times sectors.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
17
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 59: Multiple Sector Setting
This field contains a validity flag in the Odd Byte and the current number of sectors that can be trans-
ferred per interrupt for Read/Write Multiple in the Even Byte. The Odd Byte is always 01H which indi-
cates that the Even Byte is always valid.
The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this
word by default contains a 00H which indicates that Read/Write Multiple commands are not valid.
Word 60-61: Total Sectors Addressable in LBA Mode
This field contains the number of sectors addressable for the NANDrive in LBA mode only.
Word 63: Multi-word DMA Transfer Mode
This field identifies the multi-word DMA transfer modes supported by the NANDrive and indicates the
mode that is currently selected. Only one DMA mode can be selected at any given time.
Bit
Function
15-11
10
Reserved
Multi-word DMA mode 2 selected
1: Multi-word DMA mode 2 is selected and bits 8 and 9 are cleared to 0
0: Multi-word DMA mode 2 is not selected.
9
8
Multi-word DMA mode 1 selected
1: Multi-word DMA mode 1 is selected and 8 and 10 should be cleared to 0.
0: Multi-word DMA mode 1 is not selected.
Multi-word DMA mode 0 selected
1: Multi-word DMA mode 0 is selected and bits 9 and 10 are cleared to 0.
0: Multi-word DMA mode 0 is not selected.
7-3
2
Reserved
Multi-word DMA mode 2 supported
1: Multi-word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1.
1
0
Multi-word DMA mode 1 supported
1: Multi-word DMA mode 1 and below are supported.
Multi-word DMA mode 0 supported
1: Multi-word DMA mode 0 is supported.
Word 64: Advanced PIO Data Transfer Mode
Bits [7:0] is defined as the PIO data and register transfer supported field. If this field is supported, bit 1
of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this
field by the device to indicate the PIO modes the device is capable of supporting. Of these bits, bits
[7:2] are Reserved for future PIO modes.
Bit
0
Function
1: NANDrive supports PIO Mode-3.
1: NANDrive supports PIO Mode-4.
1
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
18
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word
This field defines the minimum Multi-word DMA transfer cycle time per word. This field defines, in
nanoseconds, the minimum cycle time that the NANDrive supports when performing Multi-word DMA
transfers on a per word basis. SST’s NANDrive supports up to Multi-word DMA Mode-2, so this field is
set to 120ns.
Word 66: Device Recommended Multi-word DMA Cycle Time
This field defines the NANDrive recommended Multi-word DMA transfer cycle time. This field defines,
in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing
a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal
conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the
NANDrive may negate DMARQ for flow control. The rate at which DMARQ is negated could result in
reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control
will not be used, but implies that higher performance may result. SST’s NANDrive supports up to Multi-
word DMA Mode-2, so this field is set to 120 ns.
Word 67: Minimum PIO Transfer Cycle Time Without Flow Control
This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guaran-
tees data integrity during the transfer without utilization of IORDY flow control. If this field is supported,
Bit 1 of word 53 shall be set to one.The NANDrive’s minimum cycle time is 120 ns. A value of 0078H is
reported.
Word 68: Minimum PIO Transfer Cycle Time With IORDY
This field defines, in nanoseconds, the minimum cycle time that the device supports while performing data
transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. The
NANDrive’s minimum cycle time is 120 ns, e.g., PIO Mode-4. A value of 0078H is reported.
Word 80: Major Version Number
If not 0000H or FFFFH, the device claims compliance with the major version(s) as indicated by bits
[6:1] being set to one. Since ATA standards maintain downward compatibility, a device may set more
than one bit. SST55VD020 supports ATA-1 to ATA-6.
Word 81: Minor Version Number
If an implementer claims that the revision of the standard they used to guide their implementation does
not need to be reported or if the implementation was based upon a standard prior to the ATA-3 stan-
dard, word 81 should be 0000H or FFFFH.
A value of 0019H reported in word 81 indicates ATA-6 T13 1410D revision 3a guided the implementa-
tion.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
19
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Words 82-84: Features/command sets supported
Words 82, 83, and 84 indicate the features and command sets supported. A value of 706BH is reported.
Word 82
Bit
15
14
13
12
11
10
9
Function
0: Obsolete
1: NOP command is supported
1: Read Buffer command is supported
1: Write Buffer command is supported
0: Obsolete
0: Host Protected Area feature set is not supported
0: Device Reset command is not supported
0: Service interrupt is not supported
0: Release interrupt is not supported
1: Look-ahead is supported
8
7
6
5
1: Write cache is supported
4
0: Packet Command feature set is not supported
1: Power Management feature set is supported
0: Removable Media feature set is not supported
1: Security Mode feature set is supported
1: SMART feature set is supported
3
2
1
0
Word 83
The values in this word should not be depended on by host implementers.
Bit
15
14
13-9
8
Function
0: Provides indication that the features/command sets supported words are not valid
1: Provides indication that the features/command sets supported words are valid
0: Reserved
0: Set-Max security extension is not supported
0: Reserved
7-5
4
0: Removable Media Status feature set is not supported
1: Advanced Power Management feature set is supported
1: CFA feature set is supported
3
2
1
0: Read DMA Queued and Write DMA Queued commands are not supported
0: Download Microcode command is not supported
0
Word 84
The values in this word should not be depended on by host implementers.
Bit
15
Function
0: Provides indication that the features/command sets supported words are valid
1: Provides indication that the features/command sets supported words are valid
0: Reserved
14
13-0
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
20
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Words 85-87: Features/command sets enabled
Words 85, 86, and 87 indicate features/command sets enabled.
The host can enable/disable the features or command set only if they are supported in
Words 82-84.
Word 85
Bit
15
14
Function
0: Obsolete
0: NOP command is not enabled
1: NOP command is enabled
13
12
0: Read Buffer command is not enabled
1: Read Buffer command is enabled
0:Write Buffer command is not enabled
1: Write Buffer command is enabled
11
10
9
0: Obsolete
1: Host Protected Area feature set is enabled
0: Device Reset command is not enabled
0: Service interrupt is not enabled
0: Release interrupt is not enabled
8
7
6
0: Look-ahead is not enabled
1: Look-ahead is enabled
5
0: Write cache is not enabled
1: Write cache is enabled
4
3
0: Packet Command feature set is not enabled
0: Power Management feature set is not enabled
1: Power Management feature set is enabled
2
1
0: Removable Media feature set is not enabled
0: Security Mode feature set has not been enabled via the Security Set Password command
1: Security Mode feature set has been enabled via the Security Set Password command
0
0: SMART feature set is not enabled
Word 86
Bit
15-9
8
Function
0: Reserved
1: Set-Max security extension supported
0: Reserved
7-5
4
0: Removable Media Status feature set is not enabled
0: Advanced Power Management feature set is not enabled
0: CFA feature set is disabled
3
2
1
0: Read DMA Queued and Write DMA Queued commands are not enabled
0: Download Microcode command is not enabled
0
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
21
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 87
The values in this word should not be depended on by host implementers.
Bit
15
Function
0: Provides indication that the features/command sets supported words are valid
1: Provides indication that the features/command sets supported words are valid
0: Reserved
14
13-0
Word 88
Bit
Function
15-13
12
Reserved
1: Ultra DMA mode 4 is selected
0: Ultra DMA mode 4 is not selected
1: Ultra DMA mode 3 is selected
0: Ultra DMA mode 3 is not selected
1: Ultra DMA mode 2 is selected
0: Ultra DMA mode 2 is not selected
1: Ultra DMA mode 1 is selected
0: Ultra DMA mode 1 is not selected
1: Ultra DMA mode 0 is selected
0: Ultra DMA mode 0 is not selected
Reserved
11
10
9
8
7-5
4
1: Ultra DMA mode 4 and below are supported
1: Ultra DMA mode 3 and below are supported
1: Ultra DMA mode 2 and below are supported
1: Ultra DMA mode 1 and below are supported
1: Ultra DMA mode 0 is supported
3
2
1
0
Word 89: Time required for Security erase unit completion
Word 89 specifies the time required for the Security Erase Unit command to complete.
Value
0
Time
Value not specified
(Value * 2) minutes
>508 minutes
1-254
255
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
22
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Word 90: Time required for Enhanced security erase unit completion
Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete.
Value
0
Time
Value not specified
(Value * 2) minutes
>508 minutes
1-254
255
Word 128: Security Status
Bit
Function
8
Security Level
1: Security mode is enabled and the security level is maximum
0: and security mode is enabled, indicates that the security level is high
5
4
Enhanced security erase unit feature supported
1: Enhanced security erase unit feature set is supported
Expire
1: Security count has expired and Security Unlock and Security Erase Unit are command
aborted until a Power-on reset or hard reset
3
2
1
Freeze
1: Security is frozen
Lock
1: Security is locked
Enable/Disable
1: Security is enabled
0: Security is disabled
0
Capability
1: NANDrive supports security mode feature set
0: NANDrive does not support security mode feature set
Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings
This word describes the capabilities and current settings for CF modes utilizing the True IDE interface.
Four separate fields determine support and selection options in the Advanced PIO and Advanced Mul-
tiword DMA timing modes. For information on the older modes, see “Word 63: Multi-word DMA Trans-
fer Mode” on page 18 and “Word 64: Advanced PIO Data Transfer Mode” on page 18. When the
Identity drive command executes, the device returns 0492H.
Bit
Function
2-0
Advanced True IDE PIO Mode Support
Indicates the maximum True IDE PIO mode supported by the card
Value
Time
0
Specified in word 64
PIO Mode 5
PIO Mode 6
Reserved
1
2
3-7
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
23
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
5-3
Value
Advanced True IDE Multiword DMA Mode Support
Indicates the maximum True IDE Multiword DMA mode supported by the card
Time
0
Specified in word 63
Multiword DMA Mode 3
Multiword DMA Mode 4
Reserved
1
2
3-7
8-6
Advanced True IDE PIO Mode Selected
Indicates the current True IDE PIO mode selected on the card
Value
Time
0
Specified in word 64
PIO Mode 5
PIO Mode 6
Reserved
1
2
3-7
11-9
Advanced True IDE Multiword DMA Mode Selected
Indicates the current True IDE Multiword DMA mode selected on the card
Value
Time
0
Specified in word 63
Multiword DMA Mode 3
Multiword DMA Mode 4
Reserved
1
2
3-7
15-12
Reserved
Set-Features - EFH
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
EFH
X
Drive
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
Config
Feature
This command is used by the host to establish or select certain features. Table 10 defines all features
that are supported.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
24
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 10: Features Supported
Feature
01H
02H
03H
09H
55H
66H
69H
81H
82H
89H
96H
97H
AAH
CCH
Operation
Enable 8-bit data transfers.
Enable Write cache
Set transfer mode based on value in Sector Count register. Table 11 defines the values.
Enable Extended Power Operations
Disable Read Look Ahead.
Disable Power-on Reset (POR) establishment of defaults at software reset.
NOP - Accepted for backward compatibility.
Disable 8-bit data transfer.
Disable Write Cache
Disable Extended Power operations
NOP - Accepted for backward compatibility.
Accepted for backward compatibility. Use of this Feature is not recommended.
Enable Read-Look-Ahead
Enable Power-on Reset (POR) establishment of defaults at software reset.
T10.0 1382
Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature com-
mand is issued all data transfers will occur on the low order D7-D0 data bus and the IOCS16# signal
will not be asserted for data register accesses.
Features 02H and 82H allow the host to enable or disable write cache in the NANDrives that imple-
ment write cache. When the subcommand Disable-Write-Cache is issued, the NANDrive should ini-
tiate the sequence to flush cache to non-volatile memory before command completion.
Feature 03H allows the host to select the transfer mode by specifying a value in the Sector Count reg-
ister. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One
PIO mode is selected at all times. The host may change the selected modes by the Set-Features com-
mand.
Feature 55H is the default feature for the NANDrive. Therefore, the host does not have to issue Set-
Features command with this feature unless it is necessary for compatibility reasons.
Features 66H and CCH can be used to enable and disable whether the Power-on Reset (POR)
Defaults will be set when a software reset occurs.
Table 11: Transfer Mode Values
Mode
Bits [7:3]
00000b
00000b
00001b
00100b
01000b
Other
Bits [2:0]
000b
PIO default mode
PIO default mode, disable IORDY
PIO flow control transfer mode
Multi-word DMA mode
Ultra-DMA mode
001b
mode1
mode1
mode1
N/A
Reserved
T11.1 1382
1. Mode = transfer mode number, all other values are not valid
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
25
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Idle - 97H or E3H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
97H or E3H
Drive
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Timer Count (5 msec increments)
X
This command causes the NANDrive to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milli-
seconds and the automatic Power-down mode is enabled. If the sector count is zero, the automatic
Power-down mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that
this time base (5 msec) is different from the ATA specification.
Set-Sleep-Mode - 99H or E6H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
99H or E6H
Drive
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command causes the NANDrive to set BSY, enter the Sleep mode, clear BSY and generate an
interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is
permitted but not required). Sleep mode is also entered when internal timers expire so the host does
not need to issue this command except when it wishes to enter Sleep mode immediately. The default
value for the timer is 15 milliseconds.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
26
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Set-WP#/PD#-Mode - 8BH
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
8BH
X
Drive
X
6EH
44H
72H
50H
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
55H or AAH
This command configures the WP#/PD# pin for either the Write Protect mode or the Power-down
mode. When the host sends this command to the device with the value AAH in the feature register, the
WP#/PD# pin is configured for the Write Protect mode. The Write Protect mode is the factory default
setting. When the host sends this command to the device with the value 55H in the feature register,
WP#/PD# is configured for the Power-down mode.
All values in the C/D/H register, the Cylinder Low register, the Cylinder High register, the Sector Num-
ber register, the Sector Count register, and the Feature register need to match the values shown
above, otherwise, the command will be treated as an invalid command.
Once the mode is set with this command, the device will stay in the configured mode until the next time
this command is issued. Power-off or reset will not change the configured mode.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
27
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Error Posting
The following table summarizes the valid status and error values for the NANDrive command set.
Table 12: Error and Status Register1
Error Register
Status Register
Command
BBK UNC IDNF ABRT AMNF RDY
DWF DSC CORR ERR
Check-Power-Mode
Execute-Drive-Diagnostic
Erase-Sector(s)
Flush-Cache
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Format-Track
Identify-Drive
Idle
Idle-Immediate
Initialize-Drive-Parameters
NOP
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Read-Buffer
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Read-DMA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Read-Multiple
Read-Sector(s)
Read-Verify-Sector(s)
Recalibrate
Request-Sense
Security-Disable-Password
Security-Erase-Prepare
Security-Erase-Unit
Security-Freeze-Lock
Security-Set-Password
Security-Unlock
Seek
V
V
V
V
V
V
V
V
V
V
V
Set-Features
Set-Multiple-Mode
Set-Sleep-Mode
Set-WP#/PD#-Mode
SMART
V
V
V
V
V
V
V
V
V
V
V
V
Standby
Standby-Immediate
Translate-Sector
Write-Buffer
V
V
Write-DMA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Write-Multiple
Write-Multiple-Without-Erase
Write-Sector(s)
Write-Sector(s)-Without-
Erase
Write-Verify
V
V
V
V
V
V
V
V
V
V
V
V
Invalid-Command-Code
V
T12.3 1382
1. The host is required to reissue any media access command (such as Read-Sector and Write Sector) that ends with an error condition.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
28
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Electrical Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Pins1 I3, I4, O4, and O5 to Ground Potential . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Pins1 I3, I4, O4, and O5 to Ground Potential . . . . . . -2.0V to VDD+2.0V
D.C. Voltage on Pins1 I1, I2, O1, O2, and O6 to Ground Potential . . . . . . . . . . . . -0.5V to VDDQ+0.5V
Transient Voltage (<20 ns) on Pins1 I1, I2, O1, O2, and O6 to Ground Potential . -2.0V to VDDQ+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
Surface Mount Solder Reflow Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Refer to Table 1 for pin assignment information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 13: Absolute Maximum Power Pin Stress Ratings
Parameter
Symbol
Conditions
Input Power
VDDQ
VDD
-0.3V min to 6.5V max
-0.3V min to 4.0V max
Voltage on all pins with respect to VSS
-0.5V min to VDDQ + 0.5V max
T13.0 1382
Table 14: Operating Range
VDDQ
VDD
Ambient
Range
Temperature
3.3V
5V
3.3V
Min
Max
Min
Max
5.5V
Min
Max
Industrial
-40°C to +85°C
3.135V
3.465V
4.5V
3.135V
3.465V
Table 15: AC Conditions of Test1
Input Rise/Fall Time
Output Load
10 ns
CL = 100 pF
T15.1 1382
1. See Figure 4
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
29
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 16: Recommended System Power-on Timing
Symbol
Parameter
Typical
Maximum
Units
TPU-INITIAL
Drive Initialization to Ready
3 sec + (0.5 sec/
GByte)
100
sec
1
TPU-READY1
Host Power-on/Reset to Ready Operation
Host Power-on/Reset to Write Operation
200
200
1000
1000
ms
1
TPU-WRITE1
ms
T16.3 1382
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 17: Capacitance (Ta = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
10 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
10 pF
T17.1 1382
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 18: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
1
ILTH
Latch Up
100 + IDD
mA
JEDEC Standard 78
T18.0 1382
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
30
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
DC Characteristics (SST85LD0512/1001T/1002U)
Table 19: DC Characteristic for Host Interface VDDQ = 3.3V or 5V
Symbol
VIH1
Type Parameter
Min
Max
Units Conditions
Input Voltage
I1
2.0
V
VDDQ=VDDQ Max
VIL1
0.8
10
VDDQ=VDDQ Min
IIL1
I1Z
I1U
Input Leakage Current
-10
uA
uA
V
VIN = GND to VDDQ
VDDQ = VDDQ Max
,
,
IU1
Input Pull-Up Current
-150
-6
VOUT = GND,
VDDQ = VDDQ Max
VT+2
VT-2
IIL2
Input Voltage Schmitt Trigger
2.0
VDDQ=VDDQ Max
VDDQ=VDDQ Min
I2
0.8
-10
I2Z
Input Leakage Current
Input Pull-Up Current
Output Voltage
10
-6
uA
uA
V
VIN = GND to VDDQ
VDDQ = VDDQ Max
IU2
I2U
O1
-150
2.4
VOUT = GND,
VDDQ = VDDQ Max
VOH1
VOL1
IOH1
IOL1
IOH1=IOH1 Min
IOL1=IOL1 Max
VDDQ=VDDQ Min
VDDQ=VDDQ Min
IOH2=IOH2 Min
IOL2=IOL2 Max
VDDQ=2.7V
0.4
4
Output Current
Output Current
Output Voltage
-4
2.4
-8
mA
mA
V
VOH2
VOL2
IOH2
IOL2
0.4
8
O2
O6
Output Current
mA
mA
V
Output Current
VDDQ Min
VOH6
VOL6
IOH6
IOL6
Output Voltage for DASP# pin
2.4
-4
IOH6=IOH6 Min
0.4
12
12
IOL6=IOL6 Max
Output Current for DASP# pin
Output Current for DASP# pin
Output Current for DASP# pin
Output Current for DASP# pin
mA
mA
mA
mA
VDDQ=2.7-3.465V
VDDQ=2.7-3.465V
VDDQ=4.5V-5.5V
VDDQ=4.5V-5.5V
IOH6
IOL6
-4
T19.1 1382
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
31
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 20: Power Consumption
Product
Symbol Type Parameter
Min Max Units Conditions
1,2
SST85LD0512-60-RI-LBTE IDD
PWR Power supply current
(TA = -40°C to +85°C)
130
1000
160
mA
VDD=VDD Max;
VDDQ=VDDQ Max
ISP
PWR Sleep/Standby/Idle current
(TA = -40°C to +85°C)
µA
VDD=VDD Max;
VDDQ=VDDQ Max
1,2
1,2
SST85LD1001T-60-RI-LBTE IDD
PWR Power supply current
(TA = -40°C to +85°C)
mA VDD=VDD Max;
VDDQ=VDDQ Max
ISP
SST85LD1002U-60-RI-LBTE IDD
ISP
PWR Sleep/Standby/Idle current
(TA = -40°C to +85°C)
1050
220
µA
V
DD=VDD Max;
VDDQ=VDDQ Max
mA VDD=VDD Max;
DDQ=VDDQ Max
PWR Power supply current
(TA = -40°C to +85°C)
V
PWR Sleep/Standby/Idle current
(TA = -40°C to +85°C)
1150
µA
VDD=VDD Max;
VDDQ=VDDQ Max
T20.2 1382
1. Sequential data transfer for 1 sector read data from host interface and write data to media.
2. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
AC Characteristics
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1319 F13.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’.
Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5
V
DD). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
Figure 4: AC Input/Output Reference Waveforms
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
32
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Appendix
Differences between the SST NANDrive and ATA-6 Specifications
Idle Timer
The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value
specified in ATA specifications.
Recovery from Sleep Mode
For NANDrive devices, recovery from sleep mode is accomplished by simply issuing another com-
mand to the device. A hardware or software reset is not required.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
33
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Product Ordering Information
SST 85 LD
1
001T
-
60
-
RI
-
LBTE
-
XX XX
X
XXXX
-
XX
-
XX
XXXX
Environmental Attribute
E1 = non-Pb
Package Modifier
T = 88 ball positions (nearest letter
code to total ball count of 91)
Package Type
LB = LBGA
Operation Temperature
I = Industrial: -40°C to +85°C
Endurance
R = 100,000,000 write cycles
minimum
Host Access Time
60 = 60ns - UDMA Mode - 4
Relative Performance Indicator
Higher letter indicates higher
performance
Capacity
512 = 512 MByte
001 = 1 GByte
002 = 2 GByte
MByte or GByte Designator
0 = MByte
1 = GByte
Voltage
L = 3.3V
Product Series
85 = NANDrive
1. Environmental suffix “E” denotes non-Pb sol-
der. SST non-Pb solder devices are “RoHS
Compliant”.
Valid Combinations
SST85LD0512-60-RI-LBTE
SST85LD1001T-60-RI-LBTE
SST85LD1002U-60-RI-LBTE
Note: Valid combinations are those products in mass production or will be in mass production. Consult
your SST sales representative to confirm availability of valid combinations and to determine
availability of new combinations.
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
34
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Packaging diagram
TOP VIEW
10
9
8
7
6
12.0
0.1
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A1
CORNER
24.0 0.1
BOTTOM VIEW
9.0
1.0
0.50
0.05
(91x)
10
9
8
7
6
5
7.0
4
3
2
1
1.0
N
T
R
P
M
L
K
J
H
G
F
E
D
C
B
A
A1
CORNER
SIDE VIEW
1mm
DETAIL
Note: 1. Although many dimensions are similar to those of JEDEC
Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
0.40 0.05
1.30
0.10
3. Coplanarity: 0.15 mm
4. Ball opening size is 0.40 mm ( 0.05 mm)
0.15
SEATING PLANE
91-lbga-LBT-12x24-1.0
Figure 5: mini-NANDrive 91-Ball Low Profile Ball Grid Array (LBGA)
SST Package Code: LBT
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
35
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Data Sheet
Table 21: Revision History
Number
Description
Date
00
Apr 2008
•
•
Initial release for SST85LD0512 / SST85LD1001T / SST85LD1002U Data
Sheet
01
Sep 2008
Added 5I (100M cycle endurance) information including updates in “Fea-
tures” , “General Description” , “Capacity Specification” , “Lifetime Expect-
ancy” , “Software Interface” “Electrical Specifications” , and “Product
Ordering Information” ,
•
•
•
Changes pin K2 from DMACK to DMACK# in Figure 2 and Table 1.
Preliminary Specifications-to-Data Sheet phase change
02
03
Nov 2008
Dec 2008
End-of-Life valid combinations SST85LD0512-60-5I-LBTE,
SST85LD1001T-60-5I-LBTE, and SST85LD1002U-60-5I-LBTE. See
S71382(02).
•
•
Removed all references to 100M cycle endurance in Features, page 1 and
Standard NANDrive on page 2 and page 12.
Removed SST85LD0512-60-5I-LBTE, SST85LD1001T-60-5I-LBTE, and
SST85LD1002U-60-5I-LBTE from Table 3 on page 9, Table 4 on page 9,
and Table 20 on page 32.
04
Oct 2009
•
•
Applied the new document format
Updated Figure 1.
© 2009 Silicon Storage Technology, Inc. All rights reserved.
SST and the SST logo are registered trademarks of Silicon Storage Technology, Inc.
Specifications are subject to change without notice. Refer to www.sst.com for the most recent data sheet versions.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale which are available on www.sst.com.
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2009 Silicon Storage Technology, Inc.
S71382-04-000
10/09
36
相关型号：
SST85LD1002U-60-RI-LBTE
IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91, 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91
MICROCHIP
SST85LD1004T-60-RI-LBTE
IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91, 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91
MICROCHIP
SST85LP1004A-M-C-LBTE
IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91, 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91
MICROCHIP
SST85LP1004A-M-W-LBTE
Flash Memory Drive, IDE Compatible, CMOS, PBGA91, 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91
MICROCHIP
SST85LP1004B-M-C-LFTE
IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91, 14 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, BGA-91
MICROCHIP
SST85LP1016B-M-C-FTE
IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91, 14 X 24 MM, 1.80 MM HEIGHT, ROHS COMPLIANT, BGA-91
MICROCHIP
©2020 ICPDF网 联系我们和版权申明