SST89V516RD2_技术文档

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

The SST89E516RDx and SST89V516RDx are members of the FlashFlex family

of 8-bit microcontroller products designed and manufactured with SST’s patented

and proprietary SuperFlash CMOS semiconductor process technology. The split-

gate cell design and thick-oxide tunneling injector offer significant cost and reli-

ability benefits for SST’s customers. The devices use the 8051 instruction set and

are pin-for-pin compatible with standard 8051 microcontroller devices.

Features

• 8-bit 8051-Compatible Microcontroller (MCU) with

Embedded SuperFlash Memory

• Programmable Watchdog Timer (WDT)

• Programmable Counter Array (PCA)

– Fully Software Compatible

– Development Toolset Compatible

– Pin-For-Pin Package Compatible

• Four 8-bit I/O Ports (32 I/O Pins) and

One 4-bit Port

• SST89E516RD2 Operation

• Second DPTR register

• Low EMI Mode (Inhibit ALE)

• SPI Serial Interface

– 0 to 40 MHz at 5V

• SST89V516RD2 Operation

– 0 to 33 MHz at 3V

• 1 KByte Internal RAM

• Standard 12 Clocks per cycle, the device has an

option to double the speed to 6 clocks per cycle.

• Dual Block SuperFlash EEPROM

– 64 KByte primary block +

• TTL- and CMOS-Compatible Logic Levels

• Brown-out Detection

8 KByte secondary block

(128-Byte sector size for both blocks)

– Individual Block Security Lock with SoftLock

– Concurrent Operation during

In-Application Programming (IAP)

– Memory Overlay for Interrupt Support during IAP

• Low Power Modes

– Power-down Mode with External Interrupt Wake-up

– Idle Mode

• Support External Address Range up to 64 KByte

of Program and Data Memory

• Temperature Ranges:

– Commercial (0°C to +70°C)

– Industrial (-40°C to +85°C)

• Three High-Current Drive Ports (16 mA each)

• Three 16-bit Timers/Counters

• Packages Available

– 40-contact WQFN (Port 4 feature not available)

– 44-lead PLCC

– 40-pin PDIP (Port 4 feature not available)

– 44-lead TQFP

• Full-Duplex, Enhanced UART

– Framing Error Detection

– Automatic Address Recognition

• All non-Pb (lead-free) devices are RoHS compliant

• Ten Interrupt Sources at 4 Priority Levels

– Four External Interrupt Inputs

www.microchip.com

DS25093B

02/13

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Product Description

The SST89E516RDx and SST89V516RDx are members of the FlashFlex family of 8-bit microcon-

troller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS

semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer

significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set

and are pin-for-pin compatible with standard 8051 microcontroller devices.

The devices come with 72 KByte of on-chip flash EEPROM program memory which is partitioned into

2 independent program memory blocks. The primary Block 0 occupies 64 KByte of internal program

memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.

The 8-KByte secondary block can be mapped to the lowest location of the 64 KByte address space; it

can also be hidden from the program counter and used as an independent EEPROM-like data mem-

ory.

In addition to the 72 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM,

the devices can address up to 64 KByte of external program memory and up to 64 KByte of external

RAM.

The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted

with a special adapter and the firmware for SST’s devices. During power-on reset, the devices can be

configured as either a slave to an external host for source code storage or a master to an external host

for an in-application programming (IAP) operation. The devices are designed to be programmed in-

system and in-application on the printed circuit board for maximum flexibility. The devices are pre-pro-

grammed with an example of the bootstrap loader in the memory, demonstrating the initial user pro-

gram code loading or subsequent user code updating via the IAP operation. The sample bootstrap

loader is available for the user’s reference and convenience only; SST does not guarantee its function-

ality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.

DS25093B

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2

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Functional Blocks

8051

CPU Core

ALU,

ACC,

B-Register,

Instruction Register,

Program Counter,

Timing and Control

Interrupt

Control

Oscillator

10 Interrupts

Flash Control Unit

Watchdog Timer

SuperFlash

EEPROM

Primary

Block

RAM

1K x8

64K x8

8

I/O

I/O Port 0

Secondary

Block

8K x8

Security

Lock

I/O Port 1

I/O Port 2

I/O Port 3

8

4

Timer 0 (16-bit)

Timer 1 (16-bit)

Timer 2 (16-bit)

PCA

I/O

I/O Port 4

SPI

Enhanced

UART

1273 B1.0

Figure 1: Functional Block Diagram

DS25093B

02/13

3

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Pin Assignments

40

1

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

(RXD) P3.0

EA#

Top View

(contacts facing down)

(TXD) P3.1

ALE/PROG#

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

PSEN#

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(T1) P3.5

1273 40-wqfn QI P1.0

Figure 2: Pin Assignments for 40-Contact WQFN

DS25093B

02/13

4

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V

DD

(T2) P1.0

(T2 EX) P1.1

(ECI) P1.2

1

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

2

3

(CEX0) P1.3

(CEX1 / SS#) P1.4

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

4

5

6

7

40-pin PDIP

Top View

8

9

(RXD) P3.0

10

11

12

13

14

15

16

17

18

19

20

ALE/PROG#

PSEN#

(TXD) P3.1

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

(T1) P3.5

(WR#) P3.6

(RD#) P3.7

XTAL2

XTAL1

V

SS

1273 40-pdip PI P2.0

Figure 3: Pin Assignments for 40-pin PDIP

DS25093B

02/13

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FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

44 43 42 41 40 39 38 37 36 35 34

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

1

33

32

31

30

29

28

27

26

25

24

23

2

3

4

(RXD) P3.0

5

44-lead TQFP

Top View

INT2#/P4.3

P4.1

6

(TXD) P3.1

ALE/PROG#

PSEN#

7

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

8

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

9

10

11

(T1) P3.5

12 13 14 15 16 17 18 19 20 21 22

1273 44-tqfp TQJ P3.0

Figure 4: Pin Assignments for 44-lead TQFP

DS25093B

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FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

6

5

4

3

2

1

44 43 42 41 40

39

7

(CEX2 / MOSI) P1.5

(CEX3 / MISO) P1.6

(CEX4 / SCK) P1.7

RST

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA#

8

38

37

36

35

34

33

32

31

30

29

9

10

11

12

13

14

15

16

17

(RXD) P3.0

44-lead PLCC

Top View

INT2#/P4.3

P4.1

(TXD) P3.1

ALE/PROG#

PSEN#

(INT0#) P3.2

(INT1#) P3.3

(T0) P3.4

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(T1) P3.5

18 19 20 21 22 23 24 25 26 27 28

1273 44-plcc NJ P4.0

Figure 5: Pin Assignments for 44-lead PLCC

DS25093B

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7

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Pin Descriptions

Table 1: Pin Descriptions (1 of 3)

Symbol

Type¹

Name and Functions

P0[7:0]

I/O

Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each

pin can sink several LS TTL inputs. Port 0 pins float that have ‘1’s written to them,

and in this state can be used as high-impedance inputs. Port 0 is also the multi-

plexed low-order address and data bus during accesses to external memory. In

this application, it uses strong internal pull-ups when transitioning to V_OH.Port 0

also receives the code bytes during the external host mode programming, and

outputs the code bytes during the external host mode verification. External pull-

ups are required during program verification.

P1[7:0]

I/O with inter- Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1

nal pull-ups

output buffers can drive LS TTL inputs. Port 1 pins are pulled high by the internal

pull-ups when “1”s are written to them and can be used as inputs in this state. As

inputs, Port 1 pins that are externally pulled low will source current because of the

internal pull-ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives

the low-order address bytes during the external host mode programming and ver-

ification.

P1[0]

P1[1]

P1[2]

I/O

T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2

T2EX: Timer/Counter 2 capture/reload trigger and direction control

I

ECI: PCA Timer/Counter External Input:

This signal is the external clock input for the PCA timer/counter.

P1[3]

P1[4]

P1[5]

P1[6]

P1[7]

P2[7:0]

I/O

CEX0: Compare/Capture Module External I/O

Each compare/capture module connects to a Port 1 pin for external I/O. When not

used by the PCA, this pin can handle standard I/O.

SS#: Master Input or Slave Output for SPI.

OR

CEX1: Compare/Capture Module External I/O

MOSI: Master Output line, Slave Input line for SPI

OR

CEX2: Compare/Capture Module External I/O

MISO: Master Input line, Slave Output line for SPI

OR

CEX3: Compare/Capture Module External I/O

SCK: Master clock output, slave clock input line for SPI

OR

CEX4: Compare/Capture Module External I/O

I/O with inter- Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins

nal pull-up

are pulled high by the internal pull-ups when “1”s are written to them and can be

used as inputs in this state. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 sends the high-order

address byte during fetches from external Program memory and during accesses

to external Data Memory that use 16-bit address (MOVX@DPTR). In this applica-

tion, it uses strong internal pull-ups when transitioning to V_OH. Port 2 also receives

some control signals and high-order address bits during the external host mode

programming and verification.

DS25093B

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8

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 1: Pin Descriptions (Continued) (2 of 3)

Symbol

Type¹

Name and Functions

P3[7:0]

I/O with inter- Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3

nal pull-up

output buffers can drive LS TTL inputs. Port 3 pins are pulled high by the internal

pull-ups when “1”s are written to them and can be used as inputs in this state. As

inputs, Port 3 pins that are externally pulled low will source current because of the

internal pull-ups. Port 3 also receives some control signals and a partial of high-

order address bits during the external host mode programming and verification.

P3[0]

P3[1]

P3[2]

P3[3]

P3[4]

P3[5]

P3[6]

P3[7]

PSEN#

I

O

I

RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input

TXD: UART - Transmit output

INT0#: External Interrupt 0 Input

I

INT1#: External Interrupt 1 Input

I

T0: External count input to Timer/Counter 0

T1: External count input to Timer/Counter 1

WR#: External Data Memory Write strobe

RD#: External Data Memory Read strobe

I

O

I/O

Program Store Enable: PSEN# is the Read strobe to External Program Store.

When the device is executing from Internal Program Memory, PSEN# is inactive

(V_OH). When the device is executing code from External Program Memory,

PSEN# is activated twice each machine cycle, except when access to External

Data Memory while one PSEN# activation is skipped in each machine cycle. A

forced high-to-low input transition on the PSEN# pin while the RST input is contin-

ually held high for more than ten machine cycles will cause the device to enter

External Host mode for programming.

RST

EA#

I

Reset: While the oscillator is running, a high logic state on this pin for two

machine cycles will reset the device. After a reset, if the PSEN# pin is driven by a

high-to-low input transition while the RST input pin is held high, the device will

enter the External Host mode, otherwise the device will enter the Normal opera-

tion mode.

External Access Enable: EA# must be driven to V_ILin order to enable the device

to fetch code from the External Program Memory. EA# must be driven to V_IHfor

internal program execution. However, Security lock level 4 will disable EA#, and

program execution is only possible from internal program memory. The EA# pin

can tolerate a high voltage²of 12V.

ALE/

PROG#

I/O

Address Latch Enable: ALE is the output signal for latching the low byte of the

address during an access to external memory. This pin is also the programming

pulse input (PROG#) for flash programming. Normally the ALE³is emitted at a

constant rate of 1/6 the crystal frequency⁴and can be used for external timing and

clocking. One ALE pulse is skipped during each access to external data memory.

However, if AO is set to 1, ALE is disabled.

P4[3:0]⁵

I/O with inter- Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. The port 4

nal pull-ups

output buffers can drive LS TTL inputs. Port 4 pins are pulled high by the internal

pull-ups when ‘1’s are written to them and can be used as inputs in this state. As

inputs, port 4 pins that are externally pulled low will source current because of the

internal pull-ups.

P4[0]

P4[1]

I/O

Bit 0 of port 4

Bit 1 of port 4

P4[2] /

INT3#

Bit 2 of port 4 / INT3# External interrupt 3 input

DS25093B

02/13

9

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 1: Pin Descriptions (Continued) (3 of 3)

Symbol

Type¹

Name and Functions

P4[3] /

INT2#

I/O

Bit 3 of port 4 / INT2# External interrupt 2 input

XTAL1

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock

generator circuits.

XTAL2

V_DD

O

I

Crystal 2: Output from the inverting oscillator amplifier

Power Supply

V_SS

I

Ground

T0-0.0 25093

1. I = Input; O = Output

2. It is not necessary to receive a 12V programming supply voltage during flash programming.

3.ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter

into modes other than normal working mode. The solution is to add a pull-up resistor of 3-50 KΩ to V_DD, e.g. for ALE

pin.

4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency.

5. Port 4 is not present on the PDIP and WQFN packages.

DS25093B

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10

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Memory Organization

The device has separate address spaces for program and data memory.

Program Flash Memory

There are two internal flash memory blocks in the device. The primary flash memory block (Block 0)

has 64 KByte. The secondary flash memory block (Block 1) has 8 KByte. Since the total program

address space is limited to 64 KByte, the SFCF[1:0] bit are used to control program bank selection.

Please refer to Figure 6 for the program memory configuration. Program bank selection is described in

the next section.

The 64K x8 primary SuperFlash block is organized as 512 sectors, each sector consists of 128 Bytes.

The 8K x8 secondary SuperFlash block is organized as 64 sectors, each sector consists also of 128

Bytes.

For both blocks, the 7 least significant program address bits select the byte within the sector. The

remainder of the program address bits select the sector within the block.

EA# = 1

SFCF[1:0] = 00

SFCF[1:0] = 01, 10, 11

EA# = 0

FFFFH

External

64 KByte

56 KByte

Block 0

64 KByte

Block 0

2000H

1FFFH

8 KByte

Block 1

0000H

1273 F01.0

Figure 6: Program Memory Organization

DS25093B

02/13

11

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Program Memory Block Switching

The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of

Block 0 to be used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program

memory block switching.

Table 2: SFCF Values for Program Memory Block Switching

SFCF[1:0] Program Memory Block Switching

01, 10, 11 Block 1 is not visible to the program counter (PC).

Block 1 is reachable only via in-application programming from 0000H - 1FFFH.

00

Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H -

1FFFH.

When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0.

Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through

in-application programming.

T0-0.0 25093

Reset Configuration of Program Memory Block Switching

Program memory block switching is initialized after reset according to the state of the Start-up Config-

uration bit SC0. The SC0 bit is programmed via an external host mode command or an IAP Mode com-

mand. See Table 14.

Once out of reset, the SFCF[0] bit can be changed dynamically by the program for desired effects.

Changing SFCF[0] will not change the SC0 bit.

Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different

physical memory to be mapped to the logical program address space. The user must avoid executing

block switching instructions within the address range 0000H to 1FFFH.

Table 3: SFCF Values Under Different Reset Conditions

State of SFCF[1:0] after:

Power-on

or

WDT Reset

or

External

Reset

Brown-out

Reset

Software

Reset

SC0¹

U (1)

00

x0

10

(default)

P (0)

01

x1

11

T0-0.0 25093

1. P = Programmed (Bit logic state = 0),

U = Unprogrammed (Bit logic state = 1)

Data RAM Memory

The data RAM has 1024 bytes of internal memory. The RAM can be addressed up to 64KB for external

data memory.

DS25093B

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12

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Expanded Data RAM Addressing

The SST89E/V516RDx have the capability of 1 KByte RAM. See Figure 7.

The device has four sections of internal data memory:

1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.

2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.

3. The special function registers (80H to FFH) are directly addressable only.

4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move

external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register

(AUXR)” in Section , “Special Function Registers”)

Since the upper 128 Bytes occupy the same addresses as the SFRs, the RAM must be accessed indi-

rectly. The RAM and SFRs space are physically separate even though they have the same addresses.

When instructions access addresses in the upper 128 Bytes (above 7FH), the MCU determines

whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is

accessed. If it is direct, then an SFR is accessed. See the examples below.

Indirect Access:

MOV@R0, #data; R0 contains 90H

Register R0 points to 90H which is located in the upper address range. Data in “#data” is written to

RAM location 90H rather than port 1.

Direct Access:

MOV90H, #data; write data to P1

Data in “#data” is written to port 1. Instructions that write directly to the address write to the SFRs.

To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used.

The extra 768 bytes of memory is physically located on the chip and logically occupies the first 768

bytes of external memory (addresses 000H to 2FFH).

When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combi-

nation with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM

does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can

be accessed as in the following example.

Expanded RAM Access (Indirect Addressing only):

MOVX@DPTR, A; DPTR contains 0A0H

DPTR points to 0A0H and data in “A” is written to address 0A0H of the expanded RAM rather than

external memory. Access to external memory higher than 2FFH using the MOVX instruction will

access external memory (0300H to FFFFH) and will perform in the same way as the standard 8051,

with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals.

When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using

MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output port pins can be

used to output higher order address bits. This provides external paging capabilities. Using MOVX

@DPTR generates a 16-bit address. This allows external addressing up the 64K. Port 2 provides the

DS25093B

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13

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with

data. Both MOVX @Ri and MOVX @DPTR generates the necessary read and write signals (P3.6 -

WR# and P3.7 - RD#) for external memory use. Table 4 shows external data memory RD#, WR# oper-

ation with EXTRAM bit.

The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 128 bytes

and upper 128 bytes). The stack pointer may not be located in any part of the expanded RAM.

Table 4: External Data Memory RD#, WR# with EXTRAM bit

MOVX @DPTR, A or MOVX A, @DPTR

MOVX @Ri, A or MOVX A, @Ri

ADDR = Any

AUXR

ADDR < 0300H

RD# / WR# not asserted

RD# / WR# asserted

ADDR >= 0300H

RD# / WR# asserted

EXTRAM = 0

EXTRAM = 1

RD# / WR# not asserted¹

RD# / WR# asserted

T0-0.0 25093

1. Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.

DS25093B

02/13

14

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

2FFH

FFH

Expanded

RAM

(Indirect Addressing)

(Direct Addressing)

768 Bytes

Special

Function

Registers

(SFRs)

Upper 128 Bytes

Internal RAM

80H

7FH

80H

Lower 128 Bytes

Internal RAM

(Indirect & Direct

Addressing)

(Indirect Addressing)

00H

000H

FFFFH

(Indirect Addressing)

External

Data

Memory

External

Data

Memory

0300H

2FFH

Expanded RAM

000H

0000H

EXTRAM = 0

EXTRAM = 1

1273 F02.0

Figure 7: Internal and External Data Memory Structure

DS25093B

02/13

15

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Dual Data Pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of

the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is

selected. Quickly switching between the two data pointers can be accomplished by a single INC

instruction on AUXR1. (See Figure 8)

AUXR1 / bit0

DPS

DPTR1

DPTR0

DPS = 0 → DPTR0

DPS = 1 → DPTR1

DPL

82H

DPH

83H

External Data Memory

1273 F03.0

Figure 8: Dual Data Pointer Organization

Special Function Registers

Most of the unique features of the FlashFlex microcontroller family are controlled by bits in special

function registers (SFRs) located in the SFR memory map shown in Table 5. Individual descriptions of

each SFR are provided and reset values indicated in Tables 6 to 10.

Table 5: FlashFlex SFR Memory Map

8 BYTES

F8H

F0H

E8H

E0H

D8H

D0H

C8H

C0H

B8H

B0H

A8H

A0H

98H

90H

88H

80H

IP1¹

B¹

IEA¹

CH

CL

CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H

CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L

FFH

F7H

EFH

E7H

DFH

D7H

CFH

C7H

BFH

B7H

AFH

A7H

9FH

97H

8FH

IP1H

ACC¹

CCON¹

PSW¹

CMOD

CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4

SPCR

T2CON¹T2MOD RCAP2L RCAP2H

WDTC¹

IP¹

P3¹

IE¹

P2¹

SCON¹

P1¹

TCON¹

P0¹

TL2

TH2

SADEN

SFCF

SFCM

SPSR

SFAL

SFAH

SFDT

P4

SFST

IPH

SADDR

XICON

AUXR1

SBUF

TMOD

SP

TL0

TL1

TH0

TH1

AUXR

SPDR

DPL

DPH

WDTD

PCON

87H

T0-0.0 25093

1. Bit addressable SFRs

DS25093B

02/13

16

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 6: CPU related SFRs

Bit Address, Symbol, or Alternative Port Function

Reset

Direct

Symbol Description

ACC¹Accumulator

Address MSB

LSB

Value

00H

E0H

F0H

D0H

ACC[7:0]

B[7:0]

B¹

B Register

PSW¹Program Sta-

CY

AC

F0

RS RS0

1

OV

F1

P

tus

Word

SP

Stack Pointer

81H

82H

SP[7:0]

07H

00H

DPL

Data Pointer

Low

DPL[7:0]

DPH

IE¹

Data Pointer

High

83H

A8H

E8H

B8H

DPH[7:0]

00H

Interrupt

Enable

EA

EC

-

ET2 ES

ET1

EBO

PT1

EX1

-

ET0

-

EX0

-

IEA¹

IP¹

Interrupt

Enable A

-

xxxx0xxx

b

Interrupt Prior-

ity

PPC

PT2 PS

PX1

PT0

PX0 x0000000

b

Reg

IPH

Interrupt Prior-

ity

Reg High

B7H

F8H

F7H

-

PPCH PT2 PS PT1H PX1

PT0H

PX2

PX0 x0000000

H

b

IP1¹

IP1H

Interrupt Prior-

ity

Reg A

-

PBO PX3

-

xxxx0xxx

b

Interrupt Prior-

ity

Reg A High

-

PBO PX3

PX2H

PD

-

xxxx0xxx

b

H

PCON Power Control

87H

8EH

A2H

AEH

SMOD SMOD BOF PO GF1 GF0

IDL 00010000

b

1

0

F

AUXR Auxiliary Reg

-

GF2

0

-

0

EXTRA

M

AO

xxxxxxx0

0b

AUXR1 Auxiliary Reg

1

-

DPS xxxx00x0

b

XICON External

Interrupt Con-

trol

EX3

IE3 IT3

EX2

IE2

IT2

00H

T0-0.0 25093

1. Bit Addressable SFRs

DS25093B

02/13

17

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 7: Flash Memory Programming SFRs

Bit Address, Symbol, or Alternative Port Function

Direct

Address MSB

Reset

Value

Symbol Description

LSB

SFCF SuperFlash

Configuration

B1H

B2H

B3H

B4H

B5H

B6H

-

IAPE

N

-

SW BSE x0xxxx00

R

L

b

SFCM SuperFlash

Command

FIE

FCM[6:0]

00H

SFAL

SuperFlash

SuperFlash Low Order Byte Address Register - A₇to A₀(SFAL)

00H

Address Low

SFAH SuperFlash

Address High

SuperFlash High Order Byte Address Register - A₁₅to A₈

(SFAH)

SFDT SuperFlash

Data

SuperFlash Data Register

SFST SuperFlash

Status

SB1 SB2_ SB3

_i _i

-

EDC_i FLASH_BU

SY

-

000x00xx

b

i

T0-0.0 25093

Table 8: Watchdog Timer SFRs

Bit Address, Symbol, or Alternative Port Function

Address MSB

Direct

Reset

Value

Symbol Description

LSB

WDTC Watchdog

C0H

-

WDOUT WDRE WDTS WDT SWDT xxx00x00

b

1

Timer

Control

WDTD Watchdog

Timer

85H

Watchdog Timer Data/Reload

00H

Data/Reload

T0-0.0 25093

1. Bit Addressable SFRs

DS25093B

02/13

18

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 9: Timer/Counters SFRs

Bit Address, Symbol, or Alternative Port Function

Direct

Reset

Value

Symbol Description

Address MSB

LSB

TMOD Timer/Counter

Mode Control

89H

Timer 1

Timer 0

00H

GAT C/T# M1

M0

GATE

IE1

C/

M1

M0

E

T#

TCON¹Timer/Counter

Control

88H

TF1

TR1 TF0

TR0

IT1

IE0

IT0

00H

TH0

TL0

TH1

TL1

Timer 0 MSB

Timer 0 LSB

Timer 1 MSB

Timer 1 LSB

8CH

8AH

8DH

8BH

C8H

TH0[7:0]

TL0[7:0]

TH1[7:0]

TL1[7:0]

00H

T2CON Timer / Coun-

TF2 EXF RCL TCL EXEN TR2

C/

T2#

CP/

RL2#

1

ter 2

2

K

2

Control

T2MOD Timer2

Mode Control

C9H

-

T2O

E

DCEN

xxxxxx00

b

TH2

TL2

Timer 2 MSB

Timer 2 LSB

CDH

CCH

CBH

TH2[7:0]

TL2[7:0]

00H

RCAP2 Timer 2

RCAP2H[7:0]

H

Capture MSB

RCAP2 Timer 2

CAH

RCAP2L[7:0]

00H

L

Capture LSB

T0-0.0 25093

1. Bit Addressable SFRs

DS25093B

02/13

19

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 10: Interface SFRs

Bit Address, Symbol, or Alternative Port Function

Direct

RESET

Symbol Description

Address MSB

LSB Value

SBUF Serial Data Buf-

fer

99H

SBUF[7:0]

SM1 SM2 REN TB8 RB8

SADDR[7:0]

Indetermi-

nate

SCON Serial Port Con-

98H

A9H

B9H

D5H

AAH

86H

SM0/

FE

TI

RI

00H

1

trol

SADD Slave Address

R

00H

04H

00H

SADE Slave Address

SADEN[7:0]

N

Mask

SPCR SPI Control

Register

SPIE

SPE DOR MST CPO CPH SPR SPR

D

R

L

A

1

0

SPSR SPI Status

Register

SPIF WCO

L

SPDR SPI Data Regis-

ter

SPDR[7:0]

P0[7:0]

P0¹

P1¹

Port 0

Port 1

80H

90H

FFH

-

T2E

X

T2

P2¹

P3¹

Port 2

Port 3

A0H

B0H

P2[7:0]

FFH

RD#

1

WR#

1

T1

1

T0

INT1 INT0 TXD RXD

#

P4²

Port 4

A5H

1

P4.3 P4.2 P4.1 P4.0

FFH

T0-0.0 25093

1. Bit Addressable SFRs

2. P4 is similar to P1 and P3 ports

DS25093B

02/13

20

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 11: PCA SFRs

Bit Address, Symbol, or Alternative Port Function

RESET

Direct

Symbol Description

Address MSB

LSB

Value

00H

PCA Timer/Coun-

ter

CH

CL

F9H

E9H

CH[7:0]

CL[7:0]

CCON¹

D8H

CF

CR

-

CCF4 CCF CCF CCF CCF0 00x0000

PCA Timer/Coun-

ter

Control Register

3

2

1

0b

PCA Timer/Coun-

ter

Mode Register

CMOD

D9H

CID WDTE

L

-

CPS CPS

ECF 00xxx000

b

1

0

CCAP0 PCA Module 0

FAH

EAH

FBH

EBH

FCH

ECH

FDH

EDH

FEH

EEH

DAH

DBH

DCH

DDH

DEH

CCAP0H[7:0]

CCAP0L[7:0]

CCAP1H[7:0]

CCAP1L[7:0]

CCAP2H[7:0]

CCAP2L[7:0]

CCAP3H[7:0]

CCAP3L[7:0]

CCAP4H[7:0]

CCAP4L[7:0]

00H

H

Compare/Cap-

ture

Registers

CCAP0

L

CCAP1 PCA Module 1

H

Compare/Cap-

ture

Registers

CCAP1

L

CCAP2 PCA Module 2

H

Compare/Cap-

ture

Registers

CCAP2

L

CCAP3 PCA Module 3

H

Compare/Cap-

ture

Registers

CCAP3

L

CCAP4 PCA Module 4

H

Compare/Cap-

ture

Registers

CCAP4

L

CCAPM PCA

-

ECOM CAPP CAPN MAT TOG PWM ECCF x000000

0b

ECOM CAPP CAPN MAT TOG PWM ECCF x000000

0b

ECOM CAPP CAPN MAT TOG PWM ECCF x000000

0b

ECOM CAPP CAPN MAT TOG PWM ECCF x000000

0b

ECOM CAPP CAPN MAT TOG PWM ECCF x000000

0

Compare/Cap-

0

ture

Module Mode

Registers

CCAPM

1

CCAPM

2

CCAPM

3

CCAPM

4

0b

T0-0.0 25093

1. Bit Addressable SFRs

DS25093B

02/13

21

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

SuperFlash Configuration Register (SFCF)

Location

7

6

5

4

3

2

1

0

Reset Value

B1H

-

IAPEN

-

SWR

BSEL

x0xxxx00b

Symbol Function

IAPEN Enable IAP operation

0: IAP commands are disabled

1: IAP commands are enabled

SWR

BSEL

Software Reset

See Section , “Software Reset”

Program memory block switching bit

See Figure 6 and Table 3

SuperFlash Command Register (SFCM)

Location

7

6

5

4

3

2

1

0

Reset Value

B2H

FIE

FCM6

FCM5

FCM4

FCM3

FCM2

FCM1

FCM0

00H

Symbol Function

FIE

Flash Interrupt Enable.

0: INT1# is not reassigned.

1: INT1# is re-assigned to signal IAP operation completion.

External INT1# interrupts are ignored.

FCM[6:0] Flash operation command

000_0001b Chip-Erase

000_1011b Sector-Erase

000_1101b Block-Erase

000_1100b Byte-Verify¹

000_1110b Byte-Program

000_1111b Prog-SB1

000_0011b Prog-SB2

000_0101b Prog-SB3

000_1001b Prog-SC0

000_1000bEnable-Clock-Double

All other combinations are not implemented, and reserved for future use.

1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.

SuperFlash Address Registers (SFAL)

Location

7

6

5

4

3

2

1

0

Reset Value

B3H

SuperFlash Low Order Byte Address Register

00H

Symbol Function

SFAL

Mailbox register for interfacing with flash memory block. (Low order address register).

DS25093B

02/13

22

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

SuperFlash Address Registers (SFAH)

Location

7

6

5

4

3

2

1

0

Reset Value

B4H

SuperFlash High Order Byte Address Register

00H

Symbol Function

SFAH Mailbox register for interfacing with flash memory block. (High order address register).

SuperFlash Data Register (SFDT)

Location

7

6

5

4

3

2

1

0

Reset Value

B5H

SuperFlash Data Register

00H

Symbol Function

SFDT Mailbox register for interfacing with flash memory block. (Data register).

SuperFlash Status Register (SFST) (Read Only Register)

Location

7

6

5

4

3

2

1

0

Reset Value

FLASH_BU

SY

B6H

SB1_i

SB2_i

SB3_i

-

EDC_i

-

xxxxx0xxb

Symbol Function

SB1_i

SB2_i

SB3_i

Security Bit 1 status (inverse of SB1 bit)

Security Bit 2 status (inverse of SB2 bit)

Security Bit 3 status (inverse of SB3 bit)

Please refer to Table 25 for security lock options.

EDC_i

Double Clock Status

0: 12 clocks per machine cycle

1: 6 clocks per machine cycle

FLASH_BUSYFlash operation completion polling bit.

0: Device has fully completed the last IAP command.

1: Device is busy with flash operation.

DS25093B

02/13

23

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Interrupt Enable (IE)

Location

A8H

7

6

5

4

3

2

1

0

Reset Value

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

00H

Symbol Function

EA

Global Interrupt Enable.

0 = Disable

1 = Enable

EC

PCA Interrupt Enable.

ET2

ES

Timer 2 Interrupt Enable.

Serial Interrupt Enable.

Timer 1 Interrupt Enable.

External 1 Interrupt Enable.

Timer 0 Interrupt Enable.

External 0 Interrupt Enable.

ET1

EX1

ET0

EX0

Interrupt Enable A (IEA)

Location

7

6

5

4

3

2

1

0

Reset Value

E8H

-

EBO

-

xxxx0xxxb

Symbol Function

EBO

Brown-out Interrupt Enable.

1 = Enable the interrupt

0 = Disable the interrupt

DS25093B

02/13

24

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Interrupt Priority (IP)

Location

B8H

7

6

5

4

3

2

1

0

Reset Value

-

PPC

PT2

PS

PT1

PX1

PT0

PX0

x0000000b

Symbol Function

PPC

PT2

PS

PCA interrupt priority bit

Timer 2 interrupt priority bit

Serial Port interrupt priority bit

Timer 1 interrupt priority bit

External interrupt 1 priority bit

Timer 0 interrupt priority bit

External interrupt 0 priority bit

PT1

PX1

PT0

PX0

Interrupt Priority High (IPH)

Location

7

6

5

4

3

2

1

0

Reset Value

B7H

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

x0000000b

Symbol Function

PPCH

PT2H

PSH

PCA interrupt priority bit high

Timer 2 interrupt priority bit high

Serial Port interrupt priority bit high

Timer 1 interrupt priority bit high

External interrupt 1 priority bit high

Timer 0 interrupt priority bit high

External interrupt 0 priority bit high

PT1H

PX1H

PT0H

PX0H

Interrupt Priority 1 (IP1)

Location

7

6

5

4

3

2

1

0

Reset Value

F8H

1

-

1

PBO

PX3

PX2

1

1xx10001b

Symbol Function

PBO

PX2

PX3

Brown-out interrupt priority bit

External Interrupt 2 priority bit

External Interrupt 3 priority bit

Interrupt Priority 1 High (IP1H)

Location

7

6

5

4

3

2

1

0

Reset Value

F7H

1

-

1

PBOH

PX3H

PX2H

1

1xx10001b

Symbol Function

PBOH Brown-out Interrupt priority bit high

PX2H

PX3H

External Interrupt 2 priority bit high

External Interrupt 3 priority bit high

DS25093B

02/13

25

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Auxiliary Register (AUXR)

Location

7

6

5

4

3

2

1

0

Reset Value

8EH

-

EXTRA

M

AO

xxxxxx00b

Symbol Function

EXTRAMInternal/External RAM access

0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri / @DPTR.

Beyond 300H, the MCU always accesses external data memory.

For details, refer to Section , “Expanded Data RAM Addressing” .

1: External data memory access.

AO

Disable/Enable ALE

0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 f_OSCin 12

clock mode.

1: ALE is active only during a MOVX or MOVC instruction.

Auxiliary Register 1 (AUXR1)

Location

7

6

5

4

3

2

1

0

Reset Value

A2H

-

GF2

0

-

DPS

xxxx00x0b

Symbol Function

GF2

DPS

General purpose user-defined flag.

DPTR registers select bit.

0: DPTR0 is selected.

1: DPTR1 is selected.

Watchdog Timer Control Register (WDTC)

Location

7

6

5

4

3

2

1

0

Reset Value

C0H

-

WDOUT WDRE

WDTS

WDT

SWDT xxx00000b

Symbol Function

WDOUT Watchdog output enable.

0: Watchdog reset will not be exported on Reset pin.

1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.

WDRE Watchdog timer reset enable.

0: Disable watchdog timer reset.

1: Enable watchdog timer reset.

WDTS Watchdog timer reset flag.

0: External hardware reset or power-on reset clears the flag.

Flag can also be cleared by writing a 1.

Flag survives if chip reset happened because of watchdog timer overflow.

1: Hardware sets the flag on watchdog overflow.

WDT

Watchdog timer refresh.

0: Hardware resets the bit when refresh is done.

1: Software sets the bit to force a watchdog timer refresh.

SWDT Start watchdog timer.

0: Stop WDT.

1: Start WDT.

DS25093B

02/13

26

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Watchdog Timer Data/Reload Register (WDTD)

Location

7

6

5

4

3

2

1

0

Reset Value

85H

Watchdog Timer Data/Reload

00H

Symbol Function

WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.

PCA Timer/Counter Control Register¹(CCON)

Location

D8H

7

6

5

4

3

2

1

0

Reset Value

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

00x00000b

1. Bit addressable

Symbol Function

CF

PCA Counter Overflow Flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set.

CF may be set by either hardware or software, but can only cleared by software.

CR

PCA Counter Run control bit

Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA

counter off.

-

Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

CCF4

CCF3

CCF2

CCF1

CCF0

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

DS25093B

02/13

27

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

PCA Timer/Counter Mode Register¹(CMOD)

Location

7

6

5

4

3

2

1

0

Reset Value

D9H

CIDL

WDTE

-

CPS1

CPS0

ECF

00xxx000b

1. Not bit addressable

Symbol Function

CIDL Counter Idle Control:

0: Programs the PCA Counter to continue functioning during idle mode

1: Programs the PCA Counter to be gated off during idle

WDTE Watchdog Timer Enable:

0: Disables Watchdog Timer function on PCA module 4

1: Enables Watchdog Timer function on PCA module 4

-

Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

PCA Count Pulse Select bit 1

CPS1

CPS0

PCA Count Pulse Select bit 2

Selected

CPS1 CPS0 PCA Input¹

Internal clock, f_OSC/6 in 6 clock mode (f_OSC/12 in 12 clock mode)

Internal clock, f_OSC/2 in 6 clock mode (f_OSC/4 in 12 clock mode)

Timer 0 overflow

0

1

0

1

0

1

0

1

2

3

External clock at ECI/P1.2 pin

(max. rate = f_OSC/4 in 6 clock mode, f_OSC/8 in 12 clock mode)

1. f_OSC= oscillator frequency

ECF

PCA Enable Counter Overflow interrupt:

0: Disables the CF bit in CCON

1: Enables CF bit in CCON to generate an interrupt

DS25093B

02/13

28

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

PCA Compare/Capture Module Mode Register¹(CCAPMn)

Location

DAH

7

-

6

5

4

3

2

1

0

Reset Value

ECOM0 CAPP0

ECOM1 CAPP1

ECOM2 CAPP2

ECOM3 CAPP3

ECOM4 CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0 00xxx000b

ECCF1 00xxx000b

ECCF2 00xxx000b

ECCF3 00xxx000b

ECCF4 00xxx000b

DBH

-

DCH

-

DDH

-

DEH

-

1. Not bit addressable

Symbol Function

Not implemented, reserved for future use.

-

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

ECOMn Enable Comparator

0: Disables the comparator function

1: Enables the comparator function

CAPPn Capture Positive

0: Disables positive edge capture on CEX[4:0]

1: Enables positive edge capture on CEX[4:0]

CAPNn Capture Negative

0: Disables negative edge capture on CEX[4:0]

1: Enables negative edge capture on CEX[4:0]

MATn

TOGn

Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode

0: Disables software timer mode

1: A match of the PCA counter with this module’s compare/capture register causes the

CCFn bit in CCON to be set, flagging an interrupt.

Toggle

0: Disables toggle function

1: A match of the PCA counter with this module’s compare/capture register causes the

CEXn pin to toggle.

PWMn Pulse Width Modulation mode

0: Disables PWM mode

1: Enables CEXn pin to be used as a pulse width modulated output

ECCFn Enable CCF Interrupt

0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt

request.

1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt

request.

DS25093B

02/13

29

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

SPI Control Register (SPCR)

Location

7

6

5

4

3

2

1

0

Reset Value

D5H

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00H

Symbol Function

SPIE

SPE

If both SPIE and ES are set to one, SPI interrupts are enabled.

SPI enable bit.

0: Disables SPI.

1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.

DORD Data Transmission Order.

0: MSB first in data transmission.

1: LSB first in data transmission.

MSTR Master/Slave select.

0: Selects Slave mode.

1: Selects Master mode.

CPOL

CPHA

Clock Polarity

0: SCK is low when idle (Active High).

1: SCK is high when idle (Active Low).

Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data

relationship between master and slave. See Figures 21 and 22.

0: Shift triggered on the leading edge of the clock.

1: Shift triggered on the trailing edge of the clock.

SPR1, SPR0SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured

as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and

the oscillator frequency, f_OSC, is as follows:

SPR1

SPR0

SCK = f_OSCdivided by

0

1

0

1

0

1

4

16

64

128

SPI Status Register (SPSR)

Location

7

6

5

4

3

2

1

0

Reset Value

AAH

SPIF

WCOL

-

00xxxxxxb

Symbol Function

SPIF SPI Interrupt Flag.

Upon completion of data transfer, this bit is set to 1.

If SPIE =1 and ES =1, an interrupt is then generated.

This bit is cleared by software.

WCOL Write Collision Flag.

Set if the SPI data register is written to during data transfer.

This bit is cleared by software.

DS25093B

02/13

30

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

SPI Data Register (SPDR)

Location

7

6

5

4

3

2

1

0

Reset Value

86H

SPDR[7:0]

00H

Power Control Register (PCON)

Location

7

5

4

3

2

1

0

Reset Value

87H

SMOD1 SMOD0

BOF

POF

GF1

GF0

PD

IDL

00010000b

Symbol Function

SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial

port is used in modes 1, 2, and 3.

SMOD0 FE/SM0 Selection bit.

0: SCON[7] = SM0

1: SCON[7] = FE,

BOF

Brown-out detection status bit, this bit will not be affected by any other reset. BOF should be

cleared by software. Power-on reset will also clear the BOF bit.

0: No brown-out.

1: Brown-out occurred

POF

Power-on reset status bit, this bit will not be affected by any other reset. POF should be

cleared by software.

0: No Power-on reset.

1: Power-on reset occurred

GF1

GF0

PD

General-purpose flag bit.

Power-down bit, this bit is cleared by hardware after exiting from power-down mode.

0: Power-down mode is not activated.

1: Activates Power-down mode.

IDL

Idle mode bit, this bit is cleared by hardware after exiting from idle mode.

0: Idle mode is not activated.

1: Activates idle mode.

DS25093B

02/13

31

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Serial Port Control Register (SCON)

Location

7

6

5

4

3

2

1

0

Reset Value

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

00000000b

Symbol Function

FE

Set SMOD0 = 1 to access FE bit.

0: No framing error

1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be

cleared by software.

SM0

SM1

SMOD0 = 0 to access SM0 bit.

Serial Port Mode Bit 0

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate¹

0

Shift Register

f_OSC/6 (6 clock mode) or

f_OSC/12 (12 clock mode)

Variable

0

1

0

1

2

8-bit UART

9-bit UART

f

_OSC/32 or f_OSC/16 (6 clock mode) or

f_OSC/64 or f_OSC/32 (12 clock mode)

1

3

9-bit UART

Variable

1. f_OSC= oscillator frequency

SM2

REN

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will

not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received

byte is a given or broadcast address. In Mode 1, if SM2 = 1 then RI will not be activated

unless a valid stop bit was received. In Mode 0, SM2 should be 0.

Enables serial reception.

0: to disable reception.

1: to enable reception.

TB8

RB8

TI

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as

desired.

In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop

bit that was received. In Mode 0, RB8 is not used.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the

beginning of the stop bit in the other modes, in any serial transmission, Must be cleared by

software.

RI

Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway

through the stop bit time in the other modes, in any serial reception (except see SM2). Must

be cleared by software.

DS25093B

02/13

32

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Timer/Counter 2 Control Register (T2CON)

Location

7

6

5

4

3

2

1

0

Reset Value

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/

00H

RL2#

Symbol Function

TF2

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not

be set when either RCLK or TCLK = 1.

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition

on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU

to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not

cause an interrupt in up/down counter mode (DCEN = 1).

RCLK

TCLK

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its

receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive

clock.

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its

transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the

transmit clock.

EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a

negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0

causes Timer 2 to ignore events at T2EX.

TR2

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2#

Timer or counter select (Timer 2)

0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode)

1: External event counter (falling edge triggered)

CP/RL2# Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2

= 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative

transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored

and the timer is forced to auto-reload on Timer 2 overflow.

Timer/Counter 2 Mode Control (T2MOD)

Location

C9H

7

6

5

4

3

2

1

0

Reset Value

-

T2OE

DCEN

xxxxxx00b

Symbol Function

-

Not implemented, reserved for future use.

Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

T2OE

Timer 2 Output Enable bit.

DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down

counter.

DS25093B

02/13

33

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

External Interrupt Control (XICON)

Location

7

6

5

4

3

2

1

0

Reset Value

AEH

-

EX3

IE3

IT3

0

EX2

IE2

IT2

00H

Symbol Function

EX2

External Interrupt 2

Enable bit if set

IE2

Interrupt Enable

If IT2=1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced.

IT2

External Interrupt 2 is falling-edge/low-level triggered when this bit is cleared by software.

EX3

External Interrupt 3

Enable bit if set

IE3

IT3

Interrupt Enable

If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced.

External Interrupt3 is falling-edge/low-level triggered when this bit is cleared by software.

DS25093B

02/13

34

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Flash Memory Programming

The device internal flash memory can be programmed or erased using In-Application Programming

(IAP) mode

Product Identification

The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as

SST. External programmers primarily use these Signature Bytes in the selection of programming algo-

rithms.

Table 12: Product Identification

Address

Data

Manufacturer’s ID

Device ID

30H

BFH

SST89E516RD2/RD

SST89V516RD2/RD

31H

93H

92H

T0-0.0 25093

In-Application Programming Mode

The device offers either 72 KByte of in-application programmable flash memory. During in-application

programming, the CPU of the microcontroller enters IAP mode. The two blocks of flash memory allow

the CPU to execute user code from one block, while the other is being erased or reprogrammed con-

currently. The CPU may also fetch code from an external memory while all internal flash is being repro-

grammed. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the special

function register (SFR), control and monitor the device’s erase and program process.

Table 14 outline the commands and their associated mailbox register settings.

In-Application Programming Mode Clock Source

During IAP mode, both the CPU core and the flash controller unit are driven off the external clock.

However, an internal oscillator will provide timing references for Program and Erase operations. The

internal oscillator is only turned on when required, and is turned off as soon as the flash operation is

completed.

Memory Bank Selection for In-Application Programming Mode

With the addressing range limited to 16 bit, only 64 KByte of program address space is “visible” at any

one time. As shown in Table 13, the bank selection (the configuration of EA# and SFCF[1:0]), allows

Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable.

The same concept is employed to allow both Block 0 and Block 1 flash to be accessible to IAP opera-

tions. Code from a block that is not visible may not be used as a source to program another address.

However, a block that is not “visible” may be programmed by code from the other block through mailbox

registers.

The device allows IAP code in one block of memory to program the other block of memory, but may not

program any location in the same block. If an IAP operation originates physically from Block 0, the tar-

get of this operation is implicitly defined to be in Block 1. If the IAP operation originates physically from

DS25093B

02/13

35

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates

from external program space, then, the target will depend on the address and the state of bank selec-

tion.

IAP Enable Bit

The IAP enable bit, SFCF[6], enables in-application programming mode. Until this bit is set, all flash

programming IAP commands will be ignored.

Table 13: IAP Address Resolution

Block Being

EA#

1

SFCF[1:0]

00

Address of IAP Inst.

>= 2000H (Block 0)

< 2000H (Block 1)

Any (Block 0)

Target Address

>= 2000H (Block 0)

< 2000H (Block 1)

Any (Block 0)

Programmed

None¹

1

00

Block 1

Block 0

None¹

1

00

1

01, 10, 11

00

>= 2000H (Block 0)

< 2000H (Block 1)

>= 2000H (Block 0)

< 2000H (Block 1)

Any (Block 0)

1

Any (Block 0)

Block 1

Block 0

Block 1

Block 0

0

From external

0

00

From external

0

01, 10, 11

From external

T0-0.0 25093

1. No operation is performed because code from one block may not program the same originating block

In-Application Programming Mode Commands

All of the following commands can only be initiated in the IAP mode. In all situations, writing the control

byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the

security locks are enabled on the selected memory block.

The Program command is for programming new data into the memory array. The portion of the mem-

ory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should

first be erased with an appropriate Erase command. Warning: Do not attempt to write (program or

erase) to a block that the code is currently fetching from. This will cause unpredictable program

behavior and may corrupt program data.

DS25093B

02/13

36

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Chip-Erase

The Chip-Erase command erases all bytes in both memory blocks. This command is only allowed

when EA#=0 (external memory execution). Additionally this command is not permitted when the

device is in level 4 locking. In all other instances, this command ignores the Security Lock status and

will erase the security lock bits and re-map bits.

IAP Enable

ORL SFCF, #40H

Set-Up

MOV SFDT, #55H

Polling scheme

Interrupt scheme

MOV SFCM, #01H

MOV SFCM, #81H

SFST[2] indicates

INT1 interrupt

operation completion

indicates completion

1273 F05.0

Figure 9: Chip Erase

Block-Erase

The Block-Erase command erases all bytes in one of two memory blocks (Block 0 or Block 1). The

selection of the memory block to be erased is determined by the SFCF[1:0]. The Block-Erase com-

mand sequence for SST89x516RDx is as follows:

IAP Enable

ORL SFCF, #40H

Select Block

Configure SFCF[1:0]

*

Set-Up

MOV SFDT, #55H

Polling scheme

Interrupt scheme

MOV SFCM, #0DH

MOV SFCM, #8DH

SFST[2] indicates

INT1 interrupt

operation completion

indicates completion

1273 F06.0

Note: * see Table 13

Figure 10:Block Erase

DS25093B

02/13

37

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Sector-Erase

The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory blocks is

128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL.

IAP Enable

ORL SFCF, #40H

Program sector address

MOV SFAH, #sector_addressH

MOV SFAL, #sector_addressL

Polling scheme

Interrupt scheme

MOV SFCM, #0BH

MOV SFCM, #8BH

SFST[2] indicates

INT1 interrupt

operation completion

indicates completion

1273 F07.0

Figure 11:Sector Erase

Byte-Program

The Byte-Program command programs data into a single byte. The address is determined by the con-

tents of SFAH and SFAL. The data byte is in SFDT.

IAP Enable

ORL SFCF, #40H

Program byte address

MOV SFAH, #byte_addressH

MOV SFAL, #byte_addressL

Move data to SFDT

MOV SFDT, #data

Polling scheme

Interrupt scheme

MOV SFCM, #0EH

MOV SFCM, #8EH

SFST[2] indicates

INT1 interrupt

operation completion

indicates completion

1273 F08.0

Figure 12:Byte Program

DS25093B

02/13

38

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Byte-Verify

The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or

Program command. Byte-Verify command returns the data byte in SFDT if the command is successful.

The user is required to check that the previous flash operation has fully completed before issuing a

Byte-Verify. Byte-Verify command execution time is short enough that there is no need to poll for com-

mand completion and no interrupt is generated.

IAP Enable

ORL SFCF, #40H

Program byte address

MOV SFAH, #byte_addressH

MOV SFAL, #byte_addressL

MOV SFCM, #0CH

SFDT register

contains data

1273 F09.0

Figure 13:Byte Verify

Prog-SB3, Prog-SB2, Prog-SB1

Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the security bits (see Table 25). Com-

pletion of any of these commands, the security options will be updated immediately.

Security bits previously in un-programmed state can be programmed by these commands. Prog-SB3,

Prog-SB2 and Prog-SB1 commands should only reside in Block 1 or external code memory.

IAP Enable

ORL SFCF, #40H

Set-Up

MOV SFDT, #0AAH

Program SB2

Program SB1

MOV SFCM, #0FH

or

Program SB3

MOV SFCM, #05H

or

MOV SFCM, #03H

or

OR

MOV SFCM, #8FH

MOV SFCM, #85H

MOV SFCM, #83H

Polling SFST[2]

INT1# Interrupt

indicates completion

1273 F10.0

Figure 14:Prog-SB3, Prog-SB2, Prog-SB1

DS25093B

02/13

39

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Prog-SC0

Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has

no effect on BSEL bit until after a reset cycle.

SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 com-

mand should reside only in Block 1 or external code memory.

IAP Enable

ORL SFCF, #40H

Set-up Program SC0

MOV SFAH, #5AH

MOV SFDT, #0AAH

Program SC0

Polling scheme

MOV SFCM, #09H

Program SC0

Interrupt scheme

MOV SFCM, #89H

Polling SFST[2]

INT1# Interrupt

indicates completion

1273 F11.0

Figure 15:Prog-SC0

Enable-Clock-Double

Enable-Clock-Double command is used to make the MCU run at 6 clocks per machine cycle. The stan-

dard (default) is 12 clocks per machine cycle (i.e. clock double command disabled).

IAP Enable

ORL SFCF, #40H

Set-up Enable-Clock-Double

MOV SFAH, #55H

MOV SFDT, #0AAH

Program Enable-Clock-Double

Polling scheme

Program Enable-Clock-Double

Interrupt scheme

MOV SFCM, #08H

MOV SFCM, #88H

Polling SFST[2]

INT1# Interrupt

indicates completion

1273 F12.0

Figure 16:Enable-Clock-Double

There are no IAP counterparts for the external host commands Select-Block0 and Select-Block1.

DS25093B

02/13

40

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Polling

A command that uses the polling method to detect flash operation completion should poll on the

FLASH_BUSY bit (SFST[2]). When FLASH_BUSY de-asserts (logic 0), the device is ready for the next

operation.

MOVC instruction may also be used for verification of the Programming and Erase operation of the

flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy.

Interrupt Termination

If interrupt termination is selected, (SFCM[7] is set), then an interrupt (INT1) will be generated to indi-

cate flash operation completion. Under this condition, the INT1 becomes an internal interrupt source.

The INT1# pin can now be used as a general purpose port pin and it cannot be the source of External

Interrupt 1 during in-application programming.

In order to use an interrupt to signal flash operation termination. EX1 and EA bits of IE register must be

set. The IT1 bit of TCON register must also be set for edge trigger detection.

.

Table 14: IAP Commands¹

Operation

Chip-Erase³

SFCM [6:0]²

SFDT [7:0]

55H

SFAH [7:0]

SFAL [7:0]

01H

X⁴

AH

AH⁶

AH

X

Block-Erase⁵

Sector-Erase⁵

Byte-Program⁵

Byte-Verify (Read)⁵

Prog-SB1⁹

Prog-SB2⁹

Prog-SB3⁹

Prog-SC0⁹

Enable-Clock-Double⁹

0DH

55H

X

0BH

X

DI⁸

AL⁷

AL

X

0EH

0CH

DO⁸

AAH

0FH

03H

X

05H

X

09H

5AH

55H

X

08H

X

T0-0.0 25093

1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.

2. Interrupt/Polling enable for flash operation completion

SFCM[7] =1: Interrupt enable for flash operation completion

0: polling enable for flash operation completion

3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.

4. X can be V_ILor V_IH, but no other value.

5. Refer to Table 13 for address resolution

6. AH = Address high order byte

7. AL = Address low order byte

8. DI = Data Input, DO = Data Output, all other values are in hex.

9. Instruction must be located in Block 1 or external code memory.

Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.

DS25093B

02/13

41

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Timers/Counters

Timers

The device has three 16-bit registers that can be used as either timers or event counters. The three

timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of

8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low)

byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2.

Timer Set-up

Refer to Table 9 for TMOD, TCON, and T2CON registers regarding timers T0, T1, and T2. The follow-

ing tables provide TMOD values to be used to set up Timers T0, T1, and T2.

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the

TR2 bit. Therefore, bit TR2 must be set separately to turn the timer on.

Table 15: Timer/Counter 0

TMOD

Mode

Function

13-bit Timer

Internal Control¹

External Control²

0

1

2

3

0

1

2

3

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

16-bit Timer

Used as Timer

8-bit Auto-Reload

Two 8-bit Timers

13-bit Timer

16-bit Timer

Used as

Counter

8-bit Auto-Reload

Two 8-bit Timers

0FH

T0-0.0 25093

1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0# (P3.2) when TR0 = 1 (hardware control).

Table 16: Timer/Counter 1

TMOD

Mode

Function

13-bit Timer

Internal Control¹

External Control²

0

1

2

3

0

1

2

3

00H

10H

20H

30H

40H

50H

60H

-

80H

90H

A0H

B0H

C0H

D0H

E0H

16-bit Timer

Used as Timer

8-bit Auto-Reload

Does not run

13-bit Timer

16-bit Timer

Used as

Counter

8-bit Auto-Reload

Not available

-

T0-0.0 25093

1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1# (P3.3) when TR1 = 1 (hardware control).

DS25093B

02/13

42

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 17: Timer/Counter 2

T2CON

Mode

Internal Control¹

External Control²

16-bit Auto-Reload

16-bit Capture

00H

01H

34H

08H

09H

36H

Baud rate generator receive and transmit

same baud rate

Used as Timer

Receive only

Transmit only

24H

14H

02H

03H

26H

16H

0AH

0BH

16-bit Auto-Reload

16-bit Capture

Used as Counter

T0-0.0 25093

1. Capture/Reload occurs only on timer/counter overflow.

2. Capture/Reload occurs on timer/counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is

used in the baud rate generating mode.

Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O

pin, has two alternate functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating fre-

quency (61 Hz to 4 MHz in 12 clock mode).

To configure Timer/Counter 2 as a clock generator, bit

C/#T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must

be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture

registers (RCAP2H, RCAP2L) as shown in this equation:

Oscillator Frequency

n x (65536 - RCAP2H, RCAP2L)

n =2 (in 6 clock mode)

4 (in 12 clock mode)

Where (RCAP2H, RCAP2L) = the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned inte-

ger.

In the Clock-Out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when it is

used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock gen-

erator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will not be the

same.

DS25093B

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43

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Serial I/O

Full-Duplex, Enhanced UART

The device serial I/O port is a full-duplex port that allows data to be transmitted and received simulta-

neously in hardware by the transmit and receive registers, respectively, while the software is perform-

ing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF)

special function register. Writing to the SBUF register loads the transmit register, and reading from the

SBUF register obtains the contents of the receive register.

The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and

SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is

initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated

in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared

and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the

other modes by the incoming start bit if the REN bit of the SCON register is set.

Framing Error Detection

Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in

modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous trans-

mission by two CPUs.

Framing Error Detection is selected by going to the PCON register and changing SMOD0 = 1 (see Fig-

ure 17). If a stop bit is missing, the Framing Error bit (FE) will be set. Software may examine the FE bit

after each reception to check for data errors. After the FE bit has been set, it can only be cleared by

software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the

last data bit (see Figure 18 and Figure 19).

SCON

SM2

SM0/FE SM1

REN

TB8

RB8

TI

RI

(98H)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

PCON

SMOD1 SMOD0 BOF

POF

GF1

GF0

PD

IDL

(87H)

To UART framing error control

1273 F13.0

Figure 17:Framing Error Block Diagram

DS25093B

02/13

44

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

1273 F14.0

Figure 18:UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth

bit

Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

1273 F15.0

Figure 19:UART Timings in Modes 2 and 3

Automatic Address Recognition

Automatic Address Recognition helps to reduce the MCU time and power required to talk to multiple

serial devices. Each device is hooked together sharing the same serial link with its own address. In this

configuration, a device is only interrupted when it receives its own address, thus eliminating the soft-

ware overhead to compare addresses.

This same feature helps to save power because it can be used in conjunction with idle mode to reduce

the system’s overall power consumption. Since there may be multiple slaves hooked up serial to one

master, only one slave would have to be interrupted from idle mode to respond to the master’s trans-

mission. Automatic Address Recognition (AAR) allows the other slaves to remain in idle mode while

only one is interrupted. By limiting the number of interruptions, the total current draw on the system is

reduced.

There are two ways to communicate with slaves: a group of them at once, or all of them at once. To

communicate with a group of slaves, the master sends out an address called the given address. To

communicate with all the slaves, the master sends out an address called the “broadcast” address.

AAR can be configured as mode 2 or 3 (9-bit modes) and setting the SM2 bit in SCON. Each slave has

its own SM2 bit set waiting for an address byte (9th bit = 1). The Receive Interrupt (RI) flag will only be

set when the received byte matches either the given address or the broadcast address. Next, the slave

then clears its SM2 bit to enable reception of the data bytes (9th bit = 0) from the master. When the 9th

bit = 1, the master is sending an address. When the 9th bit = 0, the master is sending actual data.

DS25093B

02/13

45

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

If mode 1 is used, the stop bit takes the place of the 9th bit. Bit RI is set only when the received com-

mand frame address matches the device’s address and is terminated by a valid stop bit. Note that

mode 0 cannot be used. Setting SM2 bit in the SCON register in mode 0 will have no effect.

Each slave’s individual address is specified by SFR SADDR. SFR SADEN is a mask byte that defines

“don’t care” bits to form the given address when combined with SADDR. See the example below:

Slave 1

SADDR

SADEN

GIVEN

=

1111 0001

1111 1010

1111 0X0X

Slave 2

SADDR

SADEN

GIVEN

=

1111 0011

1111 1001

1111 0XX1

Using the Given Address to Select Slaves

Any bits masked off by a 0 from SADEN become a “don’t care” bit for the given address. Any bit

masked off by a 1, becomes ANDED with SADDR. The “don’t cares” provide flexibility in the user-

defined addresses to address more slaves when using the given address.

Shown in the example above, Slave 1 has been given an address of 1111 0001 (SADDR). The SADEN

byte has been used to mask off bits to a given address to allow more combinations of selecting Slave 1

and Slave 2. In this case for the given addresses, the last bit (LSB) of Slave 1 is a “don’t care” and the

last bit of Slave 2 is a 1. To communicate with Slave 1 and Slave 2, the master would need to send an

address with the last bit equal to 1 (e.g. 1111 0001) since Slave 1’s last bit is a don’t care and Slave 2’s

last bit has to be a 1. To communicate with Slave 1 alone, the master would send an address with the

last bit equal to 0 (e.g. 1111 0000), since Slave 2’s last bit is a 1. See the table below for other possible

combinations.

Select Slave 1 Only

Slave 1

Given Address

Possible Addresses

1111 0X0X

1111 0000

1111 0100

Select Slave 2 Only

Slave 2

Given Address

Possible Addresses

1111 0XX1

1111 0111

1111 0011

Select Slaves 1 & 2

Slaves 1 & 2

Possible Addresses

1111 0001

1111 0101

DS25093B

02/13

46

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

If the user added a third slave such as the example below:

Slave 3

SADDR = 1111 1001

SADEN = 1111 0101

GIVEN

= 1111 X0X1

Select Slave 3 Only

Given Address

1111 X0X1

Slave 2

Possible Addresses

1111 1011

1111 1001

The user could use the possible addresses above to select slave 3 only. Another combination could be

to select slave 2 and 3 only as shown below.

Select Slaves 2 & 3 Only

Slaves 2 & 3

Possible Addresses

1111 0011

More than one slave may have the same SADDR address as well, and a given address could be used

to modify the address so that it is unique.

Using the Broadcast Address to Select Slaves

Using the broadcast address, the master can communicate with all the slaves at once. It is formed by

performing a logical OR of SADDR and SADEN with ‘0’s in the result treated as “don’t cares”.

Slave 1

1111 0001 = SADDR

+1111 1010 = SADEN

1111 1X11 = Broadcast

“Don’t cares” allow for a wider range in defining the broadcast address, but in most cases, the broad-

cast address will be FFH.

On reset, SADDR and SADEN are “0”. This produces an given address of all “don’t cares” as well as a

broadcast address of all “don’t cares.” This effectively disables Automatic Addressing mode and allows

the microcontroller to function as a standard 8051, which does not make use of this feature.

DS25093B

02/13

47

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Serial Peripheral Interface

SPI Features

•

Master or slave operation

10 MHz bit frequency (max)

LSB first or MSB first data transfer

Four programmable bit rates

End of transmission (SPIF)

Write collision flag protection (WCOL)

Wake up from idle mode (slave mode only)

SPI Description

The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the

SST89E/V516RDx and peripheral devices or between several SST89E/V516RDx devices.

Figure 20 shows the correspondence between master and slave SPI devices. The SCK pin is the clock

output and input for the master and slave modes, respectively. The SPI clock generator will start follow-

ing a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin

on the master device into the MOSI pin of the slave device. Following a complete transmission of one

byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will

be generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are

both set.

An external master drives the Slave Select input pin, SS#/P1[4], low to select the SPI module as a

slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5]

port can also be used as an input port pin.

CPHA and CPOL control the phase and polarity of the SPI clock. Figures 21 and 22 show the four pos-

sible combinations of these two bits.

MSB Master LSB

8-bit Shift Register

MSB Slave LSB

8-bit Shift Register

MISO MISO

MOSI MOSI

SCK

SS#

SCK

SS#

SPI

Clock Generator

1273 F16.0

V

DD

SS

Figure 20:SPI Master-slave Interconnection

DS25093B

02/13

48

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

SPI Transfer Formats

SCK Cycle #

(for reference)

1

2

3

4

5

6

7

8

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MSB

6

5

4

3

2

1

LSB

(from Master)

MISO

(from Slave)

MSB

6

5

4

3

2

1

SS# (to Slave)

1273 F17.0

Figure 21:SPI Transfer Format with CPHA = 0

SCK Cycle #

(for reference)

1

2

3

4

5

6

7

8

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MSB

6

5

4

3

2

1

LSB

(from Master)

MISO

(from Slave)

6

5

LSB

SS# (to Slave)

1273 F18.0

Figure 22:SPI Transfer Format with CPHA = 1

DS25093B

02/13

49

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Watchdog Timer

The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software

deadlock and automatic recovery.

To protect the system against software deadlock, the user software must refresh the WDT within a

user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset

will be initiated if enabled (WDRE= 1). The software can be designed such that the WDT times out if

the program does not work properly.

The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a

watchdog counter rather than a watchdog timer. The WDT register will increment every 344,064 crystal

clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT.

The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear

WDTS by writing “1” to it.

Figure 23 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer

operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt

exit from idle.

The time-out period of the WDT is calculated as follows:

Period = (255 - WDTD) * 344064 * 1/f_{CLK (XTAL1)}

where WDTD is the value loaded into the WDTD register and f_OSCis the oscillator frequency.

344064

clks

WDT Reset

CLK (XTAL1)

Internal Reset

Counter

WDT Upper Byte

Ext. RST

WDTC

WDTD

1273 F19.0

Figure 23:Block Diagram of Programmable Watchdog Timer

DS25093B

02/13

50

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Programmable Counter Array

The Programmable Counter Array (PCA) present on the SST89E/V516RDx is a special 16-bit timer

that has five 16-bit capture/compare modules. Each of the modules can be programmed to operate in

one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width

modulator. The 5th module can be programmed as a Watchdog Timer in addition to the other four

modes. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0),

module 1 to P1[4] (CEX1), module 2 to P1[5] (CEX2), module 3 to P1[6] (CEX3), and module 4 to

P1[7] (CEX4). PCA configuration is shown in Figure 24.

PCA Overview

PCA provides more timing capabilities with less CPU intervention than the standard timer/counter. Its

advantages include reduced software overhead and improved accuracy.

The PCA consists of a dedicated timer/counter which serves as the time base for an array of five com-

pare/capture modules. Figure 24 shows a block diagram of the PCA. External events associated with

modules are shared with corresponding Port 1 pins. Modules not using the port pins can still be used

for standard I/O.

Each of the five modules can be programmed in any of the following modes:

•

Rising and/or falling edge capture

Software timer

High speed output

Watchdog Timer (Module 4 only)

Pulse Width Modulator (PWM)

PCA Timer/Counter

The PCA timer is a free-running 16-bit timer consisting of registers CH and CL (the high and low bytes

of the count values). The PCA timer is common time base for all five modules and can be programmed

to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, Timer 0 overflow, or the input on the

ECI pin (P1.2). The timer/counter source is determined from the CPS1 and CPS0 bits in the CMOD

SFR as follows (see “PCA Timer/Counter Mode Register (CMOD)” on page 28):

Table 18: PCA Timer/Counter Source

CPS1

CPS0

12 Clock Mode

6 Clock Mode

f_OSC/6

0

1

0

1

0

1

f_OSC/12

f_OSC/4

f_OSC/2

Timer 0 overflow

External clock at ECI pin

(maximum rate = f_OSC/8)

External clock at ECI pin

(maximum rate = f_OSC/4)

T0-0.0 25093

DS25093B

02/13

51

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

16 Bits Each

Module 0

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

Module 1

Module 2

Module 3

Module 4

16 Bits

PCA Timer/Counter

P1.7/CEX4

1273 F20.0

Figure 24:PCA Timer/Counter and Compare/Capture Modules

The table below summarizes various clock inputs at two common frequencies.

Table 19: PCA Timer/Counter Inputs

Clock Increments

PCA Timer/Counter Mode

Mode 0: f_OSC/12

12 MHz

1 µsec

16 MHz

0.75 µsec

250 nsec

Mode 1:

330 nsec

Mode 2: Timer 0 Overflows¹

Timer 0 programmed in:

8-bit mode

256 µsec

65 msec

192 µsec

49 µsec

16-bit mode

8-bit auto-reload

1 to 255 µsec

0.66 µsec

0.75 to 191 µsec

0.50 µsec

Mode 3: External Input MAX

T0-0.0 25093

1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.

The four possible CMOD timer modes with and without the overflow interrupt enabled are shown

below. This list assumes that PCA will be left running during idle mode.

Table 20: CMOD Values

CMOD Value

PCA Count Pulse Selected

Internal clock, f_OSC/12

Internal clock, f_OSC/4

Timer 0 overflow

Without Interrupt Enabled

With Interrupt Enabled

00H

02H

04H

06H

01H

03H

05H

07H

External clock at P1.2

T0-0.0 25093

The CCON register is associated with all PCA timer functions. It contains run control bits and flags for

the PCA timer (CF) and all modules. To run the PCA the CR bit (CCON.6) must be set by software.

Clearing the bit, will turn off PCA. When the PCA counter overflows, the CF (CCON.7) will be set, and

DS25093B

02/13

52

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared

by software. Each module has its own timer interrupt or capture interrupt flag (CCF0 for module 0,

CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can only be

cleared by software. (See “PCA Timer/Counter Control Register (CCON)” on page 27.)

Compare/Capture Modules

Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0, CCAPM1 for

module 1, etc. Refer to “PCA Compare/Capture Module Mode Register (CCAPMn)” on page 29 for details.

The registers each contain 7 bits which are used to control the mode each module will operate in. The ECCF

bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on module) will enable the CCF flag in the CCON SFR to

generate an interrupt when a match or compare occurs. PWM (CCAPMn.1) enables the pulse width modula-

tion mode. The TOG bit (CCAPMn.2) when set, causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare register. When there is a

match between the PCA counter and the module’s capture/compare register, the MATn (CCAPMn.3) and the

CCFn bit in the CCON register to be set.

Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine whether the capture input will be active on a pos-

itive edge or negative edge. The CAPN bit enables the negative edge that a capture input will be active on,

and the CAPP bit enables the positive edge. When both bits are set, both edges will be enabled and a capture

will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set, enables the compara-

tor function. Table 22 shows the CCAPMn settings for the various PCA functions.

There are two additional register associated with each of the PCA modules: CCAPnH and CCAPnL. They are

registers that hold the 16-bit count value when a capture occurs or a compare occurs. When a module is used

in PWM mode, these registers are used to control the duty cycle of the output. See Figure 24.

Table 21: PCA High and Low Register Compare/Capture Modules

Bit Address, Symbol, or Alternative Port Function

Direct

RESET

Value

Symbol Description

Address MSB

LSB

CCAP0H PCA Module 0

FAH

EAH

FBH

EBH

FCH

ECH

FDH

EDH

FEH

EEH

CCAP0H[7:0]

CCAP0L[7:0]

CCAP1H[7:0]

CCAP1L[7:0]

CCAP2H[7:0]

CCAP2L[7:0]

CCAP3H[7:0]

CCAP3L[7:0]

CCAP4H[7:0]

CCAP4L[7:0]

00H

Compare/Capture Registers

CCAP0L

CCAP1H PCA Module 1

Compare/Capture Registers

CCAP1L

CCAP2H PCA Module 2

Compare/Capture Registers

CCAP2L

CCAP3H PCA Module 3

Compare/Capture Registers

CCAP3L

CCAP4H PCA Module 4

Compare/Capture Registers

CCAP4L

00H

T0-0.0 25093

DS25093B

02/13

53

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 22: PCA Module Modes

Without Interrupt enabled

1

-

ECOMy²CAPPy²CAPNy²MATy²TOGy²PWMy²ECCFy²Module Code

-

0

1

0

No Operation

-

16-bit capture on positive-edge trigger at

CEX[4:0]

0

1

0

16-bit capture on negative-edge trigger at

CEX[4:0]

16-bit capture on positive/negative-edge

trigger at CEX[4:0]

-

1

0

1

0

1

0

1

0

1

0

Compare: software timer

Compare: high-speed output

Compare: 8-bit PWM

Compare: PCA WDT (CCAPM4 only)⁴

0 or

1³

T0-0.0 25093

1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

2. y = 0, 1, 2, 3, 4

3. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.

4. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.

Table 23: PCA Module Modes

With Interrupt enabled

1

-

ECOMy²CAPPy²CAPNy²MATy²TOGy²PWMy²ECCFy²Module Code

-

0

1

0

1

0

1

0

1

16-bit capture on positive-edge trig-

ger at CEX[4:0]

-

16-bit capture on negative-edge trig-

ger at CEX[4:0]

16-bit capture on positive/negative-

edge

trigger at CEX[4:0]

-

1

0

1

0

1

0

1

0

1

X³

X⁵

Compare: software timer

Compare: high-speed output

Compare: 8-bit PWM

1

0

0 or 1⁴

Compare: PCA WDT (CCAPM4

only)⁶

T0-0.0 25093

1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.

2. y = 0, 1, 2, 3, 4

3. No PCA interrupt is needed to generate the PWM.

4. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.

5. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer.

6. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.

DS25093B

02/13

54

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Capture Mode

Capture mode is used to capture the PCA timer/counter value into a module’s capture registers

(CCAPnH and CCAPnL). The capture will occur on a positive edge, negative edge, or both on the cor-

responding module’s pin. To use one of the PCA modules in the capture mode, either one or both the

CCAPM bits CAPN and CAPP for that module must be set. When a valid transition occurs on the CEX

pin corresponding to the module used, the PCA hardware loads the 16-bit value of the PCA counter

register (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for

the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set, then an interrupt will be

generated. In the interrupt service routine, the 16-bit capture value must be saved in RAM before the

next event capture occurs. If a subsequent capture occurred, the original capture values would be lost.

After flag event flag has been set by hardware, the user must clear the flag in software. (See Figure 25)

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

CCON

PCA Interrupt

PCA Timer/Counter

CH

CL

Capture

CEXn

CCAPnH

CCAPnL

CCAPMn

1273 F21.0

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

n=0 to 4

0

Figure 25:PCA Capture Mode

DS25093B

02/13

55

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

16-Bit Software Timer Mode

The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic inter-

vals. It is setup by setting both the ECOM and MAT bits in the module’s CCAPMn register. The PCA

timer will be compared to the module’s capture registers (CCAPnL and CCAPnH) and when a match

occurs, an interrupt will occur, if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the

module are both set.

If necessary, a new 16-bit compare value can be loaded into CCAPnH and CCAPnL during the inter-

rupt routine. The user should be aware that the hardware temporarily disables the comparator function

while these registers are being updated so that an invalid match will not occur. Thus, it is recom-

mended that the user write to the low byte first (CCAPnL) to disable the comparator, then write to the

high byte (CCAPnH) to re-enable it. If any updates to the registers are done, the user may want to hold

off any interrupts from occurring by clearing the EA bit. (See Figure 26)

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

CCON

Write to

CCAPnL Reset

PCA Interrupt

Write to

CCAPnH

CCAPnL

CCAPnH

1

0

Enable

Match

16-bit Comparator

CH

CL

PCA Timer/Counter

CCAPMn

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

n=0 to 4

0

1273 F22.0

Figure 26:PCA Compare Mode (Software Timer)

High Speed Output Mode

The high speed output mode is used to toggle a port pin when a match occurs between the PCA timer

and the preloaded value in the compare registers. In this mode, the CEX output pin (on port 1) associ-

ated with the PCA module will toggle every time there is a match between the PCA counter (CH and

CL) and the capture registers (CCAPnH and CCAPnL). To activate this mode, the user must set TOG,

MAT, and ECOM bits in the module’s CCAPMn SFR.

High speed output mode is much more accurate than toggling pins since the toggle occurs before

branching to an interrupt. In this case, interrupt latency will not affect the accuracy of the output. When

using high speed output, using an interrupt is optional. Only if the user wishes to change the time for

the next toggle is it necessary to update the compare registers. Otherwise, the next toggle will occur

when the PCA timer rolls over and matches the last compare value. (See Figure 27)

DS25093B

02/13

56

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

CCON

Write to

CCAPnL Reset

PCA Interrupt

Write to

CCAPnH

CCAPnL

CCAPnH

1

0

Enable

Match

16-bit Comparator

Toggle

CEXn

CH

CL

PCA Timer/Counter

CCAPMn

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

n=0 to 4

0

1273 F23.0

Figure 27:PCA High Speed Output Mode

Pulse Width Modulator

The Pulse Width Modulator (PWM) mode is used to generate 8-bit PWMs by comparing the low byte of

the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the out-

put is low. When CL ≥ CCAPnL the output is high. To activate this mode, the user must set the PWM

and ECOM bits in the module’s CCAPMn SFR. (See Figure 28 and Table 24)

In PWM mode, the frequency of the output depends on the source for the PCA timer. Since there is

only one set of CH and CL registers, all modules share the PCA timer and frequency. Duty cycle of the

output is controlled by the value loaded into the high byte (CCAPnH). Since writes to the CCAPnH reg-

ister are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for com-

parison until the next period of the output (when CL rolls over from 255 to 00).

To calculate values for CCAPnH for any duty cycle, use the following equation:

CCAPnH = 256(1 - Duty Cycle)

where CCAPnH is an 8-bit integer and Duty Cycle is a fraction.

DS25093B

02/13

57

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

CCAPnH

CCAPnL

0

CL < CCAPnL

CEXn

Enable

8-bit Comparator

CL >= CCAPnL

1

CL

Overflow

PCA Timer/Counter

CCAPMn

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

n=0 to 4

1273 F24.0

0

Figure 28:PCA Pulse Width Modulator Mode

Table 24: Pulse Width Modulator Frequencies

PWM Frequency

PCA Timer Mode

1/12 Oscillator Frequency

1/4 Oscillator Frequency

Timer 0 Overflow:

8-bit

12 MHz

16 MHz

3.9 KHz

5.2 KHz

11.8 KHz

15.6 KHz

15.5 Hz

0.06 Hz

20.3 Hz

0.08 Hz

16-bit

8-bit Auto-Reload

External Input (Max)

3.9 KHz to 15.3 Hz

5.9 KHz

5.2 KHz to 20.3 Hz

7.8 KHz

T0-0.0 25093

DS25093B

02/13

58

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Watchdog Timer

The Watchdog Timer mode is used to improve reliability in the system without increasing chip count

(See Figure 29). Watchdog Timers are useful for systems that are susceptible to noise, power glitches,

or electrostatic discharge. It can also be used to prevent a software deadlock. If during the execution of

the user’s code, there is a deadlock, the Watchdog Timer will time out and an internal reset will occur.

Only module 4 can be programmed as a Watchdog Timer (but still can be programmed to other modes

if the Watchdog Timer is not used).

To use the Watchdog Timer, the user pre-loads a 16-bit value in the compare register. Just like the

other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to

occur, an internal reset will be generated. This will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog timer by clearing the WDTE bit before a match occurs and then re-

enable it.

The first two options are more reliable because the Watchdog Timer is never disabled as in option #3.

If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The

second option is also not recommended if other PCA modules are being used. Remember, the PCA

timer is the time base for all modules; changing the time base for other modules would not be a good

idea. Thus, in most application the first solution is the best option.

Use the code below to initialize the Watchdog Timer. Module 4 can be configured in either compare

mode, and the WDTE bit in CMOD must also be set. The user’s software then must periodically

change (CCAP4H, CCAP4L) to keep a match from occurring with the PCA timer (CH, CL). This code is

given in the Watchdog routine below.

;==============================================

Init_Watchdog:

MOVCCAPM4, #4CH; Module 4 in compare mode

MOVCCAP4L, #0FFH; Write to low byte first

MOVCCAP4H, #0FFH; Before PCA timer counts up

; to FFFF Hex, these compare

; values must be changed.

ORLCMOD, #40H; Set the WDTE bit to enable the

; watchdog timer without

; changing the other bits in

; CMOD

;==============================================

;Main program goes here, but call WATCHDOG periodically.

;==============================================

WATCHDOG:

DS25093B

02/13

59

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

CLR EA; Hold off interrupts

MOVCCAP4L, #00; Next compare value is within

MOVCCAP4H, CH; 65,535 counts of the

; current PCA

SETBEA; timer value

RET

;==============================================

This routine should not be part of an interrupt service routine. If the program counter goes astray and

gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset.

Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main pro-

gram of the PCA timer.

CIDL WDTE

CPS1 CPS0

ECF

CMOD

Write to

CCAP4L Reset

Write to

CCAP4H

Module 4

Match

CCAP4H

CCAP4L

1

0

Enable

16-bit Comparator

Reset

CH

CL

PCA Timer/Counter

CCAPM4

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

0

1

X

0

X

1273 F25.0

Figure 29:PCA Watchdog Timer (Module 4 only)

DS25093B

02/13

60

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Security Lock

The security lock protects against software piracy and prevents the contents of the flash from being

read by unauthorized parties. It also protects against code corruption resulting from accidental erasing

and programming to the internal flash memory. There are two different types of security locks in the

device security lock system: hard lock and SoftLock.

Hard Lock

When hard lock is activated, MOVC or IAP instructions executed from an unlocked or soft locked pro-

gram address space, are disabled from reading code bytes in hard locked memory blocks (See Table

26). Hard lock can either lock both flash memory blocks or just lock the 8 KByte flash memory block

(Block 1). All external host and IAP commands except for Chip-Erase are ignored for memory blocks

that are hard locked.

SoftLock

SoftLock allows flash contents to be altered under a secure environment. This lock option allows the

user to update program code in the soft locked memory block through in-application programming

mode under a predetermined secure environment. For example, if Block 1 (8K) memory block is locked

(hard locked or soft locked), and Block 0 memory block is soft locked, code residing in Block 1 can pro-

gram Block 0. The following IAP mode commands issued through the command mailbox register,

SFCM, executed from a Locked (hard locked or soft locked) block, can be operated on a soft locked

block: Block-Erase, Sector-Erase, Byte-Program and Byte-Verify.

In external host mode, SoftLock behaves the same as a hard lock.

Security Lock Status

The three bits that indicate the device security lock status are located in SFST[7:5]. As shown in Figure

30 and Table 25, the three security lock bits control the lock status of the primary and secondary blocks

of memory. There are four distinct levels of security lock status. In the first level, none of the security

lock bits are programmed and both blocks are unlocked. In the second level, although both blocks are

now locked and cannot be programmed, they are available for read operation via Byte-Verify. In the

third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both

blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2, Block 1 except read

operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/pro-

gram of internal memory or boot from external memory. For details on how to program the security lock

bits refer to the external host mode and in-application programming sections.

DS25093B

02/13

61

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

UUU/NN

Level 1

Level 2

PUU/SS

UPU/SS

UUP/LS

Level 3

UPP/LL

PPU/LS

PUP/LL

UPP/LL

Level 4

PPP/LL

1273 F26.0

Figure 30:Security Lock Levels

Note: P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked, S = Soft

locked

Table 25: Security Lock Options

Security Lock Bits^1,2

Security Status of:

Level SFST[7:5]

SB1

SB2¹

SB3¹

Block 1

Block 0

Security Type

1

000

U

Unlock

No Security Features are

Enabled.

2

100

P

U

SoftLock

MOVC instructions executed from

external program memory are

disabled from fetching code bytes

from internal memory, EA# is

sampled and latched on Reset,

and further programming of the

flash is disabled.

3

4

011

101

U

P

U

P

Hard Lock Hard Lock Level 2 plus Verify disabled, both

blocks locked.

010

U

P

U

SoftLock

Level 2 plus Verify disabled. Code

in Block 1 may program Block 0

and vice versa.

110

001

P

U

P

U

P

Hard Lock SoftLock

Level 2 plus Verify disabled. Code

in Block 1 may program Block 0.

111

P

Hard Lock Hard Lock Same as Level 3 hard lock/hard

lock, but MCU will start code exe-

cution from the internal memory

regardless of EA#.

T0-0.0 25093

1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1).

2. SFST[7:5] = Security Lock Status Bits (SB1_i, SB2_i, SB3_i)

DS25093B

02/13

62

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Read Operation Under Lock Condition

The status of security bits SB1, SB2, and SB3 can be read when the read command is disabled by

security lock. There are three ways to read the status.

1. External host mode: Read-back = 00H (locked)

2. IAP command: Read-back = previous SFDT data

3. MOVC: Read-back = FFH (blank)

Table 26: Security Lock Access Table

Byte-Verify Allowed

MOVC Allowed

Source

Address¹

Target

Address²

Level

SFST[7:5]

External Host³

IAP

516RDx

Block 0/1

External

Block 0/1

External

Block 0/1

External

Block 0/1

External

Block 0

N

N/A

N

N/A

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

Block 0/1

External

Block 0/1

External

111b

4

(hard lock on both blocks)

N/A

N

N/A

N

N/A

N

N/A

N

011b/101b

(hard lock on both blocks)

N/A

N

N/A

N

Block 0

Block 1

N

External

Block 0

N/A

N

N/A

Y

001b/110b

(Block 0 = SoftLock,

Block 1 = hard lock)

Block 1

External

Block 0

Block 1

N

External

Block 0/1

External

Block 0

N/A

N

N/A

N

3

N/A

N

N/A

N

Block 1

N

Y

External

Block 0

N/A

N

N/A

Y

010b

(SoftLock on both blocks)

Block 1

External

Block 0

Block 1

N

External

Block 0/1

External

Block 0

N/A

N

N/A

N

N/A

Y

N/A

N

Block 1

Y

External

Block 0

N/A

Y

N/A

Y

100b

2

(SoftLock on both blocks)

Block 1

Y

N

External

Block 0/1

External

N/A

Y

N/A

N

External

N/A

DS25093B

02/13

63

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 26: Security Lock Access Table

Byte-Verify Allowed

MOVC Allowed

Source

Address¹

Target

Address²

Level

SFST[7:5]

External Host³

IAP

516RDx

Block 0

Block 1

External

Block 0

Block 1

External

Block 0/1

External

Y

N

Y

N

Y

N

Block 0

N/A

Y

N/A

Y

000b

(unlock)

1

Block 1

Y

N

N/A

Y

N/A

Y

External

N/A

Y

T0-0.0 25093

1. Location of MOVC or IAP instruction

2. Target address is the location of the byte being read

3. External host Byte-Verify access does not depend on a source address.

DS25093B

02/13

64

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Reset

A system reset initializes the MCU and begins program execution at program memory location 0000H.

The reset input for the device is the RST pin. In order to reset the device, a logic level high must be

applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable.

ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in

order to perform a proper reset. This level must not be affected by external element. A system reset will

not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip

RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return

to their reset values outlined in Tables 6 to 10.

Power-on Reset

At initial power up, the port pins will be in a random state until the oscillator has started and the internal

reset algorithm has weakly pulled all pins high. Powering up the device without a valid reset could

cause the MCU to start executing instructions from an indeterminate location. Such undefined

states may inadvertently corrupt the code in the flash.

When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usu-

ally several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An

example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to V_DD

through a 10 µF capacitor and to V_SSthrough an 8.2KΩ resistor as shown in Figure 31. Note that if an RC circuit is

being used, provisions should be made to ensure the V_DDrise time does not exceed 1 millisecond and the oscillator

start-up time does not exceed 10 milliseconds.

For a low frequency oscillator with slow start-up time the reset signal must be extended in order to

account for the slow start-up time. This method maintains the necessary relationship between V_DDand

RST to avoid programming at an indeterminate location, which may cause corruption in the code of the

flash. The power-on detection is designed to work as power up initially, before the voltage reaches the

brown-out detection level. The POF flag in the PCON register is set to indicate an initial power up con-

dition. The POF flag will remain active until cleared by software. Please see Section , “Power Control

Register (PCON)” on page 31 for detailed information.

For more information on system level design techniques, please review the FlashFlex MCU: Oscilla-

tor Circuit Design Considerations application note.

V

DD

+

-

10µF

8.2K

V

DD

RST

SST89E/V516RDx

C

2

XTAL2

XTAL1

C

1

1273 F27.0

Figure 31:Power-on Reset Circuit

DS25093B

02/13

65

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Software Reset

The software reset is executed by changing SFCF[1] (SWR) from “0” to “1”. A software reset will reset

the program counter to address 0000H. All SFR registers will be set to their reset values, except

SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.

Brown-out Detection Reset

The device includes a brown-out detection circuit to protect the system from severed supplied voltage

V_DDfluctuations. SST89E516RDx internal brown-out detection threshold is 3.85V, SST89V516RDx

brown-out detection threshold is 2.35V. For brown-out voltage parameters, please refer to Table 36.

When V_DDdrops below this voltage threshold, the brown-out detector triggers the circuit to generate a

brown-out interrupt but the CPU still runs until the supplied voltage returns to the brown-out detection

voltage V_BOD. The default operation for a brown-out detection is to cause a processor reset.

V

_DDmust stay below V_BODat least four oscillator clock periods before the brown-out detection circuit

will respond.

Brown-out interrupt can be enabled by setting the EBO bit in IEA register (address E8H, bit 3). If EBO

bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the pro-

gram at location 004BH. It is required that the EBO bit be cleared by software after the brown-out inter-

rupt is serviced. Clearing EBO bit when the brown-out condition is active will properly reset the device.

If brown-out interrupt is not enabled, a brown-out condition will reset the program to resume execution

at location 0000H.

DS25093B

02/13

66

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Interrupts

Interrupt Priority and Polling Sequence

The device supports eight interrupt sources under a four level priority scheme. Table 27 summarizes

the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share

the same interrupt vector. (See Figure 32)

Table 27: Interrupt Polling Sequence

Interrupt

Flag

Vector

Address

Interrupt

Enable

Interrupt

Priority

Service

Priority

Wake-Up

Power-down

Description

Ext. Int0

Brown-out

T0

IE0

-

0003H

004BH

000BH

0013H

001BH

0033H

003BH

0043H

0023H

002BH

EX0

EBO

ET0

EX1

ET1

EC

PX0/H

PBO/H

PT0/H

PX1/H

PT1/H

PPCH

PX2/H

PX3/H

PS/H

1(highest)

yes

no

yes

no

2

3

TF0

Ext. Int1

T1

IE1

4

TF1

5

PCA

CF/CCFn

IE2

6

Ext. Int. 2

Ext. Int. 3

UART/SPI

T2

EX2

EX3

ES

7

IE3

8

TI/RI/SPIF

TF2, EXF2

9

ET2

PT2/H

10

no

T0-0.0 25093

DS25093B

02/13

67

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

HIGHEST PRIORITY

INTERRUPT

IP/IPH/IPA/IPAH

REGISTERS

IE & IEA

REGISTERS

0

1

INT0#

BOF

TF0

IT0

IE0

INTERRUPT

POLLING

SEQUENCE

0

1

INT1#

TF1

IT1

IE1

ECF

CF

CCFn

ECCFn

0

1

INT2#

IT2

IE2

0

1

INT3#

IT3

IE3

RI

TI

SPIF

SPIE

TF2

EXF2

GLOBAL

DISABLE

INDIVIDUAL

ENABLES

LOWEST PRIORITY

INTERRUPT

1273 F28.0

Figure 32:Interrupt Structure

DS25093B

02/13

68

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Power-Saving Modes

The device provides two power saving modes of operation for applications where power consumption

is critical. The two modes are idle and power-down, see Table 28.

Idle Mode

Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is

stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-

chip RAM and the special function registers hold their data during this mode.

The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via

system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt

Service Routine, the interrupted program resumes execution beginning at the instruction immediately

following the instruction which invoked the idle mode. A hardware reset starts the device similar to a

power-on reset.

Power-down Mode

The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode,

the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents

are retained during power-down, the minimum V_DDlevel is 2.0V.

The device exits power-down mode through either an enabled external level sensitive interrupt or a

hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external

interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bring-

ing back high to complete the exit. Upon interrupt signal being restored to logic V_IH,the first instruction

of the interrupt service routine will execute. A hardware reset starts the device similar to power-on

reset.

To exit properly out of power-down, the reset or external interrupt should not be executed before the

V_DDline is restored to its normal operating voltage. Be sure to hold V_DDvoltage long enough at its nor-

mal operating level for the oscillator to restart and stabilize (normally less than 10 ms).

DS25093B

02/13

69

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 28: Power Saving Modes

Mode

Initiated by

State of MCU

CLK is running.

Exited by

Idle Mode

Software

Enabled interrupt or hardware

(Set IDL bit in PCON)

MOV PCON, #01H;

Interrupts, serial port and reset. Start of interrupt clears IDL

timers/counters are active. bit and exits idle mode, after the

Program Counter is

ISR RETI instruction, program

stopped. ALE and PSEN# resumes execution beginning at

signals at a HIGH level

during Idle. All registers

remain unchanged.

the instruction following the one

that invoked idle mode. A user

could consider placing two or three

NOP instructions after the instruc-

tion that invokes idle mode to elim-

inate any problems. A hardware

reset restarts the device similar to

a power-on reset.

Power-down

Mode

Software

(Set PD bit in PCON)

MOV PCON, #02H;

CLK is stopped. On-chip Enabled external level sensitive

SRAM and SFR data is

maintained. ALE and

interrupt or hardware reset. Start

of interrupt clears PD bit and exits

PSEN# signals at a LOW power-down mode, after the ISR

level during power -down. RETI instruction program resumes

External Interrupts are

execution beginning at the instruc-

only active for level sensi- tion following the one that invoked

tive interrupts, if enabled. power-down mode. A user could

consider placing two or three NOP

instructions after the instruction

that invokes power-down mode to

eliminate any problems. A hard-

ware reset restarts the device sim-

ilar to a power-on reset.

T0-0.0 25093

DS25093B

02/13

70

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

System Clock and Clock Options

Clock Input Options and Recommended Capacitor Values for Oscillator

Shown in Figure 33 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which

can be configured for use as an on-chip oscillator.

When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1

should be driven.

At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction

between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF

once the external signal meets the V_ILand V_IHspecifications.

Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from

one application to another. C1 and C2 should be adjusted appropriately for each design. Table 29,

shows the typical values for C1 and C2 vs. crystal type for various frequencies

Table 29: Recommended Values for C1 and C2 by Crystal Type

Crystal

Quartz

C1 = C2

20-30pF

40-50pF

Ceramic

T0-0.0 25093

More specific information about on-chip oscillator design can be found in the FlashFlex Oscillator

Circuit Design Considerations application note.

Clock Doubling Option

By default, the device runs at 12 clocks per machine cycle (x1 mode). The device has a clock doubling

option to speed up to 6 clocks per machine cycle. Please refer to Table 30 for detail.

Clock double mode can be enabled either via the external host mode or the IAP mode. Please refer to

Table 14 for the IAP mode enabling commands (When set, the EDC# bit in SFST register will indicate

6 clock mode.).

The clock double mode is only for doubling the internal system clock and the internal flash

memory, i.e. EA#=1. To access the external memory and the peripheral devices, careful consideration

must be taken. Also note that the crystal output (XTAL2) will not be doubled.

DS25093B

02/13

71

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

XTAL2

XTAL1

NC

C

XTAL2

2

External

XTAL1

1

Oscillator

Signal

V

SS

V

SS

1273 F29.0

External Clock Drive

Using the On-Chip Oscillator

Figure 33:Oscillator Characteristics

Table 30: Clock Doubling Features

Device

Standard Mode (x1)

Clock Double Mode (x2)

Clocks per

Machine

Cycle

Max. External Clock

Frequency

Clocks per

Machine

Cycle

Max. External Clock

Frequency

(MHz)

SST89E516RDx

SST89V516RDx

12

40

33

6

20

16

T0-0.0 25093

DS25093B

02/13

72

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Electrical Specification

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on EA# Pin to V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V

D.C. Voltage on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD+0.5V

Transient Voltage (<20ns) on Any Other Pin to V_SS. . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V_DD+1.0V

Maximum I_OLper I/O Pins P1.5, P1.6, P1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Maximum I_OLper I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA

Package Power Dissipation Capability (T_A= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C

Surface Mount Solder Reflow Temperature¹. . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current². . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest

information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

(Based on package heat transfer limitations, not device power consumption.

Note: This specification contains preliminary information on new products in production.

The specifications are subject to change without notice.

Table 31: Operating Range

Symbol

Description

Min.

Max

Unit

T_A

Ambient Temperature Under Bias

Standard

0

+70

+85

°C

Industrial

-40

V_DD

Supply Voltage

SST89E516RDx

SST89V516RDx

Oscillator Frequency

SST89E516RDx

SST89V516RDx

Oscillator Frequency for IAP

SST89E516RDx

SST89V516RDx

4.5

2.7

5.5

3.6

V

f_OSC

0

40

33

MHz

.25

40

33

MHz

T0-0.0 25093

DS25093B

02/13

73

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 32: Reliability Characteristics

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units Test Method

1

N_END

10,000

100

Cycles JEDEC Standard A117

Years JEDEC Standard A103

1

T_DR

1

I_LTH

100 + I_DD

mA

JEDEC Standard 78

T0-0.0 25093

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Table 33: AC Conditions of Test¹

Input Rise/Fall Time

Output Load

10 ns

C_L= 100 pF

T33.1 25093

1. See Figures 41 and 43

Table 34: Recommended System Power-up Timings

Symbol

Parameter

Minimum

100

Units

1

T_PU-READ

Power-up to Read Operation

Power-up to Write Operation

µs

1

T_PU-WRITE

100

µs

T0-0.0 25093

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter

Table 35: Pin Impedance (V_DD=3.3V, T_A=25°C, f=1 Mhz, other pins open)

Parameter Description

Test Condition

V_I/O= 0V

Maximum

15 pF

1

C_I/O

I/O Pin Capacitance

1

C_IN

Input Capacitance

Pin Inductance

V_IN= 0V

12 pF

2

L_PIN

20 nH

T0-0.0 25093

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. Refer to PCI spec.

DS25093B

02/13

74

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

DC Electrical Characteristics

Table 36: DC Electrical Characteristics for SST89E516RDx

T_A= -40°C to +85°C; V_DD= 4.5-5.5V; V_SS= 0V

Symbol Parameter

Test Conditions

Min

Max

Units

V_IL

Input Low Voltage

4.5 < V_DD< 5.5

-0.5

0.2V_DD

0.1

-

V

V_IH

Input High Voltage

4.5 < V_DD< 5.5

0.2V_DD

0.9

+

V_DD+ 0.5

V

V_IH1

V_OL

Input High Voltage (XTAL1, RST)

4.5 < V_DD< 5.5

V_DD= 4.5V

I_OL= 16mA

V_DD= 4.5V

0.7V_DD

Output Low Voltage (Ports 1.5, 1.6, 1.7)

1.0

V

V_OL

Output Low Voltage (Ports 1, 2, 3)¹

I

_OL= 100µA²

I_OL= 1.6mA²

0.3

0.45

1.0

V

I

_OL= 3.5mA²

V_OL1

Output Low Voltage (Port 0, ALE,

PSEN#)^1,3

V_DD= 4.5V

I_OL= 200µA²

0.3

V

I

_OL= 3.2mA²

0.45

V_OH

Output High Voltage (Ports 1, 2, 3, ALE,

PSEN#)⁴

V_DD= 4.5V

I_OH= -10µA

V_DD- 0.3

V_DD- 0.7

V_DD- 1.5

V

I

_OH= -30µA

_OH= -60µA

V_OH1

Output High Voltage (Port 0 in External

Bus Mode)⁴

V_DD= 4.5V

_OH= -200µA

_OH= -3.2mA

I

V_DD- 0.3

V_DD- 0.7

3.85

V

V_BOD

I_IL

Brown-out Detection Voltage

4.15

-75

V

Logical 0 Input Current (Ports 1, 2, 3)

V_IN= 0.4V

V_IN= 2V

µA

I_TL

Logical 1-to-0 Transition Current (Ports 1,

2, 3)⁵

-650

I_LI

Input Leakage Current (Port 0)

RST Pull-down Resistor

Pin Capacitance⁶

Power Supply Current

IAP Mode

0.45 < V_IN< V_DD-0.3

@ 1 MHz, 25°C

±10

225

15

µA

KΩ

pF

R_RST

C_IO

I_DD

40

@ 40 MHz

88

50

mA

Active Mode

@ 40 MHz

Idle Mode

@ 40 MHz

42

80

90

mA

µA

Power-down Mode (min. V_DD= 2V)

T_A= 0°C to +70°C

T_A= -40°C to +85°C

µA

T0-0.1 25093

DS25093B

02/13

75

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin:

Maximum I_OLper 8-bit port:

15mA

26mA

Maximum I_OLtotal for all outputs:71mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification.

Pins are not guaranteed to sink current greater than the listed test conditions.

2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and Ports 1 & 3.

The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions

during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed

0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt

Trigger STROBE input.

3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.

4. Capacitive loading on Ports 0 and 2 may cause the V_OHon ALE and PSEN# to momentarily fall below the V_DD- 0.7

specification when the address bits are stabilizing.

5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition cur-

rent reaches its maximum value when V_INis approximately 2V.

6. Pin capacitance is characterized but not tested. EA# is 25pF (max).

DS25093B

02/13

76

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 37: DC Electrical Characteristics for SST89V516RDx

T_A= -40°C to +85°C; V_DD= 2.7-3.6V; V_SS= 0V

Symbo

l

Unit

s

Parameter

Test Conditions

Min

Max

V_IL

V_IH

Input Low Voltage

Input High Voltage

2.7 < V_DD< 3.6

-0.5

0.7

V

0.2V_DD

0.9

+

V_DD

0.5

+

V_IH1

V_OL

Input High Voltage (XTAL1, RST)

2.7 < V_DD< 3.6

0.7V_DD

V_DD

0.5

+

V

Output Low Voltage (Ports 1.5, 1.6, 1.7)

V_DD= 2.7V

I

_OL= 16mA

1.0

V_OL

Output Low Voltage (Ports 1, 2, 3)¹

V_DD= 2.7V

_OL= 100µA²

_OL= 1.6mA²

I

0.3

V

0.45

1.0

I_OL= 3.5mA²

V_OL1

Output Low Voltage (Port 0, ALE, PSEN#)^1,3

V_DD= 2.7V

I

_OL= 200µA²

0.3

V

I_OL= 3.2mA²

0.45

V_OH

Output High Voltage (Ports 1, 2, 3, ALE,

PSEN#)⁴

V_DD= 2.7V

I

_OH= -10µA

I_OH= -30µA

_OH= -60µA

V_DD- 0.3

V_DD- 0.7

V_DD- 1.5

V

I

V_OH1

Output High Voltage (Port 0 in External Bus

Mode)⁴

V_DD= 2.7V

I_OH= -200µA

V_DD- 0.3

V_DD- 0.7

2.35

V

I

_OH= -3.2mA

V_BOD

I_IL

Brown-out Detection Voltage

Logical 0 Input Current (Ports 1, 2, 3)

Logical 1-to-0 Transition Current (Ports 1, 2, 3)⁵

Input Leakage Current (Port 0)

RST Pull-down Resistor

Pin Capacitance⁶

2.55

-75

V

V_IN= 0.4V

V_IN= 2V

µA

KΩ

pF

I_TL

-650

±10

225

15

I_LI

0.45 < V_IN< V_DD-0.3

R_RST

C_IO

I_DD

@ 1 MHz, 25°C

Power Supply Current

IAP Mode

@ 33 MHz

47

30

mA

Active Mode

@ 33 MHz

Idle Mode

@ 33 MHz

21

45

55

mA

µA

Power-down Mode (min. V_DD= 2V)

T_A= 0°C to +70°C

T_A= -40°C to +85°C

µA

T0-0.1 25093

DS25093B

02/13

77

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin:

Maximum I_OLper 8-bit port:

15mA

26mA

Maximum I_OLtotal for all outputs: 71mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current

greater than the listed test conditions.

2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and Ports 1 & 3.

The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions

during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed

0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt

Trigger STROBE input.

3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.

4. Capacitive loading on Ports 0 & 2 may cause the V_OHon ALE and PSEN# to momentarily fall below the V_DD- 0.7 spec-

ification when the address bits are stabilizing.

5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition cur-

rent reaches its maximum value when V_INis approximately 2V.

6. Pin capacitance is characterized but not tested. EA# is 25pF (max).

DS25093B

02/13

78

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

30

25

20

15

10

5

Maximum Active I

DD

Maximum Idle I

DD

Typical Active I

DD

Typical Idle I

DD

0

5

10

15

20

25

30

35

Internal Clock Frequency (MHz)

Figure 34:I_DDvs. Frequency for 3V SST89V516RDx

50

Maximum Active I

DD

40

30

20

10

0

Maximum Idle I

DD

Typical Active I

DD

Typical Idle I

DD

5

10

15

20

25

30

35

40

Internal Clock Frequency (MHz)

Figure 35:I_DDvs. Frequency for 5V SST89E516RDx

DS25093B

02/13

79

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

AC Electrical Characteristics

AC Characteristics:

(Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF;

Load Capacitance for All Other Outputs = 80pF)

Table 38: AC Electrical Characteristics (1 of 2)

T_A= -40°C to +85°C, V_DD= 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, V_SS= 0V

Oscillator

33 MHz (x1

Mode)

40 MHz (x1

Mode)

16 MHz (x2

Mode)¹

20 MHz (x2

Mode)¹

Variable

Symbol Parameter

Min

Max

33

Min

Max

40

Min

Max

Units

0

40

MHz

1/T_CLCLx1 Mode Oscillator Fre-

quency

0

16

0

20

0

20

MHz

1/2T_CLCLx2 Mode Oscillator Fre-

quency

46

5

35

2T_CLCL- 15

ns

T_LHLL

T_AVLL

ALE Pulse Width

T_CLCL- 25 (3V)

T_CLCL- 15 (5V)

T_CLCL- 25 (3V)

Address Valid to ALE Low

10

5

T_LLAX

Address Hold After ALE

Low

T_CLCL- 15 (5V)

ns

56

4T_CLCL- 65 (3V)

4T_CLCL- 45 (5V)

T_LLIV

T_LLPL

T_PLPH

ALE Low to Valid Instr In

ALE Low to PSEN# Low

PSEN# Pulse Width

55

5

T_CLCL- 25 (3V)

10

60

T

_CLCL- 15 (5V)

66

3T_CLCL- 25

(3V)

3T_CLCL- 15

(5V)

35

25

3T_CLCL- 55 (3V)

3T_CLCL- 50 (5V)

ns

T_PLIV

PSEN# Low to Valid Instr

In

25

10

ns

0

T_PXIX

T_PXIZ

Input Instr Hold After

PSEN#

T_CLCL- 5 (3V)

T_CLCL- 15 (5V)

ns

Input Instr Float After

PSEN#

ns

22

17

T_CLCL- 8

T_PXAV

T_AVIV

PSEN# to Address valid

Address to Valid Instr In

72

10

5T_CLCL- 80 (3V)

5T_CLCL- 60 (5V)

10

65

10

T_PLAZ

T_RLRH

PSEN# Low to Address

Float

142

6T_CLCL- 40 (3V)

6T_CLCL- 30 (5V)

ns

RD# Pulse Width

120

6T_CLCL- 40 (3V)

6T_CLCL- 30 (5V)

T_WLWHWrite Pulse Width (WE#)

T_RLDVRD# Low to Valid Data In

62

5T_CLCL- 90 (3V)

DS25093B

02/13

80

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 38: AC Electrical Characteristics (Continued) (2 of 2)

T_A= -40°C to +85°C, V_DD= 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, V_SS= 0V

Oscillator

33 MHz (x1

Mode)

40 MHz (x1

Mode)

16 MHz (x2

Mode)¹

20 MHz (x2

Mode)¹

Variable

Symbol Parameter

Min

Max

Min

Max

Min

Max

Units

ns

75

5T_CLCL- 50 (5V)

0

ns

T_RHDX

T_RHDZ

Data Hold After RD#

36

2T_CLCL- 25 (3V)

2T_CLCL- 12 (5V)

8T_CLCL- 90 (3V)

8T_CLCL- 50 (5V)

9T_CLCL- 90 (3V)

9T_CLCL- 75 (5V)

ns

Data Float After RD#

38

ns

152

183

116

ns

T_LLDV

T_AVDV

T_LLWL

T_AVWL

ALE Low to Valid Data In

Address to Valid Data In

150

ns

150

90

ns

66

46

3T_CLCL- 25 (3V) 3T_CLCL+ 25 (3V)

3T_CLCL- 15 (5V) 3T_CLCL+ 15 (5V)

ns

ALE Low to RD# or WR#

Low

60

4T_CLCL- 75 (3V)

ns

Address to RD# or WR#

Low

70

5

4T_CLCL- 30 (5V)

T_CLCL- 27 (3V)

T_CLCL- 20 (5V)

7T_CLCL- 70 (3V)

7T_CLCL- 50 (5V)

T_CLCL- 20

ns

3

T_WHQXData Hold After WR#

T_QVWHData Valid to WR# High

142

10

125

5

T_QVWXData Valid to WR# High to

Low

Transition

RD# Low to Address Float

0

ns

T_RLAZ

RD# to WR# High to ALE

High

5

55

T_CLCL- 25 (3V) T_CLCL+ 25 (3V)

T_WHLH

10

40

T_CLCL- 15 (5V) T_CLCL+ 15 (5V)

ns

T0-0.0 25093

1. Calculated values are for x1 Mode only

DS25093B

02/13

81

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Explanation of Symbols

Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for the name of a signal or the logical status of that sig-

nal. The following is a list of all the characters and what they stand for.

A: Address

Q: Output data

C: Clock

R: RD# signal

D: Input data

T: Time

H: Logic level HIGH

I: Instruction (program memory contents)

L: Logic level LOW or ALE

P: PSEN#

V: Valid

W: WR# signal

X: No longer a valid logic level

Z: High Impedance (Float)

For example:

_AVLL= Time from Address Valid to ALE Low

_LLPL= Time from ALE Low to PSEN# Low

T

DS25093B

02/13

82

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

T

LHLL

ALE

T

PLPH

T

LLIV

AVLL

T

LLPL

T

PLIV

PSEN#

T

PXAV

T

PLAZ

T

PXIZ

PXIX

INSTR IN

T

LLAX

T

A0 - A7

PORT 0

PORT 2

A0 - A7

T

AVIV

A8 - A15

1273 F32.0

Figure 36:External Program Memory Read Cycle

T

LHLL

ALE

T

WHLH

PSEN#

T

LLDV

T

RLRH

T

LLWL

RD#

T

LLAX

T

RHDZ

RLDV

T

AVLL

T

RLAZ

T

RHDX

A0-A7 FROM PCL

A0-A7 FROM RI or DPL

DATA IN

INSTR IN

PORT 0

PORT 2

T

AVWL

T

AVDV

P2[7:0] or A8-A15 FROM DPH

A8-A15 FROM PCH

1273 F33.0

Figure 37:External Data Memory Read Cycle

DS25093B

02/13

83

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

T

LHLL

ALE

T

WHLH

PSEN#

T

WLWH

LLWL

WR#

T

LLAX

T

AVLL

QVWX

WHQX

T

QVWH

A0-A7 FROM RI or DPL

PORT 0

PORT 2

DATA OUT

A0-A7 FROM PCL

INSTR IN

T

AVWL

P2[7:0] or A8-A15 FROM DPH

A8-A15 FROM PCH

1273 F34.0

Figure 38:External Data Memory Write Cycle

Table 39: External Clock Drive

Oscillator

40MHz

12MHz

Variable

Symbol

1/T_CLCL

T_CLCL

Parameter

Min

Max

Min

Max

Min

Max

Units

Oscillator Frequency

0

40

MHz

ns

83

25

T_CHCX

T_CLCX

High Time

Low Time

Rise Time

Fall Time

8.75

0.35T_CLCL

0.65T_CLCL

ns

T_CLCH

T_CHCL

20

10

ns

T0-0.0 25093

V

DD - 0.5

0.7V

DD

- 0.1

T

CHCX

0.2 V

0.45 V

DD

T

CLCX

CLCH

CHCL

T

CLCL

1273 F35.0

Figure 39:External Clock Drive Waveform

DS25093B

02/13

84

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 40: Serial Port Timing

Oscillator

12MHz

40MHz

Variable

Symbol Parameter

Min Max Min Max

Min

Max

Units

µs

T_XLXL

Serial Port Clock Cycle Time

1.0

0.3

12T_CLCL

T_QVXH

Output Data Setup to Clock Rising 700

Edge

117

10T_CLCL- 133

ns

T_XHQX

Output Data Hold After Clock Ris- 50

ing Edge

2T_CLCL- 117

2T_CLCL- 50

0

ns

0

T_XHDX

T_XHDV

Input Data Hold After Clock Rising

Edge

0

Clock Rising Edge to Input Data

Valid

700

117

10T_CLCL- 133

ns

T0-0.0 25093

INSTRUCTION

0

1

2

3

4

5

6

7

8

ALE

T

XLXL

CLOCK

T

XHQX

T

QVXH

0

1

2

3

4

5

6

7

OUTPUT DATA

T

XHDX

T

SET TI

WRITE TO SBUF

INPUT DATA

XHDV

VALID

SET R I

CLEAR RI

1273 F36.0

Figure 40:Shift Register Mode Timing Waveforms

V

IHT

V

HT

V

LT

V

ILT

1273 F37.0

AC Inputs during testing are driven at V

(V

IHT DD

-0.5V) for Logic "1" and

V

(0.45V) for a Logic "0". Measurement reference points for inputs and

ILT

outputs are at V

(0.2V

+ 0.9) and V (0.2V

- 0.1)

HT

DD LT

DD

Note: V - V

Test

HIGH Test

HT HIGH

V

- V

-V

LT

LOW

IHT INPUT

- V

LOW Test

ILT INPUT

Figure 41:AC Testing Input/Output Test Waveform

DS25093B

02/13

85

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

V

+0.1V

-0.1V

LOAD

V

-0.1V

OH

OL

Timing Reference

Points

V

LOAD

V

+0.1V

LOAD

1273 F38.0

For timing purposes, a port pin is no longer floating when a 100 mV

change from load voltage occurs, and begins to float when a 100 mV

change from the loaded V

/V

level occurs. I /I = ± 20mA.

OH OL

OL OH

Figure 42:Float Waveform

TO TESTER

TO DUT

C

L

1273 F39.0

Figure 43:A Test Load Example

V

DD

I

DD

V

DD

P0

DD

V

DD

RST

EA#

SST89x516RDx

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V

SS

1273 F40.0

All other pins disconnected

Figure 44:I_DDTest Condition, Active Mode

DS25093B

02/13

86

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

V

DD

I

DD

V

DD

P0

DD

RST

EA#

SST89x516RDx

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V

SS

1273 F41.0

All other pins disconnected

Figure 45:I_DDTest Condition, Idle Mode

V

DD

I

DD

V

DD

P0

DD

RST

EA#

SST89x5xxRDx

XTAL2

XTAL1

(NC)

V

SS

1273 F42.0

All other pins disconnected

Figure 46:I_DDTest Condition, Power-down Mode

Table 41: Flash Memory Programming/Verification Parameters¹

Parameter²

Max

150

100

30

Units

ms

µs

Chip-Erase Time

Block-Erase Time

Sector-Erase Time

Byte-Program Time³

Select-Block Program Time

Re-map or Security bit Program Time

50

500

80

ns

µs

T0-0.1 25093

1. For IAP operations, the program execution overhead must be added to the above timing parameters.

2. Program and Erase times will scale inversely proportional to programming clock frequency.

3. Each byte must be erased before programming.

DS25093B

02/13

87

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Product Ordering Information

SST 89

E

516RD2

-

33

-

C

-

TQJE

-

XX XX XXXXXX

-

XX

-

X

XXXX

Environmental Attribute

E¹= non-Pb

F¹= non-Pb / non-Sn contact finish

Package Modifier

I = 40 pins

J = 44 pins

Package Type

P = PDIP

N = PLCC

Q = WQFN

TQ = TQFP

Operation Temperature

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Operating Frequency

33 = 0-33MHz

40 = 0-40MHz

Feature Attribute

2 = Port 4 present

Feature Set and Flash Memory Size

516RD = C52 feature set + 64(72)

KByte

Note: Number in parenthesis includes an addi-

tional 8 KByte flash which can be enabled.

Voltage Range

E = 4.5-5.5V

V = 2.7-3.6V

Product Series

89 = C51 Core

1. Environmental suffix “E” denotes non-Pb sol-

der. Environmental suffix “F” denote non-Pb

/non-Sn solder. SST non-Pb / non-Sn solder

devices are “RoHS Compliant”.

DS25093B

02/13

88

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Valid Combinations

Valid combinations for SST89E516RD2

SST89E516RD2-40-C-NJE

SST89E516RD2-40-C-TQJE

SST89E516RD2-40-I-NJE

SST89E516RD2-40-I-TQJE

Valid combinations for SST89V516RD2

SST89V516RD2-33-C-NJE

SST89V516RD2-33-C-TQJE

SST89V516RD2-33-I-NJE

SST89V516RD2-33-I-TQJE

Valid combinations for SST89E516RD

SST89E516RD-40-C-PIE

SST89E516RD-40-C-QIF

SST89E516RD-40-I-QIF

Valid combinations for SST89V516RD

SST89V516RD-33-C-PIE

SST89V516RD-33-C-QIF

SST89V516RD-33-I-QIF

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combi-

nations.

DS25093B

02/13

89

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Packaging Diagrams

TOP VIEW

SIDE VIEW

BOTTOM VIEW

See notes

2 and 3

0.2

Pin #1

0.5 BSC

6.00 ± 0.10

4.1

0.075

0.30

0.18

0.45

0.35

0.05 Max

6.00 ± 0.10

0.80

0.70

Note: 1. Complies with JEDEC JEP95 MO-220I, variant WJJD-5 except external paddle nominal dimensions.

2. From the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch.

1mm

3. The external paddle is electrically connected to the die back-side and possibly to certain V leads.

SS

This paddle should be soldered to the PC board; it is suggested to connect this paddle to the V of the unit.

SS

Connection of this paddle to any other voltage potential will result in shorts and/or electrical malfunction of the device.

4. Untoleranced dimensions are nominal target dimensions.

40-wqfn-6x6-QI-1

5. All linear dimensions are in millimeters (max/min).

Figure 47:40-contact Very-very-thin Quad Flat No-lead (WQFN)

SST Package Code: QI

DS25093B

02/13

90

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

40

C

L

.600

.625

1

Pin #1 Identifier

.530

.557

2.020

2.070

.065

.075

12°

4 places

Base

Plane

.220 Max.

Seating

Plane

.015 Min.

0°

15°

.008

.012

.100 †

.200

.063

.090

.045

.055

.015

.022

.100 BSC

.600 BSC

Note:

1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent.

† = JEDEC min is .115; SST min is lessstringent

2. All linear dimensions are in inches (min/max).

40-pdip-PI-7

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

Figure 48:40-pin Plastic Dual In-line Pins (PDIP)

SST Package Code: PI

DS25093B

02/13

91

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

TOP VIEW

SIDE VIEW

BOTTOM VIEW

.685

.695

.646 †

.656

Optional

Pin #1 Identifier

.147

.158

.020 R.

MAX.

.042

.048

.025

.045

.042

.056

R.

x45°

1

44

.042

.048

.013

.021

.685

.695

.646 †

.656

.500 .590

REF. .630

.026

.032

.050

BSC.

.020 Min.

.100

.112

.050

BSC.

.026

.032

.165

.180

44.PLCC.NJ-ILL.6

Note:

1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent.

† = JEDEC min is .650; SST min is lessstringent

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: ± 4 mils.

Figure 49:44-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NJ

DS25093B

02/13

92

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

44

34

Pin #1

Identifier

1

33

.30

.45

10.00 ± 0.10

.80 BSC

12.00 ± 0.25

11

23

.09

.20

12

22

10.00 ± 0.10

12.00 ± 0.25

.95

1.05

1.2

max.

0°- 7°

.45

.75

.05

.15

1.00 ref

Note:

1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±0.05) mm.

44-tqfp-TQJ-7

4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.

1mm

Figure 50:44-lead Thin Quad Flat Pack (TQFP)

SST Package Code: TQJ

DS25093B

02/13

93

FlashFlex MCU

SST89E516RD2 / SST89E516RD

SST89V516RD2 / SST89V516RD

Data Sheet

Table 42: Revision History

Revision

Description

Date

00

Mar 2005

•

Initial Release of S71273 data sheet.

SST89E/V516RD2 devices were previously released in S71255-00-

000

S71273 and

S71273(01): Added 40-WQFN (QI) package and associated MPNs

•

Added SST89E/V516RD PDIP devices and associated MPNs

Clarified the solder temperature profile under “Absolute Maximum

Stress Ratings” on page 73

•

Added RoHS compliance information on page 1 and in the “Product

Ordering Information” on page 88

•

Removed references to External Host Mode programming

Corrected MPN breakdown definition for “2” to read “Port 4 present”

Corrected the SPI control Register definition for CPHA on page 30

Status change from Preliminary Specifications to Data sheet

Removed NJ, TQJ, and PI from Valid Combinations on page 78

01

02

Mar 2005

Oct 2006

Removed valid combination SST89E516RD-40-I-PIE and

SST89V516RD-33-I-PIE on page 78

03

A

Jan 2007

Nov 2011

•

Replaced FlashFlex51 with FlashFlex globally

Applied new document format

Released document under letter revision system

Updated spec number from S71273 to DS25093

Removed “Not recommended for new designs” statement on page 1.

B

Feb 2013

ISBN: 978-1-62076-989-8

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

DS25093B

02/13

94


型号：	SST89V516RD2
厂家：	MICROCHIP
描述：	FlashFlex MCU FlashFlex MCU
文件：	总94页 (文件大小：762K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST89V516RD2 [MICROCHIP]

相关型号：

SST89V516RD2-33-C-NI

SST89V516RD2-33-C-NJ

SST89V516RD2-33-C-NJE

SST89V516RD2-33-C-NJE

SST89V516RD2-33-C-NJE-T

SST89V516RD2-33-C-PI

SST89V516RD2-33-C-PIE

SST89V516RD2-33-C-PJ

SST89V516RD2-33-C-TQI

SST89V516RD2-33-C-TQJ

SST89V516RD2-33-C-TQJE

SST89V516RD2-33-C-TQJE