SY100EP196VTG-TR [MICROCHIP]
ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32;
| 型号： | SY100EP196VTG-TR |
| 厂家： | 
MICROCHIP |
| 描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 输出元件 逻辑集成电路 延迟线 |
| 文件： | 总18页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ECLPro®
SY100EP196V
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY CHIP WITH
FINE TUNE CONTROL
FEATURES
■ Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
ECL Pro®
■ Maximum frequency > 2.5GHz
■ Programmable range: 2.2ns to 12.2ns
■ 10ps increments
DESCRIPTION
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
■ 30ps fine tuning range
■ PECL mode operating range: V = 3.0V to 5.5V
CC
with V = 0V
EE
■ NECL mode operating range: V = 0V
CC
with V = –3.0V to –5.5V
EE
■ Open input default state
■ Safety clamp on inputs
■ A logic high on the /EN pin will force Q to logic low
■ D[0:10] can accept either ECL, CMOS, or TTL inputs
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
■ V output reference voltage
BB
■ Available in a 32-pin TQFP package
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
CROSS REFERENCE TABLE
APPLICATIONS
■ Clock de-skewing
■ Timing adjustment
■ Aperture centering
Micrel Semiconductor
SY100EP196VTI
ON Semiconductor
MC100EP196FA
SY100EP196VTITR
MC100EP196FAR2
TYPICAL PERFORMANCE
TYPICAL APPLICATIONS CIRCUIT
Delay vs. Tap
12000
Data Signal
of Unknown Phase
D
Q+
10000
8000
6000
4000
2000
0
Flip-Flop
SY100EP196V
CLOCK+
IN
Q
CK
Q–
/IN
CLOCK–
Fine Tune Voltage
FTUNE /Q
D[9:0]
CONTROL
LOGIC
0
200 400 600 800 1000 1200
TAP (DIGITAL WORD)
ECL Pro is a registered trademark of Micrel, Inc.
Rev.: B
Amendment:/0
M0644-012704
1
Issue Date: January 2004
ECL Pro®
SY100EP196V
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package Operating
Package
Marking
32 31 30 29 28 27 26 25
Part Number
Type
T32-1
T32-1
Range
VEE
D0
VCC
Q
/Q
VCC
VCC
FTUNE
D8
D9
D10
IN
1
2
3
4
5
6
24
23
22
21
20
19
SY100EP196VTI
SY100EP196VTITR
Industrial
Industrial
SY100EP196V
SY100EP196V
(1)
/IN
Note:
1. Tape and Reel.
VBB
VEF
VCF
7
8
18
17
9 10 11 12 13 14 15 16
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
M0644-012704
2
ECL Pro®
Micrel
SY100EP196V
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
4, 5
6
IN, /IN
VBB
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC-
coupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01µF
capacitor. Limit current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the “Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
8
9, 24, 28
10
VCF
VEE
LEN
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
Most Negative Supply. Supply ground for PECL systems.
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
12
SETMIN
SETMAX
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
14, 15
VCC
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1µF and
0.01µF low ESR capacitors.
CASCADE,
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
17
FTUNE
Q, /Q
Voltage Control Input: By varying the voltage at this pin from VCC through VEE, the delay
may be fine tuned by approximately ±15ps.
20, 21
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
M0644-012704
3
ECL Pro®
SY100EP196V
Micrel
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (V
)
Supply Voltage (V
)
CC
CC
PECL Mode (V =0V)............................. –0.5V to +6.0V
PECL Mode (V =0V)............................. +3.0V to +5.5V
EE
EE
Supply Voltage (V
)
Supply Voltage (V
)
EE
EE
NECL Mode (V =0V) ............................ +0.5V to –6.0V
NECL Mode (V =0V) ............................ –3.0V to –5.5V
CC
CC
Any Input Voltage (V )
Ambient Temperature (T ) ......................... –40°C to +85°C
IN
A
PECL Mode .......................................–0.5V to V +0.5V
Package Thermal Resistance
CC
NECL Mode....................................... +0.5V to V –0.5V
TQFP-32 (θ
)
EE
JA
ECL Output Current (I
)
Still-air .............................................................50°C/W
500lfpm............................................................42°C/W
OUT
Continuous .............................................................50mA
Surge....................................................................100mA
TQFP-32 (θ ).....................................................20°C/W
JC
I
Sink/Source Current ..........................................±0.5mA
BB
Lead Temperature (soldering, 10 sec.) ................... +300°C
Storage Temperature (T ) ....................... –65°C to +150°C
S
(3)
ESD Rating ........................................................... >1.5kV
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply Voltage (PECL)
3.0
4.5
3.3
5.0
3.6
5.5
V
V
VEE
Power Supply Voltage (NECL)
Power Supply Current(4)
–3.6
–5.5
–3.3
–5.0
–3.0
–4.5
V
V
IEE
No Load, Over Supply Voltage
150
175
mA
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Required 500lfpm air flow when using +5V or –5V power supply.
M0644-012704
4
ECL Pro®
Micrel
SY100EP196V
(100kEP) LVPECL DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V, VEE = 0V; TA = –40°C to +85°C(5, 6)
Symbol
VOH
Parameter
Condition
Min
2155
1355
Typ
2280
1480
Max
2405
1605
Units
mV
Output HIGH Voltage
Output LOW Voltage
Figures 2, 3, 6
Figures 2, 3, 6
Figures 1, 4
VOL
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
2075
1815
2000
2420
mV
mV
mV
VIL
Input LOW Voltage
Figures 1, 4
PECL
CMOS
TTL
1355
1675
1485
800
mV
mV
mV
VBB
Output Voltage Reference
Input Select Voltage
Mode Connection
1775
1610
1900
2.0
1875
1720
2000
1975
1825
2100
3.3
mV
mV
mV
V
VCF
VEF
VIHCMR
Input HIGH Voltage Common
Mode Range(7)
Figure 5
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
IN
/IN
0.5
–150
µA
µA
Notes:
5. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +0.3V to –2.2V.
CC
EE
7.
V
maximum varies 1:1 with V . The V
range is referenced to the most positive side of the differential input signal.
IHCMR
IHCMR
CC
M0644-012704
5
ECL Pro®
SY100EP196V
Micrel
(100kEP) PECL DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V; TA = –40°C to +85°C(8, 9)
Symbol
VOH
Parameter
Condition
Min
3855
3055
Typ
3980
3180
Max
4105
3305
Units
mV
Output HIGH Voltage
Output LOW Voltage
Figures 2, 3, 6
Figures 2, 3, 6
Figures 1, 4
VOL
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
3775
2750
2000
4120
mV
mV
mV
VIL
Input LOW Voltage
Figures 1, 4
Figure 5
PECL
CMOS
TTL
3055
3375
2250
800
mV
mV
mV
VBB
Output Voltage Reference
3475
2.0
3575
3675
5.0
mV
V
VIHCMR
Input HIGH Voltage Common
Mode Range(10)
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
IN
/IN
0.5
–150
µA
µA
(100kEP) NECL DC ELECTRICAL CHARACTERISTICS
VCC = 0V, VEE = –5.5V to –3.0V; TA = –40°C to +85°C(8)
Symbol
VOH
Parameter
Condition
Min
Typ
Max
Units
mV
mV
mV
mV
mV
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage NECL
Input LOW Voltage NECL
Output Voltage Reference
Figures 2, 3
Figures 2, 3
Figures 1, 4
Figures 1, 4
–1145 –1020 –895
–1945 –1820 –1695
VOL
VIH
–1225
–1945
–880
VIL
–1625
VBB
–1525 –1425 –1325
VIHCMR
Input HIGH Voltage Common
Mode Range(11)
Figure 5
VEE+2.0
0.0
IIH
IIL
Input HIGH Current
150
µA
Input LOW Current
IN
/IN
0.5
–150
µA
µA
Notes:
8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
9. Input and output parameters vary 1:1 with V . V can vary +2.0V to –0.5V.
CC
EE
10. V
11. V
maximum varies 1:1 with V . The V
range is referenced to the most positive side of the differential input signal.
IHCMR
IHCMR
CC
IHCMR
IHCMR
minimum varies 1:1 with V . The V
range is referenced to the most positive side of the differential input signal.
EE
M0644-012704
6
ECL Pro®
Micrel
SY100EP196V
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C(12, 13)
TA = –40°C
Typ
TA = +25°C
Typ
TA = +85°C
Typ
Symbol
fMAX
Parameter
Maximum Frequency(14)
Propagation Delay
Min
Max
Min
Max
Min
Max
Unit
2.5
2.5
2.5
GHz
tPD
IN to Q; D[0-10]=0
1650
2000
2450
1800
2050
2600
1950
2250
2750
ps
ps
ps
ps
IN to Q; D[0-10]=1023
/EN to Q: D[0-10]=0
D10 to CASCADE
9500 11500 13500 9800 12200 14000 10600 13300 15800
1600
300
2150
420
2600
500
1800
325
2300
450
2800
550
2000
325
2500
525
3000
625
tRANGE
Programmable Range
tPD(max)-tPD(min)
7850
9450
8200 10000
8850 10950
ps
∆t
Step Delay(15)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
9
25
42
75
142
296
532
1080
2100
4250
10
26
42
10
27
43
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
80
81
143
300
540
1095
2150
4300
150
310
565
1140
2250
4500
Lin
Linearity(16)
±10
±10
±10
%LSB
tSKEW
Duty Cycle Skew(17)
tPHL-tPLH
25
ps
tS
Setup Time
D to LEN
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
ps
ps
ps
D to IN(18)
/EN to IN(19)
tH
tR
Hold Time
LEN to D
200
400
60
250
200
400
100
280
200
400
80
300
ps
ps
IN to /EN(20)
Release Time
/EN to IN(21)
SETMAX to LEN
SETMIN to LEN
500
250
200
ps
ps
ps
400
350
200
275
400
350
400
350
300
335
Cycle-to-Cycle Jitter(22)
0.2
< 1
0.2
< 1
0.2
< 1
psrms
mV
tJIT
VPP
Input Voltage Swing (Differential)
150
800
1200
150
800
1200
150
800
1200
tr
tf
Output Rise/Fall Time
20% to 80% (Q)
180
180
250
250
210
210
300
300
230
230
325
325
ps
ps
20% to 80% (CASCADE)
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source.
14. Refer to “Typical Operating Characteristics” for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
M0644-012704
7
ECL Pro®
SY100EP196V
Micrel
TYPICAL OPERATING CHARACTERISTICS
Supply Current
vs. Temperature
Q, /Q Output Swing
vs. Frequency
Propagation Delay
vs. FTUNE Voltage
800
700
600
500
400
300
200
100
0
15
10
5
180
160
140
120
100
80
VCC = 5.5V
VCC = 3.3V
VCC = 3.0V
VCC = 5.0V
0
-5
-10
-15
-20
-25
60
–40
25
40
20
85
0
0
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
0
0.5
1
1.5
2
2.5
3
3.5
-40 -20
0
20 40 60 80 100
FTUNE VOLTAGE (V)
TEMPERATURE (°C)
M0644-012704
8
ECL Pro®
Micrel
SY100EP196V
VCC
Q, CASCADE
/Q, /CASCADE
SY100EP196V
Figure 2. Emitter Output Structure
Figure 1a. Differential Input Structure
VCC
SY100EP196V
Q
/Q
/EN
LEN
SETMIN
SETMAX
D[0:10]
VOH
CASCADE
/CASCADE
VBB
VOL
0V
Figure 3a. Output Levels, PECL, LVPECL
75k
0V
VOH
Q
/Q
VOL
CASCADE
/CASCADE
Figure 1b. Single-Ended Input Structure
Figure 3b. Output Levels, NECL
M0644-012704
9
ECL Pro®
SY100EP196V
Micrel
VCC
VIH(MAX)
0V
VIH(MAX)
Invalid
Invalid
Logic High
Invalid
Logic High
Invalid
VIH(MIN)
VIL(MAX)
VIH(MIN)
VIL(MAX)
Logic Low
Logic Low
VIL(MIN)
0V
VIL(MIN)
VEE
Invalid
Invalid
Figure 4a. Input Levels, PECL
Figure 4c. Input Levels, NECL
IN
VIHCMR
Invalid
VCC
/IN
Logic High
Invalid
0V
VIH(MIN)
VIL(MAX)
Figure 5a. Input Common Mode, PECL, LVPECL
Logic Low
0V
Invalid
0V
IN
VIHCMR
Figure 4b. Input Levels, CMOS, TTL
/IN
VIHCMR
Figure 5b. Input Common Mode, NECL
M0644-012704
10
ECL Pro®
Micrel
SY100EP196V
TERMINATING PECL
+3.3V
R1
R1
+3.3V
130Ω
130Ω
+3.3V
ZO = 50Ω
ZO = 50Ω
R2
82Ω
R2
82Ω
Vt = VCC —2V
Figure 6a. Parallel Termination—Thevenin Equivalent
Note:
1. For +5.0V systems: R1 = 82Ω, R2 = 130Ω.
+3.3V
+3.3V
Z = 50Ω
Z = 50Ω
50Ω
50Ω
Source
Destination
C1 (optional)
0.01µF
50Ω
R
b
Figure 6b. Three-Resistor “Y-Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R resistor sets the DC bias voltage, equal to V . For +3.3V systems R = 46Ω to 50Ω. For +5V systems, R = 110Ω.
b
t
b
b
+3.3V
+3.3V
R1
130Ω
R1
130Ω
+3.3V
+3.3V
Q
ZO = 50Ω
50Ω
/Q
VBB
Vt = VCC —2V
0.01µF
+3.3V
R2
82Ω
R2
82Ω
Figure 6c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. Micrel's differential I/O logic devices include a V reference pin .
BB
3. Connect unused input through 50Ω to V . Bypass with a 0.01µF capacitor to V , not GND, as PECL is referenced to V .
CC
BB
CC
M0644-012704
11
ECL Pro®
SY100EP196V
Micrel
VCC +3.3V
D[0:10]
VCC
LVPECL
Signals
0.01µF
PECL
Output
IN
VCF
VEF
/IN
SY100EP196V
VBB
VEE 0V
SY100EP196V
Figure 9b. Connecting LVPECL Signals
to the D Inputs
Figure 7a. Interfacing to a
Single-Ended PECL Signal
VCC +3.3V or +5.0V
VCC
0.01µF
CMOS
D[0:10]
Inputs
IN
NC VCF
PECL
/IN
Output
NC VEF
SY100EP196V
VBB
SY100EP196V
VEE 0V
Figure 7b. Interfacing to and Inverting
a Single-Ended PECL Signal
Figure 9c. Connecting CMOS Signals
to the D Inputs
Note: V and V are not connected
CF
EF
IN
VCC +3.3V
VCC
0.01µF
/IN
50
50
VBB
TTL
Inputs
D[0:10]
VCF
SY100EP196V
Figure 8. Re-Biasing an AC-Coupled Signal
NC VEF
1.5k
SY100EP196V
VCC +5.0V
0V
VEE 0V
PECL
D[0:10]
Signals
Figure 9d. Connecting TTL Signals
to the D Inputs with V = 3.3V
CC
VCF
VCC +5.0V
VEF
SY100EP196V
TTL
D[0:10]
Inputs
VEE 0V
Figure 9a. Connecting PECL Signals
to the D Inputs
VCF
NC VEF
500
SY100EP196V
0V
VEE 0V
Figure 9e. Connecting TTL Signals
to the D Inputs with V = 5.0V
CC
M0644-012704
12
ECL Pro®
Micrel
SY100EP196V
FUNCTIONAL DESCRIPTION
SY100EP196V is a programmable delay line, varying the Digital Control Logic Standard
delay of a PECL or NECL input signal by any amount between
about 2.2ns and 12.2ns. A 10-bit digital control register affords
delay steps of approximately 10ps.
SY100EP196V implements the delay using a multiplexer
chain and a set of fixed delay elements. Under digital control,
various subsets of the delay elements are included in the
signal chain. To simplify interfacing, the 10-bit digital delay
control word interfaces to PECL, CMOS, or TTL interface
standards.
When used in systems where V
connects to ground,
EE
SY100EP196V may interface either to PECL, CMOS, or TTL
on its D[0:10] inputs. To this end, the VCF pin sets the
threshold at which the D inputs switch between logic low and
logic high.
As shown in Table 3, connecting V
to V
sets the
CF
EF
threshold to PECL (if V is 5V) or LVPECL (if V is 3.3V).
CC
CC
Leaving V
and V open yields a threshold suitable for
CF
EF
detecting CMOS output logic levels. Leaving V open and
EF
Since multiplexers must appear in the delay path,
SY100EP196V has a minimum delay of about 2.2ns. Delays
below this value are not possible. In addition, when cascading
multiple SY100EP196V to extend the delay range, the
minimum delay is about 2.2ns times the number of
SY100EP196V in cascade. An eleventh control bit, D[10],
along with the CASCADE and /CASCADE outputs and the
SETMIN and SETMAX inputs, simplifies the task of cascading.
connecting V to a 1.5V source allows the D inputs to accept
TTL signals.
CF
Logic Standard
ECL, PECL
CMOS
VCF Connects To
VEF
No Connect
1.5V Source
TTL
Signal Path Logic Standard
Table 3. Digital Control Standard Truth Table
The signal path, from IN, /IN to Q, /Q, interfaces to PECL,
LVPECL, or NECL signals, as shown in Table 6. The choice
of signal path logic standard may limit possible choices for
the delay control inputs, D.
If a 1.5V source is not available, connecting V to V
CF
EE
through an appropriate resistor will bias V at about 1.5V.
CF
The value of this resistor depends on the V
indicated in Table 4.
supply, as
CC
Input Enable
The /EN input gates the signal at IN, /IN. When disabled,
the input is effectively gated out, just as if a logic low was
being provided to SY100EP196V.
VCC
3.3V
5.0V
Resistor Value
1.5kΩ
500Ω
/EN
L
Value at Q, /Q
IN, /IN Delayed
Table 4. Resistor Values for TTL Input
Cascade Logic
H
Logic Low Delayed
SY100EP196V is designed to ease cascading multiple
devices in order to achieve a greater delay range. The SETMIN
and SETMAX pins accomplish this, as set out in the
applications section below. SETMIN and SETMAX override
the delay by changing the value in the D latch register. Table
5 lists the action of these pins.
Table 1. /EN Truth Table
Digital Control Latch
SY100EP196V can capture the digital delay control word
into its internal 11-bit latch, 10 bits for D[0:9], and an extra bit
for the D[10] cascade control. The LEN input controls the
action of this latch, as per Table 2.
Note that the LEN input is always PECL, LVPECL, or
NECL, the same as the IN, /IN signal pair. The 11-bit delay
control word, however, may also be CMOS or TTL.
SETMIN
SETMAX
Nominal Delay (ps)
As per D Latch
2200 + 10 × 1024
2200
L
L
L
H
L
H
H
LEN
L
Latch Action
Pass Through D[0:10]
Latch D[0:10]
H
Not Allowed
H
Table 5. SETMIN and SETMAX Action
Table 2. LEN Truth Table
The nominal delay value is based on the binary value in
D[0:9], where D[0] is the least significant bit, and D[9] is the
most significant bit. This delay from IN, /IN to Q, /Q is about:
∆t = 2200 +10 × value D 9:0 + delay FTUNE ,ps
(
)
[
]
)
(
M0644-012704
13
ECL Pro®
SY100EP196V
Micrel
Fine Tune Control
In addition to the digital delay control, the FTUNE input
permits a continuous variation in delay. Though it may be
set to any voltage between V and V , most of the delay
“Typical Operating Characteristics.” For convenience, a V
CC
of 3.3V is assumed. Typically, the FTUNE input will be fed
by a DAC whose purpose is to provide extremely fine delay
under digital control.
CC
EE
EE
variation occurs between V
and V + 1.5V. Refer to
EE
Signal Path Logic Standard
VCC
VEE
0V
Delay Control Input Choices
PECL, CMOS, TTL
LVPECL, CMOS, TTL
NECL
PECL
LVPECL
NECL
+4.5V to +5.5V
+3.0V to +3.6V
0V
0V
–3.0 to –5.5V
Table 6. Signal Path Logic Standard
M0644-012704
14
ECL Pro®
Micrel
SY100EP196V
APPLICATIONS INFORMATION
For best performance, use good high frequency layout Setting D Input Logic Thresholds
techniques, filter V supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP196V data inputs and outputs.
CC
As explained earlier, in all designs where the
SY100EP196V V supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
EE
PECL or LVPECL. Figures 9 show how to connect V and
CF
V
Supply
V
for all possible cases.
BB
EF
The VBB pin is an internally generated supply, and is Cascading
available for use only by the SY100EP196V. When unused,
this pin should be left unconnected. The two common uses
Two or more SY100EP196V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP196V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP196V. Using this internal circuitry, SY100EP196V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP196V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
for V are to handle a single-ended PECL input, and to re-
BB
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, V is used
BB
to bias the unused input. Please refer to Figures 9. The
PECL signal driving SY100EP196V may optionally be
inverted in this case.
When the signal is AC-coupled, V is used, as shown
BB
in Figure 10, to re-bias IN, /IN. This ensures that
SY100EP196V inputs are within its acceptable common
mode range.
In all cases, V
current sinking or sourcing must be
BB
limited to 0.5mA or less.
Control Word (11bits)
DAC
SY100EP196V
SY100EP196V
C[10]
FTUNE
D[10]
FTUNE
C[9:0]
D[9:0]
IN
#2
#1
IN
/IN
Q
/Q
Q
/IN
/Q
SETMIN
SETMAX
/CASCADE
CASCADE
Figure 10a. Cascading Two SY100EP196V
Control Word (12bits)
DAC
SY100EP196V
SY100EP196V
SY100EP196V
C[11]
C[10]
D[10]
FTUNE
D[10]
D[9:0]
IN
FTUNE
C[9:0]
#3
#2
#1
IN
/IN
Q
/Q
IN
Q
Q
/IN
/Q
/IN
/Q
SETMIN
/CASCADE
SETMIN
SETMAX
/CASCADE
SETMAX
CASCADE
CASCADE
Figure 10b. Cascading Three SY100EP196V
15
M0644-012704
ECL Pro®
SY100EP196V
Micrel
Control Word (12bits)
DAC
SY100EP196V
SY100EP196V
SY100EP196V
SY100EP196V
C[11]
C[10]
D[10]
FTUNE
D[10]
D[9:0]
IN
FTUNE
C[9:0]
IN
/IN
Q
/Q
IN
/IN
Q
/Q
IN
Q
Q
/IN
/Q
/IN
/Q
SETMIN
/CASCADE
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
SETMAX
CASCADE
CASCADE
Figure 10c. Cascading Four SY100EP196V
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY100EP195VTI 3.3V/5V 2.5GHz Programmable Delay Chip http://www.micrel.com/product-info/products/sy100ep195v.shtml
SY55856UHI
M0644-012704
2.5V/3.3V 2.5GHz Differential 2-Channel
Precision CML Delay Line
http://www.micrel.com/product-info/products/sy55856u.shtml
16
ECL Pro®
Micrel
SY100EP196V
Control Inputs
Nominal Delay (ps)
D[11]
D[10]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
D[9:0]
One Chip
2,200
2,210
2,220
2,240
2,280
2,360
2,520
2,840
3,480
4,760
7,320
12,430
Two Chips
Three Chips
6,600
Four Chips
8,800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
0000000000
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
4,400
4,410
6,610
8,810
4,420
6,620
8,820
4,440
6,640
8,840
4,480
6,680
8,880
4,560
6,760
8,960
4,720
6,920
9,120
5,040
7,240
9,440
5,680
7,880
10,080
11,360
13,920
19,030
19,040
19,050
19,060
19,080
19,120
19,200
19,360
19,680
20,320
21,600
24,160
29,270
29,280
29,290
29,300
29,320
29,360
29,440
29,600
29,920
30,560
31,840
34,400
39,510
39,520
39,530
39,540
39,560
39,600
39,680
39,840
40,160
40,800
42,080
44,640
49,750
6,960
9,160
9,520
11,720
16,830
16,840
16,850
16,860
16,880
16,920
17,000
17,160
17,480
18,120
19,400
21,960
27,070
27,080
27,090
27,100
27,120
27,160
27,240
27,400
27,720
28,360
29,640
32,200
37,310
27,080
27,090
27,100
27,120
27,160
27,240
27,400
27,720
28,360
29,640
32,200
37,310
14,630
14,640
14,650
14,660
14,680
14,720
14,800
14,960
15,280
15,920
17,200
19,760
24,870
Table 7. List of Nominal Delay Values for Cascaded SY100EP196V
17
M0644-012704
ECL Pro®
SY100EP196V
Micrel
32 LEAD TQFP (T32-1)
Rev. 01
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
M0644-012704
18
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