SY87700VSH_技术文档

5V/3.3V 32-175Mbps AnyRate^®

CLOCK AND DATA RECOVERY

Micrel, Inc.

SY87700V

FEATURES

■ 3.3V and 5V power supply options

■ SONET/SDH/ATM compatible

®

AnyRate

■ Clock and data recovery from 32Mbps up to

175Mbps NRZ data stream, clock generation from

32Mbps to 175Mbps

DESCRIPTION

■ Two on-chip PLLs: one for clock generation and

The SY87700V is a complete Clock Recovery and Data

Retiming integrated circuit for data rates from 32Mbps

up to 175Mbps NRZ. The device is ideally suited for

SONET/SDH/ATM applications and other high-speed data

transmission systems.

Clock recovery and data retiming is performed by

synchronizing the on-chip VCO directly to the incoming

data stream. The VCO center frequency is controlled by

the reference clock frequency and the selected divide

ratio. On-chip clock generation is performed through the

use of a frequency multiplier PLL with a byte rate source

as reference.

another for clock recovery

■ Selectable reference frequencies

■ Differential PECL high-speed serial I/O

■ Line receiver input: no external buffering needed

■ Link Fault indication

■ 100K ECL compatible I/O

■ Complies with Bellcore, ITU/CCITT and ANSI

specifications such as OC-1, OC-3, FDDI, Fast

Ethernet, as well as proprietary applications

■ Available in 32-pin EPAD-TQFP and 28-pin SOIC

packages (28-pin SOIC is available, but not

recommended for new designs)

The SY87700V also includes a link fault detection

circuit.

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

APPLICATIONS

■ SONET/SDH/ATM OC-1/OC-3

■ Fast Ethernet

■ Proprietary architectures up to 175Mbps

BLOCK DIAGRAM

PLLR P/N

RDOUTP

(PECL)

RDINP

(PECL)

RDINN

PHASE

DETECTOR

RDOUTN

RCLKP

(PECL)

0

1

CHARGE

PUMP

VCO

RCLKN

PHASE/

FREQUENCY

DETECTOR

LINK

FAULT

CD

(PECL)

DETECTOR

LFIN

(TTL)

REFCLK

(TTL)

PHASE/

CHARGE

PUMP

FREQUENCY

VCO

TCLKP

(PECL)

1

0

DETECTOR

TCLKN

V^CC

DIVIDER

VCCA

VCCO

GND

BY 8, 10, 16, 20

SY87700V

DIVSEL 1/2

PLLS P/N

(TTL)

FREQSEL 1/2/3

(TTL)

CLKSEL

(TTL)

AnyRate is a registered trademark of Micrel, Inc.

Rev.: H

Amendment:/0

M9999-030106

hbwhelp@micrel.com or (408) 955-1690

1

Issue Date: March 2006

Micrel, Inc.

SY87700V

PACKAGE/ORDERING INFORMATION

Ordering Information⁽¹⁾

VCCA

LFIN

1

2

3

4

5

6

7

8

9

28 VCC

27 CD

Package Operating

Type Range

Package

Marking

Lead

Finish

DIVSEL1

RDINP

26 DIVSEL2

25 RDOUTP

24 RDOUTN

23 VCCO

22 RCLKP

21 RCLKN

20 VCCO

19 TCLKP

18 TCLKN

17 CLKSEL

16 PLLRP

15 PLLRN

Part Number

SY87700VZC

SY87700VZCTR⁽²⁾

Z28-1 Commercial

H32-1 Commercial

Z28-1 Commercial

SY87700VZC

Sn-Pb

NiPdAu

RDINN

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

SY87700VHC

SY87700VZH with

Top View

SOIC

Z28-1

&

SY87700VHCTR⁽²⁾

SY87700VZH⁽³⁾

S28-1

Pb-Free bar line indicator Pb-Free

SY87700VZH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VHH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VHH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VSH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VSH with NiPdAu

Pb-Free bar line indicator Pb-Free

N/C 10

PLLSP 11

PLLSN 12

GND 13

SY87700VZHTR^{(2, 3)}Z28-1 Commercial

SY87700VHH H32-1 Commercial

SY87700VHHTR^{(2, 3)}H32-1 Commercial

SY87700VSH H32-1 Commercial

GND 14

28-Pin SOIC (Z28-1)

SY87700VSHTR^{(2, 3)}H32-1 Commercial

Notes:

32 31

30 29 28 27 26 25

1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.

A

RDOUTP

RDOUTN

VCCO

NC

RDINP

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

RDINN

Top View

EPAD-TQFP

H32-1

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

NC

RCLKP

RCLKN

VCCO

TCLKP

TCLKN

9

10

11 12 13 14 15 16

32-Pin EPAD TQFP (H32-1)

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SY87700V

PIN DESCRIPTIONS

OUTPUTS

INPUTS

RDINP, RDINN [Serial Data Input] Differential PECL.

These built-in line receiver inputs are connected to the

differential receive serial data stream. An internal receive

PLL recovers the embedded clock (RCLK) and data

(RDOUT) information. The incoming data rate can be within

one of five frequency ranges depending on the state of the

FREQSEL pins. See “Frequency Selection” Table.

LFIN [Link Fault Indicator] TTL Output.

This output indicates the status of the input data stream

RDIN. Active HIGH signal is indicating when the internal

clock recovery PLL has locked onto the incoming data

stream. LFIN will go HIGH if CD is HIGH and RDIN is within

the frequency range of the Receive PLL (1000ppm). LFIN

is an asynchronous output.

REFCLK [Reference Clock] TTL Inputs.

RDOUTP, RDOUTN [Receive Data Output] Differential

PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered data from the input data stream

(RDIN). This recovered data is specified against the rising

edge of RCLK.

This input is used as the reference for the internal

frequency synthesizer and the “training” frequency for the

receiver PLL to keep it centered in the absence of data

coming in on the RDIN inputs.

CD [Carrier Detect] PECL Input.

This input controls the recovery function of the Receive

PLL and can be driven by the carrier detect output of optical

modules or from external transition detection circuitry. When

this input is HIGH the input data stream (RDIN) is recovered

normally by the Receive PLL. When this input is LOW the

data on the inputs RDIN will be internally forced to a constant

LOW, the data outputs RDOUT will remain LOW, the Link

Fault Indicator output LFIN forced LOW and the clock

recovery PLL forced to look onto the clock frequency

generated from REFCLK.

RCLKP, RCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered clock used to sample the recovered

data (RDOUT).

TCLKP, TCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent either the recovered clock (CLKSEL = HIGH) used

to sample the recovered data (RDOUT) or the transmit clock

of the frequency synthesizer (CLKSEL = LOW).

FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL

Inputs.

PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]

External loop filter pins for the clock synthesis PLL.

These inputs select the output clock frequency range as

shown in the “Frequency Selection” Table.

PLLRP, PLLRN [Clock Recovery PLL Loop Filter]

External loop filter pins for the receiver PLL.

DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs.

These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency

as shown in the “Reference Frequency Selection” Table.

POWER & GROUND

V

Supply Voltage⁽¹⁾

Analog Supply Voltage⁽¹⁾

Output Supply Voltage⁽¹⁾

Ground

CC

CCA

CLKSEL [Clock Select] TTL Inputs.

CCO

This input is used to select either the recovered clock of

the receiver PLL (CLKSEL = HIGH) or the clock of the

frequency synthesizer (CLKSEL = LOW) to the TCLK

outputs.

GND

N/C

No Connect

Note 1.

V

, V

must be the same value.

CC

CCA

CCO

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SY87700V

FUNCTIONAL DESCRIPTION

Clock Recovery

Lock Detect

The SY87700V contains a link fault indication circuit which

Clock Recovery, as shown in the block diagram generates

a clock that is at the same frequency as the incoming data monitors the integrity of the serial data inputs. If the received

bit rate at the Serial Data input. The clock is phase aligned serial data fails the frequency test, the PLL will be forced to

by a PLL so that it samples the data in the center of the lock to the local reference clock. This will maintain the correct

data eye pattern.

frequency of the recovered clock output under loss of signal

The phase relationship between the edge transitions of or loss of lock conditions. If the recovered clock frequency

the data and those of the generated clock are compared by deviates from the local reference clock frequency by more

a phase/frequency detector. Output pulses from the detector than approximately 1000ppm, the PLL will be declared out

indicate the required direction of phase correction. These of lock. The lock detect circuit will poll the input data stream

pulses are smoothed by an integral loop filter. The output of in an attempt to reacquire lock to data. If the recovered

the loop filter controls the frequency of the Voltage Controlled clock frequency is determined to be within approximately

Oscillator (VCO), which generates the recovered clock.

1000ppm, the PLL will be declared in lock and the lock

Frequency stability without incoming data is guaranteed detect output will go active.

by an alternate reference input (REFCLK) that the PLL locks

onto when data is lost. If the Frequency of the incoming

signal varies by greater than approximately 1000ppm with

respect to the synthesizer frequency, the PLL will be declared

out of lock, and the PLL will lock to the reference clock.

The loop filter transfer function is optimized to enable the

PLL to track the jitter, yet tolerate the minimum transition

density expected in a received SONET data signal. This

transfer function yields a 30µs data stream of continuous

1’s or 0’s for random incoming NRZ data.

The total loop dynamics of the clock recovery PLL

provides jitter tolerance which is better than the specified

tolerance in GR-253-CORE.

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Micrel, Inc.

SY87700V

CHARACTERISTICS

Performance

Jitter Transfer

The SY87700V PLL complies with the jitter specifications

proposed for SONET/SDH equipment defined by the Bellcore

Specifications: GR-253-CORE, Issue 2, December 1995 and

ITU-T Recommendations: G.958 document, when used with

differential inputs and outputs.

Jitter transfer function is defined as the ratio of jitter on

the output OC-N/STS-N signal to the jitter applied on the

input OC-N/STS-N signal versus frequency. Jitter transfer

requirements are shown in Figure 2.

Jitter Generation

Input Jitter Tolerance

The jitter of the serial clock and serial data outputs shall

not exceed .01 U.I. rms when a serial data input with no

jitter is presented to the serial data inputs.

Input jitter tolerance is defined as the peak-to-peak

amplitude of sinusoidal jitter applied on the input signal that

causes an equivalent 1dB optical/electrical power penalty.

SONET input jitter tolerance requirement condition is the

input jitter amplitude which causes an equivalent of 1dB

power penalty.

A

Jitter Transfer (dB)

0.1

-20dB/decade

15

-20dB/decade

1.5

-20dB/decade

Acceptable

Range

-20

0.40

f0

f1

f2

f4

ft

fc

Frequency

OC/STS-N

Level

f0

(Hz)

f1

(Hz)

f2

(Hz)

f3

(kHz)

ft

(kHz)

OC/STS-N

Level

fc

(kHz)

P

(dB)

3

10

30

300

6.5

65

3

130

0.1

Figure 1. Input Jitter Tolerance

Figure 2. Jitter Transfer

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SY87700V

(Note 1)

FREQUENCY SELECTION TABLE

FREQSEL1

FREQSEL2

FREQSEL3

fVCO/fRCLK

fRCLK Data Rates (Mbps)

0

1

0

1

0

1

0

1

6

125 –175

94 – 157

63 – 104

47 – 78

0

8

1

12

16

24

—

0

1

0

32 – 52

undefined

X^{(Note 2)}

Note 1. SY87700V operates from 32-175MHz. For higher speed applications, the SY87701V operates from 35-1250MHz.

Note 2. X is a DON'T CARE.

(Note 1)

REFERENCE FREQUENCY SELECTION

LOOP FILTER COMPONENTS

DIVSEL1

DIVSEL2

fRCLK/fREFCLK

R5

C3

0

1

0

1

0

1

8

10

16

20

PLLSP

PLLSN

Wide Range

R5 = 350Ω

C3 = 1.0µF (X7R Dielectric)

R6

C4

PLLRP

PLLRN

Wide Range

R6 = 680Ω

C4 = 1.0µF (X7R Dielectric)

Note 1. Suggested Values. Values may vary for different applications.

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Micrel, Inc.

SY87700V

(Note 1)

Rating

ABSOLUTE MAXIMUM RATINGS

Symbol

Value

Unit

V

V_CC

V_IN

Power Supply Voltage

–0.5 to +7.0

–0.5 to V_CC

Input Voltage

V

I_OUT

Output Current

mA

– Continuous

– Surge

50

100

T_store

T_A

Storage Temperature

Operating Temperature

–65 to +150

°C

0 to +85

Note 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is

not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings”

conditions for extended periods may affect device reliability.

(Note 1)

PACKAGE THERMAL DATA

θ

(°C/W) by Velocity (LFPM)

JA

Package

0

200

—

500

—

28-Pin SOIC^{(Note 2)}

80

32-Pin EP-TQFP^{(Note 3)}

27.6

22.6

20.7

Note 1. Airflow of 500lfpm recommended for 28-pin SOIC.

Note 2. 28-pin SOIC package is NOT recommended for new designs.

Note 3. Using JEDEC standard test boards with die attach pad soldered

to PCB. See www.amkor.com for additional package details.

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Micrel, Inc.

SY87700V

DC ELECTRICAL CHARACTERISTICS

V

= V

= 3.3V ±5% or 5.0V ±5%, T = 0°C to + 85°C

CCA A

CC

CCO

Symbol

Parameter

Min.

Typ.

Max.

Unit

Condition

V_CC

Power Supply Voltage

3.15

4.75

3.3

5.0

3.45

5.25

V

I_CC

Power Supply Current

—

170

230

mA

PECL 100K DC ELECTRICAL CHARACTERISTICS

V

= V

= 3.3V ±5% or 5.0V ±5%, T = 0°C to + 85°C

CC

CCO

CCA A

Symbol

V_IH

Parameter

Min.

Typ.

—

Max.

Unit

V

Condition

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Input LOW Current

V_CC–1.165

V_CC–1.810

V_CC–1.075

V_CC–1.860

0.5

V_CC–0.880

V_CC–1.475

V_CC–0.830

V_CC–1.570

—

V_IL

—

V

V_OH

V_OL

I_IL

—

V

50Ω to V_CC–2V

V_IN= V_IL(Min.)

—

V

—

µA

TTL DC ELECTRICAL CHARACTERISTICS

V

= V

= 3.3V ±5% or 5.0V ±5%, T = 0°C to + 85°C

CC

CCO

CCA A

Symbol

V_IH

Parameter

Min.

2.0

—

Typ.

—

Max.

V_CC

0.8

Unit

V

Condition

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Current

V_IL

—

V

V_OH

V_OL

I_IH

2.0

—

V

I_OH= –0.4mA

—

0.5

V

I_OL= 4mA

–125

—

+100

µA

V_IN= 2.7V, V_CC= Max.

V_IN= V_CC, V_CC= Max.

I_IL

Input LOW Current

–300

–15

—

µA

V_IN= 0.5V, V_CC= Max.

I_OS

Output Short Circuit Current

–100

mA

V_OUT= 0V (maximum 1sec)

AC ELECTRICAL CHARACTERISTICS

V

= V

= 3.3V ±5% or 5.0V ±5%, T = 0°C to + 85°C

CCA A

CC

CCO

Symbol

f_VCO

Parameter

Min.

750

—

Typ.

—

Max.

1250

—

Unit

MHz

%

Condition

VCO Center Frequency

f

_REFCLK× Byte Rate

∆f_VCO

t_ACQ

VCO Center Freq. Tolerance

Acquisition Lock Time

5

Nominal

—

15

µs

t_CPWH

t_CPWL

t_ir

REFCLK Pulse Width HIGH

REFCLK Pulse Width LOW

REFCLK Input Rise Time

Output Duty Cycle (RCLK/TCLK)

4

—

ns

4

—

ns

—

0.5

—

2

ns

t_ODC

45

100

55

% of UI

ps

t_r

t_f

ECL Output Rise/Fall Time

(20% to 80%)

—

500

50Ω to V_CC–2V

t_SKEW

t_DV

Recovered Clock Skew

Data Valid

–200

—

+200

—

ps

1/(2×f_RCLK) – 200

t_DH

Data Hold

—

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SY87700V

TIMING WAVEFORMS

t

CPWH

CPWL

REFCLK

t

ODC

RCLK

t

SKEW

t

tDH

DV

RDOUT

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SY87700V

32-PIN APPLICATION EXAMPLE

R13

VCC

LED

D2

R12

Q1

2N2222A

VEE

DIODE

D1

32 31

30 29 28 27 26 25

VCC

1N4148

R10

RDOUTP

RDOUTN

VCCO

NC

24

23

22

1

2

3

4

5

6

7

8

RDINP

RDINN

FREQSEL1

REFCLK

1

2

3

RCLKP

RCLKN

VCCO

21

20

19

18

FREQSEL2

FREQSEL3

CLKSEL

DIVSEL1

DIVSEL2

4

5

6

7

TCLKP

TCLKN

NC

17

9

10

11 12 13 14 15 16

CD

VEE R11 SW1

1kΩ

C3

C4

GND

R1

R2

C2

C1

Ferrite Bead

BLM21A102

VCCO (+2V)

VCC (+2V)

VCC

L3

L2

L1

VCCA (+2V)

C5

22 F

C6

0.1 F

C7

6.8 F

C11

0.1 F

C12

0.01 F

C8

6.8 F

C13

0.1 F

C14

0.01 F

C9

C15

C16

6.8 F

0.1 F

0.01 F

GND

C10

6.8 F

C17

0.1 F

C18

0.01 F

VEE (—3V)

VEE

C21

0.01 F

C19

1.0 F

C20

0.1 F

VEEA (—3V)

Note:

C3, C4 are optional

C1 = C2 = 1.0µF

R1 = 350Ω

R2 = 680Ω

R3 through R10 = 5kΩ

R12 = 12kΩ

R13 = 130Ω

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SY87700V

28-PIN APPLICATION EXAMPLE

VCC

(R17 - R22)

5kΩ x 6

1

2

3

4

5

6

VCC

Ferrite Bead

BLM21A102

Stand Off

LED

R8

D2

FB1

22 F

0.1 F

130Ω

0.1 F

22 F

C9

C8

C7

C6

GND

1

VCCA

LFIN

VCC 28

J1

VCC

2

3

Capacitor Pads

(1206 format)

27

26

25

VCC

CD

R7

1kΩ

Diode D1

1N4148

R1

R3

R2

R4

DIVSEL1

RDINP

DIVSEL2

RDOUTP

RDOUTN

VCCO

0.1 F

C1

4

5

C14

C15

RDIN

RDINN

24

23

22

C2

6

7

8

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

N/C

0.1 F

See Table 1

RCLKP

RCLKN

C16

C17

GND

21

9

VCCO 20

0.1 F

19

10

11

TCLKP

C18

C19

R5

80Ω

18

PLLSP

TCLKN

LOOP FILTER

NETWORK

C3

12

13

14

17

PLLSN

CLKSEL

If VCC = +5V:

R9 through R14 = 330Ω

1.5 F

R6 50‰

16

15

PLLRP

PLLRN

GND

C4

If VCC = +3.3V:

1.0 F

R9 through R14 = 220Ω

REFCLK

(TTL)

VCC

GND

NC

C5

Pin 1 (VCCA)

Pin 28 (VCC)

XTAL

Oscillator

0.1 F

C10

C11

C12

14

C13

1

7

0.1 F

Pin 23 (VCCO)

Pin 20 (VCCO)

8

VCC

120Ω

R21

Note 1. C5 and C10–C12 are decoupling capacitors and should be kept

as close to the power pins as possible.

For AC-Coupling Only

For DC Mode Only

when V_CC= +5V

C1 = C2 = 0.1µF

R1 = R2 = 1.2kΩ

R3 = R4 = 3.4kΩ

when V_CC= +3.3V

C1 = C2 = 0.1µF

R1 = R2 = 680Ω

R3 = R4 = 1kΩ

when V_CC= +5V

C1 = C2 = Shorted

R1 = R2 = 82Ω

when V_CC= +3.3V

C1 = C2 = Shorted

R1 = R2 = 130Ω

R3 = R4 = 82Ω

R3 = R4 = 130Ω

Table 1.

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SY87700V

BILL OF MATERIALS (32-PIN EPAD-TQFP)

Item

Part Number

Manufacturer

Description

Qty.

C1, C2

VJ0603Y105JXJAT

Vishay

1.0µF Ceramic Capacitor, Size 1206

2

X7R Dielectric, Loop Filter, Critical

C3, C4

VJ0603Y105JXJAT

Vishay

1.0µF Ceramic Capacitor, Size 1206

2

X7R Dielectric, Loop Filter, Optional

C5

C6

ECS-T1ED226R

Panasonic

22µF Tantalum Electrolytic Capacitor, Size D

1

ECU-V1H104KBW

0.1µF Ceramic Capacitor, Size 1206

X7R Dielectric, Power Supply Decoupling

C7, C8, C9, C10

C19

ECS-T1EC685R

ECJ-3YB1E105K

Panasonic

6.8µF Tantalum Electrolytic Capacitor, Size C

4

1

1.0µF Ceramic Capacitor, Size 1206

X7R Dielectric, VEEA Decoupling

C11, C13

C15, C17

C20

ECU-V1H104KBW

ECU-V1H103KBW

Panasonic

0.1µF Ceramic Capacitor, Size 1206

X7R Dielectric, VCCO/VCC Decoupling

1

0.1µF Ceramic Capacitor, Size 1206

X7R Dielectric, VCCA/VEEA Decoupling

0.1µF Ceramic Capacitor, Size 1206

X7R Dielectric, VEEA Decoupling

C12, C14

C16, C18

C21

0.01µF Ceramic Capacitor, Size 1206

X7R Dielectric, VCCO/VCC Decoupling

0.01µF Ceramic Capacitor, Size 1206

X7R Dielectric, VCCA/VEEA Decoupling

0.01µF Ceramic Capacitor, Size 1206

X7R Dielectric, VEEA Decoupling

D1

D2

1N4148

Diode

1

P300-ND/P301-ND

Panasonic

T-1 3/4 Red LED

J1, J2, J3, J4, J5 142-0701-851

J6, J7, J8, J9,

Johnson

Components

Gold Plated, Jack, SMA, PCB Mount

12

J10, J11, J12

L1, L2, L3

Q1

BLM21A102F

NTE123A

Murata

NTE

Ferrite Beads, Power Noise Suppression

2N2222A Buffer/Driver Transistor, NPN

3

1

R1

350Ω Resistor, 2%, Size 0402

Loop Filter Component, Critical

R2

680Ω Resistor, 2%, Size 0402

Loop Filter Component, Critical

1

8

R3, R4, R5, R6

R7, R8, R9, R10

5kΩ Pullup Resistors, 2%, Size 1206

R11

R12

R13

SW1

1kΩ Pulldown Resistor, 2%, Size 1206

12kΩ Resistor, 2%, Size 1206

1

130Ω Pullup Resistor, 2%, Size 1206

SPST, Gold Finish, Sealed Dip Switch

206-7

CTS

M9999-030106

hbwhelp@micrel.com or (408) 955-1690

12

Micrel, Inc.

SY87700V

28 LEAD SOIC .300" WIDE (Z28-1)

Rev. 02

Note:

The 28 Lead SOIC package is NOT recommended for new designs.

M9999-030106

hbwhelp@micrel.com or (408) 955-1690

13

Micrel, Inc.

SY87700V

32 LEAD EPAD TQFP (DIE UP) (H32-1)

Rev. 01

Package

EP- Exposed Pad

Die

CompSide Island

Heat Dissipation

V_EE

Heavy Copper Plane

V_EE

PCB Thermal Consideration for 32-Pin EPAD-TQFP Package

M9999-030106

hbwhelp@micrel.com or (408) 955-1690

14

Micrel, Inc.

SY87700V

APPENDIX A

Layout and General Suggestions

1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques.

2. Signal paths should have, approximately, the same width as the device pads.

3. All differential paths are critical timing paths, where skew should be matched to within ±10ps.

4. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal

traces.

5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to

reduce stray capacitance. Be careful of crosstalk coupling into the filter network.

6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately

decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals.

7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based

oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter.

8. Evaluate ASIC AND FPGA REFIN source clocks with suitable jitter analysis equipment, such as TDS11801 tektronix

DSO oscilloscope, or Wavecrest DTS2077 Time Interval Analyzer.

9. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1kΩ

resistor to V

.

EE

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s

use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

M9999-030106

hbwhelp@micrel.com or (408) 955-1690

15


型号：	SY87700VSH
厂家：	MICROCHIP
描述：	Clock Recovery Circuit, 1-Func, PQFP32
文件：	总15页 (文件大小：139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SY87700VSH [MICROCHIP]

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