SY89429VJZ [MICROCHIP]
PLL FREQUENCY SYNTHESIZER, 25MHz, PQCC28;
| 型号： | SY89429VJZ |
| 厂家： | 
MICROCHIP |
| 描述： | PLL FREQUENCY SYNTHESIZER, 25MHz, PQCC28 |
| 文件： | 总10页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
5V/3.3V PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
Precision Edge
SY89429V
FEATURES
■ 3.3V and 5V power supply options
■ 25MHz to 400MHz differential PECL outputs
■ 50ps peak-to-peak output jitter
■ Minimal frequency over-shoot
■ Synthesized architecture
®
Precision Edge
DESCRIPTION
The SY89429V is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 800MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 2, 4, 8 or 16. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
■ Serial 3-wire interface
■ Parallel interface for power-on
■ Internal quartz reference oscillator driven by quartz
crystal
■ Application Note (AN-07) for ease of design-ins
■ Available in 28-pin PLCC and SOIC packages
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
APPLICATIONS
■ Workstations
■ Advanced communications
■ High end consumer
■ High-performance computing
■ RISC CPU clock
■ Graphics pixel clock
■ Test equipment
■ Other high-performance processor-based
applications
Precision Edge is a registered trademark of Micrel, Inc.
Rev.: J
Amendment: /0
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: January 2006
Precision Edge®
SY89429V
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Range
Package
Marking
Lead
Finish
Part Number
Type
SY89429VJC
J28-1
J28-1
Z28-1
Z28-1
J28-1
Commercial
Commercial
Commercial
Commercial
Commercial
SY89429VJC
SY89429VJC
SY89429VZC
SY89429VZC
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
24 23 22 21 20 19
25
S_CLOCK
S_DATA
26
27
28
1
18
17
16
15
14
13
12
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
SY89429VJCTR(2)
S_LOAD
SY89429VZC
PLCC
TOP VIEW
VCC_QUIET
LOOP_FILTER
LOOP_REF
XTAL1
SY89429VZCTR(2)
SY89429VJZ(3)
2
3
SY89429VJZ with Matte-Sn
Pb-Free bar line indicator Pb-Free
4
5
6
7
8
9
10 11
SY89429VJZTR(2, 3)
SY89429VZH(3)
SY89429VZHTR(2, 3)
Notes:
J28-1
Z28-1
Z28-1
Commercial
Commercial
Commercial
SY89429VJZ with Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89429VZH with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89429VZH with NiPdAu
Pb-Free bar line indicator Pb-Free
28-PinPLCC (J28-1)
1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.
A
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
28-PinSOIC (Z28-1)
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
2
Precision Edge®
SY89429V
Micrel, Inc.
BLOCK DIAGRAM
+3.3V
or
+5.0V
PLL
FREF
÷ 8
PHASE DETECTOR
VCO
PECL
10-25MHz
Fundamental
Crystal
OSC
FOUT
TEST
÷ M
÷ N
400 – 800MHz
INTERFACE
LOGIC
3 WIRE
INTERFACE
SERIAL
PARALLEL
CONFIG INFO
DETAILED BLOCK DIAGRAM
Ω
µ
÷
÷
÷
10pF
NOTE:
Pin numbers reference PLCC pinout.
M9999-011106
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Precision Edge®
SY89429V
Micrel, Inc.
PIN DESCRIPTIONS
INPUTS
OUTPUTS
XTAL1, XTAL2
FOUT, /FOUT
These pins form an oscillator when connected to an external These differential positive-referenced ECL signals (PECL)
crystal.Thecrystalisseriesresonant. See“AN-07”forCrystal are the output of the synthesizer.
Interface Guideline.
TEST
S
_LOAD
The function of this TTL output is determined by the serial
configuration bits T[2:0].
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
POWER
HIGH-to-LOW transition of S
for proper operation.
_LOAD
V
CC1
S
This is the positive supply for the chip and is normally
connected to +3.3V or +5.0V.
_DATA
This TTL pin is the input to the serial configuration shift
registers.
V
CC_OUT
Thisisthepositive referencefor thePECLoutputs, FOUT and
/FOUT. It is constrained to be less than or equal to V
S
_CLOCK
.
CC1
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S is sampled.
_DATA
V
CC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
/P
_LOAD
This TTL pin loads the configuration latches with the contents
oftheparallelinputs. Thelatcheswillbetransparentwhenthis GND
signal is LOW: Thus, the parallel data must be stable on the
LOW-to-HIGH transition of /P for proper operation.
These pins are the negative supply for the chip and are
normally all connected to ground.
_LOAD
During power up, hold /P
M[0] - M[8] until supplies have stabilized.
low with a valid M count on
_LOAD
OTHER
M[8:0]
LOOP_FILTER
These TTL pins are used to configure the PLL loop divider.
.
This is an analog I/O pin that provides the loop filter for the
PLL.
They are sampled on the LOW-to-HIGH transition of /P
_LOAD
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of /P
.
_LOAD
N[1:0]
0 0
Output Division
2
4
0 1
1 0
8
1 1
16
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Precision Edge®
SY89429V
Micrel, Inc.
WITH 16MHZ INPUT
VCO Frequency
256
M8
128
M7
64
32
16
8
4
2
1
(MHz)
M Count
M6
M5
M4
M3
M2
M1
M0
400
402
404
406
•
200
201
202
203
•
0
0
0
0
•
1
1
1
1
•
1
1
1
1
•
0
0
0
0
•
0
0
0
0
•
1
1
1
1
•
0
0
0
0
•
0
0
1
1
•
0
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
794
796
798
800
397
398
399
400
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector.Witha16MHzcrystal,thisprovidesareferencefrequency
of 2MHz.
The VCO, within the PLL, operates over a range of 400–
800MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequencytobeMtimesthereferencefrequencyby adjustingthe
VCO control voltage. Note that for some values of M (either too
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter
performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The output
divider is configured through either the serial or the parallel
interfacesandcanprovideoneoffourdividerratios (2,4,8or16).
This divider extends the performance of the part while providing
a 50% duty cycle.
in50Ω toVCC –2volts. Thepositivereferencefortheoutputdriver
is provided by a dedicated power pin (VCC_OUT) to reduce noise
induced jitter.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, upon
system reset, the /P_LOAD input is held LOW until some time
after power becomes valid. With S_LOAD held LOW, on the
LOW-to-HIGH transition of /P_LOAD, the parallel inputs are
captured. The parallel interface has priority over the serial
interface. Internal pull-up resistors are provided on the M[8:0]
and N[1:0] inputs to reduce component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet set-up and
holdtimingasspecifiedintheACparameterssectionofthisdata-
sheet. With /P_LOAD held HIGH, the configuration latches will
capture the value in the shift register on the HIGH-to-LOW edge
of the S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and is
controlled by the T[2:0] bits in the serial data stream. See the
programming subsection of this data sheet for more information.
The output driver is driven differentially from the output divider
and is capable of driving a pair of transmission lines terminated
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89429V
Micrel, Inc.
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
The TEST output provides visibility for one of several
configuring the internal dividers to produce the desired internal nodes (as determined by the T[1:0] bits in the serial
frequency at the outputs. The output frequency can be configurationstream).Itisnotconfigurablethroughtheparallel
represented by this formula:
interface. Although it is possible to select the node that
represents FOUT, the TTL output may not be able to toggle
fastenoughforsomeofthehigheroutputfrequencies.TheT2,
M
N
FXTAL
FOUT = (
) x
8
T1, T0 configuration latches are preset to 000 when /P
_LOAD
Where FXTAL is the crystal frequency, M is the loop divider is low, so that the FOUT outputs are as jitter-free as possible.
modulus, and N is the output divider modulus. Note that it is The serial configuration port can be used to select one of the
possible to select values of M such that the PLL is unable to alternate functions for this pin.
achieve loop lock. To avoid this, always ensure that M is
selected to be 200 ≤ M ≤ 400 for a 16MHz input reference.
M[8:0]and N[1:0]arenormallyspecifiedonceatpower-on, bits of the data stream on the S
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
input. For each register,
_DATA
throughtheparallelinterface,andthenpossiblyagainthrough the most significant bit is loaded first (T2, N1 and M8).
theserialinterface. Thisapproachallowsthedesignertobring When T[2:0] is set to 100 the SY89429V is placed in PLL
up the application at one frequency and then change or fine- bypass mode. In this mode the S input is fed directly
_CLOCK
tune the clock, as the ability to control the serial interface into the M and N dividers. The N divider drives the FOUT
becomes available. To minimize transients in the frequency differential pair and the M counter drives the TEST output pin.
domain, the output should be varied in the smallest step size In this mode the S
input could be used for low speed
_CLOCK
possible.
board level functional test or debug. Bypassing the PLL and
driving FOUT directly gives the user more control on the test
clockssentthroughtheclocktree(SeedetailedBlockDiagram).
T2 T1 T0
TEST
Data Out – Last Bit SR
HIGH
FOUT / /FOUT
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
Because the S
is a TTL level the input frequency is
_CLOCK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
limited to 250MHz or less. This means the fastest the FOUT
pincanbetoggledviatheS is125MHzastheminimum
_CLOCK
divideratiooftheNcounteris2.NotethattheMcounteroutput
ontheTESToutputwillnotbea50%dutycycleduetotheway
the divider is implemented.
FREF
M Counter Output
FOUT
LOW
S
÷ M
S
÷ N
_CLOCK
_CLOCK
FOUT ÷ 4
FVCO ÷ N
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
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Precision Edge®
SY89429V
Micrel, Inc.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Power Supply Voltage
Value
Unit
V
–0.5 to +7.0
–0.5 to +7.0
VI
Input Voltage
Output Source
V
IOUT
Continuous
Surge
50
100
mA
TLEAD
Tstore
TA
Lead Temperature (soldering 20sec.)
Storage Temperature
+260
°C
°C
°C
–65 to +150
–0 to +75
Operating Temperature
NOTE:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions
other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device
reliability.
100H ECL DC ELECTRICAL CHARACTERISTICS
V
CC1
= V
= V
= V = +3.3V to +5.0V ±5%; T = 0°C to +75°C
CC_OUT A
CC_QUIET
CC_TTL
Symbol
VOH
Parameter
Min.
Max.
Unit
V
Condition
Output HIGH Voltage
Output LOW Voltage
VCC_OUT –1.075
VCC_OUT –1.860
VCC_OUT –0.830
VCC_OUT –1.570
50Ω to VCC_OUT –2V
50Ω to VCC_OUT –2V
VOL
V
TTL DC ELECTRICAL CHARACTERISTICS
V
CC1
= V
= V
= V = +3.3V to +5.0V ±5%; T = 0°C to +75°C
CC_OUT A
CC_QUIET
CC_TTL
TA = 0°C
TA = +25°C
TA = +75°C
Symbol
VIH
Parameter
Min.
Max.
Min.
2.0
—
Max.
Min.
2.0
—
Max.
Unit
Condition
—
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
2.0
—
—
—
—
—
—
—
—
0.8
50
—
V
V
VIL
0.8
0.8
—
IIH
50
—
—
50
µA
mA
V
VIN = 2.7V
VIN = 0.5V
IIN = –12mA
IOH = –2.0mA
IOL = 8mA
VOUT = 0V
IIL
–0.6
–1.2
2.0
—
–0.6
–1.2
2.0
0.5
—
–0.6
–1.2
2.0
VIK
—
—
VOH
VOL
IOS
—
—
V
0.5
—
—
0.5
V
Output Short Circuit Current
Supply Current
–100 (Typ.)
190
0.89X of 5V Val. 0.89X of 5V Val. 0.89X of 5V Val.
–100 (Typ.)
–100 (Typ.)
mA
ICC1
—
—
190
—
190
mA
mA
5.0V ±5%
3.3V ±5%
Typical % of ICC1
VCC1
33%
9%
14%
44%
33%
9%
14%
44%
33%
9%
14%
44%
VCC_OUT
VCC_QUIET
VCC_TTL
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Precision Edge®
SY89429V
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS
= V
V
CC1
= V
= V
= +3.3V to +5.0V ±5%; T = 0°C to +75°C
CC_OUT A
CC_QUIET
CC_TTL
TA = 0°C
TA = +25°C
TA = +75°C
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
Condition
fMAXI
Maximum Input Frequency
Note 1
S_CLOCK
Xtal Oscillator
—
10
10
25
—
10
10
25
—
10
10
25
MHz
Fundamental
Cyrstal
fMAXO
Maximum Output Frequency VCO (Internal)
FOUT
400
25
800
400
400
25
800
400
400
25
800 MHz
400
tLOCK
tjitter
tS
Maximum PLL Lock Time
—
—
10
50
—
—
10
50
—
—
10
50
ms
ps
ns
Cycle-to-Cycle Jitter (Peak-to-Peak)
Test output static
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to /P_LOAD
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to /P_LOAD
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
tpw(MIN)
tDC
Minimum Pulse Width
FOUT Duty Cycle
S_LOAD
/P_LOAD
50
50
—
—
50
50
—
—
50
50
—
—
45
55
45
55
45
55
%
tr
tf
Output Rise/Fall
20% to 80%
FOUT
300
800
300
800
300
800
ps
NOTE:
1. 10MHz is the maximum frequency to load the feedback divide registers. S
TEST_MODE 6.
can be switched at high frequencies when used as a test clock in
_CLOCK
TIMING DIAGRAM
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
8
Precision Edge®
SY89429V
Micrel, Inc.
28-PIN SOIC .300" WIDE (Z28-1)
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
9
Precision Edge®
SY89429V
Micrel, Inc.
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-011106
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