SY89825UHGTR [MICROCHIP]
Low Skew Clock Driver, 89825 Series, 22 True Output(s), 0 Inverted Output(s), ECL, PQFP64, LEAD FREE, TQFP-64;
| 型号： | SY89825UHGTR |
| 厂家： | 
MICROCHIP |
| 描述： | Low Skew Clock Driver, 89825 Series, 22 True Output(s), 0 Inverted Output(s), ECL, PQFP64, LEAD FREE, TQFP-64 驱动 逻辑集成电路 |
| 文件： | 总9页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
2.5/3.3V 1:22 HIGH-PERFORMANCE,
LOW-VOLTAGE PECL BUS CLOCK DRIVER
& TRANSLATOR w/ INTERNAL TERMINATION
®
Precision Edge
SY89825U
FEATURES
■ LVPECL or LVDS input to 22 LVPECL outputs
■ 100K ECL compatible outputs
®
Precision Edge
■ LVDS input includes 100Ω termination
■ Guaranteed AC parameters over voltage:
DESCRIPTION
• > 1GHz fMAX (toggle)
• < 35ps max. ch-ch skew
The SY89825U is a High Performance Bus Clock Driver
with 22 differential LVPECL output pairs. This part is
designed for use in low voltage (2.5V, 3.3V) applications
which require a large number of outputs to drive precisely
aligned, ultra low skew signals to their destination. The
input is multiplexed from either LVDS or LVPECL by the
CLK_SEL pin. The LVDS input includes a 100Ω internal
termination, thus eliminating the need for external
termination. The Output Enable (OE) is synchronous so
that the outputs will only be enabled/disabled when they
are already in the LOW state. This eliminates any chance
of generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The SY89825U features low pin-to-pin skew (35ps max.)
—performance previously unachievable in a standard
product having such a high number of outputs. The
SY89825U is available in a single space saving package
which provides a lower overall cost solution. In addition, a
single chip solution improves timing budgets by eliminating
the multiple device solution with their corresponding large
part-to-part skew.
■ Low voltage operation: 2.5V, 3.3V
■ Temperature range: –40°C to +85°C
■ Output enable pin
■ Available in a 64-Pin EPAD-TQFP
APPLICATIONS
■ High-performance PCs
■ Workstations
■ Parallel processor-based systems
■ Other high-performance computing
■ Communications
Precision Edge is a registered trademark of Micrel, Inc.
Rev.: D
Amendment: /0
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: November 2005
Precision Edge®
SY89825U
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Marking
Lead
Finish
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Part Number
Type
H64-1
H64-1
Range
Industrial
Industrial
VCCO
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCCO
Q7
/Q7
Q8
/Q8
SY89825UHI
SY89825UHITR(2)
SY89825UHI
Sn-Pb
NC
3
VCCI
4
SY89825UHI
Sn-Pb
LVDS_CLK
/LVDS_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GND
5
6
7
8
Q9
/Q9
SY89825UHG(3)
SY89825UHGTR(2,3)
Notes:
H64-1
Industrial
SY89825UHG with
Pb-Free bar-line indicator NiPdAu
SY89825UHG with Pb-Free
Pb-Free bar-line indicator NiPdAu
Pb-Free
64-Pin
EPAD-TQFP
(Top View)
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
VCCO
9
10
11
12
13
14
15
16
OE
NC
NC
/Q21
Q21
VCCO
H64-1
Industrial
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3. Pb-Free package recommended for new designs.
64-Pin EPAD-TQFP (H64-1)
PIN NAMES
LOGIC SYMBOL
Pin
Function
CLK_SEL
LVDS_CLK,
/LVDS_CLK
Differential LVDS Inputs
(Internal 100Ω termination included)
LVDS_CLK
/LVDS_CLK
0
1
LVPECL_CLK,
/LVPECL_CLK
Differential LVPECL Inputs.
22
22
Q0 - Q21
CLK_SEL
Input CLK Select (LVTTL)
Output Enable (LVTTL)
/Q0 - /Q21
LVPECL_CLK
/LVPECL_CLK
OE
Q0 – Q21, /Q0 – /Q21
Differential LVPECL Outputs.
LEN
D
Terminate with 50Ω to VCC-2V
Q
GND
VCCI
Ground
OE
Power Supply. Connect to
VCC on PCB. VCCI and VCCO are not
internally connected
VCCO
Power Supply for Output Buffer.
Connect to VCCI on PCB. VCCI and
VCCO are not internally connected
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
2
Precision Edge®
SY89825U
Micrel, Inc.
TRUTH TABLE
SIGNAL GROUPS
OE(1)
CLK_SEL
Q0 – Q21
LOW
/Q0 – /Q21
HIGH
Signal
I/O
Input
Output
Input
Input
Level
LVDS
0
0
1
1
0
1
0
1
LVDS_CLK, /LVDS_CLK
Q0 – Q21, /Q0 – /Q21
LVPECL_CLK, /LVPECL_CLK
CLK_SEL, OE
LOW
HIGH
LVPECL
LVDS_CLK
LVPECL_CLK
/LVDS_CLK
/LVPECL_CLK
LVPECL
LVCMOS/LVTTL
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
LVDS_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCCI / VCCO
VIN
Rating
VCC Pin Potential to Ground Pin
Value
Unit
V
–0.5 to +4.0
–0.5 to VCCI
–50
Input Voltage
V
IOUT
DC Output Current
mA
TLEAD
Tstore
θJA
Lead Temperature (soldering, 20 sec.)
Storage Temperature
+260
°C
°C
–65 to +150
Package Thermal Resistance (Junction-to-Ambient)
With exposed pad soldered to GND
– Still-Air (multi-layer PCB)
– 200lfpm (multi-layer PCB)
– 500lfpm (multi-layer PCB)
23
18
15
°C/W
°C/W
°C/W
Exposed pad not soldered to GND
– Still-Air (multi-layer PCB)
– 200lfpm (multi-layer PCB)
– 500lfpm (multi-layer PCB)
44
36
30
°C/W
°C/W
°C/W
θJC
Package Thermal Resistance
(Junction-to-Case)
4.3
°C/W
NOTE:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data book. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
3
Precision Edge®
SY89825U
Micrel, Inc.
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = –40°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
VCCI,
VCCO
Power Supply(1)
2.37
—
3.6
2.37
—
3.6
2.37
—
3.6
V
ICC
Total Supply Current(2)
—
100
150
—
100
150
—
100
150
mA
Notes:
1. V
and V
must be connected together on the PCB such that they remain at the same potential. V
and V
are not internally connected on the die.
CCI
CCO
CCI
CCO
2. No load. Outputs floating.
LVDS Input (VCC = 2.37V to 3.6V, GND = 0V)
TA = –40°C
TA = +25°C
TA = +85°C
Symbol
VIN
Parameter
Input Voltage Range
Differential Input Swing
Input Low Current(1)
Min.
0
Typ.
—
Max.
2.4
—
Min.
0
Typ.
—
Max.
2.4
—
Min.
0
Typ.
—
Max.
2.4
—
Unit
V
VID
100
–1.25
80
—
100
–1.25
80
—
100
–1.25
80
—
mV
mA
Ω
IIL
—
—
—
—
—
—
RIN
LVDS Differential Input Resistance
(LVDS_CLK to /LVDS_CLK)
100
120
100
120
100
120
Note:
1. For I , both LVDS inputs are grounded.
IL
LVPECL Input/Output (VCC = 2.37V to 3.6V, GND = 0V)
TA = –40°C
TA = +25°C
Min. Max.
TA = +85°C
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
VIH
Input HIGH Voltage
(Single ended)
VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88
V
VIL
Input LOW Voltage
VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625
V
VPP
Minimum Input Swing(1)
LVPECL_CLK
600
—
600
—
600
—
mV
VCMR
Common Mode Range(2)
LVPECL_CLK
–1.5
–0.4
–1.5
–0.4
–1.5
–0.4
V
VOH
VOL
IIH
Output HIGH Voltage(3)
Output LOW Voltage(3)
Input HIGH Current
Input LOW Current
VCCO – 1.085 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880
VCCO – 1.830 VCCO – 1.555 VCCO – 1.810 VCCO – 1.620 VCCO – 1.810 VCCO – 1.620
V
V
—
150
—
—
150
—
—
150
—
µA
µA
IIL
0.5
0.5
0.5
Notes:
1. The V (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
PP
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are
referenced to V . The V level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V (min.). The lower end of the
CCI
IL
PP
CMR range varies 1:1 with V . The V
(min) will be fixed at 3.3V – |V
(min)|.
CCI
CMR
CMR
3. Outputs loaded with 50Ω to VCC -2V.
LVCMOS/LVTTL Control Inputs (OE, CLK_SEL) (VCC = 2.37V to 3.6V, GND = 0V)
TA = –40°C
TA = +25°C
TA = +85°C
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Min.
2.0
—
Typ.
—
Max.
—
Min.
2.0
—
Typ.
—
Max.
—
Min.
2.0
—
Typ.
—
Max. Unit
—
V
V
VIL
—
0.8
—
0.8
—
0.8
IIH
+20
—
—
–250
–600
+20
—
—
–250
–600
+20
—
—
–250
–600
µA
µA
IIL
—
—
—
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
4
Precision Edge®
SY89825U
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 2.37V to 3.6V, GND = 0V
TA = –40°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max. Unit
fMAX
tPD
Max Toggle Frequency(2)
1
—
—
1
—
—
1
—
—
GHz
ns
Propagation Delay
(Differential)(3)
LVPECL IN 0.600
LVDS IN 0.800
—
—
1.2
1.4
0.600 0.900
0.800
1.2
1.4
0.600
0.800
—
—
1.2
1.4
1.1
20
100
—
tSKEW
Within-Device Skew(4)
Part-to-Part Skew(5)
OE Set-Up Time(6)
OE Hold Time(6)
Random Jitter(7)
Cycle-to-Cylce Jitter(8)
Total Jitter(9)
—
—
—
100
—
35
200
—
—
35
200
—
—
—
—
100
—
35
200
—
ps
ps
—
tS(OE)
tH(OE)
tJITTER
1.0
0.5
—
1.0
0.5
—
1.0
0.5
—
ns
—
—
—
—
—
—
ns
—
1
—
1
—
1
psRMS
psRMS
psPP
ps
—
—
1
—
—
1
—
—
1
—
—
10
600
—
—
10
600
—
—
10
600
tr
tf
Output Rise/Fall Time
(20% – 80%)
300
—
300
450
300
—
t(switchover) Input Switchover
CLK_SEL-to-valid output
—
—
1.2
—
—
1.2
—
—
1.2
ns
Notes:
1. Outputs loaded with 50Ω to V – 2V. Airflow ≥ 300lfpm.
CC
2. f
is defined as the maximum toggle frequency measured. Measured with a 800mV input signal, output swing ≥ 200mV, and all loading with 50Ω
MAX
to V –2V.
CC
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
7. Random jitter is measured using K28.7 pattern, measured at ≤ f
.
MAX
8. Cycle-to-cycle definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output signal.
12
9. Total jitter definition: with an ideal clock input of frequency ≤ f
, no more than one output edge in 10 output edges will d eviate by more than the
MAX
specified peak-to-peak jitter value.
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
5
Precision Edge®
SY89825U
Micrel, Inc.
LVDS/LVPECL INPUTS
VCC
VCC
1.9k
1.9k
75k
LVPECL_CLK
/LVPECL_CLK
1.9k
1.9k
75k
75k
VIN
VIN
100Ω
GND
GND
LVPECL Input Stage
LVDS Input Stage
Figure 1. Simplified LVPECL & LVDS Input Stage
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
6
Precision Edge®
SY89825U
Micrel, Inc.
TYPICAL CHARACTERISTICS
Frequency Response
vs. Output Amplitude @ 2.5V
Frequency Response
vs. Output Amplitude @3.3V
800
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
0
200 400 600 800 1000 1200
FREQUENCY (MHz)
0
200 400 600 800 1000 1200
FREQUENCY (MHz)
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
7
Precision Edge®
SY89825U
Micrel, Inc.
LVPECL TERMINATION RECOMMENDATIONS
down resistor at the output of each driver. The emmiter follower
outputs requires a DC current path to GND. Unused outputs can be
left floating with minimal impact on skew and jitter.
Output Considerations
Be sure to properly terminate all outputs as shown below, or
equivalent.ForACcoupledapplications,besuretoincludeapull
+3.3V
R1
130Ω
R1
130Ω
+3.3V
+3.3V
Z
O = 50Ω
Z
O = 50Ω
R2
82Ω
R2
82Ω
V = VCC —2V
t
Figure 1. Parallel Termination–Thevenin Equivalent
Notes:
1. For +2.5V systems:
R1 = 250Ω
R2 = 62.5Ω
+3.3V
+3.3V
Z = 50Ω
Z = 50Ω
“source”
“destination”
50Ω
50Ω
46Ω to 49Ω
R
b
Figure 2. Three-Resistor “Y–Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R resistor sets the DC bias voltage equal to V . For +3.3V systems R = 46Ω to 49Ω.
b
t
b
4. Precision, low-cost 3-Resistor networks are available from resistor manufacturers such as Thin Film Technology (www.thinfilm.com).
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
8
Precision Edge®
SY89825U
Micrel, Inc.
64-PIN EPAD-TQFP (DIE UP) (H64-1)
0.472 BSC SQ.
4
12.00
10.00
+0.05
–0.05
1.00
0.039
DETAIL "A"
+0.002
–0.002
6
7
0.394
BSC SQ.
0° MIN.
0.20 0.008
+0.05
0.09 0.004
4.50
0.177
–0.05
+0.012
–0.012
0.15 0.006
0.05 0.002
64
48
6
48
0°- 7°
+0.03
4.50 –0.03
+0.012
+0.15
0.60
0.024
–0.15
+0.006
0.177
–0.012
–0.006
1.00 0.039 REF.
33
16
17
32
5
SEE DETAIL "A"
0.50 0.020
BSC
0.047 MAX
0.01 0.004
1.20
7
+0.05
0.22
0.009
–0.05
Rev. 03
+0.002
–0.002
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
M9999-120205
hbwhelp@micrel.com or (408) 955-1690
9
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