TC1270ALVRCTR [MICROCHIP]
Voltage Supervisor with Manual Reset Input; 电压监控器与手动复位输入
| 型号： | TC1270ALVRCTR |
| 厂家： | 
MICROCHIP |
| 描述： | Voltage Supervisor with Manual Reset Input |
| 文件： | 总40页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC1270A/70AN/71A
Voltage Supervisor with Manual Reset Input
Package Types
Features:
SOT-143
• Precision voltage monitor
SOT-143
- 2.63V, 2.93V, 3.08V, 4.38V and 4.63V trip
points (Typical)
VDD
VDD VSS
VSS
1
4
1
4
• Manual Reset input
MR
2
3
2
MR RST
• Reset Time-out Delay:
3
RST
- Standard: 280 ms (Typical)
- Optional: 2.19 ms, and 35 ms (Typical)
• Power Consumption ≤ 15 µA max
• No glitches on outputs during power-up
• Active Low Output Options:
- Push-Pull Output and Open-Drain Output
• Active High Output Option:
- Push-Pull Output
SOT-23-5
SOT-23-5
VSS
NC
NC
VDD
MR
1
2
3
5
1
2
3
5
VSS
VDD
MR
RST
4
4
RST
Functional Block Diagram
• Replacement for (Specification compatible with):
- TC1270, TC1271
Voltage
Reset
- TCM811, TCM812
VDD
RST
(TC1271A)
RST
(TC1270A)
RST
(TC1270AN)
Detector
PP
PP
OD
Generator
& Delay
• Fully static design
Circuitry
• Low voltage operation (1.0V)
• ESD protection:
Timer
(2.19 ms,
35 ms,
- ≥ 4 kV Human Body Model (HBM)
- ≥ 400V Machine Model (MM)
• Extended (E) Temperature range:
-40°C to +125°C
280 ms)
18.5 kΩ
MR
Glitch Filter
• Package Options:
- 4-lead SOT-143
- 5-lead SOT-23
- Pb-free Device
Device Features
Output
Device
Active
Packages Comment
Type
Level
TC1270A
Push-Pull
Low
SOT-143(2), Replaces TC1270 and
SOT-23-5 TCM811
2.19, 4.63, 4.38, 1.0V
-40°C
to
5.5V +125°C
TC1270AN Open-Drain
TC1271A Push-Pull
Low
35,
3.08, 2.93,
to
SOT-23-5 New Option
SOT-143(2), Replaces TC1271 and
280(1)
2.63(4)
High
SOT-23-5 TCM812
Note 1: The 280 ms Reset Delay time-out is compatible with the TC1270, TC1271, TCM811, and TCM812
devices.
2: The SOT-143 package is compatible with the TC1270, TC1271, TCM811, and TCM812 devices.
3: Custom Reset Trip Points and Reset Delays available, contact factory.
4: The TC1270/1 and TCM811/12 1.75V Trip Point Option is not supported.
© 2007 Microchip Technology Inc.
DS22035B-page 1
TC1270A/70AN/71A
† Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress ratings only and functional
operation of the device at those or any other conditions
above those indicated in the operational listing of this
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD to VSS) ...............................+7.0V
Input Current, VDD..............................................10 mA
Output Current, RESET, RESET........................10 mA
Voltage on all inputs and outputs
w.r.t. VSS ............................ -0.6V to (VDD + 1.0V)
Storage Temperature Range..............-65°C to +150°C
Operating Temperature Range...........-40°C to +125°C
Maximum Junction Temperature, TS................... 150°C
ESD protection on all pins
Human Body Model ....................................... ≥ 4 kV
Machine Model ..............................................≥ 400V
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
Parameter
Sym
Min
Typ(1)
Max
Units
Test Conditions
Operating Voltage Range
Supply Current
VDD
IDD
1.0
—
—
7
5.5
15
V
µA
VDD > VTRIP, for L/M/R/S/T,
VDD = 5.5V
—
4.75
10
10
µA
µA
V
VDD > VTRIP, for R/S/T, VDD = 3.6V
—
15
V
DD < VTRIP, for L/M/R/S/T
TC127xAL: TA = +25°C
TA = –40°C to +125°C
TC127xAM: TA = +25°C
TA = –40°C to +125°C
TC127xAT: TA = +25°C
TA = –40°C to +125°C
TC127xAS: TA = +25°C
TA = –40°C to +125°C
TC127xA:(5) TA = +25°C
TA = –40°C to +125°C
TC127xAR: TA = +25°C
TA = –40°C to +125°C
Reset Trip Point
Threshold (3)
VTRIP
4.54
4.50
4.30
4.25
3.03
3.00
2.88
2.85
2.72
2.70
2.58
2.55
4.63
—
4.72
4.75
4.46
4.50
3.14
3.15
2.98
3.00
2.82
2.85
2.68
2.70
V
4.38
—
V
V
3.08
—
V
V
2.93
—
V
V
2.77
—
V
V
2.63
—
V
V
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.
2: RST output for TC1270A, and TC1270AN, RST output for TC1271A.
3: TC127XA refers to either the TC1270A, TC1270AN or TC1271A device.
4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.
5: Custom ordered Voltage Trip Point. Minimum order volume requirement.
6: This specification allows this device to be used in PIC® microcontroller applications that require the
In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for
voltage requirements). The total time that the RST pin can be above the maximum device operational
voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the
device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional
information, refer to Figure 2-41.
DS22035B-page 2
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
DD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
V
Parameter
Sym
Min
Typ(1)
Max
Units
Test Conditions
Reset Threshold Tempco
—
—
±30
0.3
—
—
ppm/°C
%
Reset Trip Point
Hysteresis (4)
VHYS
VIH
Percentage of VTRIP Voltage
MR Input High Threshold
MR Input Low Threshold
MR Pull-up Resistance
2.3
0.7 VDD
—
—
—
—
—
V
V
VDD > VTRIP(MAX), L/M only
VDD > VTRIP(MAX), R/S/T only
VDD > VTRIP(MAX), L/M only
VDD > VTRIP(MAX), R/S/T only
VIL
—
0.8
V
—
—
0.25 VDD
40
V
10
18.5
—
kΩ
V
Open-Drain High Voltage
on Output
VODH
—
13.5
Open-Drain Output pin only.
VDD = 3.0V, Time voltage > 5.5
applied ≤ 100s. Current into pin
limited to 2 mA +25°C operation
recommended (Note 6)
Reset
TC1270A/
TC1270AN
VOL
—
—
—
—
—
—
—
—
—
0.3
0.3
0.4
0.3
0.3
—
V
V
V
V
V
V
V
R/S/T only,
ISINK = 1.2 mA, VDD = VTRIP(MIN)
Output
Voltage
Low (2)
TC1271A
R/S/T only,
ISINK = 1.2 mA, VDD = VTRIP(MAX)
TC1270A/
TC1270AN
—
L/M only,
ISINK = 3.2 mA, VDD = VTRIP(MIN)
TC1271A
—
L/M only,
ISINK = 3.2 mA, VDD = VTRIP(MAX)
TC1270A/
TC1270AN
—
L/M only,
ISINK = 50 µA, VDD > 1.0V
Reset
TC1270A
TC1270A
TC1271A
VOH
0.8 VDD
VDD - 1.5
R/S/T only,
ISOURCE = 500 µA, VDD = VTRIP(MAX)
Output
Voltage
High (2)
—
L/M only,
ISOURCE = 800 µA, VDD = VTRIP(MAX)
0.8 VDD
—
—
—
—
—
±1
1
V
ISOURCE = 500 µA, VDD ≤ VTRIP(MIN)
VPIN = VDD
Input Leakage Current
IIL
µA
µA
Open-Drain RST Output
Leakage
IOLOD
—
Open-Drain configuration only.
Capacitive Loading
Specification on Output
Pins
CIO
—
—
50
pF
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.
2: RST output for TC1270A, and TC1270AN, RST output for TC1271A.
3: TC127XA refers to either the TC1270A, TC1270AN or TC1271A device.
4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.
5: Custom ordered Voltage Trip Point. Minimum order volume requirement.
6: This specification allows this device to be used in PIC® microcontroller applications that require the
In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for
voltage requirements). The total time that the RST pin can be above the maximum device operational
voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the
device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional
information, refer to Figure 2-41.
© 2007 Microchip Technology Inc.
DS22035B-page 3
TC1270A/70AN/71A
1.1
AC CHARACTERISTICS
1.1.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
T
F
E
Frequency
Error
Time
Lowercase letters (pp) and their meanings:
pp
io
Input or Output pin
Receive
osc
tx
Oscillator
Transmit
Reset
rx
bitclk
drt
RX/TX BITCLK
Device Reset Timer
RST
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 1-1:
TEST LOAD CONDITIONS
CL = 50 pF
Pin
VSS
DS22035B-page 4
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
1.1.2
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 1-2:
MR PIN AND RESET PIN WAVEFORM
tMR
MR
tRST
tMRNI
tMD
RST
RST
FIGURE 1-3:
DEVICE VOLTAGE AND RESET PIN (ACTIVE LOW) WAVEFORM
VTRIP(MAX)
VTRIP
VTRIP(MIN)
VDD
tRST
1V
tRST
tRD
RST(1)
RST
VDD < 1V is outside the device operating specification. The RST (or RST) output state is unknown while VDD < 1V.
Note 1: The TC1270AN requires an external pull-up resistor.
TABLE 1-1:
RESET AND DEVICE RESET TIMER REQUIREMENTS
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
Parameter
DD to Reset Delay
Sym
Min
Typ(1)
Max
Units
Test Conditions
V
tRD
—
50
—
µs
VDD = VTRIP(MAX) to
VTRIP(MIN) –125 mV
Reset Active TC127XAxBVyy (3)
tRST
1.09
17.5
140
10
2.19
35
4.38
70
ms
ms
ms
µs
VDD = VTRIP(MAX)
VDD = VTRIP(MAX)
VDD = VTRIP(MAX)
TC127XAxCVyy (3)
TC127XAxVyy (3)
Timeout
Period
280
—
560
—
MR Minimum Pulse Width
MR Noise Immunity
tMR
tMRNI
tMD
—
0.1
0.2
—
µs
MR to Reset Propagation Delay
—
—
µs
Note 1: Unless otherwise stated, data in the Typical (“Typ”) column is at 5V, +25°C.
2: RST output for TC1270A, RST output for TC1271A.
3: TC127XA refers to either the TC1270A, TC1270AN or TC1271A device. “x” indicated the selected Voltage
Trip Point, while “yy” indicates the package code.
© 2007 Microchip Technology Inc.
DS22035B-page 5
TC1270A/70AN/71A
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.0V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 4L-SOT-143
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
θJA
θJA
—
—
256
426
—
—
°C/W
°C/W
DS22035B-page 6
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
7
6.5
6
2.5
2
5.0V
4.0V
3.0V
5.5V
4.8V
1.5
1
5.5
5
2.0V
1.0V
0.5
0
4.5
Temperature (°C)
Temperature (°C)
FIGURE 2-1:
I
vs. Temperature (Reset
FIGURE 2-4:
I
vs. Temperature (Reset
DD
DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
7
3
5.0V
6.5
5.5V
2.5
6
4.0V
4.5V
2
5.5
5
3.0V
1.5
2.0V
4.5
4
3.5V
1
1.0V
0.5
3.5
3
0
Temperature (°C)
Temperature (°C)
FIGURE 2-2:
I
vs. Temperature (Reset
FIGURE 2-5:
I
vs. Temperature (Reset
DD
DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
3
5.0V
2.5
6.5
5.0V
6
5.5
4.0V
2
4.0V
5
3.0V
1.5
4.5
2.0V
4
1
3.0V
3.5
3
0.5
0
1.0V
2.5
Temperature (°C)
Temperature (°C)
FIGURE 2-3:
I
vs. Temperature (Reset
FIGURE 2-6:
I
vs. Temperature (Reset
DD
DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
© 2007 Microchip Technology Inc.
DS22035B-page 7
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
3
2.5
2
7
6.5
6
+125°C
+25°C
+125°C
1.5
1
+25°C
5.5
5
-40°C
-40°C
0.5
0
4.5
1
2
3
4
5
4.5
4.7
4.9
5.1
5.3
5.5
V
DD (V)
VDD (V)
FIGURE 2-7:
I
vs. V (Reset
FIGURE 2-10:
I
vs. V (Reset
DD
DD
DD DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
3
7
6.5
+125°C
2.5
+125°C
6
2
5.5
+25°C
5
1.5
+25°C
4.5
-40°C
1
4
3.5
3
-40°C
0.5
0
2.5
1
2
3
4
5
3
3.5
4
4.5
5
5.5
VDD (V)
VDD (V)
FIGURE 2-8:
I
vs. V (Reset
FIGURE 2-11:
I
vs. V (Reset
DD
DD
DD DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
3.5
3
7
+125°C
6
2.5
+125°C
2
1.5
1
+25°C
5
+25°C
4
3
2
-40°C
-40°C
0.5
0
1
2
3
4
5
2.5
3
3.5
4
4.5
5
5.5
V
DD (V)
V
DD (V)
FIGURE 2-9:
I
vs. V (Reset
FIGURE 2-12:
I
vs. V (Reset
DD
DD
DD DD
Power-up Timer Inactive)
Power-up Timer Active)
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
DS22035B-page 8
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
0.12
0.1
4.65
4.645
4.64
0.4
VTRIP (with VDD Rising)
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
3.0V
0.08
0.06
0.04
0.02
0
4.635
4.63
4.3V
2.0V
4.625
4.62
4.4V
VHYS
VTRIP (with VDD Falling)
4.5V
4.615
4.61
4.605
0.00
1.00
2.00
OL (mA)
3.00
4.00
-40
25
125
I
Temperature (°C)
FIGURE 2-13:
V
and V
vs.
FIGURE 2-16:
V
vs. I
OL OL
TRIP
HYS
Temperature
(TC1270AL, TC1270ANL, TC1271AL
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
- 4.50V min. / 4.63V typ. / 4.75V max.).
3.086
3.084
3.082
3.08
3.078
3.076
3.074
3.072
3.07
3.068
3.066
0.4
0.25
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
3.15
0.2
VTRIP (with VDD Rising)
3.2V
4.0V
0.15
0.1
0.05
0
VHYS
4.5V
5.0V
VTRIP (with VDD Falling)
5.5V
-40
25
125
0
2
4
6
8
IOL (mA)
Temperature (°C)
FIGURE 2-17:
V
vs. I
FIGURE 2-14:
V
and V
vs.
HYS
OL
OL
TRIP
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
Temperature
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
2.64
0.4
VTRIP (with VDD Rising)
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
2.635
2.45V
2.0V
2.63
2.625
VHYS
2.5V
2.62
VTRIP (with VDD Falling)
2.615
2.61
0
1
2
3
4
-40
25
125
IOL (mA)
Temperature (°C)
FIGURE 2-18:
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
V
vs. I
FIGURE 2-15:
Temperature
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
V
and V
vs.
HYST
OL
OL
TRIP
© 2007 Microchip Technology Inc.
DS22035B-page 9
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
0.12
0.1
5.6
5.4
5.2
5
5.5V
4 mA
2 mA
0.08
0.06
0.04
0.02
0
5.0V
4.8
4.6
4.4
4.2
4.8V
4.75V
2.00
1 mA
0.35 mA
0.5
0.2
0.00
1.00
3.00
OH (mA)
4.00
5.00
-40
10
60
110
I
Temperature (°C)
FIGURE 2-19:
V
vs. Temperature
FIGURE 2-22:
V
vs. I
OH OL
OL
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.)
@ +25°C).
@ V = 4.5V).
DD
0.35
0.3
2.9
2.7
8 mA
2.9V
0.25
0.2
2.7V
6 mA
4 mA
2 mA 1 mA
2.5
2.3
2.1
1.9
1.7
0.15
0.1
2.5V
0.5
0.05
0
0
1
2
3
4
5
-40
10
60
110
Temperature (°C)
IOH (mA)
FIGURE 2-20:
V
vs. Temperature
FIGURE 2-23:
V
vs. I
OH OH
OL
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.)
@ +25°C).
@ V = 2.7V).
DD
6
0.2
0.15
0.1
5.5V
5.5
5.0V
5
4 mA
2 mA
4.5V
4.5
4.0V
4
3.5
0.5
0.35 mA
1 mA
3
2.5
2
3.0V
0.05
0.2
2.8V
0
0
1
2
3
4
5
-40
10
60
110
IOH (mA)
Temperature (°C)
FIGURE 2-21:
V
vs. Temperature
FIGURE 2-24:
V
vs. I
OH OH
OL
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.)
@ +25°C).
@ V = 1.8V).
DD
DS22035B-page 10
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
320
315
310
305
300
295
290
285
280
275
55
54
53
52
51
50
49
48
5.0V
5.5V
4.75V
-40
10
60
110
-40
10
60
110
Temperature (°C)
Temperature (°C)
FIGURE 2-25:
Propagation Delay (t
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
V
Falling to Reset
) vs. Temperature
FIGURE 2-28:
vs. Temperature
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
Reset Timeout Period (t
)
)
)
DD
RST
RST
RST
RPD
55
54
53
52
51
50
49
48
325
320
3.2V
315
310
305
300
295
290
285
280
275
3.15
4.0V
4.5V
5.0V
5.5V
-40
10
60
110
-40
10
60
110
Temperature (°C)
Temperature (°C)
FIGURE 2-26:
Propagation Delay (t
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
V
Falling to Reset
) vs. Temperature
FIGURE 2-29:
vs. Temperature
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
Reset Timeout Period (t
DD
RPD
55
54
53
52
51
50
49
48
320
3.0V
315
310
305
300
295
290
285
280
275
4.5V
5.0V
2.8V
5.5V
4.0V
-40
10
60
110
-40
10
60
110
Temperature (°C)
Temperature (°C)
FIGURE 2-27:
V
Falling to Reset
FIGURE 2-30:
Reset Timeout Period (t
DD
Propagation Delay (t
) vs. Temperature
vs. Temperature
RPD
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
© 2007 Microchip Technology Inc.
DS22035B-page 11
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
2.5
2.45
2.4
40
39
38
37
36
35
34
2.35
2.3
5.0V
2.25
2.2
5.0V
4.75V
4.75V
5.5V
5.5V
2.15
2.1
-40
10
60
Temperature (°C)
110
-40
10
60
110
Temperature (°C)
FIGURE 2-31:
Reset Timeout Period (t
)
)
)
FIGURE 2-34:
Reset Timeout Period (t
)
)
)
RST
RST
RST
RST
RST
RST
(C timeout option) vs. Temperature
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
(B timeout option) vs. Temperature
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
40
2.5
3.2V
3.2V
2.45
2.4
39
3.15V
3.15V
38
2.35
2.3
4.0V
4.0V
4.5V
37
36
35
34
4.5V
2.25
2.2
5.0V
5.5V
5.0V
5.5V
2.15
2.1
-40
10
60
110
-40
10
60
110
Temperature (°C)
Temperature (°C)
FIGURE 2-32:
Reset Timeout Period (t
FIGURE 2-35:
Reset Timeout Period (t
(C timeout option) vs. Temperature
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
(B timeout option) vs. Temperature
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
40
2.5
3.0V
3.0V
2.45
2.4
39
38
37
36
35
34
2.35
2.3
4.5V
4.5V
5.0V
5.0V
2.25
2.2
2.8V
2.8V
5.5V
5.5V
4.0V
2.15
2.1
4.0V
-40
10
60
110
-40
10
60
110
Temperature (°C)
Temperature (°C)
FIGURE 2-33:
Reset Timeout Period (t
FIGURE 2-36:
Reset Timeout Period (t
(C timeout option) vs. Temperature
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
(B timeout option) vs. Temperature
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
DS22035B-page 12
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
0.22
0.21
0.2
60
50
40
30
20
10
0
Above Line, Reset Occurs
2.63V
3.08V
4.8V
5.0V
4.75V
0.19
0.18
0.17
4.63V
5.5V
Below Line, No Reset Occurs
0.001
0.01
0.1
1
10
-40
10
60
110
V
TRIPMIN - VDD (V)
Temperature (°C)
FIGURE 2-37:
MR Low to Reset
FIGURE 2-40:
V
Transient Duration vs.
DD
Propagation Delay (t ) vs. Temperature
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min. / 4.63V typ. / 4.75V max.).
Reset Threshold Overdrive
(V (minimum) - V ).
MD
TRIP
DD
0.22
0.21
1.E-02
1.E-04
1.E-06
1.E-08
1.E-10
1.E-12
1.E-14
13.5V
4.5V
5.5V
0.2
0.19
0.18
0.17
+125°C
+25°C
4.0V
5.0V
-40°C
-40
10
60
110
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Temperature (°C)
Output Voltage (V)
FIGURE 2-38:
Propagation Delay (t ) vs. Temperature
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min. / 3.08V typ. / 3.15V max.).
MR Low to Reset
FIGURE 2-41:
Open-Drain Leakage
MD
Current vs. Voltage Applied to RST Pin
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V minimum).
0.22
0.21
4.0V
0.2
0.19
4.5V
5.0V
0.18
0.17
5.5V
-40
10
60
110
Temperature (°C)
FIGURE 2-39:
MR Low to Reset
Propagation Delay (t ) vs. Temperature
MD
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V min. / 2.63V typ. / 2.70V max.).
© 2007 Microchip Technology Inc.
DS22035B-page 13
TC1270A/70AN/71A
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PINOUT DESCRIPTION
Pin Number
TC1270A
TC1270AN
TC1271A
Pin
(Push-Pull, (Open-Drain, (Push-Pull,
active low)
active low)
active high)
Sym
Standard Function
Buffer
Type
/
Driver
VSS
5
4
1
2
5
1
—
O
Power Ground
—
—
—
RST
Push- Reset output (Push Pull), active low
Pull
H = VDD > VTRIP, Reset pin is inactive
(after Reset Timer Delay completes)
L = VDD < VTRIP, Reset pin is active
Goes active (Low) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
—
—
4
—
—
RST
O
Open- Reset output (Open-Drain), active low
Drain Float = VDD > VTRIP, Reset pin is inactive
(after Reset Timer Delay completes)
L = VDD < VTRIP, Reset pin is active
Goes active (Low) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
—
—
—
4
2
RST
O
Push- Reset output (Push Pull), active high
Pull
H = VDD < VTRIP, Reset pin is active
L = VDD > VTRIP, Reset pin is inactive
(after Reset Timer Delay completes)
Goes active (High) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
Note 1: The MR pin has an internal weak pull-up (18.5 kΩ typical).
DS22035B-page 14
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
TABLE 3-1:
TC1270A
PINOUT DESCRIPTION (CONTINUED)
Pin Number
TC1270AN
TC1271A
Pin
(Push-Pull, (Open-Drain, (Push-Pull,
active low)
active low)
active high)
Sym
Standard Function
Buffer
Type
/
Driver
3
3
—
3
3
MR
I
ST (1) Manual Reset input pin
This input allows a push button switch to be
directly connected to the
TC1270A/70AN/71A’s MR pin, which can then
be used to force a system Reset. The input fil-
ter (ignores) noise pulses that occur on the
MR pin.
H = Switch is open (internal pull-up resistor
pulls signal high). State of the RST/RST
pin determined by other system condi-
tions.
L = Switch is depressed (shorted to ground).
This forces the RST/RST pin Active.
2
1
4
—
—
2
1
4
VDD
NC
—
—
Power Supply Voltage
No Connection
—
—
—
Note 1: The MR pin has an internal weak pull-up (18.5 kΩ typical).
© 2007 Microchip Technology Inc.
DS22035B-page 15
TC1270A/70AN/71A
3.1
Ground Terminal (VSS)
3.4
Manual Reset Input (MR)
VSS provides the negative reference for the analog
input voltage. Typically, the circuit ground is used.
The Manual Reset (MR) input pin allows a push button
switch to easily be connected to the system. When the
push button is depressed, it forces a system Reset.
This pin has circuitry that filters noise that may be
present on the MR signal.
3.2
Supply Voltage (VDD)
VDD can be used for power supply monitoring or a
voltage level that requires monitoring.
The MR pin is active-low and has an internal pull-up
resistor.
3.3
Reset Output (RST and RST)
There are three types of Reset output pins. These are:
1. Push-Pull active-low Reset
2. Push-Pull active-high Reset
3. Open-Drain active-low Reset, External pull-up
resistor required.
3.3.1
ACTIVE-LOW (RST) - PUSH-PULL
The RST push-pull output remains low while VDD is
below the reset voltage threshold (VTRIP). The time that
the RST pin is held low after the device voltage (VDD
)
returns to a high level (> VTRIP) is typically 280 ms.
After the Reset delay timer expires, the RST pin will be
driven to the high state.
3.3.2
ACTIVE-HIGH (RST) - PUSH-PULL
The RST push-pull output remains high while VDD is
below the reset voltage threshold (VTRIP). The time that
the RST pin is held high after the device voltage (VDD
)
returns to a high level (> VTRIP) is typically 280 ms.
After the Reset delay timer expires, the RST pin will be
driven to the low state.
3.3.3
ACTIVE-LOW (RST) - OPEN-DRAIN
The RST open-drain output remains low while VDD is
below the reset voltage threshold (VTRIP). The time that
the RST pin is held low after the device voltage (VDD
)
returns to a high level (> VTRIP) depends on the Reset
Timeout selected. After the Reset Delay Timer expires,
the RST pin will float.
DS22035B-page 16
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
Figure 4-2 shows a typical circuit for a push-pull device
and Figure 4-3 shows a typical circuit for an open-drain
device.
4.0
4.1
DEVICE OPERATION
General Description
For many of today’s microcontroller applications, care
must be taken to prevent low-power conditions that can
cause many different system problems. The most
common causes are brown-out conditions, where the
system supply drops below the operating level
momentarily. The second most common cause is when
a slowly decaying power supply causes the microcon-
troller to begin executing instructions without sufficient
voltage to sustain volatile memory (RAM), thus
producing indeterminate results.
VDD
MR
Voltage
Detector
Circuit
VRST
Reset
Generator
Circuit
RST
or
RST
Manual Reset
with Glitch
Filter Circuit
MRRST
FIGURE 4-1:
Diagram.
TC127XA High Level Block
The TC127XA family (TC1270A, TC1270AN, and
TC1271A) are cost-effective voltage supervisor
devices designed to keep a microcontroller in Reset
until the system voltage has reached and stabilized at
the proper level for reliable system operation. These
devices also operate as protection from brown-out
conditions when the system supply voltage drops
below a safe operating level.
VDD
0.1 µF
VDD
VDD
TC1270A/1A
RST
or
RST
Reset Input
VSS
MR
A Manual Reset input (MR pin) is provided. This allows
a push button switch to be directly connected to the
TC127XA device, and is suitable for use as a push
button Reset. This allows the system to easily be reset
from the external control of the push button switch. No
external components are required.
Push
Button
VSS
FIGURE 4-2:
Application Circuit.
Typical Push-Pull
The Reset pin (RST or RST) will be forced active, if any
of the following occur:
• During device power up
VDD
• VDD goes below the device threshold voltage
• The Manual Reset input (MR) goes low
0.1 µF
VDD
TC1270AN
MR
RST
VDD
Figure 4-1 shows a high level block diagram of the
devices. The device can be described with three
functional blocks. These are:
Reset Input
VSS
Push
Button
• Voltage Detect circuit
• Manual Reset with Glitch Filter circuit
• Reset Generator circuit
VSS
The Reset Generator circuit controls the reset delay
time of the reset output signal.
FIGURE 4-3:
Application Circuit.
Typical Open-Drain
There are three Reset Delay time options. Depending
on the option, the reset signal (RST/RST pin) will be
held active for a minimum of 1.09 ms, 17.5 ms, or
140 ms.
The TC1270A and TC1271A devices are available in a
4-Pin SOT-143 package to maintain footprint compati-
bility with the TC1270, TC1271, TCM811, and TCM812
devices, and the SOT-23-5 package. The TC1270AN is
only available in the SOT-23-5 package.
The TC1271A has an active-high RST output while the
TC1270A and TC1270AN have an active-low RST
output.
Low supply current makes these devices suitable for
battery powered applications.
The TC1270A and TC1271A have a push-pull output
driver, while the TC1270AN has an open-drain output.
Device specific block diagrams are shown in Figure 4-4
through Figure 4-6.
© 2007 Microchip Technology Inc.
DS22035B-page 17
TC1270A/70AN/71A
4.2
Voltage Detect Circuit
VDD
The Voltage Detect Circuit monitors VDD. The device’s
Reset voltage trip point (VTRIP) is selected when the
device is ordered. The voltage on the device’s VDD pin
determines the output state of the RST/RST pin.
Comparator
Output
+
Driver
(Push-
Pull)
RST
–
Reference
Voltage
VDD voltages above the VTRIP(MAX) force the RST/RST
pin inactive. VDD voltages below the VTRIP(MIN) force
the RST/RST pin active. The state of the RST/RST pin
is unknown for VDD voltages between VTRIP(MAX) and
VTRIP(MIN). This is shown in Table 4-1
Delay
MR
Noise Filter
TABLE 4-1:
V
LEVELS TO RST/RST
DD
FIGURE 4-4:
TC1270A Block Diagram.
OUTPUT STATES
VDD
Output State
VDD Voltage Level
RST
RST
Comparator
Output
Driver
(Open-
Drain)
+
VDD ≥ VTRIP(MAX)
H (1, 2)
L (1)
U
RST
–
VTRIP(MIN) < VDD < VTRIP(MAX)
VDD ≤ VTRIP(MIN)
U
L
Reference
Voltage
H
Delay
Legend: H = Driven High
L = Driven Low
U = Unknown, driven either High or Low
MR
Noise Filter
Note 1: The RST/RST pin will be driven inactive
after the Reset Delay Timer (tRST) times
out.
VSS
FIGURE 4-5:
TC1270AN Block Diagram.
2: The TC1270AN RST pin will be floated
after the Reset Delay Timer (tRST) times
out.
VDD
The term VTRIP will be used as the general term for the
trip point voltage where the device actually trips.
Comparator
Output
Driver
(Push-
Pull)
+
RST
In the case where VDD is falling (for voltages starting
above VTRIP(MAX)):
–
Reference
Voltage
• Voltages above VTRIP(MAX) will never cause the
RST/RST output pin to be driven Active.
Delay
MR
• Voltages below VTRIP(MIN) will always cause the
RST/RST output pin to be driven Active.
Noise Filter
Now in the case where VDD is rising (for voltages
starting below VTRIP(MIN)):
FIGURE 4-6:
TC1271A Block Diagram.
• Voltages above VTRIP(MAX) will always cause the
RST/RST output pin to be driven Inactive, (or
floated - TC1270AN) after the Reset Delay Timer
(tRST), times out.
DS22035B-page 18
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
Table 4-2 shows the various device trip point options
and their VTRIP(MAX) and VTRIP(MIN) voltages. Also the
negative percentage change from common regulated
voltages is shown.
4.2.1
HYSTERESIS
There is also a minimal hysteresis (VHYS) on the trip
point. This is so that small noise signals on the device
voltage (VDD) do not cause the Reset pin (RST/RST) to
“jitter” (change between driving an active and inactive).
In the case where VDD is falling from the regulated volt-
age, as the VDD crosses the VTRIP voltage the
RST/RST pin is driven active. Now the desired circuitry
is in reset, or the circuitry has the indication that the
The characterization graphs shown in Figures 2-13
through 2-15 shows the device hysteresis as a percent-
age of the voltage trip point (VTRIP).
VDD is below the selected VTRIP
.
The Reset Delay Timer (tRST) gives a time based hys-
teresis for the system.
In the case where VDD is rising. As the VDD crosses the
VTRIP voltage, the RST/RST pin is driven inactive after
the Reset Delay Timer elapses. Now the desired cir-
cuitry is released from reset and will start to operate in
its normal mode, or the circuitry has the indication that
4.2.2
POWER-UP/RISING V
DD
As the device VDD rises, the device’s Reset circuit will
remain active until the voltage rises above the “actual”
trip point (VTRIP).
the VDD is above the selected VTRIP
.
Figure 4-7 shows a power-up sequence and the wave-
form of the RST and RST pins. As the device powers
up, the voltage will start below the valid operating volt-
age of the device. At this voltage, the RST/RST output
is not valid. Once the voltage is above the minimum
TABLE 4-2:
SELECTING THE TRIP POINT
(1)
- % From
Regulated Voltage
Trip
Voltage
Selection VTRIP(MIN)
VTRIP(MAX)
/
(2)
5.0V
3.3V
3.0V
operating voltage (1V) and below the selected VTRIP
,
L
M
T
4.75V
4.50V
4.50V
4.25V
3.15V
3.00V
3.00V
2.85V
2.70V
2.55V
5.0%
10.0%
10.0%
15.0%
—
—
—
—
—
the Reset output will be active.
Once the device voltage rises above the VTRIP voltage,
the Reset delay timer (tRST) starts. When the Reset
delay timer times out, the Reset output (RST/RST) is
driven inactive.
—
—
—
—
4.5%
9.2%
9.2%
13.7%
—
—
—
—
VTRIP
S
R
—
—
—
—
(1)
VDD
tRST
1V
—
10.0%
15.0%
—
—
Note 1: Voltage regulator circuit must have tighter
tolerance (%) than VTRIP(MAX) % from
regulated voltage.
RST(2)
2: Circuitry being reset must have a wider
tolerance (%) than VTRIP(MIN) % from
regulated voltage.
RST
The TC1270A/TC1270AN/TC1271A devices are
optimized to reject fast transient glitches on the VDD
line. If the low input signal (which is below VTRIP) is not
rejected, the Reset output is driven active within 50 µs
of VDD falling through the Reset voltage threshold.
Note 1: Additional system current is consumed
during the tRST time.
2: The TC1270AN requires an external
pull-up resistor.
After the device exits the Reset condition, the delay
circuitry will hold the RST/RST pin active until the
appropriate Reset delay time (tRST) has elapsed.
FIGURE 4-7:
Power-up.
RST/RST pin Operation
During device power up, the input voltage is below the
Trip Point voltage. The device must enter the valid
operating range for the device to start operation.
© 2007 Microchip Technology Inc.
DS22035B-page 19
TC1270A/70AN/71A
Figure 4-8 shows the waveform of the RST pin as
determined by the VDD voltage. As the VDD voltage falls
from the normal operating point, the device “enters”
reset by crossing the VTRIP voltage (between
VTRIP(MAX) and VTRIP(MIN)). Then when VDD voltage
rises, the device “exits” reset by crossing the VTRIP volt-
age (below or at VTRIP(MAX)). After the “exit” state has
been detected, the Reset Delay Timer (tRST) starts.
Once the tRST time completes, the Reset pin is driven
inactive.
4.2.3
POWER-DOWN/BROWN-OUTS
As the device powers-down/brown-outs, the VDD falls
from a voltage above the devices trip point (VTRIP). The
device will trip at a voltage between the maximum trip
point (VTRIP(MAX)
) and the minimum trip point
(VTRIP(MIN)). Once the device voltage (VDD) goes
below this voltage, the RST/RST pin will be forced to
the active state.
Table 4-3 shows the state of the RST or RST pins.
TABLE 4-3:
Device
RESET PIN STATES
State of RST Pin when:
State of RST Pin when:
Output Driver
VDD < VTRIP VDD > VTRIP
(1)
(1)
VDD < VTRIP
VDD > VTRIP
TC1270A
TC1271A
L
H
—
H
—
L
Push-Pull
Push-Pull
—
—
Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out.
VTRIP
(with VDD Rising)
VDD
VTRIP
(with VDD Falling)
1V
RST(1)
tRST
tRST
< 1V is outside the
tRD
tRD
device specifications
Note 1: The TC1270AN requires an external pull-up resistor.
RST Operation as determined by the V
FIGURE 4-8:
.
TRIP
DS22035B-page 20
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
4.3
Negative Going VDD Transients
4.4
Manual Reset with Glitch Filter
Circuit
The minimum pulse width (time) required to cause a
Reset may be an important criteria in the implementa-
tion of a Power-on Reset (POR) circuit. This time is
referred to as transient duration. The TC127XA devices
are designed to reject a level of negative-going
transients (glitches) on the power supply line.
The Manual Reset input pin (MR) allows the Reset pins
(RST/RST) to be manually forced to their active states.
The MR pin has circuitry to filter noise pulses that may
be present on the pin. Figure 4-10 shows a block
diagram for using the TC127XA with a push button
switch. To minimize the required external components,
the MR input has an internal pull-up resistor.
Transient duration is the amount of time needed for
these supervisory devices to respond to a drop in VDD
.
The transient duration time (tTRAN) is dependent on the
magnitude of VTRIP – VDD (overdrive). Any combination
of duration and overdrive that lies under the
duration/overdrive curve will not generate a Reset
signal. Generally speaking, the transient duration time
decreases with an increase in the VTRIP – VDD voltage.
A mechanical push button or active logic signal can
drive the MR input.
Once MR has been low for a time, tMD (the Manual
Reset delay time), the Reset output pins are forced
active. The Reset output pins will remain in their active
states for the Reset delay timer time out period (tRST).
Figure 4-9 shows an example transient duration vs.
Reset comparator overdrive. It shows that the farther
below the trip point the transient pulse goes, the
duration of the pulse required to cause a Reset gets
shorter. So any combination of duration and overdrive
that lays under the curve will not generate a Reset
signal. Combinations above the curve are detected as
a brown-out or power-down.
Figure 4-11 shows a waveform for the Manual Reset
switch input and the Reset pins output.
+5V
VDD
MR
Transient immunity can be improved by adding a
bypass capacitor (typically 0.1 µF) as close as possible
to the VDD pin of the TC127XA device.
PIC® MCU
TC127XA
RST
MCLR
VSS
5V
VTRIP(MAX)
VTRIP(MIN)
VTRIP(MIN) - VDD
(Overdrive)
FIGURE 4-10:
Push Button Reset.
tTRAN (Duration)
tMR
0V
Time (µs)
tMD
MR
VIH
tRST
Area above curve will
generate a reset signal
VIL
RST
RST
Area below curve will
not generate a reset signal
The MR input typically ignores input pulses
of 100 ns.
Transient Overdrive Voltage (mV)
FIGURE 4-11:
MR Input – Push Button.
FIGURE 4-9:
Example of Typical
Transient Duration Waveform.
4.4.1 NOISE FILTER
The noise filter filters out noise spikes (glitches) on the
Manual Reset pin (MR). Noise spikes less than 100 ns
(typical) are filtered.
© 2007 Microchip Technology Inc.
DS22035B-page 21
TC1270A/70AN/71A
4.5.2
EFFECT OF TEMPERATURE ON
RESET POWER-UP TIMER (t
4.5
Reset Generator Circuit
)
RPU
The output signals from the Voltage Detect Circuit and
the Manual Reset with Glitch Filter Circuit are OR’d
together and is used to activate the Reset Generator
Module.
The Reset delay timer time out period (tRST
)
determines how long the device remains in the Reset
condition. This time out is affected by both the device
VDD and temperature. Typical responses for different
VDD values and temperatures are shown in
Figures 2-28, 2-29 and 2-30.
After the reset conditions have been removed (the MR
pin is no longer forced low and the input voltage is
greater than the Trip Point voltage), the Reset Genera-
tor circuit determines the reset delay timeout required.
TABLE 4-4:
RESET DELAY TIMER
TIME OUTS
There are three options for the delay circuit. These are:
• 2.19 ms (typical) delay
• 35 ms (typical) delay
• 280 ms (typical) delay
tRST
Units
Min
Typ
Max
1.09
17.5
140
↑
2.19
35
4.38
70
ms
ms
ms
4.5.1
RESET DELAY TIMER
The Reset delay timer ensures that the TC127XA
device will “hold” the embedded system in Reset until
the system voltage has stabilized. The Reset delay
timer time out is shown in Table 4-4.
280
560
↑
This is the
minimum time that
the Reset Delay
Timer will “hold”
the Reset pin
This is the
maximum time
that the Reset
Delay Timer will
“hold” the Reset
pin active after
VDD rises above
The Reset Delay Timer starts once the Voltage
Detector Circuit output AND the Manual Reset with
Glitch Filter Circuit output become inactive. While the
Reset Delay Timer is active, the RST or RST pin is
driven to the active state. Once the Reset Delay Timer
times-out, the RST or RST pin is driven inactive.
active after VDD
rises above VTRIP
VTRIP
The Reset delay timer (tRST) starts after the device
voltage rises above the “actual” trip point (VTRIP).
When the Reset delay timer times out, the Reset output
pin (RST/RST) is driven inactive.
Note 1: Shaded rows are custom ordered time
outs.
VDD
The Reset Delay Timer is cleared, if either (or both) the
Voltage Detector Circuit output OR the Manual Reset
with Glitch Filter Circuit output become active. The RST
or RST pin continues to be driven to the active state.
VTRIP
tRST
RST
Figure 4-12 illustrates when the Reset Delay Timer
(tRST) is active or inactive.
Reset
Delay
Timer
Reset Delay
Inactive
Timer Inactive
See Figures 2-9,
2-7 and 2-8
See Figures 2-9,
2-7 and 2-8
See Figures 2-12, 2-11 and 2-10
FIGURE 4-12:
Reset Power-up Timer
Waveform.
DS22035B-page 22
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
5.3
Using in PIC® Microcontroller,
ICSP™ Applications
5.0
APPLICATION INFORMATION
This section shows application related information that
may be useful for your particular design requirements.
Note:
This operation can only be done using the
device with the Open-Drain RST pin
(TC1270AN).
5.1
Supply Monitor Noise Sensitivity
The TC127XA devices are optimized for fast response
to negative-going changes in VDD. Systems with an
inordinate amount of electrical noise on VDD (such as
systems using relays) may require a 0.01 µF or 0.1 µF
bypass capacitor to reduce detection sensitivity. This
capacitor should be installed as close to the TC127XA
as possible to keep the capacitor lead length short.
Figure 5-4 shows the typical application circuit for using
the TC1270AN for voltage supervisory function when
the PIC microcontroller will be programmed via the
In-Circuit Serial Programming™ (ICSP™) feature.
Additional information is available in TB087, “Using
Voltage Supervisors with PICmicro® Microcontroller
Systems which Implement In-Circuit Serial Program-
ming™”, DS91087.
Note:
It is recommended that the current into the
RST pin be current limited by a 1 kΩ
resistor.
0.1 µF
VDD
TC127XA
RST
VDD/VPP
RST
MR
VSS
0.1 µF
VDD
RPU
VDD
PIC®
Microcontroller
TC1270AN
FIGURE 5-1:
Typical Application Circuit
with Bypass Capacitor.
MCLR
Reset input)
(Active-Low)
RST
VSS
1 kΩ
5.2
Conventional Voltage Monitoring
VSS
Figure 5-2 and Figure 5-3 show the TC127XA in
conventional voltage monitoring applications.
FIGURE 5-4:
for PIC Microcontroller with the ICSP™
Feature.
Typical Application Circuit
®
+
VDD
–
TC127XA
BATLOW
RST
VSS
FIGURE 5-2:
Battery Voltage Monitor.
VDD
+
RST
Pwr
Sply
TC127XA
Power Good
–
VSS
FIGURE 5-3:
Power Good Monitor.
© 2007 Microchip Technology Inc.
DS22035B-page 23
TC1270A/70AN/71A
5.4
Modifying The Trip Point, VTRIP
5.5
MOSFET Low-Drive Protection
Although the TC127XA device has a fixed voltage trip
point (VTRIP), it is sometimes necessary to make
custom adjustments. This can be accomplished by
connecting an external resistor divider to the TC127XA
VDD pin. This causes the VSOURCE voltage to be at a
higher voltage than when the TC127XA input equals
it’s VTRIP voltage (Figure 5-5).
Low operating power and small physical size make the
TC1270AN series ideal for many voltage detector
applications. Figure 5-6 shows a low-voltage gate drive
protection circuit that prevents overheating of the
logic-level MOSFET due to insufficient gate voltage.
When the input signal is below the threshold of the
TC1270AN, its output grounds the gate of the
MOSFET.
To maintain detector accuracy, the bleeder current
through the divider should be significantly higher than
the 15 µA maximum operating current required by the
TC127XA. A reasonable value for this bleeder current
is 1 mA (67 times the 10 µA required by the TC127XA).
For example, if VTRIP = 2V and the desired trip point is
2.5V, the value of R1 + R2 is 2.5 kΩ (2.5V/1 mA). The
value of R1 + R2 can be rounded to the nearest stan-
dard value and plugged into the equation of Figure 5-5
to calculate values for R1 and R2. 1% tolerance resis-
tors are recommended.
VTRIP
270Ω (1)
VDD
VDD
RL
MTP3055EL
RST
TC1270AN
VSS
VSOURCE
Note 1: This resistance needs to be properly
sized for the selected Trip point voltage
related to the VOL operation.
R2
VDD
RST
TC127XA
or RST
FIGURE 5-6:
MOSFET Low-Drive
Protection.
R1
VSS
R
1
-------------------
V
×
= V
SOURCE
TRIP
R + R
1
2
Where:
VSOURCE
VTRIP
Note:
=
=
Voltage to be monitored
Threshold Voltage setting
In this example, VSOURCE must be
greater than (VTRIP).
FIGURE 5-5:
Modify Trip-Point using
External Resistor Divider.
DS22035B-page 24
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
5.6
Controllers and Processors With
Bidirectional I/O Pins
5.8
Reset Signal Integrity During
Power-Down
Some microcontrollers have bidirectional Reset pins.
Depending on the current drive capability of the
controller pin, an indeterminate logic level may result if
there is a logic conflict. This can be avoided by adding
a 4.7 kΩ resistor in series with the output of the
TC127XA (Figure 5-7). If there are other components
in the system that require a Reset signal, they should
be buffered so as not to load the Reset line. If the other
components are required to follow the Reset I/O of the
microcontroller, the buffer should be connected as
shown with the solid line.
The TC1270A and TC1271A reset output is valid down
to VDD = 1.0V. Below this voltage the output becomes
an “open circuit” and does not sink current. This means
CMOS logic inputs to the Microcontroller will be floating
at an undetermined voltage. Most digital systems are
completely shut down well above this voltage.
However, in situations where the Reset signal must be
maintained valid to VDD = 0V, external circuitry is
required.
For devices where the Reset signal is active-low, a
pull-down resistor must be connected from the
TC1270A RST pin to ground to discharge stray
capacitances and hold the output low (Figure 5-9).
Buffered
Reset to
Similarly for devices where the Reset signal is
active-high, a pull-up resistor to VDD is required to
ensure a valid high RST signal for VDD below 1.0V
(Figure 5-10).
system
VDD
VDD
VDD
TC1270A/71A
This resistor value, though not critical, should be
chosen such that it does not appreciably load the Reset
pin under normal operation (100 kΩ will be suitable for
most applications).
RST
MR
Reset I/O
VSS
or
4.7 kΩ
RST
VSS
VDD
VDD
TC1270A
FIGURE 5-7:
Interfacing the TC1270A or
TC1271A Push-Pull Output to a Bidirectional
Reset I/O pin.
MR
RST
VSS
R1
100 kΩ
5.7
Migration Paths
Figure 5-8 shows the 5-pin SOT-23 footprint of the
TC1270A, TC1270AN and TC1271A devices. Devices
that are in the 3-pin SOT-23 package could be used in
that circuit with the loss of the Manual Reset
functionality. Examples of compatible footprint devices
in the SOT-23-3 package are the MCP111, MCP112,
TC54, and TC51 devices. This allows the system to be
designed to offer a “base” functionality and a higher
end system with the “enhanced” functionality, which
includes a manual reset.
FIGURE 5-9:
Reset pin output state as V approaches 0V.
Ensuring a valid active-low
DD
VDD
VDD
R1
100 kΩ
TC1271A
MR
RST
SOT-23-3
VSS
SOT-23-5
VSS
NC
VDD
MR
2
1
2
3
5
VSS
VDD
3
RST
or
RST
or
1
4
FIGURE 5-10:
Reset pin output state as V approaches 0V.
Ensuring a valid active-high
RST
RST
DD
FIGURE 5-8:
SOT-23 5-pin to 3-pin
Comparison.
© 2007 Microchip Technology Inc.
DS22035B-page 25
TC1270A/70AN/71A
The configuration includes the:
• Voltage Trip Point (VTRIP
• Reset Time Out (tRST
6.0
STANDARD DEVICES
)
Table 6-1 shows the standard devices and their order
number that are available and their respective
configuration.
)
TABLE 6-1:
STANDARD VERSIONS
Reset Threshold (V) Reset Time Out (ms)
Device
Order Number
Replaces
SOT-23-5 TC1270ALVCTTR
SOT-143 TC1270ALVRCTR
SOT-23-5 TC1270AMVCTTR
SOT-143 TC1270AMVRCTR
SOT-23-5 TC1270ATVCTTR
SOT-143 TC1270ATVRCTR
SOT-23-5 TC1270ASVCTTR
SOT-143 TC1270ASVRCTR
SOT-23-5 TC1270ARVCTTR
SOT-143 TC1270ARVRCTR
—
TC1270A
TC1270A
TC1270A
TC1270A
TC1270A
4.50 4.63 4.75
4.25 4.38 4.50
3.00 3.08 3.15
2.85 2.93 3.00
2.55 2.63 2.70
L
M
T
140 280 560 “blank”
140 280 560 “blank”
140 280 560 “blank”
140 280 560 “blank”
140 280 560 “blank”
TC1270LERC /
TCM811LERC
—
TC1270MERC /
TCM811MERC
—
TC1270TERC /
TCM811TERC
—
S
R
TC1270SERC /
TCM811SERC
—
TC1270RERC /
TCM811RERC
TC1270AN 4.50 4.63 4.75
TC1270AN 4.25 4.38 4.50
TC1270AN 3.00 3.08 3.15
TC1270AN 2.85 2.93 3.00
TC1270AN 2.55 2.63 2.70
L
M
T
140 280 560 “blank” SOT-23-5 TC1270ANLVCT
140 280 560 “blank” SOT-23-5 TC1270ANMVCT
140 280 560 “blank” SOT-23-5 TC1270ANTVCT
140 280 560 “blank” SOT-23-5 TC1270ANSVCT
140 280 560 “blank” SOT-23-5 TC1270ANRVCT
SOT-23-5 TC1271ALVCTTR
—
—
—
—
—
—
S
R
TC1271A
TC1271A
TC1271A
TC1271A
TC1271A
4.50 4.63 4.75
4.25 4.38 4.50
3.00 3.08 3.15
2.85 2.93 3.00
2.55 2.63 2.70
L
M
T
140 280 560 “blank”
TC1271LERC /
TCM812LERC
SOT-143 TC1271ALVRCTR
SOT-23-5 TC1271AMVCTTR
—
140 280 560 “blank”
TC1271MERC /
TCM812MERC
SOT-143 TC1271AMVRCTR
SOT-23-5 TC1271ATVCTTR
—
140 280 560 “blank”
TC1271TERC /
TCM812TERC
SOT-143 TC1271ATVRCTR
SOT-23-5 TC1271ASVCTTR
—
S
R
140 280 560 “blank”
TC1271SERC /
TCM812SERC
SOT-143 TC1271ASVRCTR
SOT-23-5 TC1271ARVCTTR
—
140 280 560 “blank”
TC1271RERC /
TCM812RERC
SOT-143 TC1271ARVRCTR
Note 1: “A” timeout delay options are only standard in the SOT-23-5 package. SOT-143 package is a custom
request.
DS22035B-page 26
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
7.0
CUSTOM CONFIGURATIONS
The following Custom Reset Trip Point is available (see
Table 7-1).
TABLE 7-1:
CUSTOM TRIP POINT
- % From
Trip
Voltage
Selection
VTRIP(MAX)
Regulated Voltage
/
VTRIP(MIN)
3.0V
(1)
2.85V
2.70V
5.0%
10.0%
Note 1: Contact factory for additional information.
Table 7-2 shows the codes that specify the desired
Reset time out (tRST) for custom devices
TABLE 7-2:
DELAY TIME OUT ORDERING CODES
Code
Reset Delay Comment
Time (Typ) (ms)
B
C
2.19
35
Note 1
Note 1
“blank”
280
Delay timings for standard device offerings
Note 1: This delay timing option is not the standard offering. For information on ordering devices with these delay
times, contact your local Microchip sales office. Minimum purchase volumes are required.
© 2007 Microchip Technology Inc.
DS22035B-page 27
TC1270A/70AN/71A
The SOIC14-EV (102-00094) board has a SOT-23-6
footprint, that can be jumpered into any portion of the
circuit. This will allow any footprint that the TC1270A
requires in the SOT-23-5 package.
8.0
8.1
DEVELOPMENT TOOLS
Evaluation/Demonstration Boards
The SOT-23-5/6 Evaluation Board (VSUPEV2) can be
used to evaluate the characteristics of the TC127XA
devices.
This blank PCB has footprints for:
• Pull-up Resistor
• Pull-down Resistor
• Loading Capacitor
• In-line Resistor
There is also a power supply filtering capacitor.
For evaluating the TC127XA devices, the selected
device should be installed into the Option A footprint.
FIGURE 8-2:
SOIC-14 Evaluation Board
(SOIC14EV).
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
FIGURE 8-1:
SOT-23-5/6 Voltage
Supervisor Evaluation Board (VSUPEV2).
DS22035B-page 28
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
5-Pin SOT-23
Example:
Part Number
Code
Part Number
Code
TC1270ALVCTTR
TC1270AMVCTTR
TC1270ATVCTTR
TC1270ASVCTTR
TC1270ARVCTTR
TC1270ANLVCTTR
TC1270ANMVCTTR
TC1270ANTVCTTR
TC1270ANSVCTTR
TC1270ANRVCTTR
F1NN
F2NN
F3NN
F4NN
F5NN
FSNN
FTNN
FUNN
FVNN
FWNN
TC1271ALVCTTR
TC1271AMVCTTR
TC1271ATVCTTR
TC1271ASVCTTR
TC1271ARVCTTR
J1NN
J2NN
J3NN
J4NN
J5NN
XXNN
F125
4-Lead SOT-143
Example:
Part Number
Code
Part Number
Code
TC1270ALVRCTR
TC1270AMVRCTR
TC1270ATVRCTR
TC1270ASVRCTR
TC1270ARVRCTR
TC1270ANLVRCTR
TC1270ANMVRCTR
TC1270ANTVRCTR
TC1270ANSVRCTR
TC1270ANRVRCTR
D1NN
D2NN
D3NN
D4NN
D5NN
E1NN
E2NN
E3NN
E4NN
E5NN
TC1271ALVRCTR
TC1271AMVRCTR
TC1271ATVRCTR
TC1271ASVRCTR
TC1271ARVRCTR
C1NN
C2NN
C3NN
C4NN
C5NN
XXNN
C125
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
YY
WW
NN
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS22035B-page 29
TC1270A/70AN/71A
5-Lead Plastic Small Outline Transistor (CT) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
N
E
E1
3
2
1
e
e1
D
A2
c
A
φ
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Lead Pitch
N
e
5
0.95 BSC
Outside Lead Pitch
Overall Height
e1
A
1.90 BSC
0.90
0.89
0.00
2.20
1.30
2.70
0.10
0.35
0°
–
–
–
–
–
–
–
–
–
–
–
1.45
1.30
0.15
3.20
1.80
3.10
0.60
0.80
30°
Molded Package Thickness
Standoff
A2
A1
E
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
L
Footprint
L1
φ
Foot Angle
Lead Thickness
Lead Width
c
0.08
0.20
0.26
0.51
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-091B
DS22035B-page 30
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
4-Lead Plastic Small Outline Transistor (RC) [SOT-143]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
e/2
N
E
E1
1
2
e1
A2
A
c
φ
A1
L
L1
b
3X
b2
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
4
1.92 BSC
Lead 1 Offset
Overall Height
e1
A
0.20 BSC
0.80
0.75
0.01
2.10
1.20
2.67
0.13
–
1.22
1.07
0.15
2.64
1.40
3.05
0.60
Molded Package Thickness
Standoff §
A2
A1
E
0.90
–
Overall Width
–
Molded Package Width
Overall Length
Foot Length
E1
D
1.30
2.90
L
0.50
Footprint
L1
φ
0.54 REF
Foot Angle
0°
–
–
–
–
8°
Lead Thickness
Lead 1 Width
c
0.08
0.76
0.30
0.20
0.94
0.54
b1
b
Leads 2, 3 & 4 Width
Notes:
1. § Significant Characteristic.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-031B
© 2007 Microchip Technology Inc.
DS22035B-page 31
TC1270A/70AN/71A
9.2
Product Tape and Reel Specifications
FIGURE 9-1:
EMBOSSED CARRIER DIMENSIONS (8 MM TAPE ONLY)
Top
Cover
Tape
A0
W
B0
P
K0
TABLE 1:
CARRIER TAPE/CAVITY DIMENSIONS
Carrier
Cavity
Dimensions
Output
Quantity
Units
Reel
Diameter in
mm
Dimensions
Case
Package
Outline
Type
W
P
A0
B0
mm
K0
mm
mm
mm
mm
OT
RC
SOT-23
5L
4L
8
8
4
4
3.2
3.1
3.2
1.4
1.3
3000
3000
180
180
SOT-143
2.69
FIGURE 9-2:
5-LEAD SOT-23 DEVICE TAPE AND REEL SPECIFICATIONS
Device
Marking
User Direction of Feed
Pin 1
W, Width
of Carrier
Tape
Pin 1
P, Pitch
Standard Reel Component Orientation
Reverse Reel Component Orientation
DS22035B-page 32
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
FIGURE 9-3:
4-LEAD SOT-143 DEVICE TAPE AND REEL SPECIFICATIONS
Component Taping Orientation for 4-Pin SOT-143 Devices
User Direction of Feed
Device
Marking
W
Pin 1
P
Standard Reel Component Orientation
for TR Suffix Device
(Mark Right Side Up)
Carrier Tape, Number of Components Per Reel and Reel Size:
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
4-Pin SOT-143
8 mm
4 mm
3000
7 in.
© 2007 Microchip Technology Inc.
DS22035B-page 33
TC1270A/70AN/71A
NOTES:
DS22035B-page 34
© 2007 Microchip Technology Inc.
TC1270A/70AN/71A
APPENDIX A: REVISION HISTORY
Revision B (June 2007)
• Added new options:
- Open-Drain output
- New Reset Delay timeouts.
• Updated Package Outline Drawings
• Updated Revision History
• Added new options to Product Identification
System
Revision A (March 2007)
• Original Release of this Document.
© 2007 Microchip Technology Inc.
DS22035B-page 35
TC1270A/70AN/71A
NOTES:
DS22035B-page 36
© 2007 Microchip Technology Inc.
TC1270A//70AN/71A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
Examples:
PART NO.
Device
XX
X
XX
X
a)
TC1270ASVCTTR:
Temperature Package
Range
Tape/Reel
Option
Reset Delay
Options
VTRIP
Options
2.85V min. / 2.93V typ. / 3.00V max.
voltage trip point,
Push-pull active low reset,
Reset Delay Timer = 280 ms,
5-LD SOT-23, Tape and Reel,
-40°C to +125°C
Device:
TC1270A: Voltage Supervisor with Manual Reset
TC1270AN: Voltage Supervisor with Manual Reset
TC1271A: Voltage Supervisor with Manual Reset
b)
TC1270ALVRCTR:
4.50V min. / 4.63V typ. / 4.75V max.
voltage trip point,
Push-pull active low reset,
Reset Delay Timer = 280 ms,
4-LD SOT-143, Tape and Reel,
-40°C to +125°C
V
Options:
R
S
T
M
L
= 2.55V (min.) / 2.63V (typ.) / 2.70V (max.)
= 2.85V (min.) / 2.93V (typ.) / 3.00V (max.)
= 3.00V (min.) / 3.08V (typ.) / 3.15V (max.)
= 4.25V (min.) / 4.38V (typ.) / 4.50V (max.)
= 4.50V (min.) / 4.63V (typ.) / 4.75V (max.)
TRIP
c)
d)
e)
TC1270ANMBVCTTR:
4.25V min. / 4.38V typ. / 4.50V max.
Open-drain active low reset,
Reset Delay Timer = 2.19 ms,
5-Lead SOT-23, Tape and Reel,
-40°C to +125°C
Time Out Options:
B
C
=
=
t
t
t
= 2.19 ms (typ)
= 35 ms (typ)
= 280 ms (typ)
RST
RST
RST
“blank” =
TC1270ANLCVCT:
Temperature Range:
Package:
V
= -40°C to +125°C
4.50V min. / 4.63V typ. / 4.75V max.
Open-drain active low reset,
Reset Delay Timer = 35 ms,
5-Lead SOT-23,
CT = Plastic Small Outline Transistor, SOT-23, 5-lead
RC = Plastic Small Outline Transistor, SOT-143,
4-lead
-40°C to +125°C
TC1271ARVCTTR:
2.55V min. / 2.63V typ. / 2.70V max.
voltage trip point,
Tape/Reel Option:
TR
= Tape and Reel
Push-pull active high reset,
Reset Delay Timer = 280 ms,
5-LD SOT-23, Tape and Reel,
-40°C to +125°C
f)
TC1271ATVRCTR:
3.00V min. / 3.08V typ. / 3.15V max.
voltage trip point,
Push-pull active high reset,
Reset Delay Timer = 280 ms,
4-LD SOT-143, Tape and Reel,
-40°C to +125°C
© 2007 Microchip Technology Inc.
DS22035B-page 37
TC1270A//70AN/71A
NOTES:
DS22035B-page 38
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS22035B-page 39
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AMERICAS
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 480-792-7200
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Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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06/25/07
DS22035B-page 40
© 2007 Microchip Technology Inc.
相关型号：
TC1270AMAVCTTR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, LEAD FREE, PLASTIC, SOT-23, 5 PIN
MICROCHIP
TC1270ANLAVRCTR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4, LEAD FREE, PLASTIC, SOT-143, 4 PIN
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