TC1301A-UWAVMFTR [MICROCHIP]
Dual LDO with Microcontroller RESET Function; 双路LDO与微控制器复位功能
| 型号： | TC1301A-UWAVMFTR |
| 厂家： | 
MICROCHIP |
| 描述： | Dual LDO with Microcontroller RESET Function |
| 文件： | 总28页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC1301A/B
Dual LDO with Microcontroller RESET Function
Features
Description
• Dual Output LDO with Microcontroller Reset
Monitor Functionality:
The TC1301A/B combines two Low Dropout (LDO)
regulators and a microcontroller RESET function into a
single 8-pin MSOP or DFN package. Both regulator
outputs feature low dropout voltage, 104 mV
- VOUT1 = 1.5V to 3.3V @ 300 mA
- VOUT2 = 1.5V to 3.3V @ 150 mA
- VRESET = 2.20V to 3.20V
@ 300 mA for VOUT1, 150 mV @ 150 mA for VOUT2
,
low quiescent current consumption, 58 µA each and a
typical regulation accuracy of 0.5%. Several fixed-
output voltage and detector voltage combinations are
available. A reference bypass pin is available to further
reduce output noise and improve the power supply
rejection ratio of both LDOs.
• Output Voltage and RESET Threshold Voltage
Options Available (See Table 8-1)
• Low Dropout Voltage:
- VOUT1 = 104 mV @ 300 mA, Typical
- VOUT2 = 150 mV @ 150 mA, Typical
The TC1301A/B is stable over all line and load
conditions with a minimum of 1 µF of ceramic output
capacitance, and utilizes a unique compensation
scheme to provide fast dynamic response to sudden
line voltage and load current changes.
• Low Supply Current: 116 µA, Typical
TC1301A/B with both output voltages available
• Reference Bypass Input for Low-Noise Operation
• Both Output Voltages Stable with a Minimum of
1 µF Ceramic Output Capacitor
For the TC1301A, the microcontroller RESET function
operates independently of both VOUT1 and VOUT2. The
input to the RESET function is connected to the VDET
pin.The SHDN2 pin is used to control the output of
• Separate Input for RESET Detect Voltage
(TC1301A)
• Separate VOUT1 and VOUT2 SHDN pins
(TC1301B)
V
OUT2 only. VOUT1 will power-up and down with VIN.
In the case of the TC1301B, the detect voltage input of
the RESET function is connected internally to VOUT1
• RESET Output Duration: 300 ms. Typical
• Power-Saving Shutdown Mode of Operation
• Wake-up from SHDN: 5.3 µs. Typical
• Small 8-pin DFN and MSOP Package Options
• Operating Junction Temperature Range:
- -40°C to +125°C
.
Both VOUT1 and VOUT2 have independent shutdown
capability.
Additional features include an overcurrent limit and
overtemperature protection that, when combined,
provide a robust design for all load fault conditions.
• Overtemperature and Overcurrent Protection
Applications
Package Types
• Cellular/GSM/PHS Phones
• Battery-Operated Systems
• Hand-Held Medical Instruments
• Portable Computers/PDAs
• Linear Post-Regulators for SMPS
• Pagers
8-Pin DFN/MSOP
TC1301A
DFN8
MSOP8
VDET
VIN
RESET 1
8
7
6
5
1
2
3
RESET
VOUT1
GND
8
7
6
5
VDET
VIN
VOUT1
2
VOUT2
VOUT2
GND
3
4
Related Literature
Bypass 4
SHDN2
Bypass
SHDN2
• AN765, “Using Microchip’s Micropower LDOs”,
DS00765, Microchip Technology Inc., 2002
TC1301B
DFN8
MSOP8
• AN766, “Pin-Compatible CMOS Upgrades to
BiPolar LDOs”, DS00766, Microchip Technology
Inc., 2002
SHDN1
VIN
RESET 1
8
7
6
5
1
2
3
RESET
VOUT1
GND
8
7
6
5
SHDN1
VIN
VOUT1
2
• AN792, “A Method to Determine How Much
Power a SOT23 Can Dissipate in an Application”,
DS00792, Microchip Technology Inc., 2001
VOUT2
VOUT2
GND
3
4
Bypass 4
SHDN2
Bypass
SHDN2
© 2005 Microchip Technology Inc.
DS21798B-page 1
TC1301A/B
Functional Block Diagrams
TC1301A
TC1301B
LDO #1
VOUT1
VOUT1
VIN
VIN
LDO #1
300 mA
SHDN1
300 mA
VOUT2
VOUT2
LDO #2
150 mA
LDO #2
150 mA
SHDN2
SHDN2
GND
GND
Bandgap
Reference
1.2V
Bandgap
Reference
1.2V
Bypass
Bypass
VDET
RESET
RESET
Threshold
Detector
Time Delay
300 ms typ
VDET
Threshold
Detector
Time Delay
300 ms, typ
Typical Application Circuits
TC1301A
VDET
RESET
8
7
6
1
System RESET
BATTERY
2
3
4
2.8V @ 300 mA
VOUT1
GND
VIN
COUT1
1 µF Ceramic
X5R
CIN
1 µF
2.6V @ 150 mA
COUT2
VOUT2
5
SHDN2
2.7V
to
Bypass
1 µF Ceramic
X5R
(Note)
CBYPASS
10 nF Ceramic
4.2V
ON/OFF Control VOUT2
ON/OFF Control VOUT1
8
TC1301B
1
System RESET
2.8V @ 300 mA
RESET SHDN1
2
3
7
6
BATTERY
VOUT1
GND
VIN
COUT1
1 µF Ceramic
X5R
CIN
1 µF
2.6V @ 150 mA
COUT2
VOUT2
4
5
Bypass SHDN2
2.7V
to
4.2V
1 µF Ceramic
X5R
ON/OFF Control VOUT2
Note: CBYPASS is optional
DS21798B-page 2
© 2005 Microchip Technology Inc.
TC1301A/B
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
...................................................................................6.5V
DD
Maximum Voltage on Any Pin ...... (V – 0.3) to (V + 0.3)V
SS
IN
Power Dissipation ..........................Internally Limited (Note 7)
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, T ...........................+150°C
J
Continuous Operating Temperature Range ..-40°C to +125°C
ESD protection on all pins, HBM, MM..................... 4 kV, 400V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C
= C = 1 µF,
OUT2
IN
R
OUT1
OUT2
IN
OUT1
C
= 10 nF, SHDN > V , T = +25°C.
BYPASS
IH A
Boldface type specifications apply for junction temperatures of -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Operating Voltage
Maximum Output Current
Maximum Output Current
Output Voltage Tolerance
V
2.7
300
150
—
—
—
6.0
—
V
Note 1
IN
I
I
mA
mA
%
V
V
= 2.7V to 6.0V (Note 1)
= 2.7V to 6.0V (Note 1)
OUT1Max
OUT2Max
IN
IN
—
V
V
– 2.5 V ±0.5
V + 2.5
R
Note 2
OUT
R
R
(V
and V
)
OUT1
OUT2
Temperature Coefficient
TCV
—
—
-1
25
0.02
0.1
—
0.2
+1
ppm/°C Note 3
OUT
(V
and V
)
OUT1
OUT2
Line Regulation
(V and V
ΔV
/
%/V
%
(V +1V) ≤ V ≤ 6V
OUT
R
IN
)
ΔV
OUT1
OUT2
IN
Load Regulation, V
≥ 2.5V
ΔV
/
/
I
= 0.1 mA to I
(Note 4)
(Note 4)
OUT
OUT
OUT
OUT
OUTX
OUTX
OUTMax
(V
and V
)
V
OUT1
OUT2
Load Regulation, V
(V and V
< 2.5V
ΔV
-1.5
0.1
+1.5
—
%
I
= 0.1 mA to I
OUT
OUT
OUTMax
)
OUT2
V
OUT1
Thermal Regulation
Dropout Voltage (Note 6)
ΔV
/ΔP
—
0.04
%/W
Note 5
OUT
D
V
V
≥ 2.7V
≥ 2.6V
V
– V
– V
—
—
104
150
180
250
mV
mV
I
I
= 300 mA
OUT1
OUT2
IN
OUT
OUT
OUT1
V
= 150 mA
IN
OUT2
Supply Current
TC1301A
I
—
—
103
114
180
180
µA
µA
SHDN2 = V , V
= OPEN,
DET
IN(A)
IN(B)
IN
I
= I
= 0 mA
OUT1
OUT2
TC1301B
I
SHDN1 = SHDN2 = V ,
IN
I
= I
= 0 mA
OUT1
OUT2
Note 1: The minimum V has to meet two conditions: V ≥ 2.7V and V ≥ V + V
.
IN
IN
IN
R
DROPOUT
2:
V
is defined as the higher of the two regulator nominal output voltages (V
or V
).
R
OUT1
OUT2
6
3: TCV
= ((V
- V
) * 10 )/(V
* ΔT).
OUT
OUT
OUTmax
OUTmin
4: Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to I
t = 10 ms.
at V = 6V for
IN
LMAX
6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value
measured at a 1V differential.
7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction-to-air (i.e., T , T , θ ). Exceeding the maximum allowable power
A
J
JA
dissipation causes the device to initiate thermal shutdown.
© 2005 Microchip Technology Inc.
DS21798B-page 3
TC1301A/B
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C
= C = 1 µF,
OUT2
IN
R
OUT1
OUT2
IN
OUT1
C
= 10 nF, SHDN > V , T = +25°C.
BYPASS
IH A
Boldface type specifications apply for junction temperatures of -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
90
Units
Conditions
Shutdown Supply Current
I
I
—
58
µA
µA
SHDN2 = GND, V
= OPEN
DET
IN_SHDNA
TC1301A
Shutdown Supply Current
—
—
—
0.1
58
1
SHDN1 = SHDN2 = GND
IN_SHDNB
TC1301B
f ≤ 100 Hz, I
= I
= 50 mA,
OUT2
OUT1
Power Supply Rejection Ratio
Output Noise
PSRR
—
—
dB
C
= 0 µF
IN
f ≤ 1 kHz, I
= I
= 50 mA,
½
OUT1
OUT2
eN
830
nV/(Hz)
C
= 0 µF
IN
Output Short-Circuit Current (Average)
V
I
—
—
45
—
200
140
—
—
—
—
15
mA
mA
R
R
≤ 1Ω
OUT1
OUT2
OUTsc
OUTsc
LOAD1
LOAD2
V
I
≤ 1Ω
SHDN Input High Threshold
SHDN Input Low Threshold
Wake-Up Time (From SHDN
V
%V
%V
V
V
V
= 2.7V to 6.0V
= 2.7V to 6.0V
IH
IN
IN
IN
IN
IN
V
—
IL
= 5V, I
= I
= 30 mA,
= 50 mA,
OUT1
OUT2
OUT2
t
—
—
5.3
50
20
—
µs
µs
WK
mode), (V
)
See Figure 5-1
OUT2
Settling Time (From SHDN mode),
(V
V
IN
= 5V, I
= I
OUT1
t
S
)
See Figure 5-2
OUT2
Thermal Shutdown Die
Temperature
T
—
—
150
10
—
—
°C
°C
V
V
V
= 5V, I
= 5V
= I
= 100 µA
SD
IN
OUT1
OUT2
Thermal Shutdown Hysteresis
Voltage Range
T
HYS
IN
1.0
1.2
6.0
6.0
T = 0°C to +70°C
A
V
—
DET
T = -40°C to +125°C
A
RESET Threshold
V
-1.4
-2.8
—
—
—
30
+1.4
+2.8
—
%
%
TH
T = -40°C to +125°C
A
RESET Threshold Tempco
ΔV /ΔT
ppm/°C
µs
TH
V
= V to (V – 100 mV),
TH TH
DET
V
RESET Delay
t
t
—
180
300
—
DET
RPD
RPU
See Figure 5-3
V
= V - 100 mV to V + 100 mV,
TH TH
DET
RESET Active Time-out Period
RESET Output Voltage Low
RESET Output Voltage High
140
560
ms
V
I
= 1.2 mA, See Figure 5-3.
SINK
V
= V
, I
= 1.2 mA,
DET
THmin SINK
V
—
—
—
0.2
I
= 100 µA for V < 1.8V,
OL
SINK
DET
See Figure 5-3
0.9
V
> V , I = 500 µA,
THmax SOURCE
DET
V
—
V
OH
V
See Figure 5-3
DET
Note 1: The minimum V has to meet two conditions: V ≥ 2.7V and V ≥ V + V
.
IN
IN
IN
R
DROPOUT
2:
V
is defined as the higher of the two regulator nominal output voltages (V
or V
).
R
OUT1
OUT2
6
3: TCV
= ((V
- V
) * 10 )/(V
* ΔT).
OUT
OUT
OUTmax
OUTmin
4: Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to I
t = 10 ms.
at V = 6V for
IN
LMAX
6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value
measured at a 1V differential.
7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction-to-air (i.e., T , T , θ ). Exceeding the maximum allowable power
A
J
JA
dissipation causes the device to initiate thermal shutdown.
DS21798B-page 4
© 2005 Microchip Technology Inc.
TC1301A/B
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all limits are specified for: V = +2.7V to +6.0V.
IN
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Operating Junction Temperature
Range
TA
-40
—
+125
°C
Steady State
Storage Temperature Range
Maximum Junction Temperature
Thermal Package Resistances
Thermal Resistance, MSOP8
Thermal Resistance, DFN8
TA
TJ
-65
—
—
—
+150
+150
°C
°C
Transient
θJA
θJA
—
—
208
41
—
—
°C/W Typical 4-Layer Board
°C/W Typical 4-Layer Board with Vias
© 2005 Microchip Technology Inc.
DS21798B-page 5
TC1301A/B
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C C = 1 µF (X5R or X7R),
OUT1 = OUT2
IN
R
OUT1
OUT2
IN
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1
A
350
300
3.00
TJ = 25°C
TJ = 25°C
OUT1 = IOUT2 = 0 µA
VOUT1 Active
TC1301B
IOUT1 = 100 mA
I
IOUT2 = 50 mA
2.90
250
200
150
100
50
VOUT1
2.80
VOUT2 Active
VOUT2 SHDN
2.70
VOUT2
0
2.60
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
Input Voltage (V)
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
6
FIGURE 2-1:
Quiescent Current vs. Input
FIGURE 2-4:
Output Voltage vs. Input
Voltage.
Voltage.
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.50
VOUT1
ON
VOUT2
OFF
TJ = +25°C
IOUT1 = 300 mA
IOUT2 = 100 mA
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
6
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input Voltage (V)
6
FIGURE 2-2:
SHDN Voltage Threshold
FIGURE 2-5:
Output Voltage vs. Input
vs. Input Voltage.
Voltage.
140
140.0
TC1301B
VIN = 4.2V
OUT1 = IOUT2 = 0 µA
VOUT1 Active
VR1 = 2.8V
R2 = 2.6V
OUT2 = 100 µA
130
120
110
100
90
VOUT2 Active
I
V
I
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TJ = +125°C
TJ = +25°C
VOUT2 SHDN
TJ = - 40°C
80
70
60
50
40
0
50
100
150
200
250
300
-40 -25 -10
5
20 35 50 65 80 95 110 125
I
OUT1 (mA)
Junction Temperature (°C)
FIGURE 2-3:
Junction Temperature.
Quiescent Current vs.
FIGURE 2-6:
Current (VOUT1).
Dropout Voltage vs. Output
DS21798B-page 6
© 2005 Microchip Technology Inc.
TC1301A/B
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C C = 1 µF (X5R or X7R),
OUT1 = OUT2
IN
R
OUT1
OUT2
IN
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1
A
0.40
140
120
VR1 = 2.8V
VR2 = 2.6V
IOUT2 = 100 µA
VOUT2
IOUT2 = 0.1 mA to 150 mA
IOUT1 = 0.1 mA to 300 mA
0.30
0.20
IOUT1 = 300 mA
100
80
60
40
20
0
VOUT1
0.10
0.00
-0.10
IOUT1 = 100 mA
IOUT1 = 50 mA
VR1 = 2.8V
-0.20
VR2 = 2.6V
-0.30
-0.40
VIN = 4.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (125°C)
Junction Temperature (°C)
FIGURE 2-7:
Dropout Voltage vs.
FIGURE 2-10:
VOUT1 and VOUT2 Load
Junction Temperature (VOUT1).
Regulation vs. Junction Temperature.
180
0.045
VIN = 3.8V to 6.0V
VR1 = 2.8V
VR2 = 2.6V
160
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.000
VR1 = 2.8V, IOUT1 = 100 µA
R2 = 2.6V, IOUT2 = 100 µA
TJ = +125°C
TJ = +25°C
TJ = - 40°C
V
140
I
OUT1 = 100 µA
VOUT2
120
100
80
60
40
20
0
VOUT1
0
30
60
90
120
150
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
IOUT2 (mA)
FIGURE 2-8:
Dropout Voltage vs. Output
FIGURE 2-11:
VOUT1 and VOUT2 Line
Current (VOUT2).
Regulation vs. Junction Temperature.
180
2.832
VIN = 4.2V
VR1 = 2.8V
IOUT2 = 150 mA
160
2.828
V
R2 = 2.6V, IOUT2 = 100 µA
IOUT1 = 300 mA
140
VR1 = 2.8V
R2 = 2.6V
IOUT1 = 100 µA
V
IOUT1 = 100 mA
120
2.824
2.820
2.816
2.812
2.808
100
80
IOUT2 = 50 mA
IOUT2 = 10 mA
60
IOUT1 = 100 µA
40
20
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-9:
Dropout Voltage vs.
FIGURE 2-12:
VOUT1 vs. Junction
Junction Temperature (VOUT2).
Temperature.
© 2005 Microchip Technology Inc.
DS21798B-page 7
TC1301A/B
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C
C
= 1 µF (X5R or X7R),
IN
R
OUT1
OUT2
IN
OUT1 = OUT2
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1
A
2.856
2.848
30
VR1 = 2.8V
VR1 = 2.8V, IOUT1 = 300 mA
R2 = 2.6V, IOUT2 = 100 µA
VDET = 6.0V
VR2 = 2.6V
V
25
20
15
10
5
VIN = 3.0V
VDET = 4.2V
VDET = 3.0V
2.840
2.832
2.824
2.816
2.808
VIN = 4.2V
VIN = 6.0V
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-13:
VOUT1 vs. Junction
FIGURE 2-16:
IDET current vs. Junction
Temperature.
Temperature.
2.645
2.640
2.635
2.630
2.625
2.620
2.615
400
375
350
325
300
275
250
225
200
VIN = 4.2V
IOUT2 = 100 µA
VR1 = 2.8V
VR2 = 2.6V
VDET = 2.63V
IOUT2 = 50 mA
IOUT2 = 150 mA
VIN = 4.2V
R1 = 2.8V, IOUT1 = 100 µA
VR2 = 2.6V
V
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-14:
VOUT2 vs. Junction
FIGURE 2-17:
RESET Active Time vs.
Temperature.
Junction Temperature.
2.644
2.6395
2.6390
2.6385
2.6380
2.6375
2.6370
2.6365
2.6360
2.6355
VIN = 3.0V
VIN = 6.0V
VR1 = 2.8V, IOUT1 = 100 µA
VR2 = 2.6V, IOUT2 = 150 mA
2.640
2.636
2.632
2.628
2.624
VIN = 4.2V
VIN = 4.2V
VR1 = 2.8V
VR2 = 2.6V
VDET = 2.63V
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-15:
Temperature.
VOUT2 vs. Junction
FIGURE 2-18:
Temperature.
VDET Trip Point vs. Junction
DS21798B-page 8
© 2005 Microchip Technology Inc.
TC1301A/B
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C C = 1 µF (X5R or X7R),
OUT1 = OUT2
IN
R
OUT1
OUT2
IN
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1
A
10
1
VOUT1
VOUT2
VIN = 4.2V
0.1
V
R1 = 2.8V
R2=2.6V
V
I
OUT1 = 150 mA
IOUT2 100 mA
BYPASS = 10 nF
0.01
=
C
0.001
0.01
0.1
1
10
100
1000
Frequency (KHz)
FIGURE 2-19:
Power Supply Rejection
FIGURE 2-22:
VOUT1 and VOUT2 Noise vs.
Ratio vs. Frequency (without bypass capacitor).
Frequency (with bypass capacitor).
FIGURE 2-20:
Power Supply Rejection
FIGURE 2-23:
VOUT1 and VOUT2 Power-up
Ratio vs. Frequency (with bypass capacitor).
from Shutdown TC1301B.
10
VOUT2
1
VOUT1
VIN = 4.2V
V
R1 = 2.8V
R2=2.6V
V
0.1
I
OUT1 = 150 mA
IOUT2 100 mA
BYPASS = 0 nF
=
C
0.01
0.01
0.1
1
10
100
1000
Frequency (KHz)
FIGURE 2-21:
VOUT1 and VOUT2 Noise vs.
FIGURE 2-24:
VOUT2 Power-up from
Frequency (without bypass capacitor).
Shutdown Input TC1301A.
© 2005 Microchip Technology Inc.
DS21798B-page 9
TC1301A/B
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C
C
= 1 µF (X5R or X7R),
IN
R
OUT1
OUT2
IN
OUT1 = OUT2
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1 A
FIGURE 2-25:
from Input Voltage TC1301B.
VOUT1 and VOUT2 Power-up
FIGURE 2-28:
VOUT2
150 mA Dynamic Load Step
.
FIGURE 2-26:
Dynamic Line Response.
FIGURE 2-29:
RESET Power-Up From VIN
TC1301B.
FIGURE 2-27:
VOUT1
300 mA Dynamic Load Step
FIGURE 2-30:
Down.
TC1301A RESET Power-
.
DS21798B-page 10
© 2005 Microchip Technology Inc.
TC1301A/B
Note: Unless otherwise indicated, V = V +1V, I
= I
= 100 µA, C = 4.7 µF, C C = 1 µF (X5R or X7R),
OUT1 = OUT2
IN
R
OUT1 OUT2
IN
C
= 0 pF, SHDN1 = SHDN2 > V . For the TC1301A, V
= V
, RESET = OPEN, T = +25°C.
BYPASS
IH
DET
OUT1
A
0.35
0.30
4.4
4.2
VR1 = 2.8V,VR2 = 2.6V
VDET = VTH - 20 mV
IOL = 3.2 mA
VDET = 4.2V
RESETISOURCE = 800 µA
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0.25
0.20
0.15
0.10
0.05
0.00
VR1 = 2.8V,VR2 = 2.6V
DET = VTH + 20 mV
V
IOL = 1.2 mA
VDET = 3.0V
RESETISOURCE = 500 µA
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
FIGURE 2-31:
RESET Output Voltage Low
FIGURE 2-32:
RESET Output Voltage High
vs. Junction Temperature.
vs. Junction Temperature.
© 2005 Microchip Technology Inc.
DS21798B-page 11
TC1301A/B
3.0
TC1301A PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
TC1301A PIN FUNCTION TABLE
Name
Pin No.
Function
1
RESET
Push-pull output pin that will remain low while VDET is below the reset threshold and for
300 ms after VDET rises above the reset threshold.
2
3
4
VOUT1
GND
Regulated output voltage #1 capable of 300 mA.
Circuit ground pin.
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
5
6
7
8
SHDN2
VOUT2
VIN
Output #2 shutdown control Input.
Regulated output voltage #2 capable of 150 mA.
Unregulated input voltage pin.
VDET
Input pin for Voltage Detector (VDET).
3.1
RESET Output Pin
3.5
Output Voltage #2 Shutdown
(SHDN2)
The push-pull output pin is used to monitor the voltage
on the VDET pin. If the VDET voltage is less than the
threshold voltage, the RESET output will be held in the
low state. As the VDET pin rises above the threshold,
the RESET output will remain in the low state for
300 ms and then change to the high state, indicating
that the voltage on the VDET pin is above the threshold.
ON/OFF control is performed by connecting SHDN2 to
its proper level. When the input of this pin is connected
to a voltage less than 15% of VIN, VOUT2 will be OFF. If
this pin is connected to a voltage that is greater than
45% of VIN, VOUT2 will be turned ON.
3.6
Regulated Output Voltage #2
(V
)
OUT2
3.2
Regulated Output Voltage #1
(V
)
Connect VOUT2 to the positive side of the VOUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. VOUT2 can be turned ON and
OFF using SHDN2.
OUT1
Connect VOUT1 to the positive side of the VOUT1
capacitor and load. It is capable of 300 mA maximum
output current. VOUT1 output is available when VIN is
available; there is no pin to turn it OFF. See TC1301B
if ON/OFF control of VOUT1 is desired.
3.7
Unregulated Input Voltage Pin
(V )
IN
3.3
Circuit Ground Pin (GND)
Connect the unregulated input voltage source to VIN. If
the input voltage source is located more than several
inches away, or is a battery, a typical input capacitance
of 1 µF to 4.7 µF is recommended.
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 µA maximum).
3.8
Input Pin for Voltage Detector
(V
3.4
Reference Bypass Input
)
DET
By connecting an external 10 nF capacitor (typical) to
the bypass input, both outputs (VOUT1 and VOUT2) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage start-up time will increase with the addition of
an external bypass capacitor. By leaving this pin
unconnected, the start-up time will be minimized.
The voltage on the input of VDET is compared with the
preset VDET threshold voltage. If the voltage is below
the threshold, the RESET output will be low. If the
voltage is above the VDET threshold, the RESET output
will be high after the RESET time period. The IDET
supply current is typically 9 µA at room temperature,
with VDET = 3.8V.
DS21798B-page 12
© 2005 Microchip Technology Inc.
TC1301A/B
4.0
TC1301B PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
TC1301B PIN FUNCTION TABLE
Name
Pin No.
Function
1
RESET
Push-pull output pin that will remain low while VDET is below the reset threshold and for
300 ms after VOUT1 rises above the reset threshold
2
3
4
VOUT1
GND
Regulated output voltage #1 capable of 300 mA
Circuit ground pin
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance
5
6
7
8
SHDN2
VOUT2
VIN
Output #2 shutdown control Input
Regulated output voltage #2 capable of 150 mA
Unregulated input voltage pin
SHDN1
Output #1 shutdown control input
4.1
RESET Output Pin
4.5
Output Voltage #2 Shutdown
(SHDN2)
The push-pull output pin is used to monitor the output
voltage (VOUT1). If VOUT1 is less than the threshold volt-
age, the RESET output will be held in the low state. As
VOUT1 rises above the threshold, the RESET output will
remain in the low state for 300 ms and then change to
the high state, indicating that the voltage on VOUT1 is
above the threshold.
ON/OFF control is performed by connecting SHDN2 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT2 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT2 will be turned ON.
4.6
Regulated Output Voltage #2
(V
4.2
Regulated Output Voltage #1
(V
)
OUT2
)
OUT1
Connect VOUT2 to the positive side of the VOUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. VOUT2 can be turned ON and
OFF using SHDN2.
Connect VOUT1 to the positive side of the VOUT1
capacitor and load. It is capable of 300 mA maximum
output current. For the TC1301B, VOUT1 can be turned
ON and OFF using the SHDN1 input pin.
4.7
Unregulated Input Voltage Pin
(V )
4.3
Circuit Ground Pin (GND)
IN
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 µA maximum).
Connect the unregulated input voltage source to VIN. If
the input voltage source is located more than several
inches away or is a battery, a typical minimum input
capacitance of 1 µF and 4.7 µF is recommended.
4.4
Reference Bypass Input
4.8
Output Voltage #1 Shutdown
(SHDN1)
By connecting an external 10 nF capacitor (typical) to
bypass, both outputs (VOUT1 and VOUT2) will have less
noise and improved Power Supply Ripple Rejection
(PSRR) performance. The LDO output voltage start-up
time will increase with the addition of an external
bypass capacitor. By leaving this pin unconnected, the
start-up time will be minimized.
ON/OFF control is performed by connecting SHDN1 to
its proper level. When this pin is connected to a voltage
less than 15% of VIN, VOUT1 will be OFF. If this pin is
connected to a voltage that is greater than 45% of VIN,
VOUT1 will be turned ON.
© 2005 Microchip Technology Inc.
DS21798B-page 13
TC1301A/B
the LDO as is practical. Larger input capacitors will help
reduce the input impedance and further reduce any
high-frequency noise on the input and output of the
LDO.
5.0
5.1
DETAILED DESCRIPTION
Device Overview
The TC1301A/B is a combination device consisting of
one 300 mA LDO regulator with a fixed output voltage,
5.6
Output Capacitor
V
OUT1 (1.5V – 3.3V), one 150 mA LDO regulator with a
A minimum output capacitance of 1 µF for each of the
TC1301A/B LDO outputs is necessary for stability.
Ceramic capacitors are recommended because of their
size, cost and environmental robustness qualities.
Electrolytic (Tantalum or Aluminum) capacitors can be
used on the LDO outputs as well. The Equivalent
Series Resistance (ESR) requirements on the
electrolytic output capacitors are between 0 and 2
ohms. The output capacitor should be located as close
to the LDO output as is practical. Ceramic materials,
X7R and X5R, have low temperature coefficients and
are well within the acceptable ESR range required. A
typical 1 uF X5R 0805 capacitor has an ESR of 50 milli-
ohms. Larger LDO output capacitors can be used with
the TC1301A/B to improve dynamic performance and
power supply ripple rejection performance. A maximum
of 10 µF is recommended. Aluminum electrolytic
capacitors are not recommended for low temperature
applications of < -25°C.
fixed output voltage, VOUT2 (1.5V – 3.3V), and a
microcontroller voltage monitor/RESET (2.2V to 3.2V).
For the TC1301A, the 300 mA output (VOUT1) is always
present, independent of the level of SHDN2. The
150 mA output (VOUT2) can be turned on/off by
controlling the level of SHDN2.
For the TC1301B, VOUT1 and VOUT2 each have
independent shutdown input pins (SHDN1 and
SHDN2) to control their respective outputs. In the case
of the TC1301B, the voltage detect input of the
microcontroller RESET function is internally connected
to the VOUT1 output of the device.
5.2
LDO Output #1
LDO output #1 is rated for 300 mA of output current.
The typical dropout voltage for VOUT1 = 104 mV @
300 mA. A 1 µF (minimum) output capacitor is needed
for stability and should be located as close to the VOUT1
pin and ground as possible.
5.7
Bypass Input
The bypass pin is connected to the internal LDO
reference. By adding capacitance to this pin, the LDO
ripple rejection, input voltage transient response and
output noise performance are all increased. A typical
bypass capacitor between 470 pF to 10 nF is
recommended. Larger bypass capacitors can be used,
but results in a longer time-period for the LDO outputs
to reach their rated output voltage when started from
SHDN or VIN.
5.3
LDO Output #2
LDO output #2 is rated for 150 mA of output current.
The typical dropout voltage for VOUT2 = 150 mV. A 1 µF
(minimum) capacitor is needed for stability and should
be located as close to the VOUT2 pin and ground as
possible.
5.4
RESET Output
The RESET output is used to detect whether the level
on the input of VDET (TC1301A) or VOUT1 (TC1301B) is
above or below a preset threshold. If the voltage
detected is below the preset threshold, the RESET
output is capable of sinking 1.2 mA (VRESET < 0.2V
maximum). Once the voltage being monitored is above
the preset threshold, the RESET output pin will
transition from a logic-low to a logic-high after a 300 ms
delay. The RESET output is a push-pull configuration
and will actively pull the RESET output up to VDET
when not in RESET.
5.8
GND
For the optimal noise and PSRR performance, the
GND pin of the TC1301A/B should be tied to a quiet
circuit ground. For applications that have switching or
noisy inputs, tie the GND pin to the return of the output
capacitor. Ground planes help lower inductance and
voltage spikes caused by fast transient load currents
and are recommended for applications that are
subjected to fast load transients.
5.9
SHDN1/SHDN2 Operation
The TC1301A SHDN2 pin is used to turn VOUT2 ON
and OFF. A logic-high level on SHDN2 will enable the
5.5
Input Capacitor
Low input source impedance is necessary for the two
LDO outputs to operate properly. When operating from
batteries or in applications with long lead length (> 10
inches) between the input source and the LDO, some
input capacitance is recommended. A minimum of
1.0 µF to 4.7 µF is recommended for most applications.
When using large capacitors on the LDO outputs,
larger capacitance is recommended on the LDO input.
The capacitor should be placed as close to the input of
VOUT2 output, while a logic-low on the SHDN2 pin will
disable the VOUT2 output. For the TC1301A, VOUT1 is
not affected by SHDN2 and will be enabled as long as
the input voltage is present.
The TC1301B SHDN1 and SHDN2 pins are used to
turn VOUT1 and VOUT2 ON and OFF. They operate
independent of each other.
DS21798B-page 14
© 2005 Microchip Technology Inc.
TC1301A/B
5.10 TC1301A SHDN2 Timing
5.12
V
and RESET Operation
DET
VOUT1 will rise independent of the level of SHDN2 for
the TC1301A. Figure 5-1 is used to define the wake-up
time from shutdown (tWK) and the settling time (tS). The
wake-up time is dependant upon the frequency of
operation. The faster the SHDN pin is pulsed, the
shorter the wake-up time will be.
The TC1301A/B integrates an independent voltage
reset monitor that can be used for low-battery input
voltage detection or a microprocessor Power-On Reset
(POR) function. The input voltage for the detector is
different for the TC1301A than it is for the TC1301B.
For the TC1301A, the input voltage to the detector is
pin 8 (VDET). For the TC1301B, the input voltage to the
detector is internally connected to the output of LDO #1
(VOUT1). The detected voltage is sensed and compared
to an internal threshold. When the voltage on the VDET
pin is below the threshold voltage, the RESET output
pin is low. When the voltage on the VDET pin rises
above the voltage threshold, the RESET output will
remain low for typically 300 ms (RESET time-out
period). After the RESET time-out period, the RESET
output voltage will transition from the low output state
to the high output state if the detected voltage pin
remains above the threshold voltage.
VIN
ts
twk
SHDN2
VOUT1
The RESET output will be driven low within 180 µs of
VDET going below the RESET voltage threshold. The
RESET output will remain valid for detected voltages
greater than 1.2V overtemperature.
VOUT2
5.13 TC1301A RESET Timing
Figure 5-3 shows the RESET timing waveforms for the
TC1301A. This diagram is also used to define the
RESET active time-out period (tRPU) and the VDET
RESET delay time (tRPD).
FIGURE 5-1:
TC1301A Timing.
5.11 TC1301B SHDN1 / SHDN2 Timing
For the TC1301B, the SHDN1 input pin is used to
control VOUT1. The SHDN2 input pin is used to control
VOUT2, independent of the logic input on SHDN1.
VTH
VDET
RESET Time
VIN
TRPD
VOH
ts
twk
RESET
SHDN1
VOUT1
VOL
1V
FIGURE 5-3:
TC1301A RESET Timing.
SHDN2
VOUT2
FIGURE 5-2:
TC1301B Timing.
© 2005 Microchip Technology Inc.
DS21798B-page 15
TC1301A/B
5.15.2
OVERTEMPERATURE
PROTECTION
5.14 TC1301B RESET Timing
The timing waveforms for the TC1301B RESET output
are shown in Figure 5-4. Note that the RESET
threshold input for the TC1301B is VOUT1. The VOUT1
to RESET threshold detector connection is made
internal in the case of the TC1301B.
If the internal power dissipation within the TC1301A/B
is excessive due to a faulted load or higher-than-
specified line voltage, an internal temperature-sensing
element will prevent the junction temperature from
exceeding approximately 150°C. If the junction
temperature does reach 150°C, both outputs will be
disabled until the junction temperature cools to
approximately 140°C. The device will resume normal
operation. If the internal power dissipation continues to
be excessive, the device will again shut off. The VDET
and RESET circuit will continue to operate normally
during an overtemperature fault condition for both the
TC1301A and TC1301B.
VIN
VTH
VOUT1
RESET Time
TRPD
VOH
RESET
VOL
1V
FIGURE 5-4:
TC1301B RESET Timing.
5.15 Device Protection
5.15.1 OVERCURRENT LIMIT
In the event of a faulted output load, the maximum
current the LDO output will permit to flow is limited
internally for each of the TC1301A/B outputs. The peak
current limit for VOUT1 is typically 1.1A, while the peak
current limit for VOUT2 is typically 0.5A. During short-
circuit operation, the average current is limited to
200 mA for VOUT1 and 140 mA for VOUT2.The VDET
and RESET circuit will continue to operate in the event
of an overcurrent on either output for the TC1301A.
The voltage detect and RESET circuit will continue to
operate in the event of an overcurrent on VOUT1 (or
VOUT2) for the TC1301B. In the event of an overcurrent
on VOUT1, the RESET will detect the absence of VOUT1
.
DS21798B-page 16
© 2005 Microchip Technology Inc.
TC1301A/B
EQUATION 6-1:
PLDO = (VIN(MAX)) – VOUT(MIN)) × IOUT(MAX))
6.0
6.1
APPLICATION CIRCUITS/
ISSUES
PLDO
= LDO Pass device internal power
dissipation
Typical Application
The TC1301A/B is used for applications that require
the integration of two LDO’s and a microcontroller
RESET.
VIN(MAX) = Maximum input voltage
VOUT(MIN)= LDO minimum output voltage
In addition to the LDO pass element power dissipation,
there is power dissipation within the TC1301A/B as a
result of quiescent or ground current. The power
dissipation as a result of the ground current can be
calculated using the following equation. The VIN pin
quiescent current and the VDET pin current are both
considered. The VIN current is a result of LDO
quiescent current, while the VDET current is a result of
the voltage detector current.
TC1301A
8
7
6
1
2
3
V
System RESET
2.8V @ 300 mA
DET
RESET
BATTERY
V
V
IN
OUT1
1.8V
@ 150 mA
C
C
OUT1
IN
V
1 µF
GND
OUT2
1 µF Ceramic
X5R
4
5
2.7V
to
4.2V
SHDN2
Bypass
C
OUT2
C
bypass
1 µF Ceramic
X5R
10 nF Ceramic
ON/OFF Control V
OUT2
EQUATION 6-2:
PI(GND) = VIN(MAX) × (IVIN + IVDET
)
ON/OFF Control V
8
OUT1
TC1301B
PI(GND) = Total current in ground pin.
IN(MAX) = Maximum input voltage.
1
SHDN1
System RESET
2.8V @ 300 mA
RESET
V
IVIN
BATTERY
2
3
4
7
6
V
V
IN
OUT2
OUT1
1.8V
@ 150 mA
= Current flowing in the VIN pin with no
output current on either LDO output.
= Current in the VDET pin with
RESET loaded.
C
C
OUT1
IN
V
1 µF
GND
1 µF Ceramic
X5R
5
IVDET
SHDN2
2.7V
to
4.2V
Bypass
C
OUT2
1 µF Ceramic
X5R
ON/OFF Control V
OUT2
The total power dissipated within the TC1301A/B is the
sum of the power dissipated in both of the LDO’s and
the P(IGND) term. Because of the CMOS construction,
the typical IGND for the TC1301A/B is 116 µA.
Operating at a maximum of 4.2V results in a power
dissipation of 0.5 milliWatts. For most applications, this
is small compared to the LDO pass device power
dissipation and can be neglected.
FIGURE 6-1:
TC1301A/B.
Typical Application Circuit
6.1.1
APPLICATION INPUT CONDITIONS
Package Type = 3X3DFN8
Input Voltage Range = 2.7V to 4.2V
VIN maximum = 4.2V
The maximum continuous operating junction
temperature specified for the TC1301A/B is 125°C. To
estimate the internal junction temperature of the
TC1301A/B, the total internal power dissipation is
multiplied by the thermal resistance from junction to
ambient (RθJA) of the device. The thermal resistance
from junction to ambient for the 3X3DFN8 pin package
is estimated at 41° C/W.
VIN typical = 3.6V
VOUT1 = 300 mA maximum
VOUT2 = 150 mA maximum
System RESET Load = 10 kΩ
6.2
6.2.1
Power Calculations
EQUATION 6-3:
POWER DISSIPATION
TJ(MAX) = PTOTAL × RθJA + TAMAX
The internal power dissipation within the TC1301A/B is
a function of input voltage, output voltage, output
current and quiescent current. The following equation
can be used to calculate the internal power dissipation
for each LDO.
TJ(MAX) = Maximum continuous junction
temperature.
PTOTAL = Total device power dissipation.
RθJA
= Thermal resistance from junction-to-
ambient.
TAMAX = Maximum ambient temperature.
© 2005 Microchip Technology Inc.
DS21798B-page 17
TC1301A/B
The maximum power dissipation capability for a
package can be calculated given the junction to
ambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package maximum
internal power dissipation.
Maximum Ambient Temperature
TA(MAX) = 50°C
Internal Power Dissipation
Internal power dissipation is the sum of the power
dissipation for each LDO pass device.
PLDO1(MAX) = (VIN(MAX) - VOUT1(MIN)) x
IOUT1(MAX)
EQUATION 6-4:
(TJ(MAX) – TA(MAX)
)
PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA
---------------------------------------------------
=
PD(MAX)
RθJA
PLDO1 = 441.0 milliWatts
PD(MAX) = Maximum device power dissipation.
TJ(MAX) = Maximum continuous junction
temperature.
PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA
PLDO2 = 366.8 milliWatts
PTOTAL = PLDO1 + PLDO2
TA(MAX) = Maximum ambient temperature.
RθJA
= Thermal resistance from junction-to-
ambient.
PTOTAL= 807.8 milliWatts
Device Junction Temperature Rise
EQUATION 6-5:
TJ(RISE) = PD(MAX) × RθJA
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (RθJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7, “High
Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method To Determine
How Much Power a SOT32 Can Dissapate in Your
Application” (DS00792), for more information regarding
this subject.
TJ(RISE) = Rise in device junction temperature
over the ambient temperature.
PD(MAX)= Maximum device power dissipation.
RθJA = Thermal resistance from junction-to-
ambient.
EQUATION 6-6:
TJ = TJ(RISE) + TA
TJ
= Junction Temperature.
TJ(RISE)= Rise in device junction temperature
over the ambient temperature.
TA
= Ambient Temperature.
TJ(RISE) = PTOTAL x RqJA
TJRISE = 807.8 milliWatts x 41.0° C/W
TJRISE = 33.1°C
6.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
6.3.1
POWER DISSIPATION EXAMPLE
Package
TJ = TJRISE + TA(MAX)
TJ = 83.1°C
Package Type 3X3DFN8
=
Maximum Package Power Dissipation at 50°C
Ambient Temperature
Input Voltage
VIN = 2.7V to 4.2V
3X3DFN8 (41° C/W RθJA
)
LDO Output Voltages and Currents
PD(MAX) = (125°C - 50°C) / 41° C/W
PD(MAX) = 1.83 Watts
V
OUT1 = 2.8V
IOUT1 = 300 mA
VOUT2 = 1.8V
MSOP8 (208° C/W RθJA
)
PD(MAX) = (125°C - 50°C) / 208° C/W
PD(MAX) = 0.360 Watts
I
OUT2 = 150 mA
DS21798B-page 18
© 2005 Microchip Technology Inc.
TC1301A/B
7.0
TYPICAL LAYOUT TC1301A
FIGURE 7-4:
DFN3X3 Top Metal Layer
Example.
FIGURE 7-1:
MSOP8 Silk Screen Layer.
Vias represent the connection to a ground plane that is
below the wiring layer.
When doing the physical layout for the TC1301A/B, the
highest priority is placing the input and output
capacitors as close to the device pins as is practical.
Figure 7-1 above represents a typical placement of the
components when using SMT0805 capacitors.
8.0
ADDITIONAL OUTPUT
VOLTAGE AND THRESHOLD
VOLTAGE OPTIONS
8.1
Output Voltage and Threshold
Voltage Range
Table 8-1 describes the range of output voltage options
available for the TC1301A/B. VOUT1 and VOUT2 can be
factory preset from 1.5V to 3.3V in 100 mV increments.
The VDET (TC1301A) or threshold voltage (TC1301B)
can be preset from 2.2V to 3.2V in 10 mV increments.
FIGURE 7-2:
MSOP8 Wiring Layer.
TABLE 8-1:
CUSTOM OUTPUT VOLTAGE
AND THRESHOLD VOLTAGE
RANGES
A wiring example for the TC1301A is shown. The vias
represent the connection to a ground plane that is
below the wiring layer.
VOUT1
VOUT2
VDET Threshold
1.5V to 3.3V
1.5V to 3.3V
2.2V to 3.2V
For a listing of TC1301A/B standard parts, refer to the
Product Identification System on page 23.
FIGURE 7-3:
DFN3X3 Silk-Screen
Example.
8-lead 3X3 DFN physical layout example with bypass
capacitor.
© 2005 Microchip Technology Inc.
DS21798B-page 19
TC1301A/B
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP
Example:
8-Lead DFN
Example:
— 31A = TC1301A
— F = 2.8V VOUT1
— H = 2.6V VOUT2
— A = 2.63V Reset
XXXX
YYWW
NNN
AFHA
0435
256
XXXXXX
YWWNNN
31AFHA
435256
X1 represents VOUT1 configuration:
Code VOUT1 Code VOUT1 Code VOUT1
Xr represents the reset voltage range:
Code
Voltage
Code
Voltage
A
B
C
D
E
F
G
H
I
3.3V
3.2V
3.1V
3.0V
2.9V
2.8V
2.7V
2.6V
2.5V
J
K
L
2.4V
2.3V
2.2V
2.1V
2.0V
1.9V
1.8V
1.7V
1.6V
S
T
1.5V
1.65V
2.85V
2.65V
1.85V
—
A
B
C
D
E
F
G
H
I
2.63V
2.2V
2.32V
2.5V
2.4V
2.6V
—
J
K
L
—
—
—
—
—
—
—
—
—
U
V
W
X
Y
Z
M
N
O
P
Q
R
M
N
O
P
Q
R
—
—
—
—
X2 represents VOUT2 configuration:
Code VOUT2 Code VOUT1 Code VOUT2
For a listing of TC1301A/B standard parts, refer to the
Product Identification System on page 23.
A
B
C
D
E
F
G
H
I
3.3V
3.2V
3.1V
3.0V
2.9V
2.8V
2.7V
2.6V
2.5V
J
K
L
2.4V
2.3V
2.2V
2.1V
2.0V
1.9V
1.8V
1.7V
1.6V
S
T
1.5V
1.65V
2.85V
2.65V
1.85V
—
U
V
W
X
Y
Z
M
N
O
P
Q
R
—
—
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21798B-page 20
© 2005 Microchip Technology Inc.
TC1301A/B
8-Lead Plastic Micro Small Outline Package (UA) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
8
MILLIMETERS*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
Molded Package Thickness
Standoff
.030
.033
.037
0.75
0.00
0.85
0.95
0.15
.000
-
.006
-
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
3.00 BSC
.118 BSC
3.00 BSC
L
.016
.024
.031
0.40
0.60
0.80
Footprint (Reference)
Foot Angle
F
.037 REF
0.95 REF
φ
c
0°
.003
.009
5°
-
.006
.012
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
5°
-
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2005 Microchip Technology Inc.
DS21798B-page 21
TC1301A/B
8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN)
D
p
b
n
L
n
E
E2
EXPOSED
METAL
2
1
PIN 1
ID INDEX
AREA
PAD
D2
BOTTOM VIEW
TOP VIEW
(NOTE 2)
A
A1
A3
EXPOSED
TIE BAR
(NOTE 1)
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
n
Number of Pins
Pitch
8
8
p
A
.026 BSC
.035
0.65 BSC
0.90
Overall Height
Standoff
.031
.000
.039
0.80
1.00
A1
A3
E
.001
.002
0.00
0.02
0.05
Contact Thickness
Overall Length
Exposed Pad Width
Overall Width
Exposed Pad Length
Contact Width
Contact Length
.008 REF.
.118 BSC
.059
0.20 REF.
3.00 BSC
1.49
(Note 3)
E2
D
.053
.063
1.34
1.59
.118 BSC
.069
3.00 BSC
1.75
(Note 3)
D2
b
.063
.008
.012
.073
.015
.022
1.60
0.20
0.30
1.85
0.37
0.55
.010
0.26
L
.019
0.48
*Controlling Parameter
Notes:
1. Package may have one or more exposed tie bars at ends.
2. Pin 1 visual index feature may vary, but must be located within the hatched area.
3. Exposed pad dimensions vary with paddle size.
4. JEDEC equivalent: MO-229
Drawing No. C04-062
Revised 05/24/04
DS21798B-page 22
© 2005 Microchip Technology Inc.
TC1301A/B
APPENDIX A: REVISION HISTORY
Revision B (January 2005)
The following is the list of modifications:
1. Correct the incorrect part number options shown
on the Product Identification System page and
change the “standard” output voltage and reset
voltage combinations.
2. Added Appendix A: Revision History.
Revision A (September 2003)
Original data sheet release.
© 2005 Microchip Technology Inc.
DS21798B-page 23
TC1301A/B
NOTES:
DS21798B-page 24
© 2005 Microchip Technology Inc.
TC1301A/B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
TC1301
X-
X
X
X
X
XX
XX
a)
TC1301A-ADAVUA:
3.3, 3.0, 2.63,
MSOP pkg.
Type
A/B
V
V
Reset
Voltage
Temp Package
Range
Tube
or
Tape &
Reel
OUT1
OUT2
b)
c)
TC1301A-APAVMFTR:
3.3 , 1.8, 2.63,
8LD DFN pkg.
Tape and Reel
3.0, 2.8 , 2.63,
MSOP pkg.
Standard
Configurations
TC1301A-DFAVUATR:
Tape and Reel
3.0, 1.8 , 2.63,
8LD DFN pkg.
2.8, 3.0, 2.63,
8LD DFN pkg.
2.8, 2.6, 2.63,
DFN pkg.
1.8, 2.8, 2.32,
MSOP pkg.
1.5, 2.8, 2.32,
DFN pkg.
d)
e)
f)
TC1301A-DPAVMF:
TC1301A-FDAVMF:
TC1301A-FHAVMF:
TC1301A-PFCVUA:
TC1301A-SFCVMFTR:
Device:
TC1301A: Dual LDO with microcontroller RESET function
and single shutdown input.
TC1301B: Dual LDO with microcontroller RESET function
and dual shutdown inputs.
g)
h)
Standard
Configurations: *
VOUT1/VOUT2/Reset
Configuration
Code
TC1301A
3.3 / 3.0 / 2.63
3.3 / 1.8 / 2.63
3.0 / 2.8 / 2.63
3.0 / 1.8 / 2.63
2.8 / 3.0 / 2.63
2.8 / 2.6 / 2.63
1.8 / 2.8 / 2.32
1.5 / 2.8 / 2.32
2.85 / 1.85 / 2.63
ADA
APA
DFA
DPA
FDA
FHA
PFC
SFC
UWA
Tape and Reel
2.85, 1.85, 2.63,
MSOP pkg.
i)
TC1301A-UWAVUATR:
Tape and Reel
a)
b)
TC1301B-ADAVMF:
3.3, 3.0, 2.63,
8LD DFN pkg.
TC1301B-APAVMFTR:
3.3, 1.8, 2.63,
8LD DFN pkg.
Tape and Reel
3.0, 2.8, 2.63,
MSOP pkg.
TC1301B
3.3 / 3.0 / 2.63
3.3 / 1.8 / 2.63
3.0 / 2.8 / 2.63
3.0 / 1.8 / 2.63
2.8 / 3.0 / 2.63
2.8 / 2.6 / 2.63
2.7 / 2.8 / 2.5
ADA
APA
DFA
DPA
FDA
FHA
GFD
GDD
UWA
c)
d)
TC1301B-DFAVUA:
TC1301B-DPAVUATR:
3.0, 1.8 ,2.63,
MSOP pkg.
Tape and Reel
2.8 ,3.0, 2.63,
8LD DFN pkg.
2.8, 2.6 ,2.63,
8LD DFN pkg.
Tape and Reel
2.7, 3.0, 2.50,
MSOP pkg.
2.7, 2.8, 2.5,
8LD DFN pkg.
2.85, 1.85, 2.63,
MSOP pkg.
2.7 / 3.0 / 2.50
2.85 / 1.85 / 2.63
e)
f)
TC1301B-FDAVMF:
TC1301B-FHAVMFTR:
* Contact Factory for Alternate Output Voltage and Reset
Voltage Configurations.
g)
h)
i)
TC1301B-GDDVUA:
TC1301B-GFDVMF:
TC1301B-UWAVUATR:
Temperature Range:
Package:
V
= -40°C to +125°C
MF
UA
=
=
Dual Flat, No Lead (3x3 mm body), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
Tape and Reel
Tube or
Tape and Reel:
Blank
TR
=
=
Tube
Tape and Reel
© 2005 Microchip Technology Inc.
DS21798B-page 25
TC1301A/B
NOTES:
DS21798B-page 26
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21798B-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
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Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
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Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
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Tel: 86-28-8676-6200
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10/20/04
DS21798B-page 28
© 2004 Microchip Technology Inc.
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