TC514CPJ中文资料_数据手册_规格书

TC500/A/510/514

Precision Analog Front Ends

Features

Package Types

• Precision (up to 17-bits) A/D Converter "Front End"

• 3-Pin Control Interface to Microprocessor

16-Pin SOIC

16 Pin-PDIP

• Flexible: User Can Trade-off Conversion Speed

for Resolution

V

C

1

16

15

14

13

12

11

10

9

DD

INT

V

2

3

4

5

6

7

8

DGND

SS

• Single Supply Operation (TC510/TC514)

• 4 Input, Differential Analog MUX (TC514)

• Automatic Input Voltage Polarity Detection

• Low Power Dissipation:

TC500/

TC500A

COE

C

CMPTR OUT

AZ

BUF

B

A

ACOM

TC500/

TC500A

CPE

C

–

+

V

+

–

REF

IN

- (TC500/TC500A): 10mΩ

- (TC510/TC514): 18mΩ

• Wide Analog Input Range: ±4.2V (TC500A/TC510)

REF

V

+

REF

• Directly Accepts Bipolar and Differential

Input Signals

24-Pin SOIC

24-Pin PDIP

V

-

1

24

CAP-

OUT

Applications

C

23

22

21

20

19

18

17

16

15

14

13

2

3

INT

DGND

CAP+

• Precision Analog Signal Processor

• Precision Sensor Interface

C

AZ

BUF

4

V

DD

• High Accuracy DC Measurements

ACOM

5

OSC

C

-

6

TC510COG

TC510CPF

CMPTR OUT

REF

Device Selection Table

C

+

7

A

B

REF

8

V

+

Part

Number

Temperature

Range

Package

9

V

-

V

+

-

REF

IN

10

11

12

N/C

IN

TC500ACOE

16-Pin SOIC (Wide)

0°C to +70°C

N/C

TC500ACPE 16-Pin PDIP (Narrow)

TC500COE

TC500CPE

TC510COG

TC510CPF

TC514COI

TC514CPJ

16-Pin SOIC (Wide)

16-Pin PDIP (Narrow)

24-Pin SOIC (Wide)

24-Pin PDIP (Narrow)

28-Pin SOIC (Wide)

28-Pin PDIP (Narrow)

28-Pin SOIC

28-Pin PDIP

V

-

1

2

3

4

5

6

28 CAP-

OUT

C

27

26

25

24

23

22

21

20

19

18

DGND

CAP+

INT

C

AZ

V

BUF

DD

ACOM

OSC

C

-

CMPTR OUT

REF

C

REF

+

-

7

8

A

TC514COI

TC514CPJ

V

B

REF

V

+

9

A0

A1

CH1+

REF

10

11

12

13

14

CH4-

CH3-

17

16

CH2-

CH1-

CH2+

CH3+

15 CH4+

N/C

2002 Microchip Technology Inc.

DS21428B-page 1

TC500/A/510/514

offset voltages in the TC5XX are corrected by a closed

loop feedback mechanism. The input voltage is applied

to the integrator during the Integrate phase. This

causes an integrator output dv/dt directly proportional

to the magnitude of the input voltage. The higher the

input voltage, the greater the magnitude of the voltage

stored on the integrator during this phase. At the start

of the De-integrate phase, an external voltage refer-

ence is applied to the integrator and, at the same time,

the external host processor starts its on-board timer.

The processor maintains this state until a transition

occurs on the CMPTR output, at which time the proces-

sor halts its timer. The resulting timer count is the con-

verted analog data. Integrator Zero (the final phase of

conversion) removes any residue remaining in the

integrator in preparation for the next conversion.

General Description

TheTC500/A/510/514 family are precision analog front

ends that implement dual slope A/D converters having

a maximum resolution of 17-bits plus sign. As a mini-

mum, each device contains the integrator, zero cross-

ing comparator and processor interface logic. The

TC500 is the base (16-bit max) device and requires

both positive and negative power supplies. The

TC500A is identical to the TC500 with the exception

that it has improved linearity, allowing it to operate to a

maximum resolution of 17-bits. The TC510 adds an on-

board negative power supply converter for single sup-

ply operation. The TC514 adds both a negative power

supply converter and a 4 input differential analog

multiplexer.

Each device has the same processor control interface

consisting of 3 wires: control inputs (A and B) and zero-

crossing comparator output (CMPTR). The processor

manipulates A, B to sequence the TC5XX through four

phases of conversion: Auto Zero, Integrate, De-inte-

grate and Integrator Zero. During the Auto Zero phase,

The TC500/A/510/514 offer high resolution (up to 17-

bits), superior 50Hz/60Hz noise rejection, low power

operation, minimum I/O connections, low input bias

currents and lower cost compared to other converter

technologies having similar conversion speeds.

Typical Application

Control Logic

A

0

B

0

Converter Sate

Zero Integrator Output

C

R

INT

C

REF

0

1

0

1

Auto-Zero

Signal Integrate

Deintegrate

C

AZ

V

REF

-

V

REF

+

A1

A0

C

REF

-

C

INT

C

AZ

C

REF

+

BUF

TC500

Buffer

-

SW SW

R

Integrator

TC500A

TC510

TC514

CH1+

CH2+

CH3+

CH4+

CH1-

CH2-

CH3-

CH4-

SW

CMPTR 1

+

I

–

DIF.

CMPTR 2

–

+

MUX

(TC514)

SW -

RI

+

SW

-

RI

Level

Shift

CMPTR

Output

–

+

SW

Z

SW

IZ

SW

Z

Polarity

Detection

SW

RI

+

SW

-

RI

ACOM

SW

1

SW

I

Analog

Phase

Decoding

Logic

DGND

Switch

Control

Signals

V

SS

DC-TO-DC

Converter

(TC510 & TC514)

OSC

V

-

OUT

CAP+

CAP-

1.0µF

V

SS

A

B

1.0µF

(TC500

TC500A)

Control Logic

C

-

OUT

DS21428B-page 2

2002 Microchip Technology Inc.

TC500/A/510/514

*Stresses above those listed under "Absolute Maxi-

mum Ratings" may cause permanent damage to the

device. These are stress ratings only and functional

operation of the device at these or any other conditions

above those indicated in the operation sections of the

specifications is not implied. Exposure to Absolute

Maximum Rating conditions for extended periods may

affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

TC510/TC514 Positive Supply Voltage

(V to GND) .........................................+10.5V

DD

TC500/TC500A Supply Voltage

(V to V ) ..............................................+18V

DD

SS

TC500/TC500A Positive Supply Voltage

(V to GND) ............................................+12V

DD

TC500/TC500A Negative Supply Voltage

(V to GND)................................................-8V

SS

Analog Input Voltage (V + or V -) ............V to V

SS

IN

DD

Logic Input Voltage...............V +0.3V to GND - 0.3V

DD

Voltage on OSC:

........................... -0.3V to (V +0.3V) for V < 5.5V

DD

Ambient Operating Temperature Range:

................................................................ 0°C to +70°C

Storage Temperature Range:............. -65°C to +150°C

TC500/A/510/514 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: TC510/TC514: V = +5V, TC500/TC500A: V = ±5V unless otherwise specified.

DD

SS

C

= C

= 0.47µF.

AZ

REF

T_A= +25°C

T_A= 0°C to 70°C

Symbol

Analog

Parameter

Unit

Test Conditions

Min

Typ

Max

Min

Typ

Max

Resolution

60

—

µV

Note 1

ZSE

ENL

Zero Scale Error

with Auto Zero Phase

—

0.005

0.003

—

0.005

0.003

0.012

0.009

% F.S. TC500/510/514

TC500A

End Point Linearity

—

0.005

—

0.015

0.010

—

0.015

0.010

0.060

0.045

% F.S. TC500/510/514,

% F.S. Note 1, Note 2,

TC500A

NL

Best Case Straight

Line Linearity

—

0.003

0.008

—

% F.S. TC500/510/514,

Note 1, Note 2

—

0.005

—

1

—

2

% F.S. TC500A

ZS_TC

SYE

Zero-Scale Temp.

Coefficient

—

µV/°C Over Operating

Temperature Range

Full-Scale Symmetry

Error (Roll-Over Error)

—

0.01

—

0.03

10

—

% F.S. Note 3

FS_TC

Full-Scale Tempera-

ture Coefficient

ppm/°C Over Operating

Temperature Range;

External Reference

TC = 0 ppm/°C

I_IN

Input Current

—

6

—

pA

V_IN= 0V

Note 1: Integrate time ≥ 66msec, auto zero time ≥ 66msec, V_INT(peak) ≈ 4V.

2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.

3: Roll-over error is related to C_INT, C_REF, C_AZcharacteristics.

2002 Microchip Technology Inc.

DS21428B-page 3

TC500/A/510/514

TC500/A/510/514 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: TC510/TC514: V = +5V, TC500/TC500A: V = ±5V unless otherwise specified.

DD

SS

C

= C

= 0.47µF.

AZ

REF

T_A= +25°C

T_A= 0°C to 70°C

Symbol

Parameter

Unit

Test Conditions

Min

Typ

Max

Min

Typ

Max

Analog (Continued)

V_CMRCommon Mode

V_SS+1.5

V_SS+0.9

V_SS+1.5

V_SS+1

—

V_DD– 1.5 V_SS+ 1.5

V_DD– 0.9 V_SS+0.9

V_DD– 1.5 V_SS+1.5

—

V_DD– 1.5

V_SS+0.9

V_SS+1.5

V_DD– 1

V

Voltage Range

Integrator Output

Swing

Analog Input Signal-

Range

ACOM = GND = 0V

V_REF

Voltage Reference

Range

V_DD– 1

V_SS+1

V_REF- V_REF+

Digital

V_OH

Comparator Logic 1,

Output High

4

—

0.4

—

1

4

—

0.4

—

1

V

I_SOURCE= 400µA

V_OL

V_IH

V_IL

Comparator Logic 0,

Output Low

—

3.5

—

3.5

—

I_SINK= 2.1mA

Logic 1, Input High

Voltage

Logic 0, Input Low

Voltage

I_L

Logic Input Current

Comparator Delay

—

2

—

0.3

3

µA

Logic 1 or 0

t_D

—

µsec

Multiplexer (TC514 Only)

Maximum Input

Voltage

-2.5

—

2.5

10

-2.5

—

2.5

—

V

V_DD= 5V

R_DSONDrain/Source ON

Resistance

6

kΩ

Power (TC510/TC514 Only)

I_S

Supply Current

—

1.8

18

—

2.4

—

3.5

—

mA

mW

V

V_DD= 5V, A = 1, B = 1

V_DD= 5V

P_D

V_DD

Power Dissipation

Positive Supply Oper-

ating Voltage Range

4.5

5.5

4.5

5.5

R_OUT

Operating Source

Resistance

—

60

85

—

100

Ω

I_OUT= 10mA

Oscillator Frequency

Maximum Current Out

—

100

—

kHz

mA

(Note 3)

I_OUT

-10

V_DD= 5V

Power (TC500/TC500A Only)

I_S

Supply Current

—

1

1.5

—

2.5

—

mA

mW

V

V_S= ±5V, A = B = 1

V_DD= 5V, V_SS= -5V

P_D

V_DD

Power Dissipation

10

—

Positive Supply Oper-

ating Range

4.5

7.5

4.5

7.5

V_SS

Negative Supply

Operating Range

-4.5

—

-7.5

- 4.5

—

-7.5

V

Note 1: Integrate time ≥ 66msec, auto zero time ≥ 66msec, V_INT(peak) ≈ 4V.

2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.

3: Roll-over error is related to C_INT, C_REF, C_AZcharacteristics.

DS21428B-page 4

2002 Microchip Technology Inc.

TC500/A/510/514

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

(TC500,

Number Number Symbol

Description

TC500A)

(TC510) (TC514)

1

2

3

4

5

2

C_INT

V_SS

C_AZ

BUF

Integrator output. Integrator capacitor connection.

Not Used Not Used

Negative power supply input (TC500/TC500A only).

Auto Zero input. The Auto Zero capacitor connection.

Buffer output. The Integrator capacitor connection.

3

4

5

3

4

5

ACOM This pin is grounded in most applications. It is recommended that ACOM and the

input common pin (Ve_n- or CH_n-) be within the analog common mode range (CMR).

6

7

6

7

6

C_REF

V_REF

V_IN

-

Input. Negative reference capacitor connection.

Input. Positive reference capacitor connection.

Input. External voltage reference (-) connection.

Input. External voltage reference (+) connection.

Negative analog input.

7

+

8

-

9

Not Used

22

+

10

11

12

13

15

16

18

17

-

V_IN

A

+

Positive analog input.

Input. Converter phase control MSB. (See input B.)

21

B

Input. Converter phase control LSB. The states of A, B place the TC5XX in one of

four required phases. A conversion is complete when all four phases have been

executed:

Phase control input pins: AB = 00: Integrator Zero

01: Auto Zero

10: Integrate

11: De-integrate

14

19

23

CMPTR Zero crossing comparator output. CMPTR is HIGH during the Integration phase

OUT

when a positive input voltage is being integrated and is LOW when a negative input

voltage is being integrated. A HIGH-to-LOW transition on CMPTR signals the pro-

cessor that the De-integrate phase is completed. CMPTR is undefined during the

Auto Zero phase. It should be monitored to time the Integrator Zero phase.

15

16

23

21

22

24

1

27

25

26

28

1

DGND Input. Digital ground.

V_DD

Input. Power supply positive connection.

CAP+ Input. Negative power supply converter capacitor (+) connection.

CAP- Input. Negative power supply converter capacitor (-) connection.

V_OUT

-

Output. Negative power supply converter output and reservoir capacitor connection.

This output can be used to power other devices in the circuit requiring a negative

bias voltage.

20

24

OSC

Oscillator control input. The negative power supply converter normally runs at a fre-

quency of 100kHz. The converter oscillator frequency can be slowed down

(to reduce quiescent current) by connecting an external capacitor between this pin

and V_DD(see Section 9.0, Typical Characteristics Curves).

18

13

17

12

16

11

15

10

20

19

CH1+ Positive analog input pin. MUX channel 1.

CH1- Negative analog input pin. MUX channel 1.

CH2+ Positive analog input pin. MUX channel 2.

CH2- Negative analog input pin. MUX channel 2.

CH3+ Positive analog input pin. MUX channel 3.

CH3- Negative analog input pin. MUX channel 3.

CH4+ Positive analog input pin. MUX channel 4.

CH4- Negative analog input pin. MUX channel 4

A0

A1

Multiplexer input channel select input LSB (see A1).

Multiplexer input channel select input MSB.

Phase control input pins: A1, A0 = 00 = Channel 1

01 = Channel 2

10 = Channel 3

11 = Channel 4

2002 Microchip Technology Inc.

DS21428B-page 5

TC500/A/510/514

the integration period are, theoretically, completely

removed, since the average value of a sine wave of

frequency (1/T) averaged over a period (T) is zero.

3.0

3.1

DETAILED DESCRIPTION

Dual Slope Conversion Principles

Integrating converters often establish the integration

period to reject 50/60Hz line frequency interference

signals. The ability to reject such signals is shown by a

normal mode rejection plot (Figure 3-1). Normal mode

rejection is limited in practice to 50 to 65dB, since the

line frequency can deviate by a few tenths of a percent

(Figure 3-2).

Actual data conversion is accomplished in two phases:

input signal Integration and reference voltage

De-integration.

The integrator output is initialized to 0V prior to the start

of Integration. During Integration, analog switch S1

connects V to the integrator input where it is main-

IN

tained for a fixed time period (T ). The application of

INT

V

causes the integrator output to depart 0V at a rate

IN

FIGURE 3-1:

INTEGRATING

CONVERTER NORMAL

MODE REJECTION

determined by the magnitude of V and a direction

determined by the polarity of V . The De-integration

phase is initiated immediately at the expiration of T

IN

.

INT

30

During De-integration, S1 connects a reference voltage

Measurment

T =

(having a polarity opposite that of V ) to the integrator

Period

IN

input. At the same time, an external precision timer is

started. The De-integration phase is maintained until

the comparator output changes state, indicating the

integrator has returned to its starting point of 0V. When

this occurs, the precision timer is stopped. The De-inte-

20

10

0

gration time period (T

), as measured by the preci-

DEINT

sion timer, is directly proportional to the magnitude of

the applied input voltage (see Figure 3-3).

A simple mathematical equation relates the Input Sig-

nal, Reference Voltage and Integration time:

0.1/T

1/T

10/T

Input Frequency

EQUATION 3-1:

FIGURE 3-2:

LINE FREQUENCY

DEVIATION

T

0

V

T

INT

1

REF DEINT

V

(T)DT =

IN

R

C

R

C

INT INT

80

70

60

50

40

Where:

= Reference Voltage

V

REF

t = 0.1 sec

T

= Signal Integration time (fixed)

INT

t

= Reference Voltage Integration time (variable)

DEINT

For a constant V

:

IN

DEV

SIN 60 p t (1

60 p t (1

)

EQUATION 3-2:

= V

100

Normal Mode = 20 LOG

REJECTION

DEV

)

30

20

100

T

DEINT

DEV = Deviation from 60Hz

t = Integration Period

V

IN

REF

T

INT

0.01

0.1

1.0

The dual slope converter accuracy is unrelated to the

integrating resistor and capacitor values as long as

they are stable during a measurement cycle.

Line Frequency Deviation from 60 Hz (%)

An inherent benefit is noise immunity. Input noise

spikes are integrated (averaged to zero) during the

integration periods. Integrating ADCs are immune to

the large conversion errors that plague successive

approximation converters in high noise environments.

Integrating converters provide inherent noise rejection

with at least a 20dB/decade attenuation rate. Interfer-

ence signals with frequencies at integral multiples of

DS21428B-page 6

2002 Microchip Technology Inc.

TC500/A/510/514

FIGURE 3-3:

BASIC DUAL SLOPE CONVERTER

C

INT

TC510

Integrator

R

INT

Analog

–

V

INT

Input (V

)

Comparator

IN

–

CMPTR Out

+

S1

Phase

Control

Switch Driver

Polarity Control

REF

VOLTAGE

Control

Logic

A

B

I/O

Microcomputer

V

SUPPLY

INT

V

≈ V

REF

IN

≈ 1/2 V

REF

Timer

Counter

ROM

RAM

T

DEINT

INT

2002 Microchip Technology Inc.

DS21428B-page 7

TC500/A/510/514

The internal analog switch status for each of these

phases is summarized in Table 4-1. This table

references the Typical Application.

4.0

TC500/A/510/514 CONVERTER

OPERATION

The TC500/A/510/514 incorporates an Auto Zero and

Integrator phase in addition to the input signal Integrate

and reference De-integrate phases. The addition of

these phases reduce system errors, calibration steps

and shorten overrange recovery time. A typical mea-

surement cycle uses all four phases in the following

order:

1. Auto Zero

2. Input signal integration

3. Reference deintegration

4. Integrator output zero

TABLE 4-1:

INTERNAL ANALOG GATE STATUS

Conversion Phase

SW

SW +

SW -

SW

IZ

I

R

Z

R

1

Auto Zero (A = 0, B = 1)

Closed

Input Signal Integration (A = 1, B = 0)

Closed

Reference Voltage De-integration

(A =1, B = 1)

Closed*

Closed

Integrator Output Zero (A = 0, B = 0)

Closed

Closed Closed

–

Note: *Assumes a positive polarity input signal. SW

would be closed for a negative input signal.

RI

4.1

Auto Zero Phase (AZ)

4.3

Reference Voltage De-integration

Phase (D_INT

)

During this phase, errors due to buffer, integrator and

comparator offset voltages are nulled out by charging

The previously charged reference capacitor is con-

nected with the proper polarity to ramp the integrator

output back to zero. An externally-provided, precision

timer is used to measure the duration of this phase.

The resulting time measurement is proportional to the

magnitude of the applied input voltage.

C

(auto zero capacitor) with a compensating error

AZ

voltage.

The external input signal is disconnected from the inter-

nal circuitry by opening the two SW switches. The

internal input points connect to analog common. The

reference capacitor is charged to the reference voltage

potential through SW . A feedback loop, closed around

I

4.4

Integrator Output Zero Phase (IZ)

R

the integrator and comparator, charges the C capac-

itor with a voltage to compensate for buffer amplifier,

integrator and comparator offset voltages.

AZ

This phase ensures the integrator output is at 0V when

the Auto Zero phase is entered and that only system

offset voltages are compensated. This phase is used at

the end of the reference voltage de-integration phase

and MUST be used for ALL TC5XX applications having

resolutions of 12-bits or more. If this phase is not used,

4.2

Analog Input Signal Integration

Phase (INT)

the value of the Auto Zero capacitor (C ) must be

about 2 to 3 times the value of the Integration capacitor

AZ

The TC5XX integrates the differential voltage between

the (V +) and (V –) inputs. The differential voltage

IN

(C ) to reduce the effects of charge sharing. The Inte-

INT

must be within the device's Common mode range

. The input signal polarity is normally checked via

grator Output Zero phase should be programmed to

operate until the output of the comparator returns

"HIGH". The overall timing system is shown in

Figure 4-1.

V

CMR

software at the end of this phase: CMPTR = 1 for

positive polarity; CMPTR = 0 for negative polarity.

DS21428B-page 8

2002 Microchip Technology Inc.

TC500/A/510/514

FIGURE 4-1:

TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING

T

TIME

Auto-Zero

Converter Status

Integrate

Full Scale Input

Reference

Overshoot Integrator

De-integrate

Output

Zero

Integrator

Voltage

0

V

INT

Comparator Delay

Undefined

0 For Negative Input

1 For Postive Input

Comparator

Output

A

A = 1

B = 1

A = 1

B = 0

A = 0

B = 1

A = 0

B = 0

AB Inputs

B

Ready for Next

Conversion

(Auto-Zero is

Idle State)

Capture

Begin Conversion with

Auto-Zero Phase

Time Input

Integration

Phase

Integrator

Controller

Operation

De-integration

Time

Output

Zero Phase

Complete

Sample Input Polarity

T

INT

Minimizing

Overshoot

will Minimize

I.O.Z. Time

Typically = T

INT

Comparator Delay +

Processor Latency

(Positive Input Shown)

Notes: The length of this phase is chosen almost arbitrarily

but needs to be long enough to null out worst case errors

(see text).

2002 Microchip Technology Inc.

DS21428B-page 9

TC500/A/510/514

The difference in reference for (+) or (-) input voltages

will cause a rollover error. This error can be minimized

by using a large reference capacitor in comparison to

the stray capacitance.

5.0

5.1

ANALOG SECTION

Differential Inputs (V_IN+, V_IN–)

The TC5XX operates with differential voltages within

the input amplifier Common mode range. The amplifier

Common mode range extends from 1.5V below posi-

tive supply to 1.5V above negative supply. Within this

Common mode voltage range, Common mode rejec-

tion is typically 80dB. Full accuracy is maintained, how-

ever, when the inputs are no less than 1.5V from either

supply.

5.4

Phase Control Inputs (A, B)

The A, B unlatched logic inputs select the TC5XX oper-

ating phase. The A, B inputs are normally driven by a

microprocessor I/O port or external logic.

5.5

Comparator Output

By monitoring the comparator output during the fixed

signal integrate time, the input signal polarity can be

determined by the microprocessor controlling the

conversion. The comparator output is HIGH for positive

signals and LOW for negative signals during the signal

integrate phase (see Figure 5-1).

The integrator output also follows the Common mode

voltage. The integrator output must not be allowed to

saturate. A worst case condition exists, for example,

when a large, positive Common mode voltage, with a

near full scale negative differential input voltage, is

applied. The negative input signal drives the integrator

positive when most of its swing has been used up by

the positive Common mode voltage. For these critical

applications, the integrator swing can be reduced. The

integrator output can swing within 0.9V of either supply

without loss of linearity.

During the reference de-integrate phase, the compara-

tor output will make a HIGH-to-LOW transition as the

integrator output ramp crosses zero. The transition is

used to signal the processor that the conversion is

complete.

The internal comparator delay is 2µsec, typically.

Figure 5-1 shows the comparator output for large

positive and negative signal inputs. For signal inputs at

or near zero volts, however, the integrator swing is very

small. If Common mode noise is present, the compara-

tor can switch several times during the beginning of the

signal integrate period. To ensure that the polarity

reading is correct, the comparator output should be

read and stored at the end of the signal integrate

phase.

5.2

Analog Common

Analog common is used as V return during system

zero and reference de-integrate. If V – is different from

analog common, a Common mode voltage exists in the

system. This signal is rejected by the excellent CMR of

the converter. In most applications, V – will be set at a

fixed known voltage (i.e., power supply common). A

Common mode voltage will exist when V – is not

connected to analog common.

IN

The comparator output is undefined during the Auto

Zero phase and is used to time the Integrator Output

Zero phase. (See Section 7.6, Integrator Output Zero

Phase).

5.3

Differential Reference

(V_REF+, V_REF–)

The reference voltage can be anywhere within 1V of

the power supply voltage of the converter. Rollover

error is caused by the reference capacitor losing or

gaining charge due to stray capacitance on its nodes.

FIGURE 5-1:

COMPARATOR OUTPUT

Signal

Integrate

Reference

Signal

Reference

Deintegrate

Integrate

De-integrate

Integrator

Output

Zero

Crossing

Integrator

Output

Zero

Crossing

Comparator

Output

Comparator

Output

A. Positive Input Signal

B. Negative Input Signal

DS21428B-page 10

2002 Microchip Technology Inc.

TC500/A/510/514

TABLE 6-1:

C

AND C SELECTION

AZ

6.0

6.1

TYPICAL APPLICATIONS

Component Value Selection

REF

Conversions Typical Value of

Per Second

Suggested* Part

Number

C

_REF, C_AZ(µF)

The procedure outlined below allows the user to arrive

at values for the following TC5XX design variables:

>7

0.1

SMR5 104K50J01L4

SMR5 224K50J02L4

SMR5 474K50J04L4

2 to 7

0.22

0.47

1. Integration Phase Timing

2 or less

2. Integrator Timing Components (R , C

)

INT INT

Note:

Manufactured by Evox-Rifa, Inc.

3. Auto Zero and Reference Capacitors

4. Voltage Reference

6.6

Calculate Integrating Capacitor

(C_INT

)

6.2

Select Integration Time

The integrating capacitor must be selected to maximize

integrator output voltage swing. The integrator output

Integration time must be picked as a multiple of the

period of the line frequency. For example, T times of

33msec, 66msec and 132msec maximize 60Hz line

rejection.

INT

voltage swing is defined as the absolute value of V

DD

(or V ) less 0.9V (i.e., IV - 0.9VI or IV + 0.9VI).

SS

DD

SS

Using the 20µA buffer maximum output current, the

value of the integrating capacitor is calculated using the

following equation.

6.3

DINT and IZ Phase Timing

The duration of the DINT phase is a function of the

amount of voltage stored on the integrator during T

EQUATION 6-2:

INT

and the value of V

. The DINT phase must be initi-

-6

REF

(T ) (20 x 10

)

INT

ated immediately following INT and terminated when

an integrator output zero-crossing is detected. In gen-

eral, the maximum number of counts chosen for DINT

µF

C

=

INT

(V - 0.9)

S

Where:

is twice that of INT (with V

chosen at V

/2).

REF

IN(MAX)

T

= Integration Period

INT

6.4

Calculate Integrating Resistor

(R_INT

V

= IV I or IV I, whichever is less (TC500/A

DD SS

S

)

= IV I (TC510, TC514)

DD

The desired full scale input voltage and amplifier output

It is critical that the integrating capacitor has a very low

dielectric absorption. Polypropylene capacitors are an

example of one such dielectic. Polyester and Polybicar-

bonate capacitors may also be used in less critical

applications. Table 6-2 summarizes recommended

current capability determine the value of R . The

INT

buffer and integrator amplifiers each have a full-scale

current of 20µA.

The value of R

is therefore directly calculated in the

INT

following equation:

capacitors for C

.

INT

EQUATION 6-1:

TABLE 6-2:

RECOMMENDED CAPACITOR

FOR C

V

INT

IN(MAX)

R

(in MΩ) =

INT

20

Value

Suggested Part Number*

0.1

SMR5 104K50J01L4

SMR5 224K50J02L4

SMR5 334K50J03L4

SMR5 474K50J04L4

Where:

0.22

0.33

0.47

V

= Maximum input voltage (full count voltage)

IN(MAX)

R

= Integrating Resistor (in MΩ)

INT

For loop stability, R

should be ≥ 50kΩ.

INT

Note:

Manufactured by Evox-Rifa, Inc.

6.5

Select Reference (C_REF) and Auto

Zero (C_AZ) Capacitors

6.7

Calculate V_REF

The reference deintegration voltage is calculated using

the following equation:

C

and C must be low leakage capacitors (such as

REF

AZ

polypropylene). The slower the conversion rate, the

larger the value C must be. Recommended capac-

REF

EQUATION 6-3:

itors for C

and C are shown in Table 6-1. Larger

REF

AZ

(V – 0.9) (C ) (R )

INT

S

INT

values for C

rollover errors.

and C

may also be used to limit

REF

AZ

V

=

V

REF

2(R

)

INT

2002 Microchip Technology Inc.

DS21428B-page 11

TC500/A/510/514

7.4

Input Signal Integrate Phase

7.0

7.1

DESIGN CONSIDERATIONS

Noise

The length of this phase is constant from one conver-

sion to the next and depends on system parameters

and component value selections. The calculation of

The threshold noise (N ) is the algebraic sum of the

TH

T

is shown elsewhere in this data sheet. At some

integrator noise and the comparator noise. This value

is typically 30µV. Figure 7-1 shows how the value of the

reference voltage can affect the final count. Such errors

can be reduced by increased integration times, in the

same way that 50/60Hz noise is rejected. The signal-

INT

point near the end of this phase, the microcontroller

should sample CMPTR to determine the input signal

polarity. This value is, in effect, the Sign Bit for the over-

all conversion result. Optimally, CMPTR should be

sampled just before this phase is terminated by chang-

ing AB from 10 to 11. The consideration here is that,

during the initial stage of input integration when the

integrator voltage is low, the comparator may be

affected by noise and its output unreliable. Once inte-

gration is well underway, the comparator will be in a

defined state.

to-noise ratio is related to the integration time (T

)

INT

and the integration time constant (R

lows:

(C ) as fol-

INT)

INT

EQUATION 7-1:

V

t

INT

IN

•

S/N (dB) = 20 Log

(

–

6

)

30 x 10

(R ) • (C

)

INT

7.5

Reference De-integration

7.2

System Timing

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling

edge of CMPTR. The comparator delay contributes

some error in timing this phase. The typical delay is

specified to be 2µsec. This should be considered in the

To obtain maximum performance from the TC5XX, the

overshoot at the end of the De-integration phase must

be minimized. Also, the Integrator Output Zero phase

must be terminated as soon as the comparator output

returns high. (See Figure 4-1).

context of the length of

a single count when

determining overall system performance and possible

single count errors. Additionally, Overshoot will result in

charge accumulating on the integrator after its output

crosses zero. This charge must be nulled during the

Integrator Output Zero phase.

Figure 4-1 shows the overall timing for a typical system

in which a TC5XX is interfaced to a microcontroller. The

microcontroller drives the A, B inputs with I/O lines and

monitors the comparator output, CMPTR, using an I/O

line or dedicated timer capture control pin. It may be

necessary to monitor the state of the CMPTR output in

addition to having it control a timer directly for the Ref-

erence De-integration phase. (This is further explained

below.)

The timing diagram in Figure 4-1 is not to scale, as the

timing in a real system depends on many system

parameters and component value selections. There

are four critical timing events (as shown in Figure 4-1):

sampling the input polarity; capturing the de-integration

time; minimizing overshoot and properly executing the

Integrator Output Zero phase.

7.3

Auto Zero Phase

The length of this phase is usually set to be equal to the

Input Signal Integration time. This decision is virtually

arbitrary since the magnitudes of the various system

errors are not known. Setting the Auto Zero time equal

to the Input Integrate time should be more than

adequate to null out system errors. The system may

remain in this phase indefinitely (i.e., Auto Zero is the

appropriate Idle state for a TC5XX device).

DS21428B-page 12

2002 Microchip Technology Inc.

TC500/A/510/514

FIGURE 7-1:

NOISE THRESHOLD

S

30 µV

N

TH

N

TH

N

TH

High V

REF

Normal V

REF

Low

REF

V

Slope (S) =

N

= Noise Threshold

TH

R

C

INT INT

7.6

Integrator Output Zero Phase

7.7

Using the TC510/TC514

The comparator delay and the controller's response

latency may result in overshoot, causing charge

buildup on the integrator at the end of a conversion.

This charge must be removed or performance will

degrade. The Integrator Output Zero phase should be

activated (AB = 00) until CMPTR goes high. It is abso-

lutely critical that this phase be terminated immediately

so that Overshoot is not allowed to occur in the oppo-

site direction. At this point, it can be assured that the

integrator is near zero. Auto Zero should be entered

(AB = 01) and the TC5XX held in this state until the next

cycle is begun (see Figure 7-2).

7.7.1

NEGATIVE SUPPLY VOLTAGE

CONVERTER (TC510, TC514)

A capacitive charge pump is employed to invert the volt-

age on V for negative bias within the TC510/TC514.

This voltage is also available on the V

negative bias elsewhere in the system. Two external

capacitors are required to perform the conversion.

DD

- pin to provide

OUT

Timing is generated by an internal state machine driven

from an on-board oscillator. During the first phase,

capacitor C is switched across the power supply and

F

charged to V +. This charge is transferred to capacitor

S

C

- during the second phase. The oscillator normally

OUT

FIGURE 7-2:

OVERSHOOT

runs at 100kHz to ensure minimum output ripple. This

frequency can be reduced by placing a capacitor from

OSC to V . The relationship between the capacitor

value is shown in Section 9.0.

DD

Integrator

Output

Zero

Crossing

7.7.2

ANALOG INPUT MULTIPLEXER

(TC514)

The TC514 is equipped with a four input differential

analog multiplexer. Input channels are selected using

select inputs (A1, A0). These are high-true control sig-

nals (i.e., channel 0 is selected when (A1, A0 = 00).

Overshoot

Comparator

Output Comp

De-integrate Phase

Integrator

Zero Phase

Integrate

Phase

2002 Microchip Technology Inc.

DS21428B-page 13

TC500/A/510/514

8.0

DESIGN EXAMPLE

(SEE FIGURES 8-1 TO 8-4)

Given: Required Resolution: (16 Bits (65,536

counts).

Maximum V : ±2V

IN

Power Supply Voltage: +5V

60Hz System

Step 1: Pick integration time (t ) as a multiple of the

INT

line frequency:

1/60Hz = 16.6msec. Use 4x line frequency

= 66msec

Step 2: Calculate R

INT

R

= V

/20µA 2 /20µA = 100kΩ

INT

IN(MAX)

Step 3: Calculate C

for maximum (4V) integrator

INT

output swing:

–6

C

= (t ) (20 x 10 ) / (V - 0.9)

INT S

INT

–6

= (.066) (20 x 10 ) / (4.1)

= .32µF (use closest value: 0.33µF)

Note: Microchip recommended capacitor:

Evox-Rifa p/n: 5MR5 334K50J03L4.

Step 4: Choose C

and C based on conversion

AZ

REF

rate:

Conversions/sec:

= 1/(T + T

+ 2 T + 2msec)

INT

AZ

INT

= 1/(66msec +66msec

+132msec +2msec)

= 3.7 conversions/sec

From which C = C

(see Table 6-1)

= 0.22µF

REF

AZ

Note: Microchip recommended capacitor:

Evox-Rifa p/n: 5MR5 224K50J02L4

Step 5: Calculate V

REF

EQUATION 8-1:

(V - 0.9) (C ) (R

)

S

INT

V

=

REF

2(T

)

INT

–6

5

= (4.1) (0.33 x 1 ) (10 ) / 2(.066)

= 1.025V

DS21428B-page 14

2002 Microchip Technology Inc.

TC500/A/510/514

FIGURE 8-1:

TC510 DESIGN SAMPLE

1

24

23

CAP-

V

-

OUT

C

INT

0.33µF

1µF

Typical Waveforms

+5V

2

1µF

DGND

C

INT

C

AZ

0.22µF

Pin 2

TC510

3

22

21

CAP+

C

AZ

V

+

IN

4

V

DD

+5V

BUF

R

INT

100k

Pin 19

5

6

ACOM

Microcontroller

19

MCP1525

CMPTR

C

-

REF

C

REF

0.22µF

R2

Pin 2

18

17

10k

7

9

8

C

V

+

A

B

V

-

IN

1µF

R3, 10k

Pin 19

-

REF

C1

16

15

V

REF

+

V

IN

+

INPUT+

0.01µF

V

-

IN

INPUT–

FIGURE 8-2:

TC514 DESIGN EXAMPLE

1

28

27

V

-

CAP-

OUT

C

INT

0.33µF

1µF

2

1µF

DGND

C

+

5V

INT

C

AZ

0.22µF

26

25

3

4

CAP+

AZ

V

+5V

TC514

DD

+5V

BUF

R

100k

INT

22

19

23

A0

5

6

Analog

Mux Logic

ACOM

Microcontroller

A1

MCP1525

C

-

CMPTR

REF

C

REF

0.22µF

10k

22

21

7

9

8

A

B

+

REF

1µF

V

+

REF

C1, .01µF

18

13

CH1+

INPUT 1+

-

CH1–

INPUT 1–

Typical Waveforms

17

12

CH2+

INPUT 2+

PIN 2

–

CH2

INPUT 2–

V

IN

+

16

11

CH3

INPUT 3+

PIN 23

–

CH3

INPUT 3–

+

15

10

CH4

INPUT4+

PIN 2

IN

–

CH4

INPUT4–

V

PIN 23

2002 Microchip Technology Inc.

DS21428B-page 15

TC500/A/510/514

®

FIGURE 8-3:

TC510 TO IBM COMPATIBLE PRINTER PORT

+5V

21

1

1µF

V

-

DD

OUT

24

CAP-

1µF

22

7

CAP+

C

+

REF

0.22µF

0.01µF

10k

6

9

C

-

REF

MCP1525

1µF

V

+

REF

TC510

8

V

-

REF

100kΩ

PC

Printer

Port

4

BUF

0.22µF

18

17

3

2

A

B

C

AZ

PORT

0378

HEX

0.33µF

100kΩ

3

2

C

V

INT

+

10

19

16

+

CMPTR

IN

0.01µF

Input

15

5

V

-

IN

–

ACOM

DGND

23

DS21428B-page 16

2002 Microchip Technology Inc.

TC500/A/510/514

FIGURE 8-4:

TC514 TO IBM COMPATIBLE PRINTER PORT

+5V

25

1

1µF

28

26

+

18

13

17

–

V

CH1+

V

OUT

DD

CAP–

Input 1

–

1µF

CH1–

10kΩ

CAP+

+

CH2+

Input 2

–

7

6

12

16

11

C

+

MCP1525

REF

CH2–

CH3+

CH3–

0.22µF

+

C

-

10k

Input 3

–

9

8

15

10

V

+

REF

+

CH4+

10k

Input 4

–

0.01µF

CH4–

TC514

V

-

REF

20

A0

A1

Analog

Mux Control Logic

19

22

21

100kΩ

0.22µF

4

3

2

IBM

Printer Port

2

BUF

A

B

C

AZ

Port

0378

0.33µF

3

INT

Hex

10

23

CMPTR

5

ACOM

DGND

27

2002 Microchip Technology Inc.

DS21428B-page 17

TC500/A/510/514

9.0

TYPICAL CHARACTERISTICS

The graphs and tables following this note are a statistical summary based on a limited number of samples and are

provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed.

In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified

power supply range), and therefore outside the warranted range.

Output Voltage vs. Output Current

Output Voltage vs Load Current

= 25 C

-0

-1

-2

-3

-4

5

4

T

= 25 C

T

A

˚

V+ = 5V

3

2

1

0

-1

-2

-3

-4

-5

-6

Slope 60Ω

-7

-8

0

2

4

6

8

10 12 14 16 18 20

0

10

20

30

40

60

70

80

50

Load Current (mA)

Output Current (mA)

Output Source Resistance vs. Temperature

Output Ripple vs. Load Current

200

100

90

V+ = 5V

I = 10mA

OUT

V+ = 5V, T = 25˚C

A

175

150

125

100

75

Osc. Freq. = 100kHz

80

CAP = 1µF

70

60

CAP = 10µF

50

25

40

0

1

2

3

4

5

6

7

8

9

10

-50

0

25

50

75

100

-25

Temperature ( C)

Load Current (mA)

˚

Oscillator Frequency vs. Capacitance

= +25˚C

Oscillator Frequency vs. Temperature

100

10

1

150

125

V+ = 5V

T

A

V+ = 5V

100

75

50

1

10

Oscillator Capacitance (pF)

-25

0

25

Temperature (˚C)

-50

75

100 125

100

1000

50

DS21428B-page 18

2002 Microchip Technology Inc.

TC500/A/510/514

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

Package marking data not available at this time.

10.2 Taping Forms

Component Taping Orientation for 16-Pin SOIC (Wide) Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation

for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

Reel Size

16-Pin SOIC (W)

16 mm

12 mm

1000

13 in

Component Taping Orientation for 24-Pin SOIC (Wide) Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation

for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

Reel Size

24-Pin SOIC (W)

24 mm

12 mm

1000

13 in

2002 Microchip Technology Inc.

DS21428B-page 19

TC500/A/510/514

10.2 Taping Forms (Continued)

Component Taping Orientation for 28-Pin SOIC (Wide) Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation

for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package

Carrier Width (W)

Pitch (P)

Part Per Full Reel

1000

Reel Size

28-Pin SOIC (W)

24 mm

12 mm

13 in

DS21428B-page 20

2002 Microchip Technology Inc.

TC500/A/510/514

10.3 Package Dimensions

16-Pin PDIP (Narrow)

PIN 1

.270 (6.86)

.240 (6.10)

.045 (1.14)

.030 (0.76)

.770 (19.56)

.740 (18.80)

.310 (7.87)

.290 (7.37)

.200 (5.08)

.140 (3.56)

.040 (1.02)

.020 (0.51)

.014 (0.36)

.008 (0.20)

10° MAX.

.150 (3.81)

.115 (2.92)

.400 (10.16)

.310 (7.87)

.110 (2.79)

.090 (2.29)

.070 (1.78)

.045 (1.14)

.022 (0.56)

.015 (0.38)

Dimensions: inches (mm)

16-Pin SOIC (Narrow)

PIN 1

.157 (3.99)

.150 (3.81)

.244 (6.20)

.228 (5.79)

.050 (1.27) TYP

.394 (10.00)

.385 (9.78)

.069 (1.75)

.053 (1.35)

8°

MAX.

.010 (0.25)

.007 (0.18)

.010 (0.25)

.004 (0.10)

.050 (1.27)

.016 (0.40)

.018 (0.46)

.014 (0.36)

Dimensions: inches (mm)

2002 Microchip Technology Inc.

DS21428B-page 21

TC500/A/510/514

10.3 Packaging Dimensions (Continued)

16-Pin SOIC (Wide)

PIN 1

.299 (7.59) .419 (10.65)

.291 (7.40) .398 (10.10)

.413 (10.49)

.398 (10.10)

.104 (2.64)

.097 (2.46)

8°

MAX.

.013 (0.33)

.009 (0.23)

.012 (0.30)

.019 (0.48)

.014 (0.36)

.004 (0.10)

.050 (1.27) TYP.

.050 (1.27)

.016 (0.40)

Dimensions: inches (mm)

24-Pin PDIP (Narrow)

PIN 1

.280 (7.11)

.240 (6.10)

.045 (1.14)

.030 (0.76)

.310 (7.87)

.290 (7.37)

1.195 (30.35)

1.155 (29.34)

.200 (5.08)

.140 (3.56)

.040 (1.02)

.015 (0.38)

.008 (0.20)

3˚ MIN.

.150 (3.81)

.115 (2.92)

.400 (10.16)

.310 (7.87)

.110 (2.79)

.090 (2.29)

.070 (1.78)

.045 (1.14)

.023 (0.58)

.015 (0.38)

Dimensions: inches (mm)

DS21428B-page 22

2002 Microchip Technology Inc.

TC500/A/510/514

10.3 Packaging Dimensions (Continued)

24-Pin SOIC (Wide)

PIN 1

.299 (7.59) .419 (10.65)

.291 (7.40) .398 (10.10)

.615 (15.62)

.597 (15.16)

.104 (2.64)

.097 (2.46)

8°

MAX.

.013 (0.33)

.009 (0.23)

.012 (0.30)

.004 (0.10)

.019 (0.48)

.014 (0.36)

.050 (1.27) TYP.

.050 (1.27)

.016 (0.40)

Dimensions: inches (mm)

PIN 1

28-Pin PDIP (Narrow)

.288 (7.32)

.240 (6.10)

.045 (1.14)

.030 (0.76)

.310 (7.87)

.290 (7.37)

1.400 (35.56)

1.345 (34.16)

.200 (5.08)

.140 (3.56)

.040 (1.02)

.015 (0.38)

.008 (0.20)

3˚ MIN.

.150 (3.81)

.115 (2.92)

.400 (10.16)

.310 (7.87)

.022 (0.56)

.015 (0.38)

.110 (2.79)

.090 (2.29)

.070 (1.78)

.045 (1.14)

Dimensions: inches (mm)

2002 Microchip Technology Inc.

DS21428B-page 23

TC500/A/510/514

10.3 Package Dimensions (Continued)

28-Pin SOIC (Wide)

PIN 1

.299 (7.59)

.291 (7.40)

.419 (10.65)

.398 (10.10)

.713 (18.11)

.697 (17.70)

.103 (2.62)

.097 (2.46)

.013 (0.33)

.009 (0.23)

8˚ MAX.

.012 (0.30)

.004 (0.10)

.019 (0.48)

.014 (0.36)

.050 (1.27)

.016 (0.40)

Dimensions: inches (mm)

DS21428B-page 24

2002 Microchip Technology Inc.

TC500/A/510/514

SALES AND SUPPORT

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2002 Microchip Technology Inc.

DS21428B-page 25

TC500/A/510/514

NOTES:

DS21428B-page 26

 2002 Microchip Technology Inc.

TC500/A/510/514

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

2002 Microchip Technology Inc.

DS21428B-page 27

WORLDWIDE SALES AND SERVICE

Japan

AMERICAS

ASIA/PACIFIC

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Corporate Office

Australia

2355 West Chandler Blvd.

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson Street

Epping 2121, NSW

Chandler, AZ 85224-6199

Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

Korea

Rocky Mountain

China - Beijing

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966 Fax: 480-792-7456

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

Bei Hai Wan Tai Bldg.

Atlanta

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770-640-0034 Fax: 770-640-0307

Boston

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848 Fax: 978-692-3821

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

China - Chengdu

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Singapore, 188980

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Microchip Technology Taiwan

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

Chicago

333 Pierce Road, Suite 180

Itasca, IL 60143

Chengdu 610016, China

Tel: 86-28-86766200 Fax: 86-28-86766599

Tel: 630-285-0071 Fax: 630-285-0075

China - Fuzhou

Dallas

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

4570 Westgrove Drive, Suite 160

Addison, TX 75001

EUROPE

Denmark

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

Tel: 972-818-7423 Fax: 972-818-2924

Detroit

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Tel: 86-591-7503506 Fax: 86-591-7503521

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Room 701, Bldg. B

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

Kokomo

France

2767 S. Albright Road

Kokomo, Indiana 46902

Tel: 765-864-8360 Fax: 765-864-8387

Los Angeles

Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microchip Technology GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949-263-1888 Fax: 949-263-1338

China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

New York

150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631-273-5305 Fax: 631-273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950 Fax: 408-436-7955

Toronto

China - Hong Kong SAR

Italy

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699 Fax: 905-673-6509

India

Tel: 39-039-65791-1 Fax: 39-039-6899883

Microchip Technology Inc.

India Liaison Office

United Kingdom

Microchip Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

04/20/02

DS21428B-page 28

2002 Microchip Technology Inc.

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP, DIP28,.3	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	9 weeks
风险等级：	1.4	Is Samacsys：	N
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	R-PDIP-T28
JESD-609代码：	e3	长度：	34.67 mm
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP28,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	4.06 mm	子类别：	Other Analog ICs
最大供电电流 (Isup)：	3.5 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	Base Number Matches：	1

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