TC7106CPLIJL [MICROCHIP]
ADC, Dual-Slope, 1 Func, 1 Channel, PDIP40, CERDIP-40;
| 型号： | TC7106CPLIJL |
| 厂家： | 
MICROCHIP |
| 描述： | ADC, Dual-Slope, 1 Func, 1 Channel, PDIP40, CERDIP-40 光电二极管 转换器 |
| 文件： | 总21页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC7106
TC7106A
TC7107
TC7107A
3-1/2 DIGIT A/D CONVERTERS
FEATURES
GENERAL DESCRIPTION
■ Internal Reference with Low Temperature Drift
TC7106/7 ....................................... 80ppm/°C Typical
TC7106A/7A.................................. 20ppm/°C Typical
■ Drives LCD (TC7106) or LED (TC7107) Display
Directly
■ Guaranteed Zero Reading With Zero Input
■ Low Noise for Stable Display
The TC7106A and TC7107A 3-1/2 digit direct-display
drive analog-to-digital converters allow existing 7106/7107
based systems to be upgraded. Each device has a preci-
sion reference with a 20ppm/°C max temperature coeffi-
cient. This represents a 4 to 7 times improvement over
similar 3-1/2 digit converters. Existing 7106 and 7107 based
systems may be upgraded without changing external pas-
sive component values. The TC7107A drives common
anode light emitting diode (LED) displays directly with 8mA
per segment. A low-cost, high-resolution indicating meter
requires only a display, four resistors, and four capacitors.
The TC7106A low power drain and 9V battery operation
make it suitable for portable applications.
The TC7106A/TC7107A reduces linearity error to less
than 1 count. Rollover error – the difference in readings for
equal magnitude but opposite polarity input signals – is
below ±1 count. High impedance differential inputs offer
1pA leakage current and a 1012Ω input impedance. The
differential reference input allows ratiometric measurements
for ohms or bridge transducer measurements. The
15µVP–P noise performance guarantees a “rock solid” read-
ing. The auto-zero cycle guarantees a zero display read-
ing with a zero-volts input.
■ Auto-Zero Cycle Eliminates Need for Zero
Adjustment
■ True Polarity Indication for Precision Null
Applications
■ Convenient 9 V Battery Operation (TC7106A)
■ High Impedance CMOS Differential Inputs.... 1012Ω
■ Differential Reference Inputs Simplify Ratiometric
Measurements
■ Low Power Operation ..................................... 10mW
ORDERING INFORMATION
PART CODE
TC710X X X XXX
6 = LCD
7 = LED
}
A or blank*
R (reversed pins) or blank (CPL pkg only)
* "A" parts have an improved reference TC
Package Code (see below):
0.1µF
LCD DISPLAY (TC7106/A) OR
COMMON ANODE LED
DISPLAY (TC7107/A)
33
–
C
REF
34
+
C
REF
1MΩ
Package
Code
Temperature
Range
31
SEGMENT
DRIVE
+
2–19
+
V
IN
22–25
ANALOG
INPUT
–
Package
Pin Layout
0.01µF
20
–
30
32
POL
BP
V
IN
MINUS SIGN
BACKPLANE
DRIVE
CKW
CLW
CPL
IPL
44-Pin PQFP
44-Pin PLCC
40-Pin PDIP
40-Pin PDIP
40-Pin CerDIP
Formed Leads
—
0°C to +70°C
0°C to +70°C
21
1
ANALOG
COMMON
+
V
Normal
Normal
Normal
0°C to +70°C
24kΩ
1kΩ
28
TC7106/A
TC7107/A
+
V
BUFF
– 25°C to +85°C
– 25°C to +85°C
9V
V
47kΩ
+
REF
36
V
0.47µF
29
REF
IJL
C
V
AZ
–
35 100mV
26
V
REF
0.22µF
27
–
V
INT
AVAILABLE PACKAGES
OSC OSC OSC
2
3
1
TO ANALOG
COMMON (PIN 32)
C
39
38
40
OSC
R
100pF
3 CONVERSIONS/SEC
200mV FULL SCALE
OSC
100kΩ
40-Pin CERDIP
40-Pin Plastic DIP
Figure 1. TC7106/A/7/A Typical Operating Circuit
44-Pin Plastic Quad Flat
Package Formed Leads
44-Pin Plastic Chip
Carrier PLCC
TC7106/6A/7/7A-7 11/4/96
TelCom Semiconductor reserves the right to make changes in the circuitryand specifications to its devices.
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
ABSOLUTE MAXIMUM RATINGS*
Clock Input ....................................................... GND to V+
Power Dissipation (Note 2) (TA ≤ 70°C)
40-Pin CerDIP Package ...................................2.29W
40-Pin Plastic DIP.............................................1.23W
44-Pin PLCC.....................................................1.23W
44-Pin PQFP ....................................................1.00W
Operating Temperature
“C” Devices ............................................ 0°C to +70°C
“I” Devices ........................................– 25°C to +85°C
Storage Temperature ............................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
TC7106A
Supply Voltage (V+ to V–) ...........................................15 V
Analog Input Voltage (either input) (Note 1)......... V+ to V–
Reference Input Voltage (either input) ................. V+ to V–
Clock Input ........................................................ Test to V+
Package Power Dissipation (Note 2) (TA ≤ 70°C)
CerDIP ..............................................................2.29W
Plastic DIP ........................................................1.23W
PLCC ................................................................1.23W
PQFP ................................................................1.00W
Operating Temperature
“C” Devices ............................................ 0°C to +70°C
“I” Devices ........................................– 25°C to +85°C
Storage Temperature ............................ – 65°C to +150°C
Lead Temperature (Soldering, 60 sec) ................... 300°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
TC7107A
Supply Voltage
V+ ................................................................................................ +6 V
V– ............................................................................................... – 9 V
Analog Input Voltage (either input) (Note 1)......... V+ to V–
Reference Input Voltage (either input) ................. V+ to V–
ELECTRICAL CHARACTERISTICS (Note 3)
TC7106/A & TC7107/A
Parameters
Test Conditions
Min
Typ
Max
Unit
Zero Input Reading
VIN = 0.0 V
– 000.0
±000.0
+000.0
Digital
Full-Scale = 200.0mV
Reading
Ratiometric Reading
VIN = VREF
VREF = 100 mV
VI–N = +VI+N 200mV
999
– 1
999/1000
1000
+1
Digital
Reading
Roll-Over Error (Difference in
Reading for Equal Positive and
Negative Reading Near Full-Scale)
±0.2
Counts
Linearity (Max. Deviation From
Best Straight Line Fit)
Full-Scale = 200mV
or Full-Scale = 2.000 V
– 1
—
—
—
±0.2
50
15
1
+1
—
—
10
Counts
µV/V
µV
Common-Mode
Rejection Ratio (Note 4)
VCM = ±1V, VIN = 0V,
Full Scale = 200.0 mV
Noise (Pk – Pk Value Not
Exceeded 95% of Time)
VIN = 0 V
Full-Scale = 200.0mV
Leakage Current @ Input
Zero Reading Drift
VIN = 0 V
pA
VIN = 0 V
“C” Device = 0°C to +70°C
—
—
0.2
1.0
1
2
µV/°C
µV/°C
V
IN = 0 V
“I” Device = – 25°C to +85°C
IN = 199.0mV,
Scale Factor
V
Temperature Coefficient
“C” Device = 0°C to +70°C
(Ext. Ref = 0ppm°C)
—
—
1
5
ppm/°C
ppm/°C
V
IN = 199.0mV
—
20
“I” Device = – 25°C to +85°C
Supply Current (Does Not
VIN = 0
—
0.8
1.8
mA
Include LED Current For TC7107/A)
2
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
ELECTRICAL CHARACTERISTICS (Cont.) (Note 3)
TC7106/A & TC7107/A
Parameters
Test Conditions
Min
Typ
Max
Unit
Analog Common Voltage
25kΩ Between Common
2.7
3.05
3.35
V
(With Respect to Pos. Supply)
and Pos. Supply
Temp. Coeff. of
Analog Common
(With Respect
to Pos. Supply)
25kΩ Between Common
and Pos. Supply
0°C ≤ TA ≤ +70°C
7106A/7A
7106/7
20
80
50
—
ppm/°C
ppm/°C
("C", Commercial Temp. Range Devices)
Temp. Coeff. of
Analog Common
(With Respect
to Pos. Supply)
25kΩ Between Common
and Pos. Supply
– 25°C ≤ TA ≤ 85°C
(“I,” Industrial Temp. Range Devices)
V+ to V– = 9V
—
4
—
5
75
6
ppm/°C
V
TC7106A ONLY Pk – Pk
Segment Drive Voltage (Note 5)
TC7106A ONLY Pk – Pk
V+ to V– = 9V
4
5
6
V
Backplane Drive Voltage (Note 5)
TC7107A ONLY
V+ = 5.0V
5
8.0
16
—
—
mA
mA
Segment Sinking Current (Except Pin 19)
Segment Voltage = 3V
V+ = 5.0V
TC7107A ONLY
10
Segment Sinking Current (Pin 19)
Segment Voltage = 3V
NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at TA = 25°C, fCLOCK = 48 kHz. Parts are tested in the
circuit of Figure 1.
4. Refer to “Differential Input” discussion.
5. Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
3
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN CONFIGURATIONS
+
+
OSC
OSC
OSC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
D
C
OSC
OSC
OSC
V
D
C
1
2
1
2
1
2
3
NORMAL PIN
CONFIGURATION
REVERSE PIN
CONFIGURATION
1
1
1
1
1
1
1
1
1
1
3
3
3
TEST
B
A
F
B
A
F
4
TEST
4
+
+
V
5
5
1's
V
1's
REF
REF
–
–
V
6
6
V
REF
REF
+
+
C
G
G
1
C
7
7
1
REF
REF
–
–
C
E
E
C
8
8
1
1
REF
REF
ANALOG
ANALOG
9
9
D
C
B
A
F
D
C
B
A
F
2
2
2
2
2
2
2
2
2
2
2
2
COMMON
COMMON
+
+
V
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
V
IN
IN
–
–
TC7106ACPL
TC7107AIPL
TC7106AIJL
TC7107AIJL
V
V
IN
IN
10's
10's
C
C
V
AZ
AZ
V
BUFF
BUFF
V
E
E
V
INT
INT
–
–
D
B
V
G
C
A
G
V
D
B
3
3
3
3
G
2
2
3
3
3
100's
100's
C
3
F
E
F
E
3
3
4
3
3
100's
100's
A
3
3
G
AB
AB
4
1000's
1000's
BP/GND 20
(7106A/7107A)
POL
(MINUS SIGN)
POL
(MINUS SIGN)
BP/GND
(7106A/7107A)
6
5
4
3
2
1
44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
7
8
REF LO
1
2
NC
F
G
E
D
C
39
38
37
NC
NC
33
32
31
30
29
28
27
1
1
1
2
2
C
G
2
REF
9
C
TEST
3
C
3
REF
10
11
OSC
3
4
A
3
36 COMMON
IN HI
NC
NC
5
G
3
35
34
33
NC 12
OSC
2
6
BP/GND
POL
TC7106ACLW
TC7107ACLW
(PLCC)
TC7106ACKW
TC7107ACKW
(FLAT PACKAGE)
B
A
F
13
14
15
16
17
IN LO
OSC
1
7
2
2
2
2
3
+
32 A/Z
V
8
26 AB
4
31 BUFF
D
1
9
25
24
23
E
F
3
E
D
30 INT
–
C
1
10
11
3
29
V
B
1
B
3
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
4
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN DESCRIPTION
(Pin No.
(Pin No.
40-Pin PDIP 40-Pin PDIP
(Normal))
(Reverse))
Symbol
Description
1
2
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
V+
D1
C1
B1
Positive supply voltage.
Activates the D section of the units display.
Activates the C section of the units display.
Activates the B section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the B section of the tens display.
Activates the A section of the tens display.
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the D section of the hundreds display.
Activates the B section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
3
4
5
A1
6
F1
7
G1
E1
8
9
D2
C2
B2
10
11
12
13
14
15
16
17
18
19
20
21
A2
F2
E2
D3
B3
F3
E3
AB4
POL
BP
GND
LCD Backplane drive output (TC7106A).
Digital ground (TC7107A).
22
23
24
25
26
27
(19)
(18)
(17)
(16)
(15)
(14)
G3
A3
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
C3
G2
V–
VINT
Integrator output. Connection point for integration capacitor. See
INTEGRATING CAPACITOR section for more details
28
29
(13)
(12)
VBUFF
CAZ
Integration resistor connection. Use a 47kΩ resistor for a 200mV full-
scale range and a 470kΩ resistor for 2V full-scale range.
The size of the auto-zero capacitor influences system noise. Use a
0.47µF capacitor for 200mV full scale, and a 0.047µF capacitor for
2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more
details.
30
31
32
(11)
(10)
(9)
V–IN
V+IN
The analog LOW input is connected to this pin.
The analog HIGH input signal is connected to this pin.
ANALOG
COMMON
This pin is primarily used to set the analog common-mode voltage
for battery operation or in systems where the input signal is
referenced to the power supply. It also acts as a reference voltage
source. See paragraph on ANALOG COMMON for more details.
33
(8)
C–REF
See pin 34.
5
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN DESCRIPTION (Cont.)
(Pin No.
(Pin No.
40-Pin PDIP 40-Pin PDIP
(Normal)
(Reverse)
Symbol
Description
34
(7)
C+REF
A 0.1µF capacitor is used in most applications. If a large common-
mode voltage exists (for example, the V–IN pin is not at analog
common), and a 200mV scale is used, a 1µF capacitor is recom-
mended and will hold the roll-over error to 0.5 count.
35
36
(6)
(5)
VR–EF
V+REF
See pin 36.
The analog input required to generate a full-scale output (1999
counts). Place 100mV between pins 35 and 36 for 199.9mV
full-scale. Place 1V between pins 35 and 36 for 2V full scale. See
paragraph on REFERENCE VOLTAGE.
37
(4)
Test
Lamp test. When pulled HIGH (to V+) all segments will be turned on
and the display should read –1888. It may also be used as a negative
supply for externally-generated decimal points. See paragraph under
TEST for additional information.
38
39
40
(3)
(2)
(1)
OSC3
OSC2
OSC1
See pin 40.
See pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock
(3 readings per section), connect pin 40 to the junction of a 100kΩ
resistor and a 100pF capacitor. The 100kΩ resistor is tied to pin 39
and the 100pF capacitor is tied to pin 38.
General Theory of Operation
where:
Dual Slope Conversion Principles
VR = Reference Voltage
TSI = Signal Integration Time (Fixed)
TRI = Reference Voltage Integration Time (Variable)
(All Pin Designations Refer to the 40-Pin DIP)
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the dual
slope conversion technique will aid in following the detailed
operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
For a constant VIN:
TRI
VIN = VR
TSI
C
ANALOG
INPUT
•
•
Input Signal Integration
Reference Voltage Integration (Deintegration)
INTEGRATOR
SIGNAL
COMPARATOR
–
–
+
The input signal being converted is integrated for a fixed
+
time period (TSI). Time is measured by counting clock
pulses. An opposite polarity constant reference voltage is
then integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional
to the input signal (TRI). (Figure 2A).
+/–
SWITCH
DRIVER
CLOCK
PHASE
REF
VOLTAGE
CONTROL
LOGIC
CONTROL
POLARITY CONTROL
In a simple dual slope converter a complete conversion
requires the integrator output to “ramp-up” and “ramp-
down.”
Asimplemathematicalequationrelatestheinputsignal,
reference voltage and integration time:
COUNTER
DISPLAY
V
V
≈
≈
V
IN
IN
FULL SCALE
1/2 V
FULL SCALE
FIXED VARIABLE
SIGNAL REFERENCE
INTEGRATE INTEGRATE
TIME TIME
TSI
VRTRI
RC
1
RC
VIN(t)dt =
∫
0
Figure 2A. Basic Dual Slope Converter
6
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50/60Hz power line period. (Figure 2B)
Signal Integrate Cycle
When the auto-zero loop is opened, the internal differ-
ential inputs connect to VI+N and VI–N. The differential input
signal is integrated for a fixed time period. The signal
integration period is 1000 counts. The externally set clock
frequency is divided by four before clocking the internal
counters. The integration time period is:
4
TSI =
x 1000
fOSC
where:
fOSC = External Clock Frequency
30
20
10
The differential input voltage must be within the device
common-mode range (1V of either supply) when the con-
verter and measured system share the same power supply
common(ground). Iftheconverterandmeasuredsystemdo
not share the same power supply common, VI–N should be
tied to analog common.
Polarity is determined at the end of the signal integrate
phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection, limited only by device noise and
auto-zero residual offsets.
T = MEASUREMENT PERIOD
0
0.1/T
1/T
10/T
Reference Integrate Cycle
INPUT FREQUENCY
The final phase is reference integrate or de-integrate.
VI–N is internally connected to analog common and VI+N is
connected across the previously charged reference capaci-
tor. Circuitrywithinthechipensuresthatthecapacitorwillbe
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between0and2000counts.Thedigitalreadingdisplayedis:
Figure 2B. Normal-Mode Rejection of Dual Slope Converter
ANALOG SECTION
In addition to the basic signal integrate and deintegrate
cycles discussed, the circuit incorporates an auto-zero
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external
potentiometers. A complete conversion consists of three
cycles: an auto-zero, signal-integrate and reference-inte-
grate cycle.
VIN
1000 x
VREF
DIGITAL SECTION (TC7106A)
Auto-Zero Cycle
The TC7106A (Figure 3) contains all the segment driv-
ers necessary to directly drive a 3-1/2 digit liquid crystal
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane fre-
quency is 60Hz with a 5V nominal amplitude. When a
segment driver is in phase with the backplane signal the
segment is “OFF.” An out of phase segment drive signal
causes the segment to be “ON” or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment. This insures long LCD display life. The
polarity segment driver is “ON” for negative analog inputs. If
VI+N and VI–N are reversed, this indicator will reverse.
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero-input condition. Additional ana-
log gates close a feedback loop around the integrator and
comparator. This loop permits comparator offset voltage
error compensation. The voltage level established on CAZ
compensates for device offset voltages. The offset error
referred to the input is less than 10µV.
The auto-zero cycle length is 1000 to 3000 counts.
7
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Figure 3. TC7106A Block Diagram
8
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
When the TEST pin on the TC7106A is pulled to V+, all
segmentsareturned“ON.” Thedisplayreads–1888.During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended
periods.
•
•
Signal Integrate: 1000 Counts
(4000 Clock Pulses)
This time period is fixed. The integration period is:
1
TSI = 4000
[f ]
OSC
Where fOSC is the externally set clock frequency.
The display font and the segment drive assignment are
shown in Figure 4.
Reference Integrate: 0 to 2000 Counts
(0 to 8000 Clock Pulses)
DISPLAY FONT
The TC7106A/7107A are drop-in replacements for the
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
1000's
100's
10's
1's
Clock Circuit
Three clocking methods may be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
Figure 4. Display Font and Segment Assignment
TO
COUNTER
÷4
In the TC7106A, an internal digital ground is generated
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
capacitivecurrentswhenthebackplanevoltageisswitched.
40
39
38
CRYSTAL
EXT
DIGITAL SECTION (TC7107A)
TC7106A
TC7107A
OSC
RC NETWORK
Figure 5 shows the TC7107A. It is designed to drive
common anode LEDs. It is identical to the TC7106A except
that the regulated supply and backplane drive have been
eliminated and the segment drive is typically 8mA. The
1000'soutput(pin19)sinkscurrentfromtwoLEDsegments,
and has a 16mA drive capability.
In both devices, the polarity indication is “ON” for nega-
tiveanaloginputs. IfVI–N and VI+N arereversed, thisindication
can be reversed also, if desired.
TO TEST PIN ON TSC7106A
TO GND PIN ON TSC7107A
Figure 6. Clock Circuits
COMPONENT VALUE SELECTION
Auto-Zero Capacitor – CAZ
The CAZ capacitor size has some influence on system
noise. A 0.47µF capacitor is recommended for 200mV full-
scaleapplicationswhere1LSBis100µV. A0.047µFcapaci-
tor is adequate for 2.0V full-scale applications. A mylar
dielectric capacitor is adequate.
The display font is the same as the TC7106A.
System Timing
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The three-phase measure-
ment cycle takes a total of 4000 counts or 16000 clock
pulses. The 4000 count cycle is independent of input signal
magnitude.
Reference Voltage Capacitor – CREF
The reference voltage used to ramp the integrator
output voltage back to zero during the reference-integrate
cycle is stored on CREF. A 0.1µF capacitor is acceptable
whenVI–N istiedtoanalogcommon. Ifalargecommon-mode
voltage exists (VR–EF ≠ analog common) and the application
requires200mVfull-scale, increaseCREF to1.0µF. Rollover
error will be held to less than 1/2 count. A mylar dielectric
capacitor is adequate.
Each phase of the measurement cycle has the following
length:
•
Auto-Zero Phase: 1000 to 3000 Counts
(4000 to 12000 Clock Pulses)
For signals less than full-scale, the auto-zero phase is
assigned the unused reference integrate time period.
9
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Figure 5. TC7107A Block Diagram
10
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Note:1. fOSC = 48kHz (3 readings/sec)
Integrating Capacitor – CINT
CINT should be selected to maximize the integrator
output voltage swing without causing output saturation. Due
to the TC7106A/7107A superior temperature coefficient
specification,analogcommonwillnormallysupplythediffer-
ential voltage reference. For this case a ±2V full-scale
integrator output swing is satisfactory. For 3 readings/
second (fOSC = 48kHz) a 0.22µF value is suggested. If a
different oscillator frequency is used, CINT must be changed
in inverse proportion to maintain the nominal ±2 V integrator
swing.
Oscillator Components
ROSC (Pin 40 to Pin 39) should be 100kΩ. COSC is
0.45
selected using the equation:
fOSC
=
RC
For fOSC of 48kHz, COSC is 100pF nominally.
NotethatfOSCisdividedbyfourtogeneratetheTC7106A
internal control clock. The backplane drive signal is derived
by dividing fOSC by 800.
An exact expression for CINT is:
To achieve maximum rejection of 60Hz noise pickup,
the signal-integrate period should be a multiple of 60Hz.
Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50 Hz rejection,
oscillatorfrequenciesof200kHz,100kHz,662/3kHz,50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 read-
ings/second) will reject both 50Hz and 60Hz.
VFS
1
(4000) (
) (
)
RINT
fOSC
CINT
=
VINT
Where:
fOSC = Clock frequency at Pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
VINT = Desired full-scale integrator output swing
CINT must have low dielectric absorption to minimize
rollover error. A polypropylene capacitor is recommended.
Required Full-Scale Voltage*
VREF
200.0mV
2.000V
100.0mV
1.000V
Integrating Resistor – RINT
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current
is 100µA. The integrator and buffer can supply 20µA drive
currents with negligible linearity errors. RINT is chosen to
remainintheoutputstagelineardriveregionbutnotsolarge
thatprintedcircuitboardleakagecurrentsinduceerrors. For
a 200mV full-scale, RINT is 47kΩ. 2.0V full-scale requires
470kΩ.
* VFS = 2 VREF
In some applications a scale factor other than unity may
exist between a transducer output voltage and the required
digitalreading.Assume,forexample,apressuretransducer
output is 400mV for 2000 lb/in2. Rather than dividing the
input voltage by two the reference voltage should be set to
200mV. This permits the transducer input to be used
directly.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analog common and VI–N. The transducer output is con-
nected between VI+N and analog common.
The internal voltage reference potential available at
analog common will normally be used to supply the convert-
er's reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
whereanexternally-generatedreferencevoltageisdesired,
refer to Figure 7.
Component
Value
Nominal Full-Scale Voltage
200.0mV
0.47µF
47kΩ
2.000V
0.047µF
470kΩ
CAZ
RINT
CINT
0.22µF
0.22µF
11
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
C
+
+
INPUT
BUFFER
I
V
V
+
V
R
+
V
–
+
–
I
+
V
–
+
+
REF
6.8V
ZENER
V
V
I
6.8kΩ
IN
–
V
INTEGRATOR
TC7106A
TC7107A
REF
20kΩ
T
I
I
V
=
V
– V
Z
I
I
[
CM
IN
[
+
V
CM
R C
V
TC7106A
TC7107A
I
I
REF
TC04
Where:
4000
fOSC
T
INTEGRATION TIME
=
=
=
–
V
1.2V
REF
REF
C
R
INTEGRATION CAPACITOR
= INTEGRATION RESISTOR
I
I
COMMON
(b)
(a)
Figure 9. Common-Mode Voltage Reduces Available Integrator
Figure 7. External Reference
Swing. (VCOM ≠ VIN)
Device Pin Functional Description
Differential Signal Inputs
Differential Refe–rence
(V+REF (Pin 36), VREF (Pin 35))
(VI+N (Pin 31), VI–N (Pin 30))
The reference voltage can be generated anywhere
within the V+ to V– power supply range.
To prevent rollover errors from being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
The TC7106A/TC7107A circuits have a significantly
lower analog common temperature coefficient. This gives a
very stable voltage suitable for use as a reference. The
temperature coefficient of analog common is 20ppm/°C
typically.
The TC7106A/7017A is designed with true differential
inputs and accepts input signals within the input stage
common mode voltage range (VCM). The typical range is V+
–1.0 to V– +1 V. Common-mode voltages are removed from
the system when the TC7106A/TC7107A operates from a
battery or floating power source (isolated from measured
system) and VI–N is connected to analog common (VCOM):
See Figure 8.
In systems where common-mode voltages exist, the
86dB common-mode rejection ratio minimizes error. Com-
mon-mode voltages do, however, affect the integrator out-
put level. Integrator output saturation must be prevented. A
worst-case condition exists if a large positive VCM exists in
conjunctionwithafull-scalenegativedifferentialsignal. The
negative signal drives the integrator output positive along
with VCM (Figure 9). For such applications the integrator
output swing can be reduced below the recommended 2.0V
full-scale swing. The integrator output will swing within 0.3V
of V+ or V– without increasing linearity errors.
SEGMENT
DRIVE
LCD DISPLAY
MEASURED
SYSTEM
V
+
C
V
POL BP
BUF
AZ
INT
OSC
1
V IN
+
V
–
OSC
OSC
3
2
V IN
TC7106A
–
V
GND
ANALOG
COMMON REF REF
–
+
+
–
V
V
V
V
+
–
V
V
GND
POWER
SOURCE
+
9V
Figure 8. Common-Mode Voltage Removed in Battery Operation with VI–N = Analog Common
12
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Analog Common (Pin 32)
Internal Voltage Reference Stability
The analog common pin is set at a voltage potential
approximately 3.0V below V+. The potential is guaranteed
to be between 2.7V and 3.35 V below V+. Analog common
is tied internally to the N channel FET capable of sinking
20mA. This FET will hold the common line at 3.0V should an
external load attempt to pull the common line toward V+.
Analog common source current is limited to 10µA. Analog
common is therefore easily pulled to a more negative
voltage (i.e., below V+ – 3.0V).
The analog common voltage temperature stability has
been significantly improved (Figure 10). The “A” version of
the industry standard circuits allow users to upgrade old
systems and design new systems without external voltage
references. External R and C values do not need to be
changed. Figure 11 shows analog common supplying the
necessary voltage reference for the TC7106A/TC7107A.
200
The TC7106A connects the internal VI+N and VI–N inputs
to analog common during the auto-zero cycle. During the
reference-integrate phase, VI–N is connected to analog com-
mon. If VI–N is not externally connected to analog common,
a common-mode voltage exists. This is rejected by the
converter's 86dB common-mode rejection ratio. In battery
operation, analog common and VI–N are usually connected,
removingcommon-modevoltageconcerns.Insystemswhere
VI–N is connected to the power supply ground or to a given
voltage, analog common should be connected to VI–N.
Theanalogcommonpinservestosettheanalogsection
reference or common point. The TC7106A is specifically
designed to operate from a battery or in any measurement
system where input signals are not referenced (float) with
respect to the TC7106A power source. The analog common
potential of V+ – 3.0V gives a 6 V end of battery life voltage.
The common potential has a 0.001%/% voltage coefficient
and a 15 Ω output impedance.
180
NO
MAXIMUM
SPECIFIED
NO MAXIMUM
SPECIFIED
160
140
120
100
TYPICAL
NO MAXIMUM
SPECIFIED
MAXIMUM
LIMIT
80
60
40
20
TYPICAL
TYPICAL
TC
ICL7106
ICL7136
7106A
0
Figure 10. Analog Common Temperature Coefficient
With sufficiently high total supply voltage (V+ – V–
> 7.0V) analog common is a very stable potential with
excellent temperature stability—typically 20ppm/°C. This
potential can be used to generate the reference voltage. An
external voltage reference will be unnecessary in most
cases because of the 50ppm/°C maximum temperature
coefficient. See Internal Voltage Reference discussion.
1
–
+
24kΩ
1kΩ
V
V
TC7106A
TC7107A
Test (Pin 37)
The TEST pin potential is 5V less than V+. TEST may be
used as the negative power supply connection for external
CMOSlogic. TheTESTpinistiedtotheinternallygenerated
negative logic supply (Internal Logic Ground) through a
500Ω resistor in the TC7106A. The TEST pin load should be
no more than 1mA .
36
+
V
REF
V
REF
–
35
V
REF
32
ANALOG
COMMON
If TEST is pulled to V+ all segments plus the minus sign
will be activated. Do not operate in this mode for more than
severalminuteswiththeTC7106A. WithTEST=V+ theLCD
segments are impressed with a DC voltage which will
destroy the LCD.
SET V
= 1/2 V
REF
FULL SCALE
Figure 11. Internal Voltage Reference Connection
The TEST pin will sink about 10mA when pulled to V+.
13
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
TC7107 Power Dissipation Reduction
POWER SUPPLIES
The TC7107A sinks the LED display current and this
causes heat to build up in the IC package. If the internal
voltage reference is used, the changing chip temperature
can cause the display to change reading. By reducing the
LED common anode voltage the TC7107A package power
dissipation is reduced.
The TC7107A is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generatedfromtheclockoutputwithtwodiodes,twocapaci-
tors, and an inexpensive IC. (Figure 12)
In selected applications a negative supply is not re-
quired. The conditions to use a single +5V supply are:
Figure 14 is a photograph of a curve-tracer display
showing the relationship between output current and output
voltage for a typical TC7107CPL. Since a typical LED has
1.8 volts across it at 7mA, and its common anode is con-
nected to +5V, the TC7107A output is at 3.2V (point A on
Figure 13). Maximum power dissipation is 8.1mA x 3.2V x
24 segments = 622mW.
Notice, however, that once the TC7107A output voltage
isabovetwovolts, theLEDcurrentisessentiallyconstantas
output voltage increases. Reducing the output voltage by
0.7V (point B in Figure 14) results in 7.7mA of LED current,
only a 5 percent reduction. Maximum power dissipation is
only 7.7mA x 2.5 V x 24 = 462mW, a reduction of 26%. An
output voltage reduction of 1 volt (point C) reduces LED
current by 10% (7.3mA) but power dissipation by 38%!
(7.3mA x 2.2V x 24 = 385mW).
•
The input signal can be referenced to the center of the
common-mode range of the converter.
The signal is less than ±1.5V.
An external reference is used.
The TSC7660 DC to DC converter may be used to
•
•
generate – 5 V from +5 V (Figure 13).
+
V
CD4009
+
V
OSC
1
OSC
0.047
µF
2
1N914
+
–
OSC
3
10
µF
1N914
TC7107A
GND
–
V
–
V
= –3.3V
Figure 12. Generating Negative Supply From +5 V
+5 V
1
+
36
35
32
+
V
V
V
REF
–
REF
LED
DRIVE
Figure 14. TC7107A Output Current vs Output Voltage
COM
TC7107A
Reduced power dissipation is very easy to obtain.
Figure15showstwoways:eithera5.1ohm,1/4wattresistor
or a 1 Amp diode placed in series with the display (but not in
series with the TC7107A). The resistor will reduce the
TC7107A output voltage, when all 24 segments are “ON,” to
point “C” of Figure 14. When segments turn off, the output
voltagewillincrease.Thediode,ontheotherhand,willresult
in a relatively steady output voltage, around point “B.”
+
31
V
IN
V
IN
–
IN
30
21
V
–
GND
V
8
26
2
4
+
(–5 V)
5
10µF
TC7660
*3-1/2 DIGIT ADC
3
+
10µF
Figure 13. Negative Power Supply Generation with TC7660
14
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
In addition to limiting maximum power dissipation, the
resistor reduces the change in power dissipation as the
display changes. This effect is caused by the fact that, as
fewer segments are “ON,” each “ON” output drops more
voltage and current. For the best case of six segments (a
“111” display) to worst case (a “1888” display) the resistor
willchangeabout230mW, whileacircuitwithouttheresistor
will change about 470mW. Therefore, the resistor will re-
duce the effect of display dissipation on reference voltage
drift by about 50%.
APPLICATIONS INFORMATION
Liquid Crystal Display Sources
Several LCD manufacturers supply standard LCD dis-
plays to interface with the TC7106A 3-1/2 digit analog-to-
digital converter.
Manufacturer Address/Phone
Part Numbers1
Crystaloid
Electronics
5282 Hudson Dr.
Hudson, OH 44236
216/655-2429
C5335, H5535,
T5135, SX440
The change in LED brightness caused by the resistor is
almost unnoticeable as more segments turn off. If display
brightness remaining steady is very important to the de-
signer, a diode may be used instead of the resistor.
AND
720 Palomar Ave.
Sunnyvale, CA 94086
408/523-8200
FE 0201,0701
FE 0203, 2201
FE 0501
IN
–5V
+5V
Epson
3415 Kashikawa St.
Torrance, CA 90505
213/534-0360
LD-B709BZ
LD-H7992AZ
+
–
1 MΩ
24kΩ
1kΩ
150Ω
Hamlin, Inc.
612 E. Lake St.
Lake Mills, WI 53551
414/648-2361
3902, 3933, 3903
TP3
0.47
µF
0.22
µF
100
pF
0.01
µF
Note: 1. Contact LCD manufacturer for full product listing/specifications.
TP5
TP2
TP1
0.1
µF
DISPLAY
100
kΩ
47
kΩ
Light Emitting Diode Display Sources
Several LED manufacturers supply seven segment
digits with and without decimal point annunciators for the
TC7107A.
40
1
30
TP
4
21
TC7107A
10
20
Manufacturer
Address
Display Type
DISPLAY
Hewlett-Packard
Components
640 Page Mill Rd.
Palo Alto, CA 94304
LED
5.1Ω 1/4W
1N4001
AND
720 Palomar Ave.
LED
Sunnyvale, CA 94086
Figure 15. Diode or Resistor Limits Package Power Dissipation
15
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Decimal Point and Annunciator Drive
Ratiometric Resistance Measurements
The TEST pin is connected to the internally-generated
digital logic supply ground through a 500 Ω resistor. The
TEST pin may be used as the negative supply for external
CMOS gate segment drivers. LCD display annunciators for
decimal points, low battery indication, or function indication
may be added without adding an additional supply. No more
than 1mA should be supplied by the TEST pin: its potential
is approximately 5V below V+.
The true differential input and differential reference
make ratiometric reading possible. Typically in a ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor is applied to the
reference input. If the unknown equals the standard, the
display will read 1000. The displayed reading can be deter-
mined from the following expression:
+
V
+
V
4049
R Unknown
Displayed Reading =
x 1000
TC7106A
R Standard
TO LCD
DECIMAL
POINT
21
BP
The display will overrange for R Unknown ≥ 2 x R
standard.
GND
37
TEST
TO LCD
BACK-
PLANE
+
+
V
V
REF
–
V
R
REF
STANDARD
+
LCD DISPLAY
+
V
V
IN
+
V
R
BP
UNKNOWN
TC7106A
–
V
IN
TO LCD
DECIMAL
POINTS
DECIMAL
ANALOG
COMMON
POINT
TC7106A
SELECT
Figure 17. Low Parts Count Ratiometric Resistance
Measurement
4030
GND
TEST
Figure 16. Decimal Point Drive Using TEST as Logic Ground
16
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
9V
+
+
IN4148
200mV
1µF
26
–
V
–
27
29
28
1
IN
9MΩ
V
+
+
V
14
13
12
11
10
9
1
2
3
4
5
6
7
10kΩ
1MΩ
24kΩ
1kΩ
2 V
0.02
µF
TC7106A
900kΩ
90kΩ
10kΩ
1MΩ
36
20 V
V
V
REF
AD636
47kΩ
1 W
10%
–
35
32
31
–
6.8µF
REF
+
200 V
ANALOG
COMMON
1MΩ 10%
40
+
V
8
IN
0.01
µF
20kW
10%
2.2µF
30
26
38
39
–
V
COM
IN
C1 = 3–10pF VARIABLE,
C2 = 132pF VARIABLE
–
V
BP
SEG
DRIVE
LCD DISPLAY
Figure 18. 3 1/2 Digit True RMS AC DMM
9V
+
+
9V
5.6kΩ
160kΩ
160kΩ
300kΩ
300kΩ
+
–
+
–
V
–
V
V
–
V
V
V
R
V
V
1N914
IN
1
IN
20kΩ
+
R
+
IN
1N4148
SENSOR
1
TC7106A
IN
TC7106A
= 2V
50kΩ
V
FS
0.7%/°C
R
2
20kΩ
+
+
R
3
R
V
V
2
V
V
PTC
REF
REF
50kΩ
–
REF
–
REF
COMMON
COMMON
Figure 20. Positive Temperature Coefficient Resistor
Temperature Sensor
Figure 19. Temperature Sensor
17
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
9V
2
1
CONSTANT 5 V
+
+
V
V
+
V
REF
REF02
TC7106A
TC911
51kΩ
5.1kΩ
50kΩ
6
–
V
V
R
OUT
ADJ
2
REF
R
4
R
5
V
= 2.00V
FS
5
3
2
–
8
1
NC
–
V
V
IN
3
+
TEMP
V
OUT =
1.86V @
4
+
IN
25°C
TEMPERATURE
DEPENDENT
OUTPUT
50kΩ
1.3k
COMMON
R
1
–
V
GND
4
26
Figure 21. Integrated Circuit Temperature Sensor
TO PIN 1
TO PIN 1
SET V
REF
Ω
= 100mV
SET V
= 100mV
REF
40
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
100k
100k
Ω
39
38
37
36
35
100pF
100pF
+5V
Ω
Ω
22k
1k
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Ω
1 k
22k
Ω
0.1µF
0.1µF
Ω
1M
0.01µF
47k
1MΩ
+
–
+
–
IN
IN
0.01µF
47kΩ
TC7106A
TC7107A
+
–
0.47µF
0.47µF
Ω
9V
0.22µF
0.22µF
–5V
TO DISPLAY
TO DISPLAY
TO BACKPLANE
Figure 22. TC7106A Using the Internal Reference: 200mV Full-
Scale, 3 Readings-per-second (RPS).
Figure 23. TC7107A Internal Reference (200mV Full-Scale,
3RPS, VI–N Tied to GND for Single Ended Inputs).
18
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
+
V
TO PIN 1
1
40
SET V
REF
= 1V
40
39
38
37
36
35
34
33
32
31
30
100k
Ω
TO
LOGIC
V
TO
LOGIC
GND
CC
100pF
Ω
24k
+
V
25k
Ω
0.1µF
TC7106A
1M
Ω
+
IN
0.01µF
TC7106A
TC7107A
–
0.047µF
–
V
O/R
29
28
27
26
25
24
23
22
21
Ω
470k
0.22µF
–
V
U/R
20
21
TO DISPLAY
CD4023
OR 74C10
CD4077
O/R = OVERRANGE
U/R = UNDERRANGE
Figure 24. Circuit for Developing Underrange and Overrange
Signals from TC7106A Outputs.
Figure 25. TC7106A/TC7107A: Recommended Component
Values for 2.00V Full-Scale
TO PIN 1
40
TO PIN 1
40
100k
Ω
100k
Ω
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SET V
= 100mV
39
38
37
36
35
34
33
32
SET V
REF
= 100mV
REF
100pF
100pF
Ω
10k
10k
Ω
Ω
10k
10k
Ω
+
+
V
V
1k
Ω
TC04
1 k
Ω
0.1µF
TC04
0.1µF
+
–
1.2V
0.01µF
+
1.2V
0.01µF
IN
1MΩ
IN
31
30
29
28
27
26
25
24
23
22
21
1MΩ
TC7107A
TC7107A
0.47µF
0.47µF
–
47kΩ
47k
Ω
0.22µF
–
V
0.22µF
TO DISPLAY
TO DISPLAY
Figure 26. TC7107A With a 1.2V External Band-Gap Reference.
(V–IN Tied to Common.)
Figure 27. TC7107A Operated from Single +5V Supply. An
External Reference Must Be Used in This Application.
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3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PACKAGE DIMENSIONS
40-Pin CerDIP
PIN 1
.540 (13.72)
.510 (12.95)
.098 (2.49) MAX.
2.070 (52.58)
.030 (0.76) MIN.
.620 (15.75)
.590 (15.00)
2.030 (51.56)
.060 (1.52)
.020 (0.51)
.210 (5.33)
.170 (4.32)
.015 (0.38)
.008 (0.20)
3°MIN.
.150 (3.81)
MIN.
.200 (5.08)
.125 (3.18)
.700 (17.78)
.620 (15.75)
.020 (0.51)
.016 (0.41)
.110 (2.79)
.090 (2.29)
.065 (1.65)
.045 (1.14)
40-Pin PDIP
PIN 1
.555 (14.10)
.530 (13.46)
2.065 (52.45)
2.035 (51.49)
.610 (15.49)
.590 (14.99)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.015 (0.38)
.008 (0.20)
.150 (3.81)
.115 (2.92)
3° MIN.
.700 (17.78)
.610 (15.50)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
20
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PACKAGE DIMENSIONS (Cont.)
44-Pin PLCC
PIN 1
.021 (0.53)
.013 (0.33)
.050 (1.27) TYP.
.695 (17.65)
.685 (17.40)
.630 (16.00)
.590 (15.00)
.656 (16.66)
.650 (16.51)
.032 (0.81)
.026 (0.66)
.020 (0.51) MIN.
.656 (16.66)
.650 (16.51)
.120 (3.05)
.090 (2.29)
.695 (17.65)
.650 (17.40)
.180 (4.57)
.165 (4.19)
44-Pin PQFP
7° MAX.
.009 (0.23)
.005 (0.13)
PIN 1
.041 (1.03)
.026 (0.65)
.018 (0.45)
.012 (0.30)
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.031 (.080) TYP.
.010 (0.25) TYP.
.398 (10.10)
.390 (9.90)
.083 (2.10)
.075 (1.90)
.557 (14.15)
.537 (13.65)
.096 (2.45) MAX.
Dimensions: inches (mm)
Sales Offices
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10 Sam Chuk Street, Ground Floor
San Po Kong, Kowloon
Hong Kong
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TelCom Semiconductor
Austin Product Center
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Austin, TX 78758
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FAX: 512-873-8236
TelCom Semiconductor
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P.O. Box 7267
Mountain View, CA 94039-7267
TEL: 415-968-9241
FAX: 415-967-1590
E-Mail: liter@c2smtp.telcom-semi.com
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21
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