TSC695F-25MAMQ_技术文档

Features

• Integer Unit Based on SPARC V7 High-performance RISC Architecture

• Optimized Integrated 32/64-bit Floating-point Unit

• On-chip Peripherals

– EDAC and Parity Generator and Checker

– Memory Interface

Chip Select Generator

Waitstate Generation

Memory Protection

– DMA Arbiter

– Timers

Rad-Hard 32-bit

SPARC

Embedded

Processor

General Purpose Timer (GPT)

Real-time Clock Timer (RTCT)

Watchdog Timer (WDT)

– Interrupt Controller with 5 External Inputs

– General Purpose Interface (GPI)

– Dual UART

• Speed Optimized Code RAM Interface

8- or 40-bit boot-PROM (Flash) Interface

• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes

• Fully Static Design

• Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz

• Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs

• Operating Range: 4.5V to 5.5V⁽¹⁾-55°C to +125°C

• Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019

• SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)

• No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm²

• Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540

• Package: 256 MQFPF; Bare Die

TSC695F

Note:

1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.

Description

The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit

RISC embedded processor implementing the SPARC architecture V7 specification. It

has been developed with the support of the ESA (European Space Agency), and

offers a full development environment for embedded space applications.

The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300

KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for

space, as it has on-chip concurrent transient and permanent error detection.

The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a

Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers

a high security watchdog, two timers, an interrupt controller, parallel and serial inter-

faces. Fault tolerance is supported using parity on internal/external buses and an

EDAC on the external data bus. The design is highly testable with the support of an

On-Chip Debugger (OCD), and a boundary scan through JTAG interface.

Rev. 4118J–AERO–08/04

Block Diagram

Figure 1. TSC695F Block Diagram

32-bit

Integer

Unit

DMA

TAP

DMA Ctrl

Arbiter

32/64-bit

Floating-Point

Unit

Clock

&

Parity

Gen./Chk.

Reset

Access

Controller

Parity

Managt

Mem Ctrl

Gen./Chk.

Wait State

Controller

Ready/Busy

Add.+Size+ASI

Address

Interface

Error

Managt

Real Time Clock

Timer

Watch

Dog

General Purpose

Timer

EDAC

Data+Check bits

Parities

Interrupt

General Purpose

Interface

UART B

UART A

Parity

Gen./Check.

Controller

Interrupts

GPI bits

RxD, TxD

Pin Descriptions

For pin assignment, refer to package section.

Table 1. Pin Descriptions

Signal

Type

Active

Description

RA[31:0]

RAPAR

RASI[3:0]

RSIZE[1:0]

RASPAR

CPAR

I/O,

I/O

O

32-bit registered address bus

Registered address bus parity

4-bit registered address space identifier

2-bit registered bus transaction size

Registered ASI and SIZE parity

Control bus parity

Output buffer: 400 pF

High

-

High

D[31:0]

CB[6:0]

DPAR

32-bit data bus

7-bit check-bit bus

High

Low

High

Low

High

Data bus parity

RLDSTO

ALE

Registered atomic load-store

Address latch enable

Data transfer

DXFER

LOCK

I/O

Bus lock

RD

Read access

WE

Write enable

WRT

Advanced write

MHOLD+FHOLD

+BHOLD+FCCV

MHOLD

O

Low

Memory bus hold

MDS

O

I

Low

Memory data strobe

-

MEXC

Memory exception

-

PROM8

BA[1:0]

Select 8-bit wide PROM

Latched address used for 8-bit wide boot PROM

PROM chip select

-

O

I

-

ROMCS

ROMWRT

MEMCS[9:0]

MEMWR

Low

-

ROM write enable

-

O

Memory chip select

Output buffer: 400 pF

Memory write strobe

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TSC695F

4118J–AERO–08/04

TSC695F

Table 1. Pin Descriptions (Continued)

Signal

Type

Active

Description

OE

O

I

Low

High

Low

High

Low

High

Low

High

Memory output enable

Data buffer enable

Output buffer: 400 pF

BUFFEN

DDIR

-

Data buffer direction

I/O chip select

DDIR

IOSEL[3:0]

IOWR

I/O and exchange memory write strobe

Exchange memory chip select

Bus ready

EXMCS

BUSRDY

BUSERR

DMAREQ

DMAGNT

DMAAS

DRDY

I

Bus error

I

DMA request

O

I

DMA grant

DMA address strobe

Data ready during DMA access

IU error

O

I

IUERR

CPUHALT

SYSERR

SYSHALT

SYSAV

NOPAR

INULL

Processor (IU & FPU) halt and freeze

System error

System halt

O

I

System availability

No parity

O

I

Integer unit nullify cycle

Instruction fetch

INST

Used to check the execute

stage of IU

FLUSH

DIA

FPU instruction flush

Delay instruction annulled

Real Time Clock Counter output

Receive data UART ’A’ and ’B’

Transmit data UART ’A’ and ’B’

GPI input/output

instruction pipeline

RTC

-

RxA/RxB

TxA/TxB

GPI[7:0]

GPIINT

EXTINT[4:0]

EXTINTACK

IWDE

Input trigger

O

I/O

O

I

-

Input trigger

High

GPI interrupt

-

External interrupt

Input trigger

O

I

High

External interrupt acknowledge

Internal watch dog enable

External watch dog input interrupt

Watch dog clock

-

EWDINT

WDCLK

CLK2

I

Input trigger

I

-

I

Double frequency clock

System clock

-

SYSCLK

RESET

SYSRESET

TMODE[1:0]

DEBUG

TCK

O

I

-

Low

Output reset

-

System input reset

Factory test mode

Input trigger

I

Functional mode=00

I

High

Low

Software debug mode

Test (JTAG) clock

-

I

-

TRST

I

Test (JTAG) reset

pull-up ≈ 37 kΩ

TMS

I

Test (JTAG) mode select

Test (JTAG) data input

Test (JTAG) data output

Main internal power

Output driver power

pull-up ≈ 37 kΩ

TDI

I

pull-up ≈ 37 kΩ

TDO

O

-

VCCI/VSSI

VCCO/VSSO

Note:

If not specified, the output buffer type is 150 pF, the input buffer type is TTL.

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4118J–AERO–08/04

System Architecture The TSC695F is to be used as an embedded processor requiring only memory and

application specific peripherals to be added to form a complete on-board computer. All

other system support functions are provided by the core.

Figure 2. System Architecture Based on TSC695F

DMA Unit

Boot PROM

Ax[31:0]

Xtd PROM

Xchg Mem

Glue

Logic

Xtd RAM

Local

Memory

I/O 0

to

I/O 3

DMAGNT

DMAREQ

DMAAS

Xtd I/O

(BUFFEN, DDIR)

Xtd general

MEMCtrl

(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...)

Memory

Interface

FPU

RAMCtrl

(MEMCS[9:0], MEMWR, OE)

RAM

Memory

DMA

(0 WS)

A[31:0]

IU

User

Application

Peripherals

TSC695F

4

TSC695F

4118J–AERO–08/04

TSC695F

Product Description

Integer Unit

The Integer Unit (IU) is designed for highly dependable space and military applications,

and includes support for error detection. The RISC architecture makes the creation of a

processor that can execute instructions at a rate approaching one instruction per pro-

cessor clock possible.

To achieve that rate of execution, the IU employs a four-stage instruction pipeline that

permits parallel execution of multiple instructions.

•

Fetch - The processor outputs the instruction address to fetch the instruction.

Decode - The instruction is placed in the instruction register and is decoded. The

processor reads the operands from the register file and computes the next

instruction address.

•

Execute - The processor executes the instruction and saves the results in temporary

registers. Pending traps are prioritized and internal traps are taken during this stage.

Write - If no trap is taken, the processor writes the result to the destination register.

All four stages operate in parallel, working on up to four different instructions at a time. A

basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.

By the time it reaches the write stage, three more instructions have entered and are

moving through the pipeline behind it. So, after the first four cycles, a single-cycle

instruction exits the pipeline and a single-cycle instruction enters the pipeline on every

cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but

they are called single cycle because with this type of instruction the processor can com-

plete one instruction per cycle after the initial four-cycle delay.

Floating-point Unit

The FLoating Point Unit (FPU) is designed to provide execution of single and double-

precision floating-point instructions concurrently with execution of integer instructions by

the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.

The FPU is designed for highly dependable space and military applications, and

includes support for concurrent error detection and testability.

The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and

write stages (F, D, E and W). The fetch unit captures instructions and their addresses

from the data and address buses. The decode unit contains logic to decode the floating-

point instruction opcodes. The execution unit handles all instruction execution. The exe-

cution unit includes a floating-point queue (FP queue), which contains stored floating-

point operate (FPop) instructions under execution and their addresses. The execution

unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon

the IU to access all addresses and control signals for memory access. Floating-point

loads and stores are executed in conjunction with the IU, which provides addresses and

control signals while the FPU supplies or stores the data. Instruction fetch for integer

and floating-point instructions is provided by the IU.

The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR

is a 32-bit status and control register. It keeps track of rounding modes, floating-point

trap types, queue status, condition codes, and various IEEE exception information. The

floating-point queue contains the floating-point instruction currently under execution,

along with its corresponding address.

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4118J–AERO–08/04

Instruction Set

TSC695F instructions fall into six functional categories: load/store, arithmetic/logi-

cal/shift, control transfer, read/write control register, floating-point, and miscellaneous.

Please refer to SPARC V7 Instruction-set Manual.

Note:

The execution of IFLUSH will cause an illegal instruction trap.

On-chip Peripherals

Memory Interface

The TSC695F is designed to allow easy interfacing to internal/external memory

resources.

Table 2. Memory Mapping

Memory Contents

Start Address

Size (bytes)

Data Size and Parity Options

Boot PROM

0x00000000

0x01000000

128K → 16M

8-bit mode

40-bit mode

8-bit mode

40-bit mode

No parity/-No EDAC/-Only byte write

Parity + EDAC mandatory/-Only word write

No parity/-No EDAC/-Only byte write

Extended PROM

Max: 15M

Parity + EDAC mandatory/-Only word write

Exchange Memory

System Registers

RAM (8 blocks)

Extended RAM

I/O Area 0

0x01F00000

0x01F80000

0x02000000

0x04000000

0x10000000

0x11000000

0x12000000

0x13000000

0x14000000

0x80000000

4k → 512k

512K (124 used)

8*32K → 8*4M

Max: 192M

0 → 16M

Parity + EDAC option/-Only word write

Parity/-Only word read/write access

Parity + EDAC option/-All data sizes allowed

Parity option/-All data sizes allowed

I/O Area 1

0 → 16M

I/O Area 2

0 → 16M

I/O Area 3

0 → 16M

Extended I/O Area

Extended General

Max: 1728M

Max: 2G

No parity/-All data sizes allowed

System Registers

The system registers are only writable by IU in the supervisor mode or by DMA during

halt mode.

Table 3. System Registers Address Map

System Register Name

System Control Register

Software Reset

Address

SYSCTR

SWRST

PDOWN

SYSFSR

FAILAR

0x 01F8 0000

0x 01F8 0004

0x 01F8 0008

0x 01F8 00A0

0x 01F8 00A4

0x 01F8 00B0

0x 01F8 00D0

Power Down

System Fault Status Register

Failing Address Register

Error & Reset Status Register

Test Control Register

ERRRSR

TESCTR

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TSC695F

4118J–AERO–08/04

TSC695F

Table 3. System Registers Address Map (Continued)

System Register Name

Address

Memory Configuration Register

I/O Configuration Register

MCNFR

0x 01F8 0010

0x 01F8 0014

0x 01F8 0018

0x 01F8 0020

0x 01F8 0024

0x 01F8 0028

0x 01F8 002C

0x 01F8 0044

0x 01F8 0048

0x 01F8 004C

0x 01F8 0050

0x 01F8 0054

0x 01F8 0060

0x 01F8 0064

0x 01F8 0080

0x 01F8 0084

0x 01F8 0088

0x 01F8 008C

0x 01F8 0098

0x 01F8 00A8

0x 01F8 00AC

0x 01F8 00E0

0x 01F8 00E4

0x 01F8 00E8

IOCNFR

WSCNFR

APS1BR

APS1ER

APS2BR

APS2ER

INTSHR

INTPDR

INTMKR

INTCLR

INTFCR

WDOGTR

WDOGST

RTCCR

Waitstate Configuration Register

Access Protection Segment 1 Base Register

Access Protection Segment 1 End Register

Access Protection Segment 2 Base Register

Access Protection Segment 2 End Register

Interrupt Shape Register

Interrupt Pending Register

Interrupt Mask Register

Interrupt Clear Register

Interrupt Force Register

Watchdog Timer Register

Watchdog Timer Trap Door Set

Real Time Clock Timer <Counter> Register

Real Time Clock Timer <Scaler> Register

General Purpose Timer <Counter> Register

General Purpose Timer <Scaler> Register

Timers Control Register

RTCSR

GPTCR

GPTSR

TIMCTR

GPICNFR

GPIDATR

UARTAR

UARTBR

UARTSR

General Purpose Interface Configuration Register

General Purpose Interface Data Register

UART ’A’ Rx & Tx Register

UART ’B’ Rx & Tx Register

UART Status Register

Wait-state and Time-out

Generator

It is possible to control the wait-state generation by programming a Wait-state Configu-

ration Register. The maximum programmable number of wait-states is applied by

default at reset.

It is possible to program the number of wait-states for the following combinations:

–

RAM read and write

PROM read and write (i.e. EEPROM or Flash write)

Exchange Memory read/write

Four individual I/O peripherals read/write

A bus time-out function of 256 system clock cycles is provided for the bus ready con-

trolled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM,

7

4118J–AERO–08/04

Extended I/O and the Extended General areas.

EDAC

The TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits

(CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR)

is used to check and generate the odd parity over the 32-bit data bus. This means that

altogether 40 bits are used when the EDAC is enabled.

The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on

the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-

one and stuck-at-zero failure for any nibble in the data word as a non-correctable error.

Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-

correctable error.

Memory and I/O Parity

The TSC695F handles parity towards memory and I/O in a special way. The processor

can be programmed to use no parity, only parity or parity and EDAC protection towards

memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR.

Memory Redundancy

Programming the Memory Configuration Register, the TSC695F provides chip selects

for two redundant memory banks for replacement of faulty banks.

Memory Access Protection

•

Unimplemented Areas - Access to all unimplemented memory areas are handled by

the TSC695F and detected as illegal.

RAM Write Access Protection - The TSC695F can be programmed to detect and

mask write accesses in any part of the RAM. The protection scheme is enabled only

for data area, not for the instruction area. The programmable write access

protection is based on two segments.

•

Boot PROM Write Protection - The TSC695F supports a qualified PROM write for

an 8-bit wide PROM and/or for a 40-bit wide PROM.

DMA

DMA Interface

The TSC695F supports Direct Memory Access (DMA). The DMA unit requests access

to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA

unit receives the DMAGNT signal in response, the processor bus is granted. In case the

processor is in the power-down mode the processor is permanent tri-stated, and a

DMAREQ will directly give a DMAGNT. The TSC695F includes a DMA session time-out

function.

Bus Arbiter

The TSC695F always has the lowest priority on the system bus.

Traps

A trap is a vectored transfer of control to the supervisor through a special trap table that

contains the first four instructions of each trap handler. The base address of the table is

established by supervisor and the displacement, within the table, is determined by the

trap type. Two categories of traps can appear.

8

TSC695F

4118J–AERO–08/04

TSC695F

Synchronous Traps

Table 4. Synchronous Traps

Trap

Priority

Trap Type (tt) Comments

Sources: SYSRESET* pin

software reset

watchdog reset

Reset

1

–

IU or System error reset

Non-restartable, imprecise

Severe error requiring a re-boot

error

2.1

2.2

2.3

2.4

64h

62h

65h

63h

61h