TXB0D4 [MICROCHIP]
Stand-Alone CAN Controller with SPI Interface; 独立CAN ，SPI接口控制器
| 型号： | TXB0D4 |
| 厂家： | 
MICROCHIP |
| 描述： | Stand-Alone CAN Controller with SPI Interface |
| 文件： | 总92页 (文件大小：1295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP2515
Stand-Alone CAN Controller with SPI Interface
Features:
Description
Microchip Technology’s MCP2515 is a stand-alone
Controller Area Network (CAN) controller that
implements the CAN specification, version 2.0B. It is
capable of transmitting and receiving both standard
and extended data and remote frames. The MCP2515
has two acceptance masks and six acceptance filters
that are used to filter out unwanted messages, thereby
reducing the host MCU’s overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).
• Implements CAN V2.0B at 1 Mb/s:
- 0 – 8 byte length in the data field
- Standard and extended data and remote
frames
• Receive Buffers, Masks and Filters:
- Two receive buffers with prioritized message
storage
- Six 29-bit filters
- Two 29-bit masks
• Data Byte Filtering on the First Two Data Bytes
(applies to standard data frames)
Package Types
18-Lead PDIP/SOIC
1
18
VDD
TXCAN
RXCAN
• Three Transmit Buffers with Prioritization and
Abort Features
2
3
4
5
17
16
15
RESET
CS
• High-Speed SPI Interface (10 MHz):
CLKOUT/SOF
- SPI modes 0,0and 1,1
TX0RTS
TX1RTS
SO
• One-Shot mode Ensures Message Transmission
is Attempted Only One Time
14 SI
13
12
11
10
6
7
8
9
SCK
• Clock Out Pin with Programmable Prescaler:
TX2RTS
OSC2
- Can be used as a clock source for other
device(s)
INT
RX0BF
RX1BF
OSC1
Vss
• Start-of-Frame (SOF) Signal is Available for
Monitoring the SOF Signal:
20-LEAD TSSOP
- Can be used for time-slot-based protocols
and/or bus diagnostics to detect early bus
degradation
1
2
20
19
18
17
16
15
14
13 INT
12
11
VDD
TXCAN
RXCAN
RESET
3
4
5
CLKOUT/SOF
TX0RTS
TX1RTS
NC
CS
SO
SI
NC
SCK
• Interrupt Output Pin with Selectable Enables
• Buffer Full Output Pins Configurable as:
- Interrupt output for each receive buffer
- General purpose output
6
7
8
9
10
TX2RTS
OSC2
OSC1
VSS
• Request-to-Send (RTS) Input Pins Individually
Configurable as:
RX0BF
RX1BF
- Control pins to request transmission for each
transmit buffer
MCP2515
20-Lead 4x4 QFN*
- General purpose inputs
• Low-Power CMOS Technology:
- Operates from 2.7V – 5.5V
20 19 18 17 16
CLKOUT
SO
SI
15
14
1
- 5 mA active current (typical)
- 1 µA standby current (typical) (Sleep mode)
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
TX0RTS
TX1RTS
NC
2
3
4
5
EP
21
13 NC
12
11
SCK
INT
TX2RTS
6
7
8
9 10
* Includes Exposed Thermal
Pad (EP); see Table 1-1.
2003-2012 Microchip Technology Inc.
DS21801G-page 1
MCP2515
NOTES:
DS21801G-page 2
2003-2012 Microchip Technology Inc.
MCP2515
1.2
Control Logic
1.0
DEVICE OVERVIEW
The control logic block controls the setup and operation
of the MCP2515 by interfacing to the other blocks in
order to pass information and control.
The MCP2515 is a stand-alone CAN controller
developed to simplify applications that require
interfacing with a CAN bus. A simple block diagram of
the MCP2515 is shown in Figure 1-1. The device
consists of three main blocks:
Interrupt pins are provided to allow greater system
flexibility. There is one multi-purpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as status
registers (accessed via the SPI interface), can also be
used to determine when a valid message has been
received.
1. The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
receive buffers.
2. The control logic and registers that are used to
configure the device and its operation.
3. The SPI protocol block.
An example system implementation using the device is
shown in Figure 1-2.
Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional, as initiating message
transmissions can also be accomplished by utilizing
control registers, accessed via the SPI interface.
1.1
CAN Module
The CAN module handles all functions for receiving
and transmitting messages on the CAN bus. Messages
are transmitted by first loading the appropriate
message buffer and control registers. Transmission is
initiated by using control register bits via the SPI
interface or by using the transmit enable pins. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against the user-
defined filters to see if it should be moved into one of
the two receive buffers.
1.3
SPI Protocol Block
The MCU interfaces to the device via the SPI interface.
Writing to, and reading from, all registers is
accomplished using standard SPI read and write
commands, in addition to specialized SPI commands.
FIGURE 1-1:
BLOCK DIAGRAM
CAN Module
RXCAN
TXCAN
CAN
Protocol
Engine
CS
SCK
SI
SPI
Interface
Logic
TX and RX Buffers
Masks and Filters
SPI
Bus
SO
Control Logic
OSC1
OSC2
Timing
Generation
INT
CLKOUT
RX0BF
RX1BF
TX0RTS
TX1RTS
TX2RTS
Control
and
Interrupt
Registers
RESET
2003-2012 Microchip Technology Inc.
DS21801G-page 3
MCP2515
FIGURE 1-2:
EXAMPLE SYSTEM IMPLEMENTATION
Node
Node
Node
Controller
Controller
Controller
SPI
SPI
SPI
MCP2515
MCP2515
MCP2515
TX
XCVR
RX
TX
XCVR
TX
XCVR
RX
RX
CANH
CANL
TABLE 1-1:
PINOUT DESCRIPTION
PDIP/
SOIC
Pin #
TSSOP QFN I/O/P
Name
Description
Alternate Pin Function
Pin #
Pin # Type
TXCAN
RXCAN
CLKOUT
1
2
3
1
2
3
19
20
1
O
I
Transmit output pin to CAN bus
Receive input pin from CAN bus
—
—
O
Clock output pin with programmable
prescaler
Start-of-Frame signal
TX0RTS
TX1RTS
TX2RTS
4
5
6
4
5
7
2
3
5
I
I
I
Transmit buffer TXB0 request-to-send. General purpose digital input.
100 kinternal pull-up to V 100 kinternal pull-up to V
DD
DD
Transmit buffer TXB1 request-to-send. General purpose digital input.
100 kinternal pull-up to V 100 kinternal pull-up to V
DD
DD
Transmit buffer TXB2 request-to-send. General purpose digital input.
100 kinternal pull-up to V
100 kinternal pull-up to V
DD
DD
OSC2
OSC1
VSS
7
8
9
8
9
6
7
8
O
I
Oscillator output
—
External clock input
—
Oscillator input
10
P
Ground reference for logic and I/O
pins
RX1BF
RX0BF
10
11
11
12
9
O
O
Receive buffer RXB1 interrupt pin or
general purpose digital output
General purpose digital output
General purpose digital output
10
Receive buffer RXB0 interrupt pin or
general purpose digital output
INT
SCK
SI
12
13
14
15
16
17
18
—
13
14
11
12
O
I
Interrupt output pin
—
—
—
—
—
—
—
—
Clock input pin for SPI interface
Data input pin for SPI interface
Data output pin for SPI interface
Chip select input pin for SPI interface
Active-low device Reset input
Positive supply for logic and I/O pins
No internal connection
16
14
I
SO
17
15
O
I
CS
18
16
RESET
VDD
NC
19
17
I
20
18
P
—
6,15
4,13
Note:
Type Identification: I = Input; O = Output; P = Power
DS21801G-page 4
2003-2012 Microchip Technology Inc.
MCP2515
1.4
Transmit/Receive Buffers/Masks/
Filters
The MCP2515 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters. Figure 1-3
shows a block diagram of these buffers and their
connection to the protocol engine.
FIGURE 1-3:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
BUFFERS
Acceptance Mask
RXM1
Acceptance Filter
RXF2
A
Acceptance Mask
RXM0
Acceptance Filter
c
A
c
c
e
p
t
RXF3
c
TXB0
TXB1
TXB2
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
R
X
B
1
R
X
B
0
M
A
B
Identifier
Identifier
Message
Queue
Control
Transmit Byte Sequencer
Data Field
Data Field
PROTOCOL
ENGINE
Receive
Error
Counter
REC
TEC
Transmit
Error
Counter
ErrPas
BusOff
Transmit<7:0>
Shift<14:0>
Receive<7:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Protocol
Finite
SOF
State
CRC<14:0>
Machine
Bit
Timing
Logic
Transmit
Logic
Clock
Generator
TX
RX
Configuration
Registers
2003-2012 Microchip Technology Inc.
DS21801G-page 5
MCP2515
1.5.3
ERROR MANAGEMENT LOGIC
1.5
CAN Protocol Engine
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
1.5.1
PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.4
BIT TIMING LOGIC
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
1.5.2
CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
FIGURE 1-4:
CAN PROTOCOL ENGINE BLOCK DIAGRAM
TX
RX
Bit Timing Logic
SAM
Transmit Logic
REC
Receive
Sample<2:0>
Error Counter
TEC
StuffReg<5:0>
Transmit
ErrPas
Majority
Decision
Error Counter
BusOff
BusMon
Comparator
CRC<14:0>
Comparator
Protocol
FSM
SOF
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Receive<7:0>
Transmit<7:0>
RecData<7:0>
TrmData<7:0>
Rec/Trm Addr.
Interface to Standard Buffer
DS21801G-page 6
2003-2012 Microchip Technology Inc.
MCP2515
CAN frame will win arbitration due to the assertion of a
dominant lDE bit. Also, the SRR bit in an extended
CAN frame must be recessive to allow the assertion of
a dominant RTR bit by a node that is sending a
standard CAN remote frame.
2.0
CAN MESSAGE FRAMES
The MCP2515 supports standard data frames,
extended data frames and remote frames (standard
and extended), as defined in the CAN 2.0B
specification.
The SRR and lDE bits are followed by the remaining
18 bits of the identifier (Extended lD) and the remote
transmission request bit.
2.1
Standard Data Frame
The CAN standard data frame is shown in Figure 2-1.
As with all other frames, the frame begins with a Start-
Of-Frame (SOF) bit, which is of the dominant state and
allows hard synchronization of all nodes.
To enable standard and extended frames to be sent
across a shared network, the 29-bit extended message
identifier is split into 11-bit (Most Significant) and 18-bit
(Least Significant) sections. This split ensures that the
lDE bit can remain at the same bit position in both the
standard and extended frames.
The SOF is followed by the arbitration field, consisting
of 12 bits: the 11-bit identifier and the Remote
Transmission Request (RTR) bit. The RTR bit is used
to distinguish a data frame (RTR bit dominant) from a
remote frame (RTR bit recessive).
Following the arbitration field is the six-bit control field.
The first two bits of this field are reserved and must be
dominant. The remaining four bits of the control field
are the DLC, which specifies the number of data bytes
contained in the message.
Following the arbitration field is the control field,
consisting of six bits. The first bit of this field is the
Identifier Extension (IDE) bit, which must be dominant
to specify a standard frame. The following bit, Reserved
Bit Zero (RB0), is reserved and is defined as a dominant
bit by the CAN protocol. The remaining four bits of the
control field are the Data Length Code (DLC), which
specifies the number of bytes of data (0-8 bytes)
contained in the message.
The remaining portion of the frame (data field, CRC
field,
acknowledge
field,
end-of-frame
and
intermission) is constructed in the same way as a
standard data frame (see Section 2.1 “Standard Data
Frame”).
2.3
Remote Frame
After the control field, is the data field, which contains
any data bytes that are being sent, and is of the length
defined by the DLC (0-8 bytes).
Normally, data transmission is performed on an
autonomous basis by the data source node (e.g., a
sensor sending out a data frame). It is possible,
however, for a destination node to request data from
the source. To accomplish this, the destination node
sends a remote frame with an identifier that matches
the identifier of the required data frame. The
appropriate data source node will then send a data
frame in response to the remote frame request.
The Cyclic Redundancy Check (CRC) field follows the
data field and is used to detect transmission errors. The
CRC field consists of a 15-bit CRC sequence, followed
by the recessive CRC Delimiter bit.
The final field is the two-bit Acknowledge (ACK) field.
During the ACK Slot bit, the transmitting node sends
out a recessive bit. Any node that has received an
error-free frame acknowledges the correct reception of
the frame by sending back a dominant bit (regardless
of whether the node is configured to accept that
specific message or not). The recessive acknowledge
delimiter completes the acknowledge field and may not
be overwritten by a dominant bit.
There are two differences between a remote frame
(shown in Figure 2-3) and a data frame. First, the RTR
bit is at the recessive state and, second, there is no
data field. In the event of a data frame and a remote
frame with the same identifier being transmitted at the
same time, the data frame wins arbitration due to the
dominant RTR bit following the identifier. In this way,
the node that transmitted the remote frame receives
the desired data immediately.
2.2
Extended Data Frame
In the extended CAN data frame, shown in Figure 2-2,
the SOF bit is followed by the arbitration field, which
consists of 32 bits. The first 11 bits are the Most
Significant bits (MSb) (Base-lD) of the 29-bit identifier.
These 11 bits are followed by the Substitute Remote
Request (SRR) bit, which is defined to be recessive.
The SRR bit is followed by the lDE bit, which is
recessive to denote an extended CAN frame.
2.4
Error Frame
An error frame is generated by any node that detects a
bus error. An error frame, shown in Figure 2-4, consists
of two fields: an error flag field followed by an error
delimiter field. There are two types of error flag fields.
The type of error flag field sent depends upon the error
status of the node that detects and generates the error
flag field.
It should be noted that if arbitration remains unresolved
after transmission of the first 11 bits of the identifier, and
one of the nodes involved in the arbitration is sending
a standard CAN frame (11-bit identifier), the standard
2003-2012 Microchip Technology Inc.
DS21801G-page 7
MCP2515
2.4.1
ACTIVE ERRORS
2.5
Overload Frame
If an error-active node detects a bus error, the node
interrupts transmission of the current message by
generating an active error flag. The active error flag is
composed of six consecutive dominant bits. This bit
sequence actively violates the bit-stuffing rule. All other
stations recognize the resulting bit-stuffing error and, in
turn, generate error frames themselves, called error
echo flags.
An overload frame, shown in Figure 2-5, has the same
format as an active-error frame. An overload frame,
however, can only be generated during an interframe
space. In this way, an overload frame can be
differentiated from an error frame (an error frame is
sent during the transmission of a message). The
overload frame consists of two fields: an overload flag
followed by an overload delimiter. The overload flag
consists of six dominant bits followed by overload flags
generated by other nodes (and, as for an active error
flag, giving a maximum of twelve dominant bits). The
overload delimiter consists of eight recessive bits. An
overload frame can be generated by a node as a result
of two conditions:
The error flag field, therefore, consists of between six
and twelve consecutive dominant bits (generated by
one or more nodes). The error delimiter field (eight
recessive bits) completes the error frame. Upon
completion of the error frame, bus activity returns to
normal and the interrupted node attempts to resend the
aborted message.
1. The node detects a dominant bit during the
interframe space, an illegal condition.
Exception: The dominant bit is detected during
the third bit of IFS. In this case, the receivers will
interpret this as a SOF.
Note:
Error echo flags typically occur when a
localized disturbance causes one or more
(but not all) nodes to send an error flag.
The remaining nodes generate error flags
in response (echo) to the original error
flag.
2. Due to internal conditions, the node is not yet
able to begin reception of the next message. A
node may generate
a maximum of two
sequential overload frames to delay the start of
the next message.
2.4.2
PASSIVE ERRORS
If an error-passive node detects a bus error, the node
transmits an error-passive flag followed by the error
delimiter field. The error-passive flag consists of six
consecutive recessive bits. The error frame for an error-
passive node consists of 14 recessive bits. From this, it
follows that unless the bus error is detected by an error-
active node or the transmitting node, the message will
continue transmission because the error-passive flag
does not interfere with the bus.
Note:
Case 2 should never occur with the
MCP2515 due to very short internal
delays.
2.6
Interframe Space
The interframe space separates a preceding frame (of
any type) from a subsequent data or remote frame.
The interframe space is composed of at least three
recessive bits called the Intermission. This allows
nodes time for internal processing before the start of
the next message frame. After the intermission, the
bus line remains in the recessive state (bus idle) until
the next transmission starts.
If the transmitting node generates an error-passive flag,
it will cause other nodes to generate error frames due to
the resulting bit-stuffing violation. After transmission of
an error frame, an error-passive node must wait for six
consecutive recessive bits on the bus before attempting
to rejoin bus communications.
The error delimiter consists of eight recessive bits, and
allows the bus nodes to restart bus communications
cleanly after an error has occurred.
DS21801G-page 8
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 2-1:
STANDARD DATA FRAME
l e D K A C
t B i o l t k S A c
C D C e R l
D L C 0
D L C 3
R B
I D E
0
t i
e d B s e r R v
R R T
I D 0
I D 3
0
I D 1
e
r a m - F o - f a t r S t
2003-2012 Microchip Technology Inc.
DS21801G-page 9
MCP2515
FIGURE 2-2:
EXTENDED DATA FRAME
l e D K A C
t B i o l t k S A c
D e l C R C
D L C 0
D L C 3
0
1
R B
R B
s
r v e e d b R i t e s
R R T
0 D E I
7 1 D E I
E I D
R S R
0 I D
I D 3
0
I D 1
r a m - f F e O - t a t r S
DS21801G-page 10
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 2-3:
REMOTE FRAME
l e D K A C
t B i o l t S A c k
l e
C R C D
C 0 D L
C 3 D L
0
R B
s
r v e e d b R i t e s
1
R B
R R T
0 D E I
7 1 D E I
I D E
R S R
I D 0
3 I D
0 1 I D
e m a r F - O t f - r a t S
2003-2012 Microchip Technology Inc.
DS21801G-page 11
MCP2515
FIGURE 2-4:
ACTIVE ERROR FRAME
D L C 0
3
D L C
R B
I D E
0
t i B d
s e r R v e
R R T
I D 0
I D 3
0
I D 1
e m a r F - O t f - r a t S
DS21801G-page 12
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 2-5:
OVERLOAD FRAME
l e K D A C
B t o i k S A l c
t
C R C D e l
C 0 D L
C 3 D L
0
R B
E I D
R R T
I D 0
0
I D 1
e m a r F - O t f - r a t S
2003-2012 Microchip Technology Inc.
DS21801G-page 13
MCP2515
NOTES:
DS21801G-page 14
2003-2012 Microchip Technology Inc.
MCP2515
3.3
Initiating Transmission
3.0
3.1
MESSAGE TRANSMISSION
Transmit Buffers
In order to initiate message transmission, the
TXBnCTRL.TXREQ bit must be set for each buffer to
be transmitted. This can be accomplished by:
The MCP2515 implements three transmit buffers. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into the device memory map.
• Writing to the register via the SPI write command
• Sending the SPI RTS command
The first byte, TXBnCTRL, is a control register
associated with the message buffer. The information in
this register determines the conditions under which the
message will be transmitted and indicates the status of
the message transmission (see Register 3-2).
• Setting the TXnRTS pin low for the particular
transmit buffer(s) that are to be transmitted
If transmission is initiated via the SPI interface, the
TXREQ bit can be set at the same time as the TXP
priority bits.
Five bytes are used to hold the standard and extended
identifiers, as well as other message arbitration
information (see Register 3-4 through Register 3-7).
The last eight bytes are for the eight possible data
bytes of the message to be transmitted (see
Register 3-8).
When TXBnCTRL.TXREQ is set, the TXBnCTRL.ABTF,
TXBnCTRL.MLOA and TXBnCTRL.TXERR bits will be
cleared automatically.
Note:
Setting the TXBnCTRL.TXREQ bit does
not initiate a message transmission. It
merely flags a message buffer as being
ready for transmission. Transmission will
start when the device detects that the bus
is available.
At a minimum, the TXBnSIDH, TXBnSIDL and
TXBnDLC registers must be loaded. If data bytes are
present in the message, the TXBnDm registers must
also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the TXBnSIDL.EXIDE bit set.
Once the transmission has completed successfully, the
TXBnCTRL.TXREQ bit will be cleared, the
CANINTF.TXnIF bit will be set and an interrupt will be
generated if the CANINTE.TXnIE bit is set.
Prior to sending the message, the MCU must initialize
the CANINTE.TXInE bit to enable or disable the
generation of an interrupt when the message is sent.
If
the
message
transmission
fails,
the
TXBnCTRL.TXREQ will remain set. This indicates that
the message is still pending for transmission and one
of the following condition flags will be set:
Note:
The TXBnCTRL.TXREQ bit must be clear
(indicating the transmit buffer is not
pending transmission) before writing to
the transmit buffer.
• If the message started to transmit but encoun-
tered an error condition, the TXBnCTRL.TXERR
and the CANINTF.MERRF bits will be set and an
interrupt will be generated on the INT pin if the
CANINTE.MERRE bit is set
3.2
Transmit Priority
Transmit priority is a prioritization within the MCP2515
of the pending transmittable messages. This is
independent from, and not necessarily related to, any
prioritization implicit in the message arbitration scheme
built into the CAN protocol.
• If the message is lost, arbitration at the
TXBnCTRL.MLOA bit will be set
Note:
If
One-Shot
mode
is
enabled
(CANCTRL.OSM), the above conditions
will still exist. However, the TXREQ bit will
be cleared and the message will not
attempt transmission a second time.
Prior to sending the SOF, the priority of all buffers that
are queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. For
example, if transmit buffer 0 has a higher priority setting
than transmit buffer 1, buffer 0 will be sent first.
3.4
One-Shot Mode
If two buffers have the same priority setting, the buffer
with the highest buffer number will be sent first. For
example, if transmit buffer 1 has the same priority
setting as transmit buffer 0, buffer 1 will be sent first.
One-Shot mode ensures that a message will only
attempt to transmit one time. Normally, if a CAN
message loses arbitration, or is destroyed by an error
frame, the message is retransmitted. With One-Shot
mode enabled, a message will only attempt to transmit
one time, regardless of arbitration loss or error frame.
There are four levels of transmit priority. If
TXBnCTRL.TXP<1:0> for a particular message buffer
is set to 11, that buffer has the highest possible priority.
If TXBnCTRL.TXP<1:0> for a particular message buf-
fer is 00, that buffer has the lowest possible priority.
One-Shot mode is required to maintain time slots in
deterministic systems, such as TTCAN.
2003-2012 Microchip Technology Inc.
DS21801G-page 15
MCP2515
3.5
TXnRTS PINS
3.6
Aborting Transmission
The TXnRTS pins are input pins that can be configured
as:
The MCU can request to abort a message in a specific
message buffer by clearing the associated
TXBnCTRL.TXREQ bit.
• Request-to-send inputs, which provide an
alternative means of initiating the transmission of
a message from any of the transmit buffers
In addition, all pending messages can be requested to
be aborted by setting the CANCTRL.ABAT bit. This bit
MUST be reset (typically after the TXREQ bits have
been verified to be cleared) to continue transmitting
messages. The TXBnCTRL.ABTF flag will only be set
if the abort was requested via the CANCTRL.ABAT bit.
Aborting a message by resetting the TXREQ bit does
NOT cause the ABTF bit to be set.
• Standard digital inputs
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (see Register 3-3). The
TXRTSCTRL register can only be modified when the
MCP2515 is in Configuration mode (see Section 10.0
“Modes of Operation”). If configured to operate as a
request-to-send pin, the pin is mapped into the
respective TXBnCTRL.TXREQ bit for the transmit
buffer. The TXREQ bit is latched by the falling edge of
the TXnRTS pin. The TXnRTS pins are designed to
allow them to be tied directly to the RXnBF pins to
automatically initiate a message transmission when the
RXnBF pin goes low.
Note 1: Messages that were transmitting when
the abort was requested will continue to
transmit. If the message does not
successfully complete transmission (i.e.,
lost arbitration or was interrupted by an
error frame), it will then be aborted.
2: When One-Shot mode is enabled, if the
message is interrupted due to an error
frame or loss of arbitration, the
TXBnCTRL.ABTF bit will set.
The TXnRTS pins have internal pull-up resistors of
100 k (nominal).
DS21801G-page 16
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 3-1:
TRANSMIT MESSAGE FLOWCHART
Start
The message transmission
sequence begins when the
device determines that the
TXBnCTRL.TXREQ for any of
the transmit registers has been
set.
Are any
TXBnCTRL.TXREQ
No
bits = 1
?
Yes
Clearing the TxBnCTRL.TXREQ bit
Clear:
while it is set, or setting the CANC-
TRL.ABAT bit before the message
has started transmission, will abort
the message.
TXBnCTRL.ABTF
TXBnCTRL.MLOA
TXBnCTRL.TXERR
Is
is
No
No
CAN bus available
to start transmission?
TXBnCTRL.TXREQ=0
or CANCTRL.ABAT=1
?
Yes
Yes
Examine TXBnCTRL.TXP <1:0> to
Determine Highest Priority Message
Transmit Message
Message
Error
Message error
Was
No
or
Message Transmitted
Successfully?
Lost arbitration
?
Set
TxBnCTRL.TXERR
Yes
Lost
Arbitration
Clear TxBnCTRL.TXREQ
Yes
CANINTE.MEERE?
No
Yes
Set
TxBNCTRL.MLOA
Generate
Interrupt
CANINTE.TXnIE=1?
Generate
Interrupt
No
Set
Set
CANTINF.MERRF
CANTINF.TXnIF
The CANINTE.TXnIE bit
determines if an interrupt
should be generated when
a message is successfully
transmitted.
GOTO START
2003-2012 Microchip Technology Inc.
DS21801G-page 17
MCP2515
REGISTER 3-1:
TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER
(ADDRESS: 30h, 40h, 50h)
U-0
—
R-0
R-0
R-0
R/W-0
U-0
—
R/W-0
TXP1
R/W-0
TXP0
ABTF
MLOA
TXERR
TXREQ
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ABTF: Message Aborted Flag bit
1= Message was aborted
0= Message completed transmission successfully
bit 5
bit 4
bit 3
MLOA: Message Lost Arbitration bit
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERR: Transmission Error Detected bit
1= A bus error occurred while the message was being transmitted
0= No bus error occurred while the message was being transmitted
TXREQ: Message Transmit Request bit
1= Buffer is currently pending transmission
(MCU sets this bit to request message be transmitted - bit is automatically cleared when
the message is sent)
0= Buffer is not currently pending transmission
(MCU can clear this bit to request a message abort)
bit 2
Unimplemented: Read as ‘0’
bit 1-0
TXP<1:0>: Transmit Buffer Priority bits
11= Highest Message Priority
10= High Intermediate Message Priority
01= Low Intermediate Message Priority
00= Lowest Message Priority
DS21801G-page 18
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 3-2:
TXRTSCTRL – TXnRTS PIN CONTROL AND STATUS REGISTER
(ADDRESS: 0Dh)
U-0
—
U-0
R-x
R-x
R-x
R/W-0
R/W-0
R/W-0
—
B2RTS
B1RTS
B0RTS
B2RTSM
B1RTSM
B0RTSM
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
B2RTS: TX2RTS Pin State bit
- Reads state of TX2RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 4
bit 3
bit 2
bit 1
bit 0
B1RTS: TX1RTX Pin State bit
- Reads state of TX1RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
B0RTS: TX0RTS Pin State bit
- Reads state of TX0RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
B2RTSM: TX2RTS Pin mode bit
1= Pin is used to request message transmission of TXB2 buffer (on falling edge)
0= Digital input
B1RTSM: TX1RTS Pin mode bit
1= Pin is used to request message transmission of TXB1 buffer (on falling edge)
0= Digital input
B0RTSM: TX0RTS Pin mode bit
1= Pin is used to request message transmission of TXB0 buffer (on falling edge)
0= Digital input
REGISTER 3-3:
TXBnSIDH – TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 31h, 41h, 51h)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier bits
2003-2012 Microchip Technology Inc.
DS21801G-page 19
MCP2515
REGISTER 3-4:
TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 32h, 42h, 52h)
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
—
R/W-x
EXIDE
R/W-x
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID<2:0>: Standard Identifier bits
Unimplemented: Reads as ‘0’
bit 3
EXIDE: Extended Identifier Enable bit
1= Message will transmit extended identifier
0= Message will transmit standard identifier
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
REGISTER 3-5:
TXBnEID8 – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 33h, 43h, 53h)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier bits
REGISTER 3-6:
TXBnEID0 – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 34h, 44h, 54h)
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier bits
DS21801G-page 20
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 3-7:
TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE
(ADDRESS: 35h, 45h, 55h)
R/W-x
—
R/W-x
RTR
R/W-x
—
R/W-x
—
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Reads as ‘0’
RTR: Remote Transmission Request bit
1= Transmitted Message will be a Remote Transmit Request
0= Transmitted Message will be a Data Frame
bit 5-4
bit 3-0
Unimplemented: Reads as ‘0’
DLC<3:0>: Data Length Code bits
Sets the number of data bytes to be transmitted (0 to 8 bytes)
Note: It is possible to set the DLC to a value greater than eight, however only eight bytes are
transmitted
REGISTER 3-8:
TXBnDm – TRANSMIT BUFFER n DATA BYTE m
(ADDRESS: 36h - 3Dh, 46h - 4Dh, 56h - 5Dh)
R/W-x
TXBnDm7
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TXBnDm6
TXBnDm5
TXBnDm4
TXBnDm3
TXBnDm2
TXBnDm1
TXBnDm0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Bytes m
2003-2012 Microchip Technology Inc.
DS21801G-page 21
MCP2515
NOTES:
DS21801G-page 22
2003-2012 Microchip Technology Inc.
MCP2515
4.2
Receive Priority
4.0
4.1
MESSAGE RECEPTION
Receive Message Buffering
RXB0, the higher priority buffer, has one mask and two
message acceptance filters associated with it. The
received message is applied to the mask and filters for
RXB0 first.
The MCP2515 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) that acts as
a third receive buffer (see Figure 4-2).
RXB1 is the lower priority buffer, with one mask and
four acceptance filters associated with it.
In addition to the message being applied to the RB0
mask and filters first, the lower number of acceptance
filters makes the match on RXB0 more restrictive and
implies a higher priority for that buffer.
4.1.1
MESSAGE ASSEMBLY BUFFER
Of the three receive buffers, the MAB is always
committed to receiving the next message from the bus.
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffers (see
Register 4-4 to Register 4-9) only if the acceptance
filter criteria is met.
When a message is received, bits <3:0> of the
RXBnCTRL register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
4.1.2
RXB0 AND RXB1
4.2.1
ROLLOVER
The remaining two receive buffers, called RXB0 and
RXB1, can receive a complete message from the
protocol engine via the MAB. The MCU can access one
buffer, while the other buffer is available for message
Additionally, the RXB0CTRL register can be configured
such that, if RXB0 contains a valid message and
another valid message is received, an overflow error
will not occur and the new message will be moved into
RXB1, regardless of the acceptance criteria of RXB1.
reception, or for holding
message.
a previously received
4.2.2
RXM BITS
Note:
The entire content of the MAB is moved
into the receive buffer once a message is
accepted. This means, that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is
overwritten with the MAB contents.
Therefore, the contents of all registers in
the buffer must be assumed to have been
modified when any message is received.
The RXBnCTRL.RXM bits set special receive modes.
Normally, these bits are cleared to 00 to enable
reception of all valid messages as determined by the
appropriate acceptance filters. In this case, the
determination of whether or not to receive standard or
extended messages is determined by the
RFXnSIDL.EXIDE bit in the acceptance filter register.
If the RXBnCTRL.RXM bits are set to 01 or 10, the
receiver will only accept messages with standard or
extended identifiers, respectively. If an acceptance
filter has the RFXnSIDL.EXIDE bit set such that it does
not correspond with the RXBnCTRL.RXM mode, that
acceptance filter is rendered useless. These two
modes of RXBnCTRL.RXM bits can be used in
systems where it is known that only standard or
extended messages will be on the bus.
4.1.3
RECEIVE FLAGS/INTERRUPTS
When a message is moved into either of the receive
buffers, the appropriate CANINTF.RXnIF bit is set. This
bit must be cleared by the MCU in order to allow a new
message to be received into the buffer. This bit
provides a positive lockout to ensure that the MCU has
finished with the message before the MCP2515
attempts to load a new message into the receive buffer.
If the RXBnCTRL.RXM bits are set to 11, the buffer will
receive all messages, regardless of the values of the
acceptance filters. Also, if a message has an error
before the EOF, that portion of the message assembled
in the MAB before the error frame will be loaded into the
buffer. This mode has some value in debugging a CAN
system and would not be used in an actual system
environment.
If the CANINTE.RXnIE bit is set, an interrupt will be
generated on the INT pin to indicate that a valid
message has been received. In addition, the
associated RXnBF pin will drive low if configured as a
receive buffer full pin. See Section 4.4 “RX0BF and
RX1BF Pins” for details.
2003-2012 Microchip Technology Inc.
DS21801G-page 23
MCP2515
4.4.1
DISABLED
4.3
Start-of-Frame Signal
The RXBnBF pins can be disabled to the high-
impedance state by clearing BFPCTRL.BnBFE.
If enabled, the Start-Of-Frame signal is generated on
the SOF pin at the beginning of each CAN message
detected on the RXCAN pin.
4.4.2
CONFIGURED AS BUFFER FULL
The RXCAN pin monitors an idle bus for a recessive-
to-dominant edge. If the dominant condition remains
until the sample point, the MCP2515 interprets this as
a SOF and a SOF pulse is generated. If the dominant
condition does not remain until the sample point, the
MCP2515 interprets this as a glitch on the bus and no
SOF signal is generated. Figure 4-1 illustrates SOF
signalling and glitch-filtering.
The RXBnBF pins can be configured to act as either
buffer full interrupt pins or as standard digital outputs.
Configuration and status of these pins is available via
the BFPCTRL register (Register 4-3). When set to
operate in Interrupt mode (by setting BFPCTRL.BxBFE
and BFPCTRL.BxBFM bits), these pins are active-low
and are mapped to the CANINTF.RXnIF bit for each
receive buffer. When this bit goes high for one of the
receive buffers (indicating that a valid message has
been loaded into the buffer), the corresponding
RXBnBF pin will go low. When the CANINTF.RXnIF bit
is cleared by the MCU, the corresponding interrupt pin
will go to the logic-high state until the next message is
loaded into the receive buffer.
As with One-Shot mode, one use for SOF signaling is
for TTCAN-type systems. In addition, by monitoring
both the RXCAN pin and the SOF pin, an MCU can
detect early physical bus problems by detecting small
glitches before they affect the CAN communications.
4.4
RX0BF and RX1BF Pins
In addition to the INT pin, which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF and RX1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively. The pins have three
different configurations (Register 4-1):
1. Disabled
2. Buffer Full Interrupt
3. Digital Output
FIGURE 4-1:
START-OF-FRAME SIGNALING
Normal SOF Signaling
START-OF-FRAME BIT
ID BIT
Sample
Point
RXCAN
SOF
Glitch-Filtering
EXPECTED START-OF-FRAME BIT
Sample
Point
Expected
BUS IDLE
RXCAN
SOF
DS21801G-page 24
2003-2012 Microchip Technology Inc.
MCP2515
4.4.3
CONFIGURED AS DIGITAL OUTPUT
TABLE 4-1:
CONFIGURING RXNBF PINS
When used as digital outputs, the BFPCTRL.BxBFM bit
must be cleared and BFPCTRL.BnBFE must be set for
the associated buffer. In this mode, the state of the pin
is controlled by the BFPCTRL.BnBFS bits. Writing a ‘1’
to the BnBFS bit will cause a high level to be driven on
the associated buffer full pin, while a ‘0’ will cause the
pin to drive low. When using the pins in this mode, the
state of the pin should be modified only by using the Bit
Modify SPI command to prevent glitches from
occurring on either of the buffer full pins.
BnBFE BnBFM BnBFS
Pin Status
0
1
1
1
X
1
0
0
X
X
0
1
Disabled, high-impedance
Receive buffer interrupt
Digital output = 0
Digital output = 1
FIGURE 4-2:
Note:
RECEIVE BUFFER BLOCK DIAGRAM
Messages received in the MAB are intially
applied to the mask and filters of RXB0. In
addition, only one filter match occurs (e.g.,
if the message matches both RXF0 and
RXF2, the match will be for RXF0 and the
message will be moved into RXB0).
Acceptance Mask
RXM1
Acceptance Filter
RXF2
Acceptance Mask
RXM0
Acceptance Filter
RXF3
A
c
c
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
A
c
Acceptance Filter
RXF1
Acceptance Filter
RXF5
c
e
p
t
R
X
B
0
R
X
B
1
M
A
B
Identifier
Identifier
Data Field
Data Field
2003-2012 Microchip Technology Inc.
DS21801G-page 25
MCP2515
FIGURE 4-3:
RECEIVE FLOW FLOWCHART
Start
Detect
Start of
No
Message?
Yes
Begin Loading Message into
Message Assembly Buffer (MAB)
Valid
Message
Received?
Generate
Error
Frame
No
Yes
Meets
a filter criteria
for RXB0?
Meets
a filter criteria
for RXB1?
No
Yes
Yes
No
Go to Start
Determines if the receive
register is empty and able
to accept a new message
Determines if RXB0 can roll
over into RXB1, if it is full.
Is
Is
No
Yes
CANINTF.RX0IF = 0?
RXB0CTRL.BUKT = 1?
No
Yes
Is
No
Generate Overflow Error:
Set EFLG.RX0OVR
Generate Overflow Error:
Set EFLG.RX1OVR
Move message into RXB0
CANINTF.RX1IF = 0?
Set CANINTF.RX0IF = 1
Yes
Move message into RXB1
No
Is
Set RXB0CTRL.FILHIT <0>
according to which filter criteria
CANINTE.ERRIE = 1?
Set CANINTF.RX1IF = 1
Yes
Set RXB0CTRL.FILHIT <2:0>
according to which filter criteria
was met
Generate
Interrupt on INT
Go to Start
Yes
Yes
Generate
Interrupt on INT
CANINTE.RX1IE = 1?
CANINTE.RX0IE = 1?
RXB1
RXB0
Set CANSTAT <3:0> accord-
ing to which receive buffer
the message was loaded into
No
No
Are
Are
Yes
Yes
BFPCTRL.B0BFM = 1
BFPCTRL.B1BFM =
and
BF1CTRL.B1BFE =
1
Set RXBF0
Pin = 0
Set RXBF1
Pin = 0
and
BF1CTRL.B0BFE = 1?
1?
No
No
DS21801G-page 26
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 4-1:
RXB0CTRL – RECEIVE BUFFER 0 CONTROL
(ADDRESS: 60h)
U-0
—
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
R/W-0
BUKT
R-0
R-0
RXRTR
BUKT1
FILHIT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
RXM<1:0>: Receive Buffer Operating mode bits
11= Turn mask/filters off; receive any message
10= Receive only valid messages with extended identifiers that meet filter criteria
01= Receive only valid messages with standard identifiers that meet filter criteria. Extended ID filter
registers RXFnEID8:RXFnEID0 are ignored for the messages with standard IDs.
00= Receive all valid messages using either standard or extended identifiers that meet filter criteria.
Extended ID filter registers RXFnEID8:RXFnEID0 are applied to first two bytes of data in the
messages with standard IDs.
bit 4
bit 3
Unimplemented: Read as ‘0’
RXRTR: Received Remote Transfer Request bit
1= Remote Transfer Request Received
0= No Remote Transfer Request Received
bit 2
BUKT: Rollover Enable bit
1= RXB0 message will rollover and be written to RXB1 if RXB0 is full
0= Rollover disabled
bit 1
bit 0
BUKT1: Read-only Copy of BUKT bit (used internally by the MCP2515)
FILHIT0: Filter Hit bit – indicates which acceptance filter enabled reception of message
1= Acceptance Filter 1 (RXF1)
0= Acceptance Filter 0 (RXF0)
Note:
If a rollover from RXB0 to RXB1 occurs, the FILHIT bit will reflect the filter that accepted
the message that rolled over.
2003-2012 Microchip Technology Inc.
DS21801G-page 27
MCP2515
REGISTER 4-2:
RXB1CTRL – RECEIVE BUFFER 1 CONTROL
(ADDRESS: 70h)
U-0
—
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
R-0
R-0
R-0
RXRTR
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
RXM<1:0>: Receive Buffer Operating mode bits
11= Turn mask/filters off; receive any message
10= Receive only valid messages with extended identifiers that meet filter criteria
01= Receive only valid messages with standard identifiers that meet filter criteria
00= Receive all valid messages using either standard or extended identifiers that meet filter criteria
bit 4
bit 3
Unimplemented: Read as ‘0’
RXRTR: Received Remote Transfer Request bit
1= Remote Transfer Request Received
0= No Remote Transfer Request Received
bit 2-0
FILHIT<2:0>: Filter Hit bits - indicates which acceptance filter enabled reception of message
101= Acceptance Filter 5 (RXF5)
100= Acceptance Filter 4 (RXF4)
011= Acceptance Filter 3 (RXF3)
010= Acceptance Filter 2 (RXF2)
001= Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)
000= Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)
DS21801G-page 28
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 4-3:
BFPCTRL – RXnBF PIN CONTROL AND STATUS
(ADDRESS: 0Ch)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
B1BFS
B0BFS
B1BFE
B0BFE
B1BFM
B0BFM
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
B1BFS: RX1BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when RX1BF is configured as interrupt pin
B0BFS: RX0BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when RX0BF is configured as interrupt pin
B1BFE: RX1BF Pin Function Enable bit
bit 4
bit 3
1= Pin function enabled, operation mode determined by B1BFM bit
0= Pin function disabled, pin goes to high-impedance state
bit 2
bit 1
bit 0
B0BFE: RX0BF Pin Function Enable bit
1= Pin function enabled, operation mode determined by B0BFM bit
0= Pin function disabled, pin goes to high-impedance state
B1BFM: RX1BF Pin Operation mode bit
1= Pin is used as interrupt when valid message loaded into RXB1
0= Digital Output mode
B0BFM: RX0BF Pin Operation mode bit
1= Pin is used as interrupt when valid message loaded into RXB0
0= Digital Output mode
REGISTER 4-4:
RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 61h, 71h)
R-x
SID10
bit 7
R-x
R-x
R-x
R-x
R-x
R-x
R-x
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier bits
These bits contain the eight Most Significant bits of the Standard Identifier for the received message
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MCP2515
REGISTER 4-5:
RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 62h, 72h)
R-x
SID2
R-x
SID1
R-x
R-x
R-x
IDE
U-0
—
R-x
R-x
SID0
SRR
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID<2:0>: Standard Identifier bits
These bits contain the three Least Significant bits of the Standard Identifier for the received message
SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘0’)
1= Standard Frame Remote Transmit Request Received
0= Standard Data Frame Received
bit 3
IDE: Extended Identifier Flag bit
This bit indicates whether the received message was a Standard or an Extended Frame
1= Received message was an Extended Frame
0= Received message was a Standard Frame
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
These bits contain the two Most Significant bits of the Extended Identifier for the received message
REGISTER 4-6:
RXBnEID8 – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 63h, 73h)
R-x
EID15
bit 7
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier bits
These bits hold bits 15 through 8 of the Extended Identifier for the received message
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MCP2515
REGISTER 4-7:
RXBnEID0 – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 64h, 74h)
R-x
EID7
R-x
EID6
R-x
R-x
R-x
R-x
R-x
R-x
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier bits
These bits hold the Least Significant eight bits of the Extended Identifier for the received message
REGISTER 4-8:
RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE
(ADDRESS: 65h, 75h)
R-x
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Reads as ‘0’
RTR: Extended Frame Remote Transmission Request bit
(valid only when RXBnSIDL.IDE = 1)
1= Extended Frame Remote Transmit Request Received
0= Extended Data Frame Received
bit 5
RB1: Reserved Bit 1
bit 4
RB0: Reserved Bit 0
bit 3-0
DLC<3:0>: Data Length Code bits
Indicates number of data bytes that were received
REGISTER 4-9:
RXBnDM – RECEIVE BUFFER n DATA BYTE M
(ADDRESS: 66h - 6Dh, 76h - 7Dh)
R-x
RBnD7
bit 7
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RBnD6
RBnD5
RBnD4
RBnD3
RBnD2
RBnD1
RBnD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
RBnD7:RBnD0: Receive Buffer n Data Field Bytes m
Eight bytes containing the data bytes for the received message
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identifier is compared to the masks and filters to deter-
mine if the message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, that bit will automatically be accepted,
regardless of the filter bit.
4.5
Message Acceptance Filters and
Masks
The message acceptance filters and masks are used to
determine if a message in the message assembly buf-
fer should be loaded into either of the receive buffers
(see Figure 4-5). Once a valid message has been
received into the MAB, the identifier fields of the mes-
sage are compared to the filter values. If there is a
match, that message will be loaded into the appropriate
receive buffer.
TABLE 4-2:
FILTER/MASK TRUTH TABLE
Message
Mask Bit n Filter Bit n Identifier
bit
Accept or
Reject bit n
0
X
X
0
1
0
1
Accept
Accept
Reject
Reject
Accept
4.5.1
DATA BYTE FILTERING
1
0
When receiving standard data frames (11-bit identifier),
the MCP2515 automatically applies 16 bits of masks
and filters normally associated with extended
identifiers to the first 16 bits of the data field (data bytes
0 and 1). Figure 4-4 illustrates how masks and filters
apply to extended and standard data frames.
1
1
0
1
1
1
Note:
X= don’t care
Data byte filtering reduces the load on the MCU when
implementing Higher Layer Protocols (HLPs) that filter
on the first data byte (e.g., DeviceNet™).
As shown in the receive buffers block diagram
(Figure 4-2), acceptance filters RXF0 and RXF1 (and
filter mask RXM0) are associated with RXB0. Filters
RXF2, RXF3, RXF4, RXF5 and mask RXM1 are
associated with RXB1.
4.5.2
FILTER MATCHING
The filter masks (see Register 4-14 through
Register 4-17) are used to determine which bits in the
identifier are examined with the filters. A truth table is
shown in Table 4-2 that indicates how each bit in the
FIGURE 4-4:
MASKS AND FILTERS APPLY TO CAN FRAMES
Extended Frame
ID10
ID0 EID17
EID0
Masks and Filters apply to the entire 29-bit ID field
Standard Data Frame
ID10
ID0 *
Data Byte 0
Data Byte 1
11-bit ID Standard frame
16-bit data filtering *
* The two MSb (EID17 and EID16) mask and filter bits are not used.
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MCP2515
If the BUKT bit is clear, there are six codes
corresponding to the six filters. If the BUKT bit is set,
there are six codes corresponding to the six filters, plus
two additional codes corresponding to RXF0 and RXF1
filters that roll over into RXB1.
4.5.3
FILHIT BITS
Filter matches on received messages can be
determined by the FILHIT bits in the associated
RXBnCTRL register. RXB0CTRL.FILHIT0 for buffer 0
and RXB1CTRL.FILHIT<2:0> for buffer 1.
The three FILHIT bits for receive buffer 1 (RXB1) are
coded as follows:
4.5.4
MULTIPLE FILTER MATCHES
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest
numbered filter that matched. For example, if filter
RXF2 and filter RXF4 match, FILHIT will be loaded with
the value for RXF2. This essentially prioritizes the
acceptance filters with a lower-numbered filter having
higher priority. Messages are compared to filters in
ascending order of filter number. This also ensures that
the message will only be received into one buffer. This
implies that RXB0 has a higher priority than RXB1.
- 101= Acceptance Filter 5 (RXF5)
- 100= Acceptance Filter 4 (RXF4)
- 011= Acceptance Filter 3 (RXF3)
- 010= Acceptance Filter 2 (RXF2)
- 001= Acceptance Filter 1 (RXF1)
- 000= Acceptance Filter 0 (RXF0)
Note: 000and 001can only occur if the BUKT bit
in RXB0CTRL is set, allowing RXB0
messages to roll over into RXB1.
4.5.5
CONFIGURING THE MASKS AND
FILTERS
RXB0CTRL contains two copies of the BUKT bit and
the FILHIT<0> bit.
The mask and filter registers can only be modified
when the MCP2515 is in Configuration mode (see
Section 10.0 “Modes of Operation”).
The coding of the BUKT bit enables these three bits to
be used similarly to the RXB1CTRL.FILHIT bits and to
distinguish a hit on filter RXF0 and RXF1 in either
RXB0 or after a roll over into RXB1.
Note: The mask and filter registers read all '0'
when in any mode except Configuration
mode.
- 111= Acceptance Filter 1 (RXB1)
- 110= Acceptance Filter 0 (RXB1)
- 001= Acceptance Filter 1 (RXB0)
- 000= Acceptance Filter 0 (RXB0)
FIGURE 4-5:
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
Acceptance Mask Register
RXFn0
RXMn0
RXMn1
RxRqst
RXFn1
RXFnn
RXMnn
Message Assembly Buffer
Identifier
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REGISTER 4-10: RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH
(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier Filter bits
These bits hold the filter bits to be applied to bits <10:3> of the Standard Identifier portion of a received
message
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
REGISTER 4-11: RXFnSIDL – FILTER n STANDARD IDENTIFIER LOW
(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Filter bits
These bits hold the filter bits to be applied to bits <2:0> of the Standard Identifier portion of a received
message
bit 4
bit 3
Unimplemented: Reads as ‘0’
EXIDE: Extended Identifier Enable bit
1= Filter is applied only to Extended Frames
0= Filter is applied only to Standard Frames
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Filter bits
These bits hold the filter bits to be applied to bits <17:16> of the Extended Identifier portion of a
received message
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
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REGISTER 4-12: RXFnEID8 – FILTER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a received
message or to byte 0in received data if corresponding RXM = 00and EXIDE = 0
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
REGISTER 4-13: RXFnEID0 – FILTER n EXTENDED IDENTIFIER LOW
(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <7:0> of the Extended Identifier portion of a received
message or to byte 1in received data if corresponding RXM = 00and EXIDE = 0.
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
REGISTER 4-14: RXMnSIDH – MASK n STANDARD IDENTIFIER HIGH
(ADDRESS: 20h, 24h)
R/W-0
SID10
R/W-0
SID9
R/W-0
SID8
R/W-0
SID7
R/W-0
SID6
R/W-0
SID5
R/W-0
SID4
R/W-0
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits <10:3> of the Standard Identifier portion of a received
message
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
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MCP2515
REGISTER 4-15: RXMnSIDL – MASK n STANDARD IDENTIFIER LOW
(ADDRESS: 21h, 25h)
R/W-0
SID2
R/W-0
SID1
R/W-0
SID0
U-0
—
U-0
—
U-0
—
R/W-0
EID17
R/W-0
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a received
message
bit 4-2
bit 1-0
Unimplemented: Reads as ‘0’
EID<17:16>: Extended Identifier Mask bits
These bits hold the mask bits to be applied to bits <17:16> of the Extended Identifier portion of a
received message
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
\
REGISTER 4-16: RXMnEID8 – MASK n EXTENDED IDENTIFIER HIGH
(ADDRESS: 22h, 26h)
R/W-0
EID15
R/W-0
EID14
R/W-0
EID13
R/W-0
EID12
R/W-0
EID11
R/W-0
EID10
R/W-0
EID9
R/W-0
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a received
message. If corresponding RXM = 00and EXIDE = 0, these bits are applied to byte 0in received data
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
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REGISTER 4-17: RXMnEID0 – MASK n EXTENDED IDENTIFIER LOW
(ADDRESS: 23h, 27h)
R/W-0
EID7
R/W-0
EID6
R/W-0
EID5
R/W-0
EID4
R/W-0
EID3
R/W-0
EID2
R/W-0
EID1
R/W-0
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier Mask bits
These bits hold the filter bits to be applied to bits <7:0> of the Extended Identifier portion of a received
message. If corresponding RXM = 00and EXIDE = 0, these bits are applied to byte 1in received data.
Note:
The mask and filter registers read all '0' when in any mode except Configuration mode.
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NOTES:
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MCP2515
5.1
The CAN Bit TIme
5.0
BIT TIMING
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the Baud
Rate Prescaler and number of time quanta in each
segment.
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non Return to
Zero (NRZ) coding, which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission times may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data
transmission edges to synchronize and maintain the
receiver clock. Since the data is NRZ-coded, it is
necessary to include bit-stuffing to ensure that an edge
occurs at least every six bit times to maintain the Digital
Phase Lock Loop (DPLL) synchronization.
The CAN bit time is made up of non-overlapping
segments. Each of these segments are made up of
integer units called Time Quanta (TQ), explained later
in this data sheet. The Nominal Bit Rate (NBR) is
defined in the CAN specification as the number of bits
per second transmitted by an ideal transmitter with no
resynchronization. It can be described with the
equation:
The bit timing of the MCP2515 is implemented using a
DPLL that is configured to synchronize to the incoming
data, as well as provide the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time,
called the Time Quanta (TQ).
EQUATION 5-1:
1
tbit
NBR = f
= ------
bit
Bus timing functions executed within the bit time frame
(such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning) are defined by the programmable bit timing
logic of the DPLL.
Nominal Bit Time
The Nominal Bit Time (NBT) (tbit) is made up of non-
overlapping segments (Figure 5-1). Therefore, the
NBT is the summation of the following segments:
t
= t
+ t
+ t
+ t
bit
SyncSeg
PropSeg PS1 PS2
Associated with the NBT are the sample point,
Synchronization Jump Width (SJW) and Information
Processing Time (IPT), which are explained later.
SYNCHRONIZATION SEGMENT
The Synchronization Segment (SyncSeg) is the first
segment in the NBT and is used to synchronize the
nodes on the bus. Bit edges are expected to occur
within the SyncSeg. This segment is fixed at 1 TQ.
FIGURE 5-1:
CAN BIT TIME SEGMENTS
SyncSeg
PropSeg
PhaseSeg1 (PS1)
PhaseSeg2 (PS2)
Sample
Point
Nominal Bit Time (NBT), tbit
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Therefore:
PROPAGATION SEGMENT
The Propagation Segment (PropSeg) exists to
compensate for physical delays between nodes. The
propagation delay is defined as twice the sum of the
signal’s propagation time on the bus line, including the
delays associated with the bus driver. The PropSeg is
programmable from 1-8 TQ.
PS2
= IPT = 2TQ
min
SYNCHRONIZATION JUMP WIDTH
The Synchronization Jump Width (SJW) adjusts the bit
clock as necessary by 1-4 TQ (as configured) to
maintain synchronization with the transmitted
message. Synchronization is covered in more detail
later in this data sheet.
PHASE SEGMENT 1 (PS1) AND PHASE
SEGMENT 2 (PS2)
The two phase segments, PS1 and PS2, are used to
compensate for edge phase errors on the bus. PS1 can
be lengthened (or PS2 shortened) by resyncronization.
PS1 is programmable from 1-8 TQ and PS2 is
programmable from 2-8 TQ.
Time Quantum
Each of the segments that make up a bit time are made
up of integer units called Time Quanta (TQ). The length
of each Time Quantum is based on the oscillator period
(tOSC). The base TQ equals twice the oscillator period.
Figure 5-2 shows how the bit period is derived from
TOSC and TQ. The TQ length equals one TQ clock
period (tBRPCLK), which is programmable using a
programmable prescaler, called the Baud Rate
Prescaler (BRP). This is illustrated in the following
equation:
SAMPLE POINT
The sample point is the point in the bit time at which the
logic level is read and interpreted. The sample point is
located at the end of PS1. The exception to this rule is
if the sample mode is configured to sample three times
per bit. In this case, while the bit is still sampled at the
end of PS1, two additional samples are taken at one-
half TQ intervals prior to the end of PS1, with the value
of the bit being determined by a majority decision.
EQUATION 5-2:
INFORMATION PROCESSING TIME
2 BRP
TQ = 2 BRP T
= ------------------
OSC
The Information Processing Time (IPT) is the time
required for the logic to determine the bit level of a
sampled bit. The IPT begins at the sample point, is
measured in TQ and is fixed at 2 TQ for the Microchip
CAN module. Since PS2 also begins at the sample
point and is the last segment in the bit time, it is
required that the PS2 minimum is not less than the IPT.
F
OSC
Where: BRP equals the configuration as shown in
Register 5-1.
FIGURE 5-2:
TQ AND THE BIT PERIOD
tOSC
TBRPCLK
Sync
(fixed)
PropSeg
(Programmable)
PS1
(Programmable)
PS2
(Programmable)
tBIT
TQ
(tTQ)
CAN Bit Time
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5.2.2.2
No Phase Error (e = 0)
5.2
Synchronization
If the magnitude of the phase error is less than or equal
to the programmed value of the SJW, the effect of a
resynchronization is the same as that of a hard
synchronization.
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. Synchronization is
the process by which the DPLL function is
implemented.
5.2.2.3
Positive Phase Error (e > 0)
If the magnitude of the phase error is larger than the
SJW and, if the phase error is positive, PS1 is
lengthened by an amount equal to the SJW.
When an edge in the transmitted data is detected, the
logic will compare the location of the edge to the
expected time (SyncSeg). The circuit will then adjust
the values of PS1 and PS2 as necessary.
5.2.2.4
Negative Phase Error (e < 0)
There are two mechanisms used for synchronization:
If the magnitude of the phase error is larger than the
resynchronization jump width and the phase error is
negative, PS2 is shortened by an amount equal to the
SJW.
1. Hard synchronization
2. Resynchronization
5.2.1
HARD SYNCHRONIZATION
5.2.3
SYNCHRONIZATION RULES
Hard synchronization is only performed when there is a
recessive-to-dominant edge during a BUS IDLE
condition, indicating the start of a message. After hard
synchronization, the bit time counters are restarted with
SyncSeg.
1. Only recessive-to-dominant edges will be used
for synchronization.
2. Only one synchronization within one bit time is
allowed.
Hard synchronization forces the edge that has
occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
3. An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
4. A transmitting node will not resynchronize on a
positive phase error (e > 0).
5.2.2
RESYNCHRONIZATION
5. If the absolute magnitude of the phase error is
greater than the SJW, the appropriate phase
segment will adjust by an amount equal to the
SJW.
As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthening or shortening of the phase buffer segments
has an upper-bound, given by the Synchronization
Jump Width (SJW).
The value of the SJW will be added to PS1 or
subtracted from PS2 (see Figure 5-3). The SJW
represents the loop filtering of the DPLL. The SJW is
programmable between 1 TQ and 4 TQ.
5.2.2.1
Phase Errors
The NRZ bit coding method does not encode a clock
into the message. Clocking information will only be
derived from recessive-to-dominant transitions. The
property which states that only a fixed maximum
number of successive bits have the same value (bit-
stuffing) ensures resynchronization to the bit stream
during a frame.
The phase error of an edge is given by the position of
the edge relative to SyncSeg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
• e = 0if the edge lies within SYNCSEG
• e > 0if the edge lies before the SAMPLE POINT
(TQ is added to PS1)
• e < 0if the edge lies after the SAMPLE POINT of
the previous bit (TQ is subtracted from PS2)
2003-2012 Microchip Technology Inc.
DS21801G-page 41
MCP2515
FIGURE 5-3:
SYNCHRONIZING THE BIT TIME
Input Signal (e = 0)
PhaseSeg2 (PS2)
SJW (PS2)
PropSeg
SJW (PS1)
PhaseSeg1 (PS1)
SyncSeg
Sample
Point
Nominal Bit Time (NBT)
No Resynchronization (e = 0)
Input Signal
(e > 0)
PhaseSeg2 (PS2)
SJW (PS2)
PropSeg
SJW (PS1)
PhaseSeg1 (PS1)
SyncSeg
Sample
Point
Nominal Bit Time (NBT)
Actual Bit Time
Resynchronization to a Slower Transmitter (e > 0)
Input Signal (e < 0)
PhaseSeg2 (PS2)
PropSeg
SJW (PS1)
PhaseSeg1 (PS1)
SyncSeg
SJW (PS2)
Sample
Point
Nominal Bit Time (NBT)
Actual Bit Time
Resynchronization to a Faster Transmitter (e < 0)
DS21801G-page 42
2003-2012 Microchip Technology Inc.
MCP2515
5.3
Programming Time Segments
5.5
Bit Timing Configuration
Registers
Some requirements for programming of the time
segments:
The configuration registers (CNF1, CNF2, CNF3)
control the bit timing for the CAN bus interface. These
registers can only be modified when the MCP2515 is in
Configuration mode (see Section 10.0 “Modes of
Operation”).
• PropSeg + PS1 >= PS2
• PropSeg + PS1 >= TDELAY
• PS2 > SJW
For example, assuming that a 125 kHz CAN baud rate
with FOSC = 20 MHz is desired:
5.5.1
CNF1
TOSC
=
50 ns, choose BRP<5:0> = 04h, then
The BRP<5:0> bits control the Baud Rate Prescaler.
These bits set the length of TQ relative to the OSC1
input frequency, with the minimum TQ length being
TQ = 500 ns. To obtain 125 kHz, the bit time must be 16
TQ.
2 TOSC (when BRP<5:0>
SJW<1:0> bits select the SJW in terms of number of
TQs.
=
‘b000000’). The
Typically, the sampling of the bit should take place at
about 60-70% of the bit time, depending on the system
parameters. Also, typically, the TDELAY is 1-2 TQ.
SyncSeg = 1 TQ and PropSeg = 2 TQ. So setting
PS1 = 7 TQ would place the sample at 10 TQ after the
transition. This would leave 6 TQ for PS2.
5.5.2
CNF2
The PRSEG<2:0> bits set the length (in TQ’s) of the
propagation segment. The PHSEG1<2:0> bits set the
length (in TQ’s) of PS1.
Since PS2 is 6, according to the rules, SJW could be a
maximum of 4 TQ. However, a large SJW is typically
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. So a SJW of 1 is usually enough.
The SAM bit controls how many times the RXCAN pin
is sampled. Setting this bit to a ‘1’ causes the bus to be
sampled three times: twice at TQ/2 before the sample
point and once at the normal sample point (which is at
the end of PS1). The value of the bus is determined to
be the majority sampled. If the SAM bit is set to a ‘0’,
the RXCAN pin is sampled only once at the sample
point.
5.4
Oscillator Tolerance
The bit timing requirements allow ceramic resonators
to be used in applications with transmission rates of up
to 125 kbit/sec as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
The BTLMODE bit controls how the length of PS2 is
determined. If this bit is set to a ‘1’, the length of PS2 is
determined by the PHSEG2<2:0> bits of CNF3 (see
Section 5.5.3 “CNF3”). If the BTLMODE bit is set to a
‘0’, the length of PS2 is greater than that of PS1 and the
information processing time (which is fixed at 2 TQ for
the MCP2515).
5.5.3
CNF3
The PHSEG2<2:0> bits set the length (in TQ’s) of PS2,
if the CNF2.BTLMODE bit is set to a ‘1’. If the
BTLMODE bit is set to a ‘0’, the PHSEG2<2:0> bits
have no effect.
2003-2012 Microchip Technology Inc.
DS21801G-page 43
MCP2515
REGISTER 5-1:
CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah)
R/W-0
SJW1
R/W-0
SJW0
R/W-0
BRP5
R/W-0
BRP4
R/W-0
BRP3
R/W-0
BRP2
R/W-0
BRP1
R/W-0
BRP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
SJW<1:0>: Synchronization Jump Width Length bits
11= Length = 4 x TQ
10= Length = 3 x TQ
01= Length = 2 x TQ
00= Length = 1 x TQ
BRP<5:0>: Baud Rate Prescaler bits
TQ = 2 x (BRP + 1)/FOSC
REGISTER 5-2:
CNF2 – CONFIGURATION 1 (ADDRESS: 29h)
R/W-0
BTLMODE
bit 7
R/W-0
SAM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHSEG12
PHSEG11
PHSEG10
PRSEG2
PRSEG1
PRSEG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
BTLMODE: PS2 Bit Time Length bit
1= Length of PS2 determined by PHSEG22:PHSEG20 bits of CNF3
0= Length of PS2 is the greater of PS1 and IPT (2 TQ)
SAM: Sample Point Configuration bit
1= Bus line is sampled three times at the sample point
0= Bus line is sampled once at the sample point
bit 5-3
bit 2-0
PHSEG1<2:0>: PS1 Length bits
(PHSEG1 + 1) x TQ
PRSEG<2:0>: Propagation Segment Length bits
(PRSEG + 1) x TQ
DS21801G-page 44
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 5-3:
CNF3 - CONFIGURATION 1 (ADDRESS: 28h)
R/W-0
SOF
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WAKFIL
PHSEG22
PHSEG21
PHSEG20
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
SOF: Start-of-Frame signal bit
If CANCTRL.CLKEN = 1:
1= CLKOUT pin enabled for SOF signal
0= CLKOUT pin enabled for clockout function
If CANCTRL.CLKEN = 0, Bit is don’t care.
WAKFIL: Wake-up Filter bit
1= Wake-up filter enabled
0= Wake-up filter disabled
bit 5-3
bit 2-0
Unimplemented: Reads as ‘0’
PHSEG2<2:0>: PS2 Length bits
(PHSEG2 + 1) x TQ
Minimum valid setting for PS2 is 2 TQ
2003-2012 Microchip Technology Inc.
DS21801G-page 45
MCP2515
NOTES:
DS21801G-page 46
2003-2012 Microchip Technology Inc.
MCP2515
6.6
Error States
6.0
ERROR DETECTION
Detected errors are made known to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states according to the value of the internal
error counters:
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
6.1
CRC Error
With the Cyclic Redundancy Check (CRC), the
transmitter calculates special check bits for the bit
sequence from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC Field. The receiving node also calculates the
CRC sequence using the same formula and performs
a comparison to the received sequence. If a mismatch
is detected, a CRC error has occurred and an error
frame is generated. The message is repeated.
1. Error-active
2. Error-passive
3. Bus-off (transmitter only)
The error-active state is the usual state where the node
can transmit messages and active error frames (made
of dominant bits) without any restrictions.
In the error-passive state, messages and passive error
frames (made of recessive bits) may be transmitted.
6.2
Acknowledge Error
The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
During this state, messages can neither be received or
transmitted. Only transmitters can go bus-off.
In the acknowledge field of a message, the transmitter
checks if the acknowledge slot (which has been sent
out as a recessive bit) contains a dominant bit. If not, no
other node has received the frame correctly. An
acknowledge error has occurred, an error frame is
generated and the message will have to be repeated.
6.7
Error Modes and Error Counters
The MCP2515 contains two error counters: the
Receive Error Counter (REC) (see Register 6-2) and
the Transmit Error Counter (TEC) (see Register 6-1).
The values of both counters can be read by the MCU.
These counters are incremented/decremented in
accordance with the CAN bus specification.
6.3
Form Error
If a node detects a dominant bit in one of the four
segments (including end-of-frame, interframe space,
acknowledge delimiter or CRC delimiter), a form error
has occurred and an error frame is generated. The
message is repeated.
The MCP2515 is error-active if both error counters are
below the error-passive limit of 128.
It is error-passive if at least one of the error counters
equals or exceeds 128.
6.4
Bit Error
A bit error occurs if a transmitter detects the opposite
bit level to what it transmitted (i.e., transmitted a
dominant and detected a recessive, or transmitted a
recessive and detected a dominant).
It goes to bus-off if the TEC exceeds the bus-off limit of
255. The device remains in this state until the bus-off
recovery sequence is received. The bus-off recovery
sequence consists of 128 occurrences of 11
consecutive recessive bits (see Figure 6-1).
Exception: In the case where the transmitter sends a
recessive bit and a dominant bit is detected during the
arbitration field and the acknowledge slot, no bit error is
generated because normal arbitration is occurring.
Note:
The MCP2515, after going bus-off, will
recover back to error-active without any
intervention by the MCU if the bus remains
idle for 128 x 11 bit times. If this is not
desired, the error interrupt Service
Routine should address this.
6.5
Stuff Error
lf, between the start-of-frame and the CRC delimiter,
six consecutive bits with the same polarity are
detected, the bit-stuffing rule has been violated. A stuff
error occurs and an error frame is generated. The
message is repeated.
The Current Error mode of the MCP2515 can be read
by the MCU via the EFLG register (see Register 6-3).
Additionally, there is an error state warning flag bit
(EFLG:EWARN) which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
2003-2012 Microchip Technology Inc.
DS21801G-page 47
MCP2515
FIGURE 6-1:
ERROR MODES STATE DIAGRAM
RESET
Error-Active
REC < 127 or
TEC < 127
128 occurrences of
11 consecutive
“recessive” bits
REC > 127 or
TEC > 127
Error-Passive
TEC > 255
Bus-Off
REGISTER 6-1:
TEC – TRANSMIT ERROR COUNTER
(ADDRESS: 1Ch)
R-0
TEC7
bit 7
R-0
R-0
R-0
R-0
R-0
TEC2
R-0
R-0
TEC6
TEC5
TEC4
TEC3
TEC1
TEC0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
TEC<7:0>: Transmit Error Count bits
REGISTER 6-2:
REC – RECEIVER ERROR COUNTER
(ADDRESS: 1Dh)
R-0
REC7
bit 7
R-0
REC6
R-0
R-0
R-0
R-0
R-0
R-0
REC5
REC4
REC3
REC2
REC1
REC0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
REC<7:0>: Receive Error Count bits
DS21801G-page 48
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 6-3:
EFLG – ERROR FLAG
(ADDRESS: 2Dh)
R/W-0
RX1OVR
bit 7
R/W-0
RX0OVR
R-0
R-0
R-0
R-0
R-0
R-0
TXBO
TXEP
RXEP
TXWAR
RXWAR
EWARN
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RX1OVR: Receive Buffer 1 Overflow Flag bit
- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1
- Must be reset by MCU
RX0OVR: Receive Buffer 0 Overflow Flag bit
- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1
- Must be reset by MCU
TXBO: Bus-Off Error Flag bit
- Bit set when TEC reaches 255
- Reset after a successful bus recovery sequence
TXEP: Transmit Error-Passive Flag bit
- Set when TEC is equal to or greater than 128
- Reset when TEC is less than 128
RXEP: Receive Error-Passive Flag bit
- Set when REC is equal to or greater than 128
- Reset when REC is less than 128
TXWAR: Transmit Error Warning Flag bit
- Set when TEC is equal to or greater than 96
- Reset when TEC is less than 96
RXWAR: Receive Error Warning Flag bit
- Set when REC is equal to or greater than 96
- Reset when REC is less than 96
EWARN: Error Warning Flag bit
- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
- Reset when both REC and TEC are less than 96
2003-2012 Microchip Technology Inc.
DS21801G-page 49
MCP2515
NOTES:
DS21801G-page 50
2003-2012 Microchip Technology Inc.
MCP2515
7.2
Transmit Interrupt
7.0
INTERRUPTS
When
the
transmit
interrupt
is
enabled
The MCP2515 has eight sources of interrupts. The
CANINTE register contains the individual interrupt
enable bits for each interrupt source. The CANINTF
register contains the corresponding interrupt flag bit for
each interrupt source. When an interrupt occurs, the
INT pin is driven low by the MCP2515 and will remain
low until the interrupt is cleared by the MCU. An
interrupt can not be cleared if the respective condition
still prevails.
(CANINTE.TXnIE = 1), an interrupt will be generated on
the INT pin once the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The CANINTF.TXnIF bit will be set to indicate
the source of the interrupt. The interrupt is cleared by
clearing the TXnIF bit.
7.3
Receive Interrupt
It is recommended that the Bit Modify command be
used to reset flag bits in the CANINTF register rather
than normal write operations. This is done to prevent
unintentionally changing a flag that changes during the
Write command, potentially causing an interrupt to be
missed.
When
the
receive
interrupt
is
enabled
(CANINTE.RXnIE = 1), an interrupt will be generated
on the INT pin once a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The CANINTF.RXnIF bit will be set to
indicate the source of the interrupt. The interrupt is
cleared by clearing the RXnIF bit.
It should be noted that the CANINTF flags are
read/write and an interrupt can be generated by the
MCU setting any of these bits, provided the associated
CANINTE bit is also set.
7.4
Message Error Interrupt
When an error occurs during the transmission or
reception of a message, the message error flag
(CANINTF.MERRF) will be set and, if the
CANINTE.MERRE bit is set, an interrupt will be
generated on the INT pin. This is intended to be used
to facilitate baud rate determination when used in
conjunction with Listen-Only mode.
7.1
Interrupt Code Bits
The source of a pending interrupt is indicated in the
CANSTAT.ICOD (interrupt code) bits, as indicated in
Register 10-2. In the event that multiple interrupts
occur, the INT will remain low until all interrupts have
been reset by the MCU. The CANSTAT.ICOD bits will
reflect the code for the highest priority interrupt that is
currently pending. Interrupts are internally prioritized
such that the lower the ICOD value, the higher the
interrupt priority. Once the highest priority interrupt
condition has been cleared, the code for the next
highest priority interrupt that is pending (if any) will be
reflected by the ICOD bits (see Table 7-1). Only those
interrupt sources that have their associated CANINTE
enable bit set will be reflected in the ICOD bits.
7.5
Bus Activity Wake-up Interrupt
When the MCP2515 is in Sleep mode and the bus activity
wake-up interrupt is enabled (CANINTE.WAKIE = 1), an
interrupt will be generated on the INT pin and the
CANINTF.WAKIF bit will be set when activity is detected
on the CAN bus. This interrupt causes the MCP2515 to
exit Sleep mode. The interrupt is reset by clearing the
WAKIF bit.
TABLE 7-1:
ICOD<2:0>
ICOD<2:0> DECODE
Boolean Expression
Note:
The MCP2515 wakes up into Listen-Only
mode.
7.6
Error Interrupt
000
001
010
011
100
101
110
111
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ERR
When
the
error
interrupt
is
enabled
(CANINTE.ERRIE = 1), an interrupt is generated on
the INT pin if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
Error Flag (EFLG) register will indicate one of the
following conditions.
ERR•WAK
ERR•WAK•TX0
ERR•WAK•TX0•TX1
ERR•WAK•TX0•TX1•TX2
ERR•WAK•TX0•TX1•TX2•RX0
ERR•WAK•TX0•TX1•TX2•RX0•RX1
7.6.1
RECEIVER OVERFLOW
An overflow condition occurs when the MAB has
assembled a valid receive message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
EFLG.RXnOVR bit will be set to indicate the overflow
condition. This bit must be cleared by the MCU.
Note:
ERR is associated with CANINTE,ERRIE.
2003-2012 Microchip Technology Inc.
DS21801G-page 51
MCP2515
7.6.2
RECEIVER WARNING
7.6.6
BUS-OFF
The REC has reached the MCU warning limit of 96.
The TEC has exceeded 255 and the device has gone
to bus-off state.
7.6.3
TRANSMITTER WARNING
7.7
Interrupt Acknowledge
The TEC has reached the MCU warning limit of 96.
Interrupts are directly associated with one or more
status flags in the CANINTF register. Interrupts are
pending as long as one of the flags is set. Once an
interrupt flag is set by the device, the flag can not be
reset by the MCU until the interrupt condition is
removed.
7.6.4
RECEIVER ERROR-PASSIVE
The REC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.5
TRANSMITTER ERROR-PASSIVE
The TEC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
REGISTER 7-1:
CANINTE – INTERRUPT ENABLE
(ADDRESS: 2Bh)
R/W-0
MERRE
bit 7
R/W-0
R/W-0
ERRIE
R/W-0
TX2IE
R/W-0
TX1IE
R/W-0
TX0IE
R/W-0
RX1IE
R/W-0
RX0IE
WAKIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MERRE: Message Error Interrupt Enable bit
1= Interrupt on error during message reception or transmission
0= Disabled
WAKIE: Wake-up Interrupt Enable bit
1= Interrupt on CAN bus activity
0= Disabled
ERRIE: Error Interrupt Enable bit (multiple sources in EFLG register)
1 = Interrupt on EFLG error condition change
0= Disabled
TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1= Interrupt on TXB2 becoming empty
0= Disabled
TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1= Interrupt on TXB1 becoming empty
0= Disabled
TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1= Interrupt on TXB0 becoming empty
0= Disabled
RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1= Interrupt when message received in RXB1
0= Disabled
RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1= Interrupt when message received in RXB0
0= Disabled
DS21801G-page 52
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 7-2:
CANINTF – INTERRUPT FLAG
(ADDRESS: 2Ch)
R/W-0
MERRF
bit 7
R/W-0
R/W-0
ERRIF
R/W-0
TX2IF
R/W-0
TX1IF
R/W-0
TX0IF
R/W-0
RX1IF
R/W-0
RX0IF
WAKIF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MERRF: Message Error Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
WAKIF: Wake-up Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
ERRIF: Error Interrupt Flag bit (multiple sources in EFLG register)
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
TX2IF: Transmit Buffer 2 Empty Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
TX1IF: Transmit Buffer 1 Empty Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
TX0IF: Transmit Buffer 0 Empty Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
RX1IF: Receive Buffer 1 Full Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
RX0IF: Receive Buffer 0 Full Interrupt Flag bit
1= Interrupt pending (must be cleared by MCU to reset interrupt condition)
0= No interrupt pending
2003-2012 Microchip Technology Inc.
DS21801G-page 53
MCP2515
NOTES:
DS21801G-page 54
2003-2012 Microchip Technology Inc.
MCP2515
8.2
CLKOUT Pin
8.0
OSCILLATOR
The CLKOUT pin is provided to the system designer for
use as the main system clock or as a clock input for
other devices in the system. The CLKOUT has an inter-
nal prescaler which can divide FOSC by 1, 2, 4 and 8.
The CLKOUT function is enabled and the prescaler is
selected via the CANCNTRL register (see
Register 10-1).
The MCP2515 is designed to be operated with a crystal
or ceramic resonator connected to the OSC1 and
OSC2 pins. The MCP2515 oscillator design requires
the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal
manufacturer’s specifications. A typical oscillator circuit
is shown in Figure 8-1. The MCP2515 may also be
driven by an external clock source connected to the
OSC1 pin, as shown in Figure 8-2 and Figure 8-3.
Note:
The maximum frequency on CLKOUT is
specified as 25 MHz (See Table 13-5).
The CLKOUT pin will be active upon system Reset and
default to the slowest speed (divide by 8) so that it can
be used as the MCU clock.
8.1
Oscillator Start-up Timer
The MCP2515 utilizes an Oscillator Start-up Timer
(OST) that holds the MCP2515 in Reset to ensure that
the oscillator has stabilized before the internal state
machine begins to operate. The OST maintains Reset
for the first 128 OSC1 clock cycles after power-up or a
wake-up from Sleep mode occurs. It should be noted
that no SPI protocol operations should be attempted
until after the OST has expired.
When Sleep mode is requested, the MCP2515 will
drive sixteen additional clock cycles on the CLKOUT
pin before entering Sleep mode. The Idle state of the
CLKOUT pin in Sleep mode is low. When the CLKOUT
function is disabled (CANCNTRL.CLKEN = 0) the
CLKOUT pin is in a high-impedance state.
The CLKOUT function is designed to ensure that
thCLKOUT and tlCLKOUT timings are preserved when the
CLKOUT pin function is enabled, disabled or the
prescaler value is changed.
FIGURE 8-1:
CRYSTAL/CERAMIC RESONATOR OPERATION
OSC1
C1
To internal logic
Sleep
XTAL
(2)
RF
(1)
RS
C2
OSC2
Note 1: A series resistor (RS) may be required for AT strip-cut crystals.
2: The feedback resistor (RF), is typically in the range of 2 to 10 M.
FIGURE 8-2:
EXTERNAL CLOCK SOURCE
Clock from
OSC1
external system
(1)
OSC2
Open
Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.
2: Duty cycle restrictions must be observed (see Table 12-1).
2003-2012 Microchip Technology Inc.
DS21801G-page 55
MCP2515
FIGURE 8-3:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT(1)
To Other
Devices
330 k
330 k
74AS04
74AS04
74AS04
MCP2510
OSC1
0.1 mF
XTAL
Note 1: Duty cycle restrictions must be observed (see Table 12-1).
TABLE 8-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 8-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values Used:
Typical Capacitor
Values Tested:
Osc
Crystal
Freq.(2)
Type(1)(4)
Mode
Freq.
OSC1
OSC2
C1
C2
HS
8.0 MHz
27 pF
22 pF
27 pF
22 pF
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
16.0 MHz
Capacitor values are for design guidance only:
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Capacitor values are for design guidance only:
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should test the performance of the oscillator over the
expected VDD and temperature range for the
application.
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should test the performance of the oscillator over the
expected VDD and temperature range for the
application.
See the notes following Table 8-2 for additional
information.
Resonators Used:
4.0 MHz
See the notes following this Table for additional
information.
Crystals Used(3)
:
8.0 MHz
16.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
Note 1: While higher capacitance increases the
stability of the oscillator, it also increases
the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: RS may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS21801G-page 56
2003-2012 Microchip Technology Inc.
MCP2515
9.0
RESET
The MCP2515 differentiates between two Resets:
1. Hardware Reset – Low on RESET pin
2. SPI Reset – Reset via SPI command
Both of these Resets are functionally equivalent. It is
important to provide one of these two Resets after
power-up to ensure that the logic and registers are in
their default state. A hardware Reset can be achieved
automatically by placing an RC on the RESET pin (see
Figure 9-1). The values must be such that the device is
held in Reset for a minimum of 2 µs after VDD reaches
operating voltage, as indicated in the electrical
specification (tRL).
FIGURE 9-1:
RESET PIN CONFIGURATION EXAMPLE
VDD
VDD
D(1)
R
R1(2)
RESET
C
Note 1: The diode D helps discharge the capacitor quickly when VDD powers down.
2: R1 = 1 k to 10 k will limit any current flowing into RESET from external
capacitor C, in the event of RESET pin breakdown due to Electrostatic
Discharge (ESD) or Electrical Overstress (EOS).
2003-2012 Microchip Technology Inc.
DS21801G-page 57
MCP2515
NOTES:
DS21801G-page 58
2003-2012 Microchip Technology Inc.
MCP2515
When in Sleep mode, the MCP2515 stops its internal
oscillator. The MCP2515 will wake-up when bus activity
occurs or when the MCU sets, via the SPI interface, the
CANINTF.WAKIF bit to ‘generate’ a wake-up attempt
(the CANINTE.WAKIE bit must also be set in order for
the wake-up interrupt to occur).
10.0 MODES OF OPERATION
The MCP2515 has five modes of operation. These
modes are:
1. Configuration mode
2. Normal mode
The TXCAN pin will remain in the recessive state while
the MCP2515 is in Sleep mode.
3. Sleep mode
4. Listen-Only mode
5. Loopback mode
10.2.1
WAKE-UP FUNCTIONS
The operational mode is selected via the
CANCTRL. REQOP bits (see Register 10-1).
The device will monitor the RXCAN pin for activity while
it is in Sleep mode. If the CANINTE.WAKIE bit is set,
the device will wake-up and generate an interrupt.
Since the internal oscillator is shut down while in Sleep
mode, it will take some amount of time for the oscillator
to start-up and the device to enable itself to receive
messages. This Oscillator Start-up Timer (OST) is
defined as 128 TOSC.
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. The requested mode must be verified by
reading
the
CANSTAT.OPMODE
bits
(see
Register 10-2).
10.1 Configuration Mode
The device will ignore the message that caused the
wake-up from Sleep mode, as well as any messages
that occur while the device is ‘waking up’. The device
will wake-up in Listen-Only mode. The MCU must set
Normal mode before the MCP2515 will be able to
communicate on the bus.
The MCP2515 must be initialized before activation.
This is only possible if the device is in the Configuration
mode. Configuration mode is automatically selected
after power-up, a Reset or can be entered from any
other mode by setting the CANTRL.REQOP bits to
‘100’. When Configuration mode is entered, all error
counters are cleared. Configuration mode is the only
mode where the following registers are modifiable:
The device can be programmed to apply a low-pass
filter function to the RXCAN input line while in internal
Sleep mode. This feature can be used to prevent the
device from waking up due to short glitches on the CAN
bus lines. The CNF3.WAKFIL bit enables or disables
the filter.
• CNF1, CNF2, CNF3
• TXRTSCTRL
• Filter registers
• Mask registers
10.3 Listen-Only Mode
Listen-Only mode provides a means for the MCP2515
to receive all messages (including messages with
errors) by configuring the RXBnCTRL.RXM<1:0> bits.
This mode can be used for bus monitor applications or
for detecting the baud rate in ‘hot plugging’ situations.
10.2 Sleep Mode
The MCP2515 has an internal Sleep mode that is used
to minimize the current consumption of the device. The
SPI interface remains active for reading even when the
MCP2515 is in Sleep mode, allowing access to all
registers.
For auto-baud detection, it is necessary that at least
two other nodes are communicating with each other.
The baud rate can be detected empirically by testing
different values until valid messages are received.
To enter Sleep mode, the mode request bits are set in
the CANCTRL register (REQOP<2:0>). The
CANSTAT.OPMODE bits indicate operation mode.
These bits should be read after sending the Sleep
command to the MCP2515. The MCP2515 is active
and has not yet entered Sleep mode until these bits
indicate that Sleep mode has been entered.
Listen-Only mode is a silent mode, meaning no
messages will be transmitted while in this mode
(including error flags or acknowledge signals). In
Listen-Only mode, both valid and invalid messages will
be received regardless of filters and masks or RXMn
Receive Buffer mode bits. The error counters are reset
and deactivated in this state. The Listen-Only mode is
activated by setting the mode request bits in the
CANCTRL register.
When in internal Sleep mode, the wake-up interrupt is
still active (if enabled). This is done so that the MCU
can also be placed into a Sleep mode and use the
MCP2515 to wake it up upon detecting activity on the
bus.
2003-2012 Microchip Technology Inc.
DS21801G-page 59
MCP2515
10.4 Loopback Mode
10.5 Normal Mode
Loopback mode will allow internal transmission of
messages from the transmit buffers to the receive
buffers without actually transmitting messages on the
CAN bus. This mode can be used in system
development and testing.
Normal mode is the standard operating mode of the
MCP2515. In this mode, the device actively monitors all
bus messages and generates Acknowledge bits, error
frames, etc. This is also the only mode in which the
MCP2515 will transmit messages over the CAN bus.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself just as if they were
coming from another node. The Loopback mode is a
silent mode, meaning no messages will be transmitted
while in this state (including error flags or Acknowledge
signals). The TXCAN pin will be in a recessive state.
The filters and masks can be used to allow only
particular messages to be loaded into the receive
registers. The masks can be set to all zeros to provide
a mode that accepts all messages. The Loopback
mode is activated by setting the mode request bits in
the CANCTRL register.
REGISTER 10-1: CANCTRL – CAN CONTROL REGISTER
(ADDRESS: XFh)
R/W-1
R/W-0
R/W-0
R/W-0
ABAT
R/W-0
OSM
R/W-1
R/W-1
R/W-1
REQOP2
REQOP1
REQOP0
CLKEN
CLKPRE1
CLKPRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-5
REQOP<2:0>: Request Operation mode bits
000= Set Normal Operation mode
001= Set Sleep mode
010= Set Loopback mode
011= Set Listen-Only mode
100= Set Configuration mode
All other values for REQOP bits are invalid and should not be used
On power-up, REQOP = b’111’
bit 4
ABAT: Abort All Pending Transmissions bit
1= Request abort of all pending transmit buffers
0= Terminate request to abort all transmissions
bit 3
OSM: One-Shot mode bit
1= Enabled. Message will only attempt to transmit one time
0= Disabled. Messages will reattempt transmission, if required
bit 2
CLKEN: CLKOUT Pin Enable bit
1= CLKOUT pin enabled
0= CLKOUT pin disabled (Pin is in high-impedance state)
bit 1-0
CLKPRE<1:0>: CLKOUT Pin Prescaler bits
00= FCLKOUT = System Clock/1
01= FCLKOUT = System Clock/2
10= FCLKOUT = System Clock/4
11= FCLKOUT = System Clock/8
DS21801G-page 60
2003-2012 Microchip Technology Inc.
MCP2515
REGISTER 10-2: CANSTAT – CAN STATUS REGISTER
(ADDRESS: XEh)
R-1
R-0
R-0
U-0
—
R-0
R-0
R-0
U-0
—
OPMOD2
OPMOD1
OPMOD0
ICOD2
ICOD1
ICOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-5
OPMOD<2:0>: Operation mode bits
000= Device is in the Normal Operation mode
001= Device is in Sleep mode
010= Device is in Loopback mode
011= Device is in Listen-Only mode
100= Device is in Configuration mode
bit 4
Unimplemented: Read as ‘0’
bit 3-1
ICOD<2:0>: Interrupt Flag Code bits
000= No Interrupt
001= Error Interrupt
010= Wake-up Interrupt
011= TXB0 Interrupt
100= TXB1 Interrupt
101= TXB2 Interrupt
110= RXB0 Interrupt
111= RXB1 Interrupt
bit 0
Unimplemented: Read as ‘0’
2003-2012 Microchip Technology Inc.
DS21801G-page 61
MCP2515
NOTES:
DS21801G-page 62
2003-2012 Microchip Technology Inc.
MCP2515
reading and writing of data. Some specific control and
status registers allow individual bit modification using
the SPI Bit Modify command. The registers that allow
this command are shown as shaded locations in
Table 11-1. A summary of the MCP2515 control
registers is shown in Table 11-2.
11.0 REGISTER MAP
The register map for the MCP2515 is shown in
Table 11-1. Address locations for each register are
determined by using the column (higher-order four
bits) and row (lower-order four bits) values. The regis-
ters have been arranged to optimize the sequential
TABLE 11-1: CAN CONTROLLER REGISTER MAP
Lower
Address
Bits
Higher-Order Address Bits
0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note:
RXF0SIDH
RXF0SIDL
RXF0EID8
RXF0EID0
RXF1SIDH
RXF1SIDL
RXF1EID8
RXF1EID0
RXF2SIDH
RXF2SIDL
RXF2EID8
RXF2EID0
BFPCTRL
TXRTSCTRL
CANSTAT
CANCTRL
RXF3SIDH RXM0SIDH
TXB0CTRL
TXB0SIDH
TXB0SIDL
TXB0EID8
TXB0EID0
TXB0DLC
TXB0D0
TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL
TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH
RXF3SIDL
RXF3EID8
RXF3EID0
RXM0SIDL
RXM0EID8
RXM0EID0
TXB1SIDL
TXB1EID8
TXB1EID0
TXB1DLC
TXB1D0
TXB1D1
TXB1D2
TXB1D3
TXB1D4
TXB1D5
TXB1D6
TXB1D7
CANSTAT
CANCTRL
TXB2SIDL
TXB2EID8
TXB2EID0
TXB2DLC
TXB2D0
TXB2D1
TXB2D2
TXB2D3
TXB2D4
TXB2D5
TXB2D6
TXB2D7
CANSTAT
CANCTRL
RXB0SIDL RXB1SIDL
RXB0EID8 RXB1EID8
RXB0EID0 RXB1EID0
RXF4SIDH RXM1SIDH
RXF4SIDL
RXF4EID8
RXF4EID0
RXF5SIDH
RXF5SIDL
RXF5EID8
RXF5EID0
TEC
RXM1SIDL
RXM1EID8
RXM1EID0
CNF3
RXB0DLC
RXB0D0
RXB0D1
RXB0D2
RXB0D3
RXB0D4
RXB0D5
RXB0D6
RXB0D7
CANSTAT
CANCTRL
RXB1DLC
RXB1D0
RXB1D1
RXB1D2
RXB1D3
RXB1D4
RXB1D5
RXB1D6
RXB1D7
CANSTAT
CANCTRL
TXB0D1
TXB0D2
CNF2
TXB0D3
CNF1
TXB0D4
CANINTE
CANINTF
EFLG
TXB0D5
TXB0D6
REC
TXB0D7
CANSTAT
CANCTRL
CANSTAT
CANCTRL
CANSTAT
CANCTRL
Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command.
TABLE 11-2: CONTROL REGISTER SUMMARY
Register
Name
Address
(Hex)
POR/RST
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BFPCTRL
TXRTSCTRL
CANSTAT
CANCTRL
TEC
0C
0D
xE
xF
1C
1D
28
29
2A
2B
2C
2D
30
40
50
60
70
—
—
—
—
B1BFS
B2RTS
B0BFS
B1RTS
—
B1BFE
B0RTS
ICOD2
OSM
B0BFE
B1BFM
B0BFM --00 0000
B2RTSM B1RTSM B0RTSM --xx x000
ICOD1 ICOD0 100- 000-
OPMOD2 OPMOD1 OPMOD0
REQOP2 REQOP1 REQOP0
—
ABAT
CLKEN CLKPRE1 CLKPRE0 1110 0111
Transmit Error Counter (TEC)
Receive Error Counter (REC)
0000 0000
0000 0000
REC
CNF3
SOF
BTLMODE
SJW1
WAKFIL
SAM
—
—
—
PHSEG22 PHSEG21 PHSEG20 00-- -000
CNF2
PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000
CNF1
SJW0
BRP5
ERRIE
ERRIF
TXBO
MLOA
MLOA
MLOA
RXM0
RXM0
BRP4
TX2IE
TX2IF
TXEP
TXERR
TXERR
TXERR
—
BRP3
TX1IE
BRP2
TX0IE
TX0IF
TXWAR
—
BRP1
RX1IE
RX1IF
BRP0
RX0IE
RX0IF
0000 0000
0000 0000
0000 0000
CANINTE
CANINTF
EFLG
MERRE
MERRF
WAKIE
WAKIF
TX1IF
RX1OVR RX0OVR
RXEP
RXWAR EWARN 0000 0000
TXB0CTRL
TXB1CTRL
TXB2CTRL
RXB0CTRL
RXB1CTRL
—
—
—
—
—
ABTF
ABTF
ABTF
RXM1
RSM1
TXREQ
TXREQ
TXREQ
RXRTR
RXRTR
TXP1
TXP1
TXP0
TXP0
TXP0
-000 0-00
-000 0-00
-000 0-00
—
—
TXP1
BUKT
FILHIT2
BUKT
FILHIT1
FILHIT0 -00- 0000
FILHIT0 -00- 0000
—
2003-2012 Microchip Technology Inc.
DS21801G-page 63
MCP2515
NOTES:
DS21801G-page 64
2003-2012 Microchip Technology Inc.
MCP2515
the same as the READinstruction (i.e., sequential reads
are possible). This instruction further reduces the SPI
overhead by automatically clearing the associated
receive flag (CANINTF.RXnIF) when CS is raised at the
end of the command.
12.0 SPI INTERFACE
12.1 Overview
The MCP2515 is designed to interface directly with the
Serial Peripheral Interface (SPI) port available on many
microcontrollers and supports Mode 0,0and Mode 1,1.
Commands and data are sent to the device via the SI
pin, with data being clocked in on the rising edge of
SCK. Data is driven out by the MCP2515 (on the SO
line) on the falling edge of SCK. The CS pin must be
held low while any operation is performed. Table 12-1
shows the instruction bytes for all operations. Refer to
Figure 12-10 and Figure 12-11 for detailed input and
output timing diagrams for both Mode 0,0 and Mode
1,1operation.
12.5 WRITEInstruction
The WRITE instruction is started by lowering the CS
pin. The WRITEinstruction is then sent to the MCP2515
followed by the address and at least one byte of data.
It is possible to write to sequential registers by
continuing to clock in data bytes, as long as CS is held
low. Data will actually be written to the register on the
rising edge of the SCK line for the D0 bit. If the CS line
is brought high before eight bits are loaded, the write
will be aborted for that data byte and previous bytes in
the command will have been written. Refer to the timing
diagram in Figure 12-4 for a more detailed illustration of
the byte write sequence.
Note:
The MCP2515 expects the first byte after
lowering CS to be the instruction/
command byte. This implies that CS must
be raised and then lowered again to
invoke another command.
12.6 LOAD TX BUFFERInstruction
12.2 RESETInstruction
The LOAD TX BUFFERinstruction (Figure 12-5) elimi-
nates the eight-bit address required by a normal Write
command. The eight-bit instruction sets the Address
Pointer to one of six addresses to quickly write to a
transmit buffer that points to the “ID” or “data” address
of any of the three transmit buffers.
The RESET instruction can be used to re-initialize the
internal registers of the MCP2515 and set Configuration
mode. This command provides the same functionality,
via the SPI interface, as the RESET pin.
The RESET instruction is a single-byte instruction that
requires selecting the device by pulling CS low,
sending the instruction byte and then raising CS. It is
highly recommended that the Reset command be sent
(or the RESET pin be lowered) as part of the power-on
initialization sequence.
12.7 REQUEST-TO-SEND(RTS)
Instruction
The RTS command can be used to initiate message
transmission for one or more of the transmit buffers.
12.3 READInstruction
The MCP2515 is selected by lowering the CS pin. The
RTS command byte is then sent. Shown in Figure 12-6,
the last 3 bits of this command indicate which transmit
buffer(s) are enabled to send.
The READinstruction is started by lowering the CS pin.
The READ instruction is then sent to the MCP2515
followed by the 8-bit address (A7 through A0). Next, the
data stored in the register at the selected address will
be shifted out on the SO pin.
This command will set the TxBnCTRL.TXREQ bit for
the respective buffer(s). Any or all of the last three bits
can be set in a single command. If the RTS command
is sent with nnn = 000, the command will be ignored.
The internal Address Pointer is automatically
incremented to the next address once each byte of
data is shifted out. Therefore, it is possible to read the
next consecutive register address by continuing to pro-
vide clock pulses. Any number of consecutive register
locations can be read sequentially using this method.
The read operation is terminated by raising the CS pin
(Figure 12-2).
12.8 READ STATUSInstruction
The READ STATUSinstruction allows single instruction
access to some of the often used status bits for
message reception and transmission.
The MCP2515 is selected by lowering the CS pin and
the Read Status command byte, shown in Figure 12-8,
is sent to the MCP2515. Once the command byte is
sent, the MCP2515 will return eight bits of data that
contain the status.
12.4 READ RX BUFFERInstruction
The READ RX BUFFER instruction (Figure 12-3) pro-
vides a means to quickly address a receive buffer for
reading. This instruction reduces the SPI overhead by
one byte, the address byte. The command byte actually
has four possible values that determine the Address
Pointer location. Once the command byte is sent, the
controller clocks out the data at the address location
If additional clocks are sent after the first eight bits are
transmitted, the MCP2515 will continue to output the
status bits as long as the CS pin is held low and clocks
are provided on SCK.
2003-2012 Microchip Technology Inc.
DS21801G-page 65
MCP2515
Each status bit returned in this command may also be
read by using the standard Read command with the
appropriate register address.
The part is selected by lowering the CS pin and the Bit
Modify command byte is then sent to the MCP2515.
The command is followed by the address of the
register, the mask byte and finally the data byte.
12.9 RX STATUSInstruction
The mask byte determines which bits in the register will
be allowed to change. A ‘1’ in the mask byte will allow
a bit in the register to change, while a ‘0’ will not.
The RX STATUS instruction (Figure 12-9) is used to
quickly determine which filter matched the message
and message type (standard, extended, remote). After
the command byte is sent, the controller will return
8 bits of data that contain the status data. If more clocks
are sent after the eight bits are transmitted, the
controller will continue to output the same status bits as
long as the CS pin stays low and clocks are provided.
The data byte determines what value the modified bits
in the register will be changed to. A ‘1’ in the data byte
will set the bit and a ‘0’ will clear the bit, provided that
the mask for that bit is set to a ‘1’ (see Figure 12-7).
FIGURE 12-1:
Mask byte
BIT MODIFY
0 0 1 1 0 1 0 1
12.10 BIT MODIFYInstruction
The BIT MODIFYinstruction provides a means for set-
ting or clearing individual bits in specific status and con-
trol registers. This command is not available for all
registers. See Section 11.0 “Register Map” to
determine which registers allow the use of this
command.
X X 1 0 X 0 X 1
0 1 0 1 0 0 0 1
0 1 1 0 0 0 0 1
Data byte
Previous
Register
Contents
Note:
Executing the Bit Modify command on
registers that are not bit-modifiable will
force the mask to FFh. This will allow byte-
writes to the registers, not bit modify.
Resulting
Register
Contents
TABLE 12-1: SPI INSTRUCTION SET
Instruction Name
Instruction Format
Description
RESET
READ
1100 0000
0000 0011
1001 0nm0
Resets internal registers to default state, set Configuration mode.
Read data from register beginning at selected address.
READ RX BUFFER
When reading a receive buffer, reduces the overhead of a normal
Read command by placing the Address Pointer at one of four
locations, as indicated by ‘n,m’. Note: The associated RX flag bit
(CANINTF.RXnIF) will be cleared after bringing CS high.
WRITE
0000 0010
0100 0abc
Write data to register beginning at selected address.
LOAD TX BUFFER
When loading a transmit buffer, reduces the overhead of a normal
Write command by placing the Address Pointer at one of six
locations as indicated by ‘a,b,c’.
RTS
(Message
1000 0nnn
Instructs controller to begin message transmission sequence for
any of the transmit buffers.
Request-To-Send)
1000 0nnn
Request-to-send for TXBO
Request-to-send for TXB2
Request-to-send for TXB1
READ STATUS
RX STATUS
1010 0000
1011 0000
0000 0101
Quick polling command that reads several status bits for transmit
and receive functions.
Quick polling command that indicates filter match and message
type (standard, extended and/or remote) of received message.
BIT MODIFY
Allows the user to set or clear individual bits in a particular
register. Note: Not all registers can be bit-modified with this
command. Executing this command on registers that are not bit-
modifiable will force the mask to FFh. See the register map in
Section 11.0 “Register Map” for a list of the registers that apply.
DS21801G-page 66
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 12-2:
READ INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
Address Byte
0
0
0
0
0
0
1
1
A7
6
5
4
3
2
1
A0
Don’t Care
Data Out
SI
High-Impedance
7
6
5
4
3
2
1
0
SO
FIGURE 12-3:
READ RX BUFFER INSTRUCTION
CS
n
m
Address Points to Address
0 0 Receive Buffer 0,
0x61
0x66
0x71
0x76
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Start at RXB0SIDH
SCK
0 1 Receive Buffer 0,
Instruction
Start at RXB0D0
n
m
1
0
0
1
0
1 0 Receive Buffer 1,
Don’t Care
Data Out
SI
0
Start at RXB1SIDH
1 1 Receive Buffer 1,
High-Impedance
Start at RXB1D0
7
6
5
4
3
2
1
0
SO
FIGURE 12-4:
BYTE WRITE INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Data Byte
Instruction
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
A7
6
5
4
3
2
1
A0
SI
High-Impedance
SO
2003-2012 Microchip Technology Inc.
DS21801G-page 67
MCP2515
FIGURE 12-5:
LOAD TX BUFFER
a
b
c
Address Points to
Addr
CS
0
0
0
TX buffer 0, Start at
TXB0SIDH
0x31
0
1
2
3
4
5
a
6
b
7
8
9
10 11 12 13 14 15
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
TX buffer 0, Start at
TXB0D0
0x36
0x41
0x46
0x51
0x56
SCK
SI
TX buffer 1, Start at
TXB1SIDH
Data In
Instruction
TX buffer 1, Start at
TXB1D0
7
6
5
4
3
2
1
0
0
1
0
0
0
c
TX buffer 2, Start at
TXB2SIDH
High-Impedance
SO
TX buffer 2, Start at
TXB2D0
FIGURE 12-6:
REQUEST-TO-SEND (RTS) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
Instruction
T1
0
1
0
0
0
T2
T0
SI
High-Impedance
SO
FIGURE 12-7:
BIT MODIFY INSTRUCTION
CS
2324 25 26 27 28 29 30 31
Data Byte
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
SI
Mask Byte
Address Byte
Instruction
7
6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0
0 0 0 0 1 0 1 A7 6 5 4 3 2
1
A0
High-Impedance
SO
Note:
Not all registers can be accessed with
this command. See the register map for a
list of the registers that apply.
DS21801G-page 68
2003-2012 Microchip Technology Inc.
MCP2515
FIGURE 12-8:
READ STATUS INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
Don’t Care
1
0
1
0
0
0
0
0
SI
Repeat
Data Out
Data Out
High-Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
CANINTF.RX0IF
CANINTFL.RX1IF
TXB0CNTRL.TXREQ
CANINTF.TX0IF
TXB1CNTRL.TXREQ
CANINTF.TX1IF
TXB2CNTRL.TXREQ
CANINTF.TX2IF
FIGURE 12-9:
RX STATUS INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
Don’t Care
Repeat
1
0
1
1
0
0
0
0
SI
Data Out
Data Out
High-Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
7
6
Received Message
4
3
Msg Type Received
2
1
0
Filter Match
0 0 No RX message
0 0 Standard data frame
0 1 Standard remote frame
1 0 Extended data frame
1 1 Extended remote frame
0 0 0 RXF0
0 0 1 RXF1
0 1 0 RXF2
0 1 1 RXF3
1 0 0 RXF4
1 0 1 RXF5
0 1 Message in RXB0
1 0 Message in RXB1
1 1 Messages in both buffers*
CANINTF.RXnIF bits are mapped to The extended ID bit is mapped to
bits 7 and 6.
bit 4. The RTR bit is mapped to
bit 3.
1 1 0 RXF0 (rollover to RXB1)
1 1 1 RXF1 (rollover to RXB1)
* Buffer 0 has higher priority, therefore, RXB0 status is
reflected in bits 4:0.
2003-2012 Microchip Technology Inc.
DS21801G-page 69
MCP2515
FIGURE 12-10:
SPI INPUT TIMING
3
CS
11
10
6
1
2
7
Mode 1,1
Mode 0,0
SCK
SI
4
5
MSB in
LSB in
High-Impedance
SO
FIGURE 12-11:
SPI OUTPUT TIMING
CS
2
8
9
SCK
Mode 1,1
Mode 0,0
12
14
13
SO
SI
MSB out
LSB out
Don’t Care
DS21801G-page 70
2003-2012 Microchip Technology Inc.
MCP2515
13.0 ELECTRICAL CHARACTERISTICS
13.1 Absolute Maximum Ratings †
VDD.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VDD +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
Soldering temperature of leads (10 seconds)....................................................................................................... +300°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2003-2012 Microchip Technology Inc.
DS21801G-page 71
MCP2515
TABLE 13-1: DC CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
DC Characteristics
Param.
No.
Sym
Characteristic
Supply Voltage
Min
2.7
2.4
Max
5.5
—
Units
Conditions
VDD
V
V
VRET
Register Retention Voltage
High-Level Input Voltage
RXCAN
VIH
2
VDD + 1
VDD + 1
VDD
V
V
V
V
SCK, CS, SI, TXnRTS Pins
OSC1
0.7 VDD
0.85 VDD
0.85 VDD
RESET
VDD
Low-Level Input Voltage
RXCAN, TXnRTS Pins
SCK, CS, SI
VIL
-0.3
-0.3
VSS
VSS
.15 VDD
0.4 VDD
.3 VDD
V
V
V
V
OSC1
RESET
.15 VDD
Low-Level Output Voltage
TXCAN
VOL
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
V
V
V
V
IOL = +6.0 mA, VDD = 4.5V
IOL = +8.5 mA, VDD = 4.5V
IOL = +2.1 mA, VDD = 4.5V
IOL = +1.6 mA, VDD = 4.5V
RXnBF Pins
SO, CLKOUT
INT
High-Level Output Voltage
TXCAN, RXnBF Pins
SO, CLKOUT
VOH
VDD – 0.7
VDD – 0.5
VDD – 0.7
—
—
—
IOH = -3.0 mA, VDD = 4.5V
IOH = -400 µA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V
INT
Input Leakage Current
ILI
All I/O except OSC1 and
TXnRTS pins
-1
+1
µA
CS = RESET = VDD,
VIN = VSS to VDD
OSC1 Pin
-5
+5
7
µA
pF
CINT
IDD
Internal Capacitance
—
TAMB = 25°C, f = 1.0 MHz,
C
VDD = 0V (Note 1)
(All Inputs and Outputs)
Operating Current
—
—
—
10
5
mA
µA
µA
VDD = 5.5V, FOSC = 25 MHz,
FCLK = 1 MHz, SO = Open
IDDS
Standby Current (Sleep mode)
CS, TXnRTS = VDD, Inputs tied to
VDD or VSS, -40°C TO +85°C
8
CS, TXnRTS = VDD, Inputs tied to
VDD or VSS, -40°C TO +125°C
Note 1: This parameter is periodically sampled and not 100% tested.
DS21801G-page 72
2003-2012 Microchip Technology Inc.
MCP2515
TABLE 13-2: OSCILLATOR TIMING CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
(Note)
Oscillator Timing Characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
FOSC
Clock-In Frequency
1
1
40
25
MHz
MHz
4.5V to 5.5V
2.7V to 5.5V
TOSC
Clock-In Period
25
40
1000
1000
ns
ns
4.5V to 5.5V
2.7V to 5.5V
TDUTY
Duty Cycle
0.45
0.55
—
TOSH/(TOSH + TOSL)
(External Clock Input)
Note:
This parameter is periodically sampled and not 100% tested.
TABLE 13-3: CAN INTERFACE AC CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
CAN Interface AC Characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
Wake-up Noise Filter
100
—
ns
TWF
TABLE 13-4: RESET AC CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
RESET AC Characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
RESET Pin Low Time
2
—
µs
trl
2003-2012 Microchip Technology Inc.
DS21801G-page 73
MCP2515
TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
CLKOUT Pin AC/DC Characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
t CLKOUT CLKOUT Pin High Time
15
15
—
—
—
5
ns
ns
ns
TOSC = 40 ns (Note 1)
h
t CLKOUT CLKOUT Pin Low Time
TOSC = 40 ns (Note 1)
l
t CLKOUT CLKOUT Pin Rise Time
Measured from 0.3 VDD to 0.7 VDD
r
(Note 1)
t CLKOUT CLKOUT Pin Fall Time
—
5
ns
Measured from 0.7 VDD to 0.3 VDD
f
(Note 1)
t CLKOUT CLOCKOUT Propagation Delay
—
—
—
100
ns
ns
ns
Note 1
Note 1
d
15
16
t SOF
Start-Of-Frame High Time
2 TOSC
h
t SOF
Start-Of-Frame Propagation
Delay
2 TOSC +
0.5 TQ
Measured from CAN bit sample
point. Device is a receiver.
d
CNF1.BRP<5:0> = 0 (Note 2)
Note 1: All CLKOUT mode functionality and output frequency is tested at device frequency limits, however, CLKOUT prescaler
is set to divide by one. This parameter is periodically sampled and not 100% tested.
2: Design guidance only, not tested.
FIGURE 13-1:
START-OF-FRAME PIN AC CHARACTERISTICS
16
RXCAN
sample point
15
DS21801G-page 74
2003-2012 Microchip Technology Inc.
MCP2515
TABLE 13-6: SPI INTERFACE AC CHARACTERISTICS
Industrial (I):
Extended (E): TAMB = -40°C to +125°C
TAMB = -40°C to +85°C
VDD = 2.7V to 5.5V
VDD = 4.5V to 5.5V
SPI Interface AC Characteristics
Param.
No.
Sym
Characteristic
Clock Frequency
Min
Max
Units
Conditions
FCLK
TCSS
TCSH
TCSD
TSU
THD
TR
—
50
50
50
10
10
—
—
45
45
10
—
—
—
—
—
2
MHz
ns
1
2
3
4
5
6
7
8
9
CS Setup Time
CS Hold Time
ns
CS Disable Time
Data Setup Time
Data Hold Time
CLK Rise Time
CLK Fall Time
Clock High Time
Clock Low Time
ns
ns
ns
µs
µs
ns
Note 1
Note 1
TF
2
THI
—
—
TLO
ns
ns
10
11
12
13
14
TCLD
TCLE
TV
Clock Delay Time
50
50
—
0
—
—
ns
ns
ns
ns
ns
Clock Enable Time
Output Valid from Clock Low
Output Hold Time
45
—
THO
TDIS
Output Disable Time
—
100
Note 1: This parameter is not 100% tested.
2003-2012 Microchip Technology Inc.
DS21801G-page 75
MCP2515
NOTES:
DS21801G-page 76
2003-2012 Microchip Technology Inc.
MCP2515
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
18-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
MCP2515-I/P^
e
3
0434256
18-Lead SOIC (300 mil)
Example:
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
MCP2515
E/SO^
3
e
1035256
20-Lead TSSOP (4.4 mm)
Example:
XXXXXXXX
XXXXXNNN
YYWW
MCP2515
e
3
IST 256
1035
20-Lead QFN (4x4)
XXXXX
Example:
2515
XXXXXX
E/ML^
e
3
YWWNNN
035256
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2012 Microchip Technology Inc.
DS21801G-page 77
MCP2515
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1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢕꢜ1
DS21801G-page 78
2003-2012 Microchip Technology Inc.
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc.
DS21801G-page 79
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21801G-page 80
2003-2012 Microchip Technology Inc.
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc.
DS21801G-page 81
MCP2515
!ꢕꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ"#ꢌꢑꢇ$#%ꢌꢑ&ꢇ$ꢖꢅꢉꢉꢇ'ꢏꢋꢉꢌꢑꢄꢇꢒ$"ꢓꢇMꢇ()(ꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ"$$'ꢈꢛ
ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ
ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
D
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ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
ꢎꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢕꢂꢁꢘꢀ''ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ
-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ
1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕ<<1
DS21801G-page 82
2003-2012 Microchip Technology Inc.
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc.
DS21801G-page 83
MCP2515
!ꢕꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ*ꢏꢅꢆꢇ+ꢉꢅꢋ,ꢇꢜꢘꢇꢃꢄꢅꢆꢇꢈꢅꢍ&ꢅ-ꢄꢇꢒ.ꢃꢓꢇMꢇ(/(/ꢕ)0ꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ*+ꢜꢛ
ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ
ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
ꢀ
D
D2
EXPOSED
PAD
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E2
E
2
1
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1
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N
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BOTTOM VIEW
TOP VIEW
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A3
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A
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ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
ꢎꢂ ꢃꢆꢌ4ꢆꢑꢈꢀꢄ!ꢀ!ꢆ*ꢀ!ꢄꢅꢑ"ꢇꢆ&ꢈ#ꢂ
-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ
1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ
ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢁꢎ?1
DS21801G-page 84
2003-2012 Microchip Technology Inc.
MCP2515
ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ
ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
2003-2012 Microchip Technology Inc.
DS21801G-page 85
MCP2515
NOTES:
DS21801G-page 86
2003-2012 Microchip Technology Inc.
MCP2515
Revision A (May 2003)
APPENDIX A: REVISION HISTORY
• Original Release of this Document.
Revision G (August 2012)
The following is the list of modifications:
1. Updated content in Register 4-1, Register 4-12,
Register 4-13, Register 4-16, Register 4-17.
Revision F (October 2010)
The following is the list of modifications:
1. Added 20-lead QFN package (4x4) and related
information.
2. Updated Table 1-1.
3. Updated the Product Identification System
section.
Revision E (November 2007)
• Removed preliminary watermark.
• Updated templates.
• Updated register information.
• Updated package outline drawings.
Revision D (April 2005)
• Added Table 8-1 and Table 8-2 in Section 8.0
“Oscillator”. Added note box following tables.
• Changed address bits in column heading in
Table 11-1, Section 11.0 “Register Map”.
• Modified Section 14.0 “Packaging Information”
to reflect pb free device markings.
• Appendix A Revision History: Rearranged order of
importance.
Revision C (November 2004)
• Section 9.0 “RESET” added.
• Heading 12.1: added notebox.
Heading 12.6: Changed verbiage within
paragraph in Section 12.0 “SPI Interface”.
• Added Appendix A: Revision History.
Revision B (September 2003)
• Front page bullet: Standby current (typical) (Sleep
mode) changed from 10 µA to 1 µA.
• Added notebox for maximum frequency on
CLKOUT in Section 8.2 “CLKOUT Pin”.
• Section 12.0 “SPI Interface”, Table 12-1:
- Changed supply voltage minimum to 2.7V.
- Internal Capacitance: Changed VDD condition
to 0V.
- Standby Current (Sleep mode): Split
specification into -40°C to +85°C and
-40°C to +125°C.
2003-2012 Microchip Technology Inc.
DS21801G-page 87
MCP2515
NOTES:
DS21801G-page 88
2003-2012 Microchip Technology Inc.
MCP2515
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
–
PART NO.
Device
X
/XX
a) MCP2515-E/P: Extended Temperature,
18LD PDIP package.
Temperature
Range
Package
b) MCP2515-I/P:
Industrial Temperature,
18LD PDIP package.
c) MCP2515-E/SO: Extended Temperature,
18LD SOIC package.
Device:
MCP2515: CAN Controller with SPI Interface
MCP2515T: CAN Controller with SPI Interface
(Tape and Reel)
d) MCP2515-I/SO: Industrial Temperature,
18LD SOIC package.
e) MCP2515T-I/SO: Tape and Reel,
Industrial Temperature,
Temperature
Range:
I
E
= -40C to +85C (Industrial)
= -40C to +125C (Extended)
18LD SOIC package.
f)
MCP2515-I/ST: Industrial Temperature,
20LD TSSOP package.
Package:
P
=
=
=
=
Plastic DIP (300 mil Body), 18-Lead
Plastic SOIC (300 mil Body), 18-Lead
TSSOP, (4.4 mm Body), 20-Lead
Plastic QFN, (4x4 mm Body), 20-Lead
SO
ST
ML
g) MCP2515T-I/ST: Tape and Reel,
Industrial Temperature,
20LD TSSOP package.
h) MCP2515-E/ML: Extended Temperature,
20LD QFN package.
i)
MCP2515T-E/MLTape and Reel,
Extended Temperature,
20LD QFN package.
MCP2515-I/ML: Industrial Temperature,
20LD QFN package.
j)
k) MCP2515T-I/ML Tape and Reel,
Industrial Temperature,
20LD QFN package.
2003-2012 Microchip Technology Inc.
DS21801G-page 89
MCP2515
NOTES:
DS21801G-page 90
2003-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-504-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2003-2012 Microchip Technology Inc.
DS21801G-page 91
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Korea - Seoul
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/11
DS21801G-page 92
2012 Microchip Technology Inc.
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