UCS2113-2-V/G4 [MICROCHIP]
USB Dual-Port Power Switch and Current Monitor;型号: | UCS2113-2-V/G4 |
厂家: | MICROCHIP |
描述: | USB Dual-Port Power Switch and Current Monitor |
文件: | 总62页 (文件大小:900K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCS2113
USB Dual-Port Power Switch and Current Monitor
Features
Description
• Dual-Port Power Switches:
The UCS2113 is a dual USB port power switch
configuration which can provide 3.0A continuous
current (3.4A maximum) per VBUS port with precision
overcurrent limiting (OCL), port power switch enables,
auto-recovery fault handling, undervoltage and
overvoltage lockout, back-drive protection and
back-voltage protection, and thermal protection.
- 2.9V to 5.5V source voltage range
- 3.0A continuous current per VBUS port with
40 m On resistance per switch
- Independent port power switch enable pins
- DUAL fault ALERT# active drain output pins
- Constant Current or Trip mode current
limiting behaviors
The UCS2113 is well suited for both stand-alone and
applications having SMBus/I2C communications.
- Undervoltage and overvoltage lockout
- Back-drive, back-voltage protection
For applications with SMBus, the UCS2113 provides
per-port current monitoring and eight programmable
current limits per switch, ranging from 0.53A to 3.0A
continuous current (3.4A maximum). Per-port charge
rationing is also provided ranging from 3.8 mAh to
246.3 Ah.
- Auto-recovery fault handling with low test
current
- BOOST# logic output to increase DC-DC
converter output under large load conditions
• SMBus 2.0/I2C Mode Features:
In stand-alone mode, the UCS2113 provides eight
current limits for both switches, ranging from
0.53A + 0.53A to 3A + 3A total continuous current
(see Table 1-1).
- Eight programmable current limits assignable
to each power switch
- Other SMBus addresses available upon
request
Both power switches include an independent VBUS
discharge function and constant current mode current
limiting for BC1.2 applications.
- Block read and block write
• Self-Contained Current Monitoring (No External
Sense Resistor Required)
The UCS2113 is available in a 4x4 mm 20-pin QFN
package.
• Fully Programmable Per-Port Charge Rationing
and Behaviors
• Configurable Per-Port BC1.2 VBUS Discharge
Function
Package Type
UCS2113
4 x 4 QFN*
• Wide Operating Temperature Range:
- -40°C to +105°C
• UL Recognized and EN/IEC 60950-1 (CB)
Certified
• Passes Automotive AEC-Q100 Reliability Testing
20 19 18 17
16
PWR_EN1
GND
PWR_EN2
15
14
1
GND
2
3
4
EP
21
13
12
11
COMM_ILIM
VBUS2
BOOST#
VBUS1
VBUS2
VBUS1
5
6
7
8
9
10
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 1
UCS2113
Block Diagram
VS
VBUS
Power
Switch 1
UVLO,
OVLO
VS
VBUS
Power
Switch 2
VBUS
discharge
PWR_EN1
ALERT#1
Charger
Control,
Measurement,
OCL
Temp
PWR_EN2
ALERT#2
BOOST#
VDD
COMM_ILIM
SMCLK
SMDATA
GND
DS20005680B-page 2
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Voltage on VDD, VS, and VBUS pins...................................................................................................................-0.3 to 6V
Pull-Up Voltage (VPULLUP)..................................................................................................................... -0.3 to VDD + 0.3
Port Power Switch Current ..................................................................................................................... Internally limited
Voltage on any Other Pin to Ground ...................................................................................................-0.3 to VDD + 0.3V
Current on any Other Pin..................................................................................................................................... ±10 mA
Package Power Dissipation ........................................................................................................................See Table 1-1
Operating Ambient Temperature Range.................................................................................................-40°C to +105°C
Storage Temperature Range ..................................................................................................................-55°C to +150°C
†
Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
TABLE 1-1:
Board
POWER DISSIPATION SUMMARY
Derating Factor
Above +25°C
TA < +25°C
TA = +70°C
TA = +85°C
Package
JC
JA
Power Rating Power Rating Power Rating
High K
(Note)
20-pin QFN 6 °C/W 41 °C/W
4x4 mm
24.4 mW/°C
2193 mW
1498 mW
1095 mW
748 mW
729 mW
498 mW
Low K
(Note)
20-pin QFN 6 °C/W 60 °C/W
4x4 mm
16.67 mW/°C
Note:
A High-K board uses a thermal via design with the thermal landing soldered to the PCB ground plane with
0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multilayer with
1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. A Low-K board
is a two-layer board without thermal via design with 2-ounce copper traces on the top and bottom.
TABLE 1-2:
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V,
VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Power and Interrupts - DC
Supply Voltage
VDD
4.5
—
5
5.5
—
V
Supply Current in Active
IACTIVE
700
µA
Average current IBUS = 0 mA
(IDD_ACT + IS1_ACT + IS2_ACT
)
Supply Current in Sleep
ISLEEP
—
6
20
µA
Average current VPULLUP VDD
(IDD_SLEEP + IS1_SLEEP
IS2_SLEEP
Power-On Reset
+
)
V
DD Low Threshold
DD Low Hysteresis
VDD_TH
—
4
4.3
600
V
VDD voltage increasing (Note 1)
VDD voltage decreasing (Note 1)
V
VDD_TH_HYST
—
500
mV
Note 1: This parameter is characterized, not 100% tested.
2: This parameter is ensured by design and not 100% tested.
3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above
LIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).
I
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 3
UCS2113
TABLE 1-2:
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V,
V
PULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.
Characteristic Symbol Min. Typ. Max. Unit
I/O Pins - SMCLK, SMDATA, PWR_EN, ALERT#, BOOST# - DC Parameters
Conditions
Output Low Voltage
VOL
—
—
0.4
V
ISINK_IO = 8 mA
SMDATA, ALERT#, BOOST#
PWR_EN, SMDATA, SMCLK
PWR_EN, SMDATA, SMCLK
Input High Voltage
Input Low Voltage
Leakage Current
VIH
VIL
2.0
—
—
—
—
—
0.8
±5
V
V
ILEAK
—
µA
Powered or unpowered
VPULLUP VDD
TA < 85°C (Note 1)
Interrupt Pins - AC Parameters
ALERT# Pin Blanking Time
tBLANK
tMASK
tBOOST_MAT
IBOOST
—
—
—
—
25
5
—
—
—
—
ms
ms
s
Blanking time, coming out of
reset
ALERT# Pin Interrupt
Masking Time
BOOST# Pin Minimum
Assertion Time
1
BOOST# Pin Assertion
Current
1.9
A
SMBus/I2C Timing
Input Capacitance
Clock Frequency
Spike Suppression
Bus Free Time Stop to Start
Start Setup Time
Start Hold Time
CIN
fSMB
—
10
5
—
400
50
—
pF
kHz
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
—
—
—
—
—
—
—
—
—
—
—
—
tSP
—
tBUF
1.3
0.6
0.6
0.6
0
tSU:STA
tHD:STA
tSU:STO
tHD:DAT
tHD:DAT
tSU:DAT
tLOW
—
—
Stop Setup Time
Data Hold Time
—
—
When transmitting to the host
When receiving from the host
Data Hold Time
0.3
0.6
1.3
0.6
—
—
Data Setup Time
Clock Low Period
Clock High Period
Clock/Data Fall Time
—
—
tHIGH
—
tFALL
300
Min. = 20+0.1CLOAD ns
(Note 1)
Clock/Data Rise Time
tRISE
—
—
300
ns
Min. = 20+0.1CLOAD ns
(Note 1)
Capacitive Load
Timeout
CLOAD
tTIMEOUT
—
25
—
—
—
400
35
pF
ms
µs
Per bus line (Note 1)
Disabled by default (Note 1)
Disabled by default (Note 1)
Idle Reset
tIDLE_RESET
350
—
Note 1: This parameter is characterized, not 100% tested.
2: This parameter is ensured by design and not 100% tested.
3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above
LIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).
I
DS20005680B-page 4
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
TABLE 1-2:
Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V,
PULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.
ELECTRICAL SPECIFICATIONS (CONTINUED)
V
Characteristic
Port Power Switch
Port Power Switch - DC Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Overvoltage Lockout
VS Low Threshold
VS Low Hysteresis
On Resistance
VS_OV
—
—
—
—
—
6
—
—
—
—
5
V
V
Note 2
Note 2
Note 2
VS_UVLO
VS_UVLO_HYST
RON_PSW
2.5
100
40
mV
m 4.75V < VS < 5.25V
VS Leakage Current
ILEAK_VS
—
µA
mV
µA
Sleep state into VS pin on one
channel (Note 1)
Back-Voltage Protection
Threshold
VBV_TH
ILKG_1
—
—
150
0
—
3
VBUS > VS
VS > VS_UVLO
Leakage Current
VDD < VDD_TH,
Leakage current from VBUS pins
to the VDD and the VS pins
(Note 1)
ILKG_2
—
0
2
µA
VDD > VDD_TH,
Leakage current from VBUS pins
to the VS pins, when the power
switch is open
Selectable Current Limits
ILIM1
ILIM2
ILIM3
ILIM4
ILIM5
ILIM6
ILIM7
ILIM8
—
—
530
960
—
—
mA
mA
mA
mA
mA
mA
mA
mA
ILIM Resistor = 0 or 47 k
(530 mA setting)
ILIM Resistor = 10 k or 56 k
(960 mA setting)
—
1070
1280
1600
2130
2670
3200
—
ILIM Resistor = 12 k or 68 k
(1070 mA setting)
—
—
ILIM Resistor = 15 k or 82 k
(1280 mA setting)
—
—
ILIM Resistor = 18 k or 100 k
(1600 mA setting)
—
—
ILIM Resistor = 22 k or 120 k
(2130 mA setting)
2500
3000
2900
3400
ILIM Resistor = 27 k or 150 k
(2670 mA setting)
ILIM Resistor = 33 k or VDD
(3200 mA setting)
Pin Wake Time
SMBus Wake Time
Idle Sleep Time
tPIN_WAKE
tSMB_WAKE
tIDLE_SLEEP
TTSD_LOW
—
—
—
—
3
—
—
—
—
ms
ms
ms
°C
4
200
120
First Thermal Shutdown
Stage Threshold
Die Temperature at which the
power switch will open if it is in
constant current mode
TTSD_LOW_HYST
First Thermal Shutdown
Stage Hysteresis
—
10
—
°C
Hysteresis for TTSD_LOW func-
tionality. Temperature must drop
by this value before any of the
power switches can be closed.
Note 1: This parameter is characterized, not 100% tested.
2: This parameter is ensured by design and not 100% tested.
3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above
LIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).
I
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 5
UCS2113
TABLE 1-2:
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V,
VPULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Second Thermal Shutdown
Stage Threshold
TTSD_HIGH
—
135
—
°C
Die Temperature at which both
power switches will open
Second Thermal Shutdown
Stage Hysteresis
TTSD_HIGH_HYST
—
25
—
°C
Hysteresis for TTSD_HIGH
functionality. Temperature must
drop by this value before any of
the power switches can be
closed.
Auto-Recovery Test Current
Auto-Recovery Test Voltage
ITEST
—
—
190
750
—
—
mA
mV
Portable device attached,
VBUS= 0 V, Die temp < TTSD
VTEST
Portable device attached,
VBUS = 0 V before application,
Die temp < TTSD
Programmable, 250 - 1000 mV,
default listed
Discharge Impedance
RDISCHARGE
—
—
100
0.9
—
—
Port Power Switch - AC Parameters
Turn-On Delay
Turn-Off Time
Turn-Off Time
tON_PSW
ms
PWR_EN active toggle to
switch on time, VBUS discharge
not active
tOFF_PSW_INA
—
—
0.75
1
—
—
ms
ms
PWR_EN inactive toggle to
switch off time
CBUS = 120 µF
tOFF_PSW_ERR
Over-current Error, VBUS Min
Error, or Discharge Error to
switch off
CBUS = 120 µF
Turn-Off Time
tOFF_PSW_ERR1
—
—
100
1.1
—
—
ns
TSD or Back-drive Error to
switch off
CBUS = 120 µF
VBUS Output Rise Time
tR_BUS
ms
Measured from 10% to 90% of
VBUS, CLOAD = 220 µF
ILIM = 1.0A
Soft Turn-On Rate
IBUS/t
tDC_TEMP
tSHORT_LIM
—
—
—
100
200
1.5
—
—
—
mA/µs
ms
Temperature Update Time
Short-Circuit Response Time
µs
Time from detection of short to
current limit applied.
No CBUS applied
Short-Circuit Detection Time
Latched Mode Cycle Time
tSHORT
—
—
6
7
—
—
ms
ms
Time from detection of short to
port power switch disconnect
and ALERT# pin assertion
tUL
From PWR_EN edge transition
from inactive to active to begin
error recovery
Note 1: This parameter is characterized, not 100% tested.
2: This parameter is ensured by design and not 100% tested.
3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above
LIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).
I
DS20005680B-page 6
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
TABLE 1-2:
Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V,
PULLUP = 3V to 5.5V, TA = -40°C to 105°C. All typical values at VDD = VS = 5V, TA = 27°C.
ELECTRICAL SPECIFICATIONS (CONTINUED)
V
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Auto-Recovery Mode Cycle
Time
tCYCLE
—
25
—
ms
Time delay before error
condition check.
Programmable 15-50 ms,
default listed
Auto-Recovery Delay
Discharge Time
tTST
—
—
20
—
—
ms
ms
Portable device attached, VBUS
must be > VTEST after this time.
Programmable 10-25 ms,
default listed
tDISCHARGE
200
Amount of time discharge
resistor applied.
Programmable 100-400 ms,
default listed
Port Power Switch Operation With Trip Mode Current Limiting
Region 2 Current
Keep-Out
IBUS_R2MIN_1
—
—
0.1
A
V
Note 2
Note 2
Minimum VBUS
VBUS_MIN_1
2.0
—
—
Allowed at Output
Port Power Switch Operation With Constant Current Limiting (Variable Slope)
Region 2 Current
Keep-Out
IBUS_R2MIN
—
—
2.13
A
Note 2
Minimum VBUS
VBUS_MIN
2.0
—
—
V
Note 2
Allowed at Output
Current Measurement - DC
Current Measurement Range
IBUS_M
0
—
3400
—
mA
mA
Range (Note 2 and Note 3)
1 LSB
Reported Current
IBUS_M
—
13.3
Measurement Resolution
Current Measurement
Accuracy
—
—
±2
±2
—
—
%
200 mA < IBUS < ILIM
LSB IBUS < 200 mA
Current Measurement - AC
Sampling Rate
—
—
—
1.1
2.2
—
—
ms
ms
Note 2
Conversion Time
Both Channels
tCONV
All registers updated in digital
(Note 2)
Charge Rationing - DC
Accumulated Current
Measurement Accuracy
—
—
—
±4.5
—
—
%
s
Charge Rationing - AC
Current Measurement
Update Time
tPCYCLE
1
Note 1: This parameter is characterized, not 100% tested.
2: This parameter is ensured by design and not 100% tested.
3: The current measurement full scale range maximum value is 3.4A. However, the UCS2113 cannot report values above
LIM (if IBUS_R2MIN ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.6A).
I
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 7
UCS2113
T
T
T
T
SU:STO
LOW
HIGH
HD:STA
T
FALL
SMCLK
T
RISE
T
T
SU:DAT
SU:STA
T
HD:DAT
T
HD:STA
SMDATA
TBUF
S
S
P
P
S - Start Condition
P - Stop Condition
FIGURE 1-1:
SMBus Timing.
TEMPERATURE SPECIFICATIONS
TABLE 1-3:
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Temperature Range
Operating Junction Temperature
Storage Temperature Range
TA
TJ
TA
-40
-40
-55
—
—
—
+105
+125
+150
°C
°C
°C
Thermal Package Resistances - see Table 1-1
DS20005680B-page 8
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
1.1
ESD and Transient Performance
TABLE 1-4:
ESD RATINGS
ESD Specification
Rating or Value
Human Body Model (JEDEC JESD22-A114) - All pins
Charged Device Model (JEDEC JESD22-C101) - All pins
8 kV
500V
1.1.1
HUMAN BODY MODEL (HBM)
PERFORMANCE
HBM testing verifies the ability to withstand ESD
strikes, like those that occur during handling and
manufacturing, and is done without power applied to
the IC. To pass the test, the device must have no
change in operation or performance due to the event.
1.1.2
CHARGED DEVICE MODEL (CDM)
PERFORMANCE
CDM testing verifies the ability to withstand ESD
strikes, like those that occur during handling and
assembly, with pick-and-place-style machinery and is
done without power applied to the IC. To pass the test,
the device must have no change in operation or
performance due to the event.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 9
UCS2113
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.
6
6
5
6
5
4
3
2
1
0
-1
VBUS
VS = VDD = 5V
5
4
ILIM = 3A min (3.4A max), short applied at 2 ms
4
IBUS
3
3
2
2
1
1
VBUS
0
0
-1
-1
0
2
4
6
8
10
0
100
200
300
400
500
Time (ms)
Time (ms)
FIGURE 2-1:
Short Applied After
FIGURE 2-4:
V
Discharge Behavior.
BUS
Power-Up.
6
5
6
5
4
3
2
1
0
-1
45
40
35
30
25
20
15
10
5
VS = VDD
4
ALERT#
3
2
IBUS
1
0
0
-40
-15
10
35
60
85
110
-1
0
20
40
60
80
100
120
140
160
180
200
Temperature (°C)
Time (ms)
FIGURE 2-2:
Power-Up Into a Short.
FIGURE 2-5:
Power Switch On
Resistance vs. Temperature.
6
28
24
20
16
12
8
VS = VDD = 5V
ILIM = 2.13A (typical), short applied at 10 µs
5
1
VBUS
Turn on time
4
3
2
1
0
0,95
0,9
Turn off time
0,85
0,8
4
0,75
0,7
IBUS
-1
0
-2
0
-4
0,65
0,6
20
40
Time (µs)
-40
-15
10
35
60
85
110
Temperature (°C)
FIGURE 2-3:
Internal Power Switch Short
Response.
FIGURE 2-6:
Power Switch On/Off Time
vs. Temperature.
DS20005680B-page 10
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.
6.10
5
4
6.08
6.06
6.04
6.02
6.00
5.98
5.96
5.94
5.92
5.90
VDD = 5V
3
2
1
0
-1
-2
-3
-4
-5
-40
-15
10
35
60
85
110
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Temperature (°C)
Current (A)
FIGURE 2-7:
V Overvoltage Threshold
FIGURE 2-10:
I
Measurement
S
BUS
vs. Temperature.
Accuracy.
800
700
600
500
400
300
200
100
0
3.0
IDD + IS1 + IS2
VDD = 5V
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
IDD
Threshold
Hysteresis
IS1 + IS2
-40
-15
10
35
60
85
110
-40
-15
10
35
60
85
110
Temperature (°C)
Temperature (°C)
FIGURE 2-8:
V Undervoltage Threshold
FIGURE 2-11:
Active State Current vs.
S
vs. Temperature.
Temperature (both channels on,
PWR_EN1 = PWR_EN2 = 1).
0%
-2%
VS = VDD = 5V
ILIM = 3.0A min. (3.2A typ., 3.4A max.)
Note: The percentage is relative to the
maximum specification (3.4A)
-4%
-6%
-8%
-10%
-12%
-40
-15
10
35
60
85
110
Temperature (°C)
FIGURE 2-9:
Trip Current Limit Operation
vs. Temperature.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 11
UCS2113
Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.
14
12
10
60%
50%
40%
30%
20%
10%
0%
IDD + IS1 + IS2
8
6
IDD
4
2
IS1 + IS2
0
-40
-15
10
35
60
85
110
VBUS Current (A)
Temperature (°C)
FIGURE 2-12:
Temperature.
Sleep State Current vs.
FIGURE 2-15:
Distribution .
ILIM3 Trip Current
(1)
60%
50%
40%
30%
20%
10%
0%
60%
50%
40%
30%
20%
10%
0%
VBUS Current (A)
VBUS Current (A)
FIGURE 2-16:
ILIM4 Trip Current
FIGURE 2-13:
Distribution.
ILIM1 Trip Current
(1)
Distribution
.
60%
50%
40%
30%
20%
10%
0%
60%
50%
40%
30%
20%
10%
0%
VBUS Current (A)
VBUS Current (A)
FIGURE 2-17:
ILIM5 Trip Current
FIGURE 2-14:
ILIM2 Trip Current
(1)
(1)
Distribution
.
Distribution
.
Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two
VBUS channels.
DS20005680B-page 12
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C.
60%
50%
40%
30%
20%
10%
0%
VBUS Current (A)
FIGURE 2-18:
ILIM6 Trip Current
Distribution.
60%
50%
40%
30%
20%
10%
0%
VBUS Current (A)
FIGURE 2-19:
ILIM7 Trip Current
Distribution.
60%
50%
40%
30%
20%
10%
0%
VBUS Current (A)
FIGURE 2-20:
ILIM8 Trip Current
Distribution.
Note 1: The histogram aspect is caused by a mixture of two normal distributions, corresponding to the two
VBUS channels.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 13
UCS2113
3.0
PIN DESCRIPTION
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Symbol Function
PWR_EN1 Port power switch enable #1
UCS2113
4x4 QFN
Connection Type if Pin
Not Used
Pin Type
1
DI
Connect to ground or VDD
(depending on the polarity
decoded via COMM_ILIM
pin)
2
3
GND
Ground
Power
OD
N/A
BOOST#
Logic output for DC-DC converter voltage
increase (requires pull-up resistor)
Connect to ground
4, 5
6, 7
VBUS1
VS
Port power switch #1 output (requires both
pins tied together)
High Power, Leave open
AIO
Voltage input to port power switch VBUS1
(requires both pins
High Power, Connect to ground
AIO
tied together)
8
VDD
VS
Common supply voltage
Power
N/A
9, 10
Voltage input to port power switch VBUS2
(requires both pins
High Power, Connect to ground
AIO
tied together)
11, 12
VBUS2
Port power switch #2 output (requires both
pins tied together)
High Power, Leave open
AIO
13
COMM_ILIM Enables SMBus or Stand-Alone mode at
power-up. Hardware strap for maximum cur-
rent limit.
AIO
N/A
14
15
GND
Ground
Power
DI
N/A
PWR_EN2 Port power switch enable #2
Connect to ground or VDD
(depending on the polarity
decoded via COMM_ILIM
pin)
16
17
ALERT#2 Output fault ALERT for VBUS2 (requires
pull-up resistor)
OD
DI
Connect to ground
SMCLK
SMDATA
GND
SMCLK - SMBus clock input (requires pull-up
resistor)
Connect to VPULLUP(or to
ground in Stand-Alone
mode)
18
SMDATA - SMBus data input/output (requires
pull-up resistor)
DIOD
Connect to VPULLUP (or to
ground in Stand-Alone
mode)
19
20
Ground
Power
OD
N/A
ALERT#1 Output fault ALERT for VBUS1 (requires
pull-up resistor)
Connect to ground
21
EP
Exposed thermal pad. Must be connected to
electrical ground.
EP
N/A
DS20005680B-page 14
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
TABLE 3-2:
Pin Type
Power
PIN TYPES
Description
This pin is used to supply power or ground to the device
Hi-Power This pin is a high-current pin
AIO
DI
Analog Input/Output - this pin is used as an I/O for analog signals
Digital Input - this pin is used as a digital input
DIOD
OD
Open-Drain Digital Input/Output - this pin is bidirectional. It is open-drain and requires a pull-up resistor.
Open-Drain Digital Output - used as a digital output. It is open-drain and requires a pull-up resistor.
Exposed thermal pad
EP
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 15
UCS2113
4.0
TERMS AND ABBREVIATIONS
Note:
The PWR_EN1 and PWR_EN2 pins each have configuration bits (“<pin name>_S” in General
Configuration 1 register (Address 11h) and General Configuration 2 register (Address 12h)) that may be
used to perform the same function as the external pin state. These bits are accessed via the SMBus/I2C
and are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced as
the <pin name> control.
TABLE 4-1:
TERMS AND ABBREVIATIONS
Term/Abbreviation
Description
CC
Constant Current
Current Limiting
Mode
Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip
opens the port power switch. Constant Current (variable slope) allows VBUS to be dropped by
the portable device.
IBUS_R2MIN
ILIM
Current limiter mode boundary
The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the
port power switch is opened. In Constant Current mode, when the current exceeds ILIM
,
operation continues at a reduced voltage and increased current; if VBUS voltage drops below
VBUS_MIN, the port power switch is opened.
OCL
Overcurrent limit
POR
Power-on Reset
Portable Device
Stand-Alone Mode
USB device attached to the USB port
Indicates that the communications protocol is not active and all communications between the
UCS2113 and a controller are done via the external pins only (PWR_EN1 and PWR_EN2 as
inputs, and ALERT1# and ALERT2# as outputs)
DS20005680B-page 16
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
5.0
GENERAL DESCRIPTION
The UCS2113 is a dual-port power switch. Two USB
power ports are supported with current limits up to 3.0A
continuous current (3.4A maximum) each. Selectable
and programmable current limiting configurations are
also available to the application. A typical block
diagram is shown in Figure 5-1.
D+
D-
VBUS
SMDAT
SMCLK
USB Port 1
Connector
VBUS1
ALERT1
PWR_EN1
D+
D-
PD_ALERT1
UCS2113
VBUS2
ALERT2
PWR_EN2
2 PORT HUB
VBUS
D+
D-
D+
D-
PD_ALERT2
USB Port 2
Connector
FIGURE 5-1:
Typical USB Application.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 17
UCS2113
5.1
UCS2113 Power States
Power states are indicators of the device’s current
consumption in the system and the functionality of the
digital logic. Table 5-1 details the UCS2113 power
states.
TABLE 5-1:
State
POWER STATES DESCRIPTION
Description
Off
This power state is entered when the voltage at the V pin voltage is < V
considered “off”. The UCS2113 will not retain its digital states and register contents nor respond to SMBus/I C
. In this state, the device is
DD_TH
DD
2
communications. The port power switch will be off. See Section 5.1.1 “Off State Operation”.
Sleep
Error
This is the lowest power state available. While in this state, the UCS2113 will retain digital functionality and wake
to respond to SMBus/I C communications. See Section 5.1.2 “Sleep State Operation”.
2
This power state is entered when a fault condition exists. Error power state is one or both channels in Fault
Handling. This state is updated as Priority One. The Interrupt Status Registers for each channel will update the
fault detected per channel. Only the channel that has detected a Fault will be affected since the other channel
can remain active if no fault is detected. See Section 5.1.4 “Error State Operation”.
Active Active power State is one, or both channels active and sourcing current to the V
Port. This state is updated
BUS
as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in
this state, operations include activation of the port power switch, current limiting, and charge rationing. See
Section 5.1.3 “Active State Operation”.
Table 5-2 shows the settings for the various power
states, except Off and Error. If VDD < VDD_TH, the
UCS2113 is in the Off state.
TABLE 5-2:
Power
POWER STATES CONTROL SETTINGS
PWR_EN1 PWR_EN2
Behavior
State
Sleep
disabled
disabled
• All switches disabled
• VBUS will be near ground potential
• The UCS2113 wakes to respond to SMBus
communications
Active enabled
disabled
disabled
enabled
enabled
• Port power switch is on for VBUS1
• VBUS2 pins are near ground potential or floating (Note 1)
• Port power switch is on for VBUS2
• VBUS1 pins are near ground potential or floating (Note 1)
• Port power switch is on for VBUS1 and VBUS2
enabled
Note 1: If the bit EN_VBUS_DISCHG is '1', the VBUS is discharged automatically and VBUS is near ground
potential. If the bit EN_VBUS_DISCHG is '0' then the corresponding VBUS pins are floating (VBUS
discharge is controlled by the SMBus host).
potential. The ALERT#1 and ALERT#2 pins will not be
asserted. If asserted prior to entering the Sleep state,
the ALERT# pin will be released. SMBus activity is lim-
ited to single byte read or write.
5.1.1
OFF STATE OPERATION
The device will be in the Off state if VDD is less than
VDD_TH. When the UCS2113 is in the Off state, it will do
nothing and all circuitry will be disabled. Digital register
values are not stored and the device will not respond to
SMBus commands.
The first data byte read from the UCS2113 when it is in
the Sleep state will wake it; however, the data to be
read will return all 0’s and should be considered invalid.
This is a “dummy” read byte meant to wake the
UCS2113. Subsequent read or write bytes will be
accepted normally. After the dummy read, the
UCS2113 will be in a higher power state (see
Figure 5-2). After communication has not occurred for
tIDLE_SLEEP, the UCS2113 will return to Sleep.
5.1.2
SLEEP STATE OPERATION
The PWR_EN1 and PWR_EN2 pins may be used to
cause the UCS2113 to enter/exit Sleep. These pins are
AND’ed for Sleep mode.
When the UCS2113 is in the Sleep state, the device will
be in its lowest power state. The port power switch will
be disabled. VBUS1 and VBUS2 will be near ground
DS20005680B-page 18
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
SMBus Read
Dummy read returns invalid data
and places device in temporary
Read returns valid data
0101_1110 0001_0000 0101_1111
Active state
0101_1110 0001_0000
0101_1111
A invalid dataN P
S
A
A S
S
A
A S
A
valid data N P
tSMB_WAKE
tIDLE_SLEEP
temporary Active state
(not all functionality available)
Power State
Sleep
Sleep
FIGURE 5-2:
Wake from Sleep using SMBus Read.
When the UCS2113 enters the Error state, the port
power switch will be disabled while the ALERT# pin is
asserted. It will remain off while in this power state. The
UCS2113 will leave this state as determined by the fault
handling selection.
5.1.3 ACTIVE STATE OPERATION
Every time the UCS2113 enters the Active state, the
port power switches are closed. The UCS2113 cannot
be in the Active state (and therefore, the port power
switch cannot be turned on) if any of the following
conditions exist:
With the Auto-recovery fault handler, after the tCYCLE
time period, the UCS2113 will check that all of the error
conditions have been removed.
• VS < VS_UVLO
• PWR_EN1 and PWR_EN2 are disabled.
If all of the error conditions have been removed, the
UCS2113 will return to the Active state.
5.1.4
ERROR STATE OPERATION
If both PWR_EN1 and PWR_EN2 controls transition
from active to inactive while the UCS2113 is in the Error
state, the device will not enter the Sleep state. After the
fault has been removed, the UCS2113 will not automat-
ically enter the Sleep state if the EN_VBUS_DISCHG
bit from the General Configuration 2 Register is not set
(default setting). To enter the Sleep state, the PWR_EN
pins must be toggled or an SMBus read register com-
mand must be sent.
The UCS2113 will enter the Error state from the Active
state when any of the following events are detected:
• The maximum allowable internal die temperature
(TTSD_HIGH) has been exceeded.
• The TTSD_LOW die temperature has been
exceeded and any of the following conditions is
met:
- a power switch operates in constant current
mode
5.2
Communication
- PWR_EN1 and/or PWR_EN2 controls
transition from inactive to active.
The UCS2113 can operate in SMBus mode (see
Section 7.0 “System Management Bus Protocol”)
or Stand-Alone mode. The resistor connected to the
COMM_ILIM pin determines the operating mode and
the hardware-set ILIM setting, as shown in Table 5-3.
Unless connected to GND or VDD, the resistors in
Table 5-3 are external pull-down resistors.
- it is a power up situation and PWR_EN1
and/or PWR_EN2 pins are active.
• An overcurrent condition has been detected.
• An undervoltage condition on either VBUS pin has
been detected (see Section 5.3.4 “Undervoltage
Lockout on VS”).
• A back-voltage condition has been detected (see
Section 5.3.2 “Back-voltage Detection”).
The SMBus address is specified in Section 7.2
“SMBus Address and RD/WR Bit”.
• A discharge error has been detected.
• An overvoltage condition on the VS pin.
TABLE 5-3:
COMMUNICATION DECODE
COMM_ILIM Pull Down
Resistor (±1%)
PWR_EN1 and
PWR_EN2 Polarity
Total ILIM (A)
(Note 1)
Communication
Mode
ILIM (A)
GND
10 k
12 k
15 k
18 k
Active-High
Active-High
Active-High
Active-High
Active-High
0.53
0.96
1.07
1.28
1.6
0.53 + 0.53
0.96 + 0.96
1.07 + 1.07
1.28 + 1.28
1.6 + 1.6
SMBUS
SMBUS
SMBUS
SMBUS
SMBUS
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 19
UCS2113
TABLE 5-3:
COMMUNICATION DECODE (CONTINUED)
COMM_ILIM Pull Down
Resistor (±1%)
PWR_EN1 and
PWR_EN2 Polarity
Total ILIM (A)
(Note 1)
Communication
Mode
ILIM (A)
22 k
27 k
33 k
47 k
56 k
68 k
82 k
100 k
120 k
150 k
VDD
Active-High
Active-High
Active-High
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
2.13
2.67
3.2
2.13 + 2.13
2.67 + 2.67
3.2 + 3.2
SMBUS
SMBUS
SMBUS
0.53
0.96
1.07
1.28
1.6
0.53 + 0.53
0.96 + 0.96
1.07 + 1.07
1.28 + 1.28
1.6 + 1.6
Stand-Alone
Stand-Alone
Stand-Alone
Stand-Alone
Stand-Alone
Stand-Alone
Stand-Alone
Stand-Alone
2.13
2.67
3.2
2.13 + 2.13
2.67 + 2.67
3.2 + 3.2
Note 1: The total maximum current depends on power dissipation characteristics of the design (see Table 1-1).
5.3.3
BACK-DRIVE CURRENT
PROTECTION
5.3
Supply Voltages
5.3.1
V
SUPPLY VOLTAGE
DD
If a portable device is attached that is self-powered, it
may drive the VBUS port to its power supply voltage
level; however, the UCS2113 is designed such that
leakage current from the VBUS pins to the VDD and/or
the VS pin shall not exceed ILKG_1 (if the VDD and/or VS
voltage is zero) or ILKG_2 (if the VDD and/or VS voltage
exceeds VDD_TH and the power switch is open).
The UCS2113 requires 4.5V to 5.5V to be present on
the VDD pin for core device functionality. Core device
functionality consists of maintaining register states and
wake-up upon SMBus/I2C query.
5.3.2
BACK-VOLTAGE DETECTION
The back-voltage detector is functional in all power
states (Sleep and Active).
5.3.4
UNDERVOLTAGE LOCKOUT ON V
S
The UCS2113 requires a minimum voltage (VS_UVLO
be present on the VS pin for Active power state.
)
When in Sleep, the UCS2113 will enter the Error state
from Sleep if a back-voltage condition was detected.
5.3.5
OVERVOLTAGE DETECTION AND
LOCKOUT ON VS
Whenever the following condition is true for either port,
the port power switch will be disabled and a
back-voltage event will be flagged. This will cause the
UCS2113 to enter the Error power state (see
Section 5.1.4 “Error State Operation”).
Both power switches will be disabled if the voltage on
any VS pin exceeds a voltage (VS_OV) for longer than
the specified time (tMASK). This will cause the device to
enter the Error state and both ALERT#1 and ALERT#2
pins will be asserted.
Note:
The VBUS voltage exceeds the VS and/or
the VDD pin voltage by VBV_TH and the
port power switch is closed. The port
power switch will be opened immediately.
5.3.6
PWR_EN1 AND PWR_EN2 INPUT
The PWR_EN control affects the power state and enables
the port power switch to be turned on if conditions are met
(see Table 5-2). The port power switch cannot be closed
if PWR_EN is disabled. However, if PWR_EN is enabled,
the port power switch is not necessarily closed (see
Section 5.1.3 “Active State Operation”). In SMBus
mode, the PWR_EN1 and PWR_EN2 pins states will be
ignored by the UCS2113 if the PIN_IGN configuration bit
is set; otherwise, the PWR_EN1S and PWR_EN2S
configuration bits are checked along with the pins.
If the condition lasts for longer than tMASK
,
then the UCS2113 will enter the Error
state. Otherwise, the port power switch
will be turned on as soon as the condition
is removed.
DS20005680B-page 20
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
The UCS2113 is compatible with the Microchip hub
devices supporting single pin power control feature.
These hub devices have a single connection to the
PWR_EN and ALERT# pins of the UCS2113, which are
tied together in the application.
5.4
Discrete Output Pins
5.4.1
ALERT#1 AND ALERT#2 OUTPUT
PINS
The UCS2113 has two independent ALERT# out pins.
ALERT#1 is tied to the status of the VBUS1 pin.
ALERT#2 is tied to the status of the VBUS2 pin.
5.4.2
BOOST# OUTPUT PIN
The UCS2113 provides a BOOST# output pin to
compensate for voltage drops during high loads. The
BOOST# pin is an active-low, open-drain output that
would be connected to a resistor in the DC-DC
converter’s feedback error voltage loop (see
Figure 5-3).
The ALERT# pin is an active-low open-drain interrupt
to the host controller. The ALERT# pin is asserted
when an error occurs. Also, when charge rationing is
enabled, the ALERT# pin is asserted by default when
the current rationing threshold is reached (as
determined by RATION_BEH<1:0>). The ALERT# pin
is released when all error conditions that may assert
the ALERT# pin (such as an error condition and charge
rationing) have been removed or reset as necessary.
The
BOOST#
pin
is
asserted
when
VBUS Current > IBOOST. IBOOST typical value is 1.9A.
The BOOST# is OR’ed for both VBUS1 and VBUS2 ports.
When the BOOST# pin is asserted, it will remain in this
state for at least tBOOST_MAT (minimum assertion time).
R + R + R V
FB
1
2
3
5V
= -------------------------------------------------------
OUT
R
3
R + R R V
FB
2
3
1
V
= -------------------------------------------------------
OUT
OUT
R
R
3
4
R
V
FB
5V
R
1
OUT
1
------------------------
V
=
------------------- – ------
R
V
R
4
FB
3
5V
R
OUT
1
R
R
--------------------------------
If
V
1
3
OUT
R
4
5.0VOUT
PWR_EN1
1
2
3
4
5
15 PWR_EN2
14 GND
R1
GND
R4
BOOST#
UCS2113
20-QFN 4 x 4 mm
13 COMM_ILIM
DC-DC
Converter Block
VBUS1
VBUS1
12
11
VBUS2
VBUS2
R2
FeedBack
VFB
R3
GND
GND FLAG
FIGURE 5-3:
Boost# Pin Usage.
5.5.3
SMDATA
5.5
Discrete Input Pins
When used in Stand-Alone, this pin should be tied to
ground.
5.5.1
The
COMM_ILIM INPUT
COMM_ILIM input
determines
the
When the UCS2113 is configured for SMBus
communications, the SMDATA is the data input/output.
communications mode, as shown in Table 6-1. This is
also the hardware strap for MAX Current Limit.
5.5.2
SMCLK
When operated in Stand-Alone mode, this pin should be
tied to ground. When the UCS2113 is configured for
SMBus communications, the SMCLK is the clock input.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 21
UCS2113
6.0
USB PORT POWER SWITCH
TABLE 6-1:
I
DECODE
LIM
To assure compliance to various charging
specifications, the UCS2113 contains a USB port
power switch that supports two current-limiting modes:
Trip and Constant current (variable slope). The current
limit (ILIM) is pin selectable (and may be updated via
the register set). The switch also includes soft start
circuitry and a separate short circuit current limit.
COMM_ILIM PWR_EN1
Total ILIM
(A)
(Note 1)
Pulldown
Resistor
(±1%)
and
PWR_EN2
Polarity
ILIM (A)
GND
10 kΩ
12 kΩ
15 kΩ
18 kΩ
22 kΩ
27 kΩ
33 kΩ
47 kΩ
56 kΩ
68 kΩ
82 kΩ
100 kΩ
120 kΩ
150 kΩ
VDD
Active-High
Active-High
Active-High
Active-High
Active-High
Active-High
Active-High
Active-High
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
Active-Low
0.53
0.96
1.07
1.28
1.6
0.53+0.53
0.96+0.96
1.07+1.07
1.28+1.28
1.6+1.6
The port power switch is on in the Active state (except
when VBUS is discharging).
6.1
Current Limiting
2.13
2.67
3.2
2.13+2.13
2.67+2.67
3.2+3.2
6.1.1
CURRENT LIMIT SETTING
The UCS2113 hardware set current limit, ILIM, can be
one of eight values. This resistor value is read once
upon UCS2113 power-up. The current limit can be
changed via the SMBus/I2C after power-up; however,
the programmed current limit cannot exceed the hard-
ware set current limit. Unless connected to VDD, the
resistors in Table 6-1 are pull-down resistors.
0.53
0.96
1.07
1.28
1.6
0.53+0.53
0.96+0.96
1.07+1.07
1.28+1.28
1.6+1.6
At power-up, the communication mode (Stand-Alone
or SMBus/I2C) and hardware current limit (ILIM) are
determined via the pull-down resistor (or pull-up
resistor if connected to VDD) on the COMM_ILIM pin,
as shown in Table 6-1.
2.13
2.67
3.2
2.13+2.13
2.67+2.67
3.2+3.2
Note 1: The total maximum current depends on
power dissipation characteristics of the
design (see Table 1-1).
6.1.2
SHORT CIRCUIT OUTPUT
CURRENT LIMITING
6.1.4
CURRENT LIMITING MODES
Short circuit current limiting occurs when the output
current is above the selectable current limit (ILIMx).
This event will be detected and the current will
immediately be limited (within tSHORT_LIM time). If the
condition remains, the port power switch will flag an
Error condition and enter the Error state.
The UCS2113 current limiting has two modes: Trip and
Constant Current (variable slope). Either mode
functions at all times when the port power switch is
closed.
6.1.4.1
Trip Mode
6.1.3
SOFT START
When using Trip current limiting, the UCS2113 USB
port power switch functions as a low-resistance switch
and rapidly turns off if the current limit is exceeded.
While operating using Trip current limiting, the VBUS
output voltage will be held relatively constant (equal to
the VS voltage minus the RON x IBUS current) for all
When the PWR_EN control changes states to enable the
port power switch, the UCS2113 invokes a soft start
routine for the duration of the VBUS rise time (tR_BUS).
This soft start routine will limit current flow from VS into
VBUS while it is active. This circuitry will prevent current
spikes due to a step in the portable device current draw.
current values up to the ILIM
.
In the case when a portable device is attached while the
PWR_EN pin is already enabled, if the bus current
exceeds ILIM, the UCS2113 current limiter will respond
within a specified time (tSHORT_LIM) and will operate
normally at this point. The CBUS capacitor will deliver the
extra current, if any, as required by the load change.
If the current drawn by a portable device exceeds ILIM
the following occurs:
,
1. The port power switch will be turned off (Trip
action).
2. The UCS2113 will enter the Error state and
assert the ALERT# pin.
3. The fault handling circuitry will then determine
subsequent actions.
DS20005680B-page 22
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
Figure 6-1 shows operation of current limits in Trip
mode with the shaded area representing the USB 2.0
specified VBUS range. Dashed lines indicate the port
power switch output will go to zero (e.g., Trip) when
ILIM is exceeded. Note that operation at all possible
values of ILIM are shown in Figure 6-1 for illustrative
purposes only; in actual operation only one ILIM can be
active at any time.
Figure 6-3 shows operation of current limits while
using CC mode. Unlike Trip mode, once IBUS current
exceeds ILIM, operation continues at a reduced voltage
and increased current. Note that the shaded area rep-
resenting the USB 2.0 specified VBUS range is now
restricted to an upper current limit of IBUS_R2MIN. Note
that the UCS2113 will heat up along each load line as
voltage decreases. If the internal temperature exceeds
the TTSD_LOW threshold, the corresponding power
switch operating in constant current mode will open. If
the internal temperature exceeds the TTSD_HIGH
threshold, both power switches will open, regardless
of whether the power switch channels are in current
limit. Also note that when the VBUS voltage is brought
low enough (below VBUS_MIN), the port power switch
will open.
ILIM (Amps)
Operating
Current
0.53
0.96 1.07 1.28
1.6
2.13
2.67
3.2
5.25
5
4.75
= ILIM’s
Trip action
(ILIM = 0.53 A)
4
Trip action
(ILIM = 3.2 A)
ILIM (Amps)
1.28
3
2
1
0
0.53
0.96
1.6 2.13
2.67
3.2
5.25
5
4.75
IBUS_R2MIN
= ILIM’s
4
3
2
1
0
Constant resistance
IBUS operation line
(ILIM = 1.6 A)
Power Switch Voltage and Current
Output go to Zero when ILIM is
Exceeded
4
Constant resistance
IBUS operation line 1
(ILIM = 0.53 A)
0.96 1.07 1.28
1.6
2.13
2.67
3.2
0
0.53
IBUS (Amps)
FIGURE 6-1:
6.1.4.2
Current Limiting in Trip Mode.
CC Mode - Power switch current increases as voltage decreases
when ILIM is exceeded following constant resistance lines
Constant Current Limiting (Variable
Slope)
Constant current limiting is used when the current
drawn is greater than ILIM (and ILIM < 1.6A). In CC
mode, the port power switch allows the attached
portable device to reduce VBUS output voltage to less
than the input VS voltage while maintaining current
delivery. The V/I slope depends on the user set ILIM
value. This slope is held constant for a given ILIM
value.
0.96
1.28
IBUS (Amps)
1.6 2.13
2.67
3.2
0.53
0
FIGURE 6-3:
Current Limiting in CC Mode.
6.2
USB Port Power Profiles
The UCS2113 combines the qualities of traditional
USB port power switches with USB port power profiles
set forth in the USB-IF BC1.2 specification. USB port
power profiles consist of distinct voltage-current
operation regions defined by “keep-out” and
“operation” regions.
This mode is specifically provided for devices that rely
on resistive means to reduce VBUS voltage for direct
battery charging or to allow portable devices a means
to “test” charger capacity. See Figure 6-2.
While operating in the CC mode of operation, the
UCS2113 provides voltage-current output operating
profiles that are specified by two keep-out regions.
IBUS
VS
VBUS << VS
Power
Switch
Battery
Charger
IC
ILIM
Control Loop
RSense
VBAT
5V DC
Temp
If the current reaches the IBUS_R2MIN setting for longer
than tMASK, the UCS2113 enters the Error state and an
Overcurrent event is flagged.
GND
UCS 2112
Portable Device
FIGURE 6-2:
Constant Current Example.
If the VBUS voltage ever goes below the no operation
lower-voltage keep-out (VBUS_MIN) value for longer
than tMASK, the port power switch is disabled and a
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 23
UCS2113
keep-out violation is flagged (by setting the
MIN_KEEP_OUT status bit). This will cause the device
to enter the Error state.
6.2.2
OPERATION OUTSIDE OF A USB
PORT POWER PROFILE
An attached device may be allowed to operate outside
of the boundaries of a USB port power profile by
setting the value of ILIM greater than the USB port
power profile IBUS_R2MIN value. This is the default
operation for all portable devices. In this case, the
USB port power switch will operate in Trip mode until
the bus current reaches the ILIM value. Once the ILIM
value has been exceeded, the port power switch will
open and terminate charging. Figure 6-5 illustrates an
example of current limiting in this configuration.
Figure 6-4 illustrates the relationship between these
USB port power profile parameters.
6.2.1
OPERATION WITHIN A USB PORT
POWER PROFILE
An attached device may be constrained to operate
within the boundaries of a USB port power profile by
setting the value of ILIM less than the USB port power
profile IBUS_R2MIN value. In this case, the port power
switch will be in Trip mode up until ILIM is exceeded. At
which point, the switch will transition into CC mode. If
the attached device reduces the output voltage to less
than VBUS_MIN, the switch will trip and terminate
charging.
ILIM (Amps)
0.53
0.96
1.28
1.6
2.13 2.67
3.2
5.25
5
4.75
ILIM = 2.67 A
ILIM (Amps)
4
3
2
1
0
0.53
0.96
1.28
1.6 2.13
2.67
3.2
5.25
5
4.75
Port Power Profile
Operating Region
ILIM = 1.6A
IBUS_R2MINꢀ = 1.ꢁ A
4
3
2
1
0
IBUS_R2MIN = 1.6A
Port Power Profile
Operating Region
VBUS_MIN = 2.0 V
(Trip)
VBUS_MIN = 2.0 V
0.96
1.28
1.6 2.13 2.67
3.2
0.53
0
IBUS (Amps)
(Trip)
FIGURE 6-5:
I
> I
Example.
LIM
BUS_R2MIN
0.96
1.28
IBUS (Amps)
1.6 2.13 2.67
3.2
0.53
0
FIGURE 6-4:
Note:
I
< I
Example.
BUS_R2MIN
LIM
The CC mode of operation is possible only
up to 1.6A. As long as the value of ILIM is
less than the fixed port power profile
IBUS_R2MIN value, CC mode is possible.
Otherwise, the USB port power switch will
operate in Trip mode operation.
DS20005680B-page 24
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
6.3.0.2
THE SECOND THERMAL
SHUTDOWN STAGE (T
6.3
Thermal Protection
)
TSD_HIGH
The UCS2113 utilizes two-stage internal thermal
management. The first is triggered when the die
temperature exceeds TTSD_LOW threshold and the
second is triggered when the die temperature exceeds
TTSD_HIGH threshold.
The second thermal protection stage turns off both
power switches when the die temperature exceeds
TTSD_HIGH threshold, regardless of whether the power
switch channels are in current limit. It also causes both
channels to enter in error state and both ALERT#1 and
ALERT#2 pins to be asserted.
6.3.0.1
THE FIRST THERMAL
SHUTDOWN STAGE (T
)
The error state will persist and the power switches
cannot be closed until the temperature is below
TTSD_HIGH - TTSD_HIGH_HYST
TSD_LOW
The first stage turns off the individual power switch
channel when the die temperature exceeds TTSD_LOW
threshold and a power switch operates in constant
current mode. It also causes the corresponding
channel to enter in error state and the corresponding
ALERT# pin will be asserted.
.
6.4
VBUS Discharge
When the EN_VBUS_DISCHG bit from General
Configuration 2 Register is set (by default it is not set),
the UCS2113 will discharge VBUS through an internal
100 resistor when at least one of the following
conditions occur:
When an over-current condition appears, the power
switch operates in constant current mode for the
duration of tMASK time. Because of the increased
voltage drop across the switch, the die temperature
increases. If the die temperature exceeds TTSD_LOW
threshold before the expiration of the tMASK time, then
the power switch will open immediately.
• The PWR_EN control is disabled (triggered on the
inactive edge of the PWR_EN control).
• The VS voltage drops below a specified threshold
(VS_UVLO) that causes the port power switch to be
disabled.
If the TTSD_LOW threshold has been exceeded, but the
die temperature has not decreased below the
TTSD_LOW recovery threshold, then the power switch
cannot be closed when commanded by the PWR_EN1
or PWR_EN2 controls in the following situations:
• When commanded into the Sleep power state.
• Upon recovery from the Error state.
• When commanded via the SMBus in the Active
state.
• PWR_EN1 and/or PWR_EN2 controls transition
from inactive to active.
When the automatic VBUS discharge circuitry is
activated, the UCS2113 will confirm that VBUS was
discharged at the end of the tDISCHARGE time. If the
VBUS voltage is not below the VTEST level, a discharge
error will be flagged (by setting the DISCH_ERR(1/2)
status bit) and the UCS2113 will enter the Error state.
• it is a power up situation and PWR_EN1 and/or
PWR_EN2 pins are active.
In these situations, the corresponding channel will
enter in error state and the corresponding ALERT# pin
will be asserted.
When the EN_VBUS_DISCHG bit from General
Configuration 2 Register is not set (default setting), the
automatic VBUS discharges described above are
disabled. In this case, the SMBus host must set and
clear bits DISCHG_LOAD1 and DISCHG_LOAD2 from
the Current Limit Behavior Registers, to discharge the
VBUS1 and VBUS2. Setting the DISCHG_LOAD1 and
DISCHG_LOAD2 bits connects the internal 100
resistor to discharge the corresponding VBUS path.
This functionality doesn't use any timers. The
discharge time is controlled by the SMBus host, which
must clear this bit when its internal timer expires.
The first thermal shutdown stage allows the two ports
to work independently, by preventing the die
temperature to increase during over-current conditions
and to exceed the maximum allowable temperature
(TTSD_HIGH).
The error state will persist and the power switches can
not be closed until the temperature is below
TTSD_LOW - TTSD_LOW_HYST
.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 25
UCS2113
will occur and be transparent to the user. When the
charge rationing threshold is reached, the UCS2113
will take action as shown in Table 6-2. If the behavior
is changed after the charge rationing threshold has
been reached, the UCS2113 will immediately adopt
the newly programmed behavior, clearing the ALERT#
pin and restoring switch operation respectively (see
Table 6-4).
6.5
Charge Rationing Interactions
When charge rationing is active, regardless of the
specified behavior, the UCS2113 will function normally
until the charge rationing threshold is reached. Note
that charge rationing is only active when the UCS2113
is in the Active state. Changing the charge rationing
behavior will have no effect on the charge rationing
data registers. If the behavior is changed prior to
reaching the charge rationing threshold, this change
TABLE 6-2:
CHARGE RATIONING BEHAVIOR
RATION_BEH
(1 or 2) <1:0>
Behavior
Actions Taken
Notes
1
0
0
0
0
1
Report
ALERT# pin asserted.
Report and 1. ALERT# pin asserted
All bus monitoring is still active.
Disconnect
(default)
Toggling the PWR_EN control will cause the
device to change power states as defined by the
registers; however, the port power switch will
remain off until the rationing circuitry is reset.
2. Port power switch discon-
nected
1
1
0
1
Disconnect 1. Port power switch discon-
All VBUS and VS monitoring will be stopped.
Toggling the PWR_EN control will have no effect
on the power state until the rationing circuitry is
reset.
and
nected
Go to Sleep
2. Device will enter the Sleep
state
Ignore
Take no further action
TABLE 6-3:
Behavior
Report
CHARGE RATIONING RESET BEHAVIOR
Reset Actions
1. Reset the Total Accumulated Charge registers
2. Clear the RATION status bit
3. Release the ALERT# pin
Report and Disconnect
1. Reset the Total Accumulated Charge registers
2. Clear the RATION status bit
3. Release the ALERT# pin
4. Check the PWR_EN controls and enter the indicated power state if the controls
changed
Disconnect and
Go to Sleep
1. Reset the Total Accumulated Charge registers
2. Clear the RATION status bit
3. Check the PWR_EN controls and enter the indicated power state if the controls
changed
Ignore
1. Reset the Total Accumulated Charge registers
2. Clear the RATION status bit
TABLE 6-4:
EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED
Previous
Behavior
New Behavior
Actions Taken
Ignore
Report
Assert ALERT# pin
Report and
Disconnect
1. Assert ALERT# pin
2. Open port power switch. See the Report and Disconnect (default) in
Table 6-2
Disconnect and 1. Open port power switch
Go to Sleep
2. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2
DS20005680B-page 26
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
TABLE 6-4:
EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED
Previous
Behavior
New Behavior
Actions Taken
Report
Ignore
Release ALERT# pin.
Open port power switch. See the Report and Disconnect (default) in Table 6-2.
Report and
Disconnect
Disconnect and 1. Release the ALERT# pin
Go to Sleep
2. Open the port power switch
3. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2.
1. Release the ALERT# pin
Report and
Disconnect
Ignore
2. Check the PWR_EN controls and enter the indicated power state if the
controls changed
Report
Check the PWR_EN controls and enter the indicated power state if the controls
changed
Disconnect and 1. Release the ALERT# pin
Go to Sleep
2. Enter the Sleep state. See the Disconnect and Go to Sleep in Table 6-2.
Disconnect
and Go to
Sleep
Ignore
Check the PWR_EN controls and enter the indicated power state if the controls
changed
Report
1. Assert the ALERT# pin
2. Check the PWR_EN controls and enter the indicated power state if the
controls changed
Report and
Disconnect
1. Assert the ALERT# pin
2. Check the PWR_EN controls to determine the power state, then enter that
state, except that the port power switch will not be closed
If the RATION_EN control is set to ‘0’ prior to reaching
the charge rationing threshold, rationing will be
disabled and the Total Accumulated Charge registers
will be cleared. If the RATION_EN control is set to ‘0’
after the charge rationing threshold has been reached,
the following additional steps occur:
1. RATION status bit will be cleared.
2. The ALERT# pin will be released if asserted by
the rationing circuitry and no other conditions
are present.
3. The PWR_EN controls are checked to
determine the power state.
Setting the RATION_RST control to ‘1’ will
automatically reset the Total Accumulated Charge
registers to 00_00h. If this is done prior to reaching the
charge rationing threshold, the data will continue to be
accumulated restarting from 00_00h. If this is done
after the charge rationing threshold is reached, the
UCS2113 will take action as shown in Table 6-3.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 27
UCS2113
Faults do not include:
6.6
Fault Handling Mechanism
• keep-out violations except VBUS_MIN.
The UCS2113 has two modes for handling faults:
• Latch (latch-upon-fault)
• TTSD_LOW die temperature has been exceeded
and any of the following conditions are met:
• Auto-recovery (automatically attempt to restore
the Active power state after a fault occurs).
- the power switch is closed at the time when
TTSD_LOW is reached and it is not in constant
current mode.
If the SMBus is actively utilized, Auto-Recovery Fault
Handling is the default error handler as determined by
the LATCH_SET bit. Faults include overcurrent,
overvoltage (on VS), undervoltage (on VBUS),
back-voltage (VBUS to VS or VBUS to VDD), discharge
error, and maximum allowable internal die temperature
(TTSD_HIGH) exceeded. Fault conditions also include
the situations when TTSD_LOW die temperature has
been exceeded and any of the following conditions are
met:
- the power switch remains open (PWR_EN1
and/or PWR_EN2 controls are not active).
6.6.1
AUTO-RECOVERY FAULT
HANDLING
When the LATCH_SET bit is low, Auto-Recovery Fault
Handling is used. When an error condition is detected,
the UCS2113 will immediately enter the Error state
and assert the ALERT# pin. Independently from the
host controller, the UCS2113 will wait a preset time
(tCYCLE), check error conditions (tTST), and restore
Active operation if the error condition(s) no longer
exist. If all other conditions that may cause the
ALERT# pin to be asserted have been removed, the
ALERT# pin will be released. Short-Circuit
Auto-Recovery example in Figure 6-6.
• a power switch operates in constant current mode
• PWR_EN1 and/or PWR_EN2 controls transition
from inactive to active.
• it is a power up situation and PWR_EN1 and/or
PWR_EN2 pins are active.
tCYCLE
VTEST
tTST
tCYCLE
tTST
VBUS
tDISCHARGE
SHORT
applied.
IBUS
ITEST
ITEST
Check short
condition. Short
removed.
Short Detected. VBUS
discharged. Enter
Error state.
Check short
condition. Short
still present.
Return to Error
State.
Wait tCYCLE
.
Wait tCYCLE
.
Return to
normal
operation.
FIGURE 6-6:
6.6.2
Error Recovery.
If the ALERT# pin is asserted and the interrupt status
registers (addresses 03h or 04h) are not read, the
corresponding ALERT# pin remains asserted until the
corresponding PWR_EN pin is toggled.
LATCHED FAULT HANDLING
When the LATCH_SET bit is high, latch fault handling
is used. When an error condition is detected, the
UCS2113 will enter the Error power state and assert
the ALERT# (1 or 2) pin. Upon command from the host
controller (by toggling the PWR_EN (1, or 2) pin
control from enabled to disabled or by clearing the
ERR bit via SMBus), the UCS2113 will check error
conditions once and restore Active operation if error
conditions no longer exist. If an error condition still
exists, the host controller is required to issue the
command again to check error conditions.
If the ALERT# pin is asserted and the interrupt status
registers are read, the ALERT# pin will deassert, but
the UCS will remain in error state until the ERR bit is
cleared via SMBus or the PWR_EN pin is toggled.
DS20005680B-page 28
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
7.6
SMBus Time-out
7.0
SYSTEM MANAGEMENT BUS
PROTOCOL
The UCS2113 includes an SMBus time-out feature. If
the clock is held at logic ‘0’ for tTIMEOUT, the device
can time out and reset the SMBus interface. The
SMBus interface can also reset if both the clock and
data lines are held at a logic ‘1’ for tIDLE_RESET
Communication is restored with a start condition.
In SMBus mode, the UCS2113 communicates with a
host controller, such as
Microchip PIC®
a
microcontroller or hub, through the SMBus. The
SMBus is a two-wire serial communication protocol
between a computer host and its peripheral devices. A
detailed timing diagram is shown in Figure 1-1.
Stretching of the SMCLK signal is supported; however,
the UCS2113 will not stretch the clock signal.
.
The time-out function defaults to disabled. It can be
enabled by clearing the DIS_TO bit in the General
Configuration 3 register (see Register 8-9).
7.1
SMBus Start Bit
7.7
SMBus and I2C Compliance
The SMBus Start bit is defined as a transition of the
SMBus Data line from a logic ‘1’ state to a logic ‘0’
state while the SMBus Clock line is in a logic ‘1’ state.
The major difference between SMBus and I2C devices
is highlighted here. For complete compliance
information, refer to the SMBus 2.0 specification and
Application Note 14.0.
• UCS2113 supports I2C fast mode at 400 kHz. This
covers the SMBus maximum time of 100 kHz.
7.2
SMBus Address and RD/WR Bit
The SMBus Address Byte consists of the 7-bit client
address followed by the RD/WR indicator bit. If this
RD/WR bit is a logic ‘0’, the SMBus Host is writing
data to the client device. If this RD/WR bit is a logic ‘1’,
the SMBus Host is reading data from the client device.
• The minimum frequency for SMBus
communications is 10 kHz.
• The client protocol will reset if the clock is held low
longer than 30 ms. This time out functionality is
disabled by default in the UCS2113 and can be
enabled by clearing the DIS_TO bit. I2C does not
have a time out.
The UCS2113 with the order code UCS2113-1-V/G4
has the SMBus address 57h - 1010_111(r/w).
Customers
should
contact
their
distributor,
• Except when operating in Sleep, the client
protocol will reset if both the clock and the data
line are logic ‘1’ for longer than 200 µs (idle
condition). This function is disabled by default in
the UCS2113 and can be enabled by clearing the
DIS_TO bit. I2C does not have an idle condition.
representatives or field application engineer (FAE) for
additional SMBus addresses. Local sales offices are
also available to help customers. A list of sales offices
and locations is included in the back of this document.
7.3
SMBus Data Bytes
• I2C devices do not support the Alert Response
Address functionality (which is optional for SMBus).
All SMBus Data bytes are sent most significant bit first
and composed of 8 bits of information.
• I2C devices support block read and write
differently. I2C protocol allows for unlimited
number of bytes to be sent in either direction. The
SMBus protocol requires that an additional data
byte indicating number of bytes to read/write is
transmitted. The UCS2113 supports I2C
formatting only.
7.4
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that
it receives. This is done by the client device pulling the
SMBus Data line low after the 8th bit of each byte that
is transmitted. This applies to both the Write Byte and
Block Write protocols.
7.8
SMBus Protocols
The Host will NACK (not acknowledge) the last data byte
to be received from the client by holding the SMBus data
line high after the 8th data bit has been sent. For the
Block Read protocol, the Host will ACK (acknowledge)
each data byte that it receives except the last data byte.
The UCS2113 is SMBus 2.0-compatible and supports
Send Byte, Read Byte, Block Read, Receive Byte as
valid protocols as shown below. The UCS2113 also
supports the I2C block read and block write protocols.
The device supports Write Byte, Read Byte, and Block
Read/Block Write. All of the below protocols use the
convention in Table 7-1.
7.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the
SMBus Data line from a logic ‘0’ state to a logic ‘1’
state while the SMBus clock line is in a logic ‘1’ state.
When the UCS2113 detects an SMBus Stop bit and it
has been communicating with the SMBus protocol, it
will reset its client interface and prepare to receive
further communications.
TABLE 7-1:
SMBUS PROTOCOL
Data Sent to Device
Data Sent to the Host
Data sent
Data sent
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 29
UCS2113
7.9
SMBus Write Byte
The Write Byte is used to write one byte of data to a
specific register as shown in Table 7-2.
TABLE 7-2:
START
WRITE BYTE PROTOCOL
Client
WR ACK
Address
Reg. Addr.
ACK Register Data ACK
STOP
1 → 0
YYYY_YYY
0
0
XXh
0
XXh
0
0 → 1
7.10 SMBus Read Byte
The Read Byte protocol is used to read one byte of
data from the registers as shown in Table 7-3.
TABLE 7-3:
START
1→0
READ BYTE PROTOCOL
Client Address
YYYY_YYY
WR
0
ACK
0
Register Address
XXh
ACK
0
START
1 →0
Client Address
YYYY_YYY
RD
1
ACK
0
Register Data
XXh
NACK
STOP
1
0 → 1
7.11 Block Write
The Block Write is used to write multiple data bytes to
a group of contiguous registers, as shown in Table 7-4.
It is an extension of the Write Byte Protocol.
Note:
The Block Write and Block Read protocols
require that the address pointer be auto-
matically incremented. For a write com-
mand, the address pointer will be
automatically incremented when the ACK
is sent to the host. There are no over or
under bound limit checking and the
address pointer will wrap around from FFh
to 00h if necessary
TABLE 7-4:
START
BLOCK WRITE PROTOCOL
Repeat N Times
Register Data ACK
XXh
Register
Address
Client Address
YYYY_YYY
WR
ACK
ACK
STOP
1 → 0
0
0
XXh
0
0
0 → 1
7.12 Block Read
The Block Read is used to read multiple data bytes
from a group of contiguous registers, as shown in
Table 7-5. It is an extension of the Read Byte Protocol.
TABLE 7-5:
START
BLOCK READ PROTOCOL
Register
Address
Client Address
WR
ACK
ACK
1→0
YYYY_YYY
0
0
XXh
0
Repeat N Times
START
Client Address
RD
ACK
Register Data NACK
XXh
STOP
Register Data ACK
1→0
YYYY_YYY
1
0
XXh
0
1
0 → 1
DS20005680B-page 30
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
7.13 SMBus Send Byte
The Send Byte protocol is used to set the internal
address register pointer to the correct address location.
No data is transferred during the Send Byte protocol as
shown in Table 7-6.
Note:
The SMBus Send Byte command is
expected to be followed by the SMBus
Receive Byte command. When two
SMbus Send Byte commands are sent in
a row, the first command receives an ACK
and will be processed by the UCS2113,
but the second command receives a
NACK and will be ignored.
TABLE 7-6:
START
SEND BYTE PROTOCOL
Client Address
WR
ACK
Register Address
ACK
STOP
1→0
YYYY_YYY
0
0
XXh
0
0 → 1
7.14 SMBus Receive Byte
The Receive Byte protocol is used to read data from a
register when the internal register address pointer is
known to be at the right location (e.g. set via Send
Byte). This is used for consecutive reads of the same
register as shown in Table 7-7.
TABLE 7-7:
START
RECEIVE BYTE PROTOCOL
Client Address
RD
ACK
Register Data
NACK
STOP
1→0
YYYY_YYY
1
0
XXh
1
0 → 1
7.14.1
Stand-Alone mode allows the UCS2113 to operate
without active communications.
SMBus/I2C
STAND-ALONE OPERATING MODE
Stand-Alone mode can be enabled by connecting a
pull-down resistor greater or equal to 47 k on the
COMM_ILIM pin as shown in Table 5-3.The SMCLK
pin should be tied to ground in this mode.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 31
UCS2113
8.0
REGISTER DESCRIPTION
The registers shown in Table 8-1 are accessible
through the SMBus or I2C. An entry of ‘—’ indicates
that the bit is not used. Writing to these bits will have no
effect and reading these bits will return ‘0’. Writing to a
reserved bit may cause unexpected results and
reading from a reserved bit will return either ‘1’ or ‘0’ as
indicated in the bit description. While in the Sleep state,
the UCS2113 will retain configuration and charge
rationing data as indicated in the text. If a register does
not indicate that data will be retained in the Sleep
power state, this information will be lost when the
UCS2113 enters the Sleep power state.
TABLE 8-1:
REGISTER SET IN HEXADECIMAL ORDER
Register Name R/W
Register
Address
Default Page
Function
Value
No.
00h
01h
02h
03h
04h
0Fh
10h
11h
12h
13h
14h
15h
16h
Port 1 Current Measurement
Port 2 Current Measurement
Port Status
R
R
R
Stores the current measurement for Port 1
Stores the current measurement for Port 2
Indicates Port and general status
00h
00h
00h
33
33
34
35
37
39
40
41
42
43
44
45
46
Interrupt Status1
See Text Indicates why ALERT# pin asserted for Port 1 00h
See Text Indicates why ALERT# pin asserted for Port 2 00h
Interrupt Status2
General Status1
R/R-C
R/R-C
R/W
Indicates General Status for Port 1
Indicates General Status for Port 2
Controls basic functionality for Port 1
Controls basic functionality for Port 2
Controls other functionality
00h
00h
06h
02h
60h
General Status2
General Configuration1
General Configuration2
General Configuration3
Current Limit
R/W
R/W
R/W
Controls/Displays MAX Current Limit per port 00h
Auto-Recovery Configuration R/W
Controls the Auto-Recovery functionality
2Ah
00h
Port 1 Total Accumulated
Charge High Byte
R
Stores the total accumulated charge
delivered high byte, Port 1
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Port 1 Total Accumulated
Charge Middle High Byte
R
Stores the total accumulated charge
delivered middle high byte, Port 1
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
46
46
46
47
47
47
47
48
48
48
Port 1 Total Accumulated
Charge Middle Low Byte
R
Stores the total accumulated charge
delivered middle low byte, Port 1
Port 1 Total Accumulated
Charge Low Byte
R
Stores the total accumulated charge
delivered low byte, Port 1
Port 2 Total Accumulated
Charge High Byte
R
Stores the total accumulated charge
delivered high byte, Port 2
Port 2 Total Accumulated
Charge Middle High Byte
R
Stores the total accumulated charge
delivered middle high byte, Port 2
Port 2 Total Accumulated
Charge Middle Low Byte
R
Stores the total accumulated charge
delivered middle low byte, Port 2
Port 2 Total Accumulated
Charge Low Byte
R
Stores the total accumulated charge
delivered low byte, Port 2
Port 1 Charge Rationing
Threshold High Byte
R/W
R/W
R/W
Sets the maximum allowed charge that will
be delivered to Port 1
Port 1 Charge Rationing
Threshold Low Byte
Sets the maximum allowed charge that will
be delivered to Port 1
Port 2 Charge Rationing
Threshold High Byte
Sets the maximum allowed charge that will
be delivered to Port 2
DS20005680B-page 32
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
TABLE 8-1:
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Address
Default Page
Register Name
R/W
R/W
R/W
Function
Value
No.
21h
Port 2 Charge Rationing
Threshold Low Byte
Sets the maximum allowed charge that will
be delivered to Port 2
FFh
48
22h
23h
Ration Configuration
Controls Charge Ration Functionality
11h
96h
49
50
Port 1 Current Limit Behavior R/W
Controls the Current Limiting Behavior (CC
Mode Region 2) for Port 1
24h
Port 2 Current Limit Behavior R/W
Controls the Current Limiting Behavior (CC
Mode Region 2) for Port 2
96h
E1h
50
51
FDh
Product ID
R
Stores a fixed value that identifies each
product
FEh
FFh
Manufacturer ID
Revision
R
R
Stores a fixed value that identifies Microchip 5Dh
51
52
Stores a fixed value that represents the
revision number
81h
8.1
Current Measurement Register
The Current Measurement register stores the
measured current value delivered to the portable
device (IBUS). This value is updated continuously while
the device is in the Active power state.
REGISTER 8-1:
PORTS 1 AND 2 CURRENT MEASUREMENT REGISTERS
(ADDRESSES 00H, 01H)
R-0
R-0
R-0
R-0
CM(x)<7:0>
R-0
R-0
R-0
R-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CM(x)<7:0>: Port X Current Measurement, where x=1 or 2 (address 00h for Port 1 and address 01h for
Port 2).
Note 1: The bit weights are in mA,1 LSB = 13.3 mA (maximum value is 255 LSB corresponding to 3.4A).
2: This data will be cleared when the device enters the Sleep state. This data will also be cleared whenever
the port power switch is turned off (or any time that VBUS is discharged).
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 33
UCS2113
8.2
Status Registers
The Status registers store bits that indicate the state of
the ALERT# pins and if the ports operate in Constant
Current Mode.
REGISTER 8-2:
PORT STATUS REGISTER (ADDRESS 02H)
R-0
R-0
R-0
R-0
U-0
—
U-0
—
R-x
—
R-x
—
ALERT2_PIN ALERT1_PIN CC_MODE2 CC_MODE1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ALERT2_PIN: Reflects the status of the ALERT#2 pin. This bit is set and cleared as the ALERT#2 pin
changes states.
1 = ALERT#2 Pin asserted (logic low)
0 = ALERT#2 Pin not asserted
bit 6
ALERT1_PIN: Reflects the status of the ALERT#1 pin. This bit is set and cleared as the ALERT#1 pin
changes states.
1 = ALERT#1 Pin asserted (logic low)
0 = ALERT#1 Pin not asserted
bit 5
CC_MODE2: Port 2 Constant Current Mode State
1 = Port 2 in Constant Current mode
0 = Port 2 operating normally
bit 4
CC_MODE1: Port 1 Constant Current Mode State
1 = Port 1 in Constant Current mode
0 = Port 1 operating normally
bit 3-0
Unimplemented
DS20005680B-page 34
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-3:
INTERRUPT STATUS 1 REGISTER (ADDRESS 03H)
R/W-0
R/C-0
DISCH_ERR1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
ERR1
bit 7
RESET
KEEP_OUT1 TSD_HIGH
OV_VOLT
BACK_V1
OV_LIM1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
ERR1: Error Port 1 - Indicates that an error was detected on the VBUS1 pin and the device has entered
the Error state. Writing this bit to ‘0’ will clear the Error state and allows the device to be returned to the
Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been
removed, the UCS2113 returns to the Active state. This bit is set automatically by the UCS2113 when
the Error state is entered. If any other bit is set in the Interrupt Status register (03h), the device will not
leave the Error state.
This bit is cleared automatically by the UCS2113 if the Auto-recovery fault handling functionality is active
and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN1 control is disabled
(Note 1).
1 = Port 1 in Error State
0 = Port 1 in Active State (no errors detected)
bit 6
bit 5
bit 4
DISCH_ERR1: Discharge Error Port 1 - Indicates the device was unable to discharge Port1. This bit will
be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will
cause the ALERT#1 pin to be asserted and the device to enter the Error state.
1 = UCS2113 was unable to Discharge VBUS1
0 = No VBUS1 discharge error
RESET: Indicates that the UCS2113 has just been reset and should be reprogrammed. This bit will be
set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT#
pins are not asserted when this bit is set. This data is retained in the Sleep state.
1 = UCS2113 has just been reset
0 = Reset did not occur
KEEP_OUT1: Port 1 Minimum Keep-Out region - Indicates that the V-I output on the VBUS1 pin has
dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or
if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter the
Error state.
1 = VBUS1 < VBUS_MIN
0 = VBUS1 > VBUS_MIN
bit 3
TSD_HIGH: Indicates that the internal temperature has exceeded TTSD_HIGH threshold and the device
has entered the Error state. This bit will be cleared when read if the error condition has been removed
or if the ERR1 bit is cleared. This bit will cause the ALERT#1and ALERT#2 pins to be asserted and the
device to enter the Error state.
1 = Internal die temperature has exceeded TTSD_HIGH
0 = Internal die temperature has not exceeded TTSD_HIGH
bit 2
OV_VOLT: VS Overvoltage indicates that the VS voltage has exceeded the VS_OV threshold, and the
device has entered the Error state. This bit will be cleared when read if the error condition has been
removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 and ALERT#2 pins to be asserted
and the device to enter the Error state.
1 = VS > VS_OV
0 = VS < VS_OV
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 35
UCS2113
REGISTER 8-3:
INTERRUPT STATUS 1 REGISTER (ADDRESS 03H) (CONTINUED)
bit 1
BACK_V1: Back-Bias Voltage Port 1 - Indicates that the VBUS1 voltage has exceeded the VS or VDD
voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed
or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted and the device to enter
the Error state.
1 = VBUS1 > VS, or VBUS1 > VDD by more than 150 mV.
0 = VBUS1 voltage has not exceeded the VS and VDD voltages by more than 150 mV.
bit 0
OV_LIM1: Over Current Limit Port 1 - Indicates that the IBUS current has exceeded both the ILIM thresh-
old and the IBUS_R2MIN threshold settings for VBUS1. This bit will be cleared when read if the error con-
dition has been removed or if the ERR1 bit is cleared. This bit will cause the ALERT#1 pin to be asserted
and the device to enter the Error state.
1 = Current Limit for Port 1 exceeded
0 = Current Limit for Port 1 not exceeded
Note 1: Note that the ERR1 bit does not necessarily reflect the ALERT#1 pin status. The ALERT#1 pin may be
cleared or asserted without the ERR1 bit changing states.
DS20005680B-page 36
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-4:
INTERRUPT STATUS 2 REGISTER (ADDRESS 04H)
R/W-0
R/C-0
DISCH_ERR2
R-0
R/C-0
R/C-0
U-0
—
R/C-0
R/C-0
ERR2
bit 7
VS_LOW
KEEP_OUT2 TSD_LOW
BACK_V2
OV_LIM2
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
ERR2: Error Port 2 - Indicates that an error was detected on the VBUS1 pin and the device has entered
the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to
the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been
removed, the UCS2113 returns to the Active state. This bit is set automatically by the UCS2113 when
the Error state is entered. If any other bit is set in the Interrupt Status register (04h), the device will not
leave the Error state. This bit is cleared automatically by the UCS2113 if the auto-recovery fault handling
functionality is active and no error conditions are detected. Likewise, this bit is cleared when the
PWR_EN2 control is disabled (Note 1).
1 = Port 2 in Error State
0 = Port 2 in Active State (no errors detected)
bit 6
bit 5
bit 4
DISCH_ERR2: Discharge Error Port 2 - Indicates the device was unable to discharge Port2. This bit will
be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will
cause the ALERT#2 pin to be asserted and the device to enter the Error state.
1 = Device was unable to Discharge VBUS2
0 = No VBUS2 discharge error
VS_LOW: Indicates that the VS voltage has fallen below the VS_UVLO threshold and both VBUS1 and
VBUS2 port power switches are held off. This bit is cleared automatically when the VS voltage is above
the VS_UVLO threshold.
1 = VS voltage has fallen below the VS_UVLO
0 = VS voltage is above VS_UVLO
KEEP_OUT2: Port 2 Minimum Keep-out region - Indicates that the V-I output on the VBUS2 pin has
dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or
if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter the
Error state.
1 = VBUS2 < VBUS_MIN
0 = VBUS2 > VBUS_MIN
bit 3
TSD_LOW: Indicates that the die temperature has exceeded the TTSD_LOW threshold and it is still above
the TTSD_LOW - TTSD_LOW_HYST. This bit is cleared automatically when the die temperature is below
the TTSD_LOW -TTSD_LOW_HYST. This bit will not cause the corresponding ALERT#1 and/or
ALERT#2 pins to be asserted and ERR1 and/or ERR2 bits to be set unless:
• a power switch operates in constant current mode
• PWR_EN1 and/or PWR_EN2 controls transition from inactive to active
• it is a power up situation and PWR_EN1 and/or PWR_EN2 pins are active.
1 = Internal die temperature has exceeded TTSD_LOW
0 = Internal die temperature has not exceeded TTSD_LOW
bit 2
bit 1
Unimplemented: Read as '0'
BACK_V2: Back-Bias Voltage Port 2 - Indicates that the VBUS2 voltage has exceeded the VS or VDD
voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed
or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and the device to enter
the Error state.
1 = VBUS2 > VS, or VBUS2 > VDD by more than 150 mV
0 = VBUS2 voltage has not exceeded the VS and VDD voltages by more than 150 mV
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 37
UCS2113
REGISTER 8-4:
INTERRUPT STATUS 2 REGISTER (ADDRESS 04H) (CONTINUED)
bit 0
OV_LIM2: Overcurrent Limit Port 2 - Indicates that the IBUS current has exceeded both the ILIM threshold
and the IBUS_R2MIN threshold settings for VBUS2. This bit will be cleared when read if the error condition
has been removed or if the ERR2 bit is cleared. This bit will cause the ALERT#2 pin to be asserted and
the device to enter the Error state.
1 = Current Limit for Port 2 exceeded
0 = Current Limit for Port 2 not exceeded
Note 1: Note that the ERR2 bit does not necessarily reflect the ALERT#2 pin status. The ALERT#2 pin may be cleared or
asserted without the ERR2 bit changing states.
DS20005680B-page 38
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-5:
GENERAL STATUS 1 REGISTER (ADDRESS 0FH)
R/C-0
RATION1
bit 7
U-x
—
U-x
—
R-0
R-0
U-x
—
U-x
—
U-x
—
CC_MODE1 PWR_EN1_CON
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
RATION1: Indicates the state of Port 1 Rationing. This bit is cleared when read, or cleared automatically
when the RATION_RST1 bit is set or the RATION_EN1 bit is cleared.
1 = Port 1 has delivered the programmed mAh of current
0 = Port 1 has not delivered the programmed mAh of current
bit 6-5
bit 4
Unimplemented
CC_MODE1: Indicates whether Port 1 has entered CC mode.
1 = Port 1 is in CC mode
0 = Port 1 not in CC mode
bit 3
PWR_EN1_CON: Reflects the PWR_EN control state. This bit is set and cleared automatically with the
logic expression (PWR_EN1 pin OR PWR_EN1S).
1 = Port 1 Power Enable is set
0 = Port 1 Power Enable is clear
bit 2-0
Unimplemented
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 39
UCS2113
REGISTER 8-6:
GENERAL STATUS 2 REGISTER (ADDRESS 10H)
R/C-0
U-x
—
U-x
—
R-0
R-0
U-x
—
U-x
—
U-x
—
RATION2
CC_MODE2 PWR_EN2_CON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
RATION2: Indicates the state of Port 2 Rationing. This bit is cleared when read, or cleared automatically
when the RATION_RST2 bit is set or the RATION_EN2 bit is cleared.
1 = Port 2 has delivered the programmed mAh of current
0 = Port 2 has not delivered the programmed mAh of current
bit 6-5
bit 4
Unimplemented
CC_MODE2: Indicates whether Port 2 has entered CC mode.
1 = Port 2 is in CC mode
0 = Port 2 not in CC mode
bit 3
PWR_EN2_CON: Reflects the PWR_EN control state. This bit is set and cleared automatically with the
logic expression (PWR_EN2 pin OR. PWR_EN2S).
1 = Port 2 Power Enable is set
0 = Port 2 Power Enable is clear
bit 2-0
Unimplemented
DS20005680B-page 40
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
8.3
Configuration Registers
The Configuration registers control basic device
functionality. The contents of these registers are
retained in Sleep.
REGISTER 8-7:
GENERAL CONFIGURATION 1 REGISTER (ADDRESS 11H)
R/W-0
ALERT1_MASK
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-1
U-1
—
U-0
—
DSCHG1
PWR_EN1S
DISCHG_TIME<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
ALERT1_MASK: Mask errors for all interrupts in Register 8-3 except OV_LIM1 and TSD.
1 = The ALERT#1 pin will only assert if a OV_LIM1 or TSD is detected
0 = The ALERT#1 pin will be asserted if an error condition or indicator event is detected
bit 6
bit 5
Unimplemented
DSCHG1: Forces the VBUS1 to be reset and discharged when the UCS2113 is in the Active state
and the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic ‘1’ will cause the port power
switch to be opened and the discharge circuitry to activate and discharge VBUS. Actual discharge
time is controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus host after the
forced VBUS discharge.
1 = VBUS1 discharge initiated
0 = Port 1 not in discharge
bit 4
PWR_EN1S: Power Enable Port 1 override - This bit is OR’ed with the PWR_EN1 pin. Thus, if the
polarity is set to active-high, either the PWR_EN1 pin or this bit must be ‘1’ to enable the port power
switch.
bit 3-2
DISCHG_TIME<1:0>: Discharge time Port 1 - sets tDISCHARGE. The discharge time value is the
same for both ports.
00 = 100 ms
01 = 200 ms
10 = 300 ms
11 = 400 ms
bit 1-0
Unimplemented
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 41
UCS2113
REGISTER 8-8:
GENERAL CONFIGURATION 2 REGISTER (ADDRESS 12H)
R/W-0
ALERT2_MASK
bit 7
U-0
—
R/W-0
R/W-0
U
R/W-0
U-1
—
U-0
—
DSCHG2 PWR_EN2S
—
EN_VBUS_DISCHG
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on
Read
-n = Value at POR
x = Bit is
unknown
bit 7
ALERT2_MASK: Mask errors for all interrupts in Register 8-4 except OV_LIM2 and TSD.
1 = The ALERT#2 pin will only assert if a OV_LIM2 or TSD is detected
0 = The ALERT#2 pin will be asserted if an error condition or indicator event is detected
bit 6
bit 5
Unimplemented
DSCHG2: Forces the VBUS2 to be reset and discharged when the UCS2113 is in the Active state and
the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic '1' will cause the port power switch
to be opened and the discharge circuitry to activate to discharge VBUS. Actual discharge time is
controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus host after the forced VBUS
discharge.
1 = VBUS2 discharge initiated
0 = Port 2 not in discharge
bit 4
PWR_EN2S: Power Enable Port 2 override - This bit is OR’ed with the PWR_EN2 pin. Thus, if the
polarity is set to active-high, either the PWR_EN2 pin or this bit must be ‘1’ to enable the port power
switch.
bit 3
bit 2
Unimplemented
EN_VBUS_DISCHG: Enables VBUS discharge circuitry.
If it is '0', it completely disables all the automatic VBUS discharges from happening and allows only
manual VBUS discharges (the SMBus host must set and clear DISCHG_LOAD1 and DISCHG_-
LOAD2 bits from the Current Limit Behavior Registers 23h and 24h). Setting DSCHG1 and DSCHG2
bits from the General Configuration 1 and 2 registers 11h and 12h does not have any effect in this
case (Note 1).
If it is '1', the VBUS is discharged automatically as described in Section 6.4, VBUS Discharge. The
VBUS can be discharged manually by the SMBus host only by setting DSCHG1 and DSCHG2 bits
from the General Configuration 1 and 2 Registers 11h and 12h. Setting DISCHG_LOAD1 and
DISCHG_LOAD2 bits from the Current Limit Behavior Registers 23h and 24h doesn't have any effect
in this case.
bit 1-0
Unimplemented
Note 1: When the automatic VBUS discharges are disabled (EN_VBUS_DISCHG is '0'), the UCS2113 will not
check that the VBUS voltage is below the VTEST level after the manual VBUS discharges.
DS20005680B-page 42
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-9:
GENERAL CONFIGURATION 3 REGISTER (ADDRESS 13H)
R/W-0
PIN_IGN
bit 7
U-1
—
R/W-1
U-x
—
U-x
—
R/W-0
U-0
—
U-0
—
DIS_TO
BOOST
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
C = Clear on Read
x = Bit is unknown
bit 7
PIN_IGN: Ignores the PWR_EN1 and PWR_EN2 pin states when determining the power state. This bit
is retained in Sleep.
1 = PWR_EN1 and PWR_EN2 pin states are ignored.
0 = Power state is determined by the OR'd combination of the PWR_EN1 and PWR_EN2 pins states
and the corresponding PWR_EN1S and PWR_EN2S bit states.
bit 6
bit 5
Unimplemented
DIS_TO: Disable Time Out - Disables the SMBus time out feature.
1 = Time out disabled
0 = Time out enabled
bit 4-3
bit 2
Unimplemented
BOOST: Indicates that the IBUS current is higher than IBOOST on VBUS1 or VBUS2 (bit is OR’ed).
1 = IBUS has exceeded IBOOST on either or both ports
0 = IBUS is less than IBOOST on either port individually
bit 1-0
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 43
UCS2113
8.4
Current Limit Register
The Current Limit register controls the ILIM used by the
port power switch. The default setting is based on the
resistor on the COMM_ILIM pin and this value cannot
be changed to be higher than hardware set value. The
contents of this register are retained in Sleep.
REGISTER 8-10: CURRENT LIMIT REGISTER (ADDRESS 14H)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ILIM_PORT2<2:0>
ILIM_PORT1<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-3
Unimplemented: Read as ‘0’
ILIM_PORT2<2:0>: Sets the ILIM value for Port 2
000 = 0.53A
001 = 0.96A
010 = 1.07A
011 = 1.28A
100 = 1.6A
101 = 2.13A
110 =2.67A
111 =3.2A
bit 2-0
ILIM_SW<2:0>: Sets the ILIM value for Port 1
000 = 0.53A
001 = 0.96A
010 = 1.07A
011 = 1.28A
100 = 1.6A
101 = 2.13A
110 = 2.67A
111 = 3.2A
DS20005680B-page 44
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
8.5
Auto-Recovery Register
The contents of this register are retained in Sleep.
The Auto-Recovery Configuration register sets the
parameters used when the Auto-Recovery fault
handling algorithm is invoked. Once the Auto-Recovery
fault handling
algorithm has checked
the
overtemperature and back-drive conditions, it will set
the ILIM value to ITEST and then turn on the port power
switch and start the tTST timer. If, after the timer has
expired, the VBUS voltage is less than VTEST, then it is
assumed that a short-circuit condition is present and
the Error state is restarted for Auto Recovery.
REGISTER 8-11: AUTO RECOVERY CONFIGURATION REGISTER (ADDRESS 15H)
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
LATCHS
TCYCLE<2:0>
TTST<1:0>
VTST_SW<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
LATCHS: Latch Set - Controls the fault-handling routine that is used in the case that an error is detected.
1 = Error state will be latched. In order for the UCS2113 to return to normal Active state, the ERR bit
must be cleared by the user.
0 = The UCS2113 will automatically retry when an error condition is detected.
bit 6-4
TCYCLE<2:0>: Defines the delay (tCYCLE) after the Error state is entered before the Auto-Recovery
fault handling algorithm is started as shown below.
000 = 15 ms
001 = 20 ms
010 = 25 ms
011 = 30 ms
100 = 35 ms
101 = 40 ms
110 = 45 ms
111 = 50 ms
bit 3-2
bit 1-0
TTST<1:0>: Retry Duration timer - Sets the tTST as shown below
00 = 10 ms
01 = 15 ms
10 = 20 ms
11 = 25 ms
VTST_SW: Short-circuit voltage threshold VTEST that must be crossed during retries to declare the short
removed
00 = 250 mV
01 = 500 mV
10 = 750 mV
11 = 1000 mV
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 45
UCS2113
8.6
Total Accumulated Charge Registers
The Total Accumulated Charge registers store the total
accumulated charge delivered from the VS source to a
portable device. The bit weighting of the registers is
given in mA-hrs. The register value is reset to 00_00h
only when the RATION_RST bit is set or if the
RATION_EN bit is cleared. This value will be retained
when the device transitions out of the Active state and
resumes accumulation, if the device returns to the
Active state and charge rationing is still enabled.
These registers are updated every one (1) second
while the UCS2113 is in the Active power state. Every
time the value is updated, it is compared against the
target value in the Charge Rationing Threshold
registers. This data is retained in the Sleep state.
REGISTER 8-12: PORT1 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESS 16H, 17H,
18H, 19H)
R-0
bit 31
R-0
bit 23
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
bit 24
R-0
bit 16
TAC1<25:18>
R-0
TAC1<17:10>
R-0
R-0
TAC1<9:2>
bit 8
bit 0
R-0
TAC1<1:0>
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
-n = Value at POR
x = Bit is unknown
bit 31-6
bit 5-0
TAC1<25:0>: Total Accumulated Charge Port 1 - Each LSB of this 26-bit value equals 0.00367 mAh
Unimplemented: Read as ‘0’
DS20005680B-page 46
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-13: PORT2 TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESS
1AH,1BH,1CH,1DH)
R-0
bit 31
R-0
bit 23
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
bit 24
R-0
bit 16
TAC2<25:18>
R-0
R-0
R-0
TAC2<17:10>
R-0
R-0
TAC2<9:2>
bit 8
bit 0
R-0
TAC2<1:0>
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
-n = Value at POR
x = Bit is unknown
bit 31-6
bit 5-0
TAC2<25:0>: Total Accumulated Charge Port 2 - Each LSB of this 26-bit value equals 0.00367 mAh
Unimplemented: Read as ‘0’
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 47
UCS2113
8.7
Charge Rationing Threshold Registers
The Charge Rationing Threshold registers set the
maximum allowed charge that will be delivered to a
portable device. Every time the Total Accumulated
Charge registers are updated, the value is checked
against this limit. If the value meets or exceeds this
limit, the RATION(1/2) bit is set and action taken
according
to
the
RATION_BEH1<1:0>
and
RATION_BEH2<1:0> bits.
REGISTER 8-14: PORT 1 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESS 1EH,1FH)
R/W-1
bit 15
R/W-1
bit 7
Legend:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CT1<15:8>
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
R/W-1
R/W-1
R/W-1
CT1<7:0>
R/W-1
R/W-1
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
CT1<15:0>: Charge Rationing Threshold Port 1 - Each LSB of this 16-bit value equals 3.76 mAh
REGISTER 8-15: PORT 2 CHARGE RATIONING THRESHOLD REGISTERS (ADDRESS 20H, 21H)
R/W-1
bit 15
R/W-1
bit 7
Legend:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CT2<15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
R/W-1
CT2<7:0>
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
CT2: Charge Rationing Threshold Port 2 - Each LSB of this 16-bit value equals 3.76 mAh
DS20005680B-page 48
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-16: RATION CONFIGURATION REGISTER (ADDRESS 22H)
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
RTN_BEH1<1:0>
bit 0
R/W-1
RTN_EN2
RTN_RST2
RTN_BEH2<1:0>
RTN_EN1
RTN_RST1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RTN_EN2: Charge Ration Enable Port 2 - Enables Charge Rationing for Port 2.
1 = Charge Rationing enabled
0 = Charge Rationing disabled. The Total Accumulated Charge registers for Port 2 will be cleared to
00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registers
have already reached the Charge Rationing Threshold, the applied response will be removed as if
the charge rationing had been reset. This will also clear the RATION2 status bit (if set).
bit 6
RTN_RST2: Port 2 Ration Reset - Resets the charge rationing functionality for Port 2.
1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the
RATION2 status bit will be cleared and, if there are no other errors or active indicators, the
ALERT#2 pin will be released.
0 = Normal operation. This bit must be cleared to enable charge rationing
bit 5-4
RTN_BEH2<1:0>: Ration Behavior Control bits - Controls how the UCS2113 responds when the Ration
Threshold has been exceeded (as shown in Table 6-2).
00 = Report
01 = Report and Disconnect
10 = Disconnect and SLEEP
11 = Ignore
bit 3
RTN_EN1: Charge Ration Enable Port 1 - Enables Charge Rationing for Port 1.
1 = Charge Rationing enabled
0 = Charge Rationing disabled. The Total Accumulated Charge registers for Port 1 will be cleared to
00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registers
have already reached the Charge Rationing Threshold, the applied response will be removed as if
the charge rationing had been reset. This will also clear the RATION1 status bit (if set).
bit 2
RTN_RST1: Port 1 Ration Reset - Resets the charge rationing functionality for Port 1.
1 = Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the
RATION1 status bit will be cleared and, if there are no other errors or active indicators, the
ALERT#1 pin will be released.
0 = Normal operation. This bit must be cleared to enable charge rationing.
bit 1-0
RTN_BEH1<1:0>: Ration Behavior Control bits - Controls how the UCS2113 responds when the Ration
Threshold has been exceeded (as shown in Table 6-2).
00 = Report
01 = Report and Disconnect
10 = Disconnect and SLEEP
11 = Ignore
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 49
UCS2113
8.8
Current Limit Behavior Registers
The Current Limit Behavior register stores the values
used by the applied current limiting mode (Trip or CC).
The contents of this register are not retained in Sleep.
REGISTER 8-17: PORT 1 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 23H)
R/W-1
SEL_VBUS1_MIN<1:0>
bit 7
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
DISCHG_LOAD1
SEL_R2_IMIN1<2:0>
Reserved
Reserved
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
SEL_VBUS1_MIN<1:0>: Define the VBUS_MIN voltage for Port 1 as follows:
00 = 1.50V
01 =1.75V
10 =2.0V
11 =2.25V
bit 5
DISCHG_LOAD1: Connects the internal 100Ω load to discharge VBUS1 (Note 1). The SMBus host must
set this bit to discharge VBUS1 if the EN_VBUS_DISCHG bit from the General Configuration 2 register
12h is '0'. This functionality doesn't use any timer. The discharge time is controlled by the SMBus host,
which must clear this bit when its internal timer expires. The difference from DSCHG1 bit from the
General Configuration 1 register 11h is that, when that bit is set, the discharge time is controlled by the
UCS2113 internal timer.
The state of this bit is ignored when the EN_VBUS_DISCHG bit from the General Configuration 2
register 12h is '1'.
bit 4-2
SEL_R2_IMIN1<2:0>: Defines the IBUS_R2MIN current
000 =100 mA
001 =530 mA
010 =960 mA
011 =1280 mA
100 =1600 mA
101 =2130 mA
bit 1-0
Reserved: Do not change
Note 1: If the corresponding power switch is still turned on (PWR_EN1 control is active) while DISCHG_LOAD1 bit
is set, the internal 100Ω load will be connected in parallel with the load on the VBUS1 pins.
REGISTER 8-18: PORT 2 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 24H)
R/W-1
SEL_VBUS2_MIN<1:0>
bit 7
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
DISCHG_LOAD2
SEL_R2_IMIN2_MIN<2:0>
Reserved
Reserved
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
SEL_VBUS2_MIN<1:0>: Define the VBUS_MIN voltage for Port 2 as follows:
00 = 1.50V
01 =1.75V
10 =2.0V
11 =2.25V
DS20005680B-page 50
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
REGISTER 8-18: PORT 2 CURRENT LIMIT BEHAVIOR REGISTER (ADDRESS 24H) (CONTINUED)
bit 5
DISCHG_LOAD2: Connects the internal 100Ω load to discharge VBUS2 (Note 1). The SMBus host must
set this bit to discharge VBUS2 if the EN_VBUS_DISCHG bit from the General Configuration 2 register
12h is '0'. This functionality doesn't use any timer. The discharge time is controlled by the SMBus host,
which must clear this bit when its internal timer expires. The difference from DSCHG2 bit from the
General Configuration 2 register 12h is that, when that bit is set, the discharge time is controlled by the
UCS2113 internal timer.
The state of this bit is ignored when the EN_VBUS_DISCHG bit from the General Configuration 2
register 12h is '1'.
bit 4-2
SEL_R2_IMIN2_MIN<2:0>: Defines the IBUS_R2MIN current
000 =100 mA
001 =530 mA
010 =960 mA
011 =1280 mA
100 =1600 mA
101 =2130 mA
bit 1-0
Reserved: Do not change
Note 1: If the corresponding power switch is still turned on (PWR_EN2 control is active) while DISCHG_LOAD2 bit
is set, the internal 100Ω load will be connected in parallel with the load on the VBUS2 pins.
8.9
Product ID Register
The Product ID register stores a unique 8-bit value that
identifies the UCS device family.
REGISTER 8-19: PRODUCT ID REGISTER (ADDRESS FDH)
R-1
R-1
R-1
R-0
PID<7:0>
R-0
R-0
R-1
R-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
PID<7:0>: Product ID for the UCS2113
8.10 Manufacture ID Register
The Manufacturer ID register stores a unique 8-bit
value that identifies Microchip Technology Inc.
REGISTER 8-20: MANUFACTURER ID REGISTER (ADDRESS FEH)
R-0
R-1
R-0
R-1
MID<7:0>
R-1
R-1
R-0
R-1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MID<7:0>: Manufacturer ID for Microchip
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 51
UCS2113
8.11 Revision Register
The Revision register stores an 8-bit value that
represents the part revision.
REGISTER 8-21: REVISION REGISTER (ADDRESS FFH)
R-1
R-0
R-0
R-0
REV<7:0>
R-0
R-0
R-0
R-1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
REV<7:0>: Part Revision
DS20005680B-page 52
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
20-Lead QFN (4x4x0.9 mm)
Example
e
3
UCS
2113-1
151256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 53
UCS2113
20-Lead Plastic Quad Flat, No Lead Package (G4) - 4x4 mm Body [QFN]
Also called VQFN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
0.15 C
TOP VIEW
0.10 C
A1
C
A
SEATING
PLANE
20X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
1
NOTE 1
K
N
L
20X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-126-G4 Rev D Sheet 1 of 2
DS20005680B-page 54
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
20-Lead Plastic Quad Flat, No Lead Package (G4) - 4x4 mm Body [QFN]
Also called VQFN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
20
0.50 BSC
0.90
e
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
0.02
0.20 REF
4.00 BSC
2.70
4.00 BSC
2.70
0.25
0.40
2.60
2.80
2.60
0.18
0.30
0.20
2.80
0.30
0.50
-
Terminal-to-Exposed-Pad
K
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-126-G4 Rev D Sheet 2 of 2
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 55
UCS2113
20-Lead Plastic Quad Flat, No Lead Package (G4) - 4x4 mm Body [QFN]
Also called VQFN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
20
1
ØV
2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
V
2.80
2.80
4.00
4.00
Contact Pad Spacing
Contact Pad Width (X20)
Contact Pad Length (X20)
Contact Pad to Center Pad (X16)
Thermal Via Diameter
0.30
0.80
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2126-G4 Rev D
DS20005680B-page 56
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
APPENDIX A: REVISION HISTORY
Revision B (December 2021)
• Added automotive qualification to Features.
• Updated document layout.
• Updated markings and drawings in Section 9.0
“Packaging Information”.
• Updated Product Identification System to include
automotive information and examples.
Revision A (December 2016)
• Original release of this document.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 57
UCS2113
NOTES:
DS20005680B-page 58
2016-2021 Microchip Technology Inc. and its subsidiaries
UCS2113
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[T](1)
–X
–X
/XX
XXX
Examples:
PART NO.
Device
Tape and Reel Version Temperature Package Qualification
Range
a)
b)
c)
d)
e)
UCS2113-1-V/G4:
UCS2113T-1-V/G4:
UCS2113-2-V/G4:
UCS2113T-2-V/G4:
Tube or Tray,
SMBus Address 57h,
Various Temperature,
20-pin 4x4 QFN Package
Device:
UCS2113:
USB Dual-Port Power Switch and Current
Monitor
Tape and Reel,
SMBus Address 57h,
Various Temperature,
20-pin 4x4 QFN Package
Tape and Reel
Option:
<Blank> = Standard packaging (tube or tray)
(1)
Tube or Tray,
T
= Tape and Reel
SMBus Address 56h,
Various Temperature,
20-pin 4x4 QFN Package
Version:
1
2
= SMBus address 57h
= SMBus address 56h
Tape and Reel,
SMBus Address 56h,
Various Temperature,
20-pin 4x4 QFN Package
Temperature Range:
Package:
V
= –40°C to +105°C (Various)
UCS2113T-1-V/G4VAO: Tape and Reel,
SMBus Address 57h,
G4
= Plastic Quad Flat No Lead Package - 4x4 mm
Body with 0.40 mm Contact Length, Saw
Singulated, QFN, 20-lead
Various Temperature,
20-pin 4x4 QFN Package,
Automotive Qualified
Qualification:
<Blank> = Standard Part
VAO = Automotive AEC-Q100 Qualified
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 59
UCS2113
NOTES:
DS20005680B-page 60
2016-2021 Microchip Technology Inc. and its subsidiaries
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only
with Microchip products, including to design, test, and integrate
Microchip products with your application. Use of this informa-
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2016-2021 Microchip Technology Inc. and its subsidiaries
DS20005680B-page 61
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2016-2021 Microchip Technology Inc. and its subsidiaries
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