UPD1001-AV/ST [MICROCHIP]
IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other;型号: | UPD1001-AV/ST |
厂家: | MICROCHIP |
描述: | IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other 光电二极管 外围集成电路 |
文件: | 总51页 (文件大小:994K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UPD1001
Programmable USB Power Delivery Controller
Highlights
Key Benefits
• Integrated USB Power Delivery (PD) PHY
• Support for Power Delivery Message Protocol
• Integrated Voltage and Current ADC Inputs
• Configuration Profile Selection
• On-chip Microcontroller
• Integrated USB Power Delivery (PD) PHY
-
-
Integrated receive termination
Requires minimal external components
• Support for Power Delivery Message Protocol
-
-
-
-
Message Generation/Consumption
Retry Generation
• SPI Interface
Error Handling
• Commercial, Industrial, and Automotive Grade
Temperature Support
State Behavior
• Cable Detect Logic
• Available in 28-TSSOP and 32-SQFN Packages
-
Cable attachment type
• CFG_SEL pins allow selection of multiple profiles
Target Applications
-
-
Provider
Consumer/Provider
• AC Adapters & Chargers
- Type-A
• Integrated Voltage (VMON) and Current (IMON)
ADC Inputs
- Type-B
• Dead Battery Support
• On-chip Microcontroller
- Micro-A
- Micro-B
-
-
Manages I/Os and other signals
Implements power delivery policy engine and
device policy manager
- Captive cable
• Configuration Programming via OTP, or Vendor
Defined Messaging
• Supports Low Power Modes
• Serial Peripheral Interface (SPI) Bus
• Internal 3.3 V and 1.8 V Voltage Regulators
• Integrated Oscillator Reduces BOM Costs
• Package
-
-
28-pin TSSOP (9.7 x 6.1 mm)
32-pin SQFN (5 x 5 mm)
• Environmental
-
-
Commercial temperature range (0°C to +70°C)
Industrial temperature range (-40°C to +85°C)
- Automotive temperature range (-40°C to +105°C)
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UPD1001
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
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To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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UPD1001
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Descriptions and Configuration ................................................................................................................................................. 6
3.0 Functional Descriptions ................................................................................................................................................................. 23
4.0 Operational Characteristics ........................................................................................................................................................... 38
5.0 Package Outlines .......................................................................................................................................................................... 44
6.0 Revision History ............................................................................................................................................................................ 47
The Microchip Web Site ...................................................................................................................................................................... 48
Customer Change Notification Service ............................................................................................................................................... 48
Customer Support ............................................................................................................................................................................... 48
Product Identification System ............................................................................................................................................................. 49
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DS00001759A-page 3
UPD1001
1.0
1.1
INTRODUCTION
General Description
The UPD1001 is a programmable USB Power Delivery (PD) controller designed to adhere to the USB Power Delivery
Specification. USB Power Delivery allows a host (or device) to provide or consume up to 5 Amps and/or up to 20 Volts
of power from a USB PD capable partner device on the other end of the USB cable. USB PD capable standard and
custom cables/connectors are supported, which in most cases are backward compatible with standard USB connec-
tions.
The UPD1001 provides a complete USB Power Delivery solution for all charger and adapter solutions. The functionality
of the UPD1001 is selected via two configuration selection pins, CFG_SEL0 and CFG_SEL1, which can be used to
select unique PD and system configurations. Designing the UPD1001 into a system can be as simple as selecting a
configuration, with no external EEPROM required. Advanced programmability options exist with an external EEPROM
installed.
The integrated USB Power Delivery MAC and PHY support provider and consumer operation via the PD communication
protocol, as specified in Revision 1.0 (Version 1.2) of the USB Power Delivery Specification. Monitoring of VBUS and
battery charging is accomplished via the integrated voltage and current ADC inputs. The PHY supports cable ID detec-
tion/identification and loopback modes. The PHY includes a 24MHz FSK modulator/demodulator and provides inte-
grated terminations. The USB PD MAC supports both USB PD insertion detection (cold socket) and dead battery cases.
The on-chip microcontroller manages the IOs and implements the power delivery local policy engine and device man-
ager. The SPI ROM controller is used by the microcontroller for optional external code execution from ROM. A One Time
Programmable (OTP) ROM is integrated in the UPD1001. Integrated 3.3 V and 1.8 V regulators allow device operation
from a single power supply. The UPD1001 is available in commercial (0°C to +70°C), industrial (-40°C to +85°C), and
automotive (-40°C to +105°C) temperature ranges. An internal block diagram of the UPD1001 is shown in Figure 1-1.
The UPD1001 is offered in 28-pin TSSOP and 32-pin SQFN packages. Each package provides multiple pin configura-
tions, based upon the CFG_SEL0 and CFG_SEL1 Configuration Select signals. Table 1-1 summarizes the available
package/pin combinations and their target applications. Refer to Section 2.0, "Pin Descriptions and Configuration," on
page 6 for detailed information on specific pin configurations.
TABLE 1-1:
UPD1001 PACKAGE/PIN CONFIGURATION SUMMARY
Pin Config.
Name
Package
PD Role
Provider
USB Receptacle
Notes
28-A
28-B
32-A
32-B
Standard-A (STD-A)
See Section 2.1 for pin assignments
See Section 2.1 for pin assignments
See Section 2.2 for pin assignments
See Section 2.2 for pin assignments
28-TSSOP
Consumer/Provider Standard-B (STD-B)
Provider Standard-A (STD-A)
Consumer/Provider Standard-B (STD-B)
32-SQFN
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UPD1001
FIGURE 1-1:
INTERNAL BLOCK DIAGRAM
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UPD1001
2.0
PIN DESCRIPTIONS AND CONFIGURATION
The pinouts for each package, along with system-level application diagrams, are detailed in the following sections:
• 28-Pin TSSOP (28-TSSOP)
• 32-Pin SQFN (32-SQFN)
Note:
For a summary of the available package/pin combinations and their corresponding target applications, refer
to Table 1-1.
Pin descriptions are detailed in Section 2.3, "Pin Descriptions," on page 14. For details on the CFG_SEL0 and CFG_-
SEL1 Configuration Select signals, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)," on
page 24.
2.1
28-Pin TSSOP (28-TSSOP)
2.1.1
28-TSSOP PIN DIAGRAM
FIGURE 2-1:
28-TSSOP PIN ASSIGNMENTS (TOP VIEW)
Note:
Note:
When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example,
RESET_N indicates that the reset signal is active low.
The buffer type for each signal is indicated in the BUFFER TYPE column of Table 2-3, "Pin Descriptions".
A description of the buffer types is provided in Section 2.4, "Buffer Types".
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UPD1001
2.1.2
28-TSSOP PIN ASSIGNMENTS
The UPD1001 28-TSSOP provides two distinct pin configurations (28-A and 28-B) based upon the CFG_SEL0 and
CFG_SEL1 Configuration Select pins. The 28-A and 28-B pin configurations are designed for use with USB Standard-
A and Standard-B receptacles, respectively, and are detailed in Table 2-1. For pin descriptions, refer to Section 2.3, "Pin
Descriptions". For example connection diagrams, refer to Section 2.5, "Power Connection Diagram," on page 22. For
information on the Configuration Select pins, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)".
Note:
The 28-A and 28-B pin configuration assignments differ only on pins 8, 21, and 22.
TABLE 2-1:
Pin Number
28-TSSOP PACKAGE PIN ASSIGNMENTS
Configuration 28-A Name
Configuration 28-B Name
1
VBUS_DISCHARGE
2
SPI_ROM_CE_N
SPI_ROM_CLK
VDDIO
3
4
5
SPI_ROM_DO
SPI_ROM_DI
TEST
6
7
8
CHG_EMU_EN
VSAFEDB_EN
9
CFG_SEL0
CFG_SEL1
FAULT_N
VDD33_CAP
VTR
10
11
12
13
14
VDD18A_CAP
VMON
15
16
IMON
17
VDDIO
18
RESET_N
VSEL0
19
20
VSEL1
21
INSERTION_DETECT
PD_DETECT
NC
22
BULK_CAP
23
PD_EN_N
VDD18_CAP
PD_VDD18
IFAULT
24
25
26
27
28
PD_ID
PD_DATA
VSS
Exposed Pad
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UPD1001
2.1.3
28-TSSOP SYSTEM LEVEL DIAGRAMS
Figure 2-2 and Figure 2-3 provide typical system level diagrams of the UPD1001 for 28-A (Standard-A receptacle) and
28-B (Standard-B receptacle) applications, respectively.
FIGURE 2-2:
CONFIGURATION 28-A SYSTEM-LEVEL DIAGRAM
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UPD1001
FIGURE 2-3:
CONFIGURATION 28-B SYSTEM-LEVEL DIAGRAM
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UPD1001
2.2
32-Pin SQFN (32-SQFN)
2.2.1
32-SQFN PIN DIAGRAM
32-SQFN PIN ASSIGNMENTS (TOP VIEW)
FIGURE 2-4:
Note:
Note:
When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example,
RESET_N indicates that the reset signal is active low.
The buffer type for each signal is indicated in the BUFFER TYPE column of Table 2-3, "Pin Descriptions".
A description of the buffer types is provided in Section 2.4, "Buffer Types".
2.2.2
32-SQFN PIN ASSIGNMENTS
The UPD1001 32-SQFN provides two distinct pin configurations (32-A and 32-B) based upon the CFG_SEL0 and
CFG_SEL1 Configuration Select pins. The 32-A and 32-B pin configurations are designed for use with USB Standard-
A and Standard-B receptacles, respectively, and are detailed in Table 2-2. For pin descriptions, refer to Section 2.3, "Pin
Descriptions". For example connection diagrams, refer to Section 2.5, "Power Connection Diagram," on page 22. For
information on the Configuration Select pins, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)".
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UPD1001
Note:
The 32-A and 32-B pin configuration assignments differ only on pins 14, 15, and 16.
TABLE 2-2:
Pin Number
32-SQFN PACKAGE PIN ASSIGNMENTS
Configuration 32-A Name
Configuration 32-B Name
1
CFG_SEL0
2
CFG_SEL1
IFAULT
3
4
VDD33_CAP
VBUS
5
6
VSW_CAP
VTR
7
8
VDD18A_CAP
SPI_ROM_CE_N
SPI_ROM_CLK
SPI_ROM_DO
SPI_ROM_DI
VDDIO
9
10
11
12
13
14
INSERTION_DETECT
PD_DETECT
BULK_CAP
SAFEDB_EN
NC
15
16
CHG_EMU_EN
17
VMON
IMON
18
19
VDDIO
20
VDD18_CAP
PD_VDD18
PD_EN_N
PD_ID
21
22
23
24
PD_DATA
VBUS_DISCHARGE
TEST
25
26
27
RESET_N
VSEL0_N
VSEL1_N
VSEL2_N
VSEL3_N
FAULT_N
VSS
28
29
30
31
32
Exposed Pad
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UPD1001
2.2.3
32-SQFN SYSTEM LEVEL DIAGRAMS
Figure 2-5 and Figure 2-6 provide typical system level diagrams of the UPD1001 for 32-A (Standard-A receptacle) and
32-B (Standard-B receptacle) applications, respectively.
FIGURE 2-5:
CONFIGURATION 32-A SYSTEM-LEVEL DIAGRAM
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UPD1001
FIGURE 2-6:
CONFIGURATION 32-B SYSTEM-LEVEL DIAGRAM
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UPD1001
2.3
Pin Descriptions
TABLE 2-3:
Name
PIN DESCRIPTIONS
Symbol
Buffer
Type
Description
Power Delivery
Power Deliv-
ery Cable ID
PD_ID
AIO
USB connector signal used to indicate a high-current
power delivery capable cable is inserted. This signal is to
be connected to the PD_ID pin located on the USB PD
Standard-B receptacle.
Power Deliv-
ery VBUS Data
PD_DATA
AIO
Modulated power delivery VBUS data. Requires in-line
isolation filter. Reference schematic available on request.
Power Deliv-
ery Detect
PD_DETECT
IS
(PU)
This signal is to be connected to the PD DETECT pins
located on the USB PD Standard-A receptacle. This sig-
nal is pulled high via an internal pull-up resistor by
default. Assertion (low value) of PD_DETECT qualifies a
USB-PD plug detection event.
Note:
This function is only available in specific
device configurations.
Power
Delivery
Enable
PD_EN_N
VMON
O8
This active low signal controls output of the power supply
voltage onto VBUS. This signal will typically always be
asserted, even when VBUS is 5 V.
Miscellaneous
VBUS Voltage
Monitor
AI
Stepped down voltage representation of the VBUS volt-
age. This signal must be connected to a voltage divider
circuit as specified in Section 2.5, "Power Connection
Diagram," on page 22. Voltage must not exceed 5 V on
this signal. Refer to Section 3.4, "Voltage/Current Moni-
tors (VMON/IMON)," on page 30 for additional informa-
tion.
Charger Cur-
rent Monitor
IMON
AI
Voltage representation of the charger current. This signal
should be fed by a current sense amplifier tuned to output
3.0 V when 6.0 A is flowing on VBUS. Voltage must not
exceed 5 V on this signal. Refer to Section 3.4, "Voltage/
Current Monitors (VMON/IMON)," on page 30 for addi-
tional information.
Power Supply
Fault Indicator
FAULT_N
CFG_SEL0
OD8
AIO
This active low signal can be connected to an external
LED or SoC and is used by the device to indicate power
supply exceptions/failures as determined by the inte-
grated voltage/current monitors. Refer to Section 3.4,
"Voltage/Current Monitors (VMON/IMON)," on page 30
for additional information.
Power Deliv-
ery Profile
Configuration
Selector 0
This pin is used in conjunction with CFG_SEL1 to select
the power delivery profile of the device via an externally
connected RC circuit. Refer to Section 3.3, "Configuration
Selection (CFG_SEL0/CFG_SEL1)" for additional infor-
mation.
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UPD1001
TABLE 2-3:
Name
PIN DESCRIPTIONS (CONTINUED)
Buffer
Symbol
Type
Description
Power Deliv-
ery Profile
Configuration
Selector 1
CFG_SEL1
AIO
This pin is used in conjunction with CFG_SEL0 to select
the power delivery profile of the device via an externally
connected RC circuit. Refer to Section 3.3, "Configuration
Selection (CFG_SEL0/CFG_SEL1)" for additional infor-
mation.
Source
Voltage
Select 0
VSEL0
OD8
This pin is used in conjunction with VSEL1 to select the
correct source voltage from the DC-to-DC or AC-to-DC
solution. VSEL1 and VSEL0 select the voltage value from
the supported voltage capabilities in ascending order with
VSEL0 being the least significant bit (see examples
below).
For example, if an adapter supports 5, 9, and 20 V capa-
bilities, the VSEL1 and VSEL0 selections will be as fol-
lows:
VSEL1 VSEL0
0
0
1
1
0:
1:
0:
1:
5 V
9 V
20 V
RESERVED
In another example, if an adapter supports 5, 9, 12, and
20 V capabilities, the VSEL1 and VSEL0 selections will
be as follows:
VSEL1 VSEL0
0
0
1
1
0:
1:
0:
1:
5 V
9 V
12 V
20 V
For a mapping of the VSEL1/VSEL0 voltage assignments
for each CFG_SEL1/CFG_SEL0 configuration profile,
refer to TABLE 3-3: 28-TSSOP CFG_SELx Configuration
Assignments on page 25.
Note:
This function is only available in specific
device configurations.
Source
Voltage
Select 1
VSEL1
OD8
This signal is used in conjunction with VSEL0 to select
the correct source voltage from the DC-to-DC or AC-to-
DC solution. VSEL0 and VSEL1 select the voltage value
from the supported voltage capabilities in ascending
order.
Refer to the VSEL0 definition for additional information.
Note:
This function is only available in specific
device configurations.
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UPD1001
TABLE 2-3:
PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
Source
Voltage
Select 0
VSEL0_N
OD8
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, VSEL2_N, and VSEL3_N) used to
select the correct source voltage from the DC-to-DC solu-
tion. Each VSELx_N pin is dedicated to one voltage,
assigned in order of increasing supported voltage.
For example, if 5, 12 and 20 V capabilities are supported,
the VSELx_N selections will be as follows:
VSEL0_N = 5 V
VSEL1_N = 12 V
VSEL2_N = 20 V
VSEL3_N = RESERVED
In another example, if only 5 and 20 V care supported,
the VSELx_N selections will be as follows:
VSEL0_N = 5 V
VSEL1_N = 20 V
VSEL2_N = RESERVED
VSEL3_N = RESERVED
The VSELx_N pins are also used to set the overvoltage
protection (OVP) voltage on the VMON pin. The OVP
fault will trigger when the measured voltage on VMON is
10% above the selected voltage setting.
For a mapping of the VSELx_N voltage assignments for
each CFG_SEL1/CFG_SEL0 configuration profile, refer
to Section 3.3, "Configuration Selection (CFG_SEL0/
CFG_SEL1)," on page 24.
Note:
This function is only available in specific
device configurations.
Source
Voltage
Select 1
VSEL1_N
OD8
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, VSEL2_N, and VSEL3_N) used to
select the correct source voltage from the DC-to-DC solu-
tion. Each VSELx_N pin is dedicated to one voltage,
assigned in order of increasing supported voltage.
Refer to the VSEL0_N definition for additional informa-
tion.
Note:
This function is only available in specific
device configurations.
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UPD1001
TABLE 2-3:
Name
PIN DESCRIPTIONS (CONTINUED)
Buffer
Symbol
Type
Description
Source
Voltage
Select 2
VSEL2_N
OD8
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, VSEL2_N, and VSEL3_N) used to
select the correct source voltage from the DC-to-DC solu-
tion. Each VSELx_N pin is dedicated to one voltage,
assigned in order of increasing supported voltage.
Refer to the VSEL0_N definition for additional informa-
tion.
Note:
This function is only available in specific
device configurations.
Source
Voltage
Select 3
VSEL3_N
OD8
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, VSEL2_N, and VSEL3_N) used to
select the correct source voltage from the DC-to-DC solu-
tion. Each VSELx_N pin is dedicated to one voltage,
assigned in order of increasing supported voltage.
Refer to the VSEL0_N definition for additional informa-
tion.
Note:
This function is only available in specific
device configurations.
VBUS
Discharge
VBUS_DISCHARGE
O8
O8
This active high output is used to drive a power NFET to
discharge VBUS during high-to-low voltage transitions in
order to achieve vSafe0V. When asserted, the external
MOSFET should conduct to GND through a current limit-
ing resistor. This signal de-asserts when the VMON sig-
nal voltage reaches a preset value (a percentage of the
destination voltage).
Emulation
Enable
CHG_EMU_EN
This active high output signal can be used to drive the
Emulation Enable pin of a Microchip UCS1001 or similar
device that supports BC 1.2. The device will assert this
signal whenever operating at VSafe5V without a PD con-
tract. Whenever a PD contract is established (even at
5 V), this signal is de-asserted.
Note:
This function is only available in specific
device configurations.
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UPD1001
TABLE 2-3:
PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
Insertion
Detect
INSERTION_DETECT
IS
(PU)
This active low input signal should be connected to the
Insertion Detect pin on the USB Standard-A (STD-A)
receptacle. This signal is pulled high via an internal pull-
up resistor by default. Assertion (low value) qualifies a
STD-A plug insertion event and triggers transition out of
the “Startup” state of the Source Policy engine.
The device firmware implements cold socket detection
using the INSERTION_DETECT signal. Even when
operating as a provider, if the signal is high, the device
will not output voltage on VBUS. VSafe5V will only be
output upon assertion of this signal (low).
Note:
Cold socket (insertion detect) is an optional
feature in the USB PD specification. If this fea-
ture is not being used in a design, the INSER-
TION_DETECT signal must be grounded.
Note:
This function is only available in specific
device configurations.
Dead Battery
Enable
VSAFEDB_EN
O8
This active high output signal is used to enable the dead
battery supply on a USB Standard-B (STD-B) receptacle
(consumer/provider) AC adapter. When no voltage has
been detected on VBUS, this signal is asserted every
10 s to back power an attached provider/consumer and
determine whether the attached device has specified to
be powered per the dead battery mechanisms specified
in the PD specification.
Note:
This function is only available in specific
device configurations.
Bulk
Capacitance
Enable
BULK_CAP
O8
This active high output signal is used to enable/disable
the source bulk capacitance charging. In dual-role ports it
is used to disable the bulk capacitance when operating as
a consumer.
Note:
This function is only available in specific
device configurations.
System Fault
Detect
IFAULT
IS
This active high signal is used by the power supplying
device to notify when a system fault condition has
occurred. This input is typically used for an over-current
or over-voltage condition, but can be used for any system
related failure. An external comparator should be used to
filter any external noise on this input. The device firmware
automatically handles all power exceptions by shutting
down the power supply, re-enabling it, and restarting PD
negotiation until successful.
Note:
The board design must ensure this signal is in
a valid state by the time PD_EN_N asserts.
System Reset
Test
RESET_N
TEST
IS
(PU)
System reset. This signal is active low.
IS
Test signal. This signal is used for internal purposes only
and must be connected to ground through a 1 K resistor
for normal operation.
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UPD1001
TABLE 2-3:
PIN DESCRIPTIONS (CONTINUED)
Buffer
Name
Symbol
Type
Description
No Connect
NC
-
No connect. For proper operation, this signal must not be
connected.
SPI ROM Interface
SPI ROM
Clock
SPI_ROM_CLK
SPI_ROM_CE_N
O8
SPI clock output to the serial ROM
SPI ROM Chip
Enable
O8
This is the active low SPI ROM chip enable output. If the
SPI ROM interface is enabled, this signal should be
pulled up to the SPI ROM Vcc rail.
SPI ROM Data
In
SPI_ROM_DI
SPI_ROM_DO
IS
SPI ROM data in
SPI ROM Data
Out
O8
(PD)
SPI ROM data out
Note:
This signal must be pulled-up to VDDIO with
an external 10 k resistor for proper opera-
tion.
Power/Ground
VTR Supply
Input
VTR
P
+3.3 to +5.0 V main power supply input. This signal must
be connected to a 2.2 μF capacitor to ground. Refer to
Figure 2-7 for additional power connection information.
+3.3 to +5.0 V
Variable Volt-
age I/O Power
VDDIO
P
+3.3 V to +5.0 V variable I/O power supply input. Refer to
Figure 2-7 for additional power connection information.
Note:
When using internal +3.3 V regulator, these
pins must be externally connected to
VDD33_CAP.
+5.0 V VBUS
Input
VBUS
P
Optional +5.0 V auxiliary power input for the integrated
power switch. This signal must be connected to ground or
to a +5.0 V voltage source with a 2.2 μF capacitor to
ground. Refer to Figure 2-7 for additional power connec-
tion information.
Note:
For externally powered devices (AC/DC
adapters, charging adapters, etc.) this power
pin is typically connected to ground.
Note:
This function is only available in specific
device configurations.
+1.8V Power
Delivery
PD_VDD18
P
P
+1.8 V power for Power Delivery PHY. Refer to Figure 2-7
for additional power connection information.
Note:
This pin must be connected to VDD18_CAP
pin externally when using the internal VDD18
regulator.
+1.8 V Power
Capacitance
VDD18_CAP
This pin is used to provide capacitance for the integrated
+1.8 V regulator and must be connected to a 1 μF
(<100 m ESR) capacitor to ground. Refer to Figure 2-7
for additional power connection information.
2014 Microchip Technology Inc.
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UPD1001
TABLE 2-3:
PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
+1.8 V Analog
Power
Capacitance
VDD18A_CAP
P
This pin is used to provide capacitance for the integrated
+1.8 V analog regulator and must be connected to a 1 μF
(<100 m ESR) capacitor to ground. Refer to Figure 2-7
for additional power connection information.
+3.3 V Power
Capacitance
VDD33_CAP
VSW_CAP
P
P
+3.3 V regulator output. This pin must be connected to a
1 μF (<100 m ESR) capacitor to ground. Refer to
Figure 2-7 for additional power connection information.
Integrated
Power Switch
Capacitance
This pin is used to provide capacitance for the integrated
power switch and must be connected to a 1 μF (<100 m
ESR) capacitor to ground. Refer to Figure 2-7 for addi-
tional power connection information.
Note:
This function is only available in specific
device configurations.
Ground
VSS
P
Common ground. This exposed pad must be connected
to the ground plane with a via array.
DS00001759A-page 20
2014 Microchip Technology Inc.
UPD1001
2.4
Buffer Types
TABLE 2-4:
BUFFER TYPES
Buffer Type
Description
IS
O8
Schmitt-triggered input
Output with 8 mA sink and 8 mA source
Open-drain output with 8 mA sink
OD8
PU
50 μA (typical) internal pull-up. Unless otherwise noted in the signal description, internal
pull-ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a
load that must be pulled high, an external resistor must be added.
PD
50 μA (typical) internal pull-down. Unless otherwise noted in the signal description, internal
pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AI
AIO
P
Analog input
Analog bi-directional
Power pin
Note:
All signals are 5 V tolerant.
2014 Microchip Technology Inc.
DS00001759A-page 21
UPD1001
2.5
Power Connection Diagram
Figure 2-7 details the various power connection requirements.
FIGURE 2-7:
POWER CONNECTION DIAGRAM
DS00001759A-page 22
2014 Microchip Technology Inc.
UPD1001
3.0
FUNCTIONAL DESCRIPTIONS
This chapter provides functional descriptions for the various device sub-systems:
• Resets
• Power Management
• Configuration Selection (CFG_SEL0/CFG_SEL1)
• Voltage/Current Monitors (VMON/IMON)
• SPI ROM Controller
3.1
Resets
The device includes the following reset controls:
• Power-On Reset (POR)
• External Chip Reset (RESET_N)
A system reset event via the external RESET_N pin or POR causes the following:
• All registers are set to their default values
• Pins are placed into their default state
The rising and falling Power-On Reset thresholds for each power supply are detailed in Table 3-1.
TABLE 3-1:
POR THRESHOLDS
POR
Rising Threshold
Falling Threshold
VDDIO Supply
VTR Supply
2.7 V
2.35 V
2.7 V
2.85 V
After power up, the POR initially de-asserts after the Rising Threshold is passed. In the event that the supply drops
below the Falling Threshold, the POR will assert. The POR stays asserted until the Rising Threshold is once again
crossed.
3.2
Power Management
The device will enter low power modes based on the state of the connection to the power delivery port partner. The low
power connection states are defined for the device operating as a Provider (Provider/Consumer) or a Consumer (Con-
sumer/Provider).
The device provides the following power states:
• Provider: Wait Insert State
• Consumer: Sink Discovery State
3.2.1
PROVIDER (OR PROVIDER/CONSUMER) POWER STATE
The device Provider configuration will enter a low power mode when it is not connected to a port partner and when a
Standard-A plug is not inserted in the receptacle.
3.2.1.1
Wait Insert State
In the Wait Insert State, the device utilizes the insertion detect feature to enter a standby mode when waiting for a Stan-
dard-A plug to be inserted in the receptacle. On insertion of a Standard-A plug, the device will exit from the standby
mode, initiate operation by enabling the supply output to 5Vsafe, and initiate the discovery of a port partner.
3.2.2
CONSUMER (OR CONSUMER/PROVIDER) POWER STATE
The device Consumer configuration enters a standby mode when it is not connected to a provider.
3.2.2.1
Sink Discovery State
In the Sink Discovery State, the device waits for the presence of VBUS to indicate a connection to provider. The device
enters a standby state when waiting for the presence of VBUS. At the presence of VBUS, the Consumer exits the
standby state and resumes full operation to establish a negotiated power contract with the Provider.
2014 Microchip Technology Inc.
DS00001759A-page 23
UPD1001
3.3
Configuration Selection (CFG_SEL0/CFG_SEL1)
The UPD1001 provides a resistor/capacitor identification detection interface which is utilized to set various device con-
figuration parameters via the Configuration Select pins:
• CFG_SEL0
• CFG_SEL1
Each Configuration Select pin can discriminate a number of quantized RC constants. The judicious selection of RC val-
ues provides a low cost means for system element configuration identification. The Configuration Select pins measure
the charge/discharge time for the RC circuit connected to it (shown in Figure 3-1), providing the ability to differentiate
16 unique “bins” for each Configuration Select pin. The resistor and capacitor values for each Configuration Select bin
are defined in Table 3-2.
FIGURE 3-1:
CFG_SEL0/CFG_SEL1 RESISTOR-CAPACITOR CIRCUIT CONNECTIONS
TABLE 3-2:
Bin
CFG_SELX PIN RESISTOR-CAPACITOR BIN ALLOCATION
Rx (+/-1%)
Cx (+/-10%)
1
2
2.70 k
2.70 k
4.87 k
8.66 k
15.40 k
2.70 k
4.87 k
8.66 k
15.40 k
2.70 k
4.87 k
8.66 k
15.40 k
2.70 k
4.87 k
8.66 k
None
470 pF
470 pF
470 pF
470 pF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
47.0 nF
47.0 nF
47.0 nF
47.0 nF
470 nF
470 nF
470 nF
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note:
CFG_SEL0 and CFG_SEL1 bin definitions are identical.
DS00001759A-page 24
2014 Microchip Technology Inc.
UPD1001
By selecting specific bins on both the CFG_SEL0 and CFG_SEL1 pins, predefined configurations may be selected.
These assignments configure multiple parameters of the device, including the following:
• Pin Configuration
• Receptacle Type
• USB Power Delivery Role Selection
A list of the configuration assignments for each package, along with the corresponding CFG_SEL0 and CFG_SEL1 bin
settings, are detailed in the following sections:
• Section 3.3.1, "28-TSSOP CFG_SELx Configuration Assignments," on page 25
• Section 3.3.2, "32-SQFN CFG_SELx Configuration Assignments," on page 27
For details on each configurable parameter, refer to the following sub-sections.
Captive A cable to micro-B solutions are not listed in the CFG_SELx assignment tables, but can be addressed as fol-
lows:
- When PD_DETECT and INSERTION_DETECT pin are grounded, the device infers a PD cable is always
attached and the source capabilities are limited to 3A.
- The CFG_SELx pin combinations for regular Standard-A solutions can be used for equivalent capabilities.
Captive B cable to A solutions are not listed in the CFG_SELx assignment tables, but can be addressed as follows:
- The proper capacitor marker, as per the USB Power Delivery Specification, should be positioned on the
PD_ID pin to signal a 3A or 5A cable.
- The CFG_SELx pin combinations for regular Standard-B solutions can be used for equivalent capabilities.
Note:
Only the bin combinations defined in the following tables are valid. All other bin combinations are reserved
and must not be used.
3.3.1
28-TSSOP CFG_SELX CONFIGURATION ASSIGNMENTS
Table 3-3 details the various 28-TSSOP CFG_SELx configuration assignments.
TABLE 3-3:
28-TSSOP CFG_SELX CONFIGURATION ASSIGNMENTS
VSEL1/VSEL0
Assignment
00 01 10 11
PD Consumer Abilities
28-A STD-A None
28-A STD-A None
PD Provider Abilities
Profile 1
1
2
3
4
5
6
7
8
9
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
Profile 1, 5V@3A
Profile 1, 5V@5A
Profile 1, 9V@2A
Profile 1, 20V@3A
Profile 1, 20V@5A
Profile 2
28-A STD-A None
28-A STD-A None
28-A STD-A None
28-A STD-A None
28-A STD-A None
28-A STD-A None
28-A STD-A None
-
-
3
9
-
4
20
20
12
9
-
5
-
6
-
7
Profile 2, 9V@2A
Profile 3
12
-
8
12
12
9
9
10 28-A STD-A None
11 28-A STD-A None
12 28-A STD-A None
13 28-A STD-A None
Profile 3, 5V@3A
Profile 3, 9V@3A
Profile 3, 5V@3A, 9V@3A
-
10
11
12
13
12
12
9
Profile 3, 5V@3A, 9V@3A,
16V@3A
9
12 16
14 28-A STD-A None
15 28-A STD-A None
16 28-A STD-A None
17 28-A STD-A None
Profile 3, 9V@3A, PP-200
Profile 3, PP-200
Profile 4
5
5
5
5
9
12
-
-
-
-
-
1
1
1
2
14
15
16
1
12
12 20
12 20
Profile 4, 5V@3A
2014 Microchip Technology Inc.
DS00001759A-page 25
UPD1001
TABLE 3-3:
28-TSSOP CFG_SELX CONFIGURATION ASSIGNMENTS (CONTINUED)
VSEL1/VSEL0
Assignment
00 01 10 11
PD Consumer Abilities
PD Provider Abilities
18 28-A STD-A None
19 28-A STD-A None
20 28-A STD-A None
21 28-A STD-A None
22 28-A STD-A None
23 28-A STD-A None
24 28-A STD-A None
25 28-A STD-A None
26 28-A STD-A None
27 28-A STD-A None
28 28-A STD-A None
29 28-A STD-A None
30 28-A STD-A None
Profile 4, 9V@3A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
9
9
12 20
12 20
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
2
3
Profile 4, 5V@3A, 9V@3A
Profile 4, 5V@3A, 16V@3A
Profile 4, 9V@3A, PP-200
Profile 4, 9V@5A, PP-200
Profile 4, PP-200
12 16 20
4
9
9
12 20
12 20
5
6
12 20
12 20
12 20
-
-
-
7
Profile 5
8
Profile 5, 5V@5A
9
Profile 5, 5V@5A, 16V@5A
Profile 5, 5V@5A, 9V@5A
Profile 5, PP-200
12 16 20
12 20
10
11
12
13
14
15
16
1
9
12 20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Profile VSafe5V-L, 20V@3A
Profile VSafe5V-L, 20V@5A
20
20
-
-
-
31 28-B STD-B NA (Profile VSafe5V-NC) Profile 1
-
32 28-B STD-B NA (Profile VSafe5V-NC) Profile 1, 5V@3A
33 28-B STD-B NA (Profile VSafe5V-NC) Profile 1, 5V@5A
34 28-B STD-B NA (Profile VSafe5V-NC) Profile 1, 9V@2A
35 28-B STD-B NA (Profile VSafe5V-NC) Profile 1, 20V@3A
36 28-B STD-B NA (Profile VSafe5V-NC) Profile 1, 20V@5A
37 28-B STD-B NA (Profile VSafe5V-NC) Profile 2
-
-
-
-
9
-
2
20
20
12
9
-
3
-
4
-
5
38 28-B STD-B NA (Profile VSafe5V-NC) Profile 2, 9V@2A
39 28-B STD-B NA (Profile VSafe5V-NC) Profile 3
12
-
6
12
12
9
7
40 28-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A
41 28-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A, 9V@3A
-
8
12
9
42 28-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A, 9V@3A,
16V@3A
9
12 16
10
43 28-B STD-B NA (Profile VSafe5V-NC) Profile 4
5
5
5
5
5
5
5
5
5
5
5
5
12 20
12 20
-
-
3
3
3
3
3
3
4
4
4
4
4
4
11
12
13
14
15
16
1
44 28-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A
45 28-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A, 16V@3A
46 28-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A, 9V@3A
47 28-B STD-B NA (Profile VSafe5V-NC) Profile 4, PP-200
48 28-B STD-B NA (Profile VSafe5V-NC) Profile 5
12 16 20
12 20
9
12 20
12 20
12 20
-
-
-
49 28-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A
50 28-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A, 16V@5A
51 28-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A, 9V@5A
52 28-B STD-B NA (Profile VSafe5V-NC) Profile 5, PP-200
53 28-B STD-B NA (Profile VSafe5V-NC) Profile VSafe5V-L, 20V@3A
54 28-B STD-B NA (Profile VSafe5V-NC) Profile VSafe5V-L, 20V@5A
12 16 20
12 20
2
9
3
12 20
-
-
-
4
20
20
-
-
5
6
DS00001759A-page 26
2014 Microchip Technology Inc.
UPD1001
3.3.2
32-SQFN CFG_SELX CONFIGURATION ASSIGNMENTS
Table 3-4 details the various 32-SQFN CFG_SELx configuration assignments.
TABLE 3-4:
32-SQFN CFG_SELX CONFIGURATION ASSIGNMENTS
PD Consumer Abilities
32-A STD-A None
32-A STD-A None
PD Provider Abilities
Profile 1
1
2
3
4
5
6
7
8
9
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
Profile 1, 5V@3A
Profile 1, 5V@5A
Profile 1, 9V@2A
Profile 1, 20V@3A
Profile 1, 20V@5A
Profile 2
32-A STD-A None
32-A STD-A None
32-A STD-A None
32-A STD-A None
32-A STD-A None
32-A STD-A None
32-A STD-A None
-
-
3
9
-
4
20
20
12
9
-
5
-
6
-
7
Profile 2, 9V@2A
Profile 3
12
-
8
12
12
9
9
10 32-A STD-A None
11 32-A STD-A None
12 32-A STD-A None
13 32-A STD-A None
Profile 3, 5V@3A
Profile 3, 9V@3A
Profile 3, 5V@3A, 9V@3A
-
10
11
12
13
12
12
9
Profile 3, 5V@3A, 9V@3A,
16V@3A
9
12 16
14 32-A STD-A None
15 32-A STD-A None
16 32-A STD-A None
17 32-A STD-A None
18 32-A STD-A None
19 32-A STD-A None
20 32-A STD-A None
21 32-A STD-A None
22 32-A STD-A None
23 32-A STD-A None
24 32-A STD-A None
25 32-A STD-A None
26 32-A STD-A None
27 32-A STD-A None
28 32-A STD-A None
29 32-A STD-A None
30 32-A STD-A None
Profile 3, 9V@3A, PP-200
Profile 3, PP-200
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
9
12
-
-
-
-
-
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
14
15
16
1
12
Profile 4
12 20
12 20
Profile 4, 5V@3A
Profile 4, 9V@3A
9
9
12 20
12 20
2
Profile 4, 5V@3A, 9V@3A
Profile 4, 5V@3A, 16V@3A
Profile 4, 9V@3A, PP-200
Profile 4, 9V@5A, PP-200
Profile 4, PP-200
3
12 16 20
4
9
9
12 20
12 20
5
6
12 20
12 20
12 20
-
-
-
7
Profile 5
8
Profile 5, 5V@5A
9
Profile 5, 5V@5A, 16V@5A
Profile 5, 5V@5A, 9V@5A
Profile 5, PP-200
12 16 20
12 20
10
11
12
13
14
15
16
1
9
12 20
-
-
-
-
-
-
-
-
-
-
-
Profile VSafe5V-L, 20V@3A
Profile VSafe5V-L, 20V@5A
20
20
-
-
-
31 32-B STD-B NA (Profile VSafe5V-NC) Profile 1
-
32 32-B STD-B NA (Profile VSafe5V-NC) Profile 1, 5V@3A
33 32-B STD-B NA (Profile VSafe5V-NC) Profile 1, 5V@5A
34 32-B STD-B NA (Profile VSafe5V-NC) Profile 1, 9V@2A
35 32-B STD-B NA (Profile VSafe5V-NC) Profile 1, 20V@3A
36 32-B STD-B NA (Profile VSafe5V-NC) Profile 1, 20V@5A
37 32-B STD-B NA (Profile VSafe5V-NC) Profile 2
-
-
-
-
9
-
2
20
20
12
9
-
3
-
4
-
5
38 32-B STD-B NA (Profile VSafe5V-NC) Profile 2, 9V@2A
12
6
2014 Microchip Technology Inc.
DS00001759A-page 27
UPD1001
TABLE 3-4:
32-SQFN CFG_SELX CONFIGURATION ASSIGNMENTS (CONTINUED)
PD Consumer Abilities
PD Provider Abilities
39 32-B STD-B NA (Profile VSafe5V-NC) Profile 3
5
5
5
5
12
12
9
-
-
-
-
-
3
3
3
3
7
8
40 32-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A
41 32-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A, 9V@3A
12
9
42 32-B STD-B NA (Profile VSafe5V-NC) Profile 3, 5V@3A, 9V@3A,
16V@3A
9
12 16
10
43 32-B STD-B NA (Profile VSafe5V-NC) Profile 4
5
5
5
5
5
5
5
5
5
5
5
5
12 20
12 20
-
-
3
3
3
3
3
3
4
4
4
4
4
4
11
12
13
14
15
16
1
44 32-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A
45 32-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A, 16V@3A
46 32-B STD-B NA (Profile VSafe5V-NC) Profile 4, 5V@3A, 9V@3A
47 32-B STD-B NA (Profile VSafe5V-NC) Profile 4, PP-200
48 32-B STD-B NA (Profile VSafe5V-NC) Profile 5
12 16 20
12 20
9
12 20
12 20
12 20
-
-
-
49 32-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A
50 32-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A, 16V@5A
51 32-B STD-B NA (Profile VSafe5V-NC) Profile 5, 5V@5A, 9V@5A
52 32-B STD-B NA (Profile VSafe5V-NC) Profile 5, PP-200
53 32-B STD-B NA (Profile VSafe5V-NC) Profile VSafe5V-L, 20V@3A
54 32-B STD-B NA (Profile VSafe5V-NC) Profile VSafe5V-L, 20V@5A
12 16 20
12 20
2
9
3
12 20
-
-
-
4
20
20
-
-
5
6
3.3.3
PIN CONFIGURATION
Each available UPD1001 package (28-TSSOP and 32-SQFN) provides selectable pin configurations via the CFG_SEL0
and CFG_SEL1 pins, as defined in Table 3-3, "28-TSSOP CFG_SELx Configuration Assignments" and Table 3-4, "32-
SQFN CFG_SELx Configuration Assignments", respectively. Table 1-1, "UPD1001 Package/Pin Configuration Sum-
mary" provides a summary of the available pin configurations for each package. Refer to Section 2.1, "28-Pin TSSOP
(28-TSSOP)" and Section 2.2, "32-Pin SQFN (32-SQFN)" for details on the corresponding package pin definitions.
3.3.4
RECEPTACLE TYPE
The USB receptacle type is configurable between Standard-A and Standard-B types via the CFG_SEL0 and CFG_SEL1
pins, as defined in Table 3-3. Each of these receptacle type settings is detailed below.
3.3.4.1
Standard-A (STD-A)
The Standard-A setting informs the device that the designer is utilizing a Standard-A USB PD receptacle.
3.3.4.2
Standard-B (STD-B)
The Standard-B setting informs the device that the designer is utilizing a Standard-B USB PD receptacle.
3.3.5
USB POWER DELIVERY ROLE SELECTION
Depending on the receptacle type selected, the device may support and swap Consumer and Provider roles.
Standard-A receptacle (captive cable or otherwise) AC adapters only support the Provider role, and therefore do not
support role swap. Standard-B receptacle AC adapters are Consumer/Providers that start operation in their default role
of Consumer and support role swapping.
Swapping rules for Standard-B AC adapters are defined as follows:
• When operating as a Consumer:
- Upon starting up, the AC adapter automatically initiates a swap request to its partner to become a Provider. If
the partner rejects the request, the AC adapter will remain in its Consumer role until the partner requests a
swap.
DS00001759A-page 28
2014 Microchip Technology Inc.
UPD1001
- If the AC adapter receives a swap request from its partner to become a Consumer, it automatically accepts it.
• When operating as a Provider
- The AC adapter will never initiate a swap request to its partner to become a Consumer.
- If the AC adapter receives a swap request from its partner to become a Consumer, it automatically accepts it
and will remain in the Consumer role (until the partner requests another swap back to Provider, or there is a
hard reset or other exception condition that causes the protocol to be re-initiated from startup). The reason for
this behavior is that the partner may have its own other external power which it decided to use instead of the
AC adapter.
Note 1: All AC Adapters will only operate when connected to external AC power. An AC Adapter that is not plugged
to the wall power supply will not be powered from its partner and will therefore not operate at all.
2: Standard-B receptacle AC adapters also support dead battery detection and can perform dead battery
implicit swaps as per the PD specification.
The various Power Delivery Provider and Consumer capabilities are detailed in the following sub-sections.
3.3.5.1
Power Delivery Provider Capabilities
The USB PD Provider capabilities may be selected via the CFG_SEL0 and CFG_SEL1 pins, as defined in Section 3.3,
"Configuration Selection (CFG_SEL0/CFG_SEL1)". Each of the PD Provider capabilities are detailed below. When
capabilities are combined, it is possible that a device can support two or more currents for the same voltage. In this case,
the device will only advertise one voltage with the highest current.
For example, a device that specifies support for “Profile 2 + 5V@3A” must support 5V@2A, 12V@1.5A and 5V@ 3A.
In this case, the device will advertise only two Power Data Objects (PDO): 5V@3A and 12V@1.5A. The device will not
explicitly advertise 5V@2A. However, a consumer that requires 5V@2A will request the 5V@ 3A PDO but only consume
2A.
VSafe5V-L (5V@1A)
The Provider Capability Profile for VSafe5V Legacy (5V@1A) indicates that the UPD1001 supports providing 5 V at 1 A.
This is typically used in dual-role ports that offer no real capability at 5 V (e.g., a Standard-B Consumer-Provider AC
adapter port that only supports 20 V), but need to abide by the USB Power Delivery Specification requirement that at
least one VSafe5V PDO be offered. Therefore, the capabilities of a legacy USB port (max 900 mA for USB 3.0) are
included.
Profile 1
The Provider Capability Profile 1 indicates that the UPD1001 supports providing the voltages and currents needed to
satisfy the USB PD profile 1, as defined by the USB Power Delivery Specification (5V@2A).
Profile 2
The Provider Capability Profile 2 indicates that the UPD1001 supports providing the voltages and currents needed to
satisfy the USB PD profile 2, as defined by the USB Power Delivery Specification (5V@2A and 12V@1.5A).
Profile 3
The Provider Capability Profile 3 indicates that the UPD1001 supports providing the voltages and currents needed to
satisfy the USB PD profile 3, as defined by the USB Power Delivery Specification (5V@2A and 12V@3A).
Profile 4
The Provider Capability Profile 4 indicates that the UPD1001 supports providing the voltages and currents needed to
satisfy the USB PD profile 4, as defined by the USB Power Delivery Specification (5V@2A, 12V@3A, and 20V@3A).
Profile 5
The Provider Capability Profile 5 indicates that the UPD1001 supports providing the voltages and currents needed to
satisfy the USB PD profile 5, as defined by the USB Power Delivery Specification (5V@2A, 12V@5A, and 20V@5A).
5V@3A
The Provider Capability 5V@3A indicates that the UPD1001 supports providing 5 V at 3 A. This option can be combined
with other provider capability options.
5V@5A
The Provider Capability 5V@5A indicates that the UPD1001 supports providing 5 V at 5 A. This option can be combined
with other provider capability options.
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UPD1001
9V@2A
The Provider Capability 9V@2A indicates that the UPD1001 supports providing 9 V at 2 A. This option can be combined
with other provider capability options.
9V@3A
The Provider Capability 9V@3A indicates that the UPD1001 supports providing 9 V at 3 A. This option can be combined
with other provider capability options.
9V@5A
The Provider Capability 9V@5A indicates that the UPD1001 supports providing 9 V at 5 A. This option can be combined
with other provider capability options.
16V@3A
The Provider Capability 16V@3A indicates that the UPD1001 supports providing 16 V at 3 A. This option can be com-
bined with other provider capability options.
16V@5A
The Provider Capability 16V@5A indicates that the UPD1001 supports providing 16 V at 5 A. This option can be com-
bined with other provider capability options.
20V@3A
The Provider Capability 20V@3A indicates that the UPD1001 supports providing 20 V at 3 A. This option can be com-
bined with other provider capability options.
20V@5A
The Provider Capability 20V@5A indicates that the UPD1001 supports providing 20 V at 5 A. This option can be com-
bined with other provider capability options.
Peak Power-Capable Setting 0b11 - 200% (PP-200)
The Peak Power-Capable 200% indicates that the UPD1001 supports providing 200% of the current limit for a 1 ms time
duration at 5% duty cycle. This will add the correct 0b11 bits to the PDO.
3.3.5.2
PD Consumer Capabilities
AC adapters are not intended to be Consumers. However, a need exists for Standard-B receptacle (Consumer/Provider)
AC adapters for powering notebooks through their PD enabled Standard-A host ports. The Power Delivery Specification
requires any consumer port to at least support VSafe5V, so a minimal non-consuming capability is defined (VSafe5V-
NC).
The USB PD Consumer capabilities may be selected via the CFG_SEL0 and CFG_SEL1 pins, as defined in Section 3.3,
"Configuration Selection (CFG_SEL0/CFG_SEL1)". Each of the PD Consumer capabilities are detailed below.
VSafe5V-NC (5V@0A)
The Consumer Capability Profile for VSafe5V Non-Consuming indicates to the UPD1001 that this solution must have
only 5 V input sources and must not consume. This is typically used in dual-role ports that offer no capability in their
default role (e.g., a Standard-B Consumer-Provider AC adapter port).
3.4
Voltage/Current Monitors (VMON/IMON)
3.4.1
VMON
The integrated voltage monitor utilizes the VMON pin to read a stepped down voltage representation of the VBUS volt-
age. This pin must be connected to a voltage divider circuit as specified in Section 2.5, "Power Connection Diagram,"
on page 22. The device monitors the VBUS voltage as a provider to manage the behavior of the power supply, detecting
power supply transitions and over/under-voltage conditions.
3.4.1.1
Power Supply Transitions
Using VMON, the device monitors the voltage on VBUS to manage the transitions of the supply output. The supply
power-on and power-off transitions are determined to be at their final states when reaching predefined voltage thresh-
olds, as detailed in Table 3-5. The power-on threshold indicates when the supply has reached the defined voltage. The
power-off threshold indicates when the supply output is discharged. All voltage transitions are bound by an internal
timer. If the voltage transition times out, the FAULT_N pin will be asserted until the power transition is successfully com-
pleted.
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UPD1001
TABLE 3-5:
VMON POWER-ON/OFF TRANSITION THRESHOLDS
Voltage Threshold
Min.
Typical
Max
Power-On
Power-Off
TBD
TBD
TBD
TBD
TBD
TBD
3.4.1.2
Overvoltage Condition
Using VMON, the device monitors the voltage on VBUS to detect an overvoltage condition on the supply output. The
overvoltage condition is determined when the predefined overvoltage threshold is crossed, as detailed in Table 3-6.
On the occurrence of the overvoltage condition:
•
The supply output will turned off and discharged with an average power-off response time of TBD.
• The FAULT_N pin will be strobed approximately every 500ms.
• If more than 3 consecutive exceptions occur within a 4 second period, FAULT_N will be strobed approximately
every 5 seconds.
TABLE 3-6:
VMON OVERVOLTAGE THRESHOLDS
Voltage Threshold
Typical
TBD
Min.
Max
Overvoltage
TBD
TBD
3.4.1.3
Undervoltage Condition
Using VMON, the device monitors the voltage on VBUS to detect an undervoltage condition on the supply output. The
undervoltage condition is determined when the predefined undervoltage threshold is crossed, as detailed in Table 3-7.
On the occurrence of the undervoltage condition:
•
The supply output will turned off and discharged with an average power-off response time of TBD.
• The FAULT_N pin will be strobed approximately every 500ms.
• If more than 3 consecutive exceptions occur within a 4 second period, FAULT_N will be strobed approximately
every 5 seconds.
TABLE 3-7:
VMON UNDERVOLTAGE THRESHOLDS
Voltage Threshold
Min.
Typical
Max
Undervoltage
TBD
TBD
TBD
3.4.2
IMON
The integrated current monitor utilizes the IMON pin to read a voltage representation of the power supply output current.
This pin should be fed by a current sense amplifier tuned to output 3.0 V when 6.0 A is flowing on VBUS. On connection
of a port partner and the completion of a negotiated power contract, the overcurrent threshold is set based on the nego-
tiated current. When the device is not connected to a port partner, the overcurrent threshold will be set to the default
level. On the occurrence of an overcurrent condition:
• The supply output will turned off and discharged with an average power-off response time of TBD.
• The FAULT_N pin will be strobed approximately every 500ms.
• If more than 3 consecutive exceptions occur within a 4 second period, FAULT_N will be strobed approximately
every 5 seconds.
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UPD1001
TABLE 3-8:
IMON OVERCURRENT THRESHOLDS
Overcurrent Threshold
Typical
Negotiated Profile
Current
Min.
Max
2 A (Default)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3 A
5 A
Note:
Only sourced currents (when the PD port is operating as a provider) can be monitored by IMON. If it is
desired to monitor a sinking current (when the port is operating as a consumer), an external circuit should
be used and the condition indicated to the device via the IFAULT pin.
3.5
SPI ROM Controller
The device is capable of code execution from an external SPI ROM. On power up, the firmware looks for an external
SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a
valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the
external SPI device. If a valid signature is not found, then execution continues from internal ROM. The following sections
describe the interface options to the external SPI ROM.
Note:
Microchip suggests using the SST 25 series serial flash family, such as the SST25VF064C.
3.5.1
OPERATION OF THE HI-SPEED READ SEQUENCE
The SPI controller will automatically handle code reads going out to the SPI ROM Address. When the controller detects
a read, the controller drops the SPI_ROM_CE_N, and puts out a 0x0B, followed by the 24-bit address. The SPI controller
then puts out a DUMMY byte. The next eight clocks clock in the first byte. When the first byte is clocked in a ready signal
is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_ROM_CE_N high. As long as the addresses are sequential, the
SPI Controller will keep clocking in data.
FIGURE 3-2:
SPI ROM HI-SPEED READ OPERATION
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UPD1001
FIGURE 3-3:
SPI ROM HI-SPEED READ SEQUENCE
3.5.2
OPERATION OF THE DUAL HI-SPEED READ SEQUENCE
The SPI controller also supports dual data mode (at 30 MHz SPI speed only). When configured in dual mode, the SPI
controller will automatically handle reads going out to the SPI ROM. When the controller detects a read, the controller
drops the SPI_ROM_CE_N, and puts out a 0x3B, followed by the 24-bit address. The SPI controller then puts out a
DUMMY byte. The next four clocks clock in the first byte. The data appears two bits at a time on data out and data in.
When the first byte is clocked in a ready signal is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, the address will change. If the address is one more than the last address, the SPI
controller will clock out one more byte. If the address in anything other than one more than the last address, the SPI
controller will terminate the transaction by taking SPI_ROM_CE_N high. As long as the addresses are sequential, the
SPI Controller will keep clocking in data.
FIGURE 3-4:
SPI ROM DUAL HI-SPEED READ OPERATION
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FIGURE 3-5:
SPI ROM DUAL HI-SPEED READ SEQUENCE
3.5.3
32-BYTE CACHE
There is a 32-byte pipeline cache, and associated with the cache is a base address pointer and a length pointer. Once
the SPI controller detects a jump, the base address pointer is initialized to that address. As each new sequential data
byte is fetched, the data is written into the cache, and the length is incremented. If the sequential run exceeds 32 bytes,
the base address pointer is incremented to indicate the last 32 bytes fetched. If the device does a jump, and the jump
is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access.
3.5.4
INTERFACE OPERATION TO SPI PORT WHEN NOT PERFORMING FAST READS
There is an 8-byte command buffer: SPI_CMD_BUF[7:0]; an 8-byte response buffer: SPI_RESP_BUF[7:0]; and a length
register that counts out the number of bytes: SPI_CMD_LEN. Additionally, there is a self-clearing GO bit in the SPI_CTL
Register. Once the GO bit is set, the device drops SPI_ROM_CE_N, and starts clocking. It will put out SPI_CMD_LEN
X 8 number of clocks. After the first byte, the COMMAND, has been sent out, and the SPI_ROM_DI is stored in the
SPI_RESP buffer. If the SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the
SPI_ROM_DO line. This mode is used for program execution out of internal RAM or ROM.
FIGURE 3-6:
SPI ROM INTERNALLY-CONTROLLED OPERATION
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UPD1001
3.5.4.1
Erase Example
To perform a SCTR_ERASE, 32BLK_ERASE, or 64BLK_ERASE, the device writes 0x20, 0x52, or 0xD8, respectively
to the first byte of the command buffer, followed by a 3-byte address. The length of the transfer is set to 4 bytes. To do
this, the device first drops SPI_ROM_CE_N, then counts out 8 clocks. It then puts out the 8 bits of command, followed
by 24 bits of address of the location to be erased on the SPI_ROM_DO pin. When the transfer is complete, the
SPI_ROM_CE_N goes high, while the SPI_ROM_DI line is ignored in this example.
FIGURE 3-7:
SPI ROM ERASE SEQUENCE
3.5.4.2
Byte Program Example
To perform a Byte Program, the device writes 0x02 to the first byte of the command buffer, followed by a 3-byte address
of the location that will be written to, and one data byte. The length of the transfer is set to 5 bytes. The device first drops
SPI_ROM_CE_N, 8 bits of command are clocked out, followed by 24 bits of address, and one byte of data on the
SPI_ROM_DO pin. The SPI_ROM_DI line is not used in this example.
FIGURE 3-8:
SPI ROM BYTE PROGRAM
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3.5.4.3
Command Only Program Example
To perform a single byte command such as the following:
• WRDI
• WREN
• EWSR
• CHIP_ERASE
• EBSY
• DBSY
The device writes the opcode into the first byte of the SPI_CMD_BUF and the SPI_CMD_LEN is set to one. The device
first drops SPI_ROM_CE_N, then 8 bits of the command are clocked out on the SPI_ROM_DO pin. The SPI_ROM_DI
is not used in this example.
FIGURE 3-9:
SPI ROM COMMAND ONLY SEQUENCE
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UPD1001
3.5.4.4
JEDEC-ID Read Example
To perform a JEDEC-ID command, the device writes 0x9F into the first byte of the SPI_CMD_BUF and the length of the
transfer is 4 bytes. The device first drops SPI_ROM_CE_N, then 8 bits of the command are clocked out, followed by the
24 bits of dummy bytes (due to the length being set to 4) on the SPI_ROM_DO pin. When the transfer is complete, the
SPI_ROM_CE_N goes high. After the first byte, the data on SPI_ROM_DI is clocked into the SPI_RSP_BUF. At the end
of the command, there are three valid bytes in the SPI_RSP_BUF. In this example, 0xBF, 0x25, 0x8E.
FIGURE 3-10:
SPI ROM JEDEC-ID SEQUENCE
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4.0
4.1
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VDDIO, VTR) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +6.0 V
Positive voltage on input signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +/-2 kV
Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 4.2, "Operating Conditions**", Section 4.4,
"DC Specifications", or any other applicable section of this specification is not implied.
4.2
Operating Conditions**
Supply Voltage (VTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.1 V to +5.3 V
Supply Voltage (VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.1 V to +3.47 V
Positive voltage on input signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V
Positive voltage on VMON and IMON pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDDIO
Negative voltage on VMON and IMON pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V
Power Supply Rise Time Max tRT (Figure 4-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBD
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 2
Note2:0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
FIGURE 4-1:
SUPPLY RISE TIME MODEL
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UPD1001
4.3
Power Consumption
This section details the power consumption of the device as measured during various modes of operation. Power dis-
sipation is determined by temperature, supply voltage, and external source/sink requirements.
TABLE 4-1:
DEVICE POWER CONSUMPTION
VTR Supply Current (VTR = 5.0V)
Power State
Min
Typical
Max
Units
RESET
275
μA
PROVIDER MODE
Wait Insert State
1.2
mA
mA
mA
Legacy Device Connected
PD Device Connected
14.6
28.0
CONSUMER MODE
Sink Discovery State /
Legacy Device Connected
7.4
mA
mA
PD Device Connected
28.0
4.4
DC Specifications
TABLE 4-2:
DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
IS Type Input Buffer
Low Input Level
VILI
VIHI
-0.3
2.5
0.8
V
V
High Input Level
VDDIO+0.3
1.55
Negative-Going Threshold
Positive-Going Threshold
Schmitt Trigger Hysteresis
VILT
VIHT
VHYS
1.25
1.40
188
1.35
1.65
225
V
Schmitt trigger
Schmitt trigger
1.76
V
250
mV
(VIHT - VILT
)
Input Leakage
(VIN = VSS or VDDIO)
IIH
-9.79
7.14
3
nA
pF
Note 3
Input Capacitance
CIN
O8 Type Buffers
Low Output Level
VOL
VOH
0.35
V
V
IOL = -8 mA
High Output Level
VDDIO - 0.7
IOH = 8 mA
OD8 Type Buffer
Low Output Level
VOL
0.35
V
IOL = -8 mA
Note3:This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up
resistors add +/- 50 μA per-pin (typical).
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UPD1001
4.5
AC Specifications
This section details the various AC timing specifications of the device.
4.5.1
RESET TIMING
Figure 4-2 illustrates the RESET_N timing requirements. Assertion of RESET_N is not a requirement. However, if used,
it must be asserted for the minimum period specified.
Refer to Section 3.1, "Resets," on page 23 for additional information on resets.
FIGURE 4-2:
RESET_N TIMING
TABLE 4-3:
Symbol
trstia
RESET_N TIMING
Description
RESET_N input assertion time
Min
Typ
Max
Units
1
μs
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UPD1001
4.5.2
VMON/IMON FAULT RECOVERY TIMING
Figure 4-3 illustrates the fault recovery timing due to VMON/IMON threshold trigger. Refer to the VMON/IMON pin
descriptions and Section 3.4, "Voltage/Current Monitors (VMON/IMON)" for additional information. For IFAULT related
recovery timing, refer to Section 4.5.3, "IFAULT Recovery Timing".
Note:
As shown in Figure 4-3, after a VMON/IMON fault condition is detected, the VSEL0/VSEL1 (28-TSSOP) or
VSEL0_N/VSEL1_N/VSEL2_N/VSEL3_N (32-SQFN) signals will reassign to support 5V (default) operation
(00b for 28-TSSOP or 0111b for 32-SQFN).
FIGURE 4-3:
VMON/IMON FAULT RECOVERY TIMING
TABLE 4-4:
Symbol
VMON/IMON FAULT RECOVERY TIMING
Description
Typ
Max
Units
t1
t2
Fault to PD_EN_N, VBUS_DISCHARGE assertion
VBUS_DISCHARGE assertion time (Note 4)
20
-
TBD
TBD
ms
ms
Note4: VBUS_DISCHARGE will assert and remain asserted only until the voltage on VBUS falls below 0.5V.
Therefore, the duration of the VBUS_DISCHARGE pulse (t2) will be application specific and does not have
a minimum or typical value. If the voltage never falls below the discharge threshold, a timeout will occur and
VBUS_DISCHARGE will de-assert after t2 MAX.
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4.5.3
IFAULT RECOVERY TIMING
Figure 4-4 illustrates the IFAULT fault recovery timing as it relates to various device signals. Refer to the IFAULT pin
description for additional information. For VMON/IMON fault related timing, refer to Section 4.5.2, "VMON/IMON Fault
Recovery Timing".
Note:
As shown in Figure 4-4, after a IFAULT condition, the VSEL0/VSEL1 (28-TSSOP) or VSEL0_N/VSEL1_N/
VSEL2_N/VSEL3_N (32-SQFN) signals will reassign to support 5V (default) operation (00b for 28-TSSOP
or 0111b for 32-SQFN).
FIGURE 4-4:
IFAULT RECOVERY TIMING
TABLE 4-5:
Symbol
IFAULT RECOVERY TIMING
Description
Typ
Max
Units
t1
t2
t3
IFAULT to PD_EN_N assertion
100
TBD
TBD
TBD
μs
ms
ms
PD_EN_N to VBUS_DISCHARGE assertion time
VBUS_DISCHARGE assertion time (Note 5)
4
-
Note5: VBUS_DISCHARGE will assert and remain asserted only until the voltage on VBUS falls below 0.5V.
Therefore, the duration of the VBUS_DISCHARGE pulse (t3) will be application specific and does not have
a minimum or typical value. If the voltage never falls below the discharge threshold, a timeout will occur and
VBUS_DISCHARGE will de-assert after t3 MAX.
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UPD1001
4.5.4
SPI ROM CONTROLLER TIMING
The following specifies the SPI ROM Controller timing requirements for the device.
FIGURE 4-5:
SPI ROM CONTROLLER TIMING
TABLE 4-6:
Symbol
SPI ROM CONTROLLER TIMING VALUES
Description
Min
Typ
Max
Units
tfc
tceh
tclq
tdh
tos
Clock frequency
46.86
48
50
15
3
48.62
MHz
ns
Chip enable (SPI_ROM_CE_EN) high time
Clock to input data
ns
Input data hold time
0.70
5.35
11.57
1.16
4.52
8.28
15.22
3.3
ns
Output setup time
7
ns
toh
tov
tcel
tceh
Output hold time
13
2
ns
Clock to output valid
ns
Chip enable (SPI_ROM_CE_EN) low to first clock
Last clock to chip enable (SPI_ROM_CE_EN) high
12
12
ns
ns
4.5.5
USB POWER DELIVERY SIGNAL TIMING
All USB Power Delivery signals (PD_DATA, PD_ID) conform to the voltage, power, and timing characteristics/specifica-
tions as set forth in the USB Power Delivery Specification. Please refer to the USB Power Delivery Specification, avail-
able at http://www.usb.org.
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UPD1001
5.0
5.1
PACKAGE OUTLINES
28-TSSOP
Note:
For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 5-1:
28-TSSOP PACKAGE (DRAWING)
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UPD1001
FIGURE 5-2:
28-TSSOP PACKAGE (DIMENSIONS)
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UPD1001
5.2
32-SQFN
Note:
For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 5-3:
32-SQFN PACKAGE
DS00001759A-page 46
2014 Microchip Technology Inc.
UPD1001
6.0
REVISION HISTORY
TABLE 6-1:
REVISION HISTORY
Revision Level &
Date
Section/Figure/Entry
Correction
DS00001759A
Initial Release
2014 Microchip Technology Inc.
DS00001759A-page 47
UPD1001
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
DS00001759A-page 48
2014 Microchip Technology Inc.
UPD1001
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
[X]
XX
XX
-
/
PART NO.
Device
a)
UPD1001-A/ST
Tray, Commercial temp., 28-pin TSSOP
Tape and Reel Temperature
Option
Range
Package
b)
UPD1001T-AI/MQ
Tape & reel, Industrial temp., 32-pin SQFN
Device:
UPD1001
Tape and Reel
Option:
Blank = Standard packaging (tray)
T
= Tape and Reel(Note 1)
Temperature
Range:
A
AI
AV
=
=
=
0C to +70C (Commercial)
-40C to +85C (Industrial)
-40C to +105C (Automotive)
Package:
ST
MQ
=
=
28-pin TSSOP
32-pin SQFN
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
2014 Microchip Technology Inc.
DS00001759A-page 49
UPD1001
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of
Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-
itly or otherwise, under any Microchip intellectual property rights.
Trademarks
32
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC
logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM,
MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-
Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
flexPWR, JukeBlox, Kleer, KleerNet, MediaLB, and MOST
The preceding is a non-exhaustive list of trademarks in use in the US and other countries. For a complete list of trademarks, email a
request to legal.department@microchip.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver
of any intellectual property rights that SMSC has established in any of its trademarks.
All other trademarks mentioned herein are property of their respective companies.
© 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781632762535
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00001759A-page 50
2014 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
2014 Microchip Technology Inc.
DS00001759A-page 51
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