UPD360-B6HX [MICROCHIP]
Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port Controller;
| 型号： | UPD360-B6HX |
| 厂家： | 
MICROCHIP |
| 描述： | Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port Controller |
| 文件： | 总221页 (文件大小：1949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UPD360
Highly Integrated Small Form Factor
USB Type-C™ Power Delivery 2.0 Port Controller
• USB Power Delivery MAC
Highlights
- Compliant with USB Power Delivery
Specification Revision 2.0
• Small Form Factor 4 x 4 mm 44-WFBGA Package
• Integrated Analog Discrete Components Reduce
Bill of Materials and Design Footprint
- Power Delivery Packet Framing
- CRC Checking/Generation
• USB Power Delivery 2.0 Compliant MAC
• USB Type-CTM (1) Connector Support with
Connection Detection and Control
- 4B/5B Encoding/Decoding
- BMC Encoding/Decoding
- EOP/SOP Generation for PD Frames
- SOP Detection and SOP Header Processing
- Separate RX/TX FIFOs
• I2C/SPI (2) Interface for CPU/SoC Communication
• USB Type-C™ Alternate Mode Support
• Dual Role Power (DRP) and Role Swap Support
- Automatic GoodCRC Message Generation
- Automatic Retry Generation
Target Applications
- Error Handling
• Notebook Computers
• All-in-One/Desktop PCs
• Smartphones
• Tablets
- Low Standby Power Support via Sleep State
• USB Type-C Cable Detect Logic
- Auto Cable Attach & Orientation Detection
- Routes Baseband Communication to
Respective CC Pin per Detected Orientation
• Monitors
• Docking Stations
• HDTVs
- VCONN Supply Control for Active Cable
- Configurable Downstream Facing Port (DFP)
and Upstream Facing Port (UFP) Modes
• Printers
- Charging Current Capability Detection
Key Benefits
- Detection of Debug Accessory Mode,
Audio Adapter Accessory Mode
• +1.8V I2C (1 MHz) Interface Supports Communi-
cation/Configuration via Companion CPU/SoC
• Integrated Analog Discrete Components
- VCONN FETs with Rp/Rd Switching
- Dead Battery Rd termination
• Alternate Mode Support
- Programmable Current Sense for
Overcurrent Conditions
- DisplayPortTM, ThunderboltTM
and other Major Protocols
,
- Voltage Sense for Overvoltage Conditions
• Integrated 5V/3A Port Power Controller (PPC)
- Supports up to 5V/3A on VBUS
• CFG_SEL0 Pin for Selection of Device Mode
• CFG_SEL1 Pin for Selection of I2C addresses (2)
• Power and I/Os
- Supplies 500mA, 900mA, 1.5A, and 3.0A per
USB Type-C™ Specification
- Integrated 1.8V Voltage Regulator
- 16 Configurable General Purpose I/O Pins
• Software
• Integrated 3.3V Power Switch
- Provides Dead Battery Support
- C Libraries
- Automatically Switch between VBUS and
Main +3.3V
• Package
- 44-ball WFBGA (4 x 4 x 0.7 mm)
• Environmental
- Commercial Temperature Range
(0°C to +70°C)
1. USB Type-C™ and USB-C™ are trademarks of
USB Implementers Forum.
2. Available only in select UPD360 configurations.
2016-2017 Microchip Technology Inc.
DS00002084C-page 1
UPD360
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Documentation
To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002084C-page 2
2016-2017 Microchip Technology Inc.
UPD360
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 7
3.0 Ball Descriptions and Configuration ................................................................................................................................................ 9
4.0 Register Map ................................................................................................................................................................................. 19
5.0 I2C Slave Controller (UPD360-A/UPD360-B Only) ....................................................................................................................... 20
6.0 SPI Slave Controller (UPD360-C Only) ........................................................................................................................................ 26
7.0 Clocks, Resets, and Power Management ..................................................................................................................................... 31
8.0 System Control ............................................................................................................................................................................. 35
9.0 Cable Plug Orientation and Detection ........................................................................................................................................... 68
10.0 Baseband CC Interface (BCI) ................................................................................................................................................... 107
11.0 Power Delivery MAC ................................................................................................................................................................. 111
12.0 USB Port Power Controller (PPC) ............................................................................................................................................ 171
13.0 Power Switch ............................................................................................................................................................................ 182
14.0 DisplayPort Hot Plug Detect (HPD) .......................................................................................................................................... 195
15.0 Watchdog Timer (WDT) ............................................................................................................................................................ 202
16.0 Operational Characteristics ....................................................................................................................................................... 206
17.0 Package Information ................................................................................................................................................................. 214
Appendix A: Data Sheet Revision History ......................................................................................................................................... 217
The Microchip Web Site .................................................................................................................................................................... 218
Customer Change Notification Service ............................................................................................................................................. 218
Customer Support ............................................................................................................................................................................. 218
Product Identification System ........................................................................................................................................................... 219
2016-2017 Microchip Technology Inc.
DS00002084C-page 3
UPD360
1.0
1.1
PREFACE
Glossary of Terms
TABLE 1-1:
Term
GLOSSARY OF TERMS
Definition
ADC
Analog to Digital Converter
Analog Front End
AFE
BCI
Baseband CC Interface
Billboard
USB Billboard Device. A required USB device class for UFPs which support Alternate Modes
in order to provide product information to the USB Host.
BIST
BMC
Byte
CC
Built-In Self Test
Bi-phase Mark Coding
8-bits
Generic reference to USB Type-C™ Cable / Connector CC1/CC2 pins
CSR
DB
Control and Status Register
Dead Battery
DFP
DP
Downstream Facing Port (USB Type-C™ Specification definition)
DisplayPort (a VESA standard interface)
DPM
DRP
DWORD
EC
Device Policy Manager (PD Specification definition)
Dual Role Power (USB Type-C™ Specification definition)
32-bits
Embedded Controller
EP
USB Endpoint
FIFO
FW
First In First Out buffer
Firmware
FS
Full-Speed
Host
HPD
External system (Includes processor, application software, etc.)
Hot-Plug Detect functionality as defined by DisplayPort and DisplayPort Alternate Mode speci-
fications
HS
High-Speed
HW
Hardware (Refers to function implemented by the device)
Integrated Circuit
IC
IFC
InterFrame Gap
LDO
Linear Drop-Out regulator
Media Access Controller
Microchip Technology Incorporated
Not Applicable
MAC
Microchip
N/A
OCS
PCS
Over-Current Sense
Physical Coding Sublayer
USB Power Delivery
PD / UPD
PIO
General Purpose I/O
PMIC
POR
PRBS
QWORD
SA
Power Management Integrated Circuit
Power-On Reset
Pseudo Random Binary Sequence
64-bits
Source Address
DS00002084C-page 4
2016-2017 Microchip Technology Inc.
UPD360
TABLE 1-1:
Term
GLOSSARY OF TERMS (CONTINUED)
Definition
SBU
SideBand Use
SCSR
SPM
System Control and Status Register
System Policy Manager (PD Specification definition)
SuperSpeed
SS
SVDM
SVID
Standard/Vendor Defined Message (PD Specification definition)
Standard/Vendor IDentity (PD Specification definition)
USB Type-C™ Port Controller
TCPC
UFP
Upstream Facing Port (USB Type-C™ Specification definition)
Universal Serial Bus
USB
USB Type-C™
VDO
USB Type-C™ Cable / Connector
Vendor-defined Object (PD Specification definition)
Vendor Specific Messaging
VSM
WORD
ZLP
16-bits
Zero Length USB Packet
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPES
Description
Buffer Type
IS
I2C
O8
Schmitt-triggered input
I2C interface
Output with 8 mA sink and 8 mA source
Open-drain output with 8 mA sink
OD8
PU
70k (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups
are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD
70k (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-
downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AIO
P
Analog bidirectional
Power pin
Note:
Note:
Digital signals are not 5V tolerant unless specified.
Refer to Section 16.5, "DC Characteristics," on page 208 for the electrical characteristics of the various buf-
fers.
2016-2017 Microchip Technology Inc.
DS00002084C-page 5
UPD360
1.3
Register Nomenclature
TABLE 1-3:
REGISTER NOMENCLATURE
Register Bit Type Notation
Register Bit Description
R
W
Read: A register or bit with this attribute can be read.
Write: A register or bit with this attribute can be written.
Read only: Read only. Writes have no effect.
RO
RS
Read to Set: This bit is set on read.
WO
W1S
W1C
WC
LL
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Set: Writing a one sets the value. Writing a zero has no effect.
Write One to Clear: Writing a one clears the value. Writing a zero has no effect.
Write Anything to Clear: Writing anything clears the value.
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
RO/LH
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it
is read, the bit will remain high, but will change to low if the condition that caused the
bit to go high is removed. If the bit has not been read, the bit will remain high regard-
less of a change to the high condition.
NASR
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise indi-
cated, to ensure future compatibility. The value of reserved bits is not guaranteed on a
read.
1.4
References
• NXP I2C-Bus Specification (UM10204, April 4, 2014): www.nxp.com/documents/user_manual/UM10204.pdf
• USB Power Delivery and USB Type-C™ Specifications: http://www.usb.org/developers/docs/usb_31_102015.zip
• VESA DisplayPort Alternate Mode Specification 1.0: http://www.vesa.org
DS00002084C-page 6
2016-2017 Microchip Technology Inc.
UPD360
2.0
2.1
INTRODUCTION
General Description
The UPD360 is a highly integrated, small form factor USB Type-C Power Delivery (PD) Port Controller designed to
adhere to the USB Type-C™ Cable and Connector Specification and USB Power Delivery 2.0 Specification. The
UPD360 provides cable plug orientation and detection for a USB Type-C receptacle and implements baseband commu-
nication with a partner USB Type-C device via the integrated USB Power Delivery 2.0 MAC. The device can function in
Standalone UFP/DFP modes, or utilize the integrated I2C/SPI interface to connect to a companion CPU/SoC (depen-
dent on device version, see Section 2.2, "UPD360 Family Differences Summary").
Additionally, the UPD360 integrates many of the analog discrete components required for USB Type-C PD applications,
including two VCONN FETs with Rp/Rd switching, a port power controller that supports up to 5V/3A on VBUS, and cur-
rent and voltage sense circuitry for over-voltage/current detection. By integrating many of the analog discrete compo-
nents required for USB Type-C PD applications, the UPD360 provides a low cost, low power, small footprint (4 x 4 mm)
solution for consumer (notebooks, desktop PCs, smartphones, tablets, monitors, docking stations) applications.
To enable the UPD360 to efficiently support dead battery use cases, an integrated power switch is provided to select
between two external 3.3V supplies (VBUS and main). This effectively allows connection detection and system wakeup
without external processor intervention (external processor in sleep mode).
The UPD360 is also capable of negotiating alternate modes over USB Type-C connectors using the Power Delivery 2.0
protocol. Both DisplayPort and Thunderbolt operation over USB Type-C connectors are supported in addition to other
major protocols.
A system diagram utilizing the UPD360 is shown in Figure 2-1. An internal block diagram of the UPD360 is shown in
Figure 2-2.
FIGURE 2-1:
SYSTEM BLOCK DIAGRAM
VBUS
Microchip
UPD360
I2C/SPI
SoC
CC1
CC2
USB Crossbar /
Alternate Mode Switches
2016-2017 Microchip Technology Inc.
DS00002084C-page 7
UPD360
FIGURE 2-2:
INTERNAL BLOCK DIAGRAM
Rp‐High
Rp‐Low
Rd
CC1
VCONN(5V)
Rp‐High
Rp‐Low
Rd
CC2
VCONN(5V)
3V3_ALW
Power
Delivery
2.0
5V/3A
Auto
Power
Switch
Baseband
CC
Interface
VBUS
Port
3V3_VBUS
Power
Controller
MAC
VSW
1.8V LDO
Regulator
I2C
OCS_COMP1
OCS_COMP2
SPI
Over‐
Current
Detection
GPIOs
(16x)
Controller
Controller
(UPD360‐A: +1.8V)
(UPD360‐B: +3.3V)
(UPD360‐C Only)
UPD360
I2C
SPI
GPIO[0:15]
in UPD360‐C)
(GPIO0 not available
(UPD360‐A/B Only)
(UPD360‐C Only)
2.2
UPD360 Family Differences Summary
The UPD360 is available in three versions:
• UPD360-A
• UPD360-B
• UPD360-C
A summary of the differences between these versions is provided in Table 2-1. Device specific features that do no per-
tain to the entire UPD360 family are called out independently throughout this document. For ordering information, refer
to the Product Identification System on page 219.
TABLE 2-1:
Device
UPD360 FAMILY DIFFERENCES
+1.8V I2C Interface +3.3V I2C Interface
SPI Interface
Standalone UFP/DFP Mode
UPD360-A
UPD360-B
UPD360-C
X
X
X
X
X
DS00002084C-page 8
2016-2017 Microchip Technology Inc.
UPD360
3.0
3.1
BALL DESCRIPTIONS AND CONFIGURATION
Ball Assignments
The ball assignments for the UPD360-A/UPD360-B are detailed in Section 3.1.1, "UPD360-A/UPD360-B Ball Assign-
ments," on page 9. The ball assignments for the UPD360-C are detailed in Section 3.1.1, "UPD360-A/UPD360-B Ball
Assignments," on page 9. For information on the differences between the UPD360 family of devices, refer to Section
2.2, "UPD360 Family Differences Summary," on page 8.
3.1.1
UPD360-A/UPD360-B BALL ASSIGNMENTS
The device ball diagram for the UPD360-A/UPD360-B can be seen in Figure 3-1. Table 3-1 provides a UPD360-A/
UPD360-B ball assignment table. Ball descriptions are provided in Section 3.2, "Ball Descriptions".
FIGURE 3-1:
UPD360-A/UPD360-B BALL ASSIGNMENTS (TOP VIEW)
1
2
3
4
5
6
7
VBUS
VS
VS
NC
GPIO13*
GPIO 14*
GPIO15*
A
B
C
D
GPIO11*/
DISCHARGE
VBUS
CC2
CC1
VBUS_DET
CC2_DB_EN
CC1_DB_EN
OCS_COMP1
PWR_DN
GPIO9*
GPO10*
VDD33IO
GPIO5
GPIO7
GPIO4
GPO1
GPIO12*
VSS
GPIO 8
VSS
VSS
RESET_N
CFG_SEL 0
3V3_ALW
VSW
VSS
GPIO 6
E
F
VDD33IO
IRQ_N
CFG_SEL 1
GPIO3/HPD
GPIO 2/
OCS_COMP2
3V3_VBUS
VDD18_CAP
I2C_DAT
I2C_CLK
GPIO0
G
Top of UPD360-A/UPD360-B 44-WFBGA Package
*The GPIO[9:15] balls provide alternate functions when in Standalone DFP or Standalone UFP mo.des
2016-2017 Microchip Technology Inc.
DS00002084C-page 9
UPD360
TABLE 3-1:
Ball
UPD360-A/UPD360-B BALL ASSIGNMENTS
Pin Name
Ball
Pin Name
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C4
C6
C7
D1
D2
D3
VBUS
D5
D6
D7
E1
E2
E4
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
VSS
GPIO7
VS
VS
RESET_N
CFG_SEL0
OCS_COMP1
VSS
NC
GPIO13 (Note 3-1)
GPIO14 (Note 3-1)
GPIO15 (Note 3-1)
VBUS
GPIO4
GPIO6
VBUS_DET
GPIO9 (Note 3-1)
GPO10 (Note 3-1) (Note 3-2)
GPIO11/DISCHARGE (Note 3-1)
VDD33IO
3V3_ALW
PWR_DN
VDD33IO
IRQ_N
CFG_SEL1
GPO1 (Note 3-2)
GPIO3/HPD
VSW
GPIO12 (Note 3-1)
CC2
CC2_DB_EN
VSS
3V3_VBUS
VDD18_CAP
I2C_DAT
I2C_CLK
GPIO0
GPIO5
GPIO8
CC1
CC1_DB_EN
VSS
GPIO2/OCS_COMP2
Note 3-1
This ball provides alternate functions when in Standalone DFP and Standalone UFP Modes. Refer to
Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP Modes" for
additional information.
Note 3-2
This general purpose signal can only function as an output and must not be pulled-up
externally during RESET_N assertion.
DS00002084C-page 10
2016-2017 Microchip Technology Inc.
UPD360
3.1.1.1
UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP Modes
When the UPD360-A/UPD360-B is configured in Standalone DFP or Standalone UFP modes, the following GPIO balls
are assigned specific alternate functions, as detailed in Table 3-2.
TABLE 3-2:
Ball
ALTERNATE GPIO[9:15] FUNCTIONS IN STANDALONE DFP/UFP MODES
I2C Companion Mode
Standalone DFP Mode
Standalone UFP Mode
B3
B4
B5
B7
A5
A6
A7
GPIO9
GPO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
ORIENTATION
ATTACH
ORIENTATION
ATTACH
OCS_N
GPIO11
PWR_EN
SINK_5V_LEGACY_N
SINK_5V_1A5_N
SINK_5V_3A0_N
GPIO15
PWR_CAP0
PWR_CAP1
ERR_RECOVER
2016-2017 Microchip Technology Inc.
DS00002084C-page 11
UPD360
3.1.2
UPD360-C BALL ASSIGNMENTS
The device ball diagram for the UPD360-C can be seen in Figure 3-2. Table 3-3 provides a UPD360-C ball assignment
table. Ball descriptions are provided in Section 3.2, "Ball Descriptions".
FIGURE 3-2:
UPD360-C BALL ASSIGNMENTS (TOP VIEW)
1
2
3
4
5
6
7
VBUS
VS
VS
NC
GPIO 13
GPIO14
GPIO 15
A
B
C
D
GPIO11/
DISCHARGE
VBUS
CC2
CC1
VBUS_DET
CC2_DB_EN
CC1_DB_EN
OCS_COMP1
PWR_DN
GPIO 9
GPO10
VDD33IO
GPIO5
GPIO7
GPIO4
GPO1
GPIO 12
VSS
GPIO8
VSS
VSS
RESET _N
CFG_SEL0
3V3_ALW
VSW
VSS
GPIO6
E
F
VDD 33IO
IRQ_N
SPI_CLK
GPIO3/HPD
GPIO 2/
OCS_COMP2
3V3_VBUS
VDD18_CAP
SPI _DO
SPI_DI
SPI_CS
G
Top of UPD360-C 44-WFBGA Package
DS00002084C-page 12
2016-2017 Microchip Technology Inc.
UPD360
TABLE 3-3:
Ball
UPD360-C BALL ASSIGNMENTS
Pin Name
Ball
Pin Name
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C4
C6
C7
D1
D2
D3
VBUS
VS
D5
D6
D7
E1
E2
E4
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
VSS
GPIO7
VS
RESET_N
CFG_SEL0
OCS_COMP1
VSS
NC
GPIO13
GPIO14
GPIO15
VBUS
GPIO4
GPIO6
VBUS_DET
GPIO9
3V3_ALW
PWR_DN
VDD33IO
IRQ_N
GPO10 (Note 3-3)
GPIO11/DISCHARGE
VDD33IO
GPIO12
CC2
SPI_CLK
GPO1 (Note 3-3)
GPIO3/HPD
VSW
CC2_DB_EN
VSS
3V3_VBUS
VDD18_CAP
SPI_DO
GPIO5
GPIO8
CC1
SPI_DI
CC1_DB_EN
VSS
SPI_CS
GPIO2/OCS_COMP2
Note 3-3
This general purpose signal can only function as an output and must not be pulled-up
externally during RESET_N assertion.
2016-2017 Microchip Technology Inc.
DS00002084C-page 13
UPD360
3.2
Ball Descriptions
This sections details the functions of the various device signals.
TABLE 3-4:
NAME
BALL DESCRIPTIONS
SYMBOL
BUFFER
TYPE
DESCRIPTION
USB Type-C™
Configuration
Channel 1
CC1
CC2
AIO
AIO
AIO
Configuration Channel (CC) used in the discovery, configu-
ration and management of connections across a USB
Type-C cable. Refer to Section 9.1, "CC Comparator," on
page 68 for additional information.
Configuration
Channel 2
Configuration Channel (CC) used in the discovery, configu-
ration and management of connections across a USB
Type-C cable. Refer to Section 9.1, "CC Comparator," on
page 68 for additional information.
CC1
Dead Battery
Enable
CC1_DB_EN
Determines whether CC1 broadcasts Rd pull-down
or Hi-Z. Refer to Section 9.6, "Dead Battery," on page 77 for
additional information.
Note:
Tie to CC1 if dead battery is supported. Other-
wise, tie to ground.
CC2
Dead Battery
Enable
CC2_DB_EN
AIO
Determines whether CC2 broadcasts Rd pull-down
or Hi-Z. Refer to Section 9.6, "Dead Battery," on page 77 for
additional information.
Note:
Tie to CC2 if dead battery is supported. Other-
wise, tie to ground.
I2C Interface (UPD360-A/UPD360-B Only)
I2C Clock
I2C Data
I2C_CLK
I2C_DAT
I2C
I2C clock signal
(+1.8V for UPD360-A, +3.3V for UPD360-B)
I2C data signal
I2C
(+1.8V for UPD360-A, +3.3V for UPD360-B)
SPI Interface Pins (UPD360-C Only)
SPI Clock
SPI_CLK
IS
SPI clock.
The maximum supported SPI clock frequency is 25 MHz.
SPI Data Out
SPI Data In
SPI_DO
SPI_DI
SPI_CS
O8
IS
SPI output data.
SPI input data.
SPI Chip
Enable
IS
Active low SPI chip enable input.
Power Delivery Control
Hot Plug Detect
Discharge
HPD
IS/O8
DisplayPort Hot Plug Detection. Refer to Section 14.0, "Dis-
playPort Hot Plug Detect (HPD)," on page 195 for addi-
tional information.
DISCHARGE
O8
VBUS Discharge. Enables external VBUS discharge circuit
when commanded by USB PD software.
DS00002084C-page 14
2016-2017 Microchip Technology Inc.
UPD360
TABLE 3-4:
NAME
BALL DESCRIPTIONS (CONTINUED)
BUFFER
SYMBOL
TYPE
DESCRIPTION
Type-C
Attach
ATTACH
O8
In the Standalone UFP and Standalone DFP modes
(UPD360-A/UPD360-B only), this signal indicates that the
USB Type-C receptacles at the near and far end of the
cable both have a plug-in. This pin is autonomously driven
by the device in DFP standalone mode.
0b: Nothing attached
1b: USB Type-C port has an end-end attached
Refer to Section 9.10, "Standalone DFP (UPD360-A/
UPD360-B Only)" and Section 9.11, "Standalone UFP
(UPD360-A/UPD360-B Only)"for additional information.
Note:
Note:
Float this signal when unused.
This signal is not available in the UPD360-C.
Type-C
Orientation
ORIENTATION
O8
In the Standalone UFP and Standalone DFP modes
(UPD360-A/UPD360-B only), this signal is used to indicate
which CC pin is terminated by the attached DFP/UFP and
is autonomously driven by the device in DFP standalone
mode.
DFP:
0b: CC1 pin is terminated by Rd.
1b: CC2 pin is terminated by Rd.
UFP:
0b: CC1 pin is pulled to a higher voltage than CC2.
1b: CC2 pin is pulled to a higher voltage than CC1.
Refer to Section 9.10, "Standalone DFP (UPD360-A/
UPD360-B Only)" and Section 9.11, "Standalone UFP
(UPD360-A/UPD360-B Only)"for additional information.
Note:
Note:
Float this signal when unused.
This signal is not available in the UPD360-C.
Over-current
sense
OCS_N
OD8
In the Standalone DFP mode (UPD360-A/UPD360-B only),
this active-low signal indicates over-current sense. This sig-
nal maps to the PPC_INT interrupt.
Note:
This signal is active-low. Float this signal when
unused.
Note:
This signal is not available in the UPD360-C.
VBUS Power
Enable
PWR_EN
IS
In the Standalone DFP mode (UPD360-A/UPD360-B only),
this signal is used as a port power switch enable for USB
hubs.
Note:
This signal should be tied to the Power Good
signal from the VS supply.
Note:
Note:
Tie this signal to ground when unused.
This signal is not available in the UPD360-C.
2016-2017 Microchip Technology Inc.
DS00002084C-page 15
UPD360
TABLE 3-4:
BALL DESCRIPTIONS (CONTINUED)
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
Power
Capability 0
PWR_CAP0
IS
In the Standalone DFP mode, these signals define the
charging current supported by the device.
Power
Capability 1
PWR_CAP1
IS
00b: USB 2.0 Default Current
01b: USB 3.0 Default Current
10b: 1.5 A
11b: 3.0 A
Note:
Note:
It is not valid to change the state of PWR_CAP0
and PWR_CAP1 pins after reset is de-asserted.
These signals are not available in the UPD360-
C.
Error
Recovery
ERR_RECOVER
IS
In Standalone DFP mode (UPD360-A/UPD360-B only), this
pin determines whether or not the USB Type-C logic shall
attempt to auto-recover from an OCS or other error.
Sources from either the Port Power Switch or VCONN FET.
Note:
This signal is not available in the UPD360-C.
Sink Legacy
Current
SINK_5V_LEGACY_N
OD8
In the Standalone UFP mode (UPD360-A/UPD360-B only),
this pin asserts autonomously when a source has been
detected that provides legacy USB current.
Note:
Note:
Float this signal when unused.
This signal is not available in the UPD360-C.
Sink 1.5A
Current
SINK_5V_1A5_N
SINK_5V_3A0_N
OD8
OD8
In the Standalone UFP mode (UPD360-A/UPD360-B only),
this pin asserts autonomously when a source has been
detected that provides 1.5A USB current.
Note:
Note:
Float this signal when unused.
This signal is not available in the UPD360-C.
Sink 3A
Current
In the Standalone UFP mode (UPD360-A/UPD360-B only),
this pin asserts autonomously when a source has been
detected that provides 3.0A USB current.
Note:
Note:
Float this signal when unused.
This signal is not available in the UPD360-C.
Miscellaneous
OD8 Active low interrupt signal.
Note: Float this signal when unused.
Interrupt
IRQ_N
VBUS
Detection
VBUS_DET
CFG_SEL0
AIO
Scaled down version of VBUS. Tie this signal to VBUS via a
resistor divider.
Configuration
Select 0
AIO
This multi-level configuration signal is sampled after a sys-
tem reset to select the device’s default mode of operation
based on the connected 1% precision resistor value.
Refer to Section 9.8.1, "Configuration Selection," on
page 81 for additional information.
DS00002084C-page 16
2016-2017 Microchip Technology Inc.
UPD360
TABLE 3-4:
NAME
BALL DESCRIPTIONS (CONTINUED)
BUFFER
SYMBOL
TYPE
DESCRIPTION
Configuration
Select 1
CFG_SEL1
AIO
This multi-level configuration signal is sampled after a sys-
tem reset to select the device’s default I2C slave address
based on the connected 1% precision resistor value
(UPD360-A/UPD360-B only).
Refer to Section 9.8.1, "Configuration Selection," on
page 81 for additional information.
Note:
This signal is not available in the UPD360-C.
General
Purpose I/O
0-15
GPIO0,
GPO1,
IS/O8/
OD8
(PU)
The general purpose I/O signals are fully programmable as
either a push-pull output, an open-drain output, or a
Schmitt-triggered input (except GPO1 and GPO10). A pro-
grammable pull-up may optionally be enabled.
GPIO2,
GPIO3,
GPIO4,
GPIO5,
GPIO6,
GPIO7,
GPIO8,
GPIO9,
GPO10
Note:
The GPO1 and GPO10 general purpose sig-
nals can only function as outputs and must
be kept in a low state coincident with de-
asserting RESET_N.
Note:
Note:
Tie these signals to ground when unused.
External pull-ups and pull-downs shall be placed
on GPIO pins to ensure that when in the reset
state the inputs to external devices are driven to
a valid state.
Note:
Note:
GPIO0 is not available in the UPD360-C.
In Standalone DFP/UFP modes (UPD360-A/
UPD360-B only), GPIOs 9-15 have alternate
dedicated functions, as defined in Section
3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15]
Functions in Standalone DFP/UFP Modes," on
page 11.
Refer to Section 8.2, "General Purpose I/O," on page 37 for
additional information.
System Reset
Power Down
RESET_N
PWR_DN
IS
AI
AI
Active low system reset.
Note:
If this signal is unused, it must be pulled up to
VDD33IO.
Refer to Section 7.7, "Reset Operation," on page 34 for
additional information.
When asserted, this signal places the device into the
SLEEP state.
Note:
Tie this signal to ground when unused.
Refer to Section 7.2.1, "SLEEP," on page 31 for additional
information.
Over-Current
Sense
OCS_COMP1
This pin is used by the integrated OCS comparator to
detect for error conditions.
Comparator 1
Note:
Tie this signal to ground when unused.
Refer to Section 8.3, "External Over-current Detection," on
page 39 for additional information.
2016-2017 Microchip Technology Inc.
DS00002084C-page 17
UPD360
TABLE 3-4:
BALL DESCRIPTIONS (CONTINUED)
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
Over-Current
Sense
OCS_COMP2
AI
This pin is used by the integrated OCS comparator to
detect for error conditions.
Comparator 2
Note:
Tie this signal to ground when unused.
Refer to Section 8.3, "External Over-current Detection," on
page 39 for additional information.
No Connect
NC
-
For proper operation, this pin must be left unconnected.
Power/Ground
+3.3V
Voltage
Switch
Supply
VSW
P
+3.3V power supply output from the integrated power
switch.
Note:
This pin also provides capacitance for integrated
power switch and must be connected to a 1 uF
(<100 Mohm ESR) capacitor to ground.
+3.3V
VBUS Supply
3V3_VBUS
3V3_ALW
P
P
+3.3V power supply input derived from VBUS to the inte-
grated power switch.
Note:
This pin must be connect to a 2.2 uF capacitor
to ground.
+3.3V
Always Supply
+3.3V main power supply input to the integrated power
switch.
Note:
This pin must be connect to a 2.2 uF capacitor
to ground.
+3.3V I/O
Power Supply
Input
VDD33IO
P
P
+3.3V I/O power supply input.
+1.8V Digital
Core Power
Supply Capaci-
tor
VDD18_CAP
+1.8V digital core power supply capacitor. This signal must
be connected to a 1uF capacitor to ground for proper oper-
ation.
VBUS
Port Power
Switch Output
VBUS
VS
P
Port power switch output.
Note:
Both VBUS signals must be tied together.
+5V
+5V input to port power switch.
Port Power
Switch Input
Note:
Note:
Both VS signals must be tied together.
A 1uF capacitor to ground is required on this sig-
nal for a single port configuration. If more than
one port is used, an additional 1uF of capaci-
tance must be added for each additional port.
P
P
Ground
VSS
Ground pins.
DS00002084C-page 18
2016-2017 Microchip Technology Inc.
UPD360
4.0
REGISTER MAP
This chapter provides the device register map, summarizing the various directly addressable System Control and Status
Registers (CSRs). All CSRs are directly accessible via the device’s internal I2C Slave Controller (UPD360-A/UPD360-
B Only) or SPI Slave Controller (UPD360-C Only). Detailed descriptions of the System CSRs are provided in the chap-
ters corresponding to their function. Table 4-1 provides a summary of all directly addressable CSRs and their corre-
sponding addresses.
Note:
Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 6.
TABLE 4-1:
Address
DEVICE REGISTER MAP
Registers
3400h-FFFFh
3000h-33FFh
2C00h-2FFFh
2800h-2BFFh
2000h-27FFh
1C00h-1FFFh
1800h-1BFFh
1400h-17FFh
1000h-13FFh
0C00h-0FFFh
0800h-0BFFh
0400h-07FFh
0000h-03FFh
RESERVED
Watchdog Timer Registers
RESERVED
Baseband CC Interface Registers
RESERVED
Power Switch Registers
Power Delivery MAC Registers
RESERVED
Clocks and Power Management Registers
DisplayPort HPD Registers
Cable Orientation and Detection Registers
Port Power Controller Registers
System Control Registers
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
2016-2017 Microchip Technology Inc.
DS00002084C-page 19
UPD360
2
5.0
I C SLAVE CONTROLLER (UPD360-A/UPD360-B ONLY)
This chapter details the integrated I2C slave controller (I2C_DAT and I2C_CLK) available in the UPD360-A (+1.8V sig-
naling) and UPD360-B (+3.3V signaling). The I2C slave controller can be used for Host CPU serial management and
data transfer, and allows host access to all device Configuration and Status Registers (Section 4.0, "Register Map," on
page 19).
5.1
I2C Overview
I2C is a bi-directional 2-wire data protocol. A device that is currently sending data is defined as the “transmitter” and a
device that is currently receiving data is defined as the “receiver”. The bus is controlled by a master which generates
the SCL clock, controls bus access, and generates the start and stop conditions. The master and slave will operate as
transmitter or receiver, bit-by-bit, as determined by the master. Since the device I2C controller is a slave only, the terms
“host” and “master” are synonymous, both referring to the external side of the interface.
Both the clock (SCL) and data (SDA) signals have analog input filters that reject pulses that are less than 50 ns. The
data pin is driven low when either interface sends a low, emulating the wired-AND function of the I2C bus. Since the
slave interface never drives the clock pin, the wired-AND is not necessary.
The following bus states exist:
• Idle: Both I2C_DAT and I2C_CLK are high when the bus is idle.
• Start & Stop Conditions: A start condition (S) is defined as a high to low transition on the SDA line while SCL is
high. A stop condition (P) is defined as a low to high transition on the SDA line while SCL is high. The bus is con-
sidered to be busy following a start condition and is considered free 4.7 µs / 1.3 µs / 0.5µs (for 100 kHz / 400 kHz
/ 1MHz operation, respectively) following a stop condition. The bus stays busy following a repeated start condition
(Sr) in the absence of a stop condition. Stop/start sequences and repeated starts are otherwise functionally equiv-
alent.
• Data Valid: Data is valid, following the start condition, when SDA is stable while SCL is high. Data can only be
changed while the clock is low. There is one valid bit per clock pulse. Every byte must be 8 bits long and is trans-
mitted MSB first.
• Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth clock pulse for
this bit, and the transmitter releases SDA (high). To provide a positive “acknowledge” (ACK), the receiver drives
SDA low so that it remains valid during the high period of the clock, taking into account the setup and hold times.
To provide a negative “no-acknowledge” (NACK or ACK), the receiver will allow the line to remain high during this
bit time. The receiver may be the master or the slave depending on the direction of the data. Typically the receiver
acknowledges each byte. If the master is the receiver, it does not generate an acknowledge on the last byte of a
transfer. This informs the slave to not drive the next byte of data, freeing SDA so that the master may generate a
stop or repeated start condition.
Figure 5-1 displays the various bus states of a typical I2C cycle.
2
FIGURE 5-1:
I C CYCLES
data
can
data
can
data
can
data
can
data
data
stable
stable
change
change
change
change
I2C_DAT
S
Sr
P
I2C_CLK
Data Valid
or Ack
Data Valid
or Ack
Stop Condition
Re-Start
Condition
Start Condition
DS00002084C-page 20
2016-2017 Microchip Technology Inc.
UPD360
5.2
I2C Slave Operation
The I2C slave serial interface consists of a data wire (I2C_DAT) and a serial clock (I2C_CLK). The serial clock is driven
by the master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up resistors.
The I2C slave controller implements the low level I2C slave serial interface (start and stop condition detection, data bit
transmission/reception and acknowledge generation/reception), handles the slave command protocol and performs
system register reads and writes. It tolerates and also provides clock stretching, in particular for supporting a transparent
Wake on Host Access (see Section 7.3, "Asynchronous I2C Wakeup (UPD360-A/UPD360-B Only)," on page 32).
The I2C slave controller conforms to the NXP I2C-Bus Specification (UM10204, April 4, 2014), and supports traffic as
defined therein for the following modes:
• Standard-mode (Sm, 100 kbit/s)
• Fast-mode (Fm, 400 kbit/s)
• Fast-mode Plus (Fm+, 1 Mbit/s)
Refer to Section 16.6.2, "I2C Slave Interface (UPD360-A/UPD360-B only)," on page 210 for timing information.
2
5.2.1
I C SLAVE COMMAND FORMAT
The I2C slave serial interface supports single register and multiple register Read and Write commands. A Read or Write
command is started by the master first sending a Start condition, followed by a Control byte. The Control byte consists
of a 7-bit slave address and a 1-bit Read/Write indication (R/~W). The default slave address used by the device is
selected via the CFG_SEL1 configuration strap. Assuming the slave address in the Control byte matches this address,
the Control byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the next Start condition.
The I2C slave controller also supports the General Call Address. The I2C command formats can be seen in Figure 5-2,
Figure 5-4, and Figure 5-5.
If the read/write indication (R/~W) in the Control byte is a 0 (Write), the next two bytes sent by the master are a register
address, and these two bytes are mandatory. The upper (first) two bits of the address field are a Direction control (DIR),
which indicates whether multi-byte accesses will increment, decrement, or fix (as static) the issued address
(Section 5.2.2). After the address bytes are acknowledged by the device, the master may send data bytes, which will
be written to successive registers starting at this address. It may instead send another Start condition (to start the read-
ing of data) or a Stop condition (only setting the address). The latter two will terminate the current Write before writing
any data, but will have the effect of setting the internal register address which will be used for subsequent Reads.
If the read/write indication (R/~W) in the Control byte is a 1 (Read), the device will start sending data following the Con-
trol byte acknowledge bit. Read commands cannot designate an address by themselves, but may optionally be prefixed
with a Write command to set it (see Figure 5-4, prefixes in gray). If however the Read immediately follows a Multiple
Register Write or Read, the address may have been incremented or decremented internally according to its DIR field,
so this Read will start its access at the next successive byte address. Also, regardless of the previous access, a multiple-
byte Read will continue the Increment/Decrement internally, as determined by the previously-issued DIR field
(Section 5.2.2).
The length of the register address field is always two full bytes. Some high-order bits are don’t-care. Don’t-care register
address bits should be sent as ‘0’ always, for upward compatibility.
2
FIGURE 5-2:
I C SLAVE ADDRESSING
Control Byte
Address Byte 1
Address Byte 0
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
A
A
A
A
9
A
8
S
0
*
DIR
15 14
13 12 11 10
Inc /
Dec /
Static
Start or
Stop or
Data [7]
R/~W
2016-2017 Microchip Technology Inc.
DS00002084C-page 21
UPD360
Note:
Within bytes (address and data), the bits are transferred most-significant bit first. Addresses are transferred
Most-Significant Byte first. All registers are accessed in units of bytes, and register data is transferred in
increasing byte address order. Refer to the device register layout to determine the effect of this on the sig-
nificance order of any multi-byte value.
5.2.2
MULTIPLE-BYTE REGISTER ADDRESS SEQUENCING
The DIR subfield in Address field bits [15:14] determines how multiple-byte sequences will be interpreted. This field is
held internally whenever issued with an address, but is not applied in I2C except in multiple-byte transfers, Read or
Write. The DIR field definitions are as follows:
• DIR = 00b: Selects auto-incrementing of the internally-held register address for subsequent byte accesses in a
multiple-byte packet.
• DIR = 10b: Selects auto-decrementing of the internally-held register address for subsequent byte accesses in a
multiple-byte packet.
• DIR = 11b: Select a fixed address. No modification of the internal register address will occur, meaning that all sub-
sequent accesses, single- or multiple-byte, are made to the same register.
• DIR = 01b: Reserved for future use.
Note that the DIR field is altered only by issuing an address. It remains, affecting any subsequent multiple-byte Read
packets, until altered.
5.2.3
GENERAL CALL ADDRESS
The device supports the I2C General Call Address. The intent of this feature is to enable global I2C writes to topologies
that have multiple UPD360 slaves. This minimizes the I2C transactions for device reset, via the Hardware Control Reg-
ister (HW_CTL), as well as for various common configuration registers. This mode of operation is intended for topologies
that consist solely of UPD360 slaves. This mode of operation may not be compatible with non-UPD360 slaves coexisting
on the I2C bus.
Only the case where the least significant bit, “B”, of the General Call address is set to one is supported. The device will
ignore the case when the least significant bit, “B”, of the General Call address is set to zero. For the latter case, the
device will ACK the first byte, General call address. The device will ignore and silently discard all subsequent bytes and
not acknowledge them. The second byte of the General Call address is also ignored and not acknowledged by the
device.
Figure 5-3 illustrates the supported General Call Address format.
2
FIGURE 5-3:
I C GENERAL CALL ADDRESS
General Call
Address
Second Byte
Address Byte 1
Address Byte 0
A
C
K
A
C
K
A
C
K
A
C
K
A
A
A
A
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
0
0
0
0
0
0
0
1
*
0
Master Address
DIR
13 12 11 10
15 14
(B)
Inc /
Dec /
Static
Start or
Stop or
Data
5.2.4
DEVICE INITIALIZATION
Until the device has initialized itself to the point where the various configuration inputs are valid, the I2C slave interface
will not respond to or be affected by any external pin activity. The device should not be accessed by the master in this
state. If, however, it is necessary to do so, this state will appear externally as a NACK (high) in the ACK bit time of the
Control Byte, and of any further bytes transmitted by the master. The device will continue to act in this manner until the
first Start condition is received after it is initialized internally. A Read transaction should not be attempted until an
Address Write has been completed successfully (Figure 5-2), since the value(s) read may be unpredictable otherwise.
Alternatively, an IRQ_N pin assertion can be used to indicate the device is ready.
DS00002084C-page 22
2016-2017 Microchip Technology Inc.
UPD360
5.2.5
ACCESS DURING AND FOLLOWING POWER MANAGEMENT
During low-power modes, a Start condition will trigger the device to wake, and the device will also stretch the I2C clock
low until its internal clocks are running and locked. It will then release the I2C clock, and process the incoming packet.
It performs these steps before receiving the Slave Address bits, meaning that if there are multiple devices of this type
asleep on the same I2C bus segment then they will all stretch the clock, and they will all wake, regardless of whether
they were actually addressed. In the event that the slave address of the I2C transaction does not match the value spec-
ified in the I2C Slave Address Register (I2C_ADDR) (UPD360-A/UPD360-B Only), the device will power-down automat-
ically.
2
5.2.6
I C SLAVE READ SEQUENCE
Following the device addressing, as detailed in Section 5.2.1, a register is read from the device when the master sends
a Start condition and Control byte with the R/~W bit set to ‘1’. Assuming the slave address in the Control byte matches
the device address, the Control byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the
next Start condition. Following the acknowledge, the device sends 1 or more bytes of data, from successive register
addresses according to the last-issued DIR address subfield (Section 5.2.2), until the master sends a no-acknowledge
followed by the Stop condition. The no-acknowledge informs the device not to send any further bytes.
The internal register address is unchanged if only a single register byte is read, otherwise (a Multiple Register Read)
the internal register address may be incremented or decremented (Section 5.2.2) after each byte including the final one.
If the internal address reaches its maximum, it rolls over to 0.
If the master sends an unexpected start or stop condition, the device will stop sending immediately and will respond to
the next sequence as needed.
Figure 5-4 illustrates a typical single and multiple register read. An optional Write of an address is allowed to occur first,
shown in gray. Note that this example shows an abbreviated case, where the Write does not have a Stop condition
before the Read transfer’s Starts. in this case, the Stop is still allowed, but not required.
2
FIGURE 5-4:
I C SLAVE READS
Control Byte
Data Byte
Control Byte
Address Byte 1
Address Byte 0
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
A
A
A
A
9
A
8
S
0
DIR
15 14
S
1
P
13 12 11 10
Inc /
Dec /
Static
R/~W
Single Register Read
Data Bytes
2 — (n-1)
Data Byte n
Control Byte
Data Byte 1
Control Byte
Address Byte 1
Address Byte 0
A
C
K
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
D
1
D
0
D
1
D
0
D
7
D
6
A
A
A
A
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
...
...
...
P
S
0
S
1
DIR
15 14
13 12 11 10
Inc /
Dec /
Static
R/~W
Multiple Register Reads
2
5.2.7
I C SLAVE WRITE SEQUENCE
Following the device addressing, as detailed in Section 5.2.1, a register value is written to the device when the master
continues to send data bytes. Each byte is acknowledged by the device. Following any data byte, after the acknowledge,
the master may either send another start condition or halt the sequence with a stop condition. The internal register
address is unchanged following a single-byte write.
Multiple writes are performed when the master sends additional data bytes following the first. The internal address is
automatically incremented and the next register is written. Once the internal address reaches its maximum value, it rolls
over to 0. The multiple write is concluded when the master sends another start or stop condition. In performing a multiple
write, the internal register address may be incremented or decremented (Section 5.2.2) for each write including the final.
2016-2017 Microchip Technology Inc.
DS00002084C-page 23
UPD360
This is not relevant for subsequent writes after a new Start condition, since a new register address (with its DIR subfield)
must then be included. However, this would affect the address used by any subsequent read without first resetting the
register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the device will stop imme-
diately and will respond to the next sequence as needed.
The data write to a multi-byte register may be delayed until after all bits are input. In the event that the full register is not
written (master sends a start or a stop condition occurs unexpectedly), the write may be considered invalid and the reg-
ister not affected. Multiple registers may be written in a multiple write cycle, each one being written in sequence. I2C
writes must not be performed to unused register addresses.
Figure 5-5 illustrates a typical single and multiple register write.
2
FIGURE 5-5:
I C SLAVE WRITES
Data Byte
Address Byte 0
Control Byte
Address Byte 1
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
A
C
K
A
A
A
A
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
P
S
0
DIR
15 14
13 12 11 10
Inc /
Dec /
Static
R/~W
Single Register Write
Data Bytes
2 — (n-1)
Data Byte 1
Data Byte n
Control Byte
Address Byte 1
Address Byte 0
A
C
K
A
C
K
A
C
K
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
A
C
K
A
C
K
A
C
K
D
1
D
0
D
7
D
6
D
1
D
0
A
A
A
A
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
...
...
...
P
S
0
DIR
15 14
13 12 11 10
Inc /
Dec /
Static
R/~W
Multiple Register Writes
5.2.8
SPECIAL CSR HANDLING
Live Bits
5.2.8.1
Register values are latched (registered) at the beginning of each register read to prevent the host from reading a chang-
ing value. The latching occurs individually per register in a multiple register read sequence.
5.2.8.2
Change-on-Read Registers and FIFOs
Any single-byte register that triggers a side-effect from a read operation (for example, containing “clear on read” bits, or
advancing a FIFO structure) triggers only after the host has begun accessing the value. The value seen by the master
will always be the original value and never the updated result of the side-effect.
For a multiple-byte register that is considered a single unit, the change may be delayed until all bytes of the register
have been read. In the event that the host sends a no-acknowledge on one of the first bytes of a multi-byte register, or
a start or stop condition occurs unexpectedly before the acknowledge of the full register, the read may be considered
invalid and the side-effect not triggered.
Registers read in multiple-register read access will trigger multiple side-effects, occurring as they are read. The following
registers have read side-effects:
• Watchdog Count Register (WDT_COUNT)
DS00002084C-page 24
2016-2017 Microchip Technology Inc.
UPD360
5.2.8.3
Live Bits that are also Change-on-Read
As described above, the current value from a register with live bits (as is the case of any register) is captured and latched
as output data, and Change on Read bits are then changed in the original register. To prevent loss of a hardware event
that occurs following the data capture but before the Change on Read, these hardware events are held pending until
after the read action and after any change due to the read. This sequence also ensures an edge in the bit due to the
hardware event.
2016-2017 Microchip Technology Inc.
DS00002084C-page 25
UPD360
6.0
SPI SLAVE CONTROLLER (UPD360-C ONLY)
This chapter details the integrated SPI slave controller (SPI_DI, SPI_DO, SPI_CLK, and SPI_CS) available in the
UPD360-C. The SPI slave controller can be used for Host CPU serial management and data transfer, and allows host
access to all device Configuration and Status Registers (Section 4.0, "Register Map," on page 19).
6.1
SPI Overview
The SPI Slave module provides a low pin count synchronous slave interface that facilitates communication between the
device and a host system. The SPI slave allows access to the System CSRs and internal FIFOs and memories. It sup-
ports single and multiple register read and write commands with incrementing, decrementing and static addressing.
Only a Single bit lane is supported in SPI mode at up to 25 MHz.
The following is an overview of the functions provided by the SPI Slave:
• Fast Read: 4-wire (clock, select, data in and data out) reads. Serial command, address and data. This is called
“Fast” Read for historical reasons, and is the only Read command supported. There is a single Dummy byte
required for first access. Single and multiple register reads with incrementing, decrementing or static addressing.
• Write: 4-wire (clock, select, data in and data out) writes at up to 25 MHz. Serial command, address and data. Sin-
gle and multiple register writes with incrementing, decrementing or static addressing.
6.2
SPI Slave Operation
A SPI frame starts on the falling edge of SPI_CS, and ends with SPI_CS rising. At the edges of SPI_CS, the SPI_CLK
clock may be at its reset state of either low (Mode 0) or high (Mode 3), at the option of the Master.
Input data on the SPI_DI pin (often called “MOSI”) is sampled on the rising edge of the SPI_CLK input clock. Output
data is launched on the SPI_DO pin (often called “MISO”) with the falling edge of the clock. While the SPI_CS chip select
input is high, the SPI_DI and SPI_CLK inputs are ignored and the SPI_DO output is floating.
Each frame starts with an 8-bit instruction byte, transmitted by the Master, and it is accepted on SPI_DI starting at the
first rising edge of the input clock after SPI_CS goes active.
For both Write and (Fast) Read instructions, two address bytes follow the instruction byte. The address field expresses
a byte address. Fourteen address bits specify the address. The remaining two bits [15:14] constitute the DIR subfield
of the address field, which specifies whether the address is Auto-Incremented (00b) or Auto-Decremented (10b) for con-
secutive data bytes in the frame. A special Static address coding (11b) keeps the address static throughout the frame
of data, causing a single byte address to be accessed repeatedly if multiple bytes are transferred in the frame. DIR sub-
field encoding 01b is reserved and should be decoded in implementation to be the same as 00b, for the sake of mini-
mizing the effect of a software error that increments beyond the address space.
For the Fast Read instruction, one dummy byte follows the address bytes. The dummy byte occupies 8 bits, one per
clock.
The device will normally not drive SPI_DO during the Instruction, Address or Dummy byte cycles, but see Section 6.2.2,
"Access During and Following Power Management," on page 27 for a special case.
For Fast Read instructions, one or more 8-bit data fields follow the dummy byte. For Write instructions, they immediately
follow the address bytes.
Individual bytes in instruction, address and data fields are transferred with the most-significant bit (msb) first. The two-
byte Address field is transferred with the most-significant byte (MSB) first. Multi-byte data values are transferred in the
order specified by the DIR subfield of the Address field (bits [15:14]), and so their order can be effectively selected by
using Increment mode (starting from the lowest byte address) or Decrement mode (starting from the highest byte
address).
The SPI interface supports a minimum time of 50ns between successive commands (a minimum SPI_CS inactive time
of 50ns).
DS00002084C-page 26
2016-2017 Microchip Technology Inc.
UPD360
The instructions supported by the SPI slave controller are listed in Table 6-1. Unsupported instructions are reserved and
must not be used.
TABLE 6-1:
Instruction
SPI INSTRUCTIONS
Description
Bus Bit
Width
Address
Bytes
Dummy
Bytes
Inst. Code
Data bytes Max Freq.
Read
FASTREAD
Read, higher
speed format
1
1
0Bh
2
2
1
0
1 to
1 to
25 MHz
25 MHz
Write
WRITE
Write
02h
6.2.1
DEVICE INITIALIZATION
Until the device has been initialized to the point where the various configuration inputs are valid, the SPI interface will
not respond to or be affected by any external pin activity.
Once device initialization completes, the SPI interface will ignore the pins until a rising edge of SPI_CS is detected.
If the device initialization completes during an active cycle (SPI_CS low), the trailing end of the frame must be seen
(SPI_CS returning high) before any internal registers are affected or the state of the SPI interface changes.
The first SPI access after device initialization must always be a dummy read to the SPI Test Register (SPI_TEST)
(UPD360-C Only).
6.2.1.1
SPI Slave Read Polling for Initialization Complete
With an external weak pull-up resistor present on SPI_DO, a value of FFh will appear to have been read from any inter-
nal register while the device is uninitialized. By verifying the SPI Test Register (SPI_TEST) (UPD360-C Only) has at
least one “0” bit in it, it is possible to tell when the device is initialized.
6.2.2
ACCESS DURING AND FOLLOWING POWER MANAGEMENT
The Wake event on SPI traffic is local to the specific device, and does not affect the states of other devices even on the
same SPI bus. Until waking is complete, the SPI interface holds the SPI_DO pin low for the duration of the SPI_CS low
time.
Until the device is awake, then, any Read access performed by the Master will appear to have returned all “1” bits. To
determine when the device is awake and the SPI interface functional, the SPI Test Register (SPI_TEST) (UPD360-C
Only) should be repeatedly polled by the Master in separate frames (SPI_CS low then high). Once a correct, non-zero
value is read, the interface can be considered functional. As an alternative to polling, an IRQ_N pin assertion can be
used to indicate the device is ready.
Once the power management mode changes back to ACTIVE, the SPI interface will still ignore the SPI_CLK and
SPI_DI pins, following SPI_CS low with SPI_DO low, until SPI_CS is seen high. At the next SPI_CS falling edge, SPI
communication will continue normally.
At any time after performing SPI traffic, the device will not go back to a non-communicating power state until explicitly
allowed to do so by a command from the SPI Master.
2016-2017 Microchip Technology Inc.
DS00002084C-page 27
UPD360
Figure 6-1 illustrates the sequence of waking from SPI traffic.
FIGURE 6-1:
POWER MANAGEMENT WAKE ON SPI TRAFFIC
Wake
Trigger
...
...
SPI_CS
Osc. Lock
(Internal)
awake
asleep
...
...
Z
Z
Z
Z
Z
X Z
Read
SPI_DO
0
0
Data
Master sees Read data as all ‘0’ bits.
Instruction / Address
X
(Ignored by Device)
X
X
SPI_DI
Recognized by Device
X
(Ignored by Device)
X
X
SPI_CLK
6.2.3
SPI READ COMMAND (FAST READ)
The Fast Read command is supported by the SPI slave. A single byte, or multiple bytes, may be read in a single frame
(SPI_CS low).
Fast Read is the only form of Read access supported by the device. The instruction inputs the instruction code, the
address and a dummy byte on SPI_DI, and outputs the data one bit per clock on SPI_DO.
The SPI slave interface is selected by first bringing SPI_CS active. The 8-bit FASTREAD instruction, 0Bh, is input into
the SPI_DI pin, followed by the two address bytes and 1 dummy byte. The address bytes specify a Byte register address
within the device, and also specify how addresses are sequenced for successive bytes in a Multiple Byte Read (below).
The contents of the dummy byte are don’t-care.
On the falling clock edge following the rising edge of the last dummy bit, the SPI_DO pin is driven starting with the most
significant bit of the selected register byte. The remaining register bits are shifted out on subsequent falling clock edges.
The SPI_CS input is brought inactive to conclude the cycle. The SPI_DO pin is floated by the device in response.
6.2.3.1
Multiple Byte Reads
Additional byte reads beyond the first are performed by the Master by continuing the clock pulses while SPI_CS is active.
The upper two bits [15:14] (DIR subfield) of the address specify Auto-Incrementing (DIR=00b) or Auto-Decrementing
(DIR=10b) or Static (fixed) (DIR=11b) for successive bytes read. Maintaining a Static internal address is provided for
FIFO Read/Write or low-level register polling within a single frame, if the Master supports it.
Towards the end of the current one-byte output shift the address is incremented or decremented, if appropriate, and
another synchronized capture sequence is done.
DS00002084C-page 28
2016-2017 Microchip Technology Inc.
UPD360
6.2.3.2
Fast Read
Figure 6-2 illustrates a typical single and multiple register fast read for SPI mode.
FIGURE 6-2:
SPI FAST READ
SPI_CS
SPI_CLK (Mode 3)
SPI_CLK (Mode 0)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
X
X
1
2
3
4
5
6
7
8
9
X
X
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
1
2
3
4
5
6
7
8
9
Instruction
Address
Dummy
A
1
3
A
1
2
A
1
1
A
1
0
A
A
8
A
7
A
A
5
A
4
A
3
A
2
A
1
A
0
x
x
x
x
x
x
x
x
X
0
0
0
0
1
0
1
1
DIR
X
SPI_DI
9
6
Inc / Dec /
Static (Irrelevant to1-byte Reads)
Data
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Z
X
Z
SPI_DO
SPI Fast Read Single Register
SPI_CS
SPI_CLK (Mode 3)
SPI_CLK (Mode 0)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
...
...
...
...
X
X
1
2
3
4
5
6
7
8
9
X
X
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
...
1
2
3
4
5
6
7
8
9
Instruction
Address
Dummy
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
...
x
x
x
x
x
x
x
x
X
0
0
0
0
1
0
1
1
DIR
X
X
X
SPI_DI
Inc / Dec /
Static
Data 1......Data m Data m.+.1....Data n
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
D
2
D
1
D
Z
X
0
Z
SPI_DO
5
SPI Fast Read Multiple Registers
6.2.4
SPI WRITE COMMANDS
The following write commands are supported by the SPI slave controller:
• Write
• Multiple Writes
6.2.4.1
Write
The Write instruction provides the instruction code and address and data bytes on the SPI_DI pin, one bit per clock.
The SPI transfer is started by the Master first driving SPI_CS active. The 8-bit WRITE instruction, 02h, is given on the
SPI_DI pin, followed by the two address bytes. The address bytes specify a byte address within the device, and a Direc-
tion control subfield (DIR).
The data immediately follows the address bytes on the SPI_DI pin, starting with the most significant bit of the first byte.
The data is input from the SPI_DI pin by the device, shifted in on each subsequent rising clock edge.
6.2.4.2
Multiple Writes
Multiple writes are performed by the Master by continuing the clock pulses and SPI_DI data while SPI_CS remains
active. The upper two bits [15:14] of the address constitute the DIR subfield, and specify auto-incrementing (DIR=00b)
or auto-decrementing (DIR=10b) or Static addressing. The internal Byte address is incremented, decremented, or kept
fixed (Static) based on these bits. Maintaining a fixed internal address may be useful for FIFO access, register “bit-bang-
ing” or other repeated activity.
The data write to the register occurs after the full register contents are input: this depends on the defined size of the
register. In the event that the full register is not written when SPI_CS is returned high, the write is considered invalid and
the register is not affected.
The SPI_CS input is then brought inactive to conclude the cycle.
2016-2017 Microchip Technology Inc.
DS00002084C-page 29
UPD360
Figure 6-3 illustrates a typical SPI single and multiple register write.
FIGURE 6-3:
SPI WRITE
SPI_CS
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
X
X
1
2
3
4
5
6
7
8
9
X
X
SPI_CLK (Mode 3)
SPI_CLK (Mode 0)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
1
2
3
4
5
6
7
8
9
Instruction
Address
Data
A
1
3
A
1
2
A
1
1
A
1
0
A
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
0
0
0
0
0
0
1
0
DIR
X
SPI_DI
9
Inc / Dec /
Static (Irrelevant to 1-byte Writes)
Z
SPI_DO
SPI Write Single Register
SPI_CS
SPI_CLK (Mode 3)
SPI_CLK (Mode 0)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
...
...
...
X
X
1
2
3
4
5
6
7
8
9
X
X
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
...
1
2
3
4
5
6
7
8
9
7
Instruction
Address
Data 1......Data m Data m.+.1.... Data n
A
1
3
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
X
0
0
0
0
0
0
1
0
DIR
X
SPI_DI
Inc / Dec /
Static
Z
SPI_DO
SPI Write Multiple Registers
6.2.5
SPECIAL CSR HANDLING
Live Bits
6.2.5.1
Register values are latched (registered) at the beginning of each register read to prevent the host from reading a chang-
ing value. The latching occurs individually per register in a multiple register read sequence.
6.2.5.2
Change-on-Read Registers and FIFOs
Any single-byte register that triggers a side-effect from a read operation (for example, containing “clear on read” bits, or
advancing a FIFO structure) triggers only after the host has begun accessing the value. The value seen by the master
will always be the original value and never the updated result of the side-effect.
For a multiple-byte register that is considered a single unit, the change may be delayed until all bytes of the register
have been read. In the event that the host sends a no-acknowledge on one of the first bytes of a multi-byte register, or
a start or stop condition occurs unexpectedly before the acknowledge of the full register, the read may be considered
invalid and the side-effect not triggered.
Registers read in multiple-register read access will trigger multiple side-effects, occurring as they are read. The following
registers have read side-effects:
• Watchdog Count Register (WDT_COUNT)
6.2.5.3
Live Bits that are also Change-on-Read
As described above, the current value from a register with live bits (as is the case of any register) is captured and latched
as output data, and Change on Read bits are then changed in the original register. To prevent loss of a hardware event
that occurs following the data capture but before the Change on Read, these hardware events are held pending until
after the read action and after any change due to the read. This sequence also ensures an edge in the bit due to the
hardware event.
DS00002084C-page 30
2016-2017 Microchip Technology Inc.
UPD360
7.0
CLOCKS, RESETS, AND POWER MANAGEMENT
This section details the various clocks, resets, and power managements states of the device:
7.1
Clocks
The following internal clocks are generated by the device:
• 48 MHz Relaxation Oscillator
• 20 KHz Keep Alive Oscillator
• Ring Oscillator
These oscillators can be manually enabled/disabled via the Clock Control Register (CLK_CTL).
7.2
Power States
The device supports four power states, as defined in the following sub-sections:
• SLEEP
• STANDBY
• ACTIVE_PPC_OFF
• ACTIVE_PPC_ON
7.2.1
SLEEP
This is the lowest power state of the device. The SLEEP state is entered via assertion of the PWR_DN pin. Virtually all
of the device is powered off in this mode with minimal circuity in the 3.3V domain to detect deassertion of PWR_DN.
This mode is intended to minimize power consumption when the device is not being used in battery powered applica-
tions. In these applications, a wake up event such as a button press, can cause the host CPU to deassert PWR_DN.
7.2.2
STANDBY
STANDBY is the lowest power functional state of the device. The majority of the device is powered off in this state. The
internal CC comparator and 20 KHz oscillator are enabled in this state as well as requisite analog components (1.8V
LDO, PORs, Biases, etc).
The CC lines are constantly monitored for an attach condition which shall result in an interrupt assertion to the host. If
an attachment has been made, this state can detect a change in the partner’s advertisement as well as a detach.
STANDBY is the power state that the UPD360 device will be in when in USB Type-CTM Unattached.SRC/SNK.
The following asynchronous wake-ups are supported from this state:
• Asynchronous I2C Wakeup (UPD360-A/UPD360-B Only)
• Asynchronous SPI Wakeup (UPD360-C Only)
• Power Delivery MAC Wakeup
7.2.3
ACTIVE_PPC_OFF
This state defines the condition where the internal 48 MHz oscillator is enabled, but the Port Power Controller is dis-
abled. A use case for this state would be when it is desired to debounce a GPIO for a micro-second period. In that case,
the internal 48 MHz oscillator is required to time the debounce.
The device also momentarily enters this state when being addressed via software I2C/SPI accesses or to implement
Power Delivery communications.
The UPD360 will be in ACTIVE_PPC_OFF primarily when in USB Type-CTM Attached.SNK state, or Attached.SRC
state with VBUS being driven by an external power source.
7.2.4
ACTIVE_PPC_ON
This state defines the condition where the Port Power Controller is operational, which necessitates the internal 48 MHz
oscillator be enabled for the Port Power Controller.
2016-2017 Microchip Technology Inc.
DS00002084C-page 31
UPD360
The UPD360 will be in ACTIVE_PPC_ON state when in USB Type-CTM Attached.SRC state with VBUS being driven
by the internal 5V port power controller.
7.3
Asynchronous I2C Wakeup (UPD360-A/UPD360-B Only)
The device supports asynchronous wakes on the I2C slave interface. Via clock stretching, the I2C transaction that
caused the wakeup will not be lost and does not have to be repeated by the host. The device will not clock stretch for
more than 3 us.
The following steps illustrate the I2C wake function. Initially the Ring Oscillator and 48 MHz Oscillator are disabled.
1. The Host initiates an I2C transaction to the device.
2. The device asynchronously detects reception of the Start Bit and enables clock stretching by pulling-down I2C_-
CLK after the host drives SCL low. The Ring Oscillator is asynchronously enabled and used as a clock source
for the power management logic.
3. After a delay of approximately 5 us the oscillator stabilizes and clocks the I2C controller.
4. Clock stretching is disabled and the I2C controller is enabled and begins processing the pending transaction.
5. The I2C transaction completes.
6. The Host checks the device status to see if there are any pending transactions. The I2C transaction may have
initiated a PD transmission or conversely a coincident PD transaction may be in the process of being received.
7. After host confirms the device has no pending transactions, it power downs the device by disabling the Ring
Oscillator and 48 MHz Relaxation Oscillator via Clock Control Register (CLK_CTL).
8. The device is ready to accept future asynchronous I2C wake event.
7.4
Asynchronous SPI Wakeup (UPD360-C Only)
UPD360 supports asynchronous wakes on the SPI interface. The SPI protocol for this device is defined such that there
is no requirement that the SPI transaction must be repeated.
The following steps illustrate the SPI wake function. Initially the Ring Oscillator and 48 MHz Oscillator are disabled.
1. The device is powered down.
2. The Host initiates an SPI transaction to the SPI Test Register (SPI_TEST) (UPD360-C Only) which, when the
device is operational, returns a non-zero value. The device drives SPI_DO to 0b while in power-down.
3. The device detects reception of an SPI message. The Ring Oscillator is asynchronously enabled and used as a
clock source for the power management logic.
4. After a delay of approximately 5 us the oscillator stabilizes and clocks the SPI controller.
5. The device processes the next received SPI transaction.
6. The SPI transaction(s) complete(s).
7. The Host checks the device status to see if there are any pending transactions. The SPI transaction may have
initiated a PD transmission or conversely a coincident PD transaction may be in the process of being received.
8. After the Host confirms the device has no pending transactions, it powers down the device by disabling the Ring
Oscillator, and 48 MHz Relaxation Oscillator via Clock Control Register (CLK_CTL).
9. The device drives SPI_DO to 0b and awaits an asynchronous SPI wake.
DS00002084C-page 32
2016-2017 Microchip Technology Inc.
UPD360
7.5
Power Delivery MAC Wakeup
The PD MAC is capable of asynchronous wakeup upon reception of a PD packet. This enables the device to be placed
in STANDBY mode and minimize power consumption.
The following steps illustrate the RX PD MAC wake function. Initially the Ring Oscillator and the 48 MHz Relaxation
Oscillator are disabled. The 20 KHz Keep Alive Oscillator is enabled, but not used in the wake process.
1. In order to receive a PD message, the RX AFE is enabled via software and the trip point is set via the CC RX
DAC Control Register (CC_RX_DAC_CTL) and CC RX DAC Filter Register (CC_RX_DAC_FILT).
2. The PD MAC is configured and enabled via software.
3. The device is powered down. Software disables the 48 MHz Relaxation Oscillator, and Ring Oscillator if enabled,
via the Clock Control Register (CLK_CTL).
4. After some time elapses, the device receives a PD message from the attached partner.
5. The PD MAC asynchronously detects preamble activity on the CC line and enables the 48 MHz Relaxation Oscil-
lator.
6. The oscillator is operational in approximately 5 us, at which point the PD MAC is operational.
7. The PD MAC receives the remainder of the preamble and stores the message into the RX FIFO, and in accor-
dance with the PD protocol, responds with GoodCRC as required.
8. An interrupt is issued via assertion of the IRQ_N pin.
9. Software services the interrupt via I2C, reads the PD message, and responds as required.
10. The device is then powered down. Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via
the Clock Control Register (CLK_CTL).
11. The device remains powered down until the next PD message is received.
7.6
Interrupt Assertion from STANDBY
When the device is in STANDBY it is able to detect a number of events that may be configured to assert the IRQ_N pin
upon being appropriately programmed via software. The logic detecting such events operates off of the 20 KHz Keep
Alive Oscillator.
Upon the occurrence of an event, which is programmed to assert IRQ_N, the 48 MHz Relaxation Oscillator and Ring
Oscillator are enabled. Upon synchronization, the IRQ_N pin shall assert.
After software services the source interrupt(s), it should disable the 48 MHz Relaxation Oscillator and Ring Oscillator
via the Clock Control Register (CLK_CTL) to place the part back in STANDBY.
The following example sequence illustrates the steps for configuring the device to detect an OCS event on the OCS_-
COMP1 pin while in STANDBY.
1. Software enables the OCS_CMP_INT bit in the Interrupt Enable Register (INT_EN).
2. Software enables OCS detection, as defined in Section 8.3, "External Over-current Detection", to sample the
OCS_COMP1 pin.
3. Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via the Clock Control Register
(CLK_CTL).
4. An OCS event occurs and is detected on OCS_COMP1.
5. The Ring Oscillator is enabled and is used to as the device’s operational clock.
6. The device enables the 48 MHz oscillator and waits about 5 us for the oscillator to stabilize.
7. The 48 MHz oscillator is stable.
8. After synchronization is complete, the IRQ_N pin is asserted.
9. Software detects IRQ_N assertion and services the interrupt.
10. Software disables the 48 MHz Relaxation Oscillator and Ring Oscillator via the Clock Control Register
(CLK_CTL) to place the part back in STANDBY.
2016-2017 Microchip Technology Inc.
DS00002084C-page 33
UPD360
7.7
Reset Operation
The following chip-level resets are supported by the device:
• Power-On-Reset (POR)
• Pin Reset (RESET_N)
• Software Reset (SRESET in Hardware Control Register (HW_CTL))
• Watchdog Timer (WDT_STS)
Chip-level resets trigger the sampling of the CFG_SEL0 and CFG_SEL1 configuration straps (see Section 9.8.1, "Con-
figuration Selection," on page 81 for additional information). Chip-level reset completion can be determined by assertion
of the RDY_INT bit in the Interrupt Enable Register (INT_EN) and assertion of the IRQ_N pin.
The following is s summary of steps that occur after a chip-level reset.
1. System level reset event (POR, RESET_N, SRESET, WDT_STS) occurs.
2. The device enables the 20 KHz Keep Alive Oscillator, 48 MHz Relaxation Oscillator, and 1MHz Ring Oscillator.
3. The device samples the CFG_SELx pins.
4. The device configures itself in accordance with the CFG_SELx pin and settings.
5. The device is enabled, the RDY_INT bit in the Interrupt Enable Register (INT_EN) asserts, the IRQ_N pin
asserts.
6. The device disables the 48 MHz Relaxation Oscillator and the Ring Oscillator.
7.8
Clocks and Power Management Registers
This section details the clocks and power management registers. For an overview of the entire device register map, refer
to Section 4.0, "Register Map," on page 19.
TABLE 7-1:
Address
1000h
CLOCKS AND POWER MANAGEMENT REGISTERS MAP
Register Name (Symbol)
Clock Control Register (CLK_CTL)
1001h – 13FFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
7.8.1
CLOCK CONTROL REGISTER (CLK_CTL)
Address:
1000h
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
RO
-
2
1
0
Ring Oscillator Enable
0: Oscillator is disabled.
1: Oscillator is enabled.
R/W
R/W
R/W
0b
Note 7-1
1b
48 MHz Relaxation Oscillator Enable
0: Oscillator is disabled.
1: Oscillator is enabled.
20 KHz Keep Alive Oscillator Enable
0: Oscillator is disabled.
1: Oscillator is enabled.
Note 7-1
This bit will always appear asserted when read by software, as the 48 MHz Relaxation Oscillator must
be enabled to facilitate I2C/SPI transactions.
DS00002084C-page 34
2016-2017 Microchip Technology Inc.
UPD360
8.0
SYSTEM CONTROL
This section details the following system controls:
• System Interrupts
• General Purpose I/O
• External Over-current Detection
• System Control Registers
8.1
System Interrupts
The device provides an open drain interrupt pin, IRQ_N, which is asserted as a function of the System Control’s Interrupt
Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The following interrupts are supported:
• HPD Interrupt
• Power Switch Module Interrupt
• Watchdog Timer Assertion Interrupt
• Port Power Controller Interrupt
• Power Delivery MAC Interrupt
• OCS Comparator Interrupt
• PIO Override Interrupt
• PIO Interrupt
• CC Interrupt
• VBUS Interrupt
• Power Control Interrupt
• Device Ready Interrupt
In order to clear an interrupt status bit, the source of the asserted bit in Interrupt Status Register (INT_STS) must be
cleared. This process typically involves dealing with the module (e.g. PD MAC, CC, Port Power Controller, Watchdog
Timer, Power Switch, etc.) that triggered the interrupt or configuring the respective module’s interrupt enable register to
disable assertion.
The PIO interrupts are cleared by writing “1” to the asserted bit(s) in PIO Interrupt Status Register (PIO_INT_STS). The
PIO Override interrupts are cleared by writing “1” to the asserted bit(s) in PIO Override Interrupt Status Register
(PIO_OVR_INT_STS). The OCS interrupts are cleared by is cleared by writing “1” to the asserted bit(s) in OCS Com-
parator Change Status Register (OCS_CMP_CHG_STS).
Figure 8-1 illustrates the device’s interrupt hierarchy. Figure 8-2 illustrates the generation of the CC_INT bit in the Inter-
rupt Status Register (INT_STS).
2016-2017 Microchip Technology Inc.
DS00002084C-page 35
UPD360
FIGURE 8-1:
SYSTEM INTERRUPT HIERARCHY
System Control.INT_STS[0]
CC_INT Interrupt
System Control.INT_EN[0]
PIO_INT[0]
PIO_EN[0]
System Control.INT_STS[1]
System Control.INT_EN[1]
PIO_INT[15]
PIO_EN[15]
PIO_OVR_INT[0]
PIO_OVR_EN[0]
System Control.INT_STS[2]
System Control.INT_EN[2]
PIO_OVR_INT[3]
PIO_EN[3]
System Control.INT_STS[3]
IRQ_N Pin
OCS Comparator Match
System Control.INT_EN[3]
System Control.INT_STS[4]
PDMAC Interrupt
System Control.INT_EN[4]
System Control.INT_STS[5]
PPC Interrupt
System Control.INT_EN[5]
System Control.INT_STS[6]
WDT Event
System Control.INT_EN[6]
System Control.INT_STS[7]
PSW Interrupt
System Control.INT_EN[7]
System Control.INT_STS[8]
HPD Interrupt
System Control.INT_EN[8]
VBUS_CHG_STS[0]
VBUS_MATCH_EN[0]
System Control.INT_STS[9]
VBUS Change Interrupt
System Control.INT_EN[9]
VBUS_CHG_STS[7]
VBUS_MATCH_EN[7]
System Control.INT_STS[10]
Power Event Interrupt
System Control.INT_EN[10]
System Control.INT_STS[11]
RESERVED
System Control.INT_EN[11]
System Control.INT_STS[12]
Device Ready
System Control.INT_EN[12]
DS00002084C-page 36
2016-2017 Microchip Technology Inc.
UPD360
FIGURE 8-2:
CC_INT INTERRUPT HIERARCHY
CC1_CHG_STS[0]
CC1_MATCH_EN[0]
CC_INT_STS[0]
CC_INT_EN[0]
CC1_CHG_STS[7]
CC2_MATCH_EN[7]
CC2_CHG_STS[0]
CC2_MATCH_EN[0]
CC_INT_STS[1]
CC_INT_EN[1]
CC2_CHG_STS[7]
CC2_MATCH_EN[7]
CC_INT_STS[2]
CC_INT_EN[2]
Connect Detected
CC_INT_STS[3]
CC_INT_EN[3]
Disconnect Detected
CC_INT
(to INT_STS[0])
CC_INT_STS[4]
CC_INT_EN[4]
CC_INT_STS[5]
CC_INT_EN[5]
Attach Detected
Detach Detected
CC_INT_STS[6]
CC_INT_EN[6]
0b
0b
CC_INT_STS[7]
CC_INT_EN[7]
8.2
General Purpose I/O
A key function of the UPD360 is to manage external devices via up to sixteen PIOs. Usually this is accomplished via
host software programming of the PIOs.
In some cases the UPD360 must automatically override the PIO state in response to an error condition. Features have
been incorporated into the design to enable such operation. This is required in cases where the latency introduced by
reliance on software to affect PIO state is either or too long or not deterministic.
A PIO is configured via the respective Configure PIOx Registers (CFG_PIOx). A PIO may also be configured to assert
PIO_INT in Interrupt Status Register (INT_STS). The state of a PIO is known by reading the PIO Status Register
(PIO_STS).
A mechanism exists for multiple PIO outputs to be updated via a single register write. This is accomplished via the Con-
figure PIO Output Register (CFG_PIO_OUT). Writes to this register that change the output value of a PIO are reflected
in the DataOutput bit of the respective Configure PIOx Registers (CFG_PIOx). Likewise, writes to DataOutput in the
Configure PIOx Registers (CFG_PIOx) will update the respective bit in the Configure PIO Output Register (CFG_PI-
O_OUT).
Note:
The GPO1 and GPO10 general purpose signals can only function as outputs and must be kept in a
low state coincident with de-asserting RESET_N.
Note:
Note:
GPIO0 is not available in the UPD360-C.
In Standalone DFP/UFP modes (UPD360-A/UPD360-B only), GPIOs 9-15 have alternate dedicated func-
tions, as defined in Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP
Modes," on page 11
2016-2017 Microchip Technology Inc.
DS00002084C-page 37
UPD360
8.2.1
PIO SIMULTANEOUS UPDATE
A mechanism has been incorporated to enable multiple PIOs to be updated simultaneously. This is desirable to simplify
software and prevent devices controlled by the UPD360 from entering an intermediary unknown state. Of particular con-
cern would be devices responsible for managing power.
The Configure PIOx Registers (CFG_PIOx) CSR is updated by this function. When the simultaneous update request is
accepted by hardware, the contents of the PIO registers are simultaneously updated.
The example below illustrates simultaneous PIO update operation:
1. Software changes Configure PIOx Update Registers (CFG_PIOx_UPD) as required.
2. Software changes Configure PIO Output Update Register (CFG_PIO_OUT_UPD) as required.
Note:
The Configure PIO Output Update Register (CFG_PIO_OUT_UPD) and Configure PIOx Update Registers
(CFG_PIOx_UPD) must be programmed consistently by software. If the output value bits are different
between the two registers, then the value in Configure PIOx Update Registers (CFG_PIOx_UPD) will be
used for updating the Configure PIOx Registers (CFG_PIOx) and the respective bit in Configure PIO Out-
put Register (CFG_PIO_OUT).
3. Software sets the Configure PIOx Update Registers (CFG_PIOx_UPD) to initiate the update.
4. A pending PIO override blocks acceptance of the update request. Only after the pending PIO override function
is cleared will the device clear PIO_UPD_REQ. The pending PIO override is cleared via the PIO Override Enable
Register (PIO_OVR_EN).
5. After the update is accepted, PIO_UPD_REQ clears automatically.
APPLICATION NOTE: If a PIO override is pending, the PIO simultaneous update is blocked.
8.2.2
PIO OVERRIDE
Overview
8.2.2.1
A mechanism is defined in this section to enable the state of a PIO to be changed without software intervention. This
provides a mechanism to instantaneously disable a power circuit, controlled by a UPD360 PIO, based upon a change
in the state of a selected PIO input, OCS detection or other event.
8.2.2.2
Description
Four override functions are included in device. For each function, a PIO or other source must be selected for monitoring
via the corresponding PIO Override x Source Select Registers (PIO_OVRx_SRC_SEL). The value to be monitored is
set in the PIO Override Monitor Value Register (PIO_OVR_MON_VAL) and is compared with the state of the respective
PIO. When these values match for an override, the enabled PIO outputs change their state accordingly.
PIO outputs controlled by an override are enabled by the PIO Override x Output Enable Registers (PIO_OVRx-
_OUT_EN). Each override has an instance in this register. A PIO may be used across multiple overrides.
Firmware can be notified that an override was executed via assertion of PIO_OVERRIDE_INT in the Interrupt Status
Register (INT_STS), if Interrupt Enable Register (INT_EN) is appropriately configured.
DS00002084C-page 38
2016-2017 Microchip Technology Inc.
UPD360
8.3
External Over-current Detection
The device incorporates an analog comparator DAC circuit to detect an over-current condition. This feature is supported
via the OCS_COMP1 and/or OCS_COMP2 pin.
This feature is enabled as follows:
1. Software clears the OCS Comparator Control bit in the OCS Comparator Control Register (OCS_CMP_CTL) to
determine the OCS debouncer.
2. Software polls OCS_DB_ACTIVE until it clears, which indicates the OCS debouncer is disabled.
3. If OCS_COMP2 is desired, the shared PIO must be disabled via the Configure PIOx Registers (CFG_PIOx).
4. Software programs one or both of the OCS Comparator x Threshold Registers (OCS_CMPx_THR), as required.
5. Software programs the OCS Comparator Debounce Register (OCS_CMP_DEBOUNCE).
6. Software enables the OCS_COMPx pin(s) via the OCS Comparator Match Enable Register (OCS_CMP_-
MATCH_EN).
7. Software enables the respective interrupt in the Interrupt Enable Register (INT_EN).
8. Software sets the OCS Comparator Control bit in the OCS Comparator Control Register (OCS_CMP_CTL) to
enable comparison on OCS_COMP1 and/or OCS_COMP2, as desired.
9. Detection of an over current event by the comparator results in the respective bit of the OCS Comparator Change
Status Register (OCS_CMP_CHG_STS) and OCS_CMP_INT asserts. The IRQ_N pin will assert, if configured.
10. Software writes to the OCS Comparator Change Status Register (OCS_CMP_CHG_STS) to clear OCS_C-
MP_INT. For a Lo-to-Hi transition, the respective bit in the OCS Comparator Match Register (OCS_CMP_-
MATCH) is set, while for a Hi-to-Lo transition the bit is cleared.
This feature is disabled when software clears the OCS Comparator Control bit in the OCS Comparator Control Register
(OCS_CMP_CTL). Either OCS_COMPx pin may be used to trigger a PIO override.
8.4
General Purpose Timer
The device incorporates a low power general purpose timer that operates off a 20 kHz oscillator and implements a 16-
bit one-shot down counter. When the timer underflows, it asserts the GP_UFLOW bit in General Purpose Timer Interrupt
Source Register (GP_TIMER_INT_SRC) and stops counting. This in turn causes the GP_TIMER_INT to assert in Inter-
rupt Status Register (INT_STS). The interrupt persists until the GP_UFLOW bit is cleared. If the respective bit is set in
Interrupt Enable Register (INT_EN), the IRQ_N pin will assert.
The timer’s upper threshold is loaded via the General Purpose Timer Load Register (GP_TIMER_LOAD). Setting
RESET in the General Purpose Timer Control Register (GP_TIMER_CTL) causes the timer’s internal counter to be
loaded to this value.
The timer is enabled by setting ENABLE in the General Purpose Timer Control Register (GP_TIMER_CTL). This causes
the timer to decrement every 1 ms. The timer continues to decrement until it underflows or it is disabled.
Note:
The underflow condition is defined as when the down counter transitions from 0x0000 to 0xFFFF.
Clearing the ENABLE bit in the General Purpose Timer Control Register (GP_TIMER_CTL) disables the timer and it
stops counting.
The timer’s current count can be read from General Purpose Timer Count Register (GP_TIMER_COUNT) The timer
should be halted by clearing ENABLE before reading it. After the count is read, the ENABLE may be set again and the
counter will resume.
The DIS_ON_UFLOW bit in the General Purpose Timer Control Register (GP_TIMER_CTL) causes the timer to auto-
matically disable upon underflow detection and assert GP_UFLOW. In this case the assertion of GP_UFLOW is delayed
until the timer is fully disabled.
APPLICATION NOTE: This timer enables clocking sources to be disabled in the host CPU which is useful for timing
events such as DRP. This helps provide for a lower total power system solution.
The following steps illustrate the usage model for DRP implementation:
1. Software configures the device as a DFP or UFP. See Section 9.4, "DRP Operation" for further details.
2. Software enables the GP_TIMER_INT in the Interrupt Enable Register (INT_EN).
2016-2017 Microchip Technology Inc.
DS00002084C-page 39
UPD360
3. Software programs the General Purpose Timer Load Register (GP_TIMER_LOAD) to a random value that com-
plies with the range for tDRP period as defined in the USB Type-C Specification.
4. Software sets the ENABLE, RESET and DIS_ON_UFLOW bits in the General Purpose Timer Control Register
(GP_TIMER_CTL). This causes the value in the General Purpose Timer Load Register (GP_TIMER_LOAD) to
be loaded into the timer and it begins decrementing. This also configures the timer to delay assertion of GP_U-
FLOW in the General Purpose Timer Interrupt Source Register (GP_TIMER_INT_SRC) until the timer is fully dis-
abled .
APPLICATION NOTE: Writes to General Purpose Timer Load Register (GP_TIMER_LOAD) and General Purpose
Timer Control Register (GP_TIMER_CTL) defined in the prior steps may be done in the
same I2C write burst.
5. Upon timer expiration, the GP_UFLOW bit will be set and the GP_TIMER_INT asserts in Interrupt Status Register
(INT_STS).
6. The IRQ_N pin asserts.
7. Software services the IRQ and determines whether or not a connection has been established with a UFP, or DFP.
If no connection has been established, software changes the device’s role. See Section 9.4, "DRP Operation" for
further details.
8. Software programs the General Purpose Timer Load Register (GP_TIMER_LOAD) to a random value that com-
plies with the range of the tDRP period as defined in the USB Type-C Specification.
9. Software shall clear the GP_UFLOW bit in the General Purpose Timer Interrupt Source Register (GP_TIM-
ER_INT_SRC).
10. Software sets the ENABLE, RESET and DIS_ON_UFLOW bits in General Purpose Timer Control Register (GP_-
TIMER_CTL). This causes the value in General Purpose Timer Load Register (GP_TIMER_LOAD) to be loaded
into the timer and the timer begins decrementing.
APPLICATION NOTE: Writes to the General Purpose Timer Load Register (GP_TIMER_LOAD), General Purpose
Timer Interrupt Source Register (GP_TIMER_INT_SRC) and General Purpose Timer Control
Register (GP_TIMER_CTL) defined in the prior steps may be done in the same I2C write
burst.
11. Upon timer expiration, and timer disablement, the GP_UFLOW bit will be set and the GP_TIMER_INT asserts in
Interrupt Status Register (INT_STS).
12. The IRQ_N pin asserts.
13. Software services the IRQ and determines if a connection has been established with a UFP, or DFP. If no con-
nection has been established SW changes the device’s role. See Section 9.4, "DRP Operation" for further details.
14. Goto step 8.
DS00002084C-page 40
2016-2017 Microchip Technology Inc.
UPD360
8.5
System Control Registers
This section details the system control registers. For an overview of the entire device register map, refer to Section 4.0,
"Register Map," on page 19.
TABLE 8-1:
Address
SYSTEM CONTROL REGISTER MAP
Register Name (Symbol)
0000h
0004h
0006h
0008h
000Ah
Device ID Register (ID_REV)
USB Vendor ID Register (VID)
USB Product ID Register (PID)
USB PD Revision Register (PD_REV)
USB Type-C™ Revision Register (C_REV)
000Bh - 000Dh Reserved for future expansion
000Eh
0010h
SPI Test Register (SPI_TEST) (UPD360-C Only)
Interrupt Status Register (INT_STS)
0014h
Interrupt Enable Register (INT_EN)
0018h
Hardware Control Register (HW_CTL)
001Ah
001Bh
001Ch - 001Fh
0020h
I2C Slave Address Register (I2C_ADDR) (UPD360-A/UPD360-B Only)
PPC Status Register (PPC_BUSY)
Reserved for future expansion
PIO Status Register (PIO_STS)
0022h
PIO Interrupt Status Register (PIO_INT_STS)
PIO Interrupt Enable Register (PIO_INT_EN)
Reserved for future expansion
0024h
0026h - 002Fh
0030h
Configure PIOx Registers (CFG_PIOx) x=0
Configure PIOx Registers (CFG_PIOx) x=1
Configure PIOx Registers (CFG_PIOx) x=2
Configure PIOx Registers (CFG_PIOx) x=3
Configure PIOx Registers (CFG_PIOx) x=4
Configure PIOx Registers (CFG_PIOx) x=5
Configure PIOx Registers (CFG_PIOx) x=6
Configure PIOx Registers (CFG_PIOx) x=7
Configure PIOx Registers (CFG_PIOx) x=8
Configure PIOx Registers (CFG_PIOx) x=9
Configure PIOx Registers (CFG_PIOx) x=10
Configure PIOx Registers (CFG_PIOx) x=11
Configure PIOx Registers (CFG_PIOx) x=12
Configure PIOx Registers (CFG_PIOx) x=13
Configure PIOx Registers (CFG_PIOx) x=14
Configure PIOx Registers (CFG_PIOx) x=15
Configure PIOx Update Registers (CFG_PIOx_UPD) x=0
Configure PIOx Update Registers (CFG_PIOx_UPD) x=1
Configure PIOx Update Registers (CFG_PIOx_UPD) x=2
Configure PIOx Update Registers (CFG_PIOx_UPD) x=3
Configure PIOx Update Registers (CFG_PIOx_UPD) x=4
Configure PIOx Update Registers (CFG_PIOx_UPD) x=5
Configure PIOx Update Registers (CFG_PIOx_UPD) x=6
Configure PIOx Update Registers (CFG_PIOx_UPD) x=7
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
2016-2017 Microchip Technology Inc.
DS00002084C-page 41
UPD360
TABLE 8-1:
Address
SYSTEM CONTROL REGISTER MAP (CONTINUED)
Register Name (Symbol)
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Bh
005Dh - 005Fh
0060h
0062h
0064h
0066h
0068h
006Ah
006Ch
006Dh
006Eh
006Fh
0070h
Configure PIOx Update Registers (CFG_PIOx_UPD) x=8
Configure PIOx Update Registers (CFG_PIOx_UPD) x=9
Configure PIOx Update Registers (CFG_PIOx_UPD) x=10
Configure PIOx Update Registers (CFG_PIOx_UPD) x=11
Configure PIOx Update Registers (CFG_PIOx_UPD) x=12
Configure PIOx Update Registers (CFG_PIOx_UPD) x=13
Configure PIOx Update Registers (CFG_PIOx_UPD) x=14
Configure PIOx Update Registers (CFG_PIOx_UPD) x=15
PIO Override x Source Select Registers (PIO_OVRx_SRC_SEL) x=0
PIO Override x Source Select Registers (PIO_OVRx_SRC_SEL) x=1
PIO Override x Source Select Registers (PIO_OVRx_SRC_SEL) x=2
PIO Override x Source Select Registers (PIO_OVRx_SRC_SEL) x=3
PIO Override Monitor Value Register (PIO_OVR_MON_VAL)
PIO Override Enable Register (PIO_OVR_EN)
PIO Override Status Register (PIO_OVR_STS)
PIO Override Interrupt Status Register (PIO_OVR_INT_STS)
PIO Override Interrupt Enable Register (PIO_OVR_INT_EN)
Configure PIO Output Register (CFG_PIO_OUT)
Configure PIO Output Update Register (CFG_PIO_OUT_UPD)
Reserved for future expansion
PIO Override x Output Enable Registers (PIO_OVRx_OUT_EN) x=0
PIO Override x Output Enable Registers (PIO_OVRx_OUT_EN) x=1
PIO Override x Output Enable Registers (PIO_OVRx_OUT_EN) x=2
PIO Override x Output Enable Registers (PIO_OVRx_OUT_EN) x=3
PIO Override Output Register (PIO_OVR_OUT)
PIO Override Direction Register (PIO_OVR_DIR)
PIO Debounce Count Ten Millisecond Register (PIO_DEBOUNCE_10MS_COUNT)
PIO Debounce Count One Millisecond Register (PIO_DEBOUNCE_1MS_COUNT)
PIO Debounce Count One Microsecond Register (PIO_DEBOUNCE_1US_COUNT)
PIO Debounce Status Register (PIO_DEBOUNCE_STS)
PIO Debounce Enable Register (PIO_DEBOUNCE_EN)
0074h – 007Fh Reserved for future expansion
0080h
0081h
0082h
0083h
0084h
0086h
0088h
OCS Comparator Control Register (OCS_CMP_CTL)
OCS Comparator Match Register (OCS_CMP_MATCH)
OCS Comparator Change Status Register (OCS_CMP_CHG_STS)
OCS Comparator Match Enable Register (OCS_CMP_MATCH_EN)
OCS Comparator x Threshold Registers (OCS_CMPx_THR) x=1
OCS Comparator x Threshold Registers (OCS_CMPx_THR) x=2
OCS Comparator Debounce Register (OCS_CMP_DEBOUNCE)
0089h – 009Ah Reserved for future expansion
009Bh
009Ch
IRQ_N PU/PD Control Register (IRQ_PUPD)
Voltage Regulator Control Register (VREG_CTL)
I2C Trim Register (I2C_TRIM)
009Dh
009E – 009Fh
Reserved for future expansion
DS00002084C-page 42
2016-2017 Microchip Technology Inc.
UPD360
TABLE 8-1:
Address
SYSTEM CONTROL REGISTER MAP (CONTINUED)
Register Name (Symbol)
00A0h
00A2h
00A3h
00A4h
General Purpose Timer Load Register (GP_TIMER_LOAD)
General Purpose Timer Interrupt Source Register (GP_TIMER_INT_SRC)
General Purpose Timer Control Register (GP_TIMER_CTL)
General Purpose Timer Count Register (GP_TIMER_COUNT)
00A6h – 03FFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
8.5.1
DEVICE ID REGISTER (ID_REV)
Address:
0000h
Size:
32 bits
Bits
31:16 Device ID (ID)
Description
Type
Default
RO
0360h
15:0
Device Revision (REV)
RO
Note 8-1
Note 8-1
The default value of this field is dependent on the silicon revision of the device.
ID_REV[7:0] = 00h
ID_REV[15:8] = 01h
ID_REV[23:16] = 02h
ID_REV[31:24] = 03h
8.5.2
USB VENDOR ID REGISTER (VID)
Address:
0004h
Size:
16 bits
Bits
15:0
Description
Type
Default
USB Vendor Identification (VID)
R/W
0424h
VID[7:0] = 04h
VID[15:8] = 05h
8.5.3
USB PRODUCT ID REGISTER (PID)
Address:
0006h
Size:
16 bits
Bits
15:0
Description
Type
Default
USB Product Identification (PID)
R/W
0360h
PID[7:0] = 06h
PID[15:8] = 07h
2016-2017 Microchip Technology Inc.
DS00002084C-page 43
UPD360
8.5.4
USB PD REVISION REGISTER (PD_REV)
Address:
0008h
Size:
16 bits
16 bits
8 bits
Bits
15:0
Description
Type
Default
USB Power Delivery Specification Revision (PD_REV)
R/W
2013h
PD_REV[7:0] = 08h
PD_REV[15:8] = 09h
8.5.5
USB TYPE-C™ REVISION REGISTER (C_REV)
Address:
000Ah
Size:
Bits
15:0
Description
Type
Default
USB Type-C™ Specification Revision (C_REV)
R/W
0011h
C_REV[7:0] = 0Ah
C_REV[15:8] = 0Bh
8.5.6
SPI TEST REGISTER (SPI_TEST) (UPD360-C ONLY)
Address:
000Eh
Size:
.
Bits
Description
Type
Default
7:0
SPI Test (SPI_TEST)
This register is used by the host to determine when the chip has come out of
powerdown when waking it via the SPI interface.
RO
FDh
DS00002084C-page 44
2016-2017 Microchip Technology Inc.
UPD360
8.5.7
INTERRUPT STATUS REGISTER (INT_STS)
Address:
0010h
Size:
16 bits
Bits
Description
Type
Default
15
14
RESERVED
RO
RO
0h
GP_TIMER_INT
Interrupt generated when the general purpose timer underflows.
0b
This interrupt reflect that value of the GP_UFLOW bit of the General Purpose
Timer Interrupt Source Register (GP_TIMER_INT_SRC).
13
12
RESERVED
RO
RO
0b
0b
RDY_INT
Interrupt generated when the device is configured and ready for access by
host CPU after a system level reset event.
This interrupt reflect that value of the DEV_READY bit of the Hardware Con-
trol Register (HW_CTL).
11
10
RESERVED
RO
RO
-
PWR_INT
Interrupt generated power event.
0b
This interrupt is cleared via the Power Interrupt Status Register
(PWR_INT_STS).
9
8
VBUS_INT
RO
RO
0b
0b
Indicates that a change occurred in the state of VBUS Change Status Register
(VBUS_CHG_STS).
HPD_INT
Interrupt generated by the HPD detection logic.
This interrupt is cleared via the HPD Interrupt Status Register
(HPD_INT_STS).
7
6
PSW_INT
RO
RO
0b
0b
Interrupt generated by the power switch.
This interrupt is cleared via the Power Switch Interrupt Status Register
(PWR_INT_STS).
WDT_INT
Interrupt generated by watchdog timer expiration.
This interrupt is cleared via WDT_STS bit in the Watchdog Control Register
(WDT_CTL).
Note:
When a Watchdog interrupt is pending, all write operations are
blocked until the WDT_STS bit in the Watchdog Control Register
(WDT_CTL) is cleared.
5
PPC_INT
Interrupt generated by PPC.
RO
0b
This interrupt is cleared via the PPC Interrupt Status Register 1
(PPC_INT_STS1).
2016-2017 Microchip Technology Inc.
DS00002084C-page 45
UPD360
Bits
Description
Type
Default
4
MAC_INT
Interrupt generated by the PD MAC.
RO
0b
This interrupt is cleared via the corresponding PD MAC interrupt register, as
detailed in Section 11.4.3, "PD MAC Interrupt Status and Enable Registers,"
on page 153.
3
2
OCS_CMP_INT
RO
RO
0b
0b
Interrupt generated from the detection of an over-current condition.
This interrupt is cleared via OCS Comparator Change Status Register
(OCS_CMP_CHG_STS).
PIO_OVERRIDE_INT
Interrupt generated from a PIO override.
This interrupt is cleared via the PIO Override Interrupt Status Register
(PIO_OVR_INT_STS).
1
0
PIO_INT
RO
RO
0b
0b
Interrupt generated from configured PIO status change.
This interrupt is cleared via the PIO Interrupt Status Register (PIO_INT_STS).
CC_INT
Interrupt generated by Cable Plug Orientation and Detection module.
This interrupt is cleared via the CC Interrupt Status Register (CC_INT_STS).
INT_STS[7:0] = 10h
INT_STS[15:8] = 11h
DS00002084C-page 46
2016-2017 Microchip Technology Inc.
UPD360
8.5.8
INTERRUPT ENABLE REGISTER (INT_EN)
Address:
0014h
Size:
16 bits
Bits
Description
Type
Default
15
14
13
12
11
10
9
RESERVED
Interrupt Enable 13
RO
R/W
RO
0h
0b
-
When “0”, prevents generation of the respective interrupt.
RESERVED
Interrupt Enable 12
When “0”, prevents generation of the respective interrupt.
R/W
RO
1b
-
RESERVED
Interrupt Enable 10
When “0”, prevents generation of the respective interrupt.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
1b
0b
0b
0b
0b
0b
0b
Interrupt Enable 9
When “0”, prevents generation of the respective interrupt.
8
Interrupt Enable 8
When “0”, prevents generation of the respective interrupt.
7
Interrupt Enable 7
When “0”, prevents generation of the respective interrupt.
6
Interrupt Enable 6
When “0”, prevents generation of the respective interrupt.
5
Interrupt Enable 5
When “0”, prevents generation of the respective interrupt.
4
Interrupt Enable 4
When “0”, prevents generation of the respective interrupt.
3
Interrupt Enable 3
When “0”, prevents generation of the respective interrupt.
2
Interrupt Enable 2
When “0”, prevents generation of the respective interrupt.
1
Interrupt Enable 1
When “0”, prevents generation of the respective interrupt.
0
Interrupt Enable 0
When “0”, prevents generation of the respective interrupt.
INT_EN[7:0] = 12h
INT_EN[15:8] = 13h
2016-2017 Microchip Technology Inc.
DS00002084C-page 47
UPD360
8.5.9
HARDWARE CONTROL REGISTER (HW_CTL)
Address:
0018h
Size:
16 bits
Bits
Description
Type
Default
15:6
5
RESERVED
I2C_GEN_CALL_EN
RO
-
R/W
0b
0: I2C General Call address not supported.
1: I2C General Call address supported.
4
3
RESERVED
RO
-
I2C FMPLUS
R/W
1b
When set, this bit configures the I2C interface to operate in fast-mode plus
mode.
Note:
UPD360-A/UPD360-B only.
2
1
DEV_READY
R/SC
R/SC
0b
0b
When set, this bit indicates that the device has been fully configured after a
system level reset event.
PIO_UPD_REQ
When this bit is set, the PIO registers are updated from the respective
simultaneous update registers.
After the operation completes, this bit is automatically cleared.
The request will not be accepted if an override function is pending. After the
override condition is cleared by software, the update request will be
accepted. The override is cleared via respective bit of PIO Override Enable
Register (PIO_OVR_EN).
0
SRESET
SC
0b
Software reset. When set this bit initiates a chip level reset.
2
8.5.10
I C SLAVE ADDRESS REGISTER (I2C_ADDR) (UPD360-A/UPD360-B ONLY)
Address:
001Ah
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
I2C Slave Address
RO
-
6:0
R/W
Note 8-2
Defines the slave address used by the I2C controller.
The default value for this register is defined by the CFG_SEL1 pin.
Note 8-2
DS00002084C-page 48
2016-2017 Microchip Technology Inc.
UPD360
8.5.11
.
PPC STATUS REGISTER (PPC_BUSY)
Address:
001Bh
Size:
8 bits
BITS
7:1
0
DESCRIPTION
TYPE
DEFAULT
RESERVED
PPC_BUSY
RO
RO
-
0b
This bit is used to indicate when the PPC is processing a register write
request.
0b: PPC is not busy processing a register write access. A new register write
may be initiated.
1b: PPC is processing a register write access. A new register write may not
be initiated until this bit clears.
8.5.12
PIO STATUS REGISTER (PIO_STS)
Address:
0020h
Size:
16 bits
Bits
Description
Type
Default
15
PIO15
0b: PIO is low
1b: PIO is high
RO
0b
14
13
12
11
10
9
PIO14
RO
RO
RO
RO
RO
RO
RO
RO
0b
0b
0b
0b
0b
0b
0b
0b
0b: PIO is low
1b: PIO is high
PIO13
0b: PIO is low
1b: PIO is high
PIO12
0b: PIO is low
1b: PIO is high
PIO11
0b: PIO is low
1b: PIO is high
PIO10
0b: PIO is low
1b: PIO is high
PIO9
0b: PIO is low
1b: PIO is high
8
PIO8
0b: PIO is low
1b: PIO is high
7
PIO7
0b: PIO is low
1b: PIO is high
2016-2017 Microchip Technology Inc.
DS00002084C-page 49
UPD360
Bits
Description
Type
Default
6
5
4
3
2
1
0
PIO6
RO
0b
0b: PIO is low
1b: PIO is high
PIO5
0b: PIO is low
1b: PIO is high
RO
RO
RO
RO
RO
RO
0b
0b
0b
0b
0b
0b
PIO4
0b: PIO is low
1b: PIO is high
PIO3
0b: PIO is low
1b: PIO is high
PIO2
0b: PIO is low
1b: PIO is high
PIO1
0b: PIO is low
1b: PIO is high
PIO0
0b: PIO is low
1b: PIO is high
PIO_STS[0] = 20h
PIO_STS[1] = 21h
Note:
The GPO1 and GPO10 general purpose signals can only function as outputs and must be kept in a
low state coincident with de-asserting RESET_N.
Note:
Note:
GPIO0 is not available in the UPD360-C.
In Standalone DFP/UFP modes (UPD360-A/UPD360-B only), GPIOs 9-15 have alternate dedicated func-
tions, as defined in Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP
Modes," on page 11
8.5.13
PIO INTERRUPT STATUS REGISTER (PIO_INT_STS)
Address:
0022h
Size:
16 bits
Bits
Description
Type
Default
15:0
PIO_INT[15:0]
When set, a level change has occurred on PIO[15:0].
R/WC
0000h
Interrupts are cleared by writing a ‘1’ to the bit.
Note:
Writing a “1” (one) to a bit clears the bit and enables the detection of the next level transition. If not disabled
by the corresponding bit in the PIO_EN register, “1” in any bit in this register will force assertion of PIO_INT
interrupt.
DS00002084C-page 50
2016-2017 Microchip Technology Inc.
UPD360
8.5.14
PIO INTERRUPT ENABLE REGISTER (PIO_INT_EN)
Address:
0024h
Size:
16 bits
Bits
Description
Type
Default
15:0
PIO_EN[15:0]
R/W
0h
When set, an interrupt can be generated on a state change from the corre-
sponding PIO line.
8.5.15
CONFIGURE PIOX REGISTERS (CFG_PIOX)
Address:
x=0: 0030h
x=1: 0031h
x=2: 0032h
x=3: 0033h
x=4: 0034h
x=5: 0035h
x=6: 0036h
x=7: 0037h
x=8: 0038h
x=9: 0039h
x=10: 003Ah
x=11: 003Bh
x=12: 003Ch
x=13: 003Dh
x=14: 003Eh
x=15: 003Fh
Size:
8 bits
Bits
Description
Type
Default
7
PullUpEnable
0b: No pull-up
R/W
0b
1b: Pull-up enabled.
6
5
4
3
PullDownEnable
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b: No pull-down
1b: Pull-down enabled.
FallingAlert
0b: No alert on falling edge
1b: Assert PIO_INT on falling edge
RisingAlert
0b: No alert on rising edge
1b: Assert PIO_INT on rising edge
DataOutput
0b: Inactive (low for push-pull or open-drain)
1b: Active (high for push-pull, high-z for open-drain)
Note:
The input buffer status can be determined from the respective bit
in PIO Status Register (PIO_STS).
Note:
The associated PIO output bit in the Configure PIO Output Regis-
ter (CFG_PIO_OUT) will be updated to match the value written to
this bit.
2016-2017 Microchip Technology Inc.
DS00002084C-page 51
UPD360
Bits
Description
Type
Default
2
Buffer Type
R/W
0b
When set, the output buffer for the corresponding GPIO signal is configured
as a push/pull driver.
When cleared, the corresponding GPIO signal is configured as an open-drain
driver.
1
0
Direction
R/W
R/W
0b
1b
0b: Input
1b: Output
Enable
0b: GPIO Disabled
1b: GPIO Enabled
Note:
When a GPIO is disabled, the default function, if any, will be func-
tional. All GPIOs default to being enabled and configured as inputs.
Note:
The GPO1 and GPO10 general purpose signals can only function as outputs and must be kept in a
low state coincident with de-asserting RESET_N.
Note:
Note:
GPIO0 is not available in the UPD360-C.
In Standalone DFP/UFP modes (UPD360-A/UPD360-B only), GPIOs 9-15 have alternate dedicated func-
tions, as defined in Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP
Modes," on page 11
DS00002084C-page 52
2016-2017 Microchip Technology Inc.
UPD360
8.5.16
CONFIGURE PIOX UPDATE REGISTERS (CFG_PIOX_UPD)
Address:
x=0: 0040h
x=1: 0041h
x=2: 0042h
x=3: 0043h
x=4: 0044h
x=5: 0045h
x=6: 0046h
x=7: 0047h
x=8: 0048h
x=9: 0049h
x=10: 004Ah
x=11: 004Bh
x=12: 004Ch
x=13: 004Dh
x=14: 004Eh
x=15: 004Fh
Size:
8 bits
Bits
Description
Type
Default
7
PullUpEnabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
6
5
4
3
2
1
0
PullDownEnabled
FallingAlert
RisingAlert
OutputValue
BufferType
Direction
0b
0b
0b
0b
0b
0b
0b
Enable
Note:
The GPO1 and GPO10 general purpose signals can only function as outputs and must be kept in a
low state coincident with de-asserting RESET_N.
Note:
Note:
GPIO0 is not available in the UPD360-C.
In Standalone DFP/UFP modes (UPD360-A/UPD360-B only), GPIOs 9-15 have alternate dedicated func-
tions, as defined in Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP
Modes," on page 11
2016-2017 Microchip Technology Inc.
DS00002084C-page 53
UPD360
8.5.17
PIO OVERRIDE X SOURCE SELECT REGISTERS (PIO_OVRX_SRC_SEL)
Address:
x=0: 0050h
x=1: 0051h
x=2: 0052h
x=3: 0053h
Size:
8 bits
Bits
Description
Type
Default
7:5
VBUS Threshold Select
This field selects which VBUS threshold shall be matched when selecting
VBUS_DET for override.
R/W
0h
000b: VSAFE0V_THR_MATCH
001b: VBUS0_THR_MATCH
010b: VBUS1_THR_MATCH
011b: VBUS2_THR_MATCH
1xxb: VBUS3_THR_MATCH
4:0
Override Select
This field selects the source for the respective PIO override.
R/W
0h
0h: PIO0
1h: PIO1
2h: PIO2/OCS_COMP2
3h: PIO3
4h: PIO4
5h: PIO5
6h: PIO6
7h: PIO7
8h: PIO8
9h: PIO9
Ah: PIO10
Bh: PIO11
Ch: PIO12
Dh: PIO13
Eh: PIO14
Fh: PIO15
10h: OCS_COMP1
11h: VBUS_DET
12h-1Fh: Reserved
DS00002084C-page 54
2016-2017 Microchip Technology Inc.
UPD360
8.5.18
PIO OVERRIDE MONITOR VALUE REGISTER (PIO_OVR_MON_VAL)
Address:
0054h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
PIO_MON_VAL3
RO
-
3
2
1
0
R/W
R/W
R/W
R/W
0b
0b
0b
0b
Override function 3 monitors for this value on the selected PIO.
PIO_MON_VAL2
Override function 2 monitors for this value on the selected PIO.
PIO_MON_VAL1
Override function 1 monitors for this value on the selected PIO.
PIO_MON_VAL0
Override function 0 monitors for this value on the selected PIO.
Note:
When the PIO is mapped to an OCS comparator or VBUS comparator, the monitored case is rising above/
falling below the associated threshold. Setting the override monitor value indicates that the source exceed-
ing the threshold is monitored. If the value is cleared then being below the threshold is monitored.
8.5.19
PIO OVERRIDE ENABLE REGISTER (PIO_OVR_EN)
Address:
0055h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
PIO_OVR_EN3
RO
-
3
2
1
0
R/W
R/W
R/W
R/W
0b
0b
0b
0b
When set PIO Override 3 is enabled.
PIO_OVR_EN2
When set PIO Override 2 is enabled.
PIO_OVR_EN1
When set PIO Override 1 is enabled.
PIO_OVR_EN0
When set PIO Override 0 is enabled.
2016-2017 Microchip Technology Inc.
DS00002084C-page 55
UPD360
8.5.20
PIO OVERRIDE STATUS REGISTER (PIO_OVR_STS)
Address:
0056h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
RO
-
3
2
1
0
PIO_OVR_STS3
Override function is active on the selected PIO.
RO
RO
RO
RO
0b
0b
0b
0b
Set on a match to PIO_MON_VAL3 and clears on override feature disable
PIO_OVR_EN3 =0.
PIO_OVR_STS2
Override function is active on the selected PIO.
Set on a match to PIO_MON_VAL2 and clears on override feature disable
PIO_OVR_EN2 =0.
PIO_OVR_STS1
Override function is active on the selected PIO.
Set on a match to PIO_MON_VAL1 and clears on override feature disable
PIO_OVR_EN1 =0.
PIO_OVR_STS0
Override function is active on the selected PIO.
Set on a match to PIO_MON_VAL0 and clears on override feature disable
PIO_OVR_EN0 =0.
DS00002084C-page 56
2016-2017 Microchip Technology Inc.
UPD360
8.5.21
PIO OVERRIDE INTERRUPT STATUS REGISTER (PIO_OVR_INT_STS)
Address:
0057h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
PIO_OVR_INTR3
RO
-
3
2
1
0
R/WC
0b
0b
0b
0b
This interrupt is set when override function 3 detects the programmed moni-
tored value on the selected PIO.
The interrupt persists until cleared.
PIO_OVR_INTR2
R/WC
R/WC
R/WC
This interrupt is set when override function 2 detects the programmed moni-
tored value on the selected PIO.
The interrupt persists until cleared.
PIO_OVR_INTR1
This interrupt is set when override function 1 detects the programmed moni-
tored value on the selected PIO.
The interrupt persists until cleared.
PIO_OVR_INTR0
This interrupt is set when override function 0 detects the programmed moni-
tored value on the selected PIO.
The interrupt persists until cleared.
8.5.22
PIO OVERRIDE INTERRUPT ENABLE REGISTER (PIO_OVR_INT_EN)
Address:
0058h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
PIO_OVR_INTR3
RO
0h
3
2
1
0
R/W
R/W
R/W
R/W
0b
0b
0b
0b
When ‘1’, enables the generation of this interrupt.
PIO_OVR_INTR2
When ‘1’, enables the generation of this interrupt.
PIO_OVR_INTR1
When ‘1’, enables the generation of this interrupt.
PIO_OVR_INTR0
When ‘1’, enables the generation of this interrupt.
2016-2017 Microchip Technology Inc.
DS00002084C-page 57
UPD360
8.5.23
CONFIGURE PIO OUTPUT REGISTER (CFG_PIO_OUT)
Address:
0059h
Size:
16 bits
This register enables multiple PIO output values to be updated in a single CSR write.
Bits
Description
Type
Default
15:0
CFG_PIO_OUT
R/W
0000h
When this register is written, the output values for the respective PIOs are
updated. Specifically, the DataOutput in the respective CFG_PIOx registers
are updated.
This register is not updated until the byte located at 005Ah is written by soft-
ware. This is to prevent placing externally driven components in an invalid
state while updating.
8.5.24
CONFIGURE PIO OUTPUT UPDATE REGISTER (CFG_PIO_OUT_UPD)
Address:
005Bh
Size:
16 bits
Bits
Description
Type
Default
15:0
CFG_PIO_OUTx_UPD
R/W
0000h
8.5.25
PIO OVERRIDE X OUTPUT ENABLE REGISTERS (PIO_OVRX_OUT_EN)
Address:
x=0: 0060h
x=1: 0062h
x=2: 0064h
x=3: 0066h
Size:
16 bits
Bits
Description
Type
Default
15:0
PIO_OVR_OUT_EN_X
R/W
0h
Each of the overrides has an instance of this CSR to indicate which PIO out-
puts are controlled by it. When asserted associated PIO output’s state is con-
trolled by the respective override function.
Note:
The same PIO output can be enabled by multiple overrides.
DS00002084C-page 58
2016-2017 Microchip Technology Inc.
UPD360
8.5.26
PIO OVERRIDE OUTPUT REGISTER (PIO_OVR_OUT)
Address:
0068h
Size:
16 bits
Bits
Description
Type
Default
15:0
PIO Override Output
This field defines the PIO output value to be used when the respective PIO is
enabled for override and the associated override is triggered.
R/W
0h
8.5.27
PIO OVERRIDE DIRECTION REGISTER (PIO_OVR_DIR)
Address:
006Ah
Size:
16 bits
Bits
Description
Type
Default
15:0
PIO Override Direction
This field defines the PIO direction value to be used when the respective PIO
is enabled for override and the associated override is triggered.
R/W
0h
8.5.28
PIO DEBOUNCE COUNT TEN MILLISECOND REGISTER (PIO_DEBOUNCE_10MS_COUNT)
Address:
006Ch
Size:
8 bits
Bits
Description
Type
Default
7:0
PIO_DEBOUNCE_10MS_COUNT
This register holds the 10 ms debounce counter.
R/W
0Ah
Any transition within the debounce period is suppressed. Each count corre-
sponds to 10 ms, with the default value being 100 ms.
This register is used when the debounce granularity is 10 ms.
Note:
The actual count may be either count or count-1.
2016-2017 Microchip Technology Inc.
DS00002084C-page 59
UPD360
8.5.29
PIO DEBOUNCE COUNT ONE MILLISECOND REGISTER (PIO_DEBOUNCE_1MS_COUNT)
Address:
006Dh
Size:
8 bits
Bits
Description
Type
Default
7:0
PIO_DEBOUNCE_1MS_COUNT
This register holds the 1 ms debounce counter.
R/W
0Ah
Any transition within the debounce period is suppressed. Each count corre-
sponds to 1 ms, with the default value being 10 ms.
This register is used when the debounce granularity is 1 ms.
Note:
The actual count may be either count or count-1.
8.5.30
PIO DEBOUNCE COUNT ONE MICROSECOND REGISTER
(PIO_DEBOUNCE_1US_COUNT)
Address:
006Eh
Size:
8 bits
Bits
Description
Type
Default
7:0
PIO_DEBOUNCE_1US_COUNT
This register holds the 1 us debounce counter.
R/W
0Ah
Any transition within the debounce period is suppressed. Each count corre-
sponds to 1 us, with the default value being 10 us.
This register is used when the debounce granularity is 1 us.
Note:
The actual count may be either count or count-1.
DS00002084C-page 60
2016-2017 Microchip Technology Inc.
UPD360
8.5.31
PIO DEBOUNCE STATUS REGISTER (PIO_DEBOUNCE_STS)
Address:
006Fh
Size:
8 bits
Bits
Description
Type
Default
7:1
RESERVED
RO
RO
0h
0
PIO_DB_ACT
PIO Debounce Active
0b
This bit is used to indicate that a PIO debounce is in process.
1b: PIO debounce pending
0b: PIO not pending
8.5.32
PIO DEBOUNCE ENABLE REGISTER (PIO_DEBOUNCE_EN)
Address:
0070h
Size:
32 bits
This register enables a PIO for debouncing and selects the debouncer to be used as defined below:
• 00b: Debounce disabled
• 01b: Debounce Enabled (PIO Debounce Count One Microsecond Register (PIO_DEBOUNCE_1US_COUNT))
• 10b: Debounce Enabled (PIO Debounce Count One Millisecond Register (PIO_DEBOUNCE_1MS_COUNT))
• 11b: Debounce Enabled (PIO Debounce Count Ten Millisecond Register (PIO_DEBOUNCE_10MS_COUNT))
Bits
Description
Type
Default
31:30 PIO_DB_EN15
R/W
00b
29:28 PIO_DB_EN14
27:26 PIO_DB_EN13
25:24 PIO_DB_EN12
23:22 PIO_DB_EN11
21:20 PIO_DB_EN10
19:18 PIO_DB_EN9
17:16 PIO_DB_EN8
15:14 PIO_DB_EN7
13:12 PIO_DB_EN6
11:10 PIO_DB_EN5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00b
00b
00b
00b
00b
00b
00b
00b
00b
00b
00b
00b
9:8
7:6
PIO_DB_EN4
PIO_DB_EN3
2016-2017 Microchip Technology Inc.
DS00002084C-page 61
UPD360
Bits
Description
Type
Default
5:4
3:2
1:0
PIO_DB_EN2
PIO_DB_EN1
PIO_DB_EN0
R/W
00b
R/W
R/W
00b
00b
Note:
GPIO0 is not available in the UPD360-C.
8.5.33
OCS COMPARATOR CONTROL REGISTER (OCS_CMP_CTL)
Address:
0080h
Size:
8 bits
Bits
Description
Type
Default
7
OCS_DB_ACTIVE
RO
0b
When this bit reads back 0b, the debouncer is disabled. The OCS debouncer
is enabled when it reads back 1b.
6:2
1:0
RESERVED
RO
0h
OCS Comparator Control
00b: OCS Comparator and DAC are powered down
R/W
00b
01b: OCS Comparator samples OCS_COMP1
10b: OCS Comparator samples OCS_COMP2
11b: OCS Comparator samples OCS_COMP1 and OCS_COMP2
When set to 01b or 10b, a sample is taken every 100 us. When set to 11b,
each OCS_COMPx pin is effectively sampled every 200 us.
8.5.34
OCS COMPARATOR MATCH REGISTER (OCS_CMP_MATCH)
Address:
0081h
Size:
8 bits
This bit is always cleared when OCS Comparator Control is not enabled for the respective OCS_COMP pin.
Bits
Description
Type
Default
7:2
RESERVED
RO
0h
1
OCS Comparator Match 2
When set, this bit indicates that a match has occurred and an OCS condition
RO
0b
has been detected on OCS_COMP2 pin.
0
OCS Comparator Match 1
When set, this bit indicates that a match has occurred and an OCS condition
RO
0b
has been detected on OCS_COMP1 pin.
DS00002084C-page 62
2016-2017 Microchip Technology Inc.
UPD360
8.5.35
OCS COMPARATOR CHANGE STATUS REGISTER (OCS_CMP_CHG_STS)
Address:
0082h
Size:
8 bits
Bits
Description
Type
Default
7:6
OCSx Match Valid (OCSx_MATCH_VLD)
R/WC
0b
Asserts after the OCS debouncer is first enabled, via OCS Comparator Con-
trol, and the first match becomes valid in OCS Comparator Match Register
(OCS_CMP_MATCH).
Bit 7 = OCS2_MATCH_VLD
Bit 6 = OCS1_MATCH_VLD
5:2
1:0
RESERVED
RO
0h
OCSx Change Status (OCSx_CHG_STS)
When set, each bit indicates that the respective bit in OCS Comparator Match
R/WC
00b
Register (OCS_CMP_MATCH) has changed.
Bit 1 = OCS2_CHG_STS
Bit 0 = OCS1_CHG_STS
A write of 1b clears the respective status bit.
8.5.36
OCS COMPARATOR MATCH ENABLE REGISTER (OCS_CMP_MATCH_EN)
Address:
0083h
Size:
8 bits
Bits
Description
Type
Default
7:6
OCSx Match Valid Enable (OCSx_MATCH_VLD_EN)
R/W
0b
When set, the corresponding bit in OCS Comparator Change Status Register
(OCS_CMP_CHG_STS) can cause the assertion of the OCS_CMP_INT inter-
rupt.
Bit 7 = OCS2_MATCH_VLD_EN
Bit 6 = OCS1_MATCH_VLD_EN
5:2
1:0
RESERVED
RO
0h
OCSx Comparator Match Enable (OCSx_CMP_MATCH_EN)
When set the corresponding bit in OCS Comparator Change Status Register
R/W
00b
(OCS_CMP_CHG_STS) can cause the assertion of the OCS_CMP_INT inter-
rupt.
Bit 1 = OCS2_CMP_MATCH_EN
Bit 0 = OCS1_CMP_MATCH_EN
2016-2017 Microchip Technology Inc.
DS00002084C-page 63
UPD360
8.5.37
OCS COMPARATOR X THRESHOLD REGISTERS (OCS_CMPX_THR)
Address:
x=1: 0084h
x=2: 0086h
Size:
16 bits
Bits
Description
Type
Default
15:10 RESERVED
RO
0h
9:0
OCS Comparator Threshold
The lower byte of the threshold must be written before the upper byte. The
entire 10-bit threshold is updated when the second write occurs.
R/W
0h
This has units of ~2.5V/1024.
Note:
This register shall not be modified while the OCS debouncer is
enabled.
8.5.38
OCS COMPARATOR DEBOUNCE REGISTER (OCS_CMP_DEBOUNCE)
Address:
0088h
Size:
8 bits
Bits
Description
Type
Default
7:0
OCS_CMP_DEBOUNCE
Indicates the period of time for which the OCS_COMP1 and OCS_COMP2
R/W
0Fh
inputs are debounced.
This field has units of 100 us.
Note:
This register shall not be modified while the OCS debouncer is
enabled.
8.5.39
IRQ_N PU/PD CONTROL REGISTER (IRQ_PUPD)
Address:
009Bh
Size:
8 bits
This register controls the PU and PU for the IRQ_N pin.
Bits
Description
Type
Default
7
PullUpEnable
0: No pull-up
R/W
0b
1: Pull-up enabled.
6
PullDownEnable
R/W
RO
0b
-
0: No pull-down
1: Pull-down enabled.
5:0
RESERVED
DS00002084C-page 64
2016-2017 Microchip Technology Inc.
UPD360
8.5.40
VOLTAGE REGULATOR CONTROL REGISTER (VREG_CTL)
Address:
009Ch
Size:
8 bits
Bits
Description
Type
Default
7:1
RESERVED
VREG_LOW_OVR
RO
-
1
R/W
0b
When set, the 1.8V voltage regulator is placed in low power mode whenever
both the Ring Oscillator and 48MHz Relaxation Oscillator are disabled.
Note:
Note:
It is expected tor this bit to be set in CPU companion mode.
In standalone modes, the respective OTP bit shall be set to enable
this feature and to ensure maximum power savings.
0
VREG Low Power Enable (VREG_LOW_EN)
When set, the 1.8V voltage regulator is placed in low power mode.
R/W
0b
Note:
This bit has no meaning when the VREG_LOW_OVR bit is set.
2
2
8.5.41
I C TRIM REGISTER (I C_TRIM)
Address:
009Dh
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:0
I2C_TRIM
R/W
9h
This register specifies the delay added by the I2C controller in order to meet
the tHD_DAT parameter.
This register has units of 20.8 ns.
8.5.42
GENERAL PURPOSE TIMER LOAD REGISTER (GP_TIMER_LOAD)
Address:
00A0h
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
GP Timer Load
R/W
FFFFh
This register defines the value to be loaded into the general purpose timer
from which it will count down.
The valid range for this register is 0001h - FFFFh.
This field has units of 1 ms.
Note:
Note:
Programming 0h into this register is not valid.
Software shall not change the contents of this register while the
RESET bit is set and shall wait until this bit is cleared.
2016-2017 Microchip Technology Inc.
DS00002084C-page 65
UPD360
8.5.43
GENERAL PURPOSE TIMER INTERRUPT SOURCE REGISTER (GP_TIMER_INT_SRC)
Address:
00A2h
Size:
8 bits
BITS
7:1
0
DESCRIPTION
TYPE
RO
DEFAULT
RESERVED
GP_UFLOW
-
R/WC
0b
This bit will be set when the general purpose timer underflows. The
GP_TIMER_INT interrupt in Interrupt Status Register (INT_STS) persists
until this bit is cleared.
When DIS_ON_UFLOW bit of the General Purpose Timer Control Register
(GP_TIMER_CTL) is set, the assertion of this bit is delayed until the timer is
fully disabled (100s us).
8.5.44
GENERAL PURPOSE TIMER CONTROL REGISTER (GP_TIMER_CTL)
Address:
00A3h
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7
STATUS
RO
0b
This bit indicates the operational state of the GP timer.
0: Timer is disabled and not counting
1: Timer is enabled and counting
When this bit is cleared the timer has halted operation.
6:3
2
RESERVED
RO
-
DIS_ON_UFLOW
R/W
0b
When this bit is set, the GP timer is automatically disabled upon detection
of the underflow condition. Additionally, the ENABLE bit is cleared upon
underflow detection and the assertion of GP_UFLOW will be delayed until
the GP Timer has halted operation and the STATUS bit is cleared.
1
RESET
R/SC
0b
Timer Reset. When set this bit stops the timer and resets the internal counter
to the value in the General Purpose Timer Load Register
(GP_TIMER_LOAD).
0: Timer is not in reset
1: Timer is in reset
Note:
This bit does not clear until propagation of the reset completes.
This may take 100s us.
DS00002084C-page 66
2016-2017 Microchip Technology Inc.
UPD360
BITS
DESCRIPTION
TYPE
DEFAULT
0
ENABLE
R/W
0b
Timer Enable. This bit is used to start and stop the General Purpose Timer
Load Register (GP_TIMER_LOAD). This bit does not reset the timer count.
This is automatically cleared when the DIS_ON_UFLOW bit is set.
0: Timer is disabled
1: Timer is enabled
8.5.45
GENERAL PURPOSE TIMER COUNT REGISTER (GP_TIMER_COUNT)
Address:
00A4h
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
GP Timer Counter
This register returns the current value of the general purpose timer.
RO
0h
The GP timer must be disabled before reading this register by clearing the
ENABLE bit.
2016-2017 Microchip Technology Inc.
DS00002084C-page 67
UPD360
9.0
CABLE PLUG ORIENTATION AND DETECTION
This section details the functions that control and monitor the CC pins, monitor the VBUS_DET pin, control the VCONN
FETs, and sample the CFG_SEL0 and CFG_SEL1 pins.
9.1
CC Comparator
The device integrates a comparator and DAC circuit to implement Type-C attach and detach functions. It supports up
to eight programmable thresholds for attach detection between UFP and DFP. When operating as a UFP, the device
supports detecting changes in the DFP’s advertised thresholds to determine current sourcing capability. The default
nominal values for the thresholds detected by the CC comparators are:
• 0.20 V
• 0.40 V
• 0.66 V
• 0.80 V
• 1.23 V
• 1.60 V
• 2.60 V
• 3.0 V Proprietary Mode
TABLE 9-1:
Parameter
CABLE DETECT SUMMARY
Threshold CSR
Description
Min
Typ
Max
DFP_ACT_DEF
CC_THR0
Detecting an active cable when configured
as DFP and advertising default USB current.
0.20 V
UFP_DFP_DEF
CC_THR0
Detecting DFP attach when configured as
UFP and DFP is advertising default USB
current.
0.20 V
DFP_ACT_1A5
UFP_DFP_1A5
DFP_ACT_3A0
UFP_DFP_3A0
DFP_UFP_DEF
DFP_UFP_1A5
DFP_UFP_3A0
CC_THR1
CC_THR2
CC_THR3
CC_THR4
CC_THR5
CC_THR5
CC_THR6
Detecting an active cable when configured
as DFP and advertising 1.5A.
0.40 V
0.66 V
0.80 V
1.23 V
1.60 V
1.60 V
2.60 V
Detecting DFP attach when configured as
UFP and DFP is advertising 1.5A.
Detecting an active cable when configured
as DFP and advertising 3.0A.
Detecting DFP attach when configured as
UFP and DFP is advertising 3.0A.
Detecting UFP attach when configured as
DFP advertising default USB current.
Detecting UFP attach when configured as
DFP advertising 1.5A.
Detecting UFP attach when configured as
DFP advertising 3.0A.
DS00002084C-page 68
2016-2017 Microchip Technology Inc.
UPD360
The following tables summarize the expected thresholds to be matched in the CCx Match Registers (CCx_MATCH) for
various configurations. Refer to the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) for the debouncer mask
used in these configurations.
TABLE 9-2:
DFP CC MATCH SUMMARY
CC
CC
CC
CC
CC
CC
CC
CC
CC State
THR0
THR1
THR2
THR3
THR4
THR5
THR6
THR7
Advertise Default USB Current and
connected to powered cable
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Advertise 1.5 A and connected to
powered cable
0
0
1
0
0
1
0
0
0
Advertise 3.0 A and connected to
powered cable
Advertise Default USB Current and
connected to UFP
Advertise 1.5 A and connected to
UFP
Advertise 3.0 A and connected to
UFP
Advertise Default USB Current and
no connect (vOpen)
Advertise 1.5 A and no connect
(vOpen)
Advertise 3.0 A and no connect
(vOpen)
Proprietary Mode and no connect
(vOpen)
TABLE 9-3:
UFP CC MATCH SUMMARY
CC
CC_
CC
CC
CC
CC
CC
CC
CC State
THR0
THR1
THR2
THR3
THR4
THR5
THR6
THR7
Powered cable detected.
No Connect (SNK.Open)
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFP Connected and advertising
default USB current
DFP Connected and advertising 1.5
A
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
DFP Connected and advertising 3.0
A
DFP Connected and advertising pro-
prietary current
The following examples illustrate the rationale behind the expected matches in the previous tables.
DFP: Advertise 1.5 A and connected to powered cable, UFP not attached
In this scenario the DFP is advertising 1.5 A and connected to a powered cable. The UFP is not attached. The vRd value
measured will be less than 0.35V per specification.
In this configuration the following thresholds are enabled for matching:
• CC_THR1 (DFP_ACT_1A5)
2016-2017 Microchip Technology Inc.
DS00002084C-page 69
UPD360
• CC_THR5 (DFP_UFP_1A5)
The value programmed into CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Regis-
ters (CCx_MATCH_EN) would therefore be 0x22.
Since the vRd is less than 0.35V no threshold matches would be detected on CCx Match Registers (CCx_MATCH) or
CCx Change Status Registers (CCx_CHG_STS).
DFP: Advertise 3.0 A and connected to UFP
In this scenario the DFP is advertising 3.0 A and connected to a UFP. The vRd value measured will be > 0.85V and <
2.45V.
In this configuration the following thresholds are enabled for matching:
• CC_THR3 (DFP_ACT_3A0)
• CC_THR6 (DFP_UFP_3A0)
The value programmed into CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Regis-
ters (CCx_MATCH_EN) would therefore be 0x44.
In this case only CC_THR3 would be matched. Bit 3 would be set in both CCx Match Registers (CCx_MATCH) or CCx
Change Status Registers (CCx_CHG_STS) after the debounce interval.
UFP: Connected to DFP advertising 3.0 A
In this case the UFP is connected to a DFP advertising 3.0A. The vRd value measured will be > 1.3V and < 2.04 V.
In this configuration the following thresholds are enabled for matching:
• UFP_DFP_DEF (CC_THR0)
• UFP_DFP_1A5 (CC_THR2)
• UFP_DFP_3A0 (CC_THR4)
The value programmed into CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Regis-
ters (CCx_MATCH_EN) would therefore be 0x15.
In this case all three thresholds would be matched since the value of vRd must exceed CC_THR4 which is 1.23V. Bits
0, 2 and 4 would be set in both CCx Match Registers (CCx_MATCH) or CCx Change Status Registers (CCx_CH-
G_STS).
9.2
DFP Operation
The device implements current sources to advertise current charging capabilities on both CC pins when operating as a
DFP.
When a UFP connection is established, the current driven across the CC pins creates a voltage across the UFP’s Rd
pull-down that can be detected by the integrated CC comparator. The voltages monitored are summarized in Table 9-
4. When connected to an active cable, an alternative pull-down (Ra) appears on the CC pin.
The DFP may provide the advertised VBUS power via the integrated Port Power Controller (PPC).
The DFP also integrates two 5V FETs for implementing the VCONN function. This is further discussed in Section 9.7,
"VCONN Operation".
TABLE 9-4:
CC1 CC2
SOURCE DETECTION
Connection State
CC Comparator State
VBUS VCONN
Open Open Nothing Attached
Rd Open UFP Attached
Open Rd UFP Attached
Ra Open Powered Cable, No UFP attached
Monitor both CC pins for attach
Monitor CC1 for detach
Off
On
On
Off
Off
Off
Off
Off
Monitor CC2 for detach
Monitor CC2 for UFP attach.
Monitor CC1 for cable detach.
Open Ra
Powered Cable, No UFP attached
Monitor CC1 for UFP attach.
Monitor CC2 for cable detach.
Off
Off
DS00002084C-page 70
2016-2017 Microchip Technology Inc.
UPD360
TABLE 9-4:
CC1 CC2
Ra
SOURCE DETECTION (CONTINUED)
Connection State
CC Comparator State
VBUS VCONN
Rd
Ra
Powered Cable, UFP attached
Monitor CC2 for UFP detach.
CC1 is not monitored for detach.
On
On
Rd
Powered Cable, UFP attached
Monitor CC1 for UFP detach.
On
On
CC2 is not monitored for detach.
Rd
Ra
Rd
Ra
Debug accessory mode attached
Audio accessory mode attached.
Monitor both CC pins for detach
Monitor both CC pins for detach
Off
Off
Off
Off
9.2.1
RP CURRENT SOURCES
In order to advertise the current charging capabilities of the device via the integrated port power controller or external
power circuit, Rp current sources are used. The current source can be selected by software using CC1 RP Value and
CC2 RP Value in the CC Control Register (CC_CTL). Table 9-5 summarizes the values supported by the current
sources in regards to the programmed value.
TABLE 9-5:
RP CURRENT SOURCES
Current source
(1.7V to 5.5V)
DFP Advertisement
RPx Value
Disabled
00b
01b
10b
11b
Default USB Power
80 uA +/-20%
180 uA +/-8%
330 uA +/-8%
1.5A @ 5V
3.0A @ 5V
The current source coupled with the CC pins for RP advertisement is also used for sampling the CFG_SEL0 and CFG_-
SEL1 pins. When either of the CFG_SEL0/CFG_SEL1 pins are sampled, current is steered away from the CC pins and
no RP value is advertised. See the VBUS Comparator Control field in VBUS Control Register (VBUS_CTL) for further
details.
2016-2017 Microchip Technology Inc.
DS00002084C-page 71
UPD360
9.2.2
SOURCE ATTACH DETECTION
When configured as a Source, the following sections describe the steps that are taken to determine if an attach has
occurred:
1. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.
2. Software programs the CC Comparator Control to 00b and disables the CC debouncer.
3. Software polls CC_DB_ACTIVE until it reads back to indicate the CC debouncer is inactive.
4. Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce period.
5. Software programs the VBUS Debounce Register (VBUS_DEB) as required.
6. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Reg-
isters (CCx_MATCH_EN) as required to match the thresholds of interest.
7. Software programs the CCx Sample Enable Registers (CCx_SAMP_EN) and VBUS Match Enable Register
(VBUS_MATCH_EN) to detect VBUS VSafe0v Match (VSAFE0V_THR_MATCH).
8. Software enables the CC_MATCH_VLD, CC1_MATCH_CHG and CC2_MATCH_CHG interrupt via CC Interrupt
Enable Register (CC_INT_EN).
9. Software enables the VBUS_MATCH_VLD interrupt via the Power Interrupt Enable Register (PWR_INT_EN).
Note:
Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and
a valid value is available in the CCx Match Registers (CCx_MATCH). VBUS_MATCH_VLD indicates a valid
value is available in the VBUS Match Register (VBUS_MATCH).
10. Software enables IRQ_N assertion by enabling the CC_INT, VBUS_INT and PWR_INT in the Interrupt Enable
Register (INT_EN).
11. Software programs the RP current sources via CC1 RP Value and CC2 RP Value in the CC Control Register
(CC_CTL).
12. Software programs the CC Threshold x Registers (CC_THRx), if required.
13. Software programs the CC Comparator Control to sample both CC pins and enables the CC debouncer. The
CC_DB_ACTIVE bit will assert soon after.
14. Software sets the Clock Control Register (CLK_CTL) to disable all clock sources accept for the keep alive clock.
15. When a UFP is attached an Rd pull-down, or Ra pull-down from active cable, is connected to one of the CC pins.
The CC comparator detects this.
16. Changes in state of the CC pin are recorded in the CCx Match Registers (CCx_MATCH) and CCx Change Status
Registers (CCx_CHG_STS) after the programmed debounce period.
17. CC_MATCH_VLD and CC1_MATCH_CHG or CC2_MATCH_CHG interrupt assert and CC_INT asserts which in
turn asserts IRQ_N pin. Likewise assertion of VBUS_MATCH_VLD causes PWR_INT to assert and also in turn
asserts IRQ_N.
18. Software implements a further debounce of the CC match for tCCDebounce in order to detect the attachment.
19. Software must verify, after VBUS_MATCH_VLD assertion, that the VBUS Match Register (VBUS_MATCH) indi-
cates vSafe0v is on VBUS.
20. After an attachment, software programs the device to power VBUS via the integrated PPC, if required. If the
power source is external to the device, software configures that source as required.
21. In the event that an active cable is attached, per the CCx Match Registers (CCx_MATCH), VCONN power may
be supplied by appropriately setting VCONN1 Control or VCONN2 Control in the VBUS Control Register
(VBUS_CTL).
22. CC Communication Select in the CC Control Register (CC_CTL) is set by software to appropriately connect the
baseband interface to the CC pin with the Rd pull-down.
23. The DFP may attempt to communicate with attached device utilizing the PD MAC if desired.
DS00002084C-page 72
2016-2017 Microchip Technology Inc.
UPD360
9.2.3
SOURCE DETACH DETECTION
When configured as a source, the detachment of the partner UFP is determined by monitoring the appropriate CC pin
(with the Rd pull-down) for a voltage exceeding DFP_UFP_DEF, DFP_UFP_1A5 or DFP_UFP_3A0, depending on the
charging current advertised by the device.
The following describes the steps that are taken to determine if a detach has occurred when operating in companion
mode:
APPLICATION NOTE: Software must not look at the CC detect status while a PD contract is in place, even though
the Type-C spec permits doing so, in order to avoid false-disconnects in the Attached.SNK
state during heavy PD message traffic.
APPLICATION NOTE: Software should set a 3A advertisement while it's a source and a PD contract is in place in
order to avoid false-disconnects in the Attached.SRC state during heavy PD message traffic;
a 1.5A advertisement (even though permitted by the Type-C spec) is not sufficient to avoid
this issue due to the lower vOPEN threshold. An exception to this recommendation is when
“Collision Avoidance” is implemented.
The following steps assume the CC debouncer has previously been used to detect attachment per the prior section.
1. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.
2. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to enable per
threshold debouncing. Typically this only involves disabling the thresholds not corresponding to vOPEN.
3. Software enables CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via CC Interrupt Enable Register
(CC_INT_EN).
4. Software enables IRQ_N via asserting the respective CC_INT bit in the Interrupt Enable Register (INT_EN).
5. Software programs the CC Comparator Control to sample appropriate CC pin.
6. The device samples the respective CC pin while operating off of 20 kHz clock.
7. Changes in state of the CC are reflected in the respective CCx Match Registers (CCx_MATCH) and CCx Change
Status Registers (CCx_CHG_STS).
8. CC1_MATCH_CHG, or CC2_MATCH_CHG, interrupt asserts, CC_INT asserts which in turn asserts the IRQ_N
pin.
9. Software implements a further debounce of the CC match for tCCDebounce in order to detect the detachment.
10. If VCONN is being supplied, than the VCONN FET shall be disabled in software by appropriately setting the
VCONN1 Control or VCONN2 Control in the VBUS Control Register (VBUS_CTL). In this case, software must
also discharge VCONN as defined in Section 9.7.1, "VCONN Discharge Programming Model".
11. Software disables the PPC which causes the internal 5V power switch to open if required. Power may have alter-
natively been provided by external power source.
12. Internal 100 Ohm VBUS discharge switch is closed if required.
13. Discharge switch remains closed until vSafe0V threshold is crossed.
14. If vSafe0V threshold is not crossed within VBUS Off Register (VBUS_OFF) which asserts VBUS Discharge Error
interrupt and asserts IRQ_N pin.
Note:
Occurrence of VBUS Discharge Error interrupt indicates a potentially catastrophic system power issue.
15. Internal discharge switch is opened.
16. The part is configured by software to detect a UFP attach. The 48 MHz oscillator is disabled. Only the keep-alive
clock remains enabled.
2016-2017 Microchip Technology Inc.
DS00002084C-page 73
UPD360
9.3
UFP Operation
When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from
the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported
by the DFP.
9.3.1
SINK ATTACH DETECTION
The following steps illustrate how the device may be programmed to detect an attachment when operating as a Sink.
The following discussion does not cover dead-battery cases, which are described in Section 9.6, "Dead Battery".
1. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.
2. Software programs the CC Comparator Control to 00b and disables the CC debouncer.
3. Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer.
4. Software polls CC_DB_ACTIVE and VBUS_DB_ACTIVE until they read back 0b to indicate that the CC
debouncer and VBUS debouncer are inactive. Software programs the Match Debounce Register (MATCH_DEB)
as required for the tPDDebounce interval.
5. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to match the
thresholds of interest.
6. Software programs the CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL)
to advertise trimmed Rd.
7. Software enables CC_MATCH_VLD, CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt
Enable Register (CC_INT_EN).
8. Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid
value is available in the CCx Match Registers (CCx_MATCH).
9. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to enable the
respective threshold(s) debouncing.
10. Software enables VBUS_INT to detect VBUS by configuring the VBUS Match Register (VBUS_MATCH).
11. Software enables VBUS_MATCH_VLD by configuring the Power Interrupt Enable Register (PWR_INT_EN).
12. Software enables IRQ_N via configured respective bits, for CC_INT, PWR_INT and VBUS_INT, in the Interrupt
Enable Register (INT_EN).
13. Software programs the CC Comparator Control to sample both CC pins.
14. Software programs VBUS Comparator/DAC to detect vSafe5V via the VBUS Comparator Control in the VBUS
Control Register (VBUS_CTL) and setting VBUS_THR0 and VBUS_THR1 via the VBUS Threshold x Registers
(VBUS_THRx).
15. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via Clock Control Register
(CLK_CTL) to save power.
16. Upon connection to a partner DFP VBUS is powered to 5V.
17. After the programmed debounce interval, the respective CCx Change Status Registers (CCx_CHG_STS) is
updated and the respective CC1_MATCH_CHG or CC2_MATCH_CHG interrupt asserts which in turn asserts
CC_INT which in turn asserts IRQ_N.
Note:
Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and
a valid value is available in the CCx Match Registers (CCx_MATCH).
18. VBUS is detected by the VBUS_DET comparator and debounced for the period defined by the VBUS Debounce
Register (VBUS_DEB). The VBUS_INT interrupt asserts which in turn asserts IRQ_N.
Note:
Assertion of VBUS_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed
and a valid value is available in the VBUS Match Register (VBUS_MATCH).
19. Software must debounce the CC match for tCCDebounce and VBUS for the PD Debounce Register (PD_DEB)
in order to detect the attach condition.
20. After attachment, software configures CC Communication Select in the CC Control Register (CC_CTL) to appro-
priately connect the baseband interface to the CC with the Rp pull-up if PD communication is desired.
21. DFP may communicate with the device.
DS00002084C-page 74
2016-2017 Microchip Technology Inc.
UPD360
9.3.2
SINK DETACH DETECTION
The DFP detach is detected by the removal of VBUS. The VBUS comparator must always be enabled for the UFP to
detect this condition.
1. Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer.
2. Software polls VBUS_DB_ACTIVE until it reads back 0b to indicate that the VBUS debouncer is inactive.
3. Software programs the VBUS Debounce Register (VBUS_DEB) as required.
4. Software programs the CCx Sample Enable Registers (CCx_SAMP_EN) as required to enable the respective
threshold(s) debouncing.
5. Software enables VBUS_INT, which is then used to detect VBUS, via the VBUS Match Enable Register (VBUS_-
MATCH_EN).
6. Software enables IRQ_N by configuring the respective bit for VBUS_INT in the Interrupt Enable Register
(INT_EN).
Note:
VBUS_THR0 and VBUS_THR1 are adjusted via the VBUS Threshold x Registers (VBUS_THRx) to
vSafe5V, if required.
7. Software enables the VBUS Comparator/DAC via the VBUS Comparator Control bit in the VBUS Control Regis-
ter (VBUS_CTL).
8. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via the Clock Control Register
(CLK_CTL) to save power.
9. DFP removes VBUS.
10. After the VBUS debounce period, the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register
(VBUS_CHG_STS) are updated. The VBUS_INT interrupt asserts which in turn asserts IRQ_N.
11. Software continues to monitor VBUS to determine if it stays below vSafe5V for a duration of tPdDebounce.
9.4
DRP Operation
This section describes a usage of the device for implementing a DRP attach. In this configuration, software utilizes the
device to alternate between a Source and Sink advertisement with an interval of tDRP per the USB Type-C Specifica-
tion.
The steps for initially configuring the device to advertise Source capabilities follows the steps defined in Section 9.2.2,
"Source Attach Detection". Software must also implement the tDRP timer. If a Sink is not detected within this time, soft-
ware shall change the device’s role to Sink and again attempt an attach detection.
1. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.
2. Software programs the CC Comparator Control to 00b and disables the CC debouncer.
3. Software polls CC_DB_ACTIVE until it reads back to indicate the CC debouncer is inactive.
4. Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce period.
5. Software programs the CC Threshold x Registers (CC_THRx) if required.
6. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Reg-
isters (CCx_MATCH_EN) as required to match the thresholds of interest.
7. Software enables the CC_MATCH_VLD, CC1_MATCH_CHG and CC2_MATCH_CHG interrupts via the CC
Interrupt Enable Register (CC_INT_EN).
8. Software enables IRQ_N assertion by enabling the CC_INT in the Interrupt Enable Register (INT_EN).
9. Software programs the RP current sources via the CC1 RP Value and CC2 RP Value in the CC Control Register
(CC_CTL).
10. Software programs the CC Comparator Control to sample both CC pins and enable the CC debouncer. The
CC_DB_ACTIVE bit will assert soon after.
11. Software sets the Clock Control Register (CLK_CTL) to disable all clock sources accept for the keep alive clock.
Note:
Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and
a valid value is available in the CCx Match Registers (CCx_MATCH).
If after time tDRP an attachment is not detected, software shall configure the device to be a Sink and attempt to detect
the presence of a Source. This is similar to the steps defined in Section 9.3.1, "Sink Attach Detection".
1. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator
2. Software programs the CC Comparator Control to 00b and disables the CC debouncer.
2016-2017 Microchip Technology Inc.
DS00002084C-page 75
UPD360
3. Software polls CC_DB_ACTIVE until it reads back 0b to indicate that the CC debouncer is inactive.
4. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to match the
thresholds of interest.
5. Software programs detection for vSafe5V by setting VBUS_THR0 and VBUS_THR1 in the VBUS Threshold x
Registers (VBUS_THRx). The CCx Sample Enable Registers (CCx_SAMP_EN) is programmed debounce these
thresholds.
6. Software programs CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL) to
advertise trimmed Rd.
7. Software enables the CC_MATCH_VLD, CC1_MATCH_CHG or CC2_MATCH_CHG interrupts via the CC Inter-
rupt Enable Register (CC_INT_EN).
8. Software enables VBUS_MATCH_VLD by configuring the Power Interrupt Enable Register (PWR_INT_EN).
9. Software enables IRQ_N via the configured respective bits, for CC_INT, PWR_INT and VBUS_INT, in the Inter-
rupt Enable Register (INT_EN).
10. Software programs the CC Comparator Control to sample both CC pins.
11. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via the Clock Control Register
(CLK_CTL) to save power.
If after time tDRP an attachment is not detected, software shall configure the device to be a Source and attempt to detect
the presence of a Sink.
Note:
Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and
a valid value is available in CCx Match Registers (CCx_MATCH).
Note:
Assertion of VBUS_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed
and a valid value is available in VBUS Match Register (VBUS_MATCH).
9.5
Collision Avoidance
An alternative mode of operation is required to enable the CC detection circuit to facilitate software implementation of
collision detection which was incorporated into version 3.0 of the USB PD Specification.
In order to avoid message collisions due to asynchronous Messaging (AMS) sent from the Sink, the Source sets Rp to
SinkTxOk (3A@5V) to indicate to the Sink that it is OK to initiate an AMS. When the Source wishes to initiate an AMS
it sets Rp to SinkTxNG (1.5A@5V). When the Sink detects that Rp is set to SinkTxOk it may initiate an AMS. When the
Sink detects that Rp is set to SinkTxNG it shall not initiate an AMS and shall only send Messages that are part of an
AMS the Source has initiated.
When operating as a Sink, a mechanism is required for quickly determining whether the Source is advertising SinkTxNG
or SinkTxOK on Rp.
A collision avoidance mechanism exists to enable software to instruct the device to sample only a single threshold on
a single CC pin. This results in a cycle through both thresholds taking only 100 us, making it easier for software to meet
the timing constraints mandated by SinkTxOk in the specification. Two CCx Sample Enable Registers (CCx_SAMP_EN)
are provided to enable software to specify which subsets of the CC thresholds shall be sampled via setting the respec-
tive bit. In the case of collision avoidance, only the threshold corresponding to SinkTxOK shall be set on the connected
CC pin. This corresponds to UFP_DFP_3A0 (CC_THR4). The CC Comparator Control field in CC Control Register
(CC_CTL) shall be set to the CC pin utilized for PD communication.
In order to prevent false positive detection of SinkTXOK when a PD packet is being transmitted or received, a debounce
value in the order to 7 ms would need to be programmed into Match Debounce Register (MATCH_DEB). Such a large
value would impair the ability of software, when operating as Sink, to detect SinkTXOK and transmit a PD message
within the time defined in the PD specification by SinkTxTime. The BLK_PD_MSG bit in CC Hardware Control Register
(CC_HW_CTL) has been incorporated to handle the above scenario and enable software to program a sub millisecond
debounce value. A minimum value of 100 us shall be used for the Match Debounce Register (MATCH_DEB) when using
this mode of operation.
The below sequence illustrates the steps to enable Collision Avoidance for a Sink. This sequence is used after a con-
nection and PD contract has been established.
DS00002084C-page 76
2016-2017 Microchip Technology Inc.
UPD360
Note:
The units of the Match Debounce Register (MATCH_DEB) is determined by MATCH_DB_UNITS bit in CC
Hardware Control Register (CC_HW_CTL). When this bit is clear, the units are 1.6 ms. When this bit is set
the units are 100 us.
1. Sink establishes connection with Source and a PD contract is negotiated. Sink wants to transmit AMS to Source.
2. Via the CC Hardware Control Register (CC_HW_CTL), the MATCH_DB_UNITS is set to 1b to utilize 100 us units
for the CC match debouncer. The BLK_PD_MSG bit is set to filter PD traffic from the debouncer.
3. Software sets the Match Debounce Register (MATCH_DEB) to 400 us by writing four into the register.
4. Software configures CC_THR4 to enable interrupt assertion via the CCx Match Enable Registers (CCx_-
MATCH_EN).
5. Software configures CC_THR4 for sampling via the CCx Sample Enable Registers (CCx_SAMP_EN).
6. Via the CC Control Register (CC_CTL), the CC Comparator Control selects the CC pin connected to the Source’s
Rp.
7. Software waits for indication that Source’s Rp is SinkTxOK via a match detected on CC_THR4.
8. Software initiates transmission of PD message to Source.
APPLICATION NOTE: Software must guarantee that a sufficient gap exists in between consecutively transmitted
PD messages to enable the source RP value to settle on the CC line. Studies by USB-IF
members have showed the settling time may take in excess of 40 us.
9.6
Dead Battery
Two variations of the Rd resistor are implemented: Rd (Dead Battery) and Rd (Trimmed). The CC1_DB_EN and CC2_D-
B_EN pins exist to determine the operation of the CC pins in dead battery conditions and are to be connected externally
via the PCB to the respective CC pin. The CC pins are configured to present either Hi-Z or an untrimmed Rd pull-down
resistance when connected to a DFP advertising a pull-up resistance.
Figure 9-1 illustrates the configuration for supporting dead battery cases via hair pining CCx_DB_EN and CCx together
on the PCB. The UFP pull-up activates the FET in series with RD_DB and enables the untrimmed dead battery pull-
down.
FIGURE 9-1:
CC RD (DEAD BATTERY)
UFP
DFP
Rp
CC_DB_ENx
CCx
RD_TRIM
5.1 KW
50 MW
RD_DB
5.1 KW
Hi-Z
EN_RD_TRIM
Hi-Z
EN_RD_DB_N
Figure 9-2 illustrates operation after the UFP has been powered over VBUS by the DFP. After the device is powered,
EN_RD_DB asserts by default to keep the RD_DB pull-down activated.
2016-2017 Microchip Technology Inc.
DS00002084C-page 77
UPD360
Upon powering the host CPU, software simultaneously deasserts EN_RD_DB and asserts EN_RD_TRIM. Going for-
ward the device presents RD_TRIM.
FIGURE 9-2:
CC RD (TRIM)
UFP
DFP
Rp
CC_DB_ENx
CCx
RD_TRIM
5.1 KW
50 MW
RD_DB
5.1 KW
EN_RD_TRIM
EN_RD_DB_N
The Rd resistor presented, trimmed or untrimmed, is controlled by the CC1 Pull-Down Value and CC2 Pull-Down Value
in the CC Control Register (CC_CTL). These register fields serve the basis for the EN_RD_TRIM and EN_RD_DB_N
control signals depicted.
9.7
VCONN Operation
VCONN is a 5V supply that is used to power circuitry in the USB Type-C plug, which is required to implement Electron-
ically Marked Cables. By default, the DFP always sources VCONN when connected to an active cable. However, this
may be changed by software by using PD VCONN_SWAP.
The VCONN FETs are enabled/disabled by software via the VCONN1 Control and VCONN2 Control control bits in the
CC Control Register (CC_CTL).
In standalone DFP mode, the device independently enables/disables the VCONN FETs. This mode is intended for con-
figurations where no host CPU is available or the CPU is not capable of managing VCONN. The Standalone Operation
bit in the CC Hardware Control Register (CC_HW_CTL) enables this mode of operation.
APPLICATION NOTE: It is not envisioned to ever enable both FETs simultaneously.
VCONN is monitored for an over current condition via an internal monitoring circuit. A VCONN over current condition is
recognized when the event persists for a time longer than specified in the VCONN OCS and Back-Drive Debounce Reg-
ister (VCONN_DEB). VCONN OCS monitoring is enabled via the VCONN OCS Enable bit in the VBUS Control Register
(VBUS_CTL).
When an over-current VCONN event is detected, the VCONN Discharge Error (VCONN_DISCH_ERR) interrupt in the
Power Interrupt Status Register (PWR_INT_STS) asserts. The device may be configured to automatically disable the
VCONN FET upon detection of a CC1 Back-Drive Error/CC2 Back-Drive Error or VCONN Discharge Error (VCONN_-
DISCH_ERR). In the event of the detection of a debounced over-current VCONN event, the enabled VCONN FET will
be disabled. The OCS event also results in an automatic disablement of the respective VCONN1 Control and VCONN2
Control control bits in the CC Control Register (CC_CTL).
9.7.1
VCONN DISCHARGE PROGRAMMING MODEL
Software may use the following programming model for implementing VCONN discharge when the device is operating
as a DFP and a UFP disconnect has been detected.
This section does not apply to standalone DFP operation.
1. Software determines the attached UFP has disconnected and disconnects the VCONN FET.
2. Software disables monitoring the CC thresholds corresponding to the attached CC pin.
DS00002084C-page 78
2016-2017 Microchip Technology Inc.
UPD360
3. The Rp current sources are disabled on both CC pins via CC1 RP Value or CC2 RP Value.
4. The Ra pull-down on the CC pin previously sourcing VCONN is selected via CC1 Pull-Down Value or CC2 Pull-
Down Value. This initiates the VCONN discharge.
5. Software sets the CC threshold 0 to 150 mv (41d), via the CC Threshold x Registers (CC_THRx), which is the
VCONN discharge threshold.
6. Software programs 01h into the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN).
7. Software programs 01h into the CCx Match Enable Registers (CCx_MATCH_EN).
8. Software enables CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt Enable Register
(CC_INT_EN).
9. Via the CC Control Register (CC_CTL), the CC Comparator Control selects the CC pin that was sourcing
VCONN.
10. Changes in state of the CC pin are recorded in CCx Match Registers (CCx_MATCH) and CCx Change Status
Registers (CCx_CHG_STS) after the programmed debounce period.
11. After VCONN discharges below 150mv, IRQ_N asserts which indicates VCONN has been discharged. IRQ_N
assertion of CC_MATCH_VLD with no threshold matches is also indicative of a complete discharge.
12. After the discharge has been completed, the device is in the Unattached.SRC state.
Note:
Software should implement a timer to indicate a VCONN discharge error. This may be implemented using
the General Purpose Timer. While there is no specific requirement in the Type-C specification for a maxi-
mum discharge time
Note:
After the UFP disconnect is detected, firmware must disconnect the VCONN supply within tVconnOff (35
ms) per release 1.1 of the Type-C specification.
9.8
VBUS Detection
The device implements a comparator for determining when VBUS is within a programmed range, vSafe5V, or vSafe0v.
VBUS is divided down externally via a 1:9 resistor divider to generate VBUS_DET. VBUS_DET is compared with an 8-
bit threshold generated by an integrated DAC. The comparator is also shared by the CFG_SEL0 and CFG_SEL1 pins
which are sampled automatically after a system reset
Figure 9-3 illustrates the VBUS_DET circuit. In a typical use case, VBUS_DET thresholds are programmed to track the
following voltage ranges as defined in Table 9-6.
Note:
Table 9-6 illustrates the values of VBUS_DET utilizing +/-1% accurate resistors where R1 is 10K Ohms and
R2 is 90 kOhms.
FIGURE 9-3:
VBUS_DET COMPARATOR
VBUS
15 uA
ZTC
CFG_SEL1
R2
CFG_SEL0
VBUS_DET
VBUS_MATCH/
CFG_MATCH
10-bits
DAC
R3
R4
R1
VBUS and
CFG_SEL
Threshold
Generation
Bandgap
Reference
20 KHz Clock
For a DFP, the VBUS comparator is useful to detect when VBUS is within the desired range per PD negotiations. This
is the case when VBUS is generated by a source external to the device.
2016-2017 Microchip Technology Inc.
DS00002084C-page 79
UPD360
For a UFP, the VBUS comparator is required to determine when a DFP is attached or detached. It may also use the
comparator to determine when VBUS is within a new voltage range negotiated via PD.
TABLE 9-6:
VBUS
VBUS DETECTION THRESHOLDS
Range
VBUS_DET
Comments
21.5
18.5
13.1
10.9
8.9
2.11
1.82
1.29
1.07
0.88
0.69
0.51
0.33
0.08
20
12
8
7.1
5.5
5
vSafe5V
vSafe0V
3.67
0.8
0.8
If supported, the ranges 8V, 12V and 20V may be programmed in VBUS Threshold 2 and VBUS Threshold 3 registers
(see VBUS Threshold x Registers (VBUS_THRx)). Likewise 5V range, vSafe5v, can be programmed in VBUS Thresh-
old 0 and VBUS Threshold 1 registers.
The threshold for vSafe0V is programmable via the VBUS VSafe0V Threshold Register (VSAFE0V_THR).
VBUS_DET monitoring logic operates off of the 20 KHz oscillator which cycles through each threshold. Including
vSafe0v, a total of five values are compared.
Results of the comparison adjust the respective bits of the VBUS Match Register (VBUS_MATCH) and VBUS Change
Status Register (VBUS_CHG_STS) after a debounce period defined in VBUS Debounce Register (VBUS_DEB).
The VBUS Match Register (VBUS_MATCH) indicates when the value on VBUS_DET is higher than the corresponding
programmed threshold and can therefore be used to determine is VBUS is in the desired range.
A change in the state of the VBUS Match Register (VBUS_MATCH) may trigger assertion of the IRQ_N pin if appropri-
ately configured in the Power Interrupt Status Register (PWR_INT_STS).
The VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) is functionality equivalent to the CCx Debounce
Clear Enable Registers (CCx_DBCLR_EN), but it applies to the VBUS debouncer. Software programs the VBUS
Debounce Clear Enable Register (VBUS_DBCLR_EN) as required to enable debouncing the thresholds of interest.
The following example illustrates the programming model when it is desired to move VBUS from 5V to 20V after PD
contract negotiation. Initially the VBUS de-bouncer is enabled and VSafe5v, VBUS_THR0 and VBUS_THR1, is sam-
pled. VBUS_THR2 and VBUS_THR3 have an initial value in excess of 5V such as 25V. See Section 9.12.24 for details
on the VBUS_THRx registers.
1. Software programs the VBUS Match Enable Register (VBUS_MATCH_EN) to include new thresholds
(VBUS_THR2 and VBUS_THR3).
2. Software programs the VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) as required to enable per
threshold debouncing.
3. Software programs new thresholds for 20V in VBUS_THR2 and VBUS_THR3 (e.g. 18.5V and 21.5V). This oper-
ation restarts the VBUS debouncer.
4. Software waits until IRQ_N asserts.
5. Software confirms the VBUS_MATCH_VLD bit is set.
6. Software reads the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register (VBUS_CH-
G_STS).
7. If VBUS Change Status Register (VBUS_CHG_STS) is non-zero, software clears the status bits.
Note:
If no bits are set in the VBUS Match Register (VBUS_MATCH), after VBUS_MATCH_VLD asserts, then
the voltage observed on VBUS is less than VSafe0V.
8. Future changes in VBUS results in IRQ_N asserting with VBUS Match Register (VBUS_MATCH) and VBUS
Change Status Register (VBUS_CHG_STS) being appropriately updated.
DS00002084C-page 80
2016-2017 Microchip Technology Inc.
UPD360
9.8.1
CONFIGURATION SELECTION
The CFG_SEL0 and CFG_SEL1(UPD360-A/UPD360-B only) pins share the comparator with VBUS as shown in
Figure 9-3. Each CFG_SELx pin is connected to a resistor divider, typically pulled up to VDDIO. After a system level
reset (POR, RESET_N, Software Reset), both CFG_SELx pins are automatically sampled to configure the device. The
CFG_SELx Match Registers (CFG_SELx_MATCH) are updated automatically and the device configures itself accord-
ingly if standalone mode is detected.
The various resistor settings for the CFG_SEL0 and CFG_SEL1 pins are detailed in Table 9-7 and Table 9-8, respec-
tively.
Note:
For additional information on device resets, refer to Section 7.7, "Reset Operation," on page 34.
TABLE 9-7:
CONFIGURATION SELECT 0 (CFG_SEL0) SETTINGS
Description
Resistor
(+/-1%)
CFG_SEL0_MATCH
Register
GND
Standalone DFP / USB58xx/USB59xx Companion DFP
0000h
Device operates in standalone DFP mode (UPD360-A/UPD360-B only) for
applications where an I2C connection to the host is not be present.
The PWR_CAPx pins are used to select the USB Type-C™ current provided.
0.475 K
Standalone UFP / USB58xx/USB59xx Companion UFP
0001h
Device operates in standalone UFP mode (UPD360-A/UPD360-B only) for
applications where an I2C connection to the host is not be present.
0.953 K
1.43 K
1.87 K
2.37 K
2.87 K
3.32 K
3.83 K
4.22 K
4.75 K
5.23 K
5.62 K
6.19 K
6.65 K
7.15 K
>7.15 K
I2C/SPI Companion Mode A (TBD)
I2C/SPI Companion Mode B (TBD)
I2C/SPI Companion Mode C (TBD)
I2C/SPI Companion Mode D (TBD)
I2C/SPI Companion Mode E (TBD)
I2C/SPI Companion Mode F (TBD)
I2C/SPI Companion Mode G (TBD)
I2C/SPI Companion Mode H (TBD)
I2C/SPI Companion Mode I (TBD)
I2C/SPI Companion Mode J (TBD)
I2C/SPI Companion Mode K (TBD)
I2C/SPI Companion Mode L (TBD)
I2C/SPI Companion Mode M (TBD)
I2C/SPI Companion Mode N (TBD)
I2C/SPI Companion Mode O (TBD)
0003h
0007h
000Fh
001Fh
003Fh
007Fh
00FFh
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
7FFFh
FFFFh
Note:
Any CFG_SEL0 value other than GND or 10.5K will select the I2C/SPI Companion mode.
2016-2017 Microchip Technology Inc.
DS00002084C-page 81
UPD360
2
TABLE 9-8:
CONFIGURATION SELECT 1 (CFG_SEL1) I C ADDRESS SETTINGS
(UPD360-A/UPD360-B ONLY)
Resistor
(+/-1%)
CFG_SEL1_MATCH
Register
Description
GND
I2C Slave Address = 1011_111
I2C Slave Address = 1011_110
I2C Slave Address = 1011_101
I2C Slave Address = 1011_100
I2C Slave Address = 1101_011
I2C Slave Address = 1101_010
I2C Slave Address = 1101_001
I2C Slave Address = 1101_000
I2C Slave Address = 1110_111
I2C Slave Address = 1110_110
I2C Slave Address = 1110_101
I2C Slave Address = 1110_100
I2C Slave Address = 1110_001
I2C Slave Address = 1110_011
I2C Slave Address = 1110_000
I2C Slave Address = 1110_010
I2C Slave Address = 1001_000
0000h
0001h
0003h
0007h
000Fh
001Fh
003Fh
007Fh
00FFh
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
7FFFh
FFFFh
0.475 K
0.953 K
1.43 K
1.87 K
2.37 K
2.87 K
3.32 K
3.83 K
4.22 K
4.75 K
5.23 K
5.62 K
6.19 K
6.65 K
7.15 K
>7.15 K
9.9
Back-Drive Detection
Back-drive detection is implemented on both CC pins, which prevents backwards current flow. The back-drive protection
circuit is always operational and triggers when VCCx > VS.
Detection of the back-drive condition causes the CC1 Back-Drive Error or CC2 Back-Drive Error bits in the Power Inter-
rupt Status Register (PWR_INT_STS) to assert.
Hardware supports automatically disabling a VCONN FET on a CC pin in which back-drive was detected after the
debounce period specified in the VCONN OCS and Back-Drive Debounce Register (VCONN_DEB). This function is
enabled by setting CC Back-Drive Enable in VBUS Control Register (VBUS_CTL).
9.10 Standalone DFP (UPD360-A/UPD360-B Only)
9.10.1
OVERVIEW
The device supports standalone DFP operation in which no CPU is available to configure the device. A key application
for this mode is a USB Type-C DFP companion for the Microchip USB58xx/USB59xx family of USB Hubs.
9.10.2
CONFIGURATION
This mode is entered by the appropriate setting of the CFG_SEL0 and CFG_SEL1 pins. The current charge advertised
and supplied is defined by the PWR_CAP0 and PWR_CAP1 pins. The device auto configures itself after a system level
reset event.
APPLICATION NOTE: The Standalone Operation field in CC Hardware Control Register (CC_HW_CTL) may be
used to disable standalone operation.
DS00002084C-page 82
2016-2017 Microchip Technology Inc.
UPD360
9.11 Standalone UFP (UPD360-A/UPD360-B Only)
9.11.1
OVERVIEW
The device supports standalone UFP operation in which no CPU is available to configure the device. A key application
for this mode is a USB Type-C UFP companion for the Microchip USB58xx/USB59xx family of USB Hubs.
9.11.2
CONFIGURATION
This mode is entered by the appropriate setting of the CFG_SEL0 and CFG_SEL1 pins. The device auto-configures itself
after a system level reset event.
APPLICATION NOTE: The Standalone Operation field in the CC Hardware Control Register (CC_HW_CTL) may be
used to disable standalone operation.
2016-2017 Microchip Technology Inc.
DS00002084C-page 83
UPD360
9.12 Cable Orientation and Detection Registers
This section details the cable plug orientation and detection registers. For an overview of the entire device register map,
refer to Section 4.0, "Register Map," on page 19.
TABLE 9-9:
Address
SYSTEM CONTROL AND STATUS REGISTERS MAP
Register Name (Symbol)
0800h
0803h
0804h
0805h
0806h
0807h
0808h
0809h
080Ah
080Bh
CC Hardware Control Register (CC_HW_CTL)
CC Interrupt Status Register (CC_INT_STS)
CCx Change Status Registers (CCx_CHG_STS) x=1
CCx Change Status Registers (CCx_CHG_STS) x=2
CCx Match Registers (CCx_MATCH) x=1
CCx Match Registers (CCx_MATCH) x=2
VBUS Match Register (VBUS_MATCH)
VBUS Change Status Register (VBUS_CHG_STS)
Power Interrupt Status Register (PWR_INT_STS)
Debug Interrupt Status Register (DBG_INT_STS)
080Ch – 0810h Reserved for future expansion
CC Interrupt Enable Register (CC_INT_EN)
0811h
0812h
0813h
0814h
0815h
0816h
0817h
0818h
0819h
081Ah
081Bh
081Ch
081Dh
081Eh
081Fh
0820h
0822h
0824h
0826h
0828h
082Ah
082Ch
082Eh
0830h
0832h
CCx Match Enable Registers (CCx_MATCH_EN) x=1
CCx Match Enable Registers (CCx_MATCH_EN) x=2
VBUS Match Enable Register (VBUS_MATCH_EN)
Power Interrupt Enable Register (PWR_INT_EN)
Debug Interrupt Enable Register (DBG_ENT_EN)
Match Debounce Register (MATCH_DEB)
PD Debounce Register (PD_DEB)
VCONN OCS and Back-Drive Debounce Register (VCONN_DEB)
CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) x=1
CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) x=2
VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN)
CCx Sample Enable Registers (CCx_SAMP_EN) x=1
CCx Sample Enable Registers (CCx_SAMP_EN) x=2
Reserved for future expansion
CC Control Register (CC_CTL)
CC Threshold x Registers (CC_THRx) x=0
CC Threshold x Registers (CC_THRx) x=1
CC Threshold x Registers (CC_THRx) x=2
CC Threshold x Registers (CC_THRx) x=3
CC Threshold x Registers (CC_THRx) x=4
CC Threshold x Registers (CC_THRx) x=5
CC Threshold x Registers (CC_THRx) x=6
CC Threshold x Registers (CC_THRx) x=7
CC Debounce Register (CC_DEB)
0834h – 083Fh Reserved for future expansion
0840h
0842h
0844h
0846h
VBUS Control Register (VBUS_CTL)
VBUS Threshold x Registers (VBUS_THRx) x=0
VBUS Threshold x Registers (VBUS_THRx) x=1
VBUS Threshold x Registers (VBUS_THRx) x=2
DS00002084C-page 84
2016-2017 Microchip Technology Inc.
UPD360
TABLE 9-9:
Address
SYSTEM CONTROL AND STATUS REGISTERS MAP (CONTINUED)
Register Name (Symbol)
VBUS Threshold x Registers (VBUS_THRx) x=3
0848h
084Ah
084Bh
084Ch
084Dh
084Eh
0850h
0852h
0854h
0856h
0858h
085Ah
085Ch
085Eh
0860h
0862h
0864h
0866h
0868h
086Ah
086Ch
086Eh
0870h
0872h
0874h
0875h – 0885h
0886h
0888h
VBUS Debounce Register (VBUS_DEB)
VBUS Off Register (VBUS_OFF)
VBUS Error Register (VBUS_ERR)
Reserved for future expansion
VBUS VSafe0V Threshold Register (VSAFE0V_THR)
CFG_SELx Match Registers (CFG_SELx_MATCH) x=0
CFG_SELx Match Registers (CFG_SELx_MATCH) x=1
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=0
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=1
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=2
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=3
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=4
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=5
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=6
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=7
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=8
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=9
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=10
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=11
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=12
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=13
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=14
CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=15
CFG_SEL Debug Register (CFG_SEL_DBG)
Reserved for future expansion
VCONN Discharge Threshold Register (VCONN_DIS_THR)
VCONN Discharge Time Register (VCONN_DIS_TIME)
088Ah – 0BFFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
2016-2017 Microchip Technology Inc.
DS00002084C-page 85
UPD360
9.12.1
CC HARDWARE CONTROL REGISTER (CC_HW_CTL)
Address:
0800h
Size:
16 bits
Bits
Description
Type
Default
15:14 SHORT_DET
R/W
00b
Defines behavior in standalone DFP mode for handling the short circuit
condition.
0xb: A0 functionality maintained where VBUS short is not checked before
initiating VBUS discharge.
10b: Device initiates VBUS discharge only after short circuit condition has
been removed.
11b: Device initiates VBUS discharge after short circuit condition has been
removed or a time equal to TCYCLE.
Note:
This field only has meaning for standalone DFP operation.
13
12
RESERVED
RO
-
BLK_PD_MSG
R/W
0b
This bit causes the CC debouncer to pause whenever a PD message is
detected by the MAC. This applies for both transmit and receive messages.
After the message is processed
0b: Disable PD message filtering.
1b: Enable PD message filtering.
Note:
This must be enabled for collision detection.
11
MATCH_DB_UNITS
R/W
0b
This bit defines the units of the Match Debounce Register (MATCH_DEB).
0b: Match debounce has units of 1.6 ms.
1b: Match debounce has units of 100 us.
Note:
1.6 ms is derived from the time to cycle through all thresholds on
both CC pins.
10
9
DEVICE_MODE
RO
RO
0b
0b
Indicates the current mode of the device.
0b: Device is in Companion Mode
1b: Device is in Standalone Mode (UPD360-A/UPD360-B only)
CC_DB_ACTIVE
When this bit reads back 0b, the debouncer is disabled. The CC debouncer is
enabled when it reads back 1b.
Note:
Software may poll this bit to determine when the CC debouncer is
disabled, which can be used as a condition for programming a new
configuration.
8
DEVICE_STATE
Indicates the current state of the device attachment.
RO
0b
0b: Device is not attached
1b: Device is attached
DS00002084C-page 86
2016-2017 Microchip Technology Inc.
UPD360
Bits
Description
Type
Default
7:6
Power Capability
RO
Note 9-2
Indicates the charging current capacity of the device as defined by the PWR_-
CAPx pins. (UPD360-A/UPD360-B only)
This field only has meaning for configurations where the PWR_CAPx pins are
available (UPD360-A/UPD360-B only).
5:3
2
Detach Threshold Select
R/W
R/W
Note 9-2
Note 9-3
Defines which CC threshold shall be used for determining a detach when
operating as a standalone DFP (UPD360-A/UPD360-B only).
Device Role
0b: Device configured as UFP.
1b: Device configured as DFP.
Note:
This bit must not be modified while the CC debouncer is enabled.
1
0
RESERVED
RO
-
Standalone Operation
0b: Companion Mode
R/W
Note 9-1
1b: Standalone mode (UPD360-A/UPD360-B only)
Standalone mode:
This is the mode of operation supported for standalone operation. During
standalone operation, the I2C interface may not be available and the host
CPU is not capable of managing the UPD360.
The following functions can be handled by the internal logic when this bit is
set:
• VCONN Enabled/Disable
• Attach detection and assertion of ATTACH
• Detach detection and de-assertion of ATTACH
• Orientation detection and assertion/de-assertion of ORIENTATION pin
• Enables CC de-bouncer.
Note 9-1
Note 9-2
Default is 1b when a standalone configuration is selected otherwise the default is 0b.
Default is a function of the PWR_CAP0 and PWR_CAP1 pins, when the configuration supports these
pins. Otherwise the default is 0h.
Note 9-3
Default is a function of the CFG_SEL0 and CFG_SEL1 pins. When the configuration indicates UFP
configuration this bit defaults to 0b. For DFP operation this bit defaults to 1b. When neither UFP or
DFP is specified the default shall be 0b.
2016-2017 Microchip Technology Inc.
DS00002084C-page 87
UPD360
9.12.2
CC INTERRUPT STATUS REGISTER (CC_INT_STS)
Address:
0803h
Size:
16 bits
Bits
Description
Type
Default
7
CC_MATCH_VLD
R/WC
0b
Asserts after the CC debouncer is first enabled, via CC Comparator Control,
and the first match becomes valid in CCx Match Registers (CCx_MATCH).
6
RP_CHG
R/WC
0b
When operating as a standalone UFP, this interrupt indicates a change in the
state of the RP value advertised by the DFP has been detected (UPD360-A/
UPD360-B only).
Note:
This bit is RO when the device is not configured as a standalone
UFP and will always read back 0b.
Note:
The source of this input is a pulse and does not persist after being
cleared.
Note:
The updated current advertisement is available via the DFP Cur-
rent Advertisement field in the CC Control Register (CC_CTL).
5
DETACH
R/WC
0b
Indicates a detach event has occurred when the device has been configured
to support standalone mode per the Standalone Operation field in the CC
Control Register (CC_CTL) (UPD360-A/UPD360-B only).
DFP Operation: CC pins are monitored for detecting a detach.
UFP Operation: VBUS is monitored for detecting a detach.
Note:
The source of this input is a pulse and does not persist after being
cleared.
4
ATTACH
R/WC
0b
Indicates an attach event has occurred when the device has been configured
to support standalone mode per the Standalone Operation field in the CC
Control Register (CC_CTL) (UPD360-A/UPD360-B only).
DFP Operation: CC pins are monitored for an attach.
UFP Operation: CC pins and VBUS are monitored for an attach.
Note:
The source of this input is a pulse and does not persist after being
cleared.
3:2
1
RESERVED
RO
RO
-
CC2_MATCH_CHG
Indicates the a change occurred in the state of the respective CCx Change
0b
Status Registers (CCx_CHG_STS).
Note:
The source of this input is a pulse and does not persist after being
cleared.
0
CC1_MATCH_CHG
Indicates the a change occurred in the state of the respective CCx Change
RO
0b
Status Registers (CCx_CHG_STS).
Note:
The source of this input is a pulse and does not persist after being
cleared.
DS00002084C-page 88
2016-2017 Microchip Technology Inc.
UPD360
9.12.3
CCX CHANGE STATUS REGISTERS (CCX_CHG_STS)
Address:
x=1: 0804h
x=2: 0805h
Size:
8 bits
Bits
Description
Type
Default
7:0
CCx Change Status
When set, each bit indicates that the respective bit in the CCx Match Regis-
ters (CCx_MATCH) has changed.
R/WC
0h
A write of 1b clears the respective status bit.
9.12.4
CCX MATCH REGISTERS (CCX_MATCH)
Address:
x=1: 0806h
x=2: 0807h
Size:
8 bits
Bits
Description
Type
Default
7:0
CCx Threshold Match (CCx_MATCH)
RO
Note 9-4
When set, each bit indicates that the respective threshold programmed in the
CC Threshold x Registers (CC_THRx) was matched. A match is determined
when the measured voltage exceeds the programmed threshold.
These registers are updated after the Match Debounce Register
(MATCH_DEB) while in the Unattached state. While in AttachWait state,
these registers are updated after the PD Debounce Register (PD_DEB) if
vOpen is seen for a time greater than in the PD Debounce Register
(PD_DEB). While in Attached Source / Attached Sink states (e.g. detecting
detach) the match registers are updated after the PD Debounce Register
(PD_DEB).
Note:
This register will always read the default value until the CC com-
parator is enabled when not operating in standalone mode.
Note:
The contents of this register are debounced per the settings in the
CCx Debounce Clear Enable Registers (CCx_DBCLR_EN), other-
wise the raw value shall be shown.
Note 9-4
Defaults to FFh when the device is configured as a DFP and 00h when configured as a UFP, per the
Device Role field in the CC Control Register (CC_CTL).
2016-2017 Microchip Technology Inc.
DS00002084C-page 89
UPD360
9.12.5
VBUS MATCH REGISTER (VBUS_MATCH)
Address:
0808h
Size:
8 bits
Indicates which VBUS thresholds are matched on VBUS_DET pin. A match is determined when the measured voltage
exceeds the programmed threshold.
Note:
Note:
When not operating in standalone mode, this register will always read 0h until the VBUS comparator is
enabled.
The contents of this register shall be debounced per the settings in VBUS Debounce Clear Enable Register
(VBUS_DBCLR_EN).
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5
4
3
2
1
0
VBUS Threshold 3 Match (VBUS3_THR_MATCH)
VBUS Threshold 2 Match (VBUS2_THR_MATCH)
VBUS Threshold 1 Match (VBUS1_THR_MATCH)
VBUS Threshold 0 Match (VBUS0_THR_MATCH)
RESERVED
RO
RO
RO
RO
RO
RO
0b
0b
0b
0b
-
VBUS VSafe0v Match (VSAFE0V_THR_MATCH)
0b
9.12.6
VBUS CHANGE STATUS REGISTER (VBUS_CHG_STS)
Address:
0809h
Size:
8 bits
Bits
Description
Type
Default
7:0
VBUS Change Status (VBUS_CHG_STS)
When set, each bit indicates that the respective bit in VBUS Match Register
(VBUS_MATCH) has changed.
R/WC
0h
A write of 1b clears the respective status bit.
DS00002084C-page 90
2016-2017 Microchip Technology Inc.
UPD360
9.12.7
POWER INTERRUPT STATUS REGISTER (PWR_INT_STS)
Address:
080Ah
Size:
8 bits
Bits
Description
Type
Default
7
VBUS_MATCH_VLD
R/WC
0b
Asserts after the VBUS debouncer is first enabled, via VBUS Comparator
Control, and the first match becomes valid in VBUS Match Register (VBUS_-
MATCH).
6
VCONN Discharge Error (VCONN_DISCH_ERR)
When set this bit indicates that a VCONN discharge error has been detected.
This bit is only available in standalone DFP mode and is otherwise reserved.
R/WC
0b
A discharge error is tracked when VCONN Discharge Control is set to 00b
or 01b. A discharge error is asserted when VCONN fails to fall below VCONN
Discharge Threshold (VCONN_DIS_THR) after a time greater than VCONN
Discharge Time (VCONN_DIS_TIME) elapses.
5
4
CC2 Back-Drive Error
R/WC
R/WC
0b
0b
When set, indicates that back-drive has been detected on the CC2 pin.
Note:
The source of this input is a level and persists until the error condi-
tion stops.
VBUS Discharge Error
When set, indicates that the an interval greater than defined in the VBUS Off
Register (VBUS_OFF) has elapsed while attempting to discharge VBUS.
Note:
The source of this input is a pulse and does not persist after being
cleared.
3
2
VCONN2 FET Power
R/WC
R/WC
0b
0b
The integrated VCONN2 FET is enabled and providing power.
This bit only has usefulness for standalone operation or where VCONN is
explicitly enabled by the host.
Note:
The source of this input is a level and persists until the VCONN is
no longer present.
VCONN1 FET Power
The integrated VCONN1 FET is enabled and providing power.
This bit only has usefulness for standalone operation or where VCONN is
explicitly enabled by the host.
Note:
The source of this input is a level and persists until the VCONN is
no longer present.
1
0
CC1 Back-Drive Error
R/WC
R/WC
0b
0b
When set indicates that back-drive has been detected on the CC1 pin.
Note:
The source of this input is a level and persists until the error condi-
tion stops.
VCONN Over-Current Error
Indicates an over-current has been detected on the integrated VCONN FET.
Note:
The source of this input is a level and persists until the error condi-
tion stops.
2016-2017 Microchip Technology Inc.
DS00002084C-page 91
UPD360
9.12.8
DEBUG INTERRUPT STATUS REGISTER (DBG_INT_STS)
Address:
080Bh
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
VCONN_DISCH_STS
When set, indicates that the CC pin previously sourcing VCONN is being
discharged.
RO
0h
3
R/WC
0b
This bit only exists in standalone DFP mode and is otherwise reserved.
2
1
VBUS_DISCH
R/WC
R/WC
0b
0b
When set indicates this indicates that VBUS is being discharged.
Note:
The source of this input is a level and it persists until the discharge
has completed.
CFG_SEL1 Done
When set, indicates that all CFG_SEL Threshold x Registers
(CFG_SEL_THRx) have been measured in response to the request enabled
by VBUS Comparator Control to sample the CFG_SEL1 pin and the results
are readable in the respective CFG_SELx Match Registers (CFG_SELx_-
MATCH) (UPD360-A/UPD360-B only).
Note:
The source of this input is a pulse and does not persist after being
cleared.
0
CFG_SEL0 Done
When set, indicates that all CFG_SEL Threshold x Registers
R/WC
0b
(CFG_SEL_THRx) have been measured in response to the request enabled
by VBUS Comparator Control to sample the CFG_SEL0 pin and the results
are readable in the respective CFG_SELx Match Registers (CFG_SELx_-
MATCH).
Note:
The source of this input is a pulse and does not persist after being
cleared.
9.12.9
CC INTERRUPT ENABLE REGISTER (CC_INT_EN)
Address:
0811h
Size:
8 bits
Bits
Description
Type
Default
7:4
CC Interrupt Enable
When “0”, prevents generation of the respective interrupt.
R/W
0000b
3:2
1:0
RESERVED
-
00b
00b
CC Interrupt Enable
When “0”, prevents generation of the respective interrupt.
R/W
DS00002084C-page 92
2016-2017 Microchip Technology Inc.
UPD360
9.12.10 CCX MATCH ENABLE REGISTERS (CCX_MATCH_EN)
Address:
x=1: 0812h
x=2: 0813h
Size:
8 bits
Bits
Description
Type
R/W
Default
7:0
CCx Match Enable
00h
When set, the corresponding bit in the CCx Change Status Registers (CCx-
_CHG_STS) can cause the assertion of the respective CCx Match Change
interrupt (CC1_MATCH_CHG/CC2_MATCH_CHG).
9.12.11 VBUS MATCH ENABLE REGISTER (VBUS_MATCH_EN)
Address:
0814h
Size:
8 bits
When set, the corresponding bit in the VBUS Change Status Register (VBUS_CHG_STS) can cause the assertion of
the VBUS_INT interrupt.
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5
4
3
2
1
0
VBUS Match Enable[5]
VBUS Match Enable[4]
VBUS Match Enable[3]
VBUS Match Enable[2]
VBUS Match Enable[1]
VBUS Match Enable[0]
R/W
R/W
R/W
R/W
RO
0b
0b
0b
0b
0b
0b
R/W
9.12.12 POWER INTERRUPT ENABLE REGISTER (PWR_INT_EN)
Address:
0815h
Size:
8 bits
Bits
Description
Type
Default
7:0
Power Interrupt Enable [7:0]
When “0”, prevents generation of the respective interrupt.
R/W
0h
2016-2017 Microchip Technology Inc.
DS00002084C-page 93
UPD360
9.12.13 DEBUG INTERRUPT ENABLE REGISTER (DBG_ENT_EN)
Address:
0816h
Size:
8 bits
Bits
Description
Type
Default
7:4
RESERVED
RO
0h
3
Debug Interrupt Enable 3
When “0”, prevents generation of the respective interrupt.
R/W
R/W
0b
0h
This bit only exists in standalone DFP mode and is otherwise reserved.
2:0
Debug Interrupt Enable [2:0]
When “0”, prevents generation of the respective interrupt.
9.12.14 MATCH DEBOUNCE REGISTER (MATCH_DEB)
Address:
0817h
Size:
8 bits
Bits
Description
Type
Default
7:0
Match Debounce
R/W
2h
Defines the debounce period utilized before updating the CCx Match Regis-
ters (CCx_MATCH) when not operating in standalone mode.
The units of this register is determined by MATCH_DB_UNITS bit in CC
Hardware Control Register (CC_HW_CTL). When this bit is clear, the units
are 1.6 ms. When this bit is set, the units are 100 us.
Note:
Note:
Note:
This register must not be modified while the CC debouncer is
enabled.
The actual debounce time may be +/-1 from the cycle time pro-
grammed.
The value programmed in this CSR should be at least equal to the
number of thresholds enabled in CCx Sample Enable Registers
(CCx_SAMP_EN). This is only an issue when MATCH_DB_UNITS
is set to 1b.
9.12.15 PD DEBOUNCE REGISTER (PD_DEB)
Address:
0818h
Size:
8 bits
Bits
Description
Type
Default
7:0
PD Debounce (PD_DEB)
Period used for implementing tPdDebounce
R/W
Ah
.
Note:
Note:
This register must not be modified while the CC debouncer is
enabled.
This register has units of 1 ms.
DS00002084C-page 94
2016-2017 Microchip Technology Inc.
UPD360
9.12.16 VCONN OCS AND BACK-DRIVE DEBOUNCE REGISTER (VCONN_DEB)
Address:
0819h
Size:
8 bits
Bits
Description
Type
Default
7:0
VCONN and Back-Drive Debounce (VCONN_DEB)
Period used for implementing debounce of over-current detected on VCONN
FET as well as back-drive detected on the CC pins.
R/W
2h
Note:
Note:
This register has units of 1 ms.
This register should not be changed when VCONN OCS Enable is
set.
9.12.17 CCX DEBOUNCE CLEAR ENABLE REGISTERS (CCX_DBCLR_EN)
Address:
x=1: 081Ah
x=2: 081Bh
Size:
8 bits
Bits
Description
Type
Default
7:0
CC Debounce Clear Enable (CC_DBCLR_DEB)
R/W
Note 9-5
When a bit is set, the respective threshold shall be included in the CC
debouncer. Alternatively, when cleared the respective threshold shall no lon-
ger be considered by the debouncer.
When CCx_DBCLR_EN bits are set on-the-fly, if a mismatch between the cur-
rent raw match vector (for the new CCx_DBCLR_EN) and the previous raw
match vector (for the old CCx_DBCLR_EN) exists, the DB will be reset.
Note:
Clearing bits in this register at run time does not reset the
debouncer.
Note:
The CC debouncer encompasses both CC1/CC2 pins. A detected
change for a threshold on either pin results in the debouncer reset-
ting.
Note:
Even though this register may change on-the-fly, the internal logic
will enable the change only at the end of the scan cycle, which is a
function of whether the CC1/CC2 pins are actively sampled and the
CCx Sample Enable Registers (CCx_SAMP_EN).
Note 9-5
The default depends on the device’s configuration, as shown in table Table 9-10 which depends upon
CFG_SEL0, PWR_CAP0, and PWR_CAP1 pins.
APPLICATION NOTE: Clearing a bit in CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) shall cause the
respective bit in CCx Match Registers (CCx_MATCH) to be immediately updated upon a
change in state of the associated threshold. This causes a state change in CCx Change
Status Registers (CCx_CHG_STS) and assertion of CC_INT, if enabled. To prevent this CCx
Match Enable Registers (CCx_MATCH_EN) should be updated before the CCx Debounce
Clear Enable Registers (CCx_DBCLR_EN) by having the associated threshold cleared.
2016-2017 Microchip Technology Inc.
DS00002084C-page 95
UPD360
TABLE 9-10: CCX_DBLCLR_DEB DEFAULTS
Configuration
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Standalone UFP
1
0
1
0
1
0
0
0
(UPD360-A/UPD360-B only)
Standalone DFP (Default Current)
(UPD360-A/UPD360-B only)
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Standalone DFP (1.5 A)
(UPD360-A/UPD360-B only)
Standalone DFP (3.0 A)
(UPD360-A/UPD360-B only)
Other
9.12.18 VBUS DEBOUNCE CLEAR ENABLE REGISTER (VBUS_DBCLR_EN)
Address:
081Ch
Size:
8 bits
When a bit is set, the respective threshold shall be included in the VBUS debouncer. Alternatively, when cleared, the
respective threshold shall no longer be considered by the debouncer.
When VBUS_DBCLR_EN bits are set on-the-fly, if a mismatch between the current raw match vector (for the new
VBUS_DBCLR_EN) and the previous raw match vector (for the old VBUS_DBCLR_EN) exists, the DB will be reset.
Note:
Clearing bits in this register at run time does not reset the debouncer.
APPLICATION NOTE: Clearing a bit in VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) shall cause
the respective bit in VBUS Match Register (VBUS_MATCH) to be immediately updated upon
a change in state of the associated threshold. This causes a state change in VBUS Change
Status Register (VBUS_CHG_STS) and assertion of VBUS_INT, if enabled. To prevent this,
the VBUS Match Register (VBUS_MATCH) should be updated before the VBUS Debounce
Clear Enable Register (VBUS_DBCLR_EN) by having the associated threshold cleared.
BITS
DESCRIPTION
TYPE
RO
DEFAULT
-
7:6
5
RESERVED
VBUS Debounce Clear Enable (VBUS3_DBCLR_DEB)
VBUS Debounce Clear Enable (VBUS2_DBCLR_DEB)
VBUS Debounce Clear Enable (VBUS1_DBCLR_DEB)
VBUS Debounce Clear Enable (VBUS0_DBCLR_DEB)
RESERVED
R/W
R/W
R/W
R/W
RO
Note 9-6
Note 9-6
Note 9-6
Note 9-6
-
4
3
2
1
0
VSAFE0V Debounce Clear Enable 9 (VSAFE0V_DBCLR_DEB)
R/W
Note 9-6
Note 9-6
The default depends on the device’s configuration, as shown in table Table 9-11 which depends upon
CFG_SEL0 pin.
DS00002084C-page 96
2016-2017 Microchip Technology Inc.
UPD360
TABLE 9-11: VBUS_DBCLR_EN DEFAULTS
Configuration
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Standalone UFP
1
0
1
1
0
0
0
0
(UPD360-A/UPD360-B only)
Standalone DFP
(UPD360-A/UPD360-B only)
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
Other
9.12.19 CCX SAMPLE ENABLE REGISTERS (CCX_SAMP_EN)
Address:
x=1: 081Dh
x=2: 081Eh
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:0
CC Sample Enable (CC_SAMP_EN)
R/W
FFh
When a bit is set, the respective CC threshold will be sampled by the CC
debouncer. When a bit cleared to 0b, the corresponding bit(s) in the CCx
Match Registers (CCx_MATCH) and CCx Change Status Registers
(CCx_CHG_STS) will always read 0b.
This register enables a reduction in latency for taking threshold
measurements by only having thresholds of interest being sampled.
Note:
For standalone DFP/UFP operation this register may remain set to
FFh, as latency for sampling CC thresholds in this case is not a
limitation.
Note:
This register must be used to implement Collision Avoidance.
2016-2017 Microchip Technology Inc.
DS00002084C-page 97
UPD360
9.12.20 CC CONTROL REGISTER (CC_CTL)
Address:
0820h
Size:
16 bits
The register controls the pull-down resistors and current sources on the respective CC1/CC2 pin.
Bits
Description
Type
Default
15
RA Detect
R/WC
0b
When set, indicates that an RA resistor has been detected.
This bit is set by the device when Standalone Operation is configured for
standalone mode. The device updates this field after an attach has been
detected.
14:13 CC Comparator Control
00b: CC Comparator and DAC powered-down
Note 9-7
00b
01b: CC Comparator samples CC1
10b: CC Comparator samples CC2
11b: CC Comparator samples CC1 and CC2
Note:
Note:
Note:
A sample is taken every 100 us. The current source reference shall
also be powered down when a value of 00b is set.
This field is RO and the contents are 11b when standalone mode
is enabled.
This field is used in conjunction with the CCx Sample Enable Reg-
isters (CCx_SAMP_EN) which constrains the number of thresh-
olds monitored on the enabled CC pin(s).
12
CC Communication Select
0b: CC1 is used for baseband communication.
Note 9-7
0b
1b: CC2 is used for baseband communication.
This bit is set by the device when Standalone Operation is configured for
standalone mode. The device updates this field after an attach has been
detected.
This bit is RO and reflects the state determined by the internal logic. In stand-
alone mode, this bit matches the state of the ORIENTATION pin (UPD360-A/
UPD360-B only).
11:10 CC2 RP Value
00b: RP current source disabled
R/W
R/W
00b
Note 9-8
01b: RP current source enabled, default USB power
10b: RP current source enabled, 1.5A
11b: RP current source enabled, 3.0A
Controls RP value on CC2 pin.
9:8
CC1 RP Value
00b: RP current source disabled
00b
Note 9-8
01b: RP current source enabled, default USB power
10b: RP current source enabled, 1.5A
11b: RP current source enabled, 3.0A
Controls RP value on CC1 pin.
DS00002084C-page 98
2016-2017 Microchip Technology Inc.
UPD360
Bits
Description
Type
Default
7:6
DFP Current Advertisement
RO
00b
When Standalone Operation is configured for standalone mode and the
device is configured as UFP, Device Role, this field indicates the DFP’s adver-
tised current. Otherwise this field shall be read back 00b.
The device updates this field after an attach has been detected.
0xb: RP current advertises default USB current
10b: RP current advertises 1.5A
11b: RP current advertises 3.0A
5
RESERVED
RO
-
4:3
CC2 Pull-Down Value
00b: Dead battery RD resistor selected
R/W
Note 9-9
01b: Trimmed RD resistor selected
10b: Trimmed RA resistor selected.
11b: Open Disconnect.
2
RESERVED
RO
-
1:0
CC1 Pull-Down Value
00b: Dead battery RD resistor selected
R/W
Note 9-9
01b: Trimmed RD resistor selected
10b: Trimmed RA resistor selected.
11b: Open Disconnect.
Note 9-7
Note 9-8
This bit is RO when operating in standalone mode. Otherwise it is R/W.
This field’s default is a function of the PWR_CAP0 and PWR_CAP1 pins when in standalone DFP
mode (see Section 9.8.1, "Configuration Selection") (UPD360-A/UPD360-B only). Otherwise the
default is 00b.
Note 9-9
For standalone DFP and standalone UFP, the value is 00b until the system reset completes.
Afterwards, the default for standalone DFP is 11b and for standalone UFP is 01b.
9.12.21 CC THRESHOLD X REGISTERS (CC_THRX)
Address:
x=0: 0822h
x=1: 0824h
x=2: 0826h
x=3: 0828h
x=4: 082Ah
x=5: 082Ch
x=6: 082Eh
x=7: 0830h
Size:
16 bits
Bits
15:10 RESERVED
Description
Type
Default
RO
-
9:0
CC Threshold X (CC_THRX)
CC Threshold X register.
R/W
Note 9-10
Note:
Note:
The units of this register are ~2.44 mV from a 2.5V/1024.
This register must not be modified while the CC debouncer is
enabled.
Note 9-10
The default varies as shown in Table 9-12.
2016-2017 Microchip Technology Inc.
DS00002084C-page 99
UPD360
TABLE 9-12: CC_THR DEFAULTS
CC_THR
Type-C Threshold
R/2R Divider
VALUE
0
1
2
3
4
5
6
7
0.2
0.4
0.66
0.8
1.23
1.6
2.6
3
0.13
0.27
0.44
0.53
0.82
1.07
1.73
2
55
109
180
219
336
437
710
820
APPLICATION NOTE: The CC Comparator must be powered down before updating these registers.
9.12.22 CC DEBOUNCE REGISTER (CC_DEB)
Address:
0832h
Size:
8 bits
Bits
Description
Type
Default
7:0
CC Debounce (CC_DEB)
Period used for implementing tCCDebounce
R/W
Fh
.
Note:
Note:
This register must not be modified while the CC debouncer is
enabled.
This register has units of 10 ms.
9.12.23 VBUS CONTROL REGISTER (VBUS_CTL)
Address:
0840h
Size:
16 bits
Bits
15:12 RESERVED
Description
Type
Default
RO
-
11
CC Back-Drive Enable
Enables the monitoring of the back-drive condition on both CC pins.
R/W
Note 9-11
When back-drive is detected, if the VCONN FET is enabled on the erred CC
pin, it shall be automatically disabled.
0b: CC Back-Drive disabled
1b: CC Back-Drive enabled
10
IBUS_LOW
R/W
0b
Determines whether IBUS Low is asserted during standalone mode when
PPC’s DISCH_SEL is cleared and a VBUS discharge is occurring.
0b: Do not assert IBUS Low
1b: Assert IBUS Low
DS00002084C-page 100
2016-2017 Microchip Technology Inc.
UPD360
Bits
Description
Type
R/W
Default
9:8
OCS_MIN
00b
Defines the minimum guaranteed assertion time for OCS_N when operating in
standalone DFP mode (UPD360-A/UPD360-B only).
00b: 5 ms
01b: 10 ms
10b: 20 ms
11b: 30 ms
7
VBUS_DB_ACTIVE
When this bit reads back 0b, the debouncer is disabled. The VBUS debouncer
RO
0b
is enabled when it reads back 1b.
Note:
Firmware polls this bit to determine when debouncer is disabled
and a new configuration may be programmed.
6
VCONN OCS Enable
R/W
R/W
Note 9-11
00b
Enables the monitoring of over current condition on the internal VCONN FETs.
0b: VCONN OCS monitor is disabled
1b: VCONN OCS monitor is enabled
5:4
VCONN Discharge Control
This field determines the VCONN discharge behavior. It only has meaning in
DFP standalone mode and should not be used by firmware when operating
in companion mode.
The discharge occurs on the CC pin that was supplying VCONN.
00b: Discharge VCONN until either the threshold defined by the VCONN
Discharge Threshold Register (VCONN_DIS_THR) is reached or the time
specified by the VCONN Discharge Time Register (VCONN_DIS_TIME) has
expired.
01b: VCONN discharge is not supported.
10b: Discharge VCONN until threshold defined by VCONN Discharge
Threshold Register (VCONN_DIS_THR) is reached.
11b: Discharge VCONN for the time specified by VCONN Discharge Time
Register (VCONN_DIS_TIME).
Note:
For options 0xb a VCONN discharge error is detected if the timer
expires and VCONN has not discharged below VCONN Discharge
Time Register (VCONN_DIS_TIME).
3
VCONN2 Control
Enables the VCONN2 FET.
R/W
0b
0b: VCONN2 FET is disabled
1b: VCONN2 FET is enabled
This bit has no meaning when in standalone mode (see Standalone Opera-
tion).
This bit automatically clears when a debounce VCONN OCS event occurs per
the assertion of VCONN Discharge Error (VCONN_DISCH_ERR).
2016-2017 Microchip Technology Inc.
DS00002084C-page 101
UPD360
Bits
Description
Type
Default
2
VCONN1 Control
Enables the VCONN1 FET.
R/W
0b
0b: VCONN1 FET is disabled
1b: VCONN1 FET is enabled
This bit has no meaning when in standalone mode (see Standalone Opera-
tion).
This bit automatically clears when a debounce VCONN OCS event occurs per
the assertion of VCONN Discharge Error (VCONN_DISCH_ERR)
1:0
VBUS Comparator Control
00b: Comparator and DAC disabled
Note 9-12
00b
01b: Sample VBUS
10b: Sample CFG_SEL0
11b: Sample CFG_SEL1 (UPD360-A/UPD360-B only)
After the sample of CFG_SEL0 or CFG_SEL1 has completed, this register
resets itself to 00b and disables the VBUS comparator.
Note:
This field is forced to 01b by hardware when operating as a stand-
alone UFP.
Note 9-11
Note 9-12
This default value is 1 when operating in standalone DFP mode. Otherwise, the default value is 0.
This field is RO and reads back 01b when operating in UFP standalone mode. In standalone mode
this value does not indicate that VBUS is being actively measured. Whether or not VBUS is being
actively measured can be determined by reading VBUS_DB_ACTIVE.
9.12.24 VBUS THRESHOLD X REGISTERS (VBUS_THRX)
Address:
x=0: 0842h
x=1: 0844h
x=2: 0846h
x=3: 0848h
Size:
16 bits
Bits
15:10 RESERVED
Description
Type
Default
RO
-
9:0
VBUS Threshold X (VBUS_THRX)
VBUS Threshold X register.
R/W
Note 9-13
The lower byte of the threshold must be written before the upper byte. The
entire 10-bit threshold is updated when the second write occurs.
Note:
The units of this register are ~2.44 mV from a 2.5V FS.
Note 9-13
The defaults are defined in Table 9-13.
TABLE 9-13: VBUS_THR DEFAULTS
VBUS_THR VBUS Threshold
1R/9R Divider
VALUE
0
1
2
3
3.67
5.5
0.36
0.54
0.54
0.54
148
222
222
222
5.5
5.5
DS00002084C-page 102
2016-2017 Microchip Technology Inc.
UPD360
9.12.25 VBUS DEBOUNCE REGISTER (VBUS_DEB)
Address:
084Ah
Size:
8 bits
This register has units of 1 ms.
Bits
Description
Type
Default
7:0
VBUS Debounce (VBUS_DEB)
Indicates debounce interval for the VBUS threshold comparators.
R/W
1h
Note:
This register must not be modified while the VBUS debouncer is
enabled.
9.12.26 VBUS OFF REGISTER (VBUS_OFF)
Address:
084Bh
Size:
8 bits
This register has units of 10 ms.
Bits
Description
Type
Default
7:0
VBUS Off
Defines timing after VBUS_DET discharges below VSafe0V.
R/W
10h
9.12.27 VBUS ERROR REGISTER (VBUS_ERR)
Address:
084Ch
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
VCONN Discharge
RO
-
3
2
R/W
R/W
0b
0b
When set the VBUS Discharge error shall be enabled to place the device in
the error state.
VBUS Discharge
When set, the VBUS Discharge error shall be enabled to place the device in
the error state.
Note:
This bit is not applicable when the PPC is selected for VBUS
discharge.
1
0
VCONN OCS
R/W
R/W
0b
0b
When set, the CC OCS error shall be enabled to place the device in the error
state.
CC Back-drive
When set, the CC back-drive error shall be enabled to place the device in the
error state.
2016-2017 Microchip Technology Inc.
DS00002084C-page 103
UPD360
9.12.28 VBUS VSAFE0V THRESHOLD REGISTER (VSAFE0V_THR)
Address:
084Eh
Size:
16 bits
BITS
15:10
9:0
DESCRIPTION
TYPE
RO
DEFAULT
-
RESERVED
VSAFE0V Threshold (VSAFE0V_THR)
R/W
Note 9-14
VSAFE0V Threshold register.
The lower byte of the threshold must be written before the upper byte. The
entire 10-bit threshold is updated when the second write occurs.
Note:
The units of this register are ~2.44 mV from a 2.5V FS.
The defaults are defined in Table 9-14.
Note 9-14
TABLE 9-14: VSAFE0V_THR DEFAULTS
VSAFE0V_THR VBUS Threshold
VSAFE0V_THR 0.8
1R/9R Divider
VALUE
32
0.08
APPLICATION NOTE: This register may be dynamically written to by software while the VBUS comparator is
enabled, provided the rules for updating defined in the register description are followed.
9.12.29 CFG_SELX MATCH REGISTERS (CFG_SELX_MATCH)
Address:
x=0: 0850h
x=1: 0852h
Size:
16 bits
Bits
Description
Type
Default
15:0
Configuration Select X Match (CFG_SELX_MATCH)
Indicates which configuration select thresholds are matched on the
RO
0h
CFG_SELx pin. A match is determined when the measured voltage exceeds
the programmed threshold. See Section 9.8.1, "Configuration Selection," on
page 81.
DS00002084C-page 104
2016-2017 Microchip Technology Inc.
UPD360
9.12.30 CFG_SEL THRESHOLD X REGISTERS (CFG_SEL_THRX)
Address:
x=0: 0854h
x=1: 0856h
x=2: 0858h
x=3: 085Ah
x=4: 085Ch
x=5: 085Eh
x=6: 0860h
x=7: 0862h
x=8: 0864h
x=9: 0866h
x=10: 0868h
x=11: 086Ah
x=12: 086Ch
x=13: 086Eh
x=14: 0870h
x=15: 0872h
Size:
16 bits
A total of 16 thresholds are supported for decoding the resistor value on the CFG_SELx pins.
Bits
Description
Type
Default
15:10 RESERVED
RO
-
9:0
CFG_SEL Threshold (CFG_SEL_THR)
R/W
Note 9-15
Note:
The units of this register are ~2.44 mV from a 2.5V FS.
Note 9-15
The defaults are defined in Table 9-15.
TABLE 9-15: CFG_SEL_THR DEFAULTS
CFG_SEL_THR
Default
0
32
1
96
2
160
224
288
352
416
480
544
608
672
736
800
864
928
992
3
4
5
6
7
8
9
10
11
12
13
14
15
2016-2017 Microchip Technology Inc.
DS00002084C-page 105
UPD360
9.12.31 CFG_SEL DEBUG REGISTER (CFG_SEL_DBG)
Address:
0874h
Size:
8 bits
Bits
Description
Type
Default
7:4
CFG_SEL1_VAL
RO
0h
This register stores a snapshot of the highest threshold matched when the
device samples the CFG_SEL1 pin after a system level reset event (UPD360-
A/UPD360-B only).
3:0
CFG_SEL0_VAL
RO
0h
This register stores a snapshot of the highest threshold matched when the
device samples the CFG_SEL0 pin after a system level reset event.
9.12.32 VCONN DISCHARGE THRESHOLD REGISTER (VCONN_DIS_THR)
Address:
0886h
Size:
16 bits
Bits
15:10 RESERVED
Description
Type
Default
RO
-
9:0
VCONN Discharge Threshold (VCONN_DIS_THR)
R/W
41h
Note 9-16
This register defines the threshold used in standalone DFP mode for
discharging VCONN.
Note:
The units of this register are ~2.44 mV from a 2.5V/1024.
41 equates to 150mV after accounting for the R/2R divider.
Note 9-16
9.12.33 VCONN DISCHARGE TIME REGISTER (VCONN_DIS_TIME)
Address:
0888h
Size:
16 bits
Bits
Description
Type
Default
7:0
VCONN Discharge Time (VCONN_DIS_TIME)
Defines the amount of time the CC pin supplying VCONN is discharged.
Note: The units of this register are 10 ms.
R/W
04h
DS00002084C-page 106
2016-2017 Microchip Technology Inc.
UPD360
10.0 BASEBAND CC INTERFACE (BCI)
The device integrates a Baseband CC Interface (BCI) to facilitate USB Power Delivery communication. This module
bridges between the PD MAC/BMC and the analog front end. Baseband communication is initiated by the PD MAC,
which interfaces to the BCI. The BCI implements the digital functions required to control TX baseband components.
10.1 Baseband TX Data-flow
The key responsibility of the BCI is to generate the wave form required for baseband communication. To this end, the
BMC has a group of eight registers that define the Lo-Hi and Hi-Lo transitions for the generated BMC signal.
When instructed to transition from Lo-Hi, the BCI steps through all BB TX Risex Registers (BB_RX_RISEx). Likewise
when instructed to transition from Hi-Lo, the BCI steps through all BB TX Fallx Registers (BB_TX_FALLx). The BCI
always presents the value at BB_TX_RISE0 or BB_RX_FALL0 first.
APPLICATION NOTE: The user may replicate values if it is desired to use less than twelve unique values for this
purpose.
The following steps should be followed to program the BCI for data transmission:
1. Software programs the BB TX Risex Registers (BB_RX_RISEx) and BB TX Fallx Registers (BB_TX_FALLx) to
define the slew rate for rising and falling transitions.
2. Software enables the PD MAC.
3. The PD MAC initiates, either via firmware, or autonomously via a data transmission (GoodCRC). The PD MAC
instructs the BCI to take the BB TX analog components out of power-down.
4. After a sufficient time elapses for the analog to power up, the PD MAC begins transmission to the BMC encoder
which drives the analog components.
5. If the MAC requests a rising transition, the BCI steps through the BB TX Risex Registers (BB_RX_RISEx). Alter-
natively, if the MAC requests a falling transition, the BCI steps through the BB TX Fallx Registers (BB_TX_-
FALLx).
6. When the PD MAC indicates the transmission has completed, the BCI powers down the TX analog components.
10.2 Baseband RX Data-flow
Baseband RX data is received by the BCI from the RX analog front end where it is compared to a threshold programmed
by software. The CC RX DAC Value defines the trip point used for reception of baseband data. The field shall be pro-
grammed to be 175 mV below the RX Eye center, as defined in the PD Specification for the mode in which the device
is operating (Sourcing Power, Sinking Power, Power Neutral).
In order to program the required trip point, the RX DAC Enable bit must be set and the CC RX DAC Value field in the
CC RX DAC Control Register (CC_RX_DAC_CTL) must be programmed.
2016-2017 Microchip Technology Inc.
DS00002084C-page 107
UPD360
10.3 Baseband CC Interface Registers
This section details the baseband CC interface registers. For an overview of the entire device register map, refer to Sec-
tion 4.0, "Register Map," on page 19.
TABLE 10-1: BASEBAND CC INTERFACE REGISTER MAP
Address
Register Name (Symbol)
CC RX DAC Control Register (CC_RX_DAC_CTL)
2800h
2802h
2803h
2804h
CC RX DAC Filter Register (CC_RX_DAC_FILT)
Reserved for future expansion
CC TX DAC Filter Register (CC_TX_DAC_FILT)
2805h – 280Fh Reserved for future expansion
2810h
2812h
2814h
2816h
2818h
281Ah
281Ch
281Eh
2820h
2822h
2824h
2826h
BB TX Risex Registers (BB_RX_RISEx) x=0
BB TX Risex Registers (BB_RX_RISEx) x=1
BB TX Risex Registers (BB_RX_RISEx) x=2
BB TX Risex Registers (BB_RX_RISEx) x=3
BB TX Risex Registers (BB_RX_RISEx) x=4
BB TX Risex Registers (BB_RX_RISEx) x=5
BB TX Risex Registers (BB_RX_RISEx) x=6
BB TX Risex Registers (BB_RX_RISEx) x=7
BB TX Risex Registers (BB_RX_RISEx) x=8
BB TX Risex Registers (BB_RX_RISEx) x=9
BB TX Risex Registers (BB_RX_RISEx) x=10
BB TX Risex Registers (BB_RX_RISEx) x=11
2828h – 282Fh Reserved for future expansion
2830h
2832h
2834h
2836h
2838h
283Ah
283Ch
283Eh
2840h
2842h
2844h
2846h
BB TX Fallx Registers (BB_TX_FALLx) x=0
BB TX Fallx Registers (BB_TX_FALLx) x=1
BB TX Fallx Registers (BB_TX_FALLx) x=2
BB TX Fallx Registers (BB_TX_FALLx) x=3
BB TX Fallx Registers (BB_TX_FALLx) x=4
BB TX Fallx Registers (BB_TX_FALLx) x=5
BB TX Fallx Registers (BB_TX_FALLx) x=6
BB TX Fallx Registers (BB_TX_FALLx) x=7
BB TX Fallx Registers (BB_TX_FALLx) x=8
BB TX Fallx Registers (BB_TX_FALLx) x=9
BB TX Fallx Registers (BB_TX_FALLx) x=10
BB TX Fallx Registers (BB_TX_FALLx) x=11
2848h – 2BFFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
DS00002084C-page 108
2016-2017 Microchip Technology Inc.
UPD360
10.3.1
CC RX DAC CONTROL REGISTER (CC_RX_DAC_CTL)
Address:
2800h
Size:
16 bits
Bits
Description
Type
Default
15
RX DAC Enable
0: Disable the CC RX DAC
R/W
0b
1: Enable the CC RX DAC
14:10
9:0
RESERVED
RO
-
CC RX DAC Value
This register defines the trip point used for reception of baseband data.
R/W
0h
Note:
Note:
The full scale range of this DAC is 1.8V.
The DAC must be programmed to be 175mV below the desired RX
Eye center.
10.3.2
CC RX DAC FILTER REGISTER (CC_RX_DAC_FILT)
Address:
2802h
Size:
8 bits
Bits
Description
Type
Default
7:2
RESERVED
RO
R/W
R/W
-
1
0
Select CC Rx Filter Configuration
CC RX DAC Filter Enable
0b
0b
10.3.3
CC TX DAC FILTER REGISTER (CC_TX_DAC_FILT)
Address:
2804h
Size:
8 bits
Bits
Description
Type
Default
7:5
RESERVED
RO
-
4
CC TX Filter Enable
R/W
R/W
0
Enables CC TX filter and driver.
3:0
CC TX Filter
Selects CC TX filter bandwidth.
8h
2016-2017 Microchip Technology Inc.
DS00002084C-page 109
UPD360
10.3.4
BB TX RISEX REGISTERS (BB_RX_RISEX)
Address:
x=0: 2810h
x=1: 2812h
x=2: 2814h
x=3: 2816h
x=4: 2818h
x=5: 281Ah
x=6: 281Ch
x=7: 281Eh
x=8: 2820h
x=9: 2822h
x=10: 2824h
x=11: 2826h
Size:
16 bits
The BB TX Rise registers define the characteristics of the baseband waveform on rising transitions.
Bits
Description
Type
Default
15:10 RESERVED
RO
-
9:0
BB TX Rise Value
Code presented to the CC TX DAC when implementing the rising transition for
a baseband transmission.
R/W
0h
10.3.5
BB TX FALLX REGISTERS (BB_TX_FALLX)
Address:
x=0: 2830h
x=1: 2832h
x=2: 2834h
x=3: 2836h
x=4: 2838h
x=5: 283Ah
x=6: 283Ch
x=7: 283Eh
x=8: 2840h
x=9: 2842h
x=10: 2844h
x=11: 2846h
Size:
16 bits
The BB TX Fall registers define the characteristics of the baseband waveform on rising transitions.
Bits
Description
Type
Default
15:10 RESERVED
RO
-
9:0
BB TX Fall Value
R/W
0h
Code presented to the CC TX DAC when implementing the falling transition
for a baseband transmission.
DS00002084C-page 110
2016-2017 Microchip Technology Inc.
UPD360
11.0 POWER DELIVERY MAC
The PD MAC implements certain features of the protocol layer and physical layer of the Universal Serial Bus Power
Delivery Specification. On one end the PD MAC interfaces to the software implementing the bulk of protocol and higher
level layers and on the other end it interfaces to a BMC encoder / decoder module.
In addition to the normal TX and RX functions, the PD MAC implements the test mode logic defined in the USB PD
specification (BIST).
The PD MAC supports the following features:
• Automatic TX Mode for packet framing and CRC32 insertion.
• Raw TX Mode for bit level packet control.
• Automatic GoodCRC response to received messages.
• Automatic BIST Error Count Message in BIST RX Mode.
• GoodCRCTimer implementation.
• Automatic retries with programmable retry count.
• Redundant receive packets automatically dropped in auto response mode.
• 74 byte TX queue.
• 128 byte RX queue.
• Programmable TX Bit-time. Allows for changing operating frequency.
• Programmable preamble length.
• BIST TX and RX logic.
• Programmable TX and RX queue modes - buffer mode and FIFO mode.
• CRC32 generator for TX.
• CRC32 calculator and comparator for RX.
11.1 PD MAC Transmitter
The PD MAC transmitter is comprised of three major blocks:
• TX Queue
• TX Control
• TX Comm
The TX Queue is where software loads the message to be transmitted.
The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and
based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control
information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in
automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also
handles the selection of the SOP type that is to be transmitted.
The TX Comm is comprised of a TX CRC generator, a 4b5b encoder, serializer, preamble generator, and TX bit timer.
It takes the nibble data, computes and inserts the CRC, 5b encodes, and generates the baseband serial data. Preamble
insertion is also performed by this logic.
The following sub-sections describe the various blocks and sub-blocks in more detail. Some of the supported TX fea-
tures are also described.
11.1.1
TX QUEUE
The TX Queue is where software loads the message to be transmitted. The following sub-sections describe the TX
Queue in more detail.
11.1.1.1
The TX Queue's write interface (MCU side) has two modes of operation: FIFO Mode and Buffer Mode.
11.1.1.1.1 FIFO Mode
TX Queue Modes of Operation
This mode is enabled by setting the EN_FMQ bit in the TX Control Register A(TX_CTL_A). In this mode, software writes
data into the TX Queue like a FIFO. Software can use any offset address in the range of 1800h-1849h (although 1800h
would be logical to use). The FIFO is 74 entries deep. Data written to the FIFO cannot be read back by software.
2016-2017 Microchip Technology Inc.
DS00002084C-page 111
UPD360
11.1.1.1.2
Buffer Mode
This mode is selected when the EN_FMQ bit in the TX Control Register A (TX_CTL_A) is cleared (default after POR).
In this mode, software writes data into the TX Queue as if it were writing to registers at different addresses. The offset
address range is 1800h-1849h and the buffer has 74 locations.
Only byte access should be used while accessing the TX Queue in this mode. Note that buffer offset address 1800h
contains the least-significant-byte (LSB) (byte that goes out first). Buffer offset address 0x049 has the most-significant-
byte (MSB) (byte that goes out last).
Software can arbitrarily write or read any location in the buffer. Only one packet can be queued into the TX Queue at
one time. Queuing of multiple packets is not supported.
11.1.1.2
TX Queue Data and Processing Modes
The data placed in the TX Queue depends on the selected processing mode. Two modes are supported: “Auto Mode
Data Processing” (AMDP) and “Raw Mode Data Processing” (RMDP).
11.1.1.2.1
Auto Mode Data Processing (AMDP)
This mode is selected by clearing the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, only the
message data (header and data objects) to be transmitted is queued in the TX Queue. Further, the data is queued as
bytes. Since there is no framing information with the data, the TX Packet Length Register (TX_PKT_LEN) is used to
provide information about the length of message data. Hardware uses this information to determine when and where to
append the CRC. Packet framing (preamble, SOP, and EOP) is automatically inserted by the hardware.
11.1.1.2.2
Raw Mode Data Processing (RMDP)
This mode is selected by setting the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, software is
responsible for constructing the entire packet including framing, except the preamble and CRC. Since framing involves
K-codes, the data placed in the queue is coded with control information. The data in each byte of the queue is treated
as a “nibble” of packet data that either needs to be 5b encoded by hardware or a K-codes that should be transmitted
without any 5b encoding. There are also some special control bytes to control insertion of CRC and termination of
packet.
When tx_queue_data[5] is “0” then tx_queue_data[3:0] is treated as 4b regular data. This 4b data goes through the
CRC32 generator for CRC calculation and is encoded to 5b per Table 5-1 of USB PD Specification R1.0 (Table 11-1
shows the 4b5b encoding).
When tx_queue_data[5] is “1” then tx_queue_data[4:0] is treated as 5b K-code (see Table 11-1). This data is eliminated
from the CRC calculation and does not go through any further encoding prior to transmission.
The tx_queue_data[7:0] values of 8'hFF and 8'hFE have special meaning. 8'hFF implies that the packet data is done
and hardware should now insert the calculated CRC32 (TX_INS_CRC). 8'hFE implies that the transmission should be
stopped immediately (TX_STOP).
Note that in RMDP, software can compute its own CRC and place it in the Queue as encoded data. In this case, the
TX_INS_CRC code would not be added to the Queue and instead software would proceed with adding the EOP and
terminating the transfer with TX_STOP.
Table 11-1 shows how the byte wide queued data is interpreted or encoded by the transmission logic in raw mode.
DS00002084C-page 112
2016-2017 Microchip Technology Inc.
UPD360
TABLE 11-1: RAW MODE DATA ENCODING
tx_queue_data[5:0]
Encoded Symbol
tx_queue_data[5:0]
Encoded Symbol
6’h00
6’h01
6’h02
6’h03
6’h04
6’h05
6’h06
6’h07
5’b11110
5’b01001
5’b10100
5’b10101
5’b01010
5’b01011
5’b01110
5’b01111
6’h08
6’h09
6’h0A
6’h0B
6’h0C
6’h0D
6’h0E
6’h0F
5’b10010
5’b10011
5’b10110
5’b10111
5’b11010
5’b11011
5’b11100
5’b11101
tx_queue_data[5:0]
K-Code
Transmitted Data
6’b1_11000
6’b1_10001
6’b1_01101
6’b1_00111
6’b1_11001
Sync-1
Sync-2
EOP
5’b11000
5’b10001
5’b01101
5’b00111
5’b11001
RST1
RST2
tx_queue_data[5:0]
Special Meaning
8’hFE
8’hFF
TX_STOP
TX_INS_CRC
Note that the tx_queue_data[4:0] is passed as-is when tx_queue_data[5] is set to 1. Thus, software can send reserved
symbols for error testing. The only caveat is that hardware cannot be used to generate and insert CRC. In this case,
software should compute the necessary CRC32 and add it the data packet and skip the 0xFF code in the queue for CRC
insertion.
11.1.1.2.3
TX Queue Programming Sequence - AMDP
The following sequence should be used when programming a sequence in AMDP. This example assumes hardware
performs packet framing and CRC insertion.
1. Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous
TX request.
2. If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the
TX Control Register B (TX_CTL_B).
3. Write the two header bytes.
4. Write the payload data, if any.
5. Write the number of bytes to the TX Packet Length Register (TX_PKT_LEN).
6. Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)).
7. If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission.
Else: repeat step 6. Note: If an RX is in progress, the current TX may need to be abandoned.
2016-2017 Microchip Technology Inc.
DS00002084C-page 113
UPD360
11.1.1.2.4
TX Queue Programming Sequence - RMDP
The following sequence should be used when programming a sequence in RMDP. This example assumes hardware
performs CRC insertion.
1. Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous
TX request.
2. If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the
TX Control Register B (TX_CTL_B).
3. Write the SOP K-Codes to the FIFO *Sync-1, Sync-1, Sync-1, Sync-2).
4. Write two header bytes, splitting each byte into nibbles.
5. Write the payload data, if any, splitting each byte into nibbles.
6. Write the value “0xFF” to insert the CRC.
7. Write the EOP K-Code (EOP).
8. Write the value “0xFE” to terminate the transmission. Failure to write this value will cause transmission to con-
tinue indefinitely looping on the TX buffer.
9. Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)).
10. If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission.
Else: repeat step 9. Note: If an RX is in progress, the current TX may need to be abandoned.
Note:
The value of the TX Packet Length Register (TX_PKT_LEN) is ignored for this mode since hardware knows
when to terminate the packet based on detection of TX_STOP control code.
11.1.2
TX CONTROL
The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and
based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control
information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in
automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also
handles the selection of the SOP type that is to be transmitted.
11.1.2.1
Transmit Requests
There are four sources of transmit requests:
• GoodCRC Ack from the receiver for a soft-reset
• GoodCRC Ack from the receiver for a normal packet
• BIST error count message from the BIST receiver
• Transmit go from the software
11.1.2.2
Transmit Aborts
Once packet transmission is initiated, the device will power up the analog and then wait for the bus turn-around timers
and power-up timers to expire. During this wait, the transmission can be aborted by software and will be aborted by the
device, when a good packet (including soft-reset), a hard reset, or a cable reset (if enabled and the SOP type of the
pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received.
Once the bus turn-around time has expired (or if it was already expired) and the power up time is expired, the bus is
checked for idle. If the bus is idle, the transmission is started. If the bus is not idle, the transmission is discarded and,
typically, an abort status set. This discard can be disabled with the WAIT4LINE_IDLE bit in the TX Control Register A
(TX_CTL_A) for all packets and is also disabled for auto response triggered GoodCRC Acks for received soft-resets
(unless the feature is disabled via the DIS_SPCL_SR_GCRC_ACK bit).
If the transmission is not discarded due to the bus being non-idle, the device waits for the bus to become idle and then,
once again, waits the turn-around time. During the wait for bus idle, the transmission can be aborted by software and
will be aborted by the hardware if a good packet, a hard reset or a cable reset (if enabled and the SOP type of the pend-
ing TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received.
Software issued hard and cable resets are not aborted due to received good packets, hard resets or cable resets.
DS00002084C-page 114
2016-2017 Microchip Technology Inc.
UPD360
Note that for a received good packet to abort a pending transmission, the SOP type of the received packet must match
the SOP type of the pending transmission, or the SOP type of the received packet must be SOP with the SOP type of
the pending transmission being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX
Control Register A (TX_CTL_A)) and, for messages other than Soft-Reset, the received message ID must indicate a
non-duplicated packet (Soft-Resets are never considered duplicates). Ping and GoodCRC messages do not cause a
transmission to abort.
Separate TX interrupt abort bits and separate abort status registers are provided for software issued and auto-response
packets.
11.1.2.3
Transmit Retries
Transmitted packets are retried under two scenarios: bus idle violations, and GoodCRC response timeout.
If the transmission is discarded due to the bus being non-idle, the option exists to retry instead of treating it as an abort.
In order for this to occur, the packet must have been initiated by software, not be a hard or cable reset, auto response
mode must be enabled, the retry count must be non-zero, and the RETRY_ON_LINE_BUSY bit in the TX Control Reg-
ister A (TX_CTL_A) must be set. If after the specified number of retries, the transmission failed due to bus busy, the
TX_FAILED status is set (not TX_ABORTED). Hard and Cable resets are not retried.
Following the transmission of a software initiated frame (other than Hard and Cable resets), the device will start a timer
and wait for a GoodCRC response to be indicated by the receiver. This assumes retries and / or the wait for GoodCRC
are enabled.
If a GoodCRC is received with the correct SOP type and message ID, then the wait is finished and the transmission is
done. If a GoodCRC is received with the wrong SOP type or message ID, it is ignored by the transmitter (the transmitter
is not even notified) and silently dropped by the receiver.
If the wait for CRC timer expires and the remaining retry count is non-zero, the original packet is re-transmitted. If the
remaining retry count is zero, then the packet is not retried and a failed status is indicated.
The wait for GoodCRC will be aborted if any of the following are received:
• A hard reset
• A cable reset (if cable reset reception is enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_De-
bug or SOP''_Debug)
• A soft-reset (if the SOP type of the RX is the same as that of the pending TX or the SOP type of the RX is SOP
with the SOP type of the pending transmission being non-SOP)
• A good packet other than a GoodCRC or Ping (if the SOP type of the RX is the same as that of the pending TX or
the SOP type of the RX is SOP with the SOP type of the pending transmission being non-SOP (the latter can be
disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and the package is
not a duplicate message)
The latter two causes are considered to be protocol errors.
The wait for GoodCRC can also be aborted by software. An aborted wait for GoodCRC is not retried.
11.1.2.4
Transmitter Disable
In order to avoid a race condition where the software is currently issuing a transmit and the hardware is receiving a
packet, the EN_FWTX bit in the TX Parameters Register A (TX_PARAM_A) is automatically cleared if a hard reset to a
cable reset (if enabled - no SOP type checking is done since a transmission may not be pending) has been received
(based on the RX_CABLE_RST and RX_HARD_RST bits in the RX Interrupt Status Register (RX_IRQ_STAT)) or if
there is any data in the RX FIFO. Using the interrupt and FIFO status (level sensitive) instead of the even occurrence
(edge) avoids another race condition where the software has set the EN_FWTX bit just following the event.
11.1.3
TX COMM
The TX Comm is responsible for taking the coded nibbles from TX Control, encoding it if necessary, and serializing to
make it ready for transmission. It is responsible for preamble insertion, CRC calculation, and CRC insertion. It also pro-
vides the TX clock signal for the BMC encoder.
11.1.3.1
Preamble Insertion
The device automatically adds the alternating “0” and “1” preamble to the transmitted packet. When the transmission of
the preamble is completed, data from TX Queue is processed under direction of the TX Control.
2016-2017 Microchip Technology Inc.
DS00002084C-page 115
UPD360
The number of preamble bits sent is programmable by the value of the PREAMBLE_LEN bit in the TX Parameters Reg-
ister B (TX_PARAM_B).
Note:
Setting the PREAMBLE_LEN field to an odd value will cause violation of the USB PD Specification which
states “The preamble shall start with a “0” and shall end with a “1”.” An odd value will cause preamble to
start with a value of “0” but it will also end in a value of “0.” Setting this field to an odd value may or may
not lead to functional issues. Therefore, this field should be set to an even value to remain USB PD Spec-
ification compliant.
11.1.3.2
TX CRC32
The transmit CRC is reset at the start of transmission (setting of the GO bit in the TX Control Register B (TX_CTL_B)
or by triggering of automatic response by hardware).
The coded nibble data is streamed into the TX CRC32 one nibble at a time for CRC calculation. Only valid D-Code data
is used in CRC calculation. All framing data (invalid D-Code) is excluded from CRC calculation.
Note:
The CRC32 algorithm is described in the USB PD Specification.
11.1.3.3
TX Bit Timing
The baseband transmit signal bit time is controlled by the value in the TX Bit-Time Count Register (TX_BITTIME_CNT).
This value determines the transmit data rate.
The count value is based on clock frequency and is given by:
((Clock Freq KHz / Bit Rate Kbps) - 1)
For example:
Clock Frequency = 48000KHz (48MHz)
Nominal Bit Rate = 300 Kbps
bit_time_cnt = (48000 / 300) - 1 = 159
11.1.4
AUTOMATIC RESPONSE MODE
The device supports an Automatic Response Mode (not to be confused with automatic-data processing mode). In this
mode, the device will automatically send a GoodCRC message upon successful packet reception, or a BIST Error Count
message upon reception of a BIST PRBS frame. This mode can be enabled by setting the EN_AUTO_RSP_MODE bit
in the TX Control Register A (TX_CTL_A).
During normal auto-response, if the bus if found to be busy when the device attempts to send the auto-response (should
not happen, except if there is noise) it will abort the transmission and the AUTO_RSP_ABORTED bit in the TX Interrupt
Status Register (TX_IRQ_STAT) will be set. This behavior can be altered by setting the WAIT4LINE_IDLE bit in the TX
Control Register A (TX_CTL_A). Setting this bit will force the device to wait until the bus becomes idle (refer to the
WAIT4LINE_IDLE bit description for additional information). GoodCRCs and BIST Error Count messages are not retried
even if RETRY_ON_LINE_BUSY in TX_CTL_A is set.
In USB Power Delivery Revision 1.0, Soft Reset had a one-strike rule and failure of Soft Reset led to Hard Reset, leading
to the link being brought down, therefore the transmission of GoodCRC ACK in response to reception of Soft Reset is
handled a little differently. If hardware finds that the line is busy when it attempts to send the GoodCRC ACK it will wait
until the line becomes idle and then re-try the transmission. This process will happen indefinitely. This behavior is same
as what happens to normal GoodCRC ACK when WAIT4LINE_IDLE bit is set. GoodCRCs are not retried even if the
RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) is set. For USB Power Delivery Revision 3.0,
Soft Resets are normally retried, therefore this function should be disabled via the DIS_SPCL_SR_GCRC_ACK bit.
The SOP type that is used for the automatically sent GoodCRC packet is the SOP type of the received packet (parsed
by the receiver). The SOP type that is used for the BIST Error Count message, is selected via the TX_SOP_SELECT
bit in the TX Parameters Register A (TX_PARAM_A).
For both GoodCRC and BIST Error Count messages, bit 8 in the packet header is taken from either the PORT_POW-
ER_ROLE (for SOPs) or the CABLE_PLUG (for SOP', SOP'' and _debugs) bits within the TX Parameters Register C
(TX_PARAM_C), depending on the SOP type that was received. Bit 5 in the packet header is taken from either the
PORT_DATA_ROLE bit (for SOPs) or set to zero (for SOP', SOP'' and _debugs), depending on the SOP type that was
received.
In order to avoid missing an auto response GoodCRC request, a flag is used. The flag is set with a request pulse from
the receiver and is cleared when the response is sent or aborted. Along with the request flag being set, the SOP type
and message ID of the request as well as the Soft Reset response indication are saved. In the event that there was a
DS00002084C-page 116
2016-2017 Microchip Technology Inc.
UPD360
pending auto response GoodCRC request and another packet was received resulting in another auto response Good-
CRC request, the second request will replace the first request, unless the first request had a SOP type of SOP and the
second request had a SOP type of SOP'_Debug or SOP'’_Debug. This replacement occurs regardless of the setting of
the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A). Even if a received packet does not
abort a pending auto response, the pending auto response may get replaced by a new auto response.
11.1.5
AUTOMATIC RETRY MODE
The device also supports an Automatic Retry Mode. In this mode, when a GoodCRC message is not received in the
appropriate time (i.e., before CRCReceiveTimer expires) the current message is retried.
Hardware will retry the message until the retry value specified in the N_RETRY_CNT field in the TX Parameters Reg-
ister C (TX_PARAM_C) is satisfied. If the N_RETRY_CNT is set to zero, Automatic Retry Mode is disabled.
The number of retries used by the device to complete the transaction are tracked and made available to software via
the N_HW_RETRIES field in the TX Status Register (TX_STAT).
An N_RETRY_CNT value of zero implies the message is attempted only once, i.e., hardware will not retry it. N_RE-
TRY_CNT specifies the number of retries so the number of attempts is (N_RETRY_CNT + 1). Stated another way, if
you want hardware to make “N” attempts to send a message then the N_RETRY_CNT field must be set to “N-1.”
Reception of Hard Reset or Cable reset (when enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_De-
bug or SOP''_Debug) from port partner, messages other than GoodCRC or Ping message (if the SOP types of the RX
and TX match or if the SOP type of the RX is SOP with the SOP type of TX being non-SOP (the latter can be disabled
via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and the packet was not a dupli-
cate), or issuance of abort by software will terminate any pending auto retries.
Detection of bus collision will cause the device to abort the current transfer including any pending auto retries unless
the RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) is set.
Note that disabling of automatic-retry by setting N_RETRY_CNT to zero will also disable the device’s ability to wait for
a GoodCRC message before a successful message transmission is indicated. This applies, for example, to the case
when Soft Reset is transmitted. To circumvent this limitation, a EXPECT_GOODCRC bit in the TX Parameters Register
A (TX_PARAM_A) is available. Setting this bit will cause the device to wait for a GoodCRC in response to a TX mes-
sage, even when the N_RETRY_CNT field is set to zero.
Note:
Setting N_RETRY_CNT to zero after the GO bit has been set will have no effect for the current transfer.
The expected message ID within the GoodCRC message is set by software via the MSG_ID field in the TX Parameters
Register A (TX_PARAM_A). This is compared to the message ID within the received GoodCRC message.
The expected SOP type within the GoodCRC message is set by software via the TX_SOP_SELECT field in the TX
Parameters Register A (TX_PARAM_A). This is compared to the SOP type received in the GoodCRC message. In order
for the GoodCRC message to be received, it is assumed that the SOP type has been enabled via the RX_SOP_EN-
ABLE field in the RX Control Register B (RX_CTL_B).
11.1.6
IFG TIMER
The TX turn-around timer is used to insure that a minimum bus idle time is guaranteed between packet reception and
packet transmission, i.e., sending of GoodCRC message upon successful packet reception.
The value of this timer is programmable via the TX Turnaround Time Register (TX_TA_TIME). The value is specified in
uSec. This timer uses the free-running 1us pulse so the value of this register should be 1 more than desired to ensure
the minimum time.
11.1.7
CRC RECEIVE TIMER
This timer is enabled when the device is expected to wait for a GoodCRC ACK (i.e., automatic-retry mode is enabled
by non-zero value in the N_RETRY_CNT field of the TX Parameters Register C (TX_PARAM_C) or if zero, EXPECT_-
GOODCRC bit in the TX Parameters Register A (TX_PARAM_A) is set) at the time transmission is requested. This timer
can also be enabled for software usage via the EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A).
If enabled, the timer starts whenever a TX packet transmission stops.
If software aborts a TX packet in between transmission with auto-retry mode enabled, this timer will not be triggered and
will be disabled. If software aborts a TX packet with auto-retry disabled, then it should also disable the timer by clearing
the EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A).
2016-2017 Microchip Technology Inc.
DS00002084C-page 117
UPD360
The timeout value for CRCReceiveTimer is programmable via the TRECEIVE field in the RX tReceive Time Register
(RX_TRECEIVE_TIME) in multiples of 10 uSec.
This timer can be used by software as the BISTReceiveErrorTimer in the BIST TX mode (the device does not automat-
ically time BISTReceiveError) and as the CRCReceiveTimer when not using automatic retry or wait for GoodCRC
modes.
11.1.8
ABORTING A TX IN PROCESS
Software can abort a transmission that has already started by issuing an abort via the ABORT bit in the TX Control Reg-
ister B (TX_CTL_B). The packet will be aborted as follows based on current phase of transmission:
• If packet transmission had not yet started because the device was waiting for the turn-around timer to expire or
line to become idle, transmission will be aborted immediately.
• If the current phase is Preamble, the device will complete transfer of the current bit, append EOP, and turn the
transmitter off.
• If the current phase is SOP, Data, or CRC, the device will complete transfer of the current nibble, append EOP,
and turn the transmitter off.
A Hard Reset should follow this operation, which is the software's responsibility.
11.2 PD MAC Receiver
The PD MAC receiver is comprised of three major blocks:
• RX Queue
• RX Control
• RX Comm
The RX Queue is where software reads the received messages.
The RX Control implements the necessary control logic. It is responsible for validating the received packet, updating the
RX Queue status, and triggering automatic responses, if required.
The RX Comm is comprised of the Clock and Data Recovery (CDR), RX DES (de-serializer) (serial-to-parallel converter,
4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to detect valid packet
reception.
The following sub-sections describe the various blocks and sub-blocks in more detail.
11.2.1
RX QUEUE
The decoded RX data (header, data objects, and CRC) is saved into an integrated 128 byte RX FIFO. The RX FIFO that
is capable of storing multiple packets and provides read and write pointers.
Two bytes are added to the beginning of each packet. Byte 0 holds the packet status (SOP type and the legacy “buffer”
valid bit) and byte 1 holds the packet length. An option exists to swap these values (length in byte 0, status in byte 1)
and add one to the packet length (to account for the status byte). This option is used for an SMBus like block read where
the first byte read indicates the length of the transfer and the remaining bytes (the status and the packet) follow. Note
that the packet includes the 4 byte CRC, which is included in the length.
The following sub-sections present details of how the write and read interfaces to the FIFO appear.
DS00002084C-page 118
2016-2017 Microchip Technology Inc.
UPD360
11.2.1.1
RX FIFO Write Interface
Figure 11-1 shows how the write interface (from receive hardware's perspective) appears at various points of reception.
FIGURE 11-1:
WRITE INTERFACE VIEW OF RX FIFO
during packet
reception
at SOP
after packet reception
Free Space
Ram Address
Ram Address
197Fh
Ram Address
197Fh
197Fh
<- Write Head Pointer Plus One
<- Write Head Pointer, Write Current Pointer
Free Space
CRC (4)
byte m
Free Space
<- Write Current Pointer
byte 0
Message
Header
byte 0
Message
Header
Nbytes*
Status*
CRC (4)
byte n
<- Write Current Pointer
<- Write Head Pointer Plus One
<- Write Head Pointer
Reserved for
Nbytes and Status
CRC (4)
Reserved for
Nbytes and Status
CRC (4)
<- Write Head Pointer Plus One
<- Write Head Pointer
byte n
byte n
byte 0
byte 0
byte 0
Message
Message
Message
Header
Nbytes*
Status*
Header
Nbytes*
Status*
Header
Nbytes*
Status*
Free Space
Free Space
Free Space
1900h
1900h
1900h
*assuming SMBus mode= 0
Each RX Packet is comprised of two bytes of control information and the received packet data. The Status byte indicates
whether the data is valid and the SOP type that was received. A value of 0x00 in the status byte implies that the data is
not valid (including the NBytes field).When bit 0 of the status byte is 1'b1, the Nbytes field indicates the length of the
packet and bits 6:4 of the status byte indicates the SOP type that was received. An empty FIFO always returns a value
of 0x00. However, the status byte should not be polled, but rather the RX_FIFO_NOT_EMPTY bit in the RX Interrupt
Status Register (RX_IRQ_STAT) should be used. The valid bit is retained for legacy compatibility. When software reads
the packet data from the FIFO, it should only read number of bytes indicated by Nbytes (in addition to the Nbytes and
Status entries). Note that the byte count indicated by NBytes includes the CRC32 data.
When SMBus mode is enabled (via the EN_SMBUS_MODE bit in the RX Control Register A (RX_CTL_A)), the Status
and Nbytes fields are swapped and Nbytes is incremented by 1 to include the status byte. The swapping makes the
(not-recommended) polling of the Status byte impossible for this mode. When software reads the packet data from the
FIFO, it should only read number of bytes indicated by NBytes (in addition to the Nbytes entry). Figure 11-2 details the
format while in SMBus mode.
FIGURE 11-2:
RX FIFO SMBUS MODE
after packet reception
Free Space
Ram Address
197Fh
<- Write Head Pointer Plus One
<- Write Head Pointer, Write Current Pointer
CRC (4)
byte m
byte 0
Message
Header
Status*
Nbytes*
CRC (4)
byte n
byte 0
Message
Header
Status*
Nbytes*
Free Space
1900h
SMBus mode = 1
2016-2017 Microchip Technology Inc.
DS00002084C-page 119
UPD360
The packet status and NBytes format are shown in Table 11-2 and Table 11-3, respectively.
TABLE 11-2: RXQ STATUS FIELD
Bits
Description
Type
7
RESERVED
Always reads 0.
RO
6:4
RX_SOP_TYPE
This field indicates the SOP type that was received.
000b: SOP
RO
001b: SOP'
010b: SOP''
011b: SOP'_Debug
100b: SOP''_Debug
101b - 111b: Reserved
3:1
0
RESERVED
RO
RO
Status
Status of queue data
0b: Data is invalid
1b: Data is valid
TABLE 11-3: RXQ NUMBER OF BYTES (NBYTES) FIELD
Bits
Description
Type
0
NBYTES
RO
If EN_SMBUS_MODE is 0, this field represents the number of bytes of valid data in the
packet.
If EN_SMBUS_MODE is 1, this field represents the number of bytes of valid data in the
packet plus 1.
When the device detects valid start-of-packet (SOP) signaling, the current write pointer is set to the write head pointer
plus 2. As packet data is received, it is written into the FIFO at the current write pointer and following each write the
current write pointer is incremented. The current write pointer points to the next location to be written. Upon reaching
the top of the RAM, the current write pointer wraps to 0. The byte count is maintained by the RX control block.
When a valid EOP is received and a good CRC residue is indicated by CRC logic, hardware will write the status (valid
bit and received SOP type) to the location addressed by the write head pointer and the number of received bytes to the
location addressed by the write head pointer plus one. SMBus mode will swap the data (and increment the number of
bytes). Following the writing of the status and length, the write head pointer is updated to the current write pointer and
the write head pointer plus one is updated to the current write pointer plus 1 (accounting for the wrap at the top of the
RAM).
If a valid EOP is not received and the bus becomes idle, then an abnormal termination is detected. In this case, the
packet is dropped, i.e., the device will not update the NBytes location or the Status location.
If a valid EOP is detected but the CRC generator indicates an invalid CRC, then the packet is corrupted. The device will
drop the packet and not update the NBytes location or the Status location.
If a more data is received than will fit in the FIFO, then an overrun is detected. The excess data does not get written into
the FIFO and the current write pointer is not incremented.
A separate test is made at the start of the packet to determine if there is sufficient room for the status and length bytes.
In the event of a “no room for header” condition, an overrun is detected. The excess data does not get written into the
FIFO and the current write pointer is not initialized.
If a packet has reached the maximum size allowed (as specified by the RX Maximum Packet Size Register (RX_MAX-
_SIZE)) and more data is received, then an oversize is detected. The excess data does not get written into the FIFO
and the current write pointer is not incremented.
DS00002084C-page 120
2016-2017 Microchip Technology Inc.
UPD360
All pointers consist of a RAM address and a wrap indication. The wrap indication is toggled each time the pointer wraps
past the top of the RAM. The wrap indication is used in the full, “no room for header” and empty comparisons to distin-
guish between the write pointers being a full RAM size ahead of the read pointer (full conditions in which case the wrap
toggles would be opposite) and the write pointers being equal to the read pointer (empty condition in which case the
wrap toggles would be equal).
All pointers and status bits are readable by the software. All pointers and wrap around status bits are writable by the
software. Software is responsible for maintaining coherency between the pointer and the wrap toggle values.
The FIFO pointers can be reset by setting and clearing the RST_RECEIVER bit in the RX Control Register A (RX_CT-
L_A).
11.2.1.1.1
Duplicate/Repeated Packet Handling
When the device is setup for automatic-response (sending of GoodCRC message), it may receive a packet multiple
times because the GoodCRC response was lost. If the original packet was received successfully then the subsequent
messages of that SOP type with matching message IDs are automatically dropped.
What the device does depends on the CRC status from CRC generator at EOP. If the CRC is good and the message
ID from current message matches that of the previous message (stored MSG_ID per SOP type), the device will not
update the Packet's status and length locations nor will it update the write head pointer and write head pointer plus one.
The FIFO space will be reclaimed at the start of the next packet. The RX_PKT_DROPPED bit in the RX Error Interrupt
Status Register (RX_ERR_IRQ_STAT) will be set to indicate this condition. The device will then resend a GoodCRC
response. If, however, the CRC generator indicates a bad CRC, or EOP is not received, the device will process the
packet like a corrupted packet. The stored MSG_ID will not be updated.
Note that a duplicate packet is dropped if Automatic Retry was enabled, the transmitter was waiting for a GoodCRC and
a message other than a GoodCRC was received (a protocol error).
The device maintains individual count of duplicate packets dropped (RX Duplicate Packet Count Register (RX_DUP_P-
KT_CNT)) and corrupt packets received (RX BadCRC Packet Count Register (RX_BADCRC_PKT_CNT)). If either of
these counts exceed 127, the DBG_EVENT bit in the RX Error Interrupt Status Register (RX_ERR_IRQ_STAT) will be
set.
11.2.1.1.2
GoodCRC Packet Storing and Dropping
In the case where Automatic Retry is enabled, and the transmitter was waiting for a GoodCRC, the GoodCRC response
will be dropped. The device will not update the packet's status and length locations nor will it update the write head
pointer and write head pointer plus one. The FIFO space will be reclaimed at the start of the next packet. Note that the
GoodCRC response is dropped even if the SOP type or message ID did not match the expected value.
Table 11-4 summarizes the conditions and results for storing or dropping good packets.
2016-2017 Microchip Technology Inc.
DS00002084C-page 121
UPD360
TABLE 11-4: CONDITIONS AND RESULTS FOR DROPPING GOOD PACKETS
Event
Result
IF
Received soft-reset with SOP of RX
matching SOP of TX
Packet stored
with error status
RX_PKT_STAT[2]
(PCOL_ERROR)
Expecting GoodCRC
Received GoodCRC with correct SOP
type and message ID
Packet dropped
Received GoodCRC with wrong SOP
type or wrong message ID
Received other than GoodCRC or Ping
with SOP or RX matching SOP of TX and
first message of this SOP type or mes-
sage ID not matching last message ID of
this SOP type (i.e., not a duplicate)
RX_PKT_STAT[2]
(PCOL_ERROR)
Packet stored,
with error status
ELSE IF
Received soft-reset
Auto Response Enabled
Received other than GoodCRC or soft-
reset and first message of this SOP type Packet stored,
message ID saved
Received other than GoodCRC or soft-
reset and message ID does not match
last message ID of this SOP type
Received other than GoodCRC or soft-
Packet dropped
RX_PKT_STAT[1]
reset and message ID matches last mes- with duplicate status (DUPLICATE_PACKET)
sage ID of this SOP type
Received GoodCRC
Packet stored
ELSE
Received other than GoodCRC
(including soft reset)
packet stored,
message ID saved
Received GoodCRC
Packet stored
Note:
If auto-response is enabled, any time a packet other than a GoodCRC is stored, a GoodCRC response is
transmitted.
DS00002084C-page 122
2016-2017 Microchip Technology Inc.
UPD360
11.2.1.2
RX FIFO Read Interface
Figure 11-3 shows how the read interface appears at various points of the software read.
FIGURE 11-3:
READ INTERFACE VIEW OF RX FIFO
after packet reception
Free Space
during packet read
Free Space
after 1st packet read
after 2st packet read
Ram Address
197Fh
Ram Address
197Fh
Ram Address
197Fh
Ram Address
197Fh
Free Space
<- Write Head Pointer,
Write Current Pointe,r
Read Pointer
<- Write Head Pointer,
Write Current Pointer
<- Write Head Pointer,
Write Current Pointer
<- Write Head Pointer,
Write Current Pointer
CRC (4)
byte m
CRC (4)
byte m
CRC (4)
byte m
byte 0
Message
Header
Nbytes*
Status*
CRC (4)
byte n
byte 0
Message
Header
Nbytes*
Status*
CRC (4)
byte n
byte 0
Message
Header
Nbytes*
Status*
<- Read Pointer
Free Space
<- Read Pointer
byte 0
Message
Header
Nbytes*
Status*
Free Space
Free Space
<- Read Pointer
1900h
Free Space
1900h
1900h
1900h
*assuming SMBus mode = 0
The RX FIFO read interface always uses a FIFO access mode. The read is destructive, returning the current data and
releasing the FIFO space. Although the software may rewind the read pointer for test purposes, there is no guarantee
that the data has not been overwritten.
After determining the validity of data in the FIFO queue by reading the RX_FIFO_NOT_EMPTY bit in the RX Interrupt
Status Register (RX_IRQ_STAT), software may read the data from the RX FIFO. Software may read the entire packet
without the need to recheck the RX_FIFO_NOT_EMPTY bit.
Although written as each byte is received, valid data in the FIFO is only indicated once the entire packet is received and
validated.
Depending on the setting of the EN_SMBUS_MODE bit in the RX Control Register A (RX_CTL_A), either the status or
the Nbytes field is read first, followed by the other. If SMBus mode is enabled, the Nbytes field is read first and will
include the status byte, otherwise it is read second and just indicates the packet length. Note that the packet includes
the 4 byte CRC and the length includes this.
As the FIFO is accessed, packet data is read from the FIFO at the read pointer and following each read the read pointer
is incremented. The read pointer points to the next location to be read. Upon reaching the top of the RAM, the read
pointer wraps to 0.
The FIFO space is released as the packet is read. There is no need for software to specifically release the buffer space.
If software needs to flush a packet without reading the data, it may do so by writing the RX FIFO Read Pointer Register
(RX_FIFO_RD_PTR) and RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS). Software
should add the appropriate value to the read pointer, taking into account the amount of data already read. Wrap at the
top of the RAM must be accounted, for both the read pointer and the RX_FIFO_RX_PTR_WRAP control bit. In order to
maintain coherency, the device will hold a write to the RX FIFO Read Pointer Register (RX_FIFO_RD_PTR) in a tem-
porary register and transfer it to the actual register when the RX FIFO Read Pointer Control Bits Register (RX_FI-
FO_RD_PTR_CTL_BITS) is written.
Although accessed as a FIFO, software can use any offset address in the 128 byte FIFO address range.
Although not recommended, the software can read from the FIFO if it is empty. The returned data will be 0 and the FIFO
will not underrun.
All pointers consist of a RAM address and a wrap indication. The wrap indication is toggled each time the pointer wraps
past the top of the RAM. The wrap indication is used in the full, “no room for header” and empty comparisons to distin-
guish between the write pointers being a full RAM size ahead of the read pointer (full conditions in which case the wrap
toggles would be opposite) and the write pointers being equal to the read pointer (empty condition in which case the
wrap toggles would be equal).
2016-2017 Microchip Technology Inc.
DS00002084C-page 123
UPD360
All pointers and status bits are readable by the software. All pointers and wrap around status bits are writable by the
software. Software is responsible for maintaining coherency between the pointer and the wrap toggle values.
The FIFO pointers can be reset by setting and clearing the RST_RECEIVER bit in the RX Control Register A (RX_CT-
L_A).
Each entry in the RX FIFO represents a byte of received data. Data written to the FIFO is the header, the payload, and
the CRC32. As stated earlier, only 5b symbols that correspond to valid D-codes are processed and written to the RX
Queue. K-Codes cannot be passed to the RX Queue, i.e., there is no “Raw Mode” receive capability. Software will see
de-framed packets only.
As mentioned earlier, the data in FIFO is the actual data and not symbols so it can be processed by software directly.
Corrupted packets are not written to the Queue.
11.2.2
RX CONTROL
RX Control implements the logic necessary for validating a received packet, updating the RX Queue status, and trigger-
ing automatic responses, if required.
11.2.2.1
Duplicate Packet Detection
For duplicate packet detection, the device maintains the last message ID received per SOP type. A flag (first_msg) is
maintained per SOP type and indicates if the stored last message ID is valid (there has been a previous packet). This
information is used when a good packet is received to detect if the message ID matches the last one received for that
SOP type.
The device stores the current message ID into the appropriate last message ID (as selected by the SOP of the current
received packet). The message ID and flag for a specified SOP type can be reset via the RX Message ID Stored Reg-
ister (RX_MSG_ID_STORED). All bits are cleared when software issues a SW_RESET or PD_RESET via the Reset
Control Register (RESET_CTL).
11.2.2.2
RX Control of Transmit Abort
Although the actual aborting of pending transmission is done by the Transmit Control block, it is the RX Control block
that makes the decision.
For pending transmissions (transmission triggered but waiting for bus idle or the bus turnaround time), the RX control
block generates a pulse at the EOP. It checks 1) that the packet is a good packet (good CRC, proper nibble alignment
and no symbol errors), 2) that the packet is not a Ping or GoodCRC message, 3a) that the SOP type of the received
packet matches the SOP type of the pending transmission or 3b) the SOP type of the received packet is SOP with the
SOP type of pending transmission being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit
in the TX Control Register A (TX_CTL_A)) and 4) that the packet is not a duplicate or is a Soft-Reset message.
For completed transmissions that are waiting for a GoodCRC to be returned, the RX Control checks 1) that the packet
is a good packet (good CRC, proper nibble alignment and no symbol errors), 2) that the packet is a Soft-Reset or is not
a GoodCRC message, 3a) that the SOP type of the received packet matches the SOP type of the pending transmission
or 3b) the SOP type of the received packet is SOP with the SOP type of pending transmission being non-SOP (the latter
can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and 4) that the
packet is not a duplicate.
11.2.3
RX COMM
The RX Comm is comprised of the clock and data recovery (CDR), RX DES (de-serializer) (serial-to-parallel converter,
4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to detect valid packet
reception.
11.2.3.1
CDR
The BMC decodes the received data and outputs the bit stream signal. This signal is applied to the input of CDR module
which locks (period and phase) on to the data stream during the preamble phase and outputs the serial data and a cap-
ture strobe centered in the data window.
The CDR relies on edge-to-edge time measurement (two bit-times) during the preamble phase for period lock. An aver-
age of four successive good period measurements is used for period lock. Valid period measurement is determined by
the range specified by the RX Maximum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MAX_BR) and RX
Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR). Phase lock is achieved by comparing in-
phase and quadrature data samples to determine whether the phase needs to be advanced or retarded.
DS00002084C-page 124
2016-2017 Microchip Technology Inc.
UPD360
11.2.3.2
RX DES (De-serializer)
The RX DES converts the received serial bit stream from the CDR into 5bit symbols, identifies and generates start-of-
packet/end-of-packet/hard and cable reset signals, and decodes the symbols to 4b data.
Note:
Note that only valid D-codes are processed to be written to the RX Queue. An invalid/reserved code is sim-
ply dropped.
11.2.3.2.1
SOP Detection
The SOP is detected by comparing the four most recently received 5-bit symbols to the expected SOP pattern. Per the
USB PD specification, detection of 3 of the 4 SOP symbols is sufficient. This is done by creating four unique groups
each containing three received symbols ({a,b,c}, {a,b,d}, {a,c,d} and {b,c,d}) with each group independently compared
to its respective symbols. Any successful match indicates an SOP.
There is a separate compare for each SOP type, enabled by the RX_SOP_ENABLE field in the RX Control Register B
(RX_CTL_B). The results are OR'ed. The SOP type is saved and used in the packet processing (auto reply, auto
response and queue status). Software is allowed to change the RX_SOP_ENABLE field at any time. The internal value
is held during active receive and updated from the register during idle time.
For generation of the RX_SOP interrupts in the RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT), each SOP
detection is decoded but is not AND'ed with its RX_SOP_ENABLE.
11.2.3.2.2
Reset Detection
Hard and Cable resets are detected by comparing the four most recently received 5-bit symbols to the expected pat-
terns. Per the USB PD specification, detection of 3 of the 4 symbols is sufficient. This is done by creating four unique
groups each containing three received symbols ({a,b,c}, {a,b,d}, {a,c,d} and {b,c,d}) with each group independently com-
pared to its respective symbols. Any successful match indicates a Hard or Cable reset respectively.
Cable Reset must be enabled via the EN_CABLE_RESET bit in the RX Control Register A (RX_CTL_A).
11.2.3.3
RX CRC32
The receive data CRC32 is computed by the RX CRC32 module. The same logic used for TX CRC generation is utilized
to calculate the RX CRC.
The coded nibble data is streamed into the RX CRC32 one nibble at a time for CRC calculation. When the packet ends,
the output of this module represents the computed CRC for the received packet. A value of 0xC704_DD7B indicates a
good CRC. Detection of a valid EOP symbol latches the CRC value. The latched value is compared with the expected
good CRC residue value, which is used by the RX Queue to determine if the RX Queue status should be updated to
reflect valid data or not.
2016-2017 Microchip Technology Inc.
DS00002084C-page 125
UPD360
11.3 PD MAC BIST
The PD MAC incorporates BIST functions as defined in the USB PD Specification. It is comprised of a TX and RX block.
The BIST TX block contains a PRBS (Pseudo Random Binary Sequence) generator, BIST pattern generation logic, and
its own bit-timing logic. The SOP type used by TX BIST Test Frames is a 20-bit static vector which is created by multi-
plexing between the five SOP ordered sets based on a register setting. The resultant 20-bit vector is simply bit selected
when the packet is transmitted.
BIST TX is entered when the BIST_EN bit in the BIST Control Register A (BIST_CTL_A) is set along with BIST_RX_EN
being clear. The BIST TX mode (TX type) is set using the BIST_TX_MODE field of the BIST Control Register A
(BIST_CTL_A) and is started by first using the BIST_TX_RST bit and then by using the BIST_TX_START/BIST_TX-
_STATUS bit of the BIST Control Register B (BIST_CTL_B). Continuous BIST transmission (modes 0, 1, 2, 3, and 5)
should be stopped by first using the BIST_TX_RST bit before clearing the BIST_EN bit. It may take up to 1 bit time for
the TX to stop. BIST_EN should not be cleared until after this time.
The BIST RX block contains a PRBS generator and bit error detection logic. BIST RX is used only during the BIST
Receiver Test. BIST RX is entered when the BIST_EN bit in the BIST Control Register A (BIST_CTL_A) is set along
with BIST_RX_EN. The BIST error counter is reset using the BIST_CLR_ERR_CNT bit of the BIST Control Register B
(BIST_CTL_B).
For information on the BIST registers, refer to Section 11.4.5, "PD MAC BIST Registers," on page 168.
DS00002084C-page 126
2016-2017 Microchip Technology Inc.
UPD360
11.4 Power Delivery MAC Registers
This section details the Power Delivery MAC registers. For an overview of the entire device register map, refer to Section
4.0, "Register Map," on page 19.
TABLE 11-5: POWER DELIVERY MAC REGISTER MAP
Address
Register Name (Symbol)
1800h – 1849h
PD MAC TX Queue/FIFO (74 bytes) (See Section 11.1.1, "TX Queue" for additional info)
184Ah – 18FFh Reserved for future expansion
1900h – 197Fh PD MAC RX FIFO (128 bytes) (See Section 11.2.1, "RX Queue" for additional info)
1980h – 19FFh Reserved for future expansion
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
TX Control Register A (TX_CTL_A)
TX Status Register (TX_STAT)
TX Parameters Register C (TX_PARAM_C)
TX Packet Length Register (TX_PKT_LEN)
TX Parameters Register A (TX_PARAM_A)
TX Control Register B (TX_CTL_B)
TX Parameters Register B (TX_PARAM_B)
TX Bit-Time Count Register (TX_BITTIME_CNT)
TX Turnaround Time Register (TX_TA_TIME)
TX Abort Status Register (TX_ABORT_STAT)
TX Auto-Response Abort Status Register (TX_AR_ABORT_STAT)
TX Power Up Time Register (TX_POWER_UP_TIME)
TX Power Down Time Register (TX_POWER_DOWN_TIME)
1A0Dh – 1A3Fh Reserved for future expansion
1A40h
1A41h
1A42h
1A43h
1A44h
1A45h
1A46h
1A47h
1A48h
1A49h
1A4Ah
1A4Bh
1A4Ch
1A4Dh
RX Control Register A (RX_CTL_A)
RX Control Register B (RX_CTL_B)
RX Maximum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MAX_BR)
RX Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR)
RX Status Register (RX_STAT)
RX Packet Status Register (RX_PKT_STAT)
RX tReceive Time Register (RX_TRECEIVE_TIME)
RX BadCRC Packet Count Register (RX_BADCRC_PKT_CNT)
RX Duplicate Packet Count Register (RX_DUP_PKT_CNT)
RX Hard Reset Detection Window Register (RX_HR_DET_WINDOW)
RX Last GoodCRC Packet High Byte Register (RX_LAST_GCRC_PKT_HI)
RX Last GoodCRC Packet Low Byte Register (RX_LAST_GCRC_PKT_LO)
RX Message ID Stored Register (RX_MSG_ID_STORED)
RX Maximum Packet Size Register (RX_MAX_SIZE)
1A4Eh – 1A4Fh Reserved for future expansion
1A50h
1A51h
1A52h
1A53h
RX FIFO Read Pointer Register (RX_FIFO_RD_PTR)
RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS)
RX FIFO Write Current Pointer Register (RX_FIFO_WR_CURRENT_PTR)
RX FIFO Write Current Pointer Control Bits Register
(RX_FIFO_WR_CURRENT_PTR_CTL_BITS)
1A54h
1A55h
1A56h
RX FIFO Write Head Pointer Register (RX_FIFO_WR_HEAD_PTR)
RX FIFO Write Head Pointer Control Bits Register (RX_FIFO_WR_HEAD_PTR_CTL_BITS)
RX FIFO Write Head Pointer Plus One Register (RX_FIFO_WR_HEAD_PTR_PLUS_ONE)
2016-2017 Microchip Technology Inc.
DS00002084C-page 127
UPD360
TABLE 11-5: POWER DELIVERY MAC REGISTER MAP (CONTINUED)
Address
Register Name (Symbol)
1A57h
RX FIFO Write Head Pointer Plus One Control Bits Register
(RX_FIFO_WR_HEAD_PTR_PLUS_ONE_CTL_BITS)
1A58h – 1A7Fh Reserved for future expansion
1A80h
1A81h
1A82h
1A83h
1A84h
1A85h
1A86h
1A87h
1A88h
1A89h
1A8Ah
1A8Bh
MAC Interrupt Status Register (MAC_IRQ_STAT)
TX Interrupt Status Register (TX_IRQ_STAT)
RX Interrupt Status Register (RX_IRQ_STAT)
RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)
Power Management Interrupt Status Register (PM_IRQ_STAT)
RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT)
TX Interrupt Enable Register (TX_IRQ_EN)
RX Interrupt Enable Register (RX_IRQ_EN)
RX Error Interrupt Enable Register (RX_ERR_IRQ_EN)
Power Management Interrupt Enable and Control Register (PM_IRQ_EN)
RX SOP Interrupt Enable Register (RX_SOP_IRQ_EN)
Reset Control Register (RESET_CTL)
1A8Ch – 1A9Fh Reserved for future expansion
1AA0h
1AA1h
1AA2h
1AA3h
1AA4h
1AA5h
1AA6h
1AA7h
1AA8h
1AA9h
BMC RX High Level Full Bit Maximum Time Register (BMC_RX_HI_FB_MAX_TIME)
BMC RX High Level Full Bit Minimum Time Register (BMC_RX_HI_FB_MIN_TIME)
BMC RX Low Level Full Bit Maximum Time Register (BMC_RX_LO_FB_MAX_TIME)
BMC RX Low Level Full Bit Minimum Time Register (BMC_RX_LO_FB_MIN_TIME)
BMC RX High Level Half Bit Maximum Time Register (BMC_RX_HI_HB_MAX_TIME)
BMC RX High Level Half Bit Minimum Time Register (BMC_RX_HI_HB_MIN_TIME)
BMC RX Low Level Half Bit Maximum Time Register (BMC_RX_LO_HB_MAX_TIME)
BMC RX Low Level Half Bit Minimum Time Register (BMC_RX_LO_HB_MIN_TIME)
BMC RX Squelch Assert Time Register (BMC_RX_SQL_ASSERT_TIME)
BMC RX Squelch Hold Time Register (BMC_RX_SQL_HOLD_TIME)
1AAAh – 1AAFh Reserved for future expansion
1AB0h
1AB1h
BMC TX Bit-Time Count Register (BMC_TX_BITTIME_CNT)
BMC Transition Window Time Register (BMC_TRANSITION_WINDOW_TIME)
1AB2h – 1ABFh Reserved for future expansion
1AC0h
1AC1h
1AC2h
1AC3h
BIST Control Register A (BIST_CTL_A)
BIST Control Register B (BIST_CTL_B)
BIST Error Count High Register (BIST_ERR_CNT_HI)
BIST Error Count Low Register (BIST_ERR_CNT_LO)
1AC4h – 1AC6h Reserved for future expansion
1AC7h
BIST RX Status Register (BIST_RX_STAT)
1AC8h – 1BFFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
DS00002084C-page 128
2016-2017 Microchip Technology Inc.
UPD360
11.4.1
PD MAC TX REGISTERS
The following sub-sections describe the various registers associated with the PD MAC TX logic.
11.4.1.1
TX Control Register A (TX_CTL_A)
Address:
1A00h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RETRY_ON_LINE_BUSY
RO
-
6
R/W
0b
Normally hardware will abort a TX packet (including all retry attempts) if the
line is Busy when hardware attempts to transmit the packet. (Note that trans-
mission of GoodCRC ACK in response for Soft Reset is an exception to this,
see the DIS_SPCL_SR_GCRC_ACK bit.)
Setting this bit will force hardware to not completely abort the transmission,
but rather it will retry the packet up to N_RETRY_CNT times. Failure after
N_RETRY_CNT times results in TX_FAILED status in the TX Interrupt Status
Register (TX_IRQ_STAT) rather than a TX_ABORTED status.
The following conditions will still abort the TX packet:
• Hard reset received
• Cable reset received (if enabled and the SOP type of the pending TX is
SOP', or SOP'', SOP'_Debug or SOP''_Debug)
• Good, non-duplicate, non-Ping, non-GoodCRC packet (including soft-
reset) received with RX and TX SOP types matching or RX SOP type
equaling SOP with TX SOP type not equaling SOP (can be disabled)
• Software sets the ABORT bit in the TX Control Register B (TX_CTL_B).
5
4
DIS_SOP_ABRTS_NON_SOP
R/W
R/W
0b
0b
Normally, when a SOP packet is received, a pending non-SOP packet (includ-
ing wait for a GoodCRC) will be aborted. When this bit is set, a non-SOP
packet will only be aborted by a packet with the same non-SOP type.
DIS_SPCL_SR_GCRC_ACK
Disable special treatment of GoodCRC ACK in response to Soft Reset.
By default, in auto-response mode a line busy condition will not abort Good-
CRC ACK transmission in response to Soft Reset reception. Setting this bit
will disable this behavior and instead GoodCRC ACK transmission for Soft
Reset will be processed the same as GoodCRC ACK for other packets.
Note:
When this bit is set, the WAIT4LINE_IDLE bit will affect GoodCRC
ACK for Soft Reset as well.
2016-2017 Microchip Technology Inc.
DS00002084C-page 129
UPD360
Bits
Description
Type
Default
3
WAIT4LINE_IDLE
R/W
0b
Normally hardware will abort a TX packet (including all retry attempt) if the line
is Busy when hardware attempts to transmit the packet. (Note that transmis-
sion of GoodCRC ACK in response for Soft Reset is an exception to this, see
the DIS_SPCL_SR_GCRC_ACK bit.)
Setting this bit will force hardware to not abort the transmission, but rather
wait until line becomes idle and then transmit the message. The
RETRY_ON_LINE_BUSY option has lower priority then this function.
The following conditions will still abort the TX packet:
• Hard reset received
• Cable reset received (if enabled and the SOP type of the pending TX is
SOP', or SOP'', SOP'_Debug or SOP''_Debug)
• Good, non-duplicate packet, non-Ping, non-GoodCRC (including soft-
reset) received with RX and TX SOP types matching or RX SOP type
equaling SOP with TX SOP type not equaling SOP (can be disabled)
• Software sets the ABORT bit in the TX Control Register B (TX_CTL_B).
2
EN_AUTO_RSP_MODE
Enable automatic sending of GoodCRC message and BIST Error Count mes-
R/W
0b
sage by hardware.
0: Auto GoodCRC Message disabled (default)
1: Auto GoodCRC Message enabled
Note:
Disabling Auto Response Mode will also disable automatic retry by
hardware, i.e., hardware will ignore the N_RETRY_CNT field of the
TX Parameters Register C (TX_PARAM_C).
1
0
EN_FMQ
R/W
R/W
0b
0b
Enable FIFO Mode queuing on the TX Queue's write interface.
0: Buffer Mode - TX Queue is accessed like a buffer/CSR (Default)
1: FIFO Mode
EN_RMDP
Enable Raw Mode Data Processing.
0: Automatic Mode Data Processing (default)
1: Enable Raw Mode Data Processing
DS00002084C-page 130
2016-2017 Microchip Technology Inc.
UPD360
11.4.1.2
TX Status Register (TX_STAT)
Address:
1A01h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RO
RO
-
6:4
N_HW_RETRIES
Number of attempts by hardware to send a message successfully.
000b
This field is automatically cleared when the GO bit in the TX Control Register
B (TX_CTL_B) is set.
This field is meaningful only if a TX was successful. It is informational only.
0: Initial message was successful. This value must be correlated with the
TX_ABORTED bit. If a TX message was aborted, this bit is meaningless.
>0: Number of retries performed by the device. The maximum value depends
on the N_RETRY_CNT field in the TX Parameters Register C
(TX_PARAM_C) register.
3:1
0
RESERVED
RO
RO
-
TX_ACTIVE
Transmitter is active.
0b
0: Transmitter is idle
1: Transmitter is active
Software can monitor this bit to determine if transmission is in progress. De-
assertion of this bit does not imply successful message transmission, only that
the transmitter is no longer active and has stopped transmitting.
2016-2017 Microchip Technology Inc.
DS00002084C-page 131
UPD360
11.4.1.3
TX Parameters Register C (TX_PARAM_C)
Address:
1A02h
Size:
8 bits
Bits
Description
Type
Default
7
PORT_DATA_ROLE
This field is used as the Port Data Role field for hardware generated packet
R/W
0b
header for packets that use SOP signaling.
0: UFP
1: DFP
Note:
SOP' and SOP'' always send a 0 bit for the Port Data Role.
6:4
N_RETRY_CNT
Number of retries allowed.
R/W
000b
Set this to zero to disable automatic hardware retry (i.e., when software will
take care of retries).
If N_RETRY_CNT is set to zero, but hardware is expected to wait for Good-
CRC, the EXPECT_GOODCRC bit should be set in the TX Parameters Reg-
ister A (TX_PARAM_A), otherwise TX will be considered complete as soon as
packet transmission is complete.
Note:
Hard and Cable Resets are not automatically retried since there is
no feedback to indicate a failure.
3
2
CABLE_PLUG
R/W
R/W
RO
0b
0b
-
This field is used as the Cable Plug field for hardware generated packet
header for packets that use SOP' and SOP'' signaling.
0: DFP or UFP
1: Cable Plug
PORT_POWER_ROLE
This field is used as the Port Power Role field for hardware generated packet
header for packets that use SOP signaling.
0: Sink
1: Source
1:0
RESERVED
DS00002084C-page 132
2016-2017 Microchip Technology Inc.
UPD360
11.4.1.4
TX Packet Length Register (TX_PKT_LEN)
Address:
1A03h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5:0
PKT_LEN
Queued packet length in bytes.
R/W
000000b
Hardware uses this value in Auto Mode to determine when to insert the CRC.
PKT_LEN = bytes in header + bytes in data objects
Note:
Note:
This applies to Auto Mode queue only and not to Raw Mode queue.
Raw Mode queue has special code to insert CRC and terminate
the transmission.
A value of '0' is invalid for this field.
11.4.1.5
TX Parameters Register A (TX_PARAM_A)
Address:
1A04h
Size:
8 bits
Bits
Description
Type
Default
7
EXPECT_GOODCRC
R/W
0b
This bit is used when the N_RETRY_CNT field in the TX Parameters Register
C (TX_PARAM_C) is set to zero but hardware is expected to wait for Good-
CRC in response to a TX message.
If N_RETRY_CNT is non-zero and EN_AUTO_RSP_MODE in the TX Control
Register A (TX_CTL_A) is set, then hardware automatically waits for Good-
CRC and this bit has no effect.
6:4
TX_SOP_SELECT
This field selects the SOP used for normal TX packets, for Returned BIST
R/W
000b
Counters packets (in response to RX BIST Test Frames) and for TX BIST Test
Frames.
This value is also used to verify the expected SOP type in the GoodCRC
response when Auto retry is enabled.
000: SOP
001: SOP'
010: SOP''
011: SOP'_Debug
100: SOP''_Debug
101 - 111: Reserved
Note:
For Auto retry mode, it is assumed that the expected SOP type is
also enabled in the RX Control Register B (RX_CTL_B).
2016-2017 Microchip Technology Inc.
DS00002084C-page 133
UPD360
Bits
Description
Type
Default
3
EN_FWTX
Enable software issued transmission.
R/W
0b
This bit is effective only at the moment the GO bit is set by software and is
intended to cover race conditions where it is not possible for software to back
off from setting the GO bit in response to a valid RX.
This bit is automatically held cleared by hardware if the RX Interrupt Status
Register (RX_IRQ_STAT) indicates reception of a Hard Reset, or a Cable
Reset, or if there is any data in the RX FIFO and, thus, software must set it
prior to each transmission it wants to issue.
When this bit is cleared, a software issued transmission will be aborted.
Note:
This is not an Abort bit. Clearing this bit will have no effect on a
transmission that has already been issued to hardware. Such
transmissions will be aborted automatically by hardware as appro-
priate. To abort a transmission in progress, use the ABORT bit in
the TX Control Register B (TX_CTL_B).
Note:
Note:
Setting of this bit does not prevent hardware issued transmissions.
This bit is reset by assertion of PD_RESET.
2:0
MSG_ID
R/W
000b
Message ID. This value is used to verify the expected message ID in the
GoodCRC response.
Note:
Note:
Hardware will not insert this value into the TX message header. For
proper normal operation, software must program the same value in
bits[11:9] of message header.
Software must set this to zero when it processes a Hard Reset,
Cable Reset or Soft Reset.
DS00002084C-page 134
2016-2017 Microchip Technology Inc.
UPD360
11.4.1.6
TX Control Register B (TX_CTL_B)
Address:
1A05h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
TX_CABLE_RESET
RO
-
5
W1S/SC
0b
Setting this bit to 1 together with the GO bit will cause hardware configured for
Auto Mode data processing to transmit a Cable Reset. Any data in the TX
Queue and related registers is ignored.
This bit is not applicable to Raw Mode data processing since Cable Reset
packets can be explicitly specified in the TX Queue. It is ignored for Raw
Mode.
This bit can only be set if the GO bit is not currently set.
The TX_HARD_RESET bit has precedence and if set along with this bit, this
bit will not set.
This bit is cleared by hardware at end of packet transmission. This bit is reset
by assertion of PD_RESET. Software can only write 1 to this bit and therefore
can not clear it once set.
Note:
Cable Reset is not automatically retried (there is no feedback to
indicate a failure). It is up to software to perform Cable Reset
retries.
Note:
This bit will be cleared upon completion of any packet transmis-
sion, so it should be set only after GO bit is cleared after completion
of the prior transmission.
4
OK_TO_TX
RO
1b
Channel is idle and it is OK to transmit. Software should monitor this bit before
setting the GO bit.
0: Software should not set the GO bit
1: Software can set the GO bit.
The following conditions will cause hardware to set this bit to 0:
• BMC line idle timer indicating line is busy.
• Hardware may be processing an automatic response to a received
packet.
3
RST_TXQ_FIFO_WRI_PTR
Setting this bit will reset the TX Queue's write interface FIFO pointer. When
WO
0b
using FIFO Mode Queuing, software must always write a '1' to this bit prior to
putting data in the FIFO.
Hardware does not latch this bit and it will read back as zero. Hardware may
automatically reset the pointer when the GO bit is cleared (i.e., hardware is
done with current transmission).
2016-2017 Microchip Technology Inc.
DS00002084C-page 135
UPD360
Bits
Description
Type
Default
2
TX_HARD_RESET
W1S/SC
0b
Setting this bit to 1 together with the GO bit will cause hardware configured for
Auto Mode data processing to transmit a Hard Reset. Any data in the TX
Queue and related registers is ignored.
This bit is not applicable to Raw Mode data processing since a Hard Reset
packet can be explicitly specified in the TX Queue. It is ignored for Raw Mode.
This bit can only be set if the GO bit is not currently set.
This bit is cleared by hardware at end of packet transmission. This bit is reset
by assertion of PD_RESET. Software can only write 1 to this bit and therefore
can not clear it once set.
Note:
Hard Reset is not automatically retried (there is no feedback to indi-
cate a failure). It is up to software to perform Hard Reset retries.
Note:
This bit will be cleared upon completion of any packet transmis-
sion, so it should be set only after the GO bit is cleared after com-
pletion of the prior transmission.
1
ABORT
WO
0b
Setting this bit will abort the current transmission in progress as soon as pos-
sible. Writing a '0' has not effect.
Hardware does not latch this bit and it will read back as zero.
Hardware will finish the current nibble transmission, send EOP, and then ter-
minate transmission. If this bit is set during preamble phase, then the current
bit of the preamble will be completed prior to termination.
Software should use the TX_EOP status bit in the TX Interrupt Status Register
(TX_IRQ_STAT) to determine when the current packet has been terminated.
0
GO
W1S/SC
0b
Writing a 1 to this bit will:
• Start transmission of the packet in the TX queue on to the wire or:
• Send Hard Reset if the TX_HARD_RESET bit of this register is set and
data processing mode is set to Auto (i.e., the EN_RMDP bit in the TX
Control Register A (TX_CTL_A) is not set).
• Send Cable Reset if the TX_CABLE_RESET bit of this register is set and
data processing mode is set to Auto (i.e., the EN_RMDP bit in the TX
Control Register A (TX_CTL_A) is not set).
Hardware will clear this bit when transmission is complete. This bit is reset by
assertion of PD_RESET. Software can only write 1 to this bit and therefore
can not clear it once set. Clearing of this bit by hardware does not indicate the
message was sent successfully.
Hardware may detect bus collision and abort transmission. In this case, the
TX_ABORTED bit in the TX Interrupt Status Register (TX_IRQ_STAT) will be
set and an interrupt to MCU will be generated.
DS00002084C-page 136
2016-2017 Microchip Technology Inc.
UPD360
11.4.1.7
TX Parameters Register B (TX_PARAM_B)
Address:
1A06h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
PREAMBLE_LEN
Number of preamble bits to send.
R/W
1000000b
Range: 1-127, specification: 64d (default)
A value of 0 is invalid and hardware does not check for validity. Software
should use the default value for normal operation.
Setting this field to an odd value will cause violation of the USB PD Specifica-
tion which states “The preamble shall start with a “0” and shall end with a “1”.”
An odd value will cause preamble to start with a value of “0” but it will also end
in a value of “0.” This may or may not lead to functional issues. This field
should be set to an even value to remain spec compliant.
11.4.1.8
TX Bit-Time Count Register (TX_BITTIME_CNT)
Address:
1A07h
Size:
8 bits
Bits
Description
Type
Default
7:0
BIT_TIME_CNT
R/W
00h
Bit-time counter value. The TX logic uses this value to determine the bit-time
for transmission (nominal bit rate is 300Kbps). This register can be used to
adjust bit-time for testing purpose (adjusting bitrate).
Count value is based on clock frequency and is given by:
((Clock Freq KHz / Bit Rate Kbps) - 1)
i.e.,
Clock Frequency = 48000KHz (48MHz)
Nominal Bit Rate = 300 Kbps
BIT_TIME_CNT = (48000 / 300) - 1 = 159
2016-2017 Microchip Technology Inc.
DS00002084C-page 137
UPD360
11.4.1.9
TX Turnaround Time Register (TX_TA_TIME)
Address:
1A08h
Size:
8 bits
This register controls the IFG timer.
Bits
Description
Type
Default
7:6
5:0
RESERVED
RO
-
TA_TIME
Turnaround time in us.
R/W
010101b
Range: 1-63, specification: 25us
A value of 0 is invalid and hardware does not check for validity.
Hardware uses a free running 1us pulse generator, thus, the value of this field
should be 1 more than desired to ensure the minimum time (26d).
11.4.1.10 TX Abort Status Register (TX_ABORT_STAT)
Address:
1A09h
Size:
8 bits
This field is used in conjunction with the TX_ABORTED interrupt and provides details for why the TX was aborted. Bits
in this register are sticky, i.e., once any bit is set by hardware this field cannot be updated by hardware until software
clears the field.
Note:
Bits in this register are set by hardware and must be cleared by software. The bits are not mutually exclu-
sive, i.e., more than one bit may be set depending on the circumstance.
Bits
Description
Type
Default
7
TX_ABORT_STAT[7]
R/W1C
0b
While waiting for GoodCRC, TX aborted due to Protocol Error (i.e., received
other than GoodCRC or Ping message while waiting for GoodCRC or Receiv-
ing a Hard or Cable Reset.)
6
5
TX_ABORT_STAT[6]
R/W1C
R/W1C
0b
0b
During software issued TX, TX was aborted due to RX (including Hard or
Cable Reset) while waiting for bus turnaround or waiting for line to go idle.
TX_ABORT_STAT[5]
Auto-retry aborted due to RX (including Hard or Cable Reset) while waiting for
bus turnaround or while waiting for line to go idle.
4
3
2
1
0
TX_ABORT_STAT[4]
R/W1C
RO
0b
-
Auto-retry aborted due to line being busy after bus turnaround.
RESERVED
TX_ABORT_STAT[2]
During software issued TX, line was busy after bus turnaround.
R/W1C
R/W1C
R/W1C
0b
0b
0b
TX_ABORT_STAT[1]
Software issued abort while software issued TX was in process.
TX_ABORT_STAT[0]
Software issued GO with TX disabled.
DS00002084C-page 138
2016-2017 Microchip Technology Inc.
UPD360
11.4.1.11 TX Auto-Response Abort Status Register (TX_AR_ABORT_STAT)
Address:
1A0Ah
Size:
8 bits
This field is used in conjunction with the AUTO_RSP_ABORTED interrupt and provides details for why the TX was
aborted. Bits in this register are sticky, i.e., once any bit is set by hardware this field cannot be updated by hardware
until software clears the field.
Note:
Bits in this register are set by hardware and must be cleared by software. The bits are not mutually exclu-
sive, i.e., more than one bit may be set depending on the circumstance.
Bits
Description
Type
Default
7
RESERVED
RO
-
6
TX_AR_ABORT_STAT[6]
Auto-response aborted due to RX (including Hard or Cable Reset) while wait-
ing for bus turnaround or while waiting for line to go idle.
R/W1C
0b
5:4
3
RESERVED
RO
R/W1C
RO
-
0b
-
TX_AR_ABORT_STAT[3]
Line was busy after bus turnaround time during auto-response.
2
RESERVED
1
TX_AR_ABORT_STAT[1]
R/W1C
RO
0b
-
Software issued abort while auto-response was in process.
0
RESERVED
11.4.1.12 TX Power Up Time Register (TX_POWER_UP_TIME)
Address:
1A0Bh
Size:
8 bits
Bits
Description
Type
Default
7:0
TX_POWER_UP_TIME
TX Power Up Time before transmitting (unit is 8 clock cycles).
Range: 0-255 (Actual time is 5 clocks larger.)
R/W
00h
The analog requires a minimum time of 5us to power up.
Count value is based on clock frequency and is given by:
TX_POWER_UP_TIME = power up time uS x Clock Freq MHz / 8
i.e.,
Clock Frequency = 48MHz
power up time = 5 uS
TX_POWER_UP_TIME = 5 x 48 / 8 = 30
2016-2017 Microchip Technology Inc.
DS00002084C-page 139
UPD360
11.4.1.13 TX Power Down Time Register (TX_POWER_DOWN_TIME)
Address:
1A0Ch
Size:
8 bits
Bits
Description
Type
Default
7:0
TX_POWER_DOWN_TIME
TX Power Down Time after transmitting (unit is 8 clock cycles).
Range: 0-255 (Actual time is 2 clocks larger.)
R/W
00h
The analog requires a minimum time of 1us before powering down.
Count value is based on clock frequency and is given by:
TX_POWER_DOWN_TIME = power down time uS x Clock Freq MHz / 8
i.e.,
Clock Frequency = 48MHz
power down time = 1 uS
TX_POWER_DOWN_TIME = 1 x 48 / 8 = 6
DS00002084C-page 140
2016-2017 Microchip Technology Inc.
UPD360
11.4.2
PD MAC RX REGISTERS
The following sub-sections describe the various registers associated with the PD MAC RX logic.
11.4.2.1
RX Control Register A (RX_CTL_A)
Address:
1A40h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5
4
EN_LOOPBACK
Enable loopback. This bit allows the MAC to receive its own transmission.
R/W
0b
0b
Note:
Loopback happens at the pin where TX and RX are connected
together.
EN_RCV
R/W
Enable Receiver. Software should set this bit when it is done configuring the
receiver. Setting this bit will enable the receiver to start normal operation.
If this bit is set while receive activity is in progress it will take effect after cur-
rent receive activity is over. If this bit is cleared while a receive is being pro-
cessed it will take effect after current receive is finished.
This bit will be automatically cleared by hardware upon reception of Hard
Reset or a Cable Reset to prevent normal packet reception.
After POR or SW_RESET, Hard and Cable Reset reception is disabled until
EN_RCV is set. Thereafter, clearing of EN_RCV (by software or hardware)
has no impact to reception of Hard or Cable Reset, i.e., hardware will process
Hard or Cable Reset even with EN_RCV cleared.
If software wishes to re-initialize receive timing parameters after EN_RCV has
been set once it must first reset the UPD_MAC_v2 using SW_RESET.
This bit is not reset by assertion of PD_RESET.
3
RST_RECEIVER
R/W
0b
Setting this bit will reset the receiver Queue. Software should set this bit if
receiver hardware may be out of sync with software. Hardware latches this bit
so it must be cleared by software to resume receiver operation. Receiver
hardware is also reset when PD_RESET bit in RESET_CTL register is set.
2016-2017 Microchip Technology Inc.
DS00002084C-page 141
UPD360
Bits
Description
Type
Default
2
EN_CRC_RCV_TMR
Enable CRCReceiveTimer.
R/W
0b
0: CRCReceiveTimer disabled (default)
1: CRCReceiveTimer Enabled
This bit is used by software only when it is not using auto-retry mode.
When auto-retry is enabled (EN_AUTO_RSP_MODE in the TX Control Regis-
ter A (TX_CTL_A) is set and N_RETRY_CNT is non-zero) or when the trans-
mitter is set to wait for the GoodCRC message (EXPECT_GOODCRC is set
and N_RETRY_CNT is zero), the CRCReceiveTimer is automatically enabled
in hardware. If GoodCRC message is not received prior to timer expiration,
then an interrupt will be generated. CRC_RCV_TIMEOUT bit in the TX Inter-
rupt Status Register (TX_IRQ_STAT) will be set.
If auto-retry and wait for GoodCRC are disabled, the software can set this bit
to enable CRCReceiveTimer prior to starting transmission to help time tRe-
ceive. Once enabled, the timer will start automatically at the end of transmis-
sion; however, software must disable the timer when a GoodCRC message is
received. If not disabled, timer expiration will generate an interrupt.
Once expired, the CRCReceiveTimer remains expired until start of another
packet transmission when it reloads.
This timer can also be used for BIST transmissions as the BISTReceiveError-
Timer.
1
0
EN_SMBUS_MODE
R/W
R/W
0b
0b
Enable SMBus block read FIFO format.
0: First location in packet is status, second location is packet length
1: First location in packet is packet length + 1, second location is status
EN_CABLE_RESET
Enable Cable Reset Detection.
0: Cable Reset Detection (default)
1: Cable Reset Detection Enabled
DS00002084C-page 142
2016-2017 Microchip Technology Inc.
UPD360
11.4.2.2
RX Control Register B (RX_CTL_B)
Address:
1A41h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RX_SOP_ENABLE
RO
-
6:2
R/W
00001b
SOP Types enabled to be received. Includes RX BIST Test Frames.
Bit 2 - SOP
Bit 3 - SOP'
Bit 4 - SOP''
Bit 5 - SOP'_Debug
Bit 6 - SOP''_Debug
Software is allowed to change the field at any time. An internal copy is held
during active receive and updated from the register during idle time
1:0
RESERVED
RO
-
11.4.2.3
RX Maximum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MAX_BR)
Address:
1A42h
Size:
8 bits
The value of this register, together with value of the RX Minimum Bit-Rate Bit Period Count Register
(RX_BIT_PER_CNT_MIN_BR), is used to determine valid bit-time (also referenced as bit-period) of the RX signal.
RX_BIT_PER_CNT_MIN_BR > valid bit time > RX_BIT_PER_CNT_MAX_BR.
Bits
Description
Type
Default
7:0
RX_BIT_PER_CNT_MAX_BR
Bit period count at maximum bit-rate.
R/W
00h
= (((clock_freq_KHz / max_bit_rate_Kbps) * (100 - tolerance) / 100) - 1)
WARNING: If macros are defined in C code, then math must be arranged so
that integer overflow does not occur.
2016-2017 Microchip Technology Inc.
DS00002084C-page 143
UPD360
11.4.2.4
RX Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR)
Address:
1A43h
Size:
8 bits
The value of this register, together with value of the RX Maximum Bit-Rate Bit Period Count Register
(RX_BIT_PER_CNT_MAX_BR), is used to determine valid bit-time (also referenced as bit-period) of the RX signal.
RX_BIT_PER_CNT_MIN_BR > valid bit time > RX_BIT_PER_CNT_MAX_BR.
Bits
Description
Type
Default
7:0
RX_BIT_PER_CNT_MIN_BR
Bit period count at minimum bit-rate.
R/W
00h
= (((clock_freq_KHz / min_bit_rate_Kbps) * (100 + tolerance) / 100) - 1)
WARNING: If macros are defined in C code, then math must be arranged so
that integer overflow does not occur.
11.4.2.5
RX Status Register (RX_STAT)
Address:
1A44h
Size:
8 bits
Bits
Description
Type
Default
7:2
RESERVED
RO
-
1
0
RX_IN_PROCESS
RO
RO
0b
0b
Receiver is active.
Hardware is receiving a packet, i.e., line is busy and transmitter is not active.
LINE_STATE
0: Line is idle
1: Line is busy (BMC line idle timer indicating line is busy)
If this bit is “1”, a receive might be in progress and software should wait for the
message reception to complete. If it is “0”, software may set the GO bit.
Hardware will take further action until the very last possible moment to avoid
bus contention. Bus contention is still possible and not 100% avoidable.
In cases where hardware takes preventative measures to avoid bus conten-
tion, the TX packet will be aborted. Software will be informed of this via an
interrupt and setting of the TX_ABORTED bit in the TX Interrupt Status Regis-
ter (TX_IRQ_STAT).
DS00002084C-page 144
2016-2017 Microchip Technology Inc.
UPD360
11.4.2.6
RX Packet Status Register (RX_PKT_STAT)
Address:
1A45h
Size:
8 bits
This register is applicable only when using auto-response/retry modes. This register is used in conjunction with the fol-
lowing bits to provide additional information regarding the status of a received packet:
• RX_DONE bit in the RX Interrupt Status Register (RX_IRQ_STAT)
• RX_PCOL_ERROR bit in the RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)
• RX_PKT_DROPPED bit in the RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)
• RX_BUF_OVR_RUN bit in the RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)
Bits in this register are sticky, i.e., once any bit is set by hardware this field cannot be updated by hardware until software
clears the field.
A value of 0x00 indicates no errors, while a value of 0xFF indicates that the packet status is currently unknown. Other
values are interpreted as specified in the bit definitions for this register.
Note:
Note:
There no status for having received a GoodCRC message with matching MSG_ID. Successful completion
of a TX is indication that a valid GoodCRC ACK was received.
Bits in this register are set by hardware and must be cleared by software. The bits are not mutually exclu-
sive, i.e., more than one bit may be set depending on the circumstance.
Bits
Description
Type
Default
7
RESERVED
RO
-
6
RX_PKT_STAT[6]
R/W1C
0b
ODD_NIBBLES. Received packet dropped because it had odd number of nib-
bles in data phase. Not set if RX_PKT_STAT[3] (RX_OVER_SIZE) is set
regardless of bad CRC, symbol errors or odd nibbles. RX_BAD_PKT interrupt
is asserted.
5
RX_PKT_STAT[5]
R/W1C
0b
SYM_ERROR. There was a symbol error in packet but BAD_CRC was not
reported. Not set if RX_PKT_STAT[3] (RX_OVER_SIZE) is set regardless of
bad CRC, symbol errors or odd nibbles. RX_BAD_PKT interrupt is asserted.
4
3
RX_PKT_STAT[4]
R/W1C
R/W1C
0b
0b
RX_FIFO_FULL. Received packet had to be dropped because the FIFO was
full either at SOP or during data. RX_BUF_OVR_RUN interrupt is asserted.
RX_PKT_STAT[3]
RX_OVER_SIZE. Received packet had to be dropped because it was larger
than the maximum size set in the RX Maximum Packet Size Register.
RX_BAD_PKT interrupt is asserted.
2
1
0
RX_PKT_STAT[2]
R/W1C
R/W1C
R/W1C
0b
0b
0b
PCOL_ERROR. Received other than GoodCRC or Ping message when
GoodCRC was expected. RX_PCOL_ERROR interrupt is asserted.
RX_PKT_STAT[1]
DUPLICATE_PACKET. Applicable to auto-response mode. RX_PKT_-
DROPPED interrupt is asserted.
RX_PKT_STAT[0]
BAD_CRC. RX packet had bad CRC. RX_BAD_PKT interrupt is asserted.
This bit is also forced set if symbol error or odd nibble count occurs. It is not
set if RX_PKT_STAT[3] (RX_OVER_SIZE) is set, regardless of bad CRC,
symbol errors or odd nibbles.
2016-2017 Microchip Technology Inc.
DS00002084C-page 145
UPD360
11.4.2.7
RX tReceive Time Register (RX_TRECEIVE_TIME)
Address:
1A46h
Size:
8 bits
Bits
Description
Type
Default
7:0
TRECEIVE
R/W
64h
CRCReceiveTimer timeout value (tReceive) in 10's of micro seconds.
Timeout value = field value * 10 (us)
Range: 0-255, specification: 900-1100us (90-110)
Note:
Note:
A value of 0 is invalid and hardware does not check for validity.
Hardware uses a free running 1us pulse generator, thus, this
CRCReceiveTimer may be 1us less than that expected.
Note:
Reset value is programmed to be 1000us (+/- 2%).
11.4.2.8
RX BadCRC Packet Count Register (RX_BADCRC_PKT_CNT)
Address:
1A47h
Size:
8 bits
This register keeps track of the number of packets received with bad CRC (any packet with valid SOP but bad CRC or
invalid EOP or symbol error). This register is for debug purpose only.
If enabled, an interrupt can be generated when the count of this register reaches 128.
Bits
Description
Type
Default
7:0
BADCRC_PKT_CNT
Number of bad packets received, i.e., with Bad CRC or invalid EOP or symbol
error.
R/WAC
00h
When the value of this register becomes greater than 127, the DBG_EVENT
bit in the RX Interrupt Status Register (RX_IRQ_STAT) will be set.
Any write to this register will clear all bits.
Note:
This register is not affected by packets received during BIST
Receiver Test. All these packets will be corrupted.
DS00002084C-page 146
2016-2017 Microchip Technology Inc.
UPD360
11.4.2.9
RX Duplicate Packet Count Register (RX_DUP_PKT_CNT)
Address:
1A48h
Size:
8 bits
This register keeps track of the number of the number of duplicate packets received. It is applicable only when Automatic
Response Mode is enabled. This register is for debug purpose only.
If enabled, an interrupt can be generated when the count of this register reaches 128.
Bits
Description
Type
Default
7:0
DUP_PKT_CNT
R/WAC
00h
Number of duplicate packets received. Applicable when Auto Response Mode
is enabled.
When the value of this register becomes greater than 127, the DBG_EVENT
bit in the RX Interrupt Status Register (RX_IRQ_STAT) will be set.
Any write to this register will clear all bits.
11.4.2.10 RX Hard Reset Detection Window Register (RX_HR_DET_WINDOW)
Address:
1A49h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
RX_HR_DET_WINDOW
Value of Hard Reset detection window in number of bits.
R/W
1011110b
This field determines when a detected Hard Reset or Cable Reset will be con-
sidered valid.
11.4.2.11 RX Last GoodCRC Packet High Byte Register (RX_LAST_GCRC_PKT_HI)
Address:
1A4Ah
Size:
8 bits
Bits
Description
Type
Default
7:0
RX_LAST_GCRC_PKT_HI
Bits [15:8] of received GoodCRC message.
RO
00h
This register is only valid when auto-retry is enabled. Since GoodCRC mes-
sage in auto-retry mode is not stored in the RX queue, this register provides a
means for software to examine the last GoodCRC message received.
2016-2017 Microchip Technology Inc.
DS00002084C-page 147
UPD360
11.4.2.12 RX Last GoodCRC Packet Low Byte Register (RX_LAST_GCRC_PKT_LO)
Address:
1A4Bh
Size:
8 bits
Bits
Description
Type
Default
7:0
RX_LAST_GCRC_PKT_LO
Bits [7:0] of received GoodCRC message.
RO
00h
This register is only valid when auto-retry is enabled. Since GoodCRC mes-
sage in auto-retry mode is not stored in the RX queue, this register provides a
means for software to examine the last GoodCRC message received.
11.4.2.13 RX Message ID Stored Register (RX_MSG_ID_STORED)
Address:
1A4Ch
Size:
8 bits
This register indicates if a last message ID was stored for each SOP type. A write to the appropriate bit will clear the
last stored message ID for the SOP type indicated. When cleared, the next packet received for the SOP type will not be
considered a duplicate. Software should clear the appropriate bit when it processes a Soft Reset.
Bits in this register are set by hardware and must be cleared by software.
This register is also cleared when software issues a SW_RESET or PD_RESET via the Reset Control Register
(RESET_CTL).
Bits
Description
Type
Default
7:5
RESERVED
RO
-
4:0
RX_MSG_ID_STORED
This field indicates that a last message ID was stored for the SOP type.
W1C
00000b
Bit 0: SOP
Bit 1: SOP'
Bit 2: SOP''
Bit 3: SOP'_Debug
Bit 4: SOP''_Debug
11.4.2.14 RX Maximum Packet Size Register (RX_MAX_SIZE)
Address:
1A4Dh
Size:
8 bits
The value of this register sets the maximum receive packet size, including the 4 bytes of CRC.
Bits
Description
Type
Default
7:0
RX_MAX_SIZE
Maximum receive packet size including the 4 byte CRC.
R/W
22h
DS00002084C-page 148
2016-2017 Microchip Technology Inc.
UPD360
11.4.2.15 RX FIFO Read Pointer Register (RX_FIFO_RD_PTR)
Address:
1A50h
Size:
8 bits
This register contains the RX FIFO read pointer. Software may update this register to flush a packet based on the known
packet length and starting point.
Software must keep the RX FIFO Read Pointer Control Bits Register coherent with this register if software were to
update this register.
In order to maintain coherency, writes to this register are held in a temporary register and are transferred to the actual
register when the RX FIFO Read Pointer Control Bits Register is written.
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
RX_FIFO_RD_PTR
This field contains the RX FIFO read pointer.
R/W
0000000b
11.4.2.16 RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS)
Address:
This register contains the auxiliary control bits of the RX FIFO read pointer.
Software must keep these bits coherent with the RX FIFO Read Pointer if software were to update the latter.
1A51h
Size:
8 bits
Bits
Description
Type
Default
7
RX_FIFO_EMPTY
RO
1b
This field indicates that the RX FIFO is empty (RX FIFO Write Head Pointer
equals the RX FIFO Read Pointer.)
6:2
1
RESERVED
RO
RO
-
RX_FIFO_RD_PTR_AT_TOP
This field indicates that the RX FIFO read pointer is at the top of the RAM
0b
(location 127).
0
RX_FIFO_RX_PTR_WRAP
This field toggles each time the RX FIFO read pointer wraps past the top of
R/W
0b
the RAM (location 127). If software updates the RX FIFO read pointer such
that it wraps, this bit must be toggled.
2016-2017 Microchip Technology Inc.
DS00002084C-page 149
UPD360
11.4.2.17 RX FIFO Write Current Pointer Register (RX_FIFO_WR_CURRENT_PTR)
Address:
1A52h
Size:
8 bits
This register contains the RX FIFO write current pointer. This pointer indicates where the next received byte of data will
be stored. This register is for debug and test purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
RX_FIFO_WR_CURRENT_PTR
This field contains the RX FIFO write current pointer.
R/W
0000000b
11.4.2.18 RX FIFO Write Current Pointer Control Bits Register
(RX_FIFO_WR_CURRENT_PTR_CTL_BITS)
Address:
1A53h
Size:
8 bits
This register contains the auxiliary control bits of the RX FIFO write current pointer. This register is for debug and test
purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
Type
Default
7
RX_FIFO_FULL
RO
0b
This field indicates that the RX FIFO is full (RX FIFO Write Current Pointer
equals the RX FIFO Read Pointer.)
6:2
1
RESERVED
RO
RO
-
RX_FIFO_WR_CURRENT_PTR_AT_TOP
This field indicates that the RX FIFO write current pointer is at the top of the
0b
RAM (location 127).
0
RX_FIFO_WR_CURRENT_PTR_WRAP
This field toggles each time the RX FIFO write current pointer wraps past the
R/W
0b
top of the RAM (location 127).
DS00002084C-page 150
2016-2017 Microchip Technology Inc.
UPD360
11.4.2.19 RX FIFO Write Head Pointer Register (RX_FIFO_WR_HEAD_PTR)
Address:
1A54h
Size:
8 bits
This register contains the RX FIFO write head pointer. This pointer indicates where the next received packet starts. This
register is for debug and test purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
RX_FIFO_WR_HEAD_PTR
This field contains the RX FIFO write head pointer.
R/W
0000000b
11.4.2.20 RX FIFO Write Head Pointer Control Bits Register (RX_FIFO_WR_HEAD_PTR_CTL_BITS)
Address:
1A55h
Size:
8 bits
This register contains the auxiliary control bits of the RX FIFO write head pointer. This register is for debug and test
purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
RX_FIFO_NO_ROOM_FOR_HEADER
Type
Default
7
RO
0b
This field indicates that the RX FIFO has no space for the RX header (status
and length) (RX FIFO Write Head Pointer equals the RX FIFO Read Pointer
or RX FIFO Write Head Pointer Plus One equals the RX FIFO Read Pointer).
6:3
2
RESERVED
RO
RO
-
RX_FIFO_WR_HEAD_PTR_AT_2ND_FROM _TOP
This field indicates that the RX FIFO write head pointer is one below the top of
0b
the RAM (location 126).
1
0
RX_FIFO_WR_HEAD_PTR_AT_TOP
RO
0b
0b
This field indicates that the RX FIFO write head pointer is at the top of the
RAM (location 127).
RX_FIFO_WR_HEAD_PTR_WRAP
This field toggles each time the RX FIFO write head pointer wraps past the top
R/W
of the RAM (location 127).
2016-2017 Microchip Technology Inc.
DS00002084C-page 151
UPD360
11.4.2.21 RX FIFO Write Head Pointer Plus One Register (RX_FIFO_WR_HEAD_PTR_PLUS_ONE)
Address:
1A56h
Size:
8 bits
This register contains the RX FIFO write head pointer plus one. This pointer indicates where the next received packet
starts plus one. This register is for debug and test purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
Type
Default
7
RESERVED
RO
-
6:0
RX_FIFO_WR_HEAD_PTR_PLUS_ONE
This field contains the RX FIFO write head pointer plus one.
R/W
0000001b
11.4.2.22 RX FIFO Write Head Pointer Plus One Control Bits Register
(RX_FIFO_WR_HEAD_PTR_PLUS_ONE_CTL_BITS)
Address:
1A57h
Size:
8 bits
This register contains the auxiliary control bits of the RX FIFO write head pointer plus one. This register is for debug and
test purpose only and should not normally be written.
Software must maintain coherency between this and the other Write Pointer Registers.
There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.
It is assumed that this register is only written while there is no active receive.
Bits
Description
Type
Default
7:1
RESERVED
RO
-
0
RX_FIFO_WR_HEAD_PTR_PLUS_ONE_WRAP
This field toggles each time the RX FIFO write head pointer plus one wraps
R/W
0b
past the top of the RAM (location 127).
DS00002084C-page 152
2016-2017 Microchip Technology Inc.
UPD360
11.4.3
PD MAC INTERRUPT STATUS AND ENABLE REGISTERS
The following sub-sections describe the various registers associated with the PD MAC interrupts.
Refer to Section 8.1, "System Interrupts," on page 35 for additional information on system level interrupt control.
11.4.3.1
MAC Interrupt Status Register (MAC_IRQ_STAT)
Address:
1A80h
Size:
8 bits
This register reflects the summary status of the various interrupt sources. If any of these bits are set, the MAC_INT inter-
rupt bit in the Interrupt Status Register (INT_STS) will be active (if enabled).
Bits in this register are read only and reflect the combined result of the other PD MAC interrupt status registers.
There is no corresponding enable register, since all interrupts have enables at lower levels of the hierarchy.
Bits
Description
Type
Default
7:5
RESERVED
RO
-
4
3
2
1
0
RX_SOP_IRQ_STAT
RO
RO
RO
RO
RO
0b
0b
0b
0b
0b
RX SOP status. This bit is set when any bit in the RX SOP Interrupt Status
Register (RX_SOP_IRQ_STAT) is set and enabled via the RX SOP Interrupt
Enable Register (RX_SOP_IRQ_EN).
This bit can only be cleared by clearing or disabling the bit(s) in the RX SOP
Interrupt Status Register (RX_SOP_IRQ_STAT).
PM_IRQ_STAT
Power Management status. This bit is set when any bit in the Power Manage-
ment Interrupt Status Register (PM_IRQ_STAT) is set and enabled via the
Power Management Interrupt Enable and Control Register (PM_IRQ_EN).
This bit can only be cleared by clearing or disabling the bit(s) in the Power
Management Interrupt Status Register (PM_IRQ_STAT).
RX_ERR_IRQ_STAT
RX Error status. This bit is set when any bit in the RX Error Interrupt Status
Register (RX_ERR_IRQ_STAT) is set and enabled via the RX Error Interrupt
Enable Register (RX_ERR_IRQ_EN).
This bit can only be cleared by clearing or disabling the bit(s) in the RX Error
Interrupt Status Register (RX_ERR_IRQ_STAT).
RX_IRQ_STAT
RX status. This bit is set when any bit in the RX Interrupt Status Register
(RX_IRQ_STAT) is set and enabled via the RX Interrupt Enable Register
(RX_IRQ_EN).
This bit can only be cleared by clearing or disabling the bit(s) in the RX Inter-
rupt Status Register (RX_IRQ_STAT).
TX_IRQ_STAT
TX status. This bit is set when any bit in the TX Interrupt Status Register
(TX_IRQ_STAT) is set and enabled via the TX Interrupt Enable Register
(TX_IRQ_EN).
This bit can only be cleared by clearing or disabling the bit(s) in the TX Inter-
rupt Status Register (TX_IRQ_STAT).
2016-2017 Microchip Technology Inc.
DS00002084C-page 153
UPD360
11.4.3.2
TX Interrupt Status Register (TX_IRQ_STAT)
Address:
1A81h
Size:
8 bits
This register reflects the status of various TX_IRQ_STAT sources. Whether an interrupt is generated or not depends on
the values in the TX Interrupt Enable Register (TX_IRQ_EN).
Bits in this register are set by hardware and must be cleared by software.
Bits
Description
Type
Default
7
AUTO_RSP_ABORTED
R/W1C
0b
A TX auto-response message was aborted. Reason for why the TX was
aborted may be determined by reading the TX Auto-Response Abort Status
Register (TX_AR_ABORT_STAT).
6
5
AUTO_RSP_SENT
R/W1C
R/W1C
0b
1b
Hardware has sent an auto-response. This bit is set when hardware is fin-
ished sending an auto-response.
OK_TO_TX
It is now OK to transmit. This bit is set when OK_TO_TX bit in TX Control
Register B (TX_CTL_B) changes from 0 to 1 indicating that it is OK for soft-
ware to initiate transmission.
4
CRC_RCV_TIMEOUT
CRC Receive Timer expired. This is a TX failure. This interrupt should be
R/W1C
0b
enabled only when Automatic Retry Mode is disabled.
The EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A) must
be set to enable the timer for use by software.
Note:
CRC Receive Timer is also used in BIST Mode to time reception of
BIST Error Count message.
3
TX_EOP
R/W1C
0b
Hardware is done sending a packet. Note this does not mean that a valid EOP
framing symbol was sent. It only means that packet transmission ended, i.e.,
transmitter was turned off.
This bit set after each TX attempt.
This can be used to signal when a Hard or Cable Reset is finished transmis-
sion since it does not have a GoodCRC response so the TX_DONE bit will not
be set - or if Auto Retry Mode is disabled in which case the hardware is done
when the transmitter turns off.
This bit is used by software to trigger internal timers. Software must be care-
fully when it enables/disables this interrupt because this bit is set after each
TX completion.
2
TX_ABORTED
R/W1C
0b
A TX message was aborted. Reason for why the TX was aborted may be
determined by reading the TX Abort Status Register (TX_ABORT_STAT).
DS00002084C-page 154
2016-2017 Microchip Technology Inc.
UPD360
Bits
Description
Type
R/W1C
Default
1
TX_FAILED
0b
Applicable in Auto Retry Mode only (or when GoodCRC timer is enabled).
This interrupt indicates a TX message request failed to complete for one of
the following reasons:
• GoodCRC timer expired
• Maximum number of retries exceeded
Note:
Software may enable the GoodCRC timer without enabling Auto
Retry. In this case this interrupt will be generated when GoodCRC
timer expires. It is software's responsibility to disable the Good-
CRC timer on reception of GoodCRC message to prevent genera-
tion of this interrupt.
0
TX_DONE
R/W1C
0b
Applicable in Auto Retry Mode only. A TX message request is successfully
completed, i.e., the message is acknowledged with GoodCRC by recipient.
This bit is not set for messages that don't get a GoodCRC message, i.e., Hard
or Cable Reset. TX_EOP should be used in such situations.
When Auto Retry Mode is disabled, TX_EOP should be used to determine
when packet is done transmitting.
11.4.3.3
RX Interrupt Status Register (RX_IRQ_STAT)
Address:
1A82h
Size:
8 bits
This register reflects the status of various RX_IRQ_STAT sources. Whether an interrupt is generated or not depends on
the values in the RX Interrupt Enable Register (RX_IRQ_EN).
Bits in this register are set by hardware and must be cleared by software.
Bits
Description
Type
Default
7
RX_FIFO_NOT_EMPTY
RO
0b
RX FIFO is not empty. This bit is set whenever the RX FIFO has data to be
read. Typically set when a valid packet is finished being received and cleared
once all data has been read.
Note:
This bit is read only and is cleared once the FIFO is empty.
6
LINE_WENT_IDLE
Line is now idle. This bit is set when hardware detects no activity on the PD
R/W1C
1b
bus.
Note:
This bit is not line status, it is an event. If line is already idle when
this interrupt is enabled, this bit will be set immediately. If line is
busy when this interrupt is enabled, this bit will be set when line
goes idle.
Software can use this to be informed when either TX is over or RX is over.
This will only work while clocks are enabled.
5
4
3
RX_CABLE_RST
R/W1C
RO
0b
-
Cable Reset Message received.
RESERVED
RX_HARD_RST
Hard Reset Message received.
R/W1C
0b
2016-2017 Microchip Technology Inc.
DS00002084C-page 155
UPD360
Bits
Description
Type
Default
2
RX_EOP
R/W1C
0b
Hardware detected valid EOP framing. A bad EOP or abnormal termination
will cause packet to be dropped.
This bit is set for only of frames that started with an SOP type that was
enabled via the RX Control Register B (RX_CTL_B).
1
0
RX_SOP
R/W1C
R/W1C
0b
0b
Hardware detected valid SOP framing sequence.
This bit is set for any SOP type that is enabled via the RX Control Register B
(RX_CTL_B).
RX_DONE
RX message is successfully received.
The following conditions apply:
• In Auto Retry Mode, expected GoodCRC messages are dropped and
therefore not indicated.
• In Auto Response Mode, duplicate packets are dropped and therefore not
indicated
Note:
In Auto Response Mode, this bit is set before the GoodCRC
response is sent and regardless of its successful transmission.
DS00002084C-page 156
2016-2017 Microchip Technology Inc.
UPD360
11.4.3.4
RX Error Interrupt Status Register (RX_ERR_IRQ_STAT)
Address:
1A83h
Size:
8 bits
This register reflects the status of various RX_ERR_IRQ_STAT sources. Whether an interrupt is generated or not
depends on the values in the RX Error Interrupt Enable Register (RX_ERR_IRQ_EN).
Bits in this register are set by hardware and must be cleared by software.
Bits
Description
Type
Default
7
DBG_EVENT
Debug event occurred:
R/W1C
0b
• Count of packets with bad CRC reached limit. Provides indication of link
quality.
• Count of duplicate packets reached limit. Provides indication dropped
GoodCRC packets by receiver.
Note:
Software must read both count registers in order to determine
which of the above two conditions caused the event.
Note:
Unlike other RX IRQ status bits, which are triggered by strobes,
this bit is persistent, i.e., if the register causing the interrupt is not
cleared prior to clearing the interrupt then this bit will set again.
6:4
3
RESERVED
RO
-
RX_BAD_PKT
R/W1C
0b
Received corrupt packet (Bad CRC, Symbol Error, Oversize or ODD nibble
count). RX_PKT_STAT[0] (BAD_CRC), RX_PKT_STAT[5] (SYM_ERROR),
RX_PKT_STAT[6] (ODD_NIBBLES) or RX_PKT_STAT[3] (RX_OVER_SIZE)
in the RX Packet Status Register (RX_PKT_STAT) will be set.
2
1
RX_BUF_OVR_RUN
R/W1C
R/W1C
0b
0b
Receiving packet but no buffer space available. In this case, the RX_PK-
T_STAT[4] (RX_FIFO_FULL) bit in the RX Packet Status Register (RX_PK-
T_STAT) will be set.
Received packet will be dropped.
RX_PCOL_ERROR
Applicable to Auto Retry Mode only. Hardware detected protocol error. i.e.,
received other than GoodCRC or Ping message when a GoodCRC message
was expected.
Received message will be placed in RXQ and RX_DONE be will be set.
Auto Retry will be aborted and TX_ABORTED bit will be set.
0
RX_PKT_DROPPED
RX packet is dropped due to:
R/W1C
0b
• Duplicate packet in Auto Response Mode
• GoodCRC message in Auto Retry Mode
2016-2017 Microchip Technology Inc.
DS00002084C-page 157
UPD360
11.4.3.5
Power Management Interrupt Status Register (PM_IRQ_STAT)
Address:
1A84h
Size:
8 bits
This register reflects the status of various PM_IRQ_STAT sources. Whether an interrupt is generated or not depends
on the values in the Power Management Interrupt Enable and Control Register (PM_IRQ_EN).
Bits in this register are set by hardware and must be cleared by software.
Bits
Description
Type
Default
7:1
RESERVED
RO
-
0
UPD_ACT_WS
R/W1C
0b
USB PD activity detected. Set asynchronously by assertion of the receive
input signal at the beginning of any activity.
To prevent metastability this interrupt should only be enabled when software
plans to stop the clocks.
Clearing the USB_PD_ACT_WS_EN bit will actually prevent this bit from
being set unlike the other interrupt status bits.
This bit is not affected by either UPD_CLK_STOP_EN or UPD_WU_EN.
USB PD Activity status is available in other register bits during normal opera-
tion.
11.4.3.6
RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT)
Address:
1A85h
Size:
8 bits
This register reflects the status of the occurrence of various received SOP types. The SOP type does not need to be
enabled via the RX Control Register B (RX_CTL_B) in order for a status bit to be set. Whether an interrupt is generated
or not depends on the value of the RX SOP Interrupt Enable Register (RX_SOP_IRQ_EN).
The bits in this register are not cascaded into the RX Interrupt Status Register but instead are enabled and OR'ed into
their own interrupt signal output.
Bits in this register are set by hardware and must be cleared by software.
Bits
Description
Type
Default
7:5
RESERVED
RX_SOP
RO
-
4:0
R/W1C
00000b
Hardware detected valid SOP framing sequence.
Bit 0: SOP
Bit 1: SOP'
Bit 2: SOP''
Bit 3: SOP'_Debug
Bit 4: SOP''_Debug
DS00002084C-page 158
2016-2017 Microchip Technology Inc.
UPD360
11.4.3.7
TX Interrupt Enable Register (TX_IRQ_EN)
Address:
1A86h
Size:
8 bits
Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-
ation is affected. The TX Interrupt Status Register (TX_IRQ_STAT) will still reflect the status of the event.
All interrupts are disabled after POR.
Bits
Description
Type
Default
7
AUTO_RSP_ABORTED_EN
Setting this bit enables the AUTO_RSP_ABORTED interrupt.
R/W
0b
6
5
4
3
2
1
0
AUTO_RSP_SENT_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
Setting this bit enables the AUTO_RSP_SENT interrupt.
OK_TO_TX_EN
Setting this bit enables the OK_TO_TX interrupt.
CRC_RCV_TIMEOUT_EN
Setting this bit enables the CRC_RCV_TIMEOUT interrupt.
TX_EOP_EN
Setting this bit enables the TX_EOP interrupt.
TX_ABORTED_EN
Setting this bit enables the TX_ABORTED interrupt.
TX_FAILED_EN
Setting this bit enables the TX_FAILED interrupt.
TX_DONE_EN
Setting this bit enables the TX_DONE interrupt.
11.4.3.8
RX Interrupt Enable Register (RX_IRQ_EN)
Address:
1A87h
Size:
8 bits
Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-
ation is affected. The RX Interrupt Status Register (RX_IRQ_STAT) will still reflect the status of the event.
All interrupts are disabled after POR.
Bits
Description
Type
Default
7
RX_FIFO_NOT_EMPTY_EN
Setting this bit enables the RX_FIFO_NOT_EMPTY interrupt.
R/W
0b
6
5
4
3
2
1
0
LINE_WENT_IDLE_EN
R/W
R/W
RO
0b
0b
-
Setting this bit enables the LINE_WENT_IDLE interrupt.
RX_CABLE_RST_EN
Setting this bit enables the RX_CABLE_RST interrupt.
RESERVED
RX_HARD_RST_EN
Setting this bit enables the RX_HARD_RST interrupt.
R/W
R/W
R/W
R/W
0b
0b
0b
0b
RX_EOP_EN
Setting this bit enables the RX_EOP interrupt.
RX_SOP_EN
Setting this bit enables the RX_SOP interrupt.
RX_DONE_EN
Setting this bit enables the RX_DONE interrupt.
2016-2017 Microchip Technology Inc.
DS00002084C-page 159
UPD360
11.4.3.9
RX Error Interrupt Enable Register (RX_ERR_IRQ_EN)
Address:
1A88h
Size:
8 bits
Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-
ation is affected. The RX Error Interrupt Status Register (RX_ERR_IRQ_STAT) will still reflect the status of the event.
All interrupts are disabled after POR.
Bits
Description
Type
Default
7
DBG_EVENT_EN
Setting this bit enables the DBG_EVENT interrupt.
R/W
0b
6:4
3
RESERVED
RO
-
RX_BAD_PKT_EN
Setting this bit enables the RX_BAD_PKT interrupt.
R/W
R/W
R/W
R/W
0b
0b
0b
0b
2
RX_BUF_OVR_RUN_EN
Setting this bit enables the RX_BUF_OVR_RUN interrupt.
1
RX_PCOL_ERROR_EN
Setting this bit enables the RX_PCOL_ERROR interrupt.
0
RX_PKT_DROPPED_EN
Setting this bit enables the RX_PKT_DROPPED interrupt.
11.4.3.10 Power Management Interrupt Enable and Control Register (PM_IRQ_EN)
Address:
1A89h
Size:
8 bits
Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-
ation is affected. The Power Management Interrupt Status Register (PM_IRQ_STAT) will still reflect the status of the
event.
All interrupts are disabled after POR. This register also enables clock start and stop requests.
Bits
Description
Type
Default
7:4
RESERVED
RO
-
3
UPD_CLK_STOP_EN
If this bit is set, the MAC, upon going idle, will request that the system clock be
stopped.
R/W
0b
If this bit is cleared, software is responsible to return the device to sleep mode.
This bit does not affect the wake up interrupt (UPD_ACT_WS) generation.
Note:
This bit does not affect the MAC's indication that it requires the
clock. Even if this bit is cleared, the MAC, once it is idle, will indi-
cate that it does not need the clock.
DS00002084C-page 160
2016-2017 Microchip Technology Inc.
UPD360
Bits
Description
Type
Default
2
UPD_WU_EN
R/W
0b
If this bit is set, the MAC, upon detecting receive activity, will request that the
system clock be started.
This bit does not affect the wake up interrupt (UPD_ACT_WS) generation.
Note:
Once clocks have been started, this bit does not affect the MAC's
indication that it requires the clock. Even if this bit is cleared, the
MAC, once it is non-idle (i.e. squelch is active), will indicate that it
requires the clock. Only the period between the asynchronous
wake up and the start of squelch is affected.
1
0
RESERVED
RO
-
USB_PD_ACT_WS_EN
Setting this bit enables the UPD_ACT_WS interrupt.
R/W
0b
11.4.3.11 RX SOP Interrupt Enable Register (RX_SOP_IRQ_EN)
Address:
1A8Ah
Size:
8 bits
Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-
ation is affected. The RX SOP Interrupt Status Register (RX_SOP_IRQ_STAT) will still reflect the status of the event.
All interrupts are disabled after POR.
Bits
Description
Type
Default
7:5
RESERVED
RX_SOP_EN
RO
-
4:0
R/W
00000b
Setting a bit enables the corresponding RX_SOP interrupt.
Bit 0: SOP
Bit 1: SOP'
Bit 2: SOP''
Bit 3: SOP'_Debug
Bit 4: SOP''_Debug
2016-2017 Microchip Technology Inc.
DS00002084C-page 161
UPD360
11.4.3.12 Reset Control Register (RESET_CTL)
Address:
1A8Bh
Size:
8 bits
Bits
Description
Type
Default
7
SW_RESET
R/W
0b
Software generated PD MAC reset. Software can use this bit to reset the PD
MAC to its POR state.
Software should toggle this bit, i.e., set it and clear it. After clearing this bit,
software will have to re initialize the PD MAC, including the BMC registers.
This bit is reset by RESET_N.
6
BMC_SW_RESET
R/W
0b
Software generated BMC reset. Software can use this bit to reset the BMC
encoder/decoder to its POR state.
Software should toggle this bit, i.e., set it and clear it. The BMC registers are
NOT affected by this reset.
5:1
0
RESERVED
RO
-
PD_RESET
R/W
0b
Software should set this bit when it is done processing a PD Hard Reset,
Cable Reset or Cable Reset so hardware can return to PD Reset state. Soft-
ware should toggle this bit, i.e., set it and clear it.
The following are reset by PD_RESET:
• RX_CTL FSM goes to POR state except Hard and Cable Reset process-
ing remains enabled if it was previously enabled by enabling the receiver.
• TX_CTL FSM goes to POR state.
• TX parallel to serial and 4b5b encoder
• TX Control Register B (TX_CTL_B) GO, TX_HARD_RESET, TX_CA-
BLE_RESET bits
• TX Parameters Register A (TX_PARAM_A) EN_FWTX bit
The following are not reset:
• All PD MAC registers, except as listed above.
• Various TX packet counters are NOT reset (NUM_PD_PACKETS_SENT,
NUM_MISSING_GCRC_MSG, NUM_MISSING_GCRC_MSG_SENT).
• Various RX packet counters are NOT reset (RX_BADCRC_PKT_CNT,
RX_DUP_PKT_CNT, NUM_PD_PACKETS_RECVD).
• RX FIFO is NOT reset.
• RX CDR, 4b5b decoder, and CRC are not reset.
• TX IFG timer and CRC are not reset.
• BIST and Power Management functions are not reset.
• BMC encoder/decoder.
DS00002084C-page 162
2016-2017 Microchip Technology Inc.
UPD360
11.4.4
PD MAC BMC ENCODER/DECODER REGISTERS
The following sub-sections describe the various registers associated with the PD MAC BMC Encoder/Decoder.
11.4.4.1
BMC RX High Level Full Bit Maximum Time Register (BMC_RX_HI_FB_MAX_TIME)
Address:
1AA0h
Size:
8 bits
The value of this register together with the value of the BMC RX High Level Full Bit Minimum Time Register (BMC_RX-
_HI_FB_MIN_TIME) is used by the BMC decoder to determine the valid full bit time for a high level RX signal. This time
should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_HI_FB_MAX_TIME > valid high time > BMC_RX_HI_FB_MIN_TIME
Bits
Description
Type
Default
7:0
BMC_RX_HI_FB_MAX_TIME
Time in clock cycles at minimum bit-rate and worst duty cycle distortion.
= (((clock_freq_KHz / min_bit_rate_Kbps) * (100 + tolerance) / 100) - 1)
R/W
00h
Note:
A value of 202 (decimal) is recommended for this field.
11.4.4.2
BMC RX High Level Full Bit Minimum Time Register (BMC_RX_HI_FB_MIN_TIME)
Address:
1AA1h
Size:
8 bits
The value of this register together with the value of the BMC RX High Level Full Bit Maximum Time Register (BMC_RX-
_HI_FB_MAX_TIME) is used by the BMC decoder to determine the valid full bit time for a high level RX signal. This time
should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_HI_FB_MAX_TIME > valid high time > BMC_RX_HI_FB_MIN_TIME
BMC_RX_HI_FB_MIN_TIME > BMC_RX_HI_HB_MAX_TIME
Bits
Description
Type
Default
7:0
BMC_RX_HI_FB_MIN_TIME
Time in clock cycles at maximum bit-rate and worst duty cycle distortion.
= (((clock_freq_KHz / max_bit_rate_Kbps) * (100 - tolerance) / 100) - 1)
R/W
00h
Note:
A value of 116 (decimal) is recommended for this field.
11.4.4.3
BMC RX Low Level Full Bit Maximum Time Register (BMC_RX_LO_FB_MAX_TIME)
Address:
1AA2h
Size:
8 bits
The value of this register together with the value of the BMC RX Low Level Full Bit Minimum Time Register (BMC_RX-
_LO_FB_MIN_TIME) is used by the BMC decoder to determine the valid full bit time for a low level RX signal. This time
should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_LO_FB_MAX_TIME > valid low time > BMC_RX_LO_FB_MIN_TIME
Bits
Description
Type
Default
7:0
BMC_RX_LO_FB_MAX_TIME
Time in clock cycles at minimum bit-rate and worst duty cycle distortion.
= (((clock_freq_KHz / min_bit_rate_Kbps) * (100 + tolerance) / 100) - 1)
R/W
00h
Note:
A value of 202 (decimal) is recommended for this field.
2016-2017 Microchip Technology Inc.
DS00002084C-page 163
UPD360
11.4.4.4
BMC RX Low Level Full Bit Minimum Time Register (BMC_RX_LO_FB_MIN_TIME)
Address:
1AA3h
Size:
8 bits
The value of this register together with the value of the BMC RX Low Level Full Bit Maximum Time Register (BMC_RX-
_LO_FB_MAX_TIME) is used by the BMC decoder to determine the valid full bit time for a low level RX signal. This time
should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_LO_FB_MAX_TIME > valid low time > BMC_RX_LO_FB_MIN_TIME
BMC_RX_LO_FB_MIN_TIME > BMC_RX_LO_HB_MAX_TIME
Bits
Description
Type
Default
7:0
BMC_RX_LO_FB_MIN_TIME
Time in clock cycles at maximum bit-rate and worst duty cycle distortion.
= (((clock_freq_KHz / max_bit_rate_Kbps) * (100 - tolerance) / 100) - 1)
R/W
00h
Note:
A value of 116 (decimal) is recommended for this field.
11.4.4.5
BMC RX High Level Half Bit Maximum Time Register (BMC_RX_HI_HB_MAX_TIME)
Address:
1AA4h
Size:
8 bits
The value of this register together with the value of the BMC RX High Level Half Bit Minimum Time Register (BMC_RX-
_HI_HB_MIN_TIME) is used by the BMC decoder to determine the valid half bit time for a high level RX signal. This
time should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_HI_HB_MAX_TIME > valid high time > BMC_RX_HI_HB_MIN_TIME
Bits
Description
Type
Default
7:0
BMC_RX_HI_HB_MAX_TIME
Time in clock cycles at minimum bit-rate and worst duty cycle distortion.
=((1 / 2) * ((clock_freq_KHz / min_bit_rate_Kbps)*(100 + tolerance) / 100) - 1)
R/W
00h
Note:
A value of 110 (decimal) is recommended for this field.
11.4.4.6
BMC RX High Level Half Bit Minimum Time Register (BMC_RX_HI_HB_MIN_TIME)
Address:
1AA5h
Size:
8 bits
The value of this register together with the value of the BMC RX High Level Half Bit Maximum Time Register (BMC_RX-
_HI_HB_MAX_TIME) is used by the BMC decoder to determine the valid half bit-time for a high level RX signal. This
time should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_HI_HB_MAX_TIME > valid high time > BMC_RX_HI_HB_MIN_TIME
BMC_RX_HI_FB_MIN_TIME > BMC_RX_HI_HB_MAX_TIME
Bits
Description
Type
Default
7:0
BMC_RX_HI_HB_MIN_TIME
Time in clock cycles at maximum bit-rate and worst duty cycle distortion.
=((1 / 2) * ((clock_freq_KHz / max_bit_rate_Kbps)*(100 - tolerance) / 100) - 1)
R/W
00h
Note:
A value of 48 (decimal) is recommended for this field.
DS00002084C-page 164
2016-2017 Microchip Technology Inc.
UPD360
11.4.4.7
BMC RX Low Level Half Bit Maximum Time Register (BMC_RX_LO_HB_MAX_TIME)
Address:
1AA6h
Size:
8 bits
The value of this register together with the value of the BMC RX Low Level Half Bit Minimum Time Register (BMC_RX-
_LO_HB_MIN_TIME) is used by the BMC decoder to determine the valid half bit-time for a low level RX signal. This
time should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_LO_HB_MAX_TIME > valid low time > BMC_RX_LO_HB_MIN_TIME
Bits
Description
Type
Default
7:0
BMC_RX_LO_HB_MAX_TIME
Time in clock cycles at minimum bit-rate and worst duty cycle distortion.
=((1 / 2) * ((clock_freq_KHz / min_bit_rate_Kbps)*(100 + tolerance) / 100) - 1)
R/W
00h
Note:
A value of 110 (decimal) is recommended for this field.
11.4.4.8
BMC RX Low Level Half Bit Minimum Time Register (BMC_RX_LO_HB_MIN_TIME)
Address:
1AA7h
Size:
8 bits
The value of this register together with the value of the BMC RX Low Level Half Bit Maximum Time Register (BMC_RX-
_LO_HB_MAX_TIME) is used by the BMC decoder to determine the valid half bit-time for a low level RX signal. This
time should take into account both the bit rate range and duty cycle distortion of the received signal.
BMC_RX_LO_HB_MAX_TIME > valid low time > BMC_RX_LO_HB_MIN_TIME
BMC_RX_LO_FB_MIN_TIME > BMC_RX_LO_HB_MAX_TIME
Bits
Description
Type
Default
7:0
BMC_RX_LO_HB_MIN_TIME
Time in clock cycles at maximum bit-rate and worst duty cycle distortion.
=((1 / 2) * ((clock_freq_KHz / max_bit_rate_Kbps)*(100 - tolerance) / 100) - 1)
R/W
00h
Note:
A value of 48 (decimal) is recommended for this field.
2016-2017 Microchip Technology Inc.
DS00002084C-page 165
UPD360
11.4.4.9
BMC RX Squelch Assert Time Register (BMC_RX_SQL_ASSERT_TIME)
Address:
1AA8h
Size:
8 bits
The value of this register is used by the BMC decoder to determine when there is a valid signal. If three edges of the
receive signal are seen within this time, then the “squelch” goes active. This time should take into account the minimum
bit rate but does not need to account for the duty cycle distortion of the received signal.
Bits
Description
Type
Default
7:0
BMC_RX_SQL_ASSERT_TIME
Time in clock cycles x 4 at minimum bit-rate.
R/W
00h
assert time uS = (BMC_RX_SQL_ASSERT_TIME x 4 + 1) / clock_freq MHz
A typical assert time would be 3 maximum half bit times plus desired toler-
ance.
Note:
A value of 70 (decimal) is recommended for this field.
11.4.4.10 BMC RX Squelch Hold Time Register (BMC_RX_SQL_HOLD_TIME)
Address:
1AA9h
Size:
8 bits
The value of this register is used by the BMC decoder to provide time for the CDR circuit to output the final bit of data.
A typical hold time would be 1 maximum half bit time pulse desired tolerance.
Note:
The Squelch Drop time is based on the BMC RX Maximum High and Low Time registers.
Bits
Description
Type
Default
7:0
BMC_RX_SQL_HOLD_TIME
Time in clock cycles x 4 at minimum bit-rate.
R/W
00h
hold time uS = (BMC_RX_SQL_HOLD_TIME x 4 + 1) / clock_freq MHz
typical value = ((1 / 2) * ((clock_freq_KHz / min_bit_rate_Kbps) *
(100 + tolerance) / 100) - 1) / 4
Note:
A value of 23 (decimal) is recommended for this field.
DS00002084C-page 166
2016-2017 Microchip Technology Inc.
UPD360
11.4.4.11 BMC TX Bit-Time Count Register (BMC_TX_BITTIME_CNT)
Address:
1AB0h
Size:
8 bits
Bits
Description
Type
R/W
Default
7:0
BMC_TX_BIT_TIME_CNT
00h
Bit-time counter value. The BMC encoder uses this value to determine the bit-
timing for the last bit of data. This register can be used to adjust bit-time for
testing purpose (adjusting bitrate).
Count value is based on clock frequency and is given by:
((Clock Freq KHz / Bit Rate Kbps) - 1)
i.e.,
Clock Frequency = 48000KHz (48MHz)
Nominal Bit Rate = 300 Kbps
bit_time_cnt = (48000 / 300) - 1 = 159
Note:
A value of 159 (decimal) is recommended for this field.
11.4.4.12 BMC Transition Window Time Register (BMC_TRANSITION_WINDOW_TIME)
Address:
1AB1h
Size:
8 bits
The value of this register is used by the BMC decoder to determine when the line is IDLE. Detection is active when 3
transitions occur at the receiver within a time window of BMC_TRANSITION_WINDOW_TIME. After waiting
BMC_TRANSITION_WINDOW_TIME without detecting 3 transitions, the bus is considered idle. The USB PD Specifi-
cation calls for 12uS minimum and 20uS maximum.
Bits
Description
Type
Default
7:0
BMC_TRANSITION_WINDOW_TIME
Time in clock cycles x 4
R/W
00h
transition time uS = (BMC_TRANSITION WINDOW_TIME x 4) / clock_freq
MHz
Per the USB PD Specification, this value should be set between 12uS and
20uS. This would be a value between 144 and 240 at 48MHz.
Note:
Unlike the TX Turnaround Time Register (TX_TA_TIME), this hard-
ware does not use a pre-scaler, therefore the time specified is
accurate.
Note:
A value of 200 (decimal) is recommended for this field.
2016-2017 Microchip Technology Inc.
DS00002084C-page 167
UPD360
11.4.5
PD MAC BIST REGISTERS
The following sub-sections describe the various registers associated with the PD MAC Built-In Self Test (BIST).
11.4.5.1
BIST Control Register A (BIST_CTL_A)
Address:
1AC0h
Size:
8 bits
Bits
Description
Type
Default
7:5
RESERVED
RO
-
4
BIST_RX_EN
Enable BIST Receiver.
R/W
0b
Setting this bit will:
• Enable the BIST receiver.
• Reset the PRBS generator in the BIST RX logic so it is ready to compare
incoming BIST PRBS pattern.
• Reset the BIST error count registers (BIST Error Count High Register
(BIST_ERR_CNT_HI) and BIST Error Count Low Register (BIST_ER-
R_CNT_LO).
Normally this bit is set only when BIST receiver mode is required; however,
this bit can be set to enable loopback BIST testing by disabling Automatic
Response Mode and enabling the RX loopback (setting the EN_LOOPBACK
bit in the RX Control Register A (RX_CTL_A)).
This bit must be cleared and set by software every time a new BIST RX
request comes in.
Note:
In BIST loopback test mode, BIST TX must be manually triggered
for each TX packet since functional receiver path is disabled.
3
BIST_EN
R/W
0b
Enable BIST. Set this bit when BIST logic is activated.
This bit together with the EN_LOOPBACK bit in the RX Control Register A
(RX_CTL_A) is used by hardware to block received data from going into func-
tional path. This means that when loopback is enabled in BIST mode hard-
ware cannot detect hard reset.
This bit also powers up the BMC transmitter for BIST mode operation. Soft-
ware should set this bit for a sufficient amount of time (5us) before trigger
transmission of BIST frame via BIST_TX_START/BIST_TX_STATUS.
2:0
BIST_TX_MODE
Set BIST Test Mode. Only the following mode is supported:
R/W
000b
010b: BIST Carrier Test Mode-2 (alternating '1's and '0's)
All other modes are reserved and should not be used.
DS00002084C-page 168
2016-2017 Microchip Technology Inc.
UPD360
11.4.5.2
BIST Control Register B (BIST_CTL_B)
Address:
1AC1h
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
BIST_CLR_ERR_CNT
Clears the BIST error count registers BIST Error Count High Register
(BIST_ERR_CNT_HI) and BIST Error Count Low Register (BIST_ER-
R_CNT_LO).
RO
-
2
1
WO
0b
0b
BIST_TX_RST
WO
Reset the TX logic and PRBS generator. Software must set this bit once
before starting the BIST test, i.e., setting BIST_TX_START/BIST_TX_STA-
TUS bit for the first time.
Since this bit resets the PRBS generator it should not be set again until the
current BIST test is ended.
This bit is not latched and will always read '0'
The PRBS generator cannot be reset by BIST_TX_START/BIST_TX_STA-
TUS because that would reset it for each TX BIST frame.
This bit should be used to stop the continuous BIST TX mode (2). It may take
up to 1 bit time for the TX to stop. BIST_EN should not be cleared until after
this time.
Note:
If this bit is set simultaneously with BIST_TX_START/BIST_TX-
_STATUS, it takes precedence and will void BIST_TX_START/
BIST_TX_STATUS.
0
BIST_TX_START/BIST_TX_STATUS
Start BIST transmission. Setting this bit will trigger transmission of BIST
WO/RO
0b
frame.
This bit is not latched and reading it will return the status of current BIST
transmission.
Depending on BIST Mode, transmission will either continue indefinitely
(unless BIST_TX_RST is asserted) or stop after sending a BIST PRBS frame.
BIST does not support sending of next BIST frame automatically. It must be
triggered by software by first clearing and then re-setting this bit.
Note:
This bit cannot be set simultaneously with BIST_TX_RST.
BIST_TX_RST has precedence and will void BIST_TX_START/
BIST_TX_STATUS.
In BIST RX mode, hardware will automatically send the BIST Error Count
message if the EN_AUTO_RSP_MODE bit in the TX Control Register A
(TX_CTL_A) is set.
2016-2017 Microchip Technology Inc.
DS00002084C-page 169
UPD360
11.4.5.3
BIST Error Count High Register (BIST_ERR_CNT_HI)
Address:
1AC2h
Size:
8 bits
8 bits
8 bits
Bits
Description
Type
Default
7:0
BIST_ERR_CNT_HI[7:0]
Upper byte of BIST error count (bits 15-8) (BIST_ERR_CNT[15:8])
RO
00h
11.4.5.4
BIST Error Count Low Register (BIST_ERR_CNT_LO)
Address:
1AC3h
Size:
Bits
Description
Type
Default
7:0
BIST_ERR_CNT_LO[7:0]
Lower byte of BIST error count (bits 7-0) (BIST_ERR_CNT[7:0])
RO
00h
11.4.5.5
BIST RX Status Register (BIST_RX_STAT)
Address:
1AC7h
Size:
This register is used to help with functional testing. Hardware is configured to transmit BIST PRBS frames. At the same
time, loopback mode is enabled and BIST receive mode is enabled. Now when a PRBS frame is transmitted it is also
received and compared. This register provides information when the BIST PRBS frame is done receiving and whether
there were any errors detected.
Bits
Description
Type
Default
7:2
RESERVED
RO
-
1
BIST_RX_ERROR
This bit is valid only when BIST_RX_DONE bit is set.
RO
0b
A value of “0” indicates that BIST PRBS frame was received without errors.
A value of “1” indicates that BIST PRBS frame was received with errors.
0
BIST_RX_DONE
Successfully received a BIST RX FRAME.
R/W1C
0b
Writing a “1” to this bit will clear it.
DS00002084C-page 170
2016-2017 Microchip Technology Inc.
UPD360
12.0 USB PORT POWER CONTROLLER (PPC)
The device’s USB Port Power Controller (PPC) provides 3.0 A of continuous current (3.2 A max) on VBUS with precision
over-current limiting (OCL), under- and over-voltage lockout, and dynamic thermal management. The PPC also includes
a VBUS discharge function and constant current mode current limiting for BC 1.2 applications.
Note:
The PPC DC and AC parameters can be seen in Table 16-6, “Port Power Controller DC Parameters,” on
page 209 and Table 16-12, “Port Power Controller AC Parameters,” on page 212, respectively.
12.1 PPC Power States
The PPC provides the following power states:
• Sleep: This is the lowest PPC power state available. See Section 12.1.1, "Sleep State Operation" for additional
information.
• Error: This state is entered when a fault condition exists. The PPC interrupt status registers detail the error condi-
tion. See Section 12.1.3, "Error State Operation" for additional information.
• Active: In this state, the PPC is active and sourcing current to VBUS. No errors are present. This power state pro-
vides full functionality. While in this state, operations include activation of the port power switch and current limit-
ing. See Section 12.1.2, "Active State Operation" for additional information.
Note:
The PPC power state is reflected in the PWR_STATE[1:0] field of the PPC General Configuration 3 Reg-
ister (PPC_GENERAL_CFG3).
12.1.1
SLEEP STATE OPERATION
The PWR_EN pin (UPD360-A/UPD360-B operating in standalone DFP mode only) may be used to cause the PPC to
enter/exit sleep. When the PPC is in the Sleep state, the device will be in its lowest power state. The bypass switch, and
the port power switch will be disabled. VBUS will be near ground potential.
12.1.2
ACTIVE STATE OPERATION
When the PPC enters the Active state, the port power switch is closed. The PPC cannot be in the Active state (and
therefore, the port power switch cannot be turned on) if any of the following conditions exist:
• VS < VS_UVLO (2.5 V).
• PWR_EN is disabled (standalone DFP mode only).
12.1.3
ERROR STATE OPERATION
The PPC will enter the Error state from the Active state when any of the following events are detected:
• The maximum allowable internal die temperature tTSD has been exceeded.
• An over-current condition has been detected.
• An under-voltage condition on VS has been detected (see Section 12.2.1, "Under-Voltage Lockout on VS").
• A discharge error has been detected.
• An over-voltage condition on the VS pin.
When the PPC enters the Error state, the port power switch and the VBUS bypass switch will be disabled, and ALERT
is asserted (by default). They will remain off while in this power state. The PPC will leave this state as determined by
the fault handling selection.
With the Auto-recovery fault handler, the PPC will check that all of the error conditions have been removed. If all of the
error conditions have been removed, the PPC will return to the Active state. The ERR_RECOVER pin is used in stand-
alone DFP mode to select the auto-recovery algorithm.
12.2 Supply Voltages
12.2.1
UNDER-VOLTAGE LOCKOUT ON VS
The PPC requires a minimum voltage VS_UVLO (2.5 V) be present on the VS pin for the Active power state.
2016-2017 Microchip Technology Inc.
DS00002084C-page 171
UPD360
12.2.2
OVER-VOLTAGE DETECTION LOCKOUT ON VS
The port power switch will be disabled if the voltage on the VS pin exceeds a voltage VS_OV for longer than the specified
time tMASK (5 ms). This will cause the device to enter the Error state.
12.2.3
PWR_EN INPUT (UPD360-A/UPD360-B ONLY)
In standalone DFP mode, the PWR_EN pin enables the port power switch to be turned on if conditions are met. The
port power switch cannot be closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is
not necessarily closed (see Section 12.1.2, "Active State Operation"). The PWR_EN pin state will be ignored by the PPC
if the PIN_IGNORE configuration bit is set. Otherwise, the PWR_EN_SET configuration bit is checked along with the
PWR_EN pin.
12.3 USB Port Power Switch
To assure compliance to USB Type-CTM, the PPC contains a USB port power switch that supports trip current limiting
mode.
The current limit (ILIM) is set via the PWR_CAP0 and PWR_CAP1 pins (UPD360-A/UPD360-B only), and may also be
updated via the PPC Current Limit Register (PPC_CURRENT_LIMIT). The switch also includes soft start circuitry and
a separate short circuit current limit. The port power switch is on in the Active state (except when VBUS is discharging).
Note:
If a load that draws between 2 mAand 7 mAis connected to the port power switch, a voltage ripple between
40-90 mVPP is observed at the VBUS output. This behavior is normal and it does not affect the charging
process when a portable device is connected.
12.3.1
CURRENT LIMITING
The current limit (ILIM) is set via the PWR_CAP0 and PWR_CAP1 pins (UPD360-A/UPD360-B only). These pins are
read at device power-up. The current limit can be changed via the PPC Current Limit Register (PPC_CURRENT_LIMIT)
after power-up. However, the programmed current limit cannot exceed the hardware set current limit defined by the
PWR_CAP0 and PWR_CAP1 pins.
The UPD360 is pre-configured with appropriate settings to satisfy the USB Type-C™ current limiting requirements and
no register writes are necessary to use this internal 5V port power controller, when operating in standalone mode.
12.3.1.1
Short Circuit Output Current Limiting
Short circuit current limiting occurs when the output current is above the selectable current limit (PPC Current Limit Reg-
ister (PPC_CURRENT_LIMIT)). This event will be detected and the current will immediately be limited within the
tSHORT_LIM time. If the condition remains, the port power switch will flag an Error condition and enter the Error state.
12.3.1.2
Soft Start
When the PWR_EN control (UPD360-A/UPD360-B only) changes states to enable the port power switch, the PPC
invokes a soft start routine for the duration of the VBUS rise time (tR_BUS). This soft start routine will limit current flow
from VS into VBUS while it is active. This circuitry will prevent current spikes due to a step in the portable device current
draw.
In the case when a portable device is attached while the PWR_EN pin is already enabled (in standalone DFP mode), or
the PWR_EN_SET bit is enabled, if the bus current exceeds ILIM, the PPC current limiter will respond within a specified
time (tSHORT_LIM) and will operate normally at this point. The CBUS capacitor will deliver the extra current, if any, as
required by the load change.
12.3.1.3
Current Limiting Modes
The PPC current limiting operates in trip mode. This mode is active when the port power switch is closed. When oper-
ating in the Detect power state, the current capacity at VBUS is limited to IBUS_BYP”.
12.3.1.3.1
Trip Mode
When using trip current limiting, the PPC USB port power switch functions as a low resistance switch and rapidly turns
off if the current limit is exceeded. While operating using trip current limiting, the VBUS output voltage will be held rela-
tively constant (equal to the VS voltage minus the RON_PSW * IBUS current) for all current values up to the ILIM. If the
internal temperature exceeds tTSD threshold, the port power switch will open.
If the current drawn by a portable device exceeds ILIM, the following occurs:
DS00002084C-page 172
2016-2017 Microchip Technology Inc.
UPD360
1. The port power switch will be turned off (trip action).
2. The PPC will enter the Error state and assert ALERT.
3. The fault handling circuitry will then determine subsequent actions.
Figure 12-1 shows operation of current limits in trip mode with the shaded area representing the USB 2.0 specified
VBUS range. Dashed lines indicate the port power switch output will go to zero (e.g., trip) when ILIM is exceeded. Note
that operation at all possible values of ILIM are shown in Figure 12-1 for illustrative purposes only; in actual operation
only one ILIM can be active at any time.
FIGURE 12-1:
TRIP CURRENT LIMITING OPERATION
ILIM (Amps)
0.53
0.96 1.07 1.28
1.6
2.13
2.67
3.2
Operating
Current
5.25
5
4.75
= ILIM’s
Trip action
(ILIM = 0.53 A)
4
Trip action
(ILIM = 3.2 A)
3
2
1
0
Power Switch Voltage and Current Output
go to Zero when ILIM is Exceeded
0.96 1.07 1.28
1.6
2.13
2.67
3.2
0
0.53
IBUS (Amps)
2016-2017 Microchip Technology Inc.
DS00002084C-page 173
UPD360
Figure 12-2 illustrates the relationship between these USB port power profile parameters.
FIGURE 12-2:
PORT POWER PROFILE PARAMETERS EXAMPLE
ILIM (Amps)
0.53
0.96
1.28
2.13
2.67
3.2
1.6
5.25
5
4.75
4
3
2
1
0
IBUS_R2MIN
KEEP-OUT
Port Power Profile
Operating Region
Enforced KEEP-OUT
VBUS_MIN
0.96
1.28
1.6 2.13 2.67
3.2
0.53
0
IBUS (Amps)
DS00002084C-page 174
2016-2017 Microchip Technology Inc.
UPD360
12.3.2
THERMAL MANAGEMENT
The PPC utilizes internal thermal management:
12.3.2.1
Thermal Shutdown
The thermal management consists of a hardware implemented thermal shutdown corresponding to the maximum allow-
able internal die temperature (tTSD). If the internal temperature exceeds this value, the port power switches (both ports)
will immediately be turned off until the temperature is below tTSD - tTSD_HYST
.
12.3.3 VBUS DISCHARGE
The PPC will discharge VBUS through an internal 100 Ohm resistor when at least one of the following conditions occurs:
• The PWR_EN control (UPD360-A/UPD360-B only) is disabled (triggered on the inactive edge of the PWR_EN
control) (Standalone DFP mode only).
• The VS voltage drops below a specified threshold VS_UVLO (2.5 V) that causes the port power switch to be dis-
abled.
• When commanded into the Sleep power state.
• Upon recovery from the Error state.
• When commanded via the DISCHARGE bit.
• Any time that the port power switch is activated after the VBUS bypass switch has been on.
• Any time that the VBUS bypass switch is activated after the port power switch has been on.
When the VBUS discharge circuitry is activated, at the end of the tDISCHARGE time, the PPC will confirm that VBUS was
discharged. If the VBUS voltage is not below the VTEST level, a discharge error will be flagged (by setting theVBUS Dis-
charge Error bit in the Power Interrupt Status Register (PWR_INT_STS)) and the PPC will enter the Error state.
12.4 VBUS Bypass Switch
The device contains circuitry to provide VBUS current as shown in Figure 12-3. The VBUS bypass switch and the port
power switch are never both on at the same time.
FIGURE 12-3:
VBUS BYPASS SWITCH
Bypass
Switch
VS
VS
VBUS
VBUS
Port Power
Switch
2016-2017 Microchip Technology Inc.
DS00002084C-page 175
UPD360
12.5 Port Power Controller Registers
This section details the Port Power Controller registers. For an overview of the entire device register map, refer to Sec-
tion 4.0, "Register Map," on page 19.
TABLE 12-1: PORT POWER CONTROLLER REGISTER MAP
Address
Register Name (Symbol)
0400h
0401h
0402h
0403h
0404h
PPC VBUS Current Measurement Register (PPC_VBUS_CURRENT)
Reserved for future expansion
PPC VBUS Port Status Register (PPC_VBUS_PORT_STS)
PPC Interrupt Status Register 1 (PPC_INT_STS1)
PPC Interrupt Status Register 2 (PPC_INT_STS2)
0405h – 040Eh Reserved for future expansion
040Fh
0410h
0411h
0412h
0413h
0414h
PPC General Status Register (PPC_GENERAL_STS)
Reserved for future expansion
PPC General Configuration 1 Register (PPC_GENERAL_CFG1)
Reserved for future expansion
PPC General Configuration 3 Register (PPC_GENERAL_CFG3)
PPC Current Limit Register (PPC_CURRENT_LIMIT)
0415h – 07FFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
DS00002084C-page 176
2016-2017 Microchip Technology Inc.
UPD360
12.5.1
PPC VBUS CURRENT MEASUREMENT REGISTER (PPC_VBUS_CURRENT)
Address:
0400h
Size:
8 bits
This register stores the measured current value delivered to the external device via the VBUS pin. This value is updated
continuously while the device is in the Active power state. The bit weights are in mA and the range is from 0mA to
3400mA (1 LSB = 13.3mA).
This data will be cleared whenever the port power switch is turned off (or any time that VBUS is discharged).
Note:
This register’s data is not intended for use when current is <100mA.
Bits
Description
Type
Default
7
1706.2 mA
RO
0b
6
5
4
3
2
1
0
853.1 mA
426.6 mA
213.3 mA
106.6 mA
53.3 mA
26.7 mA
13.3 mA
RO
RO
RO
RO
RO
RO
RO
0b
0b
0b
0b
0b
0b
0b
12.5.2
PPC VBUS PORT STATUS REGISTER (PPC_VBUS_PORT_STS)
Address:
0402h
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
ALERT
RO
-
6
RO
0b
This bit is asserted when an error (ERR) occurs in the PPC. It also asserts the
PPC_INT bit in the Interrupt Status Register (INT_STS), if enabled.
This bit can also be configured to assert when the LOW_CUR (portable
device is pulling less current and may be finished charging) bit is set and
linked via the ALERT_LINK bit. The ALERT bit is de-asserted when all error
conditions that may assert it (error condition, and LOW_CUR if linked) have
been removed or reset as necessary.
5
4
RESERVED
RO
RO
-
CC_MODE
0b
Indicates that the IBUS current on VBUS has exceeded ILIM and sourcing
Region 2.
3:0
RESERVED
RO
-
2016-2017 Microchip Technology Inc.
DS00002084C-page 177
UPD360
12.5.3
PPC INTERRUPT STATUS REGISTER 1 (PPC_INT_STS1)
Address:
0403h
Size:
8 bits
Bits
Description
Type
Default
7
ERR
R/W1C
0b
Indicates that an error was detected on the VBUS pin and the PPC has
entered the Error state. Writing this bit to “1” will clear the Error state and
allows the PPC to return to the Active state. When written to “1”, all error con-
ditions are checked. If all error conditions have been removed, the PPC
returns to the Active state. This bit is set automatically by the PPC when the
Error state is entered. If any other bit is set in this register, the device will not
leave the Error state.
0: No errors are detected
1: One or more errors have been detected and the PPC has entered the Error
state.
6
5
RESERVED
RO
-
RESET
R/W1C
0b
Indicates that the PPC has just been reset and should be re-programmed.
This bit will set at power-up. This bit is cleared when written with “1” or when
the PWR_EN pin (UPD360-A/UPD360-B only) is toggled (standalone DFP
mode only). The ALERT bit is asserted when this bit is set. This data is
retained in the Sleep state.
4
3
2
MIN_KEEP_OUT
R/W1C
R/W1C
R/W1C
0b
0b
0b
Indicates that the V-I output on the VBUS pin has dropped below VBUS_MIN
.
This bit will be cleared when written with “1” if the error condition has been
removed or if the ERR bit is cleared. This bit will cause ALERT to be asserted
and the device to enter the Error state.
TSD
Indicates that the internal temperature has exceeded tTSD threshold and the
device has entered the Error state. This bit will be cleared when written with
“1” if the error condition has been removed or if the ERR bit is cleared. This bit
will cause ALERT to be asserted and the device to enter the Error state.
OVER_VOLT
Indicates that the VS voltage has exceeded the VS_OV threshold and the
device has entered the Error state. This bit will be cleared when written with
“1” if the error condition has been removed or if the ERR bit is cleared. This bit
will cause ALERT to be asserted and the device to enter the Error state.
1
0
RESERVED
R/W1C
R/W1C
0b
0b
OVER_ILIM
Indicates that the IBUS current has exceeded both the ILIM threshold (PPC
Current Limit Register (PPC_CURRENT_LIMIT)) and the IBUS_R2MIN1 thresh-
old settings (to cover the CC case) on the VBUS pin. This bit will be cleared
when written with “1” if the error condition has been removed or if the ERR bit
is cleared. This bit will cause ALERT to be asserted and the device to enter
the Error state.
DS00002084C-page 178
2016-2017 Microchip Technology Inc.
UPD360
12.5.4
PPC INTERRUPT STATUS REGISTER 2 (PPC_INT_STS2)
Address:
0404h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
VS_LOW
RO
-
5
4:0
R/W1C
0b
-
Indicates that the VS voltage is below the VS_UVLO (2.5 V) threshold and the
port power switch is held off. This bit is cleared automatically when the VS
voltage is above the VS_UVLO threshold.
RESERVED
RO
12.5.5
PPC GENERAL STATUS REGISTER (PPC_GENERAL_STS)
Address:
040Fh
Size:
8 bits
Bits
Description
Type
Default
7:5
RESERVED
CC_MODE
RO
-
4
R/W1C
0b
Indicates that the IBUS current has exceeded ILIM (PPC Current Limit Regis-
ter (PPC_CURRENT_LIMIT)). This bit identifies that the port power switch
current limiting circuitry has been activated and the switch is in current limit
mode. This bit will be ‘0’ when the port power switch is off.
3
2
PWR_EN
R/W1C
R/W1C
0b
0b
This bit reflects the port power switch control state. This bit is set and cleared
automatically as the PWR_EN pin (UPD360-A/UPD360-B only) and/or
PWR_EN_SET bit state changes.
LOW_CUR
Indicates that a portable device has reduced its charge current to below the
threshold on VBUS and may be finished charging. This bit is cleared when
written with “1” and will not cause the ALERT bit to be asserted unless the
ALERT_LINK bit is set.
1:0
RESERVED
RO
-
2016-2017 Microchip Technology Inc.
DS00002084C-page 179
UPD360
12.5.6
PPC GENERAL CONFIGURATION 1 REGISTER (PPC_GENERAL_CFG1)
Address:
0411h
Size:
8 bits
Bits
Description
Type
Default
7
ALERT_MASK
R/W
0b
Masks errors for all interrupts in the PPC Interrupt Status Register 1
(PPC_INT_STS1), except OVER_ILIM and TSD.
0: The ALERT bit in the PPC VBUS Port Status Register
(PPC_VBUS_PORT_STS) will be asserted if an error condition or indicator
even is detected.
1: The ALERT bit in the PPC VBUS Port Status Register
(PPC_VBUS_PORT_STS) will only assert if OVER_ILIM or TSD is detected.
6
ALERT_LINK
R/W
0b
Links the ALERT bit in the PPC VBUS Port Status Register
(PPC_VBUS_PORT_STS) to be asserted when the LOW_CUR bit is
asserted.
0: The ALERT bit in the PPC VBUS Port Status Register
(PPC_VBUS_PORT_STS) will not be asserted if the LOW_CUR indicator bit
is asserted.
1: The ALERT bit in the PPC VBUS Port Status Register
(PPC_VBUS_PORT_STS) will be asserted if the LOW_CUR indicator bit is
asserted.
5
DISCHARGE
R/W
0b
Forces the VBUS pin to be reset and discharged when the PPC is in the
Active state. Writing this bit to a logic “1” will cause the port power switch to be
opened and the discharge circuitry to activate to discharge VBUS. The port
power switch will remain open with the 100 ohm short to GND per the tDIS-
CHARGE time in the DISCHARGE_TIME_SEL[1:0] field. This bit is self-clear-
ing.
4
PWR_EN_SET
R/W
R/W
0b
Controls whether the port power switch may be turned on or not and affects
the power state. This bit is OR’ed with the PWR_EN pin (standalone DFP
mode only). Thus, either the PWR_EN pin or this bit must be ‘1’ to enable the
port power switch.
3:2
DISCHARGE_TIME_SEL[1:0]
This field sets the tDISCHARGE time as follows:
01b
00: 100 ms
01: 200 ms (default)
10: 300 ms
11: 400 ms
1:0
RESERVED
RO
-
DS00002084C-page 180
2016-2017 Microchip Technology Inc.
UPD360
12.5.7
PPC GENERAL CONFIGURATION 3 REGISTER (PPC_GENERAL_CFG3)
Address:
0413h
Size:
8 bits
Bits
Description
Type
Default
7
PIN_IGNORE
R/W
0b
When set, ignores the PWR_EN pin state (UPD360-A/UPD360-B only) when
determining the Active mode selection and power state.
6:5
4:3
RESERVED
RO
-
PWR_STATE[1:0]
R/W
00b
This field indicates the current PPC power state as detailed below. These bits
are set and cleared automatically as the power state changes.
00: Sleep
01: Detect
10: Active
11: Error
2
BOOST#
R/W
RO
0b
-
Indicates that the IBUS current is >2.0A on VBUS.
1:0
RESERVED
12.5.8
PPC CURRENT LIMIT REGISTER (PPC_CURRENT_LIMIT)
Address:
0414h
Size:
8 bits
This register controls the ILIM used by the port power switch. The contents of this register are retained in the Sleep state.
Refer to Section 12.3.1, "Current Limiting," on page 172 for additional information.
Bits
Description
Type
Default
7:3
RESERVED
RO
-
2:0
ILIM_VBUS[2:0]
Sets the ILIM value as follows:
R/W
Note 12-1
000: 530 mA
001: 960 mA
010: 1070 mA
011: 1280 mA
100: 1600 mA
101: 2130 mA
110: 2670 mA
111: 3200 mA
Note 12-1
When operating in Standalone DFP modes (UPD360-A/UPD360-B only), the default is defined by the
PWR_CAP0 and PWR_CAP1 pins.
2016-2017 Microchip Technology Inc.
DS00002084C-page 181
UPD360
13.0 POWER SWITCH
To enable the device to efficiently support dead battery use cases, an integrated power switch is provided to select
between two external +3.3V supplies:
• 3V3_ALW: +3.3V main power supply input to integrated power switch.
• 3V3_VBUS: +3.3V power supply input derived from VBUS to the integrated power switch.
The power switch allows the core to be powered from 3V3_ALW normally, and from 3V3_VBUS when 3V3_ALW is not
present. This effectively allows connection detection and system wakeup without external processor intervention (exter-
nal processor in sleep mode).
Attached to 3V3_ALW and 3V3_VBUS are two FET switches. The first FET switches have a diode across the output.
There are three voltage comparators. VBUS_PWRGD is on when 3V3_VBUS exceeds 2.7V. 3V3_ALW_PWRGD is on
when 3V3_ALW exceeds 2.7V. VCORE_PWRGD is on when the core voltage reaches an operational level.
If VCORE_PWRGD is not asserted, the part is held in reset. If both VBUS_PWRGD and 3V3_ALW_PWRGD are not
asserted, the part is held in reset, regardless of the state of the VCORE_PWRGD.
A block diagram of the internal power switch can be seen in Figure 13-1.
FIGURE 13-1:
POWER SWITCH BLOCK DIAGRAM
VSW
LDO
EN
1.8V Analog
1.8V Core
3V3_ALW
G
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD
VMUX_PWRGD
3V3_VBUS
3V3_ALWAYS_PWRGD
A
B
SWITCH
CONTROL
3V3_VBUS_PWRGD
VCORE_PWRGD
C
D
D
C
3V3_VBUS_PWRGD
DS00002084C-page 182
2016-2017 Microchip Technology Inc.
UPD360
13.1 Operation
13.1.1
POWER UP
When the device is powering up, both VBUS_PWRGD and 3V3_ALW_PWRGD are low. Under these conditions,
switches A and C are open, B and D are closed. The voltage going to the input of the core regulator is the higher of
3V3_ALW and 3V3_VBUS. The diodes prevent back drive.
FIGURE 13-2:
POWER SWITCH: POWERING UP
VSW
3V3_ALW
LDOs
EN
1.8V Analog
1.8V Core
G
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD=0
VMUX_PWRGD
3V3_VBUS
3V3_ALWAYS_PWRGD
A
B
C
D
3V3_VBUS_PWRGD
VCORE_PWRGD
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=0
2016-2017 Microchip Technology Inc.
DS00002084C-page 183
UPD360
13.1.2
3V3_ALW ONLY POWERS UP
In this case, only 3V3_ALW powers up (VBUS_PWRGD = 0 and 3V3_ALW_PWRGD = 1). When this occurs, FET
switch D is opened. After 50us, FET switch A is shorted. This sequence eliminates the possibility of back-drive when
the diode is shorted to eliminate the voltage drop.
FIGURE 13-3:
POWER SWITCH: POWERING UP STEP ONE
VSW
3V3_ALW-0.7V
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
G
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD=1
VMUX_PWRGD
3V3_VBUS
3V3_ALWAYS_PWRGD
A
B
3V3_VBUS_PWRGD
VCORE_PWRGD
SWITCH
CONTROL
C
D
D
C
VBUS_PWRGD=0
FIGURE 13-4:
POWER SWITCH: POWERING UP STEP TWO
VSW
3V3_ALW
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
G
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=1
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=0
DS00002084C-page 184
2016-2017 Microchip Technology Inc.
UPD360
13.1.3
VBUS ONLY POWERS UP
This is the opposite example from the previous case. In this case, only VBUS powers up (3V3_ALW_PWRGD = 0
throughout, and VBUS_PWRGD = 1 when the threshold is hit). Once VBUS_PWRGD is valid, the internal regulator is
turned on and normal operation begins. At no time during this process is the 3V3_ALW rail back driven.
FIGURE 13-5:
POWER SWITCH: VBUS ONLY POWER UP STEP ONE
VSW
3V3_VBUS-0.7V
LDOs
3V3_ALW
1.8V Analog
1.8V Core
EN
G
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD=0
VMUX_PWRGD
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
SWITCH
CONTROL
D
C
C
D
3V3_VBUS_PWRGD=1
FIGURE 13-6:
POWER SWITCH: VBUS ONLY POWER UP STEP TWO
VSW
3V3_VBUS
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD=0
VMUX_PWRGD
3V3_VBUS
3V3_ALWAYS_PWRGD
A
3V3_VBUS_PWRGD
VCORE_PWRGD
SWITCH
CONTROL
B
C
D
D
C
3V3_VBUS_PWRGD=1
2016-2017 Microchip Technology Inc.
DS00002084C-page 185
UPD360
13.1.4
VBUS POWERED UP FOLLOWED BY 3V3_ALW COMING UP
In this case, VBUS is already powered up and 3V3_ALW starts to come up (and will take over and power the core).
Figure 13-7 shows the VBUS only state.
FIGURE 13-7:
POWER SWITCH: VBUS FOLLOWED BY 3V3_ALW STEP ONE
VSW
3V3_VBUS
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS _PWRGD=0
3V3_VBUS
3V3_ALWAYS _PWRGD
A
B
C
D
3V3_VBUS_PWRGD
VCORE_PWRGD
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
Once 3V3_ALW_PWRGD is detected, FET switch C is opened. The diode is required because 3V3_ALW could be
greater than or less than VBUS. The voltage at the input to the LDO drops to 3V3_VBUS-0.7V.
FIGURE 13-8:
POWER SWITCH: VBUS FOLLOWED BY 3V3_ALW STEP TWO
VSW
3V3_VBUS-0.7
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=1
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
DS00002084C-page 186
2016-2017 Microchip Technology Inc.
UPD360
50us after FET C is opened, FET B is shorted. The two diodes ensure there is no back drive. The input to the core reg-
ulator will be at the higher voltage of VBUS - 0.7V or 3V3_ALW - 0.7V.
FIGURE 13-9:
POWER SWITCH: VBUS FOLLOWED BY 3V3_ALW STEP THREE
Higher of
3V3_VBUS-0.7
or
VSW
3V3_ALW-0.7
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=1
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
50us after FET B is shorted, FET D is opened. The core regulator input is now 3V3_ALW - 0.7V.
FIGURE 13-10:
POWER SWITCH: VBUS FOLLOWED BY 3V3_ALW STEP FOUR
VSW
3V3_ALW-0.7
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=1
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
2016-2017 Microchip Technology Inc.
DS00002084C-page 187
UPD360
In the final step, 50us after FET D is opened, FET A is shorted. The input to the core regulator now becomes 3V3_ALW.
FIGURE 13-11:
POWER SWITCH: VBUS FOLLOWED BY 3V3_ALW STEP FIVE
VSW
3V3_ALW
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=1
3V3_VBUS
VTR_PWRGD
A
B
C
D
SWITCH
CONTROL
VBUS_PWRGD
D
C
VCORE_PWRGD
3V3_VBUS_PWRGD=1
13.1.5
3V3_ALW POWERED UP FOLLOWED BY VBUS COMING UP
In this case, 3V3_ALW is already powered up and VBUS starts to come up. 3V3_ALW will remain the power source for
the core and no changes will be made to the FET switches.
13.1.6
POWERED UP WITH VBUS AND 3V3_ALW, VBUS GOING AWAY
In this case, 3V3_ALW and VBUS are both present. The core is always powered from 3V3_ALW. If VBUS goes away,
nothing changes in the voltage to the core. An interrupt will be generated to the processor to let it know that VBUS status
changed.
DS00002084C-page 188
2016-2017 Microchip Technology Inc.
UPD360
13.1.7
POWERED UP WITH VBUS AND 3V3_ALW, 3V3_ALW GOING AWAY
In this case, 3V3_ALW and VBUS are both present. The core is always powered from 3V3_ALW. If 3V3_ALW goes
away, the switch will first transition to the initial power on state, then transition to the VBUS only state.
FIGURE 13-12:
POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP ONE
VSW
3V3_ALW
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
G
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=(1
0)
3V3_VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
First FET A is opened. The voltage at the core regulator input goes to 3V3_ALW-0.7
FIGURE 13-13:
POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP TWO
VSW
3V3_ALW-0.7
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
3V3_ALWAYS_PWRGD=0
VMUX_PWRGD
3V3_ VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
SWITCH
CONTROL
B
C
D
D
C
3V3_VBUS_PWRGD=1
2016-2017 Microchip Technology Inc.
DS00002084C-page 189
UPD360
50uS later, the FET is closed. The voltage at the input of the core regulator will be the higher of 3V3_ALW-0.7 or 3V3_V-
BUS -0.7.
FIGURE 13-14:
POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP THREE
VSW
Higher of
3V3_ALW – 0.7
Or
3V3_VBUS – 0.7
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=0
3V3_ VBUS
3V3_ALWAYS_PWRGD
A
B
C
D
3V3_VBUS_PWRGD
VCORE_PWRGD
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
50uS later, FET B is opened. The voltage at the input of the core regulator is VBUS-0.7.
FIGURE 13-15:
POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP FOUR
VSW
3V3_VBUS-0.7V
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=0
3V3_ VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
D
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
DS00002084C-page 190
2016-2017 Microchip Technology Inc.
UPD360
50uS later, FET C is shorted. The voltage at the input of the core regulator is 3V3_VBUS.
FIGURE 13-16:
POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP FIVE
VSW
3V3_VBUS
LDOs
EN
1.8V Analog
1.8V Core
3V3_ALW
VCORE_PWRGD
B
A
VMUX_PWRGD
3V3_ALWAYS_PWRGD=0
3V3_ VBUS
3V3_ALWAYS_PWRGD
3V3_VBUS_PWRGD
VCORE_PWRGD
A
B
C
SWITCH
CONTROL
D
C
3V3_VBUS_PWRGD=1
13.2 Software Override
In the event that both 3V3_VBUS and 3V3_ALW are available, the Power Switch automatically selects 3V3_ALW for
operation. This can be overridden by the VBUS Switch Enable Override (VBUS_SW_EN_OVR) bit of the Power Switch
Control Register (PWR_SW_CTL), which forces the switch to operate off of VBUS. When this bit is set, the auto-switch
mechanism of the switch is disabled.
13.3 Power Switch Interrupts
The power switch interrupt alerts software to changes in the state of the Power Switch. These events are listed in the
Power Switch Interrupt Status Register (PWR_INT_STS). The interrupt persists until the asserted bits in the Power
Switch Interrupt Status Register (PWR_INT_STS) are cleared. Individual interrupt events can be a enabled via the
Power Switch Interrupt Enable Register (PWR_INT_EN). Power switch interrupt status sources are capable of triggering
asynchronous wakes.
13.4 Power Switch Registers
This section details the power switch registers. For an overview of the entire device register map, refer to Section 4.0,
"Register Map," on page 19.
TABLE 13-1: POWER SWITCH REGISTER MAP
Address
Register Name (Symbol)
Power Switch Control Register (PWR_SW_CTL)
1C00h
1C01h
1C02h
1C03h
1C04h
Power Switch Status Register (PWR_SW_STS)
Power Switch Interrupt Status Register (PWR_INT_STS)
Power Switch Interrupt Enable Register (PWR_INT_EN)
Power Switch State Status Register (PWR_SW_STATE_STS)
1C05h – 1FFFh Reserved for future expansion
2016-2017 Microchip Technology Inc.
DS00002084C-page 191
UPD360
13.4.1
POWER SWITCH CONTROL REGISTER (PWR_SW_CTL)
Address:
1C00h
Size:
8 bits
Bits
Description
Type
Default
7:2
RESERVED
RO
-
1
0
Power Switch Enable (PM_SW_ENB)
R/W
R/W
0b
0b
This active low signal enables the power switch.
VBUS Switch Enable Override (VBUS_SW_EN_OVR)
When this bit is asserted, the power switch utilizes the 3V3_VBUS supply. This
bit only has meaning if the device is currently operating on 3V3_ALW and the
VBUS supply is present.
This bit disables the auto-switch mechanism of the power switch.
13.4.2
POWER SWITCH STATUS REGISTER (PWR_SW_STS)
Address:
1C01h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5
3V3_ALW POR (3V3_ALW_RDY)
POR output from the main VBAT external supply. Active high when the supply
is above 2.85V. Active low when the supply drops below 2.7V.
RO
0b
4
3V3_VBUS POR (VBUS_RDY)
POR output from the VBUS external supply. Active high when the supply is
RO
0b
above 4V. Active low when the supply drops below 2.7V.
3
2
1
RESERVED
RO
RO
RO
-
PWR_RDY
1b
0b
Indicates power ready on VSW and VDD18 supplies.
3V3_ALW Switch Gate Off (3V3_ALW_SW_OKB)
Indicates state of VSW with respect to 3V3_ALW.
0: VSW < 3V3_ALW
1: VSW > 3V3_ALW
0
VBUS Switch Gate Off (VBUS_SW_OKB)
Indicates state of VSW with respect to VBUS.
RO
0b
0: VSW < VBUS
1: VSW > VBUS
DS00002084C-page 192
2016-2017 Microchip Technology Inc.
UPD360
13.4.3
POWER SWITCH INTERRUPT STATUS REGISTER (PWR_INT_STS)
Address:
1C02h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
RO
-
5
3V3_ALW to VBUS Switch Interrupt (3V3_ALW2VBUS_INTR)
This interrupt asserts after the power switch automatically transitions from
R/WC
0b
selecting 3V3_ALW to selecting VBUS as the power source.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
Note:
Assertion
of
the
VBUS
Switch
Enable
Override
(VBUS_SW_EN_OVR) bit causes this interrupt to assert.
4
VBUS to 3V3_ALW Switch Interrupt POR (VBUS23V3_ALW_INTR)
This interrupt asserts after the power switch automatically transitions from
R/WC
0b
selecting VBUS to selecting 3V3_ALW as the power source.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
Note:
Assertion
of
the
VBUS
Switch
Enable
Override
(VBUS_SW_EN_OVR) bit prevents assertion of this interrupt when
VBUS is lost and 3V3_ALW is present.
3
2
1
0
3V3_ALW Lost Interrupt (3V3_ALW_LOST_INTR)
R/WC
R/WC
R/WC
R/WC
0b
0b
0b
0b
This interrupt asserts when 3V3_ALW POR (3V3_ALW_RDY) transitions from
1 to 0. It indicates that the 3V3_ALW supply has been lost.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
3V3_ALW Ready Interrupt (3V3_ALW_RDY_INTR)
This interrupt asserts when 3V3_ALW POR (3V3_ALW_RDY) transitions from
0 to 1. It indicates that a 3V3_ALW supply has been detected.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
VBUS Lost Interrupt (VBUS_LOST_INTR)
This interrupt asserts when 3V3_VBUS POR (VBUS_RDY) transitions from
1to 0. It indicates that the VBUS supply has been lost.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
VBUS Ready Interrupt (VBUS_RDY_INTR)
This interrupt asserts when 3V3_VBUS POR (VBUS_RDY) transitions from 0
to 1. It indicates that a VBUS supply has been detected.
Write a ‘1’ to clear this bit. Writes of ‘0’ have no effect.
2016-2017 Microchip Technology Inc.
DS00002084C-page 193
UPD360
13.4.4
POWER SWITCH INTERRUPT ENABLE REGISTER (PWR_INT_EN)
Address:
1C03h
Size:
8 bits
Bits
Description
Type
Default
7:6
RESERVED
3V3_ALW2VBUS_EN
RO
-
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
When ‘0’, prevents the generation of this interrupt.
VBUS23V3_ALW_EN
When ‘0’, prevents the generation of this interrupt.
3V3_ALW_LOST_EN
When ‘0’, prevents the generation of this interrupt.
3V3_ALW_RDY_EN
When ‘0’, prevents the generation of this interrupt.
VBUS_LOST_EN
When ‘0’, prevents the generation of this interrupt.
VBUS_RDY_EN
When ‘0’, prevents the generation of this interrupt.
13.4.5
POWER SWITCH STATE STATUS REGISTER (PWR_SW_STATE_STS)
This register indicates the current state of the 3V3_ALW and 3V3_VBUS switches.
Address:
1C04h
Size:
8 bits
Bits
Description
Type
Default
7:2
RESERVED
RO
-
1
VBUS Switch State (3V3_VBUS_STATE)
0 = 3V3_VBUS switch is disabled.
RO
0b
1 = 3V3_VBUS switch is enabled.
0
3V3_ALW Switch State (3V3_ALW_STATE)
0 = 3V3_ALW switch is disabled.
RO
0b
1 = 3V3_ALW switch is enabled.
DS00002084C-page 194
2016-2017 Microchip Technology Inc.
UPD360
14.0 DISPLAYPORT HOT PLUG DETECT (HPD)
14.1 Overview
The device provides hardware offload support for detecting the state of a Display Port compliant HPD input pin to the
device.
The USB Type-C DisplayPort Alternate Mode Specification defines the HPD state in terms of two status flags:
• HPD_STATE: Indicates whether the HPD’s logical state is high or low (denoted as HPD_HIGH or HPD_LOW,
respectively). For the purposes of communicating the HPD state over USB, the logical state of HPD is considered
as remaining high while receiving an IRQ_HPD, and is low during the time that HPD is being de-bounced on a
new mechanical connection. The logical state of HPD transitions from high to low when a low level on the HPD link
has been detected for 2ms (i.e., longer than the maximum IRQ_HPD pulse detection time). The logical state of
HPD is unchanged during glitches (as specified in DP v1.3) on the HPD link.
• IRQ_HPD: Indicates an IRQ_HPD (i.e., a high-to-low transition on HPD followed by a low-to-high transition was
detected between 250us and 2ms later, as specified in DP v1.3).
Note:
The HPD pin is always configured as a push/pull driver.
14.2 HPD Receiver
The device provides HPD detection (input) via the HPD pin. HPD detection is enabled by setting HPD Enable bit and
configuring the HPD pin to be an input via HPD Configuration in HPD Control Register (HPD_CTL). Upon setting this
bit, the device continuously monitors the state of the HPD pin as follows:
• When an IRQ_HPD event occurs, the IRQ_HPD interrupt bit in HPD Interrupt Status Register (HPD_INT_STS)
will assert. IRQ_HPD is detected when HPD is initially high and de-asserts for a time greater than or equal to the
value in the IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME) and less than or equal to the value in the
IRQ_HPD Maximum Time Register (IRQ_HPD_MAX_TIME).
• When a Low to High transition is debounced and detected, the HPD_HIGH interrupt bit in HPD Interrupt Status
Register (HPD_INT_STS) will assert. HPD_HIGH is detected when the HPD pin is initially low and asserts for a
time greater than or equal to the value in the HPD High Detect Time Register (HPD_HIGH_DET_TIME).
• When a High to Low transition is debounced and detected, the HPD_LOW interrupt bit in HPD Interrupt Status
Register (HPD_INT_STS) will assert. HPD_LOW is detected when HPD pin is initially low and asserts for a time
greater than or equal to the value in the HPD Low Detect Time Register (HPD_LOW_DET_TIME).
APPLICATION NOTE: The HPD Interrupt Status Register (HPD_INT_STS) contents are reset to 00h when HPD
Enable is cleared.
APPLICATION NOTE: Enabled and asserted interrupts trigger the HPD_INT interrupt in the Interrupt Status Register
(INT_STS).
A mechanism has been added via the HPD Event Queue Register (HPD_QUEUE) to record up to four HPD events.
This function is enabled when HPD Enable is set and HPD Configuration indicates the HPD pin is operating as an input.
See Section 14.4.4, "HPD Event Queue Register (HPD_QUEUE)," on page 199 for additional details.
APPLICATION NOTE: The state of the HPD pin is available by reading HPD State in HPD Control Register
(HPD_CTL).
This feature is used as follows:
1. Software configures IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME), IRQ_HPD Maximum Time Reg-
ister (IRQ_HPD_MAX_TIME), HPD High Detect Time Register (HPD_HIGH_DET_TIME) and HPD Low Detect
Time Register (HPD_LOW_DET_TIME). To comply with the DisplayPort specification for IRQ_HPD, the
IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME) and IRQ_HPD Maximum Time Register (IRQ_HPD_-
MAX_TIME) should be configured to 250 us and 2 ms, respectively. Likewise, HPD Low Detect Time Register
(HPD_LOW_DET_TIME) should be configured to greater than 2 ms.
2. If desired, interrupts may be enabled by asserting the respective bits in the HPD Interrupt Enable Register
(HPD_INT_EN).
3. HPD Enable is set and HPD Configuration is cleared in the HPD Control Register (HPD_CTL).
2016-2017 Microchip Technology Inc.
DS00002084C-page 195
UPD360
4. When an Hot Plug event occurs, the HPD Event Queue Register (HPD_QUEUE) is updated and an interrupt will
assert if configured.
5. HPD state changes are reflected by assertion of QUEUE_NOT_EMPTY, HPD_HIGH, HPD_LOW and IRQ_HPD
bits in HPD Interrupt Status Register (HPD_INT_STS). They may cause assertion of HPD_INT in the Interrupt
Status Register (INT_STS), if enabled.
6. Software reads the HPD Event Queue Register (HPD_QUEUE) to determine the Hot Plug events received.
7. Software writes to the HPD Event Queue Register (HPD_QUEUE) and clears the valid entries.
14.3 HPD Transmission
The device provides HPD transmission (output) via the HPD pin. This is done via the HPD Control Register (HPD_CTL)
by setting both HPD Configuration and HPD Enable to “1”. The value driven on the HPD pin is controlled by HPD Output
Value.
Support is also provided for generating an IRQ_HPD. This is accomplished by programming the deassertion time in
HPD IRQ Generation Time Register (HPD_IRQ_GEN) and then setting Generate IRQ in HPD Control Register
(HPD_CTL). Generate IRQ self clears after the interrupt pulse is issued.
This feature is used as follows:
1. Configure the HPD pin as an output by setting HPD Configuration and HPD Enable in HPD Control Register
(HPD_CTL). The value for HPD is defined by the value programmed in HPD Output Value.
2. If it is desired to generate an IRQ_HPD, the HPD IRQ Generation Time Register (HPD_IRQ_GEN) must be pro-
grammed with the desired HPD deassertion time.
3. If it is desired to receive an interrupt upon generation of IRQ_HPD, the respective bit in the HPD Interrupt Enable
Register (HPD_INT_EN) should be enabled.
4. Software requests IRQ_HPD generation by setting Generate IRQ in the HPD Control Register (HPD_CTL). HPD
Output Value must also be set to 1b.
5. Upon generating the IRQ_HPD interrupt, the Generate IRQ bit will self clear.
6. The IRQ_HPD bit asserts in the HPD Interrupt Status Register (HPD_INT_STS) and shall cause assertion of the
HPD_INT interrupt in the Interrupt Status Register (INT_STS), if enabled.
14.4 DisplayPort HPD Registers
This section details the DisplayPort HPD registers. For an overview of the entire device register map, refer to Section
4.0, "Register Map," on page 19.
TABLE 14-1: DISPLAYPORT HPD REGISTER MAP
Address
Register Name (Symbol)
0C00h
0C01h
0C02h
0C03h
0C04h
0C05h
0C06h
0C08h
0C0Ah
HPD Control Register (HPD_CTL)
HPD Interrupt Status Register (HPD_INT_STS)
HPD Interrupt Enable Register (HPD_INT_EN)
HPD Event Queue Register (HPD_QUEUE)
IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME)
IRQ_HPD Maximum Time Register (IRQ_HPD_MAX_TIME)
HPD High Detect Time Register (HPD_HIGH_DET_TIME)
HPD Low Detect Time Register (HPD_LOW_DET_TIME)
HPD IRQ Generation Time Register (HPD_IRQ_GEN)
0C0Bh – 0FFFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
DS00002084C-page 196
2016-2017 Microchip Technology Inc.
UPD360
14.4.1
HPD CONTROL REGISTER (HPD_CTL)
Address:
0C00h
Size:
8 bits
Bits
Description
Type
Default
7
HPD State
Provides the state of the HPD pin.
RO
-
This bit resets to 0b when HPD Enable is cleared.
Note:
Note:
An IRQ_HPD event is recorded as an HPD_HIGH state.
This bit is valid when HP is configured as an input or output.
6:4
3
RESERVED
RO
-
HPD Output Value
This bit only has meaning when the HPD pin is configured as an output per
R/W
0b
HPD Configuration. Otherwise, it will always read 0b.
2
Generate IRQ
R/SC
0b
When set, the HPD pin generates an HPD IRQ by deasserting HPD for the
amount of time defined in the HPD IRQ Generation Time Register
(HPD_IRQ_GEN).
This bit only has meaning when the HPD pin is configured as an output per
HPD Configuration. Otherwise, it will always read 0b.
Note:
Note:
HPD Output Value must be set to 1b before using this feature.
Software may not change the state of this bit while HPD Enable is
set to 1b.
1
0
HPD Configuration
R/W
R/W
0b
0b
0: HPD is configured as an input
1: HPD is configured as an output
Note:
Software may not change the state of this bit while HPD Enable is
set to 1b.
HPD Enable
When set, the HPD pin is enabled.
2016-2017 Microchip Technology Inc.
DS00002084C-page 197
UPD360
14.4.2
HPD INTERRUPT STATUS REGISTER (HPD_INT_STS)
Address:
0C01h
Size:
8 bits
The contents of this register reset to 00h when the HPD Enable bit in the HPD Control Register (HPD_CTL) is cleared.
BITS
DESCRIPTION
TYPE
DEFAULT
7:4
RESERVED
RO
-
3
2
1
0
QUEUE_NOT_EMPTY
RO
0b
0b
0b
0b
Indicates that the HPD Event Queue Register (HPD_QUEUE) is not empty.
Note:
Note:
This interrupt is cleared after HPD Event Queue Register (HPD_-
QUEUE) is read.
This bit only has meaning when the HPD pin is configured as an
input.
HPD_HIGH
R/WC
R/WC
R/WC
When set, indicates that an HPD Low to High transition has been detected.
Note:
Note:
The source of this input is a pulse and does not persist after being
cleared.
This bit only has meaning when the HPD pin is configured as an
input.
HPD_LOW
When set, indicates that an HPD High to Low transition has been detected.
Note:
Note:
The source of this input is a pulse and does not persist after being
cleared.
This bit only has meaning when the HPD pin is configured as an
input.
IRQ_HPD
When set, indicates that an HPD IRQ has been detected.
Note:
Note:
The source of this input is a pulse and does not persist after being
cleared.
When the HPD pin is configured as an input, this bit indicates that
an IRQ_HPD has been detected. When the HPD pin is configured
as an output, this pin indicates that the request to generate an
IRQ_HPD has completed.
DS00002084C-page 198
2016-2017 Microchip Technology Inc.
UPD360
14.4.3
HPD INTERRUPT ENABLE REGISTER (HPD_INT_EN)
Address:
0C02h
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:4
RESERVED
HPD Interrupt Enable
RO
0h
3:0
R/W
0h
When “0”, prevents generation of the respective interrupt.
14.4.4
HPD EVENT QUEUE REGISTER (HPD_QUEUE)
Address:
0C03h
Size:
8 bits
This register implements a circular queue that records HPD events detected by the device.
As an event is detected, it is written into the next HPD Event status field that is available and initially starts at HPD Event
0 out of reset.
After this register is read, any entries with a valid HPD event field are cleared when software writes 01b into the respec-
tive locations. The device will keep track of the last valid entry and store the next received event into the next entry. For
example, if entries 0 and 1 are valid, the device will always place the next event into location 2, regardless of whether
or not entries 0 and 1 have been cleared by software.
The device will only add entries to empty fields. After writing to HPD Event 3, the device will write the next event into
HPD Event 0, if available.
Each field is encoded as follows.
• 00b: HPD event field is empty
• 01b: HPD_HIGH Detected
• 10b: HPD_LOW Detected
• 11b: HPD_IRQ Detected
When HPD Enable is set to 0b and/or HPD Configuration is set to 1b, this register will always read 00h.
After four HPD events are recorded, any future HPD events shall be ignored until HPD event locations are freed up by
software.
BITS
DESCRIPTION
TYPE
DEFAULT
7:6
HPD Event 3
HPD Event 2
HPD Event 1
HPD Event 0
R/WC
00b
5:4
3:2
1:0
R/WC
R/WC
R/WC
00b
00b
00b
2016-2017 Microchip Technology Inc.
DS00002084C-page 199
UPD360
14.4.5
IRQ_HPD MINIMUM TIME REGISTER (IRQ_HPD_MIN_TIME)
Address:
0C04h
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:0
IRQ HPD Minimum Time
R/W
0h
This field defines the minimum amount of time that HPD must be deasserted
for an IRQ event to be recognized. De-assertions for less than this amount of
time shall be ignored.
The programmed time is (50 us * IRQ_HPD_MIN_TIME) + 100 us.
Note:
Software may not change the state of this register while HPD
Enable is set to 1b.
14.4.6
IRQ_HPD MAXIMUM TIME REGISTER (IRQ_HPD_MAX_TIME)
Address:
0C05h
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:0
IRQ HPD Maximum Time
R/W
0h
This field defines the maximum amount of time that HPD shall be deasserted
for an IRQ event to be recognized. Assertions for more than this amount of
time shall not be determined to be an HPD interrupt event.
The programmed time is (50 us * IRQ_HPD_MAX_TIME) + 100 us.
Note:
Software may not change the state of this register while HPD
Enable is set to 1b.
14.4.7
HPD HIGH DETECT TIME REGISTER (HPD_HIGH_DET_TIME)
Address:
0C06h
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
HPD High Detect Time
This field defines the amount of time that HPD must be asserted, after initially
R/W
0h
being low, in order to detect an HPD_HIGH event.
The programmed time is (50 us * HPD_HIGH_DET_TIME) + 100 us.
Note:
Software may not change the state of this register while HPD
Enable is set to 1b.
DS00002084C-page 200
2016-2017 Microchip Technology Inc.
UPD360
14.4.8
HPD LOW DETECT TIME REGISTER (HPD_LOW_DET_TIME)
Address:
0C08h
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:0
HPD Low Detect Time
This field defines the amount of time that HPD must be deasserted, after ini-
R/W
0h
tially being high, in order to detect an HPD_LOW event.
The programmed time is (50 us * HPD_LOW_DET_TIME) + 100 us.
Note:
Software may not change the state of this register while HPD
Enable is set to 1b.
14.4.9
HPD IRQ GENERATION TIME REGISTER (HPD_IRQ_GEN)
Address:
0C0Ah
Size:
8 bits
BITS
DESCRIPTION
TYPE
DEFAULT
7:0
HPD IRQ Generation Time
R/W
0h
This field defines the amount of time, in units of 50 us, that HPD shall be deas-
serted after the Generate IRQ bit in the HPD Control Register (HPD_CTL) is
set.
After this amount of time, the HPD pin will be returned to the state defined in
HPD Output Value.
Note:
Software may not change the state of this register while HPD
Enable is set to 1b.
2016-2017 Microchip Technology Inc.
DS00002084C-page 201
UPD360
15.0 WATCHDOG TIMER (WDT)
15.1 General Description
The function of the Watchdog Timer (WDT) is to provide a mechanism to detect if the device has failed.
When enabled, the Watchdog Timer circuit will generate a WDT initiated system reset if the user program fails to reload
the WDT within a specified length of time known as the WDT Interval.
The Watchdog timer operates off of the 20 KHz Keep Alive Oscillator or 48 MHz Relaxation Oscillator depending on the
resolution selected by WDT_UNITS bit in Watchdog Control Register (WDT_CTL).
A watchdog timer initiated system reset is indicated by assertion of WDT_INT bit in the Interrupt Enable Register
(INT_EN). In order to clear the WDT_INT bit, the WDT_STS bit in Watchdog Control Register (WDT_CTL) must be
cleared.
15.2 WDT Operation
15.2.1
WDT ACTIVATION MECHANISM
The WDT is activated by the following sequence of operations during normal operation:
1. Clear the WDT_EN bit of Watchdog Control Register (WDT_CTL).
2. Load the Watchdog Load Register (WDT_LOAD) with the count value.
3. Set the WDT_EN bit of Watchdog Control Register (WDT_CTL).
The WDT Activation Mechanism starts the WDT decrementing counter.
15.2.2
WDT DEACTIVATION MECHANISM
The WDT is deactivated by clearing the WDT_EN bit in the Watchdog Control Register (WDT_CTL). The WDT Reload
Mechanism places the WDT in a low power state in which clocks are gated and the counter stops decrementing.
15.2.3
WDT RELOAD MECHANISM
If the WDT is not reloaded within periods that are shorter than the programmed watchdog interval, the WDT will under-
flow, a WDT reset will be generated, and the WDT_STS bit will be set in the Watchdog Control Register (WDT_CTL).
It is the responsibility of software to continually execute sections of code which reload the watchdog timer (WDT), caus-
ing the counter to be reloaded via the WDT Activation Mechanism or writing to the Watchdog Kick Register (WDT_-
KICK).
15.2.4
WDT INTERVAL
The WDT Interval is the time it takes for the WDT to decrements from the Watchdog Load Register (WDT_LOAD) value
to 0h.
15.3 I2C/SPI Writes
When a watchdog interrupt is pending all write operations are blocked until the WDT_STS bit in the Watchdog Control
Register (WDT_CTL) is cleared.
DS00002084C-page 202
2016-2017 Microchip Technology Inc.
UPD360
15.4 Watchdog Timer Registers
This section details the watchdog timer registers. For an overview of the entire device register map, refer to Section 4.0,
"Register Map," on page 19.
TABLE 15-1: WATCHDOG TIMER REGISTER MAP
Address
Register Name (Symbol)
Watchdog Control Register (WDT_CTL)
3000h
3002h
3004h
3008h
Watchdog Kick Register (WDT_KICK)
Watchdog Count Register (WDT_COUNT)
Watchdog Load Register (WDT_LOAD)
300Ch – 33FFh Reserved for future expansion
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
15.4.1
WATCHDOG CONTROL REGISTER (WDT_CTL)
Address:
3000h
Size:
16 bits
Bits
Description
Type
Default
15:4
RESERVED
RO
0h
3
WDT_UNITS
R/W
0b
0: Units of 1 ms are used.
1: Units of 1 us are used.
Note:
When units of 1 us are used, the 48 MHz Relaxation Oscillator
must be enabled and device current consumption will increase by
over 400 uA. Otherwise, when units are 1 ms, the 20 KHz Keep
Alive Oscillator is used.
2
WDT_SIM
R/W
0b
Used for speeding up the watchdog timer for simulation. Watchdog operates
off of a 1 MHz clock when set.
When this bit is set, WDT_UNITS shall be set to 1b.
1
0
WDT_STS
R/WC
R/W
Note 15-1
WDT Status is set by hardware if the last reset of the device was caused by an
underflow of the WDT. This bit must be cleared by software writing a ‘1’ to this
bit. Writing a ‘0’ to this bit has no effect.
WDT_EN
0b
When set, the watchdog timer is enabled. Clearing this bit disables the watch-
dog timer.
Note:
Due to clock domain synchronization, several clock cycles may
elapse before this takes affect and the WDT counter begins to dec-
rement.
Note 15-1
Default value depends on whether a WDT initiated reset occurred, in which the case the value is 1b.
Otherwise the value is 0b.
2016-2017 Microchip Technology Inc.
DS00002084C-page 203
UPD360
15.4.2
WATCHDOG KICK REGISTER (WDT_KICK)
Address:
3002h
Size:
8 bits
Bits
Description
Type
Default
7:1
RESERVED
KICK
RO
0h
0
R/W
0h
Writes of any value to this register shall cause the watchdog timer to be imme-
diately reloaded with the value defined in Watchdog Load Register (WDT_-
LOAD) and start decrementing when the WDT_EN bit in the Watchdog
Control Register (WDT_CTL) is set to 1b. Writes to this register when
WDT_EN is 0b have no affect.
Note:
Note:
Reads of this register always return 0h.
Due to clock domain synchronization, several clock cycles may
elapse before this takes affect and the counter reloads.
15.4.3
WATCHDOG COUNT REGISTER (WDT_COUNT)
Address:
3004h
Size:
32 bits
Bits
Description
Type
Default
31:0
WDT_COUNT
RO
FFFF_FFFFh
This read only register provides a snapshot of the current state of the timer.
The lower byte shall always be read first. Reading of the lower order byte
results in a snapshot of the counter taken. This ensures that when the upper
bytes are read the state of the counter is remains in sync.
WDT_COUNT[7:0] = 0x4h
WDT_COUNT[15:8] = 0x5h
WDT_COUNT[23:16] = 0x6h
WDT_COUNT[31:24] = 0x7h
DS00002084C-page 204
2016-2017 Microchip Technology Inc.
UPD360
15.4.4
WATCHDOG LOAD REGISTER (WDT_LOAD)
Address:
3008h
Size:
32 bits
Bits
Description
Type
R/W
Default
FFFF_FFFFh
31:0
WDT_LOAD
Writing this register reloads the Watch Dog Timer counter. This register can
be programmed only when WDT_EN = 0.
Zero is not a valid load value.
WDT_LOAD[7:0] = 0x8h
WDT_LOAD[15:8] = 0x9h
WDT_LOAD[23:16] = 0xAh
WDT_LOAD[31:24] = 0xBh
2016-2017 Microchip Technology Inc.
DS00002084C-page 205
UPD360
16.0 OPERATIONAL CHARACTERISTICS
16.1 Absolute Maximum Ratings*
Supply Voltage (VS, VBUS) (Note 16-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +6.0 V
Supply Voltage (VDD33IO, 3V3_VBUS, 3V3_ALW) (Note 16-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +4.0 V
Positive voltage on input signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+/-2 kV
Note 16-1
When powering this device from laboratory or system power supplies, it is important that the absolute
maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp
circuit.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 16.2, "Operating Conditions**", Section
16.5, "DC Characteristics", or any other applicable section of this specification is not implied.
16.2 Operating Conditions**
Supply Voltage (VS, VBUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 V to +5.25 V
Supply Voltage (VDD33IO, 3V3_VBUS, 3V3_ALW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.1 V to +3.47 V
Positive voltage on input signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V
Power Supply Rise Time Max (TRT) (Figure 16-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
**Proper operation of the device is guaranteed only within the ranges specified in this section.
FIGURE 16-1:
SUPPLY RISE TIME MODEL
Voltage
tRT
3.3V
100%
VDD33IO
90%
10%
VSS
t90%
Time
t10%
DS00002084C-page 206
2016-2017 Microchip Technology Inc.
UPD360
16.3 Package Thermal Specifications
TABLE 16-1: PACKAGE THERMAL PARAMETERS
Parameter
Symbol
°C/W
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Top of Case
Thermal Resistance Junction to Board
JA
JC
JB
JT
74.2
25.2
47.9
8.8
Thermal Resistance Junction to Bottom of Case
Note:
Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.
TABLE 16-2:
POWER DISSIPATION
Parameter
Symbol
Max
Units
Power Dissipation
Pdis
825
mW
Note:
This is the worst-case power dissipation as a consequence of maximum loading (before current-limiting
protections take effect) upon the internal VBUS power switch, VCONN power switch, 3.3V power-ORing
switch, analog blocks, and core digital logic.
16.4 Current Consumption
TABLE 16-3: 3V3_ALW DEVICE CURRENT CONSUMPTION
3V3_ALW Supply Current
Max
Power State
Typical
Units
SLEEP
14
70
70
10
µA
µA
µA
mA
STANDBY
ACTIVE_PPC_OFF
ACTIVE_PPC_ON
ACTIVE and PD packet transmitting
+5
mA
See Note 4
Note 1: This table details the power consumption of the UPD360 device as measured during various modes of
operation. Power dissipation is determined by temperature, supply voltage, and external source/sin k
requirements. Maximum values represent very short bursts of activity over a small amount of time. Typical
values represent averaged current consumption over time.
2: SLEEP power state is achieved with PWR_DN pin asserted
3: STANDBY is equivalent to USB Type-C™ specification’s Unattached.SRC/Unattached.SNK
4: 3V3_VBUS current is ~0µA except during bus-powered conditions, where the power consumption is
equivalent to “ACTIVE_PPC_OFF”.
5: Supply current for the ACTIVE and PD packet transmitting is in addition to the appropriate ACTIVE_P-
PC_ON/OFF state’s typical value.
2016-2017 Microchip Technology Inc.
DS00002084C-page 207
UPD360
TABLE 16-4: VS DEVICE CURRENT CONSUMPTION
VS Supply Current
Max
Power State
Typical
Units
SLEEP
50
60
µA
µA
µA
mA
STANDBY
ACTIVE_PPC_OFF
ACTIVE_PPC_ON
60
See Note 4
Note 1: This table details the power consumption of the UPD360 device as measured during various modes of
operation. Power dissipation is determined by temperature, supply voltage, and external source/sin k
requirements. Maximum values represent very short bursts of activity over a small amount of time. Typical
values represent averaged current consumption over time.
2: SLEEP power state is achieved with PWR_DN pin asserted
3: STANDBY is equivalent to USB Type-C™ specification’s Unattached.SRC/Unattached.SNK
4: VS current consumption is equal to the sum of VBUS (when internal 5V PPC is used) and VCONN loads.
16.5 DC Characteristics
TABLE 16-5: DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
Notes
IS Type Input Buffer
Low Input Level
VILI
VIHI
-0.3
2.0
0.8
3.6
1.8
1.8
0
V
V
High Input Level
Negative-Going Threshold
Positive-Going Threshold
Schmitt Trigger Hysteresis
VILT
VIHT
VHYS
1.21
1.31
100
1.33
1.58
133
V
Schmitt trigger
Schmitt trigger
V
mV
(VIHT - VILT
)
Input Leakage
(VIN = VSS or VDDIO)
IIH
-10
10
3
µA
pF
Note 16-2
Input Capacitance
CIN
O8 Type Output Buffer
Low Output Level
VOL
VOH
0.4
0.4
V
V
IOL = -8 mA
IOH = 8 mA
VDDIO - 0.4
High Output Level
OD8 Type Output Buffer
Low Output Level
VOL
V
IOL = -8 mA
Note 16-3
I2C Type Buffer
Note 16-2
This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up
resistors add +/- 50 µA per-pin (typical).
Note 16-3
The I2C type buffer conforms to the NXP I2C-Bus Specification (UM10204, Rev. 6). Refer to the I2C-
Bus Specification for additional information.
DS00002084C-page 208
2016-2017 Microchip Technology Inc.
UPD360
TABLE 16-6: PORT POWER CONTROLLER DC PARAMETERS
Parameter
Symbol
Min
Typ
Max
Units
Notes
Over-voltage Lockout
On Resistance
VS_OV
RON_PSW
tTSD
6
V
40
m
°C
4.75 V < VS < 5.25 V
Thermal Shutdown
Threshold
135
Die Temperature at which port
power switch will turn off
Thermal Shutdown
Hysteresis
tTSD_HYST
35
°C
After shutdown due to TTSD
being reached, die temperature
drop required before port power
switch can be turned on again
Discharge Imped-
ance
RDISCHARGE
ILIM_USB2
100
500
ILIM USB 2.0 Default
Current
600
1100
1800
3700
mA
Used when PWR_CAPx pins are
set to the USB 2.0 Default Cur-
rent limit or configured via PPC
control registers.
ILIM USB 3.0 Default
Current
ILIM_USB3
ILIM_1.5A
ILIM_3A
900
1500
3000
mA
mA
mA
Used when PWR_CAPx pins are
set to the USB 3.0 Default Cur-
rent limit or configured via PPC
control registers.
ILIM 1.5A
ILIM 3.0A
Used when PWR_CAPx pins are
set to the 1.5A current limit or
configured via PPC control regis-
ters.
Used when PWR_CAPx pins are
set to the 3.0A current limit or
configured via PPC control regis-
ters.
TABLE 16-7: VCONN SOURCE DC PARAMETERS
Parameter
Symbol
ILIM_VCONN
RON_VCONN
Min
Typ
600
270
Max
Units
mA
Notes
ILIM
On Resistance
VS=5V
m
TABLE 16-8: POWER SWITCH DC PARAMETERS
Parameter
VSW Load
VSW Resistance
Symbol
Min
Typ
Max
Units
Notes
VSW_Load
R_VSW
100
mA
3V3_ALW/3V3_VBUS = 3.3V
500
2016-2017 Microchip Technology Inc.
DS00002084C-page 209
UPD360
16.6 AC Characteristics and Timing
This section details the various AC timing specifications of the device.
16.6.1
RESET_N TIMING
Figure 16-2 illustrates the RESET_N timing requirements. Assertion of RESET_N is not a requirement. However, if used,
it must be asserted for the minimum period specified
FIGURE 16-2:
RESET_N TIMING
trstia
RESET_N
TABLE 16-9: RESET_N TIMING VALUES
Symbol
Description
RESET_N input assertion time
Min
Typ
Max
Units
trstia
1
s
2
16.6.2
I C SLAVE INTERFACE (UPD360-A/UPD360-B ONLY)
Figure 16-3 illustrates the I2C slave interface timing requirements. The I2C slave interface can operate in Standard
Mode, Fast Mode, or Fast Mode Plus. Refer to Section 5.0, "I2C Slave Controller (UPD360-A/UPD360-B Only)," on
page 20 for additional information.
2
FIGURE 16-3:
I C SLAVE TIMING
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
(P)
Protocol
tSU;STA
tHIGH
1 / fCLK
tLOW
0.7 x VDD
0.3 x VDD
I2C_CLK
I2C_DAT
tr
tf
tBUF
0.7 x VDD
0.3 x VDD
tHD;STA
tSU;DAT tHD;DAT
tVD;DAT
tVD;ACK tSU;STO
DS00002084C-page 210
2016-2017 Microchip Technology Inc.
UPD360
2
TABLE 16-10: I C SLAVE TIMING VALUES
Symbol
Description
Min
Max
Units
fCLK
tBUF
I2C_CLK clock frequency
0
1000
kHz
s
s
s
s
ns
s
ns
ns
s
s
ns
Bus free time between a STOP and START condition
Hold time (repeated) START condition
Setup time for repeated START condition
Setup time for STOP condition
Data hold time
0.5
0.26
0.26
0.26
0
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
Data valid acknowledge time (Note 16-4)
Data valid time (Note 16-5)
0.05
50
0.45
450
Data setup time
50
LOW period of the I2C_CLK clock
HIGH period of the I2C_CLK clock
0.5
0.26
tHIGH
tf
Fall time of I2C_CLK and I2C_DAT
(Note 16-6)(Note 16-7)
120
120
50
tr
Rise time of I2C_CLK and I2C_DAT
(Note 16-6)(Note 16-7)
ns
ns
tSP
Pulse width of spikes that must be suppressed by the input filter
(Note 16-8)
Note 16-4
Note 16-5
Note 16-6
tVD;ACK = time for Acknowledgment signal from I2C_CLK LOW to I2C_DAT (out) LOW.
tVD;DAT = minimum time for I2C_DAT data out to be valid following I2C_CLK LOW.
A master device must internally provide a hold time of at least 300 ns for the I2C_DAT signal (refer
to the VIL of the I2C_CLK signal) in order to bridge the undefined region I2C_CLK‘s falling edge.
Note 16-7
The maximum tf for the I2C_DAT and I2C_CLK bus lines is specified at 300 ns. The maximum fall
time for the I2C_DAT output stage tf is specified at 250 ns. This allows series protection resistors to
be connected between the I2C_DAT and I2C_CLK pins and the respective bus lines without
exceeding the maximum specified tf.
Note 16-8
Input filters on the I2C_DAT and I2C_CLK inputs suppress noise spikes less than 50 ns.
16.6.3
SPI SLAVE INTERFACE (UPD360-C ONLY)
Figure 16-4 and Figure 16-5 illustrate the SPI slave interface input and output timing requirements, respectively. Refer
to Section 6.0, "SPI Slave Controller (UPD360-C Only)," on page 26 for additional information.
FIGURE 16-4:
SPI SLAVE INPUT TIMING
tscshl
SPI_CS
SPI_CLK
SPI_DI
tscss
tscsh
thigh tlow
tsu
thd
2016-2017 Microchip Technology Inc.
DS00002084C-page 211
UPD360
FIGURE 16-5:
SPI_CS
SPI SLAVE OUTPUT TIMING
tclk_duty
SPI_CLK
ton
tv
tho
tdis
SPI_DO
TABLE 16-11: SPI TIMING VALUES
Symbol
Description
SPI_CLK clock frequency
Min
Typ
Max
Units
fsck
tclk_duty
tscss
tscsh
tscshl
tsu
25
60
MHz
%
SPI_CLK high/low duty cycle
40
5
SPI_CS setup time to SPI_CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI_CS hold time from SPI_CLK
5
SPI_CS inactive time
100
10
4
Data input setup time to SPI_CLK
Data input hold time from SPI_CLK
Data output turn on time from SPI_CLK
Data output valid time from SPI_CLK
Data output hold time from SPI_CLK
Data output disable time from SPI_CS inactive
8.5 or 8.0, depending on loading of 30pF or 10pF, respectively.
thd
ton
0
Note 16-9
20
tv
tho
0
tdis
Note 16-9
16.6.4
PORT POWER CONTROLLER AC PARAMETERS
TABLE 16-12: PORT POWER CONTROLLER AC PARAMETERS
Parameter
Symbol
Min
Typ
Max
Units
Notes
Turn On Delay
tON_PSW
0.75
ms
PWR_EN active toggle to switch
on time, VBUS discharge not
active.
Turn Off Time
Turn Off Time
tOFF_PSW_INA
0.75
1
ms
ms
PWR_EN inactive toggle to
switch off time.
CBUS = 120 F
tOFF_PSW_ERR
Over-current Error, VBUS Min
Error, or Discharge Error to
switch off.
CBUS = 120 F
Note 16-10
Turn Off Time
tOFF_PSW_ERR
100
1.1
ns
TSD or Back-drive Error to switch
off.
CBUS = 120 F
VBUS Output
Rise Time
tR_BUS
ms
Measured from 10% to 90% of
VBUS, CLOAD = 220 F
ILIM = 1.0 A
Soft Turn on Rate
IBUS / t
100
mA /
µs
DS00002084C-page 212
2016-2017 Microchip Technology Inc.
UPD360
TABLE 16-12: PORT POWER CONTROLLER AC PARAMETERS (CONTINUED)
Parameter
Symbol
Min
Typ
Max
Units
Notes
Temperature Update
Time
tDC_TEMP
200
ms
Cycle Time
tCYCLE
25
ms
µs
Time period after which PPC
faults are determined to be
cleared, as part of the auto-
recovery fault handler.
Short Circuit
Response Time
tSHORT_LIM
1.5
Time from detection of short to
current limit applied.
No CBUS applied
Note 16-10
Short Circuit
Detection Time
tSHORT
6
7
ms
ms
ms
Time from detection of short to
port power switch disconnect and
alert assertion.
Note 16-10
Latched Mode Cycle
Time
tUL
From PWR_EN edge transition
from inactive to active to begin
error recovery.
Note 16-10
Discharge Time
tDISCHARGE
200
Amount of time discharge resis-
tor applied. Programmable to
100-400 ms, default listed.
Port Power Switch Operation with Trip Mode Current Limiting
Region 2 Current
Keep-out
IBUS_R2MIN1
VBUS_MIN1
0.1
A
V
Note 16-10
Note 16-10
Minimum VBUS
2.0
Allowed at Output
Note 16-10 Design guidance only. Not tested in production.
2016-2017 Microchip Technology Inc.
DS00002084C-page 213
UPD360
17.0 PACKAGE INFORMATION
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
FIGURE 17-1:
PACKAGE MARKING INFORMATION
44-WFBGA
UP360A
e
3
<R>010
<V><COO>
YWWNNN
Legend: <R>
Functional revision
000
<V>
Firmware/Tracking number
Assembly vendor code
<COO> Country code
Y
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
e
3
DS00002084C-page 214
2016-2017 Microchip Technology Inc.
UPD360
FIGURE 17-2:
PACKAGE (DRAWING & DIMENSIONS)
2016-2017 Microchip Technology Inc.
DS00002084C-page 215
UPD360
FIGURE 17-3:
PACKAGE (BALL MATRIX & ROUTING)
DS00002084C-page 216
2016-2017 Microchip Technology Inc.
UPD360
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
Revision
DS00002084C (07-19-17)
REVISION HISTORY
Section/Figure/Entry
Correction
Public Release
2016-2017 Microchip Technology Inc.
DS00002084C-page 217
UPD360
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
DS00002084C-page 218
2016-2017 Microchip Technology Inc.
UPD360
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X]( 1)
PART NO.
[X]
/XXX
-X
Examples:
a)
UPD360-A/6HX
Device Tape & Reel
Option
Temp. Package
Range
Version
+1.8V I2C Interface,
Standard packaging,
Commercial temperature,
44-ball WFBGA package
b)
UPD360T-B/6HX
Device:
UPD360
+3.3V I2C Interface,
Tape and Reel,
Commercial temperature,
44-ball WFBGA package
Tape and Reel
Option:
Blank = Standard packaging (tray)
T
= Tape and Reel (Note 1)
c)
UPD360-C/6HX
SPI Interface,
Version:
A
B
C
= +1.8V I2C Interface
= +3.3V I2C Interface
= SPI Interface
Standard packaging,
Commercial temperature,
44-ball WFBGA package
Temperature
Range:
Blank
6HX
=
0C to +70C (Commercial)
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
Package:
= 44-ball WFBGA
2016-2017 Microchip Technology Inc.
DS00002084C-page 219
UPD360
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016-2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522419181
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
CERTIFIEDꢀBYꢀDNVꢀ
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
== ISO/TSꢀ16949ꢀ==ꢀ
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00002084C-page 220
2016-2017 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Finland - Espoo
Tel: 358-9-4520-820
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
France - Saint Cloud
Tel: 33-1-30-60-70-00
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Boston
Tel: 49-2129-3766400
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Heilbronn
Tel: 49-7131-67-3636
China - Dongguan
Tel: 86-769-8702-9880
Germany - Karlsruhe
Tel: 49-721-625370
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Guangzhou
Tel: 86-20-8755-8029
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Korea - Seoul
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Rosenheim
Tel: 49-8031-354-560
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Israel - Ra’anana
Tel: 972-9-744-7705
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Detroit
Novi, MI
Tel: 248-848-4000
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Houston, TX
Tel: 281-894-5983
Italy - Padova
Tel: 39-049-7625286
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Shanghai
Tel: 86-21-3326-8000
Fax: 86-21-3326-8021
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Norway - Trondheim
Tel: 47-7289-7561
Los Angeles
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Poland - Warsaw
Tel: 48-22-3325737
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Romania - Bucharest
Tel: 40-21-407-87-50
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Raleigh, NC
Tel: 919-844-7510
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
Sweden - Gothenberg
Tel: 46-31-704-60-40
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Sweden - Stockholm
Tel: 46-8-5090-4654
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
DS00002084C-page 221
2016-2017 Microchip Technology Inc.
11/07/16
相关型号：
UPD360-C6HX
Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
UPD360T-A6HX
Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
UPD360T-B/6HX
USB Bus ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
UPD360T-B6HX
Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
UPD360T-C6HX
Highly Integrated Small Form Factor USB Type-C⢠Power Delivery 2.0 Port ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
MICROCHIP
UPD3700CS
LINEAR CCD IMAGE ARRAYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD3719
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD3719D
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD3720A
2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD3720ACY
2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
©2020 ICPDF网 联系我们和版权申明