USB7006-I/KDXVAO_技术文档

USB7006

6-Port USB 3.2 Gen 1 Controller Hub

• Supports battery charging of most popular battery

powered devices on all ports

Highlights

• 6-Port USB Smart Hub with:

-

USB-IF Battery Charging rev. 1.2 support

(DCP, CDP, SDP)

-

Five Standard USB 3.2 Gen 1 downstream ports

One Standard USB 2.0 downstream port

-

Apple^®portable product charger emulation

Chinese YD/T 1591-2006/2009 charger emulation

European Union universal mobile charger support

Supports additional portable devices

- Internal Hub Feature Controller enables:

-USB to I²C/SPI/I²S/GPIO bridge endpoint support

-USB to internal hub register write and read

• USB Link Power Management (LPM) support

• On-chip Microcontroller

• Programming of firmware image to external SPI

memory device from USB host

-

manages I/Os, VBUS, and other signals

• 96kB RAM, 256kB ROM

• USB-IF Battery Charger revision 1.2 support on

downstream ports (DCP, CDP, SDP)

• 8kB One-Time-Programmable (OTP) ROM

-

Includes on-chip charge pump

• Enhanced OEM configuration options available

through either OTP or external SPI memory

• Configuration programming via OTP Memory, SPI

external memory, or SMBus

• Available in 100-pin (12mm x 12mm) VQFN

RoHS compliant package

• FlexConnect

-

The roles of the upstream and all downstream

ports are reversible on command

• Commercial and industrial grade temperature

support

• USB Bridging

• Automotive/AEC-Q100 qualified

-

USB to I²C, SPI, I²S, and GPIO

• PortSwap

Target Applications

• Standalone USB Hubs

• Laptop Docks

-

Configurable USB 2.0 differential pair signal swap

• PHYBoost

-

Programmable USB transceiver drive strength for

recovering signal integrity

• PC Motherboards

• PC Monitor Docks

• Multi-function USB 3.2 Gen 1 Peripherals

• VariSense

-

Programmable USB receive sensitivity

Key Benefits

• USB 3.2 Gen 1 compliant 5 Gbps,

480 Mbps, 12 Mbps, and 1.5Mbps operation

• PortSplit

-

USB 2.0 and USB 3.2 Gen 1 port operation can be

split for custom applications using embedded USB

3.x devices in parallel with USB 2.0 devices

-

5V tolerant USB 2.0 pins

1.21V tolerant USB 3.2 Gen 1 pins

• Compatible with Microsoft Windows 10, 8, 7, XP,

Apple OS X 10.4+, and Linux hub drivers

- Integrated termination and pull-up/down resistors

• Optimized for low-power operation and low ther-

mal dissipation

• 100-pin VQFN package (12mm x 12mm)

 2021 Microchip Technology Inc.

DS00003715A-page 1

USB7006

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of

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lications will be refined and enhanced as new volumes and updates are introduced.

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sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner

of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of doc-

ument DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may

exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The

errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature num-

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DS00003715A-page 2

 2021 Microchip Technology Inc.

USB7006

1.0

1.1

PREFACE

General Terms

TABLE 1-1:

GENERAL TERMS

Term

Description

ADC

Analog-to-Digital Converter

Byte

8 bits

CDC

Communication Device Class

Control and Status Registers

Downstream Facing Port

32 bits

CSR

DFP

DWORD

EOP

End of Packet

EP

Endpoint

FIFO

First In First Out buffer

Full-Speed

FS

FSM

Finite State Machine

General Purpose I/O

Hi-Speed

GPIO

HS

HSOS

High Speed Over Sampling

Hub Feature Controller

The Hub Feature Controller, sometimes called a Hub Controller for short is the internal

processor used to enable the unique features of the USB Controller Hub. This is not to

be confused with the USB Hub Controller that is used to communicate the hub status

back to the Host during a USB session.

I²C

Inter-Integrated Circuit

Low-Speed

LS

lsb

Least Significant Bit

Least Significant Byte

Most Significant Bit

Most Significant Byte

Not Applicable

LSB

msb

MSB

N/A

NC

No Connect

OTP

PCB

PCS

PHY

PLL

One Time Programmable

Printed Circuit Board

Physical Coding Sublayer

Physical Layer

Phase Lock Loop

RESERVED

Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must

always be zero for write operations. Unless otherwise noted, values are not guaran-

teed when reading reserved bits. Unless otherwise noted, do not read or write to

reserved addresses.

SDK

Software Development Kit

System Management Bus

Upstream Facing Port

Universally Unique IDentifier

16 bits

SMBus

UFP

UUID

WORD

 2021 Microchip Technology Inc.

DS00003715A-page 3

USB7006

1.2

Buffer Types

TABLE 1-2:

BUFFER TYPES

Buffer Type

Description

I

Input.

IS

Input with Schmitt trigger.

O12

OD12

PU

Output buffer with 12 mA sink and 12 mA source.

Open-drain output with 12 mA sink

50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-

ups are always enabled.

Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal

resistors to drive signals external to the device. When connected to a load that must be

pulled high, an external resistor must be added.

PD

50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal

pull-downs are always enabled.

Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on

internal resistors to drive signals external to the device. When connected to a load that

must be pulled low, an external resistor must be added.

ICLK

OCLK

I/O-U

I-R

Crystal oscillator input pin

Crystal oscillator output pin

Analog input/output defined in USB specification.

RBIAS.

A

Analog.

AIO

P

Analog bidirectional.

Power pin.

DS00003715A-page 4

 2021 Microchip Technology Inc.

USB7006

1.3

Pin Reset States

The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual

pin reset states.

TABLE 1-3:

Symbol

PIN RESET STATE LEGEND

Description

AI

AIO

AO

PD

PU

Y

Analog input

Analog input/output

Analog output

Hardware enables pull-down

Hardware enables pull-up

Hardware enables function

Z

Hardware disables output driver (high impedance)

Hardware enables internal pull-up

Hardware enables internal pull-down

PU

PD

1.4

Reference Documents

1. Universal Serial Bus Revision 3.2 Specification, http://www.usb.org

2. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org

3. I²C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf

4. I²S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf

5. System Management Bus Specification, Version 1.0, http://smbus.org/specs

 2021 Microchip Technology Inc.

DS00003715A-page 5

USB7006

2.0

2.1

INTRODUCTION

General Description

The Microchip USB7006 hub is a low-power, OEM configurable, USB 3.2 Gen 1 hub controller with 6 downstream ports

and advanced features for embedded USB applications. The USB7006 is fully compliant with the Universal Serial Bus

Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7006 supports 5 Gbps Super-

Speed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-

Speed (LS) USB downstream devices on five standard USB 3.2 Gen 1 downstream ports and only legacy speeds (HS/

FS/LS) on one standard USB 2.0 downstream port.

The USB7006 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the cul-

mination of seven generations of Microchip hub feature controller design and experience with proven reliability, interop-

erability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,

decoupling the 5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.

The USB7006 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-

uration process assigning default values to USB 3.2 Gen 1 ports and GPIOs. OEMs can disable ports, enable battery

charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI

ROM.

The USB7006 supports downstream battery charging. The USB7006 integrated battery charger detection circuitry sup-

ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7006 provides the bat-

tery charging handshake and supports the following USB-IF BC1.2 charging profiles:

• DCP: Dedicated Charging Port (Power brick with no data)

• CDP: Charging Downstream Port (1.5A with data)

• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)

Additionally, the USB7006 includes many powerful and unique features such as:

The Hub Feature Controller, an internal USB device dedicated for use as a USB to I²C/SPI/GPIO interface that allows

external circuits or devices to be monitored, controlled, or configured via the USB interface.

FlexConnect, which provides flexible connectivity options. One of the USB7006’s downstream ports can be reconfig-

ured to become the upstream port, allowing master capable devices to control other devices on the hub.

AEC-Q100 compliance, which tailors the device for use in automotive applications requiring automotive grade robust-

ness, starting with the comprehension of proprietary design for reliability techniques within the silicon IC itself, as well

as for the package design.

• Automotive qualified technologies and processes are used to fabricate the products with enhanced monitors to

continuously drive improvements in accordance with Microchip's zero-dpm methodology.

• Product qualification is focused on customer expectations and exceeds many of the automotive reliability stan-

dards including AEC-Q100.

• Microchip automotive services are provided during the life of the product from a dedicated organization of opera-

tions, quality, and product support personnel specialized in meeting the requirements of the automotive customer.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment

of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the

PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength

in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity

in a compromised system environment. The graphic on the right shows an example of

Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in

a compromised system environment.

VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive

sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is

used.

Port Split, which allows for the USB 3.2 Gen 1 and USB 2.0 portions of downstream ports 3, 4, and 5 to operate inde-

pendently and enumerate two separate devices in parallel in special applications.

The USB7006 can be configured for operation through internal default settings. Custom OEM configurations are sup-

ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow

for maximum operational flexibility and are available as GPIOs for customer specific use.

 2021 Microchip Technology Inc.

DS00003715A-page 6

USB7006

The USB7006 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal

block diagram of the USB7006 in an upstream Type-B application is shown in Figure 2-1.

FIGURE 2-1:

USB7006 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION

P0

B

+3.3 V

PHY0 PHY0

VCORE

USB3 USB2

Hub Controller Logic

HFC

PHY

25 Mhz

PHY1 PHY1 PHY2 PHY2 PHY3 PHY3 PHY4 PHY4 PHY5 PHY5

PHY6

OTP

Hub Feature Controller

GPIO I²C

SPI

I²S

Mux

P1

A

P2

A

P3

A

P4

A

P5

A

P6

A

Note:

All port numbering in this document is LOGICAL port numbering with the device in the default configuration.

LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any

port number remapping or port disabling. The PHYSICAL port number is the port number with respect to

the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by

LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port num-

bering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Config-

uration of USB70xx Family” application note for details on the LOGICAL vs. PHYSICAL mapping and

additional configuration details.

DS00003715A-page 7

 2021 Microchip Technology Inc.

USB7006

3.0

3.1

PIN DESCRIPTIONS

Pin Assignments

FIGURE 3-1:

USB7006 100-VQFN PIN ASSIGNMENTS

1

2

75

RESET_N

PF26

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PF30/VBUS_DET

PF31

PF29

3

SPI_D3/PF25

4

DP1_VBUS_MON

USB2DN_DP1/PRT_DIS_P1

USB2DN_DM1/PRT_DIS_M1

USB3DN_TXDP1A

USB3DN_TXDM1A

VCORE

SPI_D2/PF24

5

SPI_D1/PF23

6

SPI_D0/CFG_BC_EN/PF22

7

SPI_CE_N/CFG_NON_REM/PF20

8

SPI_CLK/PF21

VDD33

PF19

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

USB3DN_RXDP1A

USB3DN_RXDM1A

DP1_CC1

TEST3

TEST2

TEST1

VDD33

PF18

Microchip

DP1_CC2

USB7006

USB2DN_DP3/PRT_DIS_P3

USB2DN_DM3/PRT_DIS_M3

USB3DN_TXDP1B

USB3DN_TXDM1B

VCORE

(Top View 100-VQFN)

PF17

PF16

PF15

USB3DN_RXDP1B

USB3DN_RXDM1B

CFG_STRAP1

PF14

PF13

Thermal slug connects to VSS

VCORE

PF12

CFG_STRAP2

CFG_STRAP3

VDD33

PF11

TESTEN

VCORE

PF10

Note:

Configuration straps are identified by an underlined symbol name. Signals that function as configuration

straps must be augmented with an external resistor when connected to a load.

 2021 Microchip Technology Inc.

DS00003715A-page 8

USB7006

Pin Num

Pin Name

Reset Pin Num

Pin Name

Reset

1

2

3

4

RESET_N

PF30/VBUS_DET

PF31

Z

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

PF10

PF11

PD

Z

VDD33

Z

NC

AI

PF12

PD

5

USB2DN_DP1/PRT_DIS_P1

USB2DN_DM1/PRT_DIS_M1

USB3DN_TXDP1

USB3DN_TXDM1

VCORE

AIO PD

AO PD

Z

VCORE

Z

6

PF13

PD

7

PF14

PD

8

PF15

PD

9

PF16

PD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

USB3DN_RXDP1

USB3DN_RXDM1

NC

AI PD

AI

PF17

PD

PF18

Z

VDD33

Z

NC

AI

TEST1

Z

USB2DN_DP2/PRT_DIS_P2

USB2DN_DM2/PRT_DIS_M2

USB3DN_TXDP2

USB3DN_TXDM2

VCORE

AIO PD

AO PD

Z

TEST2

Z

TEST3

Z

PF19

Z

VDD33

Z

SPI_CLK/PF21

SPI_CE_N/CFG_NON_REM/PF20

SPI_D0/CFG_BC_EN/PF22

SPI_D1/PF23

SPI_D2/PF24

SPI_D3/PF25

PF29

Z

USB3DN_RXDP2

USB3DN_RXDM2

CFG_STRAP1

CFG_STRAP2

CFG_STRAP3

TESTEN

AI PD

Z

PU

Z

VCORE

Z

PF26

Z

VDD33

Z

PF27

Z

USB2DN_DP3/PRT_DIS_P3

USB2DN_DM3/PRT_DIS_M3

USB3DN_TXDP3

USB3DN_TXDM3

VCORE

AIO PD

AO PD

Z

PF28

Z

VCORE

Z

VDD33

Z

NC

AI

USB2DN_DP5/PRT_DIS_P5

USB2DN_DM5/PRT_DIS_M5

USB3DN_TXDP5

USB3DN_TXDM5

VCORE

AIO PD

AO PD

Z

USB3DN_RXDP3

USB3DN_RXDM3

USB2DN_DP4/PRT_DIS_P4

USB2DN_DM4/PRT_DIS_M4

USB3DN_TXDP4

USB3DN_TXDM4

VCORE

AI PD

AIO PD

AO PD

Z

USB3DN_RXDP5

USB3DN_RXDM5

VDD33

AI PD

Z

USB3DN_RXDP4

USB3DN_RXDM4

USB2DN_DM6/PRT_DIS_M6

USB2DN_DP6/PRT_DIS_P6

VDD33

AI PD

AIO PD

Z

USB2UP_DP

USB2UP_DM

USB3UP_TXDP

USB3UP_TXDM

VCORE

AIO Z

AO PD

Z

PF3

Z

USB3UP_RXDP

USB3UP_RXDM

ATEST

AI PD

AO

PF4

Z

PF5

Z

PF6

Z

XTALO

AO

PF7

Z

XTALI/CLK_IN

VDD33

AI

PF8

Z

PF9

Z

RBIAS

AI

Exposed Pad (VSS) must be connected to ground.

DS00003715A-page 9

 2021 Microchip Technology Inc.

USB7006

3.2

Pin Descriptions

This section contains descriptions of the various USB7006 pins. The “_N” symbol in the signal name indicates that the

active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the

reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage

level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-

tive.

The “If Unused” column provides information on how to terminate pins if they are unused in a customer design.

Buffer type definitions are detailed in Section 1.2, Buffer Types.

TABLE 3-1:

Name

PIN DESCRIPTIONS

Symbol

Buffer

Type

Description

If Unused

USB 3.2 Gen 1 Interfaces

Upstream USB

3.2 Gen 1 TX D+

USB3UP_TXDP

USB3UP_TXDM

USB3UP_RXDP

I/O-U

Upstream USB 3.2 Gen 1 Transmit Data

Plus.

Float

Upstream USB

3.2 Gen 1 TX D-

Upstream USB 3.2 Gen 1 Transmit Data

Minus.

Upstream USB

3.2 Gen 1 RX D+

Upstream USB 3.2 Gen 1 Receive Data

Plus.

Weak pull-

down to

GND

Upstream USB

3.2 Gen 1 RX D-

USB3UP_RXDM

USB3DN_TXDP[1:5]

USB3DN_TXDM[1:5]

USB3DN_RXDP[1:5]

USB3DN_RXDM[1:5]

I/O-U

Upstream USB 3.2 Gen 1 Receive Data

Minus.

Weak pull-

down to

GND

Downstream

Ports 1-5 USB

3.2 Gen 1 TX D+

Downstream SuperSpeed+ Transmit Data

Plus, ports 1 through 5.

Float

Downstream

Ports 1-5 USB

3.2 Gen 1 TX D-

Downstream SuperSpeed+ Transmit Data

Minus, ports 1 through 5.

Float

Downstream

Ports 1-5 USB

3.2 Gen 1 RX D+

Downstream SuperSpeed+ Receive Data

Plus, ports 1 through 5.

Weak pull-

down to

GND

Downstream

Ports 1-5 USB

3.2 Gen 1 RX D-

Downstream SuperSpeed+ Receive Data

Minus, ports 1 through 5.

Weak pull-

down to

GND

USB 2.0 Interfaces

Upstream USB

2.0 D+

USB2UP_DP

USB2UP_DM

I/O-U

Upstream USB 2.0 Data Plus (D+).

Mandatory

Note 3-5

Upstream USB

2.0 D-

Upstream USB 2.0 Data Minus (D-).

Mandatory

Note 3-5

Downstream

Ports 1-6 USB

2.0 D+

USB2DN_DP[1:6]

Downstream USB 2.0 Ports 1-6 Data Plus

(D+).

Connect

directly to

3.3V

 2021 Microchip Technology Inc.

DS00003715A-page 10

USB7006

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

If Unused

Downstream

Ports 1-6 USB

2.0 D-

USB2DN_DM[1:6]

I/O-U

Downstream USB 2.0 Ports 1-6 Data Minus

(D-)

Connect

directly to

3.3V

VBUS Detect

VBUS_DET

IS

This signal detects the state of the upstream

bus power.

Not

Recom-

mended.

If unused,

tie to a

3.3V rail

through a

10-100k

pull-up

Externally, VBUS can be as high as 5.5 V,

which can be damaging to this pin. The

amplitude of VBUS must be reduced by a

voltage divider. The recommended voltage

divider is shown below.

VBUS_UP

resistor.

VBUS_DET

43K

For self-powered applications with a perma-

nently attached host, this pin must be con-

nected to either 3.3 V or 5.0 V through a

resistor divider to provide 3.3 V.

In embedded applications, VBUS_DET may

be controlled (toggled) when the host

desires to renegotiate a connection without

requiring a full reset of the device.

SPI Interface

SPI Clock

SPI_CLK

I/O-U

SPI clock. If the SPI interface is enabled,

this pin must be driven low during reset.

Weak pull-

down to

GND

SPI Data 3-0

SPI_D[3:0]

I/O-U

SPI Data 3-0. If the SPI interface is enabled,

these signals function as Data 3 through 0.

Note 3-1

SPI_D0 operates as the

CFG_BC_EN strap if

external SPI memory is not

used. It must be terminated

with the selected strap

resistor to 3.3V or GND.

SPI_D[1:3] should be

connected to GND through

a weak pull-down.

SPI Chip

Enable

SPI_CE_N

I/O12

Active low SPI chip enable input. If the SPI

interface is enabled, this pin must be driven

high in powerdown states.

Note 3-2

Operates

as

the

CFG_NON_REM strap if

external SPI memory is not

used. It must be terminated

with the selected strap

resistor to 3.3V or GND.

DS00003715A-page 11

 2021 Microchip Technology Inc.

USB7006

TABLE 3-1:

Name

PIN DESCRIPTIONS (CONTINUED)

Buffer

Symbol

Type

Description

If Unused

Miscellaneous

Programmable

Function Pins

PF[31:3]

I/O12

Programmable function pins.

Note 3-3

If unused: depends on the

configured pin function.

Refer to Section 3.3.4,

PF[31:3] Configuration

(CFG_STRAP[2:1])

Test 1

Test 2

Test 3

TEST1

TEST2

TEST3

A

Test 1 pin.

Pull to 3.3V

through a

10 k

This signal is used for test purposes and

must always be pulled-up to 3.3V via a 10

k resistor.

resistor

Test 2 pin.

Pull to 3.3V

or GND

through a

10 k

This signal is used for test purposes and

must always be pulled-up to 3.3V or GND

via a 10 k resistor.

resistor

Test 3 pin.

Pull to 3.3V

or GND

through a

10 k

This signal is used for test purposes and

must always be pulled-up to 3.3V or GND

via a 10 k resistor.

resistor

Reset Input

RESET_N

RBIAS

IS

This active low signal is used by the system

to reset the device.

Mandatory

Note 3-5

Bias Resistor

I-R

A 12.0 k 1.0% resistor is attached from

ground to this pin to set the transceiver’s

internal bias settings. Place the resistor as

close the device as possible with a dedi-

cated, low impedance connection to the

ground plane.

Mandatory

Note 3-5

Test

TESTEN

ATEST

I/O12

A

Test pin.

Connect to

GND

This signal is used for test purposes and

must always be connected to ground.

Analog Test

Analog test pin.

Float

This signal is used for test purposes and

must always be left unconnected.

External 25 MHz

Crystal Input

XTALI

ICLK

External 25 MHz crystal input

Mandatory

Note 3-5

External 25 MHz

Reference Clock

Input

CLK_IN

External reference clock input.

Mandatory

Note 3-5

The device may alternatively be driven by a

single-ended clock oscillator. When this

method is used, XTALO should be left

unconnected.

 2021 Microchip Technology Inc.

DS00003715A-page 12

USB7006

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

If Unused

External 25 MHz

Crystal Output

XTALO

OCLK External 25 MHz crystal output

Float

(only if sin-

gle-ended

clock is

connected

to CLK_IN)

No Connect

NC

-

No connect.

No connect

For proper operation, this pin must be left

unconnected.

Configuration Straps

Port 6-1 D+ Disable Configuration Strap.

Port 6-1 D+

Disable

Configuration

Strap

PRT_DIS_P[6:1]

I

N/A

These configuration straps are used in con-

junction with the corresponding

PRT_DIS_M[6:1] straps to disable the

related port (6-1). See Note 3-6.

Both USB data pins for the corresponding

port must be tied to 3.3V to disable the

associated downstream port.

Port 6-1 D-

Disable

Configuration

Strap

PRT_DIS_M[6:1]

Port 6-1 D- Disable Configuration Strap.

Mandatory

Note 3-5

These configuration straps are used in con-

junction with the corresponding

PRT_DIS_P[6:1] straps to disable the

related port (6-1). See Note 3-6.

Both USB data pins for the corresponding

port must be tied to 3.3V to disable the

associated downstream port.

Non-Removable

Ports

CFG_NON_REM

Non-Removable Ports Configuration Strap.

Note 3-4

Configuration

Strap

This configuration strap controls the number

of reported non-removable ports. See

Note 3-6.

Note 3-4

Mandatory if external SPI

memory is not used for

firmware execution. If

external SPI memory is

used

execution,

for

firmware

then

configuration strap resistor

should be omitted.

DS00003715A-page 13

 2021 Microchip Technology Inc.

USB7006

TABLE 3-1:

Name

PIN DESCRIPTIONS (CONTINUED)

Buffer

Symbol

Type

Description

If Unused

BatteryCharging

Configuration

Strap

CFG_BC_EN

I/O12

Battery Charging Configuration Strap.

Mandatory

Note 3-5

This configuration strap controls the number

of BC 1.2 enabled downstream ports. See

Note 3-6.

Note 3-5

Mandatory if external SPI

memory is not used for

firmware execution. If

external SPI memory is

used

execution,

for

firmware

then

configuration strap resistor

should be omitted.

Device Mode

Configuration

Straps 3-1

CFG_STRAP[3:1]

I

Device Mode Configuration Straps 3-1.

Mandatory

Note 3-5

These configuration straps are used to

select the device’s mode of operation. See

Note 3-6.

Power/Ground

+3.3V I/O Power

Supply Input

VDD33

P

+3.3 V power and internal regulator input.

Mandatory

Note 3-5

Digital Core

Power Supply

Input

VCORE

P

Digital core power supply input.

Mandatory

Note 3-5

Ground

VSS

P

Common ground.

Mandatory

Note 3-5

This exposed pad must be connected to the

ground plane with a via array.

Note 3-6

Note 3-7

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. For additional information, refer to Section 3.3, Configuration Straps and Programmable

Functions.

Pin use is mandatory. Cannot be left unused.

 2021 Microchip Technology Inc.

DS00003715A-page 14

USB7006

3.3

Configuration Straps and Programmable Functions

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset

(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following

deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the var-

ious device configuration straps and associated programmable pin functions.

Note:

The system designer must guarantee that configuration straps meet the timing requirements specified in

Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap

Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may

capture incorrect strap values.

3.3.1

PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])

The PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1)

For PRT_DIS_Px (where x is the corresponding port 6-1):

0 = Port x D+ Enabled

1 = Port x D+ Disabled

For PRT_DIS_Mx (where x is the corresponding port 6-1):

0 = Port x D- Enabled

1 = Port x D- Disabled

Note:

Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable

the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0

port.

3.3.2

NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)

The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of

six settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The

resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-

up, as shown in Table 3-2.

TABLE 3-2:

CFG_NON_REM RESISTOR ENCODING

CFG_NON_REM Resistor Value

Setting

200 kΩ Pull-Down

200 kΩ Pull-Up

10 kΩ Pull-Down

10 kΩ Pull-Up

All ports removable

Port 1 non-removable

Ports 1, 2 non-removable

Ports 1, 2, 3 non-removable

Ports 1, 2, 3, 4 non-removable

10 Ω Pull-Down

10 Ω Pull-Up

Ports 1, 2, 3, 4, 5, 6 non-removable

DS00003715A-page 15

 2021 Microchip Technology Inc.

USB7006

3.3.3

BATTERY CHARGING CONFIGURATION (CFG_BC_EN)

The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of six

settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor

options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as

shown in Table 3-3.

TABLE 3-3:

CFG_BC_EN RESISTOR ENCODING

CFG_BC_EN Resistor Value

Setting

Battery charging not enable on any port

200 kΩ Pull-Down

200 kΩ Pull-Up

10 kΩ Pull-Down

10 kΩ Pull-Up

BC1.2 DCP and CDP battery charging enabled on Port 1

BC1.2 DCP and CDP battery charging enabled on Ports 1, 2

BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3

BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4

BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4, 5, 6

10 Ω Pull-Down

10 Ω Pull-Up

3.3.4

PF[31:3] CONFIGURATION (CFG_STRAP[2:1])

The USB7006 provides 29 programmable function pins (PF[31:3]). These pins can only be configured to 1 predefined

configuration via the CFG_STRAP[2:1] pins. This configuration is selected via external resistors on the

CFG_STRAP[2:1] pins, as detailed in Table 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved

and should not be used.

Note:

CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.

TABLE 3-4:

CFG_STRAP[2:1] RESISTOR ENCODING

CFG_STRAP2

Resistor Value

CFG_STRAP1

Resistor Value

Mode

Configuration 3

200 kΩ Pull-Down

10 kΩ Pull-Down

Note:

Configurations 1 and 2 are not used in the USB7006.

A summary of the configuration pin assignments is provided in Table 3-5. For details on behavior of each programmable

function, refer to Table 3-6.

 2021 Microchip Technology Inc.

DS00003715A-page 16

USB7006

TABLE 3-5:

PF[31:3] FUNCTION ASSIGNMENT

Configuration 3

PF3

I2S_SDI

I2S_SDO

PF4

PF5

I2S_SCK

PF6

I2S_LRCK

I2S_MCLK

NC

PF7

PF8

PF9

NC

PF10

PF11

PF12

PF13

PF14

PF15

PF16

PF17

PF18

PF19

PF20

PF21

PF22

PF23

PF24

PF25

PF26

PF27

PF28

PF29

PF30

PF31

PRT_CTL3_U3

PRT_CTL4_U3

PRT_CTL5_U3

PRT_CTL5

PRT_CTL4

PRT_CTL3

PRT_CTL2

PRT_CTL1

MSTR_I2C_CLK

MIC_DET

SPI_CE_N

SPI_CLK

SPI_D0

SPI_D1

SPI_D2

SPI_D3

SLV_I2C_CLK

SLV_I2C_DATA

PRT_CTL6

⁽Note 3-1⁾

VBUS_DET

MSTR_I2C_DATA

Note 3-1

The default function is not used in the USB7006.

Note:

The default PFx pin functions can be overridden with additional configuration by modification of the pin mux

registers. These changes can be made during the SMBus configuration stage, by programming to OTP

memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave

interface or USB commands to the internal Hub Feature Controller Device.

DS00003715A-page 17

 2021 Microchip Technology Inc.

USB7006

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS

Buffer

Function

Description

Type

If Unused

Master SMBus/I²C Interface

MSTR_I2C_CLK

MSTR_I2C_DATA

I/O12

Bridging Master SMBus/I²C controller clock (SMBus/I²C controller

Weak pull-

down to

GND

1). External 1k-10k pull-up resistors to 3.3V are required if the I²C

Master Interface is to be used.

Bridging Master SMBus/I²C controller data (SMBus/I²C controller

1). External 1k-10k pull-up resistors to 3.3V are required if the I²C

Master Interface is to be used.

Weak pull-

down to

GND

Slave SMBus/I²C Interface

SLV_I2C_CLK

SLV_I2C_DATA

I/O12

Slave SMBus/I²C controller clock (SMBus/I²C controller 2). Exter-

nal 1k-10k pull-up resistors to 3.3V are required if the I²C Slave

Interface is to be used.

Weak pull-

down to

GND

Slave SMBus/I²C controller data (SMBus/I²C controller 2). External

1k-10k pull-up resistors to 3.3V are required if the I²C Slave Inter-

face is to be used.

Weak pull-

down to

GND

I²S Interface

I2S_SDI

I2S_SDO

I2S_SCK

I2S_LRCK

I2S_MCLK

MIC_DET

I

I²S Serial Data In

Weak pull-

down to

GND

O12

I

I²S Serial Data Out

Weak pull-

down to

GND

I²S Continuous Serial Clock

I²S Word Select / Left-Right Clock

I²S Master Clock

Weak pull-

down to

GND

Weak pull-

down to

GND

Weak pull-

down to

GND

I²S Microphone Plug Detect

Weak pull-

down to

GND

0 = No microphone plugged into the audio jack

1 = Microphone plugged into the audio jack

 2021 Microchip Technology Inc.

DS00003715A-page 18

USB7006

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Buffer

Type

Function

Description

Miscellaneous

If Unused

PRT_CTL6

I/O12

(PU)

Port 6 power enable / overcurrent sense

Float

(Note 3-1)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 6.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

This signal controls both the USB 2.0 and USB 3.2 por-

tions of the port.

Note 3-1

This pin can be left unused only if Port 6 is

disabled via strap/OTP/SMBus/SPI configuration.

PRT_CTL5

I/O12

(PU)

Port 5 power enable / overcurrent sense

Float

(Note 3-2)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 5.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the

USB 2.0 and USB 3.2 portions of the port. When

PortSplit is enabled, this signal controls the USB 2.0

portion of the port only.

Note 3-2

This pin can be left unused only if Port 5 is

disabled via strap/OTP/SMBus/SPI configuration.

PRT_CTL4

I/O12

(PU)

Port 4 power enable / overcurrent sense

Float

(Note 3-3)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 4.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the

USB 2.0 and USB 3.2 portions of the port. When

PortSplit is enabled, this signal controls the USB 2.0

portion of the port only.

Note 3-3

This pin can be left unused only if Port 4 is

disabled via strap/OTP/SMBus/SPI configuration.

DS00003715A-page 19

 2021 Microchip Technology Inc.

USB7006

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Buffer

Function

Description

Type

If Unused

PRT_CTL3

PRT_CTL2

PRT_CTL1

I/O12

(PU)

Port 3 power enable / overcurrent sense

Float

(Note 3-4)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 3.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the

USB 2.0 and USB 3.2 portions of the port. When

PortSplit is enabled, this signal controls the USB 2.0

portion of the port only.

Note 3-4

This pin can be left unused only if Port 3 is

disabled via strap/OTP/SMBus/SPI configuration.

I/O12

(PU)

Port 2 power enable / overcurrent sense

Float

(Note 3-1)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 2.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the

USB 2.0 and USB 3.2 portions of the port. When

PortSplit is enabled, this signal controls the USB 2.0

portion of the port only.

Note 3-5

This pin can be left unused only if Port 2 is

disabled via strap/OTP/SMBus/SPI configuration.

I/O12

(PU)

Port 1 power enable / overcurrent sense

Float

(Note 3-1)

When the downstream port is enabled, this pin is set as an input

with an internal pull-up resistor applied. The internal pull-up

enables power to the downstream port while the pin monitors for an

active low overcurrent signal assertion from an external current

monitor on USB port 1.

This pin will change to an output and be driven low when the port is

disabled by configuration or by the host control.

Note:

When PortSplit is disabled, this signal controls both the

USB 2.0 and USB 3.2 portions of the port. When

PortSplit is enabled, this signal controls the USB 2.0

portion of the port only.

Note 3-6

This pin can be left unused only if Port 1 is

disabled via strap/OTP/SMBus/SPI configuration.

 2021 Microchip Technology Inc.

DS00003715A-page 20

USB7006

TABLE 3-6:

PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)

Buffer

Type

Function

Description

If Unused

PRT_CTL5_U3

PRT_CTL4_U3

PRT_CTL3_U3

O12

Port 5 USB 3.2 PortSplit power enable

Float

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 5 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

Port 4 USB 3.2 PortSplit power enable

Float

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 4 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

Port 3 USB 3.2 PortSplit power enable

This signal is an active high control signal used to enable to the

USB 3.2 portion of the downstream port 3 when PortSplit is

enabled. When PortSplit is disabled, this pin is not used.

Note:

This signal should only be used to control an embedded

USB 3.2 device.

3.4

Physical and Logical Port Mapping

The USB70xx family of devices are based upon a common architecture, but all have different modifications and/or pin

bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7

USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL

port mapping.

The actual port numbering is remapped by default in different ways on each device in the family. This changes the way

that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.

The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or

LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared

as such within the register description.

The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics

and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default

LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when

determining the hub configuration.

Note:

The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect

to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.

Refer to Section 6.0, Device Configuration for additional information.

DS00003715A-page 21

 2021 Microchip Technology Inc.

USB7006

TABLE 3-7:

Device

USB7006 PHYSICAL VS. LOGICAL PORT MAPPING

LOGICAL PORT NUMBER

PHYSICAL PORT NUMBER

Pin Name (as in datasheet)

0

1

2

3

4

5

6

0

1

2

3

4

5

6

5

USB2DN_DP1

X

6

USB2DN_DM1

USB3DN_TXDP1

USB3DN_TXDM1

USB3DN_RXDP1

USB3DN_RXDM1

USB2DN_DP2

7

8

10

11

14

15

16

17

19

20

27

28

29

30

32

33

34

35

36

37

39

40

41

42

81

82

83

84

86

87

89

90

91

92

94

95

X

USB2DN_DM2

USB3DN_TXDP2

USB3DN_TXDM2

USB3DN_RXDP2

USB3DN_RXDM2

USB2DN_DP3

X

USB2DN_DM3

USB3DN_TXDP3

USB3DN_TXDM3

USB3DN_RXDP3

USB3DN_RXDM3

USB2DN_DP4

X

USB2DN_DM4

USB3DN_TXDP4

USB3DN_TXDM4

USB3DN_RXDP4

USB3DN_RXDM4

USB2DN_DM6

USB2DN_DP6

X

USB2DN_DP5

X

USB2DN_DM5

USB3DN_TXDP5

USB3DN_TXDM5

USB3DN_RXDP5

USB3DN_RXDM5

USB2UP_DP

X

USB2UP_DM

USB3UP_TXDP

USB3UP_TXDM

USB3UP_RXDP

USB3UP_RXDM

 2021 Microchip Technology Inc.

DS00003715A-page 22

USB7006

4.0

4.1

DEVICE CONNECTIONS

Power Connections

Figure 4-1 illustrates the device power connections.

FIGURE 4-1:

POWER CONNECTIONS

+3.3V

Supply

VCORE

Supply

VCORE (x9)

VDD33 (x8)

Digital Core

Internal Logic

3.3V Internal Logic

VSS (exposed pad)

USB7006

+3.3V

VCORE

F

u

F

u

F

u

F

u

F

u

1

0

F

u

1

0

1

.

7

.

1

.

7

.

0

4

0

4

0

.

0

.

0

x8

x9

4.2

SPI Flash Connections

Figure 4-2 illustrates the Quad-SPI flash connections.

FIGURE 4-2:

QUAD-SPI FLASH CONNECTIONS

+3.3V

K

0

1

SPI_CE_N

CE#

SPI_CLK

SPI_D0

SPI_D1

CLK

SIO0

SIO1

SPI_D2

SPI_D3

SIO2/WPn

SIO3/HOLDn

Quad-SPI Flash

USB7006

 2021 Microchip Technology Inc.

DS00003715A-page 23

USB7006

4.3

SMBus/I²C Connections

Figure 4-3 illustrates the SMBus/I²C connections.

FIGURE 4-3:

SMBUS/I²C CONNECTIONS

+3.3V

4.7K

x_I2C_CLK

Clock

SMBus/I²C

+3.3V

4.7K

USB7006

x_I2C_DAT

Data

4.4

I²S Connections

Figure 4-4 illustrates the I²S connections.

FIGURE 4-4:

I²S CONNECTIONS

+3.3V

K

0

1

K

0

1

CODEC

USB7006

I2S_MCLK

I2S_SCK

I2S_LRCK

I2S_SDO

I2S_SD

I²S

MSTR_I2C_CLK

MSTR_I2C_DAT

MIC_DET

I²C

Audio Jack

DS00003715A-page 24

 2021 Microchip Technology Inc.

USB7006

5.0

MODES OF OPERATION

The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the

RESET_N pin, as shown in Table 5-1.

TABLE 5-1:

MODES OF OPERATION

RESET_N Input

0

Summary

Standby Mode: This is the lowest power mode of the device. No functions are active

other than monitoring the RESET_N input. All port interfaces are high impedance and

the PLL is halted. Refer to Section 8.9, Resets for additional information on RESET_N.

1

Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has

various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based

on the number of active ports, their speed, and amount of data received.

The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode

stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.

FIGURE 5-1:

HUB MODE FLOWCHART

RESET_N deasserted

(SPI_INIT)

In SPI Mode

(CFG_ROM)

NO

Load Config from

Internal ROM

& Ext. SPI ROM

present?

YES

(CFG_STRAP)

Modify Config

Based on Config

Straps

Run From

External SPI ROM

YES

Configuration 1?

NO

Perform SMBus/I²C

Initialization

YES

SMBus Slave Pull-ups?

NO

(SMBUS_CHECK)

NO

SOC Done?

YES

(CFG_SMBUS)

Combine OTP

Config Data

(CFG_OTP)

Hub Connect

(USB_ATTACH)

Normal Operation

(NORMAL_MODE)

 2021 Microchip Technology Inc.

DS00003715A-page 25

USB7006

5.1

Boot Sequence

5.1.1

STANDBY MODE

If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-

mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream

ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no

states saved), all internal registers return to their default state, the PLLis halted, and core logic is powered down in order

to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode

and must be re-initialized after RESET_N is negated high.

5.1.2

SPI INITIALIZATION STAGE (SPI_INIT)

The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,

the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal

firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid

signature of “2DFU” (device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the

external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid

signature is not found, then execution continues from internal ROM (CFG_ROM stage).

The required SPI ROM must be a minimum of 1 Mbit, and 60 MHz or faster. Both 1, 2, and 4-bit SPI operation is sup-

ported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also sup-

ported.

If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).

5.1.3

CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)

In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-

ters, USB descriptors, electrical settings, etc. will be initialized in this state.

5.1.4

CONFIGURATION STRAP READ STAGE (CFG_STRAP)

In this stage, the firmware reads the following configuration straps to override the default values:

• CFG_STRAP[3:1]

• PRT_DIS_P[6:1]

• PRT_DIS_M[6:1]

• CFG_NON_REM

• CFG_BC_EN

If the CFG_STRAP[3:1] pins are set to Configuration 1, the device will move to the SMBUS_CHECK stage, otherwise

it will move to the CFG_OTP stage. Refer to Section 3.3, Configuration Straps and Programmable Functions for infor-

mation on usage of the various device configuration straps.

5.1.5

SMBUS CHECK STAGE (SMBUS_CHECK)

Based on the PF[31:3] configuration selected (refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1])), the

firmware will check for the presence of external pull up resistors on the SMBus slave programmable function pins. If 10K

pull-ups are detected on both pins, the device will be configured as an SMBus slave, and the next state will be CFG_SM-

BUS. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.

5.1.6

SMBUS CONFIGURATION STAGE (CFG_SMBUS)

In this stage, the external SMBus master can modify any of the default configuration settings specified in the integrated

ROM, such as USB device descriptors, port electrical settings, and control features such as downstream battery

charging.

There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I²C configuration. The

external SMBus master writes to register 0xFF to end the configuration in legacy mode. In non-legacy mode, the SMBus

command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configu-

ration.

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USB7006

5.1.7

OTP CONFIGURATION STAGE (CFG_OTP)

Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The

default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-

grammed.

Note:

If the same register is modified in both CFG_SMBUS and CFG_OTP stages, the value from CFG_OTP will

overwrite any value written during CFG_SMBUS.

5.1.8

HUB CONNECT STAGE (USB_ATTACH)

Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable

attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register (for USB 2.0) and the

USB3_HUB_ENABLE bit (for USB 3.2). The device will remain in the Hub Connect stage indefinitely.

5.1.9

NORMAL MODE (NORMAL_MODE)

Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB

Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-

tem.

If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated

hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until

the soft disconnect is negated.

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DS00003715A-page 27

USB7006

6.0

DEVICE CONFIGURATION

The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly

function when attached to a USB host controller. Microchip provides a comprehensive software programming tool,

MPLAB Connect Configurator (formerly ProTouch2), for OTP configuration of various USB7006 functions and registers.

All configuration is to be performed via the MPLAB Connect Configurator programming tool. For additional information

on this tool, refer to the MPLAB Connect Configurator programming tool product page at http://www.microchip.com/

design-centers/usb/mplab-connect-configurator.

Additional information on configuring the USB7006 is also provided in the “Configuration of the USB70xx” application

note, which contains details on the hub operational mode, SOC configuration stage, OTP configuration, USB configu-

ration, and configuration register definitions. This application note, along with additional USB7006 resources, can be

found on the Microchip USB7006 product page at www.microchip.com/USB7006.

Note:

Device configuration straps and programmable pins are detailed in Section 3.3, Configuration Straps and

Programmable Functions.

Refer to Section 7.0, Device Interfaces for detailed information on each device interface.

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DS00003715A-page 28

USB7006

7.0

DEVICE INTERFACES

The USB7006 provides multiple interfaces for configuration, external memory access, etc.. This section details the var-

ious device interfaces:

• SPI/SQI Master Interface

• SMBus/I2C Master/Slave Interfaces

• I2S Interface

Note:

For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable

Functions.

For information on device connections, refer to Section 4.0, Device Connections. For information on device

configuration, refer to Section 6.0, Device Configuration.

Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly

ProTouch2), for configuring the USB7006 functions, registers and OTP memory. All configuration is to be

performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,

refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/

design-centers/usb/mplab-connect-configurator.

7.1

SPI/SQI Master Interface

The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to

SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU

(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is

enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,

then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.

The entire firmware image is then executed in place entirely from the SPI interface. The SPI interface will remain con-

tinuously active while the hub is in the runtime state. The hub configuration options are also loaded entirely out of the

SPI memory device. Both the internal ROM firmware image and internal OTP memory are completely ignored while exe-

cuting the firmware and configuration from the external SPI memory.

The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in

Section 8.7, USB to SPI Bridging.

Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode

TABLE 7-1:

SPI/SQI PIN USAGE

SQI Mode

SPI Mode

Description

SPI_CE_N

SPI_CLK

SPI_D0

SPI_D1

-

SQI_CE_N

SQI_CLK

SQI_D0

SPI/SQI Chip Enable (Active Low)

SPI/SQI Clock

SPI Data Out; SQI Data I/O 0

SPI Data In; SQI Data I/O 1

SQI Data I/O 2

SQI_D1

SQI_D2

-

SQI_D3

SQI Data I/O 3

Note:

For SPI/SQI master timing information, refer to Section 9.6.10, SPI/SQI Master Timing.

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DS00003715A-page 29

USB7006

7.2

SMBus/I²C Master/Slave Interfaces

The device provides twothree independent SMBus/I²C controllers (Slave, and Master) which can be used to access

internal device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to

enable simultaneous master/slave operation and to minimize firmware overhead in processed I²C packets. The I²C

interfaces support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.

The SMBus/I²C interfaces are assigned to programmable pins (PFx). Refer to Section 3.3.4, PF[31:3] Configuration

(CFG_STRAP[2:1]) for additional information.

Note:

For SMBus/I²C timing information, refer to Section 9.6.7, SMBus Timing and Section 9.6.8, I2C Timing.

7.3

I²S Interface

The device provides an integrated I²S interface to facilitate the connection of digital audio devices. The I²S interface

conforms to the voltage, power, and timing characteristics/specifications as set forth in the I²S-Bus Specification, and

consists of the following signals:

• I2S_SDI: Serial Data Input

• I2S_SDO: Serial Data Output

• I2S_SCK: Serial Clock

• I2S_LRCK: Left/Right Clock (SS/FSYNC)

• I2S_MCLK: Master Clock

• MIC_DET: Microphone Plug Detect

Each audio connection is half-duplex, so I2S_SDO exists only on the transmit side and I2S_SDI exists only on the

receive side of the interface. Some codecs refer to the Serial Clock (I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/

Right Clock is commonly referred to as LRC or LRCK. The I²S and other audio protocols refer to LRC as Word Select

(WS).

The following codec is supported by default:

• Analog Devices ADAU1961 (24-bit 96KHz)

The I²S interface is assigned to programmable pins (PFx). Refer to Section 3.3.4, PF[31:3] Configuration

(CFG_STRAP[2:1]) for additional information.

Note:

For I²S timing information, refer to Section 9.6.9, I2S Timing. For detailed information on utilizing the I²S

interface, including support for other codecs, refer to the application note “USB7202/USB725x I²S Opera-

tion”, which can be found on the Microchip USB7006 product page at www.microchip.com/USB7006.

7.3.1

MODES OF OPERATION

The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple oper-

ating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,

and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is

recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two

channels: 16 bits per channel.

7.3.1.1

Asynchronous IN 48KHz Streaming

In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The

data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount

of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,

a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three reg-

isters to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water

mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_P-

KT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.

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USB7006

7.3.1.2

Adaptive OUT 48KHz Streaming

In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the

OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The

codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If

the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between

the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling

clock is decreased.

7.3.1.3

Synchronous Operation

For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally

1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of

time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.

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USB7006

8.0

FUNCTIONAL DESCRIPTIONS

This section details various USB7006 functions, including:

• Downstream Battery Charging

• Port Power Control

• PortSplit

• FlexConnect USB to GPIO Bridging

• USB to I2C Bridging

• USB to SPI Bridging

• Link Power Management (LPM)

• Resets

8.1

Downstream Battery Charging

The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role

in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery

charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the

device. Those components must be provided externally by the OEM.

FIGURE 8-1:

BATTERY CHARGING EXTERNAL POWER SUPPLY

DC Power

INT

SCL

Microchip

SOC

SDA

Hub

VBUS[n]

If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can

be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTLx pins, is on

a per port basis. For example, the OEM can configure two ports to support battery charging through high current power

FETs and leave the other two ports as standard USB ports.

The port control signals are assigned to programmable pins (PFx) and therefore the device must be programmed into

specific configurations to enable the signals. Refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for addi-

tional information.

For detailed information on utilizing the battery charging feature, refer to the application note “USB Battery Charging

with Microchip USB70xx Hubs”, which can be found on the Microchip USB7006 product page www.microchip.com/

USB7006.

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USB7006

8.2

Port Power Control

Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled

directly from the USB hub, or via the processor.

Note:

The PRT_CTLx function is assigned to programmable function pins (PFx) via configuration straps. Refer

to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for additional information.

8.2.1

PORT POWER CONTROL USING USB POWER SWITCH

When operating in combined mode, the device will have one port power control and over-current sense pin for each

downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,

the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable

the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert

the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-

fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.

Note:

An external power switch is the required implementation for Type-C ports due to the requirement that VBUS

on Type-C ports must be discharged to 0V when no device is attached to the port.

FIGURE 8-2:

PORT POWER CONTROL WITH USB POWER SWITCH

Pull‐Up Enable

50k

5V

PRT_CTLx

OCS

USB Power

Switch

EN

PRTPWR

USB

Device

FILTER

OCS

8.2.2

PORT POWER CONTROL USING POLY FUSE

When using the device with a poly fuse, there is no need for an output power control. A single port power control and

over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the

driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power

is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing

3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cath-

ode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register

this as a low resulting in an over-current detection. The open drain output does not interfere.

Note:

Type-C ports may not utilize a Poly-Fuse port power implementation due to the requirements that VBUS

on Type-C ports must be discharged to 0V when no device is attached to the port.

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USB7006

FIGURE 8-3:

PORT POWER CONTROL USING A POLY FUSE

5V

Pull-Up Enable

Poly Fuse

50k

PRT_CTLx

USB

Device

PRTPWR

FILTER

OCS

8.3

PortSplit

The PortSplit feature allows the USB 2.0 and USB 3.2 PHYs associated with a downstream port to be operationally sep-

arated. The intention of this feature is to allow a system designer to connect an embedded USB 3.x device to the USB

3.2 PHY, while allowing the USB 2.0 PHY to be used as either a standard USB 2.0 port or with a separate embedded

USB 2.0 device. PortSplit can be configured via OTP/SMBus. By default, all ports are configured to non-split mode.

When PortSplit is disabled on a specific port, the corresponding PRT_CTLx pin controls both the USB 2.0 and USB 3.2

portions of the port (port power and overcurrent condition). When PortSplit is enabled on a specific port, the corre-

sponding PRT_CTLx pin controls the USB 2.0 portion of the port, and the corresponding PRT_CTLx_U3 pin controls

the USB 3.2 portion of the port.

8.4

FlexConnect

The device allows the upstream port to be swapped with any downstream port, enabling any USB port to assume the

role of USB host at any time during hub operation. This host role exchange feature is called FlexConnect. Additionally,

the USB 2.0 ports can be flexed independently of the USB 3.2 ports.

This functionality can be used in two primary ways:

1. Host Swapping: This functionality can be achieved through a hub wherein a host and device can agree to swap

the host/device relationship; The host becomes a device, and the device becomes a host.

2. Host Sharing: A USB ecosystem can be shared between multiple hosts. Note that only 1 host may access to

the USB tree at a time.

FlexConnect can be enabled through any of the following three methods:

• I²C Control: The embedded I²C slave can be used to control the state of the FlexConnect feature through basic

write/read operations.

• USB Command: FlexConnect can be initiated via a special USB command directed to the hub’s internal Hub

Feature Controller device.

• Direct Pin Control: Any available GPIO pin on the hub can be assigned the role of a FlexConnect control pin.

Note:

Direct Pin Control is only available in certain configurations. Refer to Section 3.3.4, PF[31:3] Configuration

(CFG_STRAP[2:1]) for additional information.

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DS00003715A-page 34

USB7006

For detailed information on utilizing the FlexConnect feature, refer to the application note “USB70xx FlexConnect Oper-

ation”, which can be found on the Microchip USB7006 product page at www.microchip.com/USB7006.

8.5

USB to GPIO Bridging

The USB to GPIO bridging feature provides system designers expanded system control and potential BOM reduction.

General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V level digital control and input functions.

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-

form the following functions:

• Set the direction of the GPIO (input or output)

• Enable a pull-up resistor

• Enable a pull-down resistor

• Read the state

• Set the state

For detailed information on utilizing the USB to GPIO bridging feature, refer to the application note “USB to GPIO Bridg-

ing with Microchip USB70xx Hubs”, which can be found on the Microchip USB7006 product page at www.micro-

chip.com/USB7006.

8.6

USB to I²C Bridging

The USB to I²C bridging feature provides system designers expanded system control and potential BOM reduction. The

use of a separate USB to I²C device is no longer required and a downstream USB port is not lost, as occurs when a

standalone USB to I²C device is implemented.

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-

form the following functions:

• Configure I²C Pass-Through Interface

• I²C Write

• I²C Read

For detailed information on utilizing the USB to I²C bridging feature, refer to the application note “USB to I²C Bridging

with Microchip USB70xx Hubs”, which can be found on the Microchip USB7006 product page at www.microchip.com/

USB7006.

8.7

USB to SPI Bridging

The USB to SPI bridging feature provides system designers expanded system control and potential BOM reduction. The

use of a separate USB to SPI device is no longer required and a downstream USB port is not lost, as occurs when a

standalone USB to SPI device is implemented.

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-

form the following functions:

• Enable SPI Pass-Through Interface

• SPI Write/Read

• Disable SPI Pass-Through Interface

For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging

with Microchip USB70xx Hubs”, which can be found on the Microchip USB7006 product page at www.microchip.com/

USB7006.

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USB7006

8.8

Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM

states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB

suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.

TABLE 8-1:

LPM STATE DEFINITIONS

State

L2

Description

Entry/Exit Time to L0

Suspend

Entry: ~3 ms

Exit: ~2 ms (from start of RESUME)

L1

L0

Sleep

Entry: <10 us

Exit: <50 us

Fully Enabled (On)

-

8.9

Resets

The device includes the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.9.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On

and Configuration Strap Timing.

8.9.2

EXTERNAL CHIP RESET (RESET_N)

A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the

specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its asso-

ciated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of RESET_N causes the following:

1. The PHY is disabled and the differential pairs will be in a high-impedance state.

2. All transactions immediately terminate; no states are saved.

3. All internal registers return to the default state.

4. The external crystal oscillator is halted.

5. The PLL is halted.

8.9.3

USB BUS RESET

Note:

All power supplies must have reached the operating levels mandated in Section 9.2, Operating Condi-

tions**, prior to (or coincident with) the assertion of RESET_N.

In response to the upstream port signaling a reset to the device, the device performs the following:

1. Sets default address to 0.

2. Sets configuration to Unconfigured.

3. Moves device from suspended to active (if suspended).

4. Complies with the USB Specification for behavior after completion of a reset sequence.

The host then configures the device in accordance with the USB Specification.

Note:

The device does not propagate the upstream USB reset to downstream devices.

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DS00003715A-page 36

USB7006

9.0

9.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings*

Digital Core Supply Voltage (VCORE) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08V to +1.32V

+3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V

Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V

Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V

Positive voltage on XTALI/CLK_IN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.63 V

Positive voltage on USB DP/DM signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 V

Positive voltage on USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground . . . . .1.32 V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55^oC to +150^oC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125^oC

Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Refer to JEDEC Spec. J-STD-020

HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +/-3 kV

Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-

imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on

their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may

appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO

*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating

only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional

operation of the device at any condition exceeding those indicated in Section 9.2, Operating Conditions**, Section 9.5,

DC Specifications, or any other applicable section of this specification is not implied.

9.2

Operating Conditions**

Digital Core Supply Voltage (VCORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V

+3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V

Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V

XTALI/CLK_IN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V

USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V

USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +1.32 V

Ambient Operating Temperature in Still Air (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 3

Digital Core Supply Voltage Rise Time (T_RTin Figure 9-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ms

+3.3 V Supply Voltage Rise Time (T_RTin Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ms

Note 3: 0^oC to +70^oC for commercial version, -40^oC to +85^oC for industrial version.

**Proper operation of the device is guaranteed only within the ranges specified in this section.

Note:

Do not drive input signals without power supplied to the device.

 2021 Microchip Technology Inc.

DS00003715A-page 37

USB7006

FIGURE 9-1:

SUPPLY RISE TIME MODEL

Voltage

VDD33

T_RT

3.3 V

100%

90%

VCORE

10%

VSS

t_90%

Time

t_10%

Note:

The Power Supply Rise time requirement does not apply if the RESET_N signal is held low during power

on and released after power levels rise and stabilize above the power on thresholds, or if the RESET_N

signal is toggled after power supplies become stable.

9.3

Package Thermal Specifications

TABLE 9-1:

PACKAGE THERMAL PARAMETERS

Symbol

°C/W

Velocity (Meters/s)

19

16

14

0.1

9

0

1

_JA

2.5

0

_JT

_JB

_JC

_JB

1

0

1.3

10

0

1

-

Note:

Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51. For

industrial applications, the USB7006 requires multi-layer 2S4P PCB power dissipation.

DS00003715A-page 38

 2021 Microchip Technology Inc.

USB7006

9.4

Power Consumption

This section details the power consumption of the device as measured during various modes of operation. Power dis-

sipation is determined by temperature, supply voltage, and external source/sink requirements.

TABLE 9-2:

DEVICE POWER CONSUMPTION

Typical (mA) @ 25°C

VCORE (1.15V) VDD33 (3.3V)

5.4 2.3

Typical Power

(mW)

Global Suspend

VBUS Off

Reset

14

27

5

5.3

4.2

6.4

0.2

Data for Calculating Active Transfer Current

Upstream Port Link Speed Base Currents

SS Current

HS Current

370

58

27.3

19.7

Additional Current Per Enabled Port

SS Current

HS Current

143

1

9.1

10.8

Example Active Data Transfer Current Calculation: 1 SS+ Port and 2 HS Ports

Active Data Transfer Current (mA @ 3.3V)

Active Data Transfer Current (mA @ 1.15V)

{30.8} + {1 * 11.1} + {2 * 10.8} = 63.5

{410} + {1 * 179} + {2 * 1} = 591

Note:

In the Active Idle and Active Data Transfer sections of Table 9-2, the various port configurations are

indicated via the following acronyms:

SS = USB 3.2 SuperSpeed (Gen 1)

HS = USB 2.0 High Speed

 2021 Microchip Technology Inc.

DS00003715A-page 39

USB7006

9.5

DC Specifications

TABLE 9-3:

I/O DC ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Min

Typical

Max

Units

Notes

I Type Input Buffer

Low Input Level

V_IL

0.9

V

High Input Level

V_IH

1.25

IS Type Input Buffer

Low Input Level

V_IL

V_IH

0.9

V

High Input Level

1.25

100

Schmitt Trigger Hysteresis

V_HYS

160

240

mV

(V_IHT- V_ILT

)

O12 Type Output Buffer

Low Output Level

V_OL

V_OH

0.4

V

I_OL= 12 mA

High Output Level

VDD33-0.4

I_OH= -12 mA

OD12 Type Output Buffer

Low Output Level

V_OL

V

I_OL= 12 mA

Note 4

ICLK Type Input Buffer

(XTALI Input)

Low Input Level

High Input Level

V_IL

0.35

1.2

V

V_IH

0.9

IO-U Type Buffer

Note 5

(See Note 5)

Note 4: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.

Note 5: Refer to the USB 3.2 Gen 1 Specification for USB DC electrical characteristics.

DS00003715A-page 40

 2021 Microchip Technology Inc.

USB7006

9.6

AC Specifications

This section details the various AC timing specifications of the device.

9.6.1

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or

at the same time as VCORE. Similarly, RESET_N and/or VBUS_DET should rise after or at the same time as VDD33.

VBUS_DET and RESET_N do not have any other timing dependencies.

FIGURE 9-2:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

VDD33

t_VDD33

VCORE

t_reset

RESET_N/

VBUS_DET

TABLE 9-4:

Symbol

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Description

Min

Typ

Max

Units

t_VDD33

t_reset

VDD33 to VCORE rise delay

0

ms

VDD33 to RESET_N/VBUS_DET rise delay

9.6.2

POWER-ON AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where

RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following

timing requirements must be met. The operational levels (V_opp) for the external power supplies are detailed in

Section 9.2, Operating Conditions**.

FIGURE 9-3:

POWER-ON CONFIGURATION STRAP VALID TIMING

All External

Power Supplies

V_opp

t_csh

Configuration

Straps

TABLE 9-5:

Symbol

t_csh

POWER-ON CONFIGURATION STRAP LATCHING TIMING

Description

Min

Typ

Max

Units

Configuration strap hold after external power supplies at opera-

1

ms

tional levels

Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Con-

figuration Strap Timing for additional details.

 2021 Microchip Technology Inc.

DS00003715A-page 41

USB7006

9.6.3

RESET AND CONFIGURATION STRAP TIMING

Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of

RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to

Section 8.9, Resets for additional information on resets. Refer to Section 3.3, Configuration Straps and Programmable

Functions for additional information on configuration straps.

FIGURE 9-4:

RESET_N CONFIGURATION STRAP TIMING

t_rstia

RESET_N

t_csh

Configuration

Straps

TABLE 9-6:

Symbol

RESET_N CONFIGURATION STRAP TIMING

Description

Min

Typ

Max

Units

t_rstia

t_csh

RESET_N input assertion time

5

1

s

Configuration strap pins hold after RESET_N deassertion

ms

Note:

The clock input must be stable prior to RESET_N deassertion.

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply.

9.6.4

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

Figure 9-5 illustrates the SMBus Slave interface readiness in relation to power-on or de-assertion of RESET_N. In order

to ensure reliable SMBus slave operation, the SMBus master must allow the bus to remain idle until t_{SMBUS_RDY}timing

has been met. The operational levels (V_opp) for the external power supplies are detailed in Section 9.2, Operating Con-

ditions**.

FIGURE 9-5:

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

Power-on-Reset

All External

Power Supplies

V_opp

& Reset

SOC_CFG STAGE

SMBus

SMBus interface not available

(slave interface will stretch clock if addressed)

SMBus commands accepted

(ifSMBus slave interface is enabled)

TABLE 9-7:

Symbol

POWER-ON OR RESET TO SMBUS SLAVE READY TIMING

Description

Min

Typ

Max

Units

t_{SMBUS_RDY}Power-on or RESET_N deassertion to SMBus ready

40

ms

DS00003715A-page 42

 2021 Microchip Technology Inc.

USB7006

9.6.5

USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING

Figure 9-6 illustrates the SMBus Slave interface readiness in relation to ACK of the Slave interface to the “USB Attach

with SMBus Runtime Access” (AA56h) from the SMBus Master. In order to ensure reliable SMBus slave operation, the

SMBus master must allow the bus to remain idle after issuing the “USB Attach with SMBus Runtime Access” until t_AT-

_{TACH_RDY}timing has been met.

Note:

When accessing SMBus during runtime, it is critical to force some clocks to stay on. If this step is not taken,

the SMBus slave interface will not be accessible while the hub is placed into a Suspend state by the host.

FIGURE 9-6:

USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING

Attach

Command ACK

At tach

Command

SSOOCC__CCFFGGSSttaaggee

Runtime Stage

SMBus

SMBus interface not available

(slave interface will stretch clock if addressed)

SMBus commands accepted

(if ‘Attach with I2C slave enabled during

runtime’ command is used)

TABLE 9-8:

Symbol

USB ATTACH COMMAND TO SMBUS SLAVE READY TIMING

Description

Min

Typ

Max

Units

t_{ATTACH_RDY}USB Attach command to SMBus ready (Note 6)

11.5

ms

Note 6: The t_{ATTACH_RDY}values are preliminary and subject to change.

9.6.6

USB TIMING

All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-

versal Serial Bus Specification. Please refer to the Universal Serial Bus Revision 3.2 Specification, available at http://

www.usb.org/developers/docs.

9.6.7

SMBUS TIMING

All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-

tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available

at http://smbus.org/specs.

9.6.8

I²C TIMING

All device I²C signals conform to the 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) voltage, power, and

timing characteristics/specifications as set forth in the I²C-Bus Specification. Please refer to the I²C-Bus Specification,

available at http://www.nxp.com/documents/user_manual/UM10204.pdf.

9.6.9

I²S TIMING

All device I²S signals conform to the voltage, power, and timing characteristics/specifications as set forth in the I²S-Bus

Specification. Please refer to the I²S-Bus Specification, available at www.sparkfun.com/datasheets/BreakoutBoards/

I2SBUS.pdf

 2021 Microchip Technology Inc.

DS00003715A-page 43

USB7006

9.6.10

SPI/SQI MASTER TIMING

This section specifies the SPI/SQI master timing requirements for the device.

FIGURE 9-7:

SPI/SQI MASTER TIMING

t_ceh

SPI_CE_N

SPI_CLK

t_fc

t_cel

t_clq

t_dh

Input

data valid

SPI_D[3:0] (in)

SPI_D[3:0] (out)

t_ost_oh

t_ov

t_oh

Output

data valid

Output

data valid

TABLE 9-9:

Symbol

SPI/SQI MASTER TIMING (30 MHZ OPERATION)

Description

Min

Typ

Max

Units

t_fc

t_ceh

t_clq

t_dh

Clock frequency

30

MHz

ns

Chip enable (SPI_CE_N) high time

Clock to input data

100

13

ns

Input data hold time

0

5

ns

t_os

Output setup time

ns

t_oh

Output hold time

5

ns

t_ov

Clock to output valid

4

ns

t_cel

t_ceh

Chip enable (SPI_CE_N) low to first clock

Last clock to chip enable (SPI_CE_N) high

12

ns

TABLE 9-10: SPI/SQI MASTER TIMING (60 MHZ OPERATION)

Symbol

Description

Min

Typ

Max

Units

t_fc

t_ceh

t_clq

t_dh

Clock frequency

60

MHz

ns

Chip enable (SPI_CE_N) high time

Clock to input data

50

9

ns

Input data hold time

0

5

ns

t_os

Output setup time

ns

t_oh

Output hold time

5

ns

t_ov

Clock to output valid

4

ns

t_cel

t_ceh

Chip enable (SPI_CE_N) low to first clock

Last clock to chip enable (SPI_CE_N) high

12

ns

DS00003715A-page 44

 2021 Microchip Technology Inc.

USB7006

9.7

Clock Specifications

The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator input. If the single-ended clock

oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a

nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTALI/XTALO). The following circuit design (Figure 9-8) and specifications (Table 9-11) are required to ensure proper

operation.

FIGURE 9-8:

25MHZ CRYSTAL CIRCUIT

USB7006

XTALO

Y1

XTALI

C₁

C₂

9.7.1

CRYSTAL SPECIFICATIONS

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTALI/XTALO). Refer to Table 9-11 for the recommended crystal specifications.

TABLE 9-11: CRYSTAL SPECIFICATIONS

Parameter

Crystal Cut

Symbol

Min

Nom

Max

Units

Notes

AT, typ

Crystal Oscillation Mode

Crystal Calibration Mode

Frequency

Frequency Tolerance @ 25^oC

Frequency Stability Over Temp

Frequency Deviation Over Time

Total Allowable PPM Budget

Shunt Capacitance

Fundamental Mode

Parallel Resonant Mode

F_fund

F_tol

-

25.000

-

MHz

PPM

pF

-

±50

F_temp

F_age

-

±50

-

±3 to 5

-

Note 7

-

7 typ

20 typ

-

±100

C_O

C_L

-

Load Capacitance

-

pF

Drive Level

P_W

R₁

100

-

uW

Ω

^oC

Equivalent Series Resistance

Operating Temperature Range

XTALI/CLK_IN Pin Capacitance

XTALO Pin Capacitance

-

60

Note 8

-

Note 9

-

3 typ

-

pF

Note 10

pF

 2021 Microchip Technology Inc.

DS00003715A-page 45

USB7006

Note 7: Frequency Deviation Over Time is also referred to as Aging.

Note 8: 0 °C for commercial version, -40 °C for industrial version.

Note 9: +70 °C for commercial version, +85 °C for industrial version.

Note 10: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this

value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calcu-

late the value of the two external load capacitors. These two external load capacitors determine the accu-

racy of the 25.000 MHz frequency.

9.7.2

EXTERNAL REFERENCE CLOCK (CLK_IN)

When using an external reference clock, the following clock characteristics are required:

• 25 MHz

• 50% duty cycle ±10%, ±100 ppm

• Jitter < 100 ps RMS

DS00003715A-page 46

 2021 Microchip Technology Inc.

USB7006

10.0 PACKAGE OUTLINE

10.1 Package Marking Information

100-VQFN (12x12 mm)

PIN 1

e3

Legend:

i

R

Temperature range designator (Blank = commercial, i = industrial)

Product revision

nnn

e3

YY

Internal code

Pb-free JEDEC^®designator for Matte Tin (Sn)

Year code (last two digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note:

In the event the full Microchip part number cannot be marked on one line, it

will be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

* Standard device marking consists of Microchip part number, year code, week code and traceability code.

For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

For QTP devices, any special marking adders are included in QTP price.

 2021 Microchip Technology Inc.

DS00003715A-page 47

USB7006

10.2 Package Drawings

Note:

For the most current package drawings, see the Microchip Packaging Specification at:

http://www.microchip.com/packaging.

FIGURE 10-1:

100-VQFN PACKAGE (DRAWING)

6((

'(7$,/ꢆ$

'

$

%

(

127(ꢆꢂ

1

ꢂ

ꢈ

ꢅ'$780ꢆ%ꢇ

ꢅ'$780ꢆ$ꢇ

ꢈ;

ꢀꢁꢂꢀ &

ꢈ;

ꢀꢁꢂꢀ &

723ꢆ9,(:

ꢂꢀꢀ;

ꢀꢁꢀꢋ &

ꢀꢁꢂꢀ

& $ %

6($7,1*

3/$1(

&

'ꢈ

6,'(ꢆ9,(:

ꢀꢁꢂꢀ

& $ %

(ꢈ

H

ꢈ

ꢂ

.

127(ꢆꢂ

1

/

ꢂꢀꢀ;ꢆE

ꢀꢁꢀꢃ

ꢀꢁꢀꢄ

& $ %

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%27720ꢆ9,(:

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DS00003715A-page 48

 2021 Microchip Technology Inc.

USB7006

FIGURE 10-2:

100-VQFN PACKAGE (DIMENSIONS)

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&

$

6($7,1*

3/$1(

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8QLWV

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ꢈꢁ 3DFNDJHꢆLVꢆVDZꢆVLQJXODWHG

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%6&ꢏꢆ%DVLFꢆ'LPHQVLRQꢁꢆ7KHRUHWLFDOO\ꢆH[DFWꢆYDOXHꢆVKRZQꢆZLWKRXWꢆWROHUDQFHVꢁ

5()ꢏꢆ5HIHUHQFHꢆ'LPHQVLRQꢐꢆXVXDOO\ꢆZLWKRXWꢆWROHUDQFHꢐꢆIRUꢆLQIRUPDWLRQꢆSXUSRVHVꢆRQO\ꢁ

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 2021 Microchip Technology Inc.

DS00003715A-page 49

USB7006

FIGURE 10-3:

100-VQFN PACKAGE (LAND-PATTERN)

C1

X2

EV

100

1

2

ØV

C2 Y2

EV

G1

Y1

X1

SILK SCREEN

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.40 BSC

MIN

0.20

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C1

C2

X1

Y1

G1

V

8.10

11.70

Contact Pad Spacing

Contact Pad Width (X100)

Contact Pad Length (X100)

Contact Pad to Center Pad (X100)

Thermal Via Diameter

0.20

1.05

0.33

1.20

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-2407A

DS00003715A-page 50

 2021 Microchip Technology Inc.

USB7006

APPENDIX A: REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Revision Level & Date

Section/Figure/Entry

Correction

DS00003715A (01-08-21)

Initial release

 2021 Microchip Technology Inc.

DS00003715A-page 51

USB7006

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

PART NO.

[X]

XXX

-

/

Examples:

Device Tape and Reel

Option

Temperature

Range

Package

Automotive

Code

a)

b)

USB7006/KDX

Tray, 0C to +70C, 100-pin VQFN

USB7006T/KDX

Tape & reel, 0C to +70C, 100-pin VQFN

c)

d)

e)

USB7006-I/KDX

Tray, -40C to +85C, 100-pin VQFN

USB7006T-I/KDX

Tape & reel, -40C to +85C, 100-pin VQFN

USB7006-I/KDXVAO

Tray, -40C to +85C, Automotive Grade 3,

100-pin VQFN

Device:

USB7006

Tape and Reel

Option:

Blank = Standard packaging (tray)

T

= Tape and Reel (Note 1)

f)

USB7006T-I/KDXVAO

Tape & reel, -40C to +85C, Automotive Grade 3,

100-pin VQFN

Temperature

Range:

Blank

I

=

0C to +70C (Commercial)

-40C to +85C (Industrial/Automotive Grade 3)

Package:

KDX

Vxx

=

100-pin VQFN

Note 1:

Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Automotive

Code:

= 3 character code with “V” prefix,

specifying automotive product

 2021 Microchip Technology Inc.

DS00003715A-page 52

USB7006

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://microchip.com/support

 2021 Microchip Technology Inc.

DS00003715A-page 53

USB7006

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specifications contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We

believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's

Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual

property rights.

•

Microchip is willing to work with any customer who is concerned about the integrity of its code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we

are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously

improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital

Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for

relief under that Act.

Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device

applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application

meets with your specifications.

THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND

WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT

NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE

OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE,

COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP

HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICRO-

CHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF

FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety

applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless

otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,

CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,

MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,

PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other

countries.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion,

SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,

CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip

Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,

NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker,

RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II,

Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and

ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in

other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other

countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 9781522470229

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

 2021 Microchip Technology Inc.

DS00003715A-page 54

Worldwide Sales and Service

AMERICAS

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http://www.microchip.com/

support

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Tel: 408-436-4270

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Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

 2021 Microchip Technology Inc.

DS00003715A-page 55

02/28/20


型号：	USB7006-I/KDXVAO
厂家：	MICROCHIP
描述：	6-Port USB 3.2 Gen 1 Controller Hub
文件：	总55页 (文件大小：1750K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

USB7006-I/KDXVAO [MICROCHIP]

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