USB82642AM-A-000728-V02

USB82642

Automotive USB 2.0 Hub and Flash Media Card

Controller Combo

Highlights

Key Benefits

• AEC-Q100 compliance

• Single-chip USB 2.0 hub controller with 2

exposed hi-speed downstream ports

- Microchip’s parts are tested to meet or

exceed the requirements of the AEC-Q100

automotive qualification standards

• The dedicated flash media reader is internally

attached to a 3rd downstream port of the hub as a

USB compound device

• PortMap

• Hub and flash media reader/writer configuration

from a single source:

- Flexible port mapping and port disable

sequencing supports multiple platform

designs

- Configures internal code using an external

SPI ROM

• PortSwap

- Supports execution of external code from SPI

Flash EEPROM

- Programmable USB differential-pair pin loca-

tions ease PCB design by aligning USB sig-

nal traces directly to connectors

- Supports custom vendor, product, and lan-

guage ID when using an external EEPROM

• PHYBoost

• Supports full power management with individual

or ganged power control of each downstream port

- Programmable USB transceiver drive

strength recovers signal integrity

• Transaction Translator (TT) in the hub supports

operation of FS and LS peripherals

Target Applications

• Single 24 MHz crystal support

• Control of peripheral I²C devices by USB host

• Automotive integrated head unit

• Automotive breakout box

• Supports internally or externally regulated 1.8 V

core voltage operation

• Automotive media player dock

• Automotive consumer connectivity ports

• Portable device charging via USB

• Supports storage addressability of up to 2 TB

• One GPO output

• RoHS compliant packages

- 48-pin (7x7 mm²) VQFN

• Temperature ranges:

- 48VQFN: -40 ºC to +85 ºC

 2012-2021 Microchip Technology Inc.

DS60001253F-page 1

USB82642

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DS60001253F-page 2

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USB82642

Table of Contents

1.0 Introduction ..................................................................................................................................................................................... 4

2.0 Block Diagram ................................................................................................................................................................................. 6

3.0 Pin Configuration ............................................................................................................................................................................ 7

4.0 Pin Table ......................................................................................................................................................................................... 8

5.0 Pin Descriptions .............................................................................................................................................................................. 9

6.0 Pin Reset States ........................................................................................................................................................................... 17

7.0 Configuration Options ................................................................................................................................................................... 19

8.0 DC Parameters ............................................................................................................................................................................. 43

9.0 AC Specifications .......................................................................................................................................................................... 48

10.0 Package Information ................................................................................................................................................................... 50

Appendix A: Data Sheet Revision History ........................................................................................................................................... 54

Appendix B: Acronyms ........................................................................................................................................................................ 59

Appendix C: References ..................................................................................................................................................................... 60

The Microchip Web Site ...................................................................................................................................................................... 61

Customer Change Notification Service ............................................................................................................................................... 61

Customer Support ............................................................................................................................................................................... 61

Product Identification System ............................................................................................................................................................. 62

 2012-2021 Microchip Technology Inc.

DS60001253F-page 3

USB82642

1.0

INTRODUCTION

Microchip’s USB82642 is designed, fabricated, tested, characterized and qualified for automotive applications.

The USB82642 is a USB 2.0 compliant, hi-speed hub and card reader combo solution. This fully-integrated, single

chip solution provides USB expansion and flash media reader/writer integration. The Microchip USB82642 provides

an ultra fast interface between a USB host and today’s popular flash media formats. The controller allows read/write

capability to flash media including the following:

• Secure Digital^TM(SD)

• SD High Capacity^TM(SDHC)

• SD Extended Capacity^TM(SDXC)

• MultiMediaCard^TM(MMC)

• Embedded MultiMediaCard (eMMC)

The USB82642 offers a versatile, cost-effective and energy-efficient hi-speed hub controller with 2 downstream USB

2.0 ports and an SD/MMC flash media card interface. The dedicated flash media reader is internally attached to a 3rd

downstream port of the hub as a USB compound device. The flash media interface can support sustained transfer rates

exceeding 35 MB/s if the media and host support those rates.

Additionally the USB82642 provides an I²C over USB bridge and an SD over USB bridge. The I²C bridge allows for

control of any I²C device operating at 50 kHz serial clock, while the SD bridge supports the use of SDIO cards.

The USB82642 will attach to an upstream port as either a full-speed or full-/hi-speed hub. The hub supports low-speed,

full-speed, and hi-speed (if operating as a full-/hi-speed hub) downstream devices on all of the enabled downstream

ports.

All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors on D+

and D- pins and all required pull-down and pull-up resistors. The over-current sense inputs for the downstream facing

ports have internal pull-up resistors.

AEC-Q100 compliance: The USB82642 is specifically tailored for use in automotive applications requiring automotive

grade robustness starting with the comprehension of proprietary design for reliability techniques within the silicon IC

itself as well as for the package design.

• Automotive qualified technologies and processes are used to fabricate the products with enhanced monitors to

continuously drive improvements in accordance with Microchip’s zero-dpm methodology.

• Product qualification is focused on customer expectations and exceeds many of the automotive reliability stan-

dards including AEC-Q100.

• Microchip automotive services are provided during the life of the product from a dedicated organization of opera-

tions, quality, and product support personnel specialized in meeting the requirements of the automotive customer.

The USB82642 includes programmable features such as:

PortMap which provides flexible port mapping and disable sequences. The down-

stream ports of a USB82642 hub can be reordered or disabled in any sequence to

support multiple platform designs with minimum effort. For any port that is disabled,

the USB82642 automatically reorders the remaining ports to match the USB host

controller’s port numbering scheme.

PortSwap which adds per-port programmability to USB differential-pair pin loca-

tions. PortSwap allows direct alignment of USB signals (D+/D-) to connectors avoid-

ing uneven trace length or crossing of the USB differential signals on the PCB.

PHYBoost which enables four programmable levels of USB signal drive strength in

downstream port transceivers. PHYBoost attempts to restore USB signal integrity.

The boost graphic shows an example of hi-speed USB eye diagrams before (PHY-

Boost at 0%) and after (PHYBoost at 12%) signal integrity restoration in a compro-

mised system environment.

DS60001253F-page 4

 2012-2021 Microchip Technology Inc.

USB82642

1.1

Device Features

1.1.1

HARDWARE FEATURES

• Single-chip hub, flash media controller, and I²C device control over USB

• USB82642 supports the temperature range of -40 °C to +85 °C

• Transaction Translator (TT) in the hub supports operation of FS and LS peripherals

• Full power management with individual or ganged power control of each downstream port

• Optional support for external firmware access via SPI interfaces

• Code execution via SPI ROM which must meet the following qualifications:

- 60 MHz operation support

- Single bit or dual bit mode support

- Mode 0 or mode 3 SPI support

Compliance with the following flash media card specifications:

• Secure Digital 2.0

- SDSC, SDHC, and SDXC

- mircoSD and reduced form factor media

- SDIO - using the SDIO over USB bridge

- Supports storage addressability of up to 2 TB

• MultiMediaCard 4.2

- 1/4/8 bit

- Includes support for eMMC devices

• Control of I²C device using the I²C over USB bridge

• Supports internal regulator for 1.8 V core operation

• Supports external regulator for 1.8 V core operation

1.1.2

CONFIGURABLE HUB FEATURES

Default configuration is loaded by USB82642 following a reset. The USB82642 may also be configured by an external

I²C EEPROM or external SPI ROM flash, where the following features are supported:

• Customizable vendor ID, product ID, and device ID

• 12-hex digits maximum for the serial number string

• 29-character manufacturer ID and product strings for flash media reader/writer

• Compound device support on a port-by-port basis

- a port is permanently hardwired to a downstream USB peripheral device

• Select over-current sensing and port power control on an individual or ganged (all ports together) basis to match

the circuit board component selection

• Port power control and over-current detection/delay features

• Configure the delay time for filtering the over-current sense inputs

• Configure the delay time for turning on downstream port power

• Bus- or self-powered selection

• Hub port disable of non-removable configurations

• Flexible port mapping and disable sequencing supports multiple platform designs

• Programmable USB differential-pair pin location selection eases PCB layout by aligning USB signal lines directly

to connectors

• Programmable USB signal drive strength improves USB signal integrity using 4 levels of signal drive strength

• Indicate the maximum current that the 2-port hub consumes from the USB upstream port

• Manage the maximum current required for the hub controller

 2012-2021 Microchip Technology Inc.

DS60001253F-page 5

USB82642

2.0

BLOCK DIAGRAM

.

FIGURE 2-1:

USB82642 BLOCK DIAGRAM

DS60001253F-page 6

 2012-2021 Microchip Technology Inc.

USB82642

3.0

PIN CONFIGURATION

FIGURE 3-1:

USB82642 48-PIN VQFN (TOP VIEW)

GPO1

RESET_N

VBUS_DET

TEST0

SD_CMD

SD_D5

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

REG_EN

SD_CLK

SD_D6

VDDA33

USB82642AM

USBUP_DP

USBUP_DM

XTAL2

SD_D7

48-Pin VQFN

SD_D0

(Top View)

SD_D1

XTAL1 (CLKIN)

VDD18PLL

RBIAS

VDD33

VDD18

SD_nCD

SD_WP

VDDA33

Ground Pad

(must be connected

to VSS)

Indicates pins on the bottom of the device.

 2012-2021 Microchip Technology Inc.

DS60001253F-page 7

USB82642

4.0

PIN TABLE

TABLE 4-1:

USB82642 48-PIN TABLE (GROUPED BY FUNCTION)

Secure Digital (12 Pins)

SD_D7

SD_D6

SD_D2

SD_D5

SD_D1

SD_D4

SD_D0

SD_WP

SD_D3

SD_CLK

SD_CMD

SD_nCD

USB 2.0 Interface (10 Pins)

USBUP_DP

RBIAS

USBUP_DM

(3) VDDA33

XTAL1 (CLKIN)

VDD18PLL

XTAL2

REG_EN

2-Port USB Interface (7 Pins)

USBDN_DP2

USBDN_DP3

USBDN_DM2

USBDN_DM3

PRTCTL2

PRTCTL3

-

VBUS_DET

SPI Interface (4 Pins)

SPI_CE_N

SPI_CLK/

SCL_EP

SPI_DO/

SDA_EP/

SPI_DI

SPI_SPD_SEL

I²C Interface (2 Pins)

SCL

SDA

Misc (7 Pins)

RESET_N

GPO1

TEST0

TEST1

(1) NC

TEST2

CRD_PWR

Power (6 Pins)

Total 48

(4) VDD33

VDD33

VDD18

DS60001253F-page 8

 2012-2021 Microchip Technology Inc.

USB82642

5.0

PIN DESCRIPTIONS

This section provides a detailed description of each signal. The signals are arranged in functional groups according to

their associated interface. The pin descriptions below are applied when using the internal default firmware and can be

referenced in Chapter 7.0, Configuration Options on page 19. The acronyms used in this chapter can be referenced in

Appendix B:, "Acronyms," on page 59.

An N at the end of a signal name indicates that the active (asserted) state occurs when the signal is at a low voltage

level. When the N is not present, the signal is asserted when it is at a high voltage level. The terms assertion and nega-

tion are used exclusively in order to avoid confusion when working with a mixture of active low and active high signals.

The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high

or low voltage. The term negate, or negation, indicates that a signal is inactive.

5.1

USB82642 Pin Description

TABLE 5-1:

Symbol

USB82642 PIN DESCRIPTIONS

48-Pin

VQFN

Buffer

Type

If Pins not Used

Connection

Description

Secure Digital Interface

SD_D[7:0]

19

20

23

30

32

33

17

18

I/O12PU

Secure Digital Data 7-0

These are the bi-directional data signals SD_D0

- SD_D7.

Leave open

Note:

The pull-up resistance is a current

source that is limited to VDD.

SD_CLK

SD_CMD

21

O12

Secure Digital Clock

This is an output clock signal to SD/MMC

device.

Leave open

24

I/O12PU

Secure Digital Command

This is a bi-directional signal that connects to

the CMD signal of the SD/MMC device. The bi-

directional signal has a weak internal pull-up

resistor.

SD_nCD

SD_WP

14

13

I/O12PU

I/O12

Secure Digital Card Detect GPIO

Leave open

This is a GPIO designated by the default firm-

ware as the Secure Digital card detection pin

and has a default internal pull-up.

Secure Digital Write Protected GPIO

This is a GPIO designated by the default firm-

ware as the Secure Digital card mechanical

write protect pin.

I²C Interface

SDA

SCL

29

36

I/O12

Serial Data Signal

Serial Clock

Leave open

 2012-2021 Microchip Technology Inc.

DS60001253F-page 9

USB82642

TABLE 5-1:

USB82642 PIN DESCRIPTIONS (CONTINUED)

48-Pin

VQFN

Buffer

Type

If Pins not Used

Connection

Symbol

Description

USB Interface

USB Bus Data

USBUP_DM

USBUP_DP

43

42

I/O-U

Leave open

These pins connect to the upstream USB bus

data signals (host port or upstream hub).

USBUP_DM and USBUP_DP can be swapped

using the PortSwap feature.

USBDN_DM

[3:2]

USBDN_DP

[3:2]

3

1

4

2

I/O-U

USB Bus Data

Leave open

These pins connect to the downstream USB bus

data signals and can be swapped using the

PortSwap feature.

PRTCTL[3:2]

7

6

I/OD12PU USB Power Enable

As an output, these pins enables power down-

stream USB peripheral devices. See Section

5.3, "Port Power Control" for diagram and usage

instructions.

As an input, when the power is enabled, these

pins monitor the over-current condition. When

an over-current condition is detected, these pins

turn the power off.

VBUS_DET

39

I

Detect Upstream VBUS Power

Pull up.

The Microchip hub monitors VBUS_DET to

determine when to assert the internal D+ pull-up

resistor (signaling a connect event).

When designing a detachable hub, connect this

pin to the VBUS power pin of the USB port that

is upstream of the hub.

Note:

Pull down will

disable entire

USB82642 chip.

For self-powered applications with a perma-

nently attached host, this pin should be pulled

up, typically to VDD33.

VBUS is a 3.3 volt input. A resistor divider must

be used when connecting to 5 volts of USB

power.

RBIAS

XTAL1 (CLKIN)

XTAL2

47

45

44

I-R

USB Transceiver Bias

N/A

A 12.0 kΩ, ±1.0% resistor is attached from VSS

to this pin in order to set the transceiver's inter-

nal bias currents.

ICLKx

OCLKx

24 MHz Crystal Input/External Clock Input

This pin can be connected to one terminal of the

crystal or it can be connected to an external

24 MHz clock when a crystal is not used.

24 MHz Crystal Output

N/A

This is the other terminal of the crystal, or a no

connect pin, when an external clock source is

used to drive XTAL1 (CLKIN).

Note:

Leave it open,

when an exter-

nal clock source

is used to drive

XTAL1 (CLKIN).

DS60001253F-page 10

 2012-2021 Microchip Technology Inc.

USB82642

TABLE 5-1:

USB82642 PIN DESCRIPTIONS (CONTINUED)

48-Pin

VQFN

Buffer

Type

If Pins not Used

Connection

Symbol

Description

1.8 V PLL Power Bypass

VDD18PLL

46

-

This pin is the 1.8 V power bypass for the PLL.

This pin requires an external bypass capacitor

of 1.0 µF.

If REG_EN is low, this pin serves as a power

supply (1.8 V) for the device.

VDDA33

5

-

3.3 V Analog Power

41

48

• 48VQFN - Pin 48 requires an external

bypass capacitor of 4.7 µF.

SPI Interface

SPI_CE_N

SPI_CLK/

8

9

O12

SPI Chip Enable

Leave open

This is the active low chip enable output. If the

SPI interface is enabled, drive this pin high in

power down states.

I/O12

SPI Clock

This is the SPI clock out to the serial ROM. See

Section 5.4, "ROM BOOT Sequence" for dia-

gram and usage instructions.

During reset, this pin is driven low.

SCL_EP

SPI_DO/

When configured, this is the I²C EEPROM clock

pin.

Leave open

10

I/O12

SPI Data Out

This is the data out for the SPI port. See Section

5.4, "ROM BOOT Sequence" for diagram and

usage instructions.

SDA_EP

This pin is the data pin when the device is con-

nected to the optional I²C EEPROM.

Leave open

SPI_SPD_SEL

This pin is used to pick the speed of the SPI

interface. During RESET_N assertion, this pin

will be tri-stated with the weak pull-down resistor

enabled. When RESET_N is negated, the value

on the pin will be internally latched, and the pin

will revert to SPI_DO functionality. Additionally,

the internal pull-down will be disabled.

0: 30 MHz (deprecated and might be removed

in future versions)

1: 60 MHz

If the latched value is 1, then the pin is tri-stated

when the chip is in the suspend state.

If the latched value is 0, then the pin is driven

low during a suspend state.

SPI_DI

11

I/O12PD

SPI Data In

Leave open

This is the data in to the controller from the SPI

ROM.

 2012-2021 Microchip Technology Inc.

DS60001253F-page 11

USB82642

TABLE 5-1:

USB82642 PIN DESCRIPTIONS (CONTINUED)

48-Pin

VQFN

Buffer

Type

If Pins not Used

Connection

Symbol

Description

Misc

GPO1

37

35

I/O12

This general purpose pin is set to be used as an

output.

Leave open

CRD_PWR

I/O200

Card power drive: 3.3 V (200 mA)

This pin powers the multiplexed flash media

interface (slot) for the SD/MMC interface.

Bits 0, 1, 2, and 3 control FET 2 of Register A5h.

See Section 7.5.2.11, "A4h-A5h: LUN 0 Power

Configuration," on page 27 for more information.

NC

31

22

IPU

Leave open

N/A

REG_EN

Regulator Enable

This pin is internally pulled up to enable the

internal 1.8 V regulators. In order to disable the

regulators, this pin will need to be externally

connected to ground.

When the internal regulator is enabled, the 1.8 V

power pins must be left unconnected, except for

the required bypass capacitors.

RESET_N

TEST[2:0]

VDD18

38

I

RESET input

N/A

This active low signal is used by the system to

reset the chip. The active low pulse should be at

least 1 µs wide. In addition, consider Note 3 in

Section 8.2, Operating Conditions.

28

27

40

IPD

TEST Input

Connect to

ground.

Tie these test pins to ground for normal opera-

tion.

Digital/Power/Ground

15

-

1.8 V Digital Core Power Bypass

This pin requires an external bypass capacitor

of 1.0 µF.

If REG_EN is low, this pin serves as a power

supply (1.8 V) for the device.

VDD33

12

16

25

34

-

3.3 V Power and Regulator Input

• 48VQFN - Pin 16 requires an external

bypass capacitor of 4.7 µF minimum.

VDD33 (OTP)

VSS

26

-

3.3 V Power

ePad

Ground Pad

The ground pad is the only VSS for the device

and must be tied to ground with multiple vias.

DS60001253F-page 12

 2012-2021 Microchip Technology Inc.

USB82642

5.2

Buffer Type Descriptions

TABLE 5-2:

Buffer

USB82642 BUFFER TYPE DESCRIPTIONS

Description

I

Input

IPU

IS

Input with weak internal pull-up

Input with Schmitt trigger

I/O12

I/O200

Input/output buffer with 12 mA sink and 12 mA source

Input/output buffer 12 mA with FET disabled, 100/200 mA source only when the FET is

enabled

I/O12PD

Input/output buffer with 12 mA sink and 12 mA source, with an internal weak pull-down

resistor

I/O12PU

I/OD12PU

O12

Open drain, 12 mA sink with pull-up. Input with Schmitt trigger

Input/open drain output buffer with a 12 mA sink

Output buffer with a 12 mA sink and a 12 mA source

XTAL clock input

ICLKx

OCLKx

I/O-U

XTAL clock output

Analog input/output defined in USB Specification [3]

RBIAS

I-R

 2012-2021 Microchip Technology Inc.

DS60001253F-page 13

USB82642

5.3

Port Power Control

5.3.1

PORT POWER CONTROL USING USB POWER SWITCH

The USB82642 has a single port power control and over-current sense signal for each downstream port. When disabling

port power, the driver will actively drive a 0. To avoid unnecessary power dissipation, the internal pull-up resistor will be

disabled at that time. When port power is enabled, the output driver is disabled, and the pull-up resistor is enabled cre-

ating an open drain output.

If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmitt trigger

input will detect this event as a low. The open drain output does not interfere. The over-current sense filter handles the

transient conditions, such as low voltage, while the device is powering up.

FIGURE 5-1:

PORT POWER CONTROL WITH USB POWER SWITCH

5 V

PRTCTL3

OCS

USB Power

Switch

EN

USB

Device

USB82642

5 V

PRTCTL2

OCS

USB Power

Switch

EN

USB

Device

DS60001253F-page 14

 2012-2021 Microchip Technology Inc.

USB82642

5.3.2

PORT POWER CONTROL USING A POLY FUSE

When using the USB82642 with a poly fuse, an external diode must be used (see Figure 5-2). When disabling port

power, the USB82642 driver will drive a 0. This procedure will have no effect since the external diode will isolate the pin

from the load. When port power is enabled, the USB82642 output driver is disabled, and the pull-up resistor is enabled

which creates an open drain output. This means that the pull-up resistor is providing 3.3 V to the anode of the diode. If

there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to zero volts.

The anode of the diode will be at 0.7 V, and the Schmitt trigger input will register this as a low resulting in an over-current

detection. The open drain output does not interfere.

FIGURE 5-2:

PORT POWER CONTROL WITH SINGLE POLY FUSE AND MULTIPLE LOADS

5 V

PRTCTL3

USB

Device

USB82642

5 V

PRTCTL2

USB

Device

When using a single poly fuse to power all devices, note that for the ganged situation, all power control pins must be

tied together.

FIGURE 5-3:

PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE

5 V

PRTCTL3

Poly Fuse

USB82642

PRTCTL2

USB

Device

 2012-2021 Microchip Technology Inc.

DS60001253F-page 15

USB82642

5.4

ROM BOOT Sequence

After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid signature of

2DFU(device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is

enabled and code execution begins at address 0x0000 in the external SPI device. Otherwise, code execution continues

from the internal ROM.

The SPI ROM required for the USB82642 is a recommended minimum of 1 Mbit and support 60 MHz. The frequency

used is set using the SPI_SPD_SEL. For 60 MHz operation, this pin must pulled up through a 100 kΩ resistor. SPI_SP-

D_SEL is used to choose the speed of the SPI interface. During RESET_N assertion, this pin will be tri-stated with the

weak pull-down resistor enabled. When RESET_N is negated, the value on the pin will be internally latched, and the pin

will revert to SPI_DO functionality, and the internal pull-down is disabled.

The firmware can determine the speed of operation on the SPI port by checking the SPI_SPEED in the SPI_CTL Register

(0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is

recommended. Both mode 0 and mode 3 SPI ROMS are also supported.

FIGURE 5-4:

SPI ROM CONNECTION

SPI_CE_N

CE#

CLK

SPI_CLK / SCL

SPI ROM

USB82642

SPI_DO / SDA / SPI_SPD_SEL

SPI_DI

SI

SO

DS60001253F-page 16

 2012-2021 Microchip Technology Inc.

USB82642

6.0

PIN RESET STATES

TABLE 6-1:

LEGEND FOR PIN RESET STATES

Symbol

Description

0

Output driven low

1

Output driven high

IP

PU

PD

none

-

Input enabled

Hardware enables pull-up

Hardware enables pull-down

Hardware disables pad

Hardware disables function

Z

Hardware disables pad. Both output driver and input buffers are disabled.

6.1

Pin Reset States

TABLE 6-2:

USB82642 RESET STATES

Reset State

Input/

Pin Name

PU/

PD

Function

Output

1

2

USBDN_DM2

USBDN_DP2

USBDN_DM3

USBDN_DP3

PRTCTL

SPI_CE_N

IO

IP

0

PD

-

USBDN_DP2

USBDN_DM3

USBDN_DP3

PRTCTL2

3

4

6

7

PRTCTL3

0

-

8

SPI_CE_N

1

-

9

SPI_CLK/SCL_EP

0

-

10

11

13

14

17

18

SPI_DO/SDA_EP/SPI_SPD_SEL

IO

0

PD

-

SPI_DI

SD_WP

SD_nCD

SD_D1

SD_D0

SPI_DI

IO

IP

0

IO

IP

Z

PU

-

none

Z

-

 2012-2021 Microchip Technology Inc.

DS60001253F-page 17

USB82642

TABLE 6-2:

USB82642 RESET STATES (CONTINUED)

Reset State

Input/

Pin Name

PU/

PD

Function

Output

19

20

21

22

23

24

27

28

29

30

31

32

33

35

36

37

38

39

40

42

43

SD_D7

none

Z

-

SD_D6

none

-

SD_CLK

REG_EN

SD_D5

none

Z

-

none

IP

Z

PU

none

-

SD_CMD

TEST1

none

Z

-

none

Z

-

TEST2

none

Z

-

SDA

IO

IP

Z

PU

SD_D4

none

-

NC

none

-

SD_D3

none

Z

-

SD_D2

none

Z

-

CRD_PWR

SCL

IO

Z

-

IO

0

-

GPO1

GPO

0

-

RESET_N

VBUS_DET

TEST0

RESET_N

VBUS_DET

TEST

USBUP_DP

USBUP_DM

IP

Z

-

PD

-

USBUP_DP

USBUP_DM

Z

-

DS60001253F-page 18

 2012-2021 Microchip Technology Inc.

USB82642

7.0

7.1

CONFIGURATION OPTIONS

Hub

Microchip’s USB 2.0 hub is fully compliant to the Universal Serial Bus 2.0 Specification [3]. See Chapter 11 (Hub Spec-

ification) for general details regarding hub operation and functionality.

The hub provides a single Transaction Translator (TT) shared by both downstream ports. The TT contains 4 non-peri-

odic buffers.

7.1.1

HUB CONFIGURATION OPTIONS

The Microchip hub supports a large number of configurable features (some are mutually exclusive). There are two prin-

cipal ways to configure the hub:

• default settings

• settings loaded from an external EEPROM or SPI Flash device

7.1.1.1

Power Switching Polarity

The hub will only support active high power controllers.

7.1.2

VBus DETECT

According to Section 7.2.1 of the USB 2.0 Specification [3], a downstream port can never provide power to its D+ or D-

pull-up resistors unless the upstream port’s VBUS is in the asserted (powered) state. The VBUS_DET pin on the hub

monitors the state of the upstream VBUS signal and will not pull-up the D+ resistor if VBUS is not active. If VBUS goes

from an active to an inactive state (not powered), the hub will remove power from the D+ pull-up resistor within 10 sec-

onds.

7.2

Card Reader

The Microchip USB82642 is fully compliant with the following flash media card reader specifications:

• Secure Digital 2.0

- SDSC, SDHC, and SDXC

- mircoSD and reduced form factor media

- SDIO - using the SDIO over USB bridge

• MultiMediaCard 4.2

- 1/4/8 bit

- includes support for eMMC devices

7.3

I²C over USB Bridge

USB82642 offers a I²C over USB bridge functionality. Host initiated SCSI pass-through commands are sent to

USB82642 using Mass Storage Class driver to control I²C master interface. Additional support for detecting clock

stretching during reads is also provided.

The following features are exposed through host side I²C API:

• Write_I2C_Stream

- Send any length of data over the I²C interface.

- The sequence follows the I²C protocol for writing data.

• WriteRead_I2C_Stream

- Read any length of data over the I²C interface.

- The sequence follows the I²C protocol for reading data.

• GPIO_1_SET_OUTPUT

- This method allows an application to control GPO1 pin. This can be driving RST of the I²C slave device.

For additional configuration information and protocol details, see the USB to I²C Bridge Reference Guide [1].

 2012-2021 Microchip Technology Inc.

DS60001253F-page 19

USB82642

7.4

SDIO Over USB Bridge

The SDIO over USB bridge allows for transmission of multiple types of data from an SDIO device over USB. The SDIO

over USB bridge uses USB Mass Storage Class Bulk-Only Transport and SCSI pass through to support this feature.

The USB82642 utilizes the following specifications:

• USB Mass Storage Class Specification Overview [4]

• USB Mass Storage Class Bulk-Only Transport [5]

• SCSI Architecture Model - 2 (SAM-2) [6]

• SCSI Primary Commands - 2 (SPC-2) [6]

• SD Specifications Part 1 Physical Layer Specification [7]

• SD Specifications Part E1 SDIO Specification [8]

• SD Specifications Part A2 SD Host Controller Standard Specification [9]

7.4.1

PROTOCOL OVERVIEW

For additional protocol information see the SDIO over USB Bridge Reference Guide [2].

7.4.1.1

USB Enumeration

A compliant device will enumerate at least one Interface Descriptor with the USB BaseClass of Mass Storage Device

Class, SubClass of SCSI transparent command set, and Protocol of Bulk-Only Transport. See USB Mass Storage Class

Specification Overview [4] Tables 2.1 and 3.1.

7.4.1.2

USB Bulk-Only Transport

The protocol will be encapsulated by Command Block Wrappers (CBWs), where the CBWCB field depicted in Table 5.1

of the USB Mass Storage Class Bulk-Only Transport [5] document, Section 5, contains the SCSI Command Descriptor

Blocks (CDBs). Data is returned according to the specific definition of each CDB.

The execution status of each CDB will be returned in a Command Status Wrapper (CSW) as defined Section 5.2 of the

same document.

7.5

System Configurations

7.5.1

EEPROM/SPI INTERFACE

The USB82642 can be configured via a 2-wire (I²C) EEPROM (512x8) or an external SPI flash device containing the

firmware for the USB82642. If an external configuration device does not exist, the internal default values will be used.

If one of the external devices is used for configuration, the OEM can update the values through the USB interface. The

hub will then attach to the upstream USB host.

The USBDM tool set is available in the Hub Card reader combo software release package.

DS60001253F-page 20

 2012-2021 Microchip Technology Inc.

USB82642

7.5.2

TABLE 7-1:

Address

EEPROM DATA DESCRIPTOR

INTERNAL FLASH MEDIA CONTROLLER CONFIGURATIONS

Register Name

Description

Internal Default Value

00h-19h

USB_SER_NUM

USB Serial Number

000008264001

(Unicode)

1Ah-1Bh

1Ch-1Dh

USB_VID

USB_PID

USB Vendor ID

USB Product ID

0424

4040 (ROM/firmware version

000528)

4041 (ROM/firmware version

000728)

1Eh-21h

22h-5Dh

5Eh-99h

USB_LANG_ID

USB_MFR_STR

USB_PRD_STR

USB Language Identifier

USB Manufacturer String

USB Product String

0409

(see Note 1)

Generic

(Unicode)

Ultra Fast Media Reader

(Unicode)

9Ah

9Bh

USB_BM_ATT

USB_MAX_PWR

ATT_LB

USB BmAttribute

USB Max Power

Attribute Lo byte

80h

30h (96 mA)

9Ch

40h (Reverse SD_WP only)

9Dh

rsvd

9Eh

ATT_LHB

Attribute Lo Hi byte

Attribute Hi byte

00h

9Fh

ATT_HB

A0h-A3h

A4h

rsvd

LUN_PWR_LB

LUN_PWR_HB

rsvd

LUN Power Lo byte

LUN Power Hi byte

00h

0Ah

A5h

A6h-BEh

BFh-C5h

C6h-CDh

CEh-D2h

DEV3_ID_STR

INQ_VEN_STR

INQ_PRD_STR

Device 3 Identifier String

Inquiry Vendor String

SD/MMC

Generic

82642

48VQFN Inquiry Product

String

D3h

DYN_NUM_LUN

LUN_DEV_MAP

rsvd

Dynamic Number of LUNs

LUN to Device Mapping

01h

D4h-D7h

D8h-DAh

DBh-DDh

FFh, 00h, 00h, 00h

SD_MMC_BUS_TIMING

SD/MMC Bus Timing

Control

59h, 56h, 97h

(Note 2)

 2012-2021 Microchip Technology Inc.

DS60001253F-page 21

USB82642

TABLE 7-1:

Address

INTERNAL FLASH MEDIA CONTROLLER CONFIGURATIONS (CONTINUED)

Register Name Description Internal Default Value

Refer to Table 7-2, “Hub Controller Configurations,” on page 23

for a continuation of the register values DEh-17Fh.

Internal Flash Media Controller Extended Configurations:

The registers below are enabled by setting bit 7 of bmAttribute.

100h-106h

107h-10Dh

10Eh-114h

115h-11Bh

11Ch-122h

123h-145h

146h

CLUN0_ID_STR

CLUN1_ID_STR

CLUN2_ID_STR

CLUN3_ID_STR

CLUN4_ID_STR

rsvd

LUN 0 Identifier String

LUN 1 Identifier String

LUN 2 Identifier String

LUN 3 Identifier String

LUN 4 Identifier String

COMBO

DYN_NUM_ EXT_LUN

Dynamic Number of

Extended LUNs

00h

147h-14Bh

14Ch-17Bh

17Ch-17Fh

LUN_DEV_MAP

rsvd

LUN to Device Mapping

FFh, FFh, FFh, FFh, FFh

NVSTORE_SIG2

Non-Volatile Storage

Signature

ecf1

Note that the following applies to the system values and descriptions:

• rsvd = reserved for internal use; do not write to these registers

Note 1: Refer to the USB 2.0 Specification [3] for other language codes.

Note 2: This register value must not be changed from the default value.

DS60001253F-page 22

 2012-2021 Microchip Technology Inc.

USB82642

TABLE 7-2:

Address

HUB CONTROLLER CONFIGURATIONS

Register Name

Description

Internal Default Value

DEh

DFh

E0h

VID_LSB

VID_MSB

PID_LSB

Vendor ID Least Significant Byte

Vendor ID Most Significant Byte

24h

04h

41h

48VQFN Product ID Least

Significant Byte

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

F0h

F1h

F2h

F3h

PID_MSB

DID_LSB

Product ID Most Significant Byte

Device ID Least Significant Byte

Device ID Most Significant Byte

Configuration Data Byte 1

Configuration Data Byte 2

Configuration Data Byte 3

Non-Removable Devices

Port Disable (Self)

40h

A2h

08h

8Bh

28h

00h

02h

00h

01h

32h

01h

32h

00h

DID_MSB

CFG_DAT_BYT1

CFG_DAT_BYT2

CFG_DAT_BYT3

NR_DEVICE

PORT_DIS_SP

PORT_DIS_BP

MAX_PWR_SP

MAX_PWR_BP

HC_MAX_C_SP

HC_MAX_C_BP

PWR_ON_TIME

BOOST_UP

Port Disable (Bus)

Max Power (Self)

Max Power (Bus)

Hub Controller Max Current (Self)

Hub Controller Max Current (Bus)

Power-on Time

Boost_Up

BOOST_3:2

Boost_3:2

PRT_SWP

PortSwap

PRTM12

PortMap 12

PRTM3

PortMap 3

TABLE 7-3:

OTHER INTERNAL CONFIGURATIONS

Register Name

Address

Description

Internal Default Value

F4h

SD_CLK_LIM

SD Clock Limit for the Flash

Media Controller

00h

F5h

F6h

rsvd

MEDIA_SETTINGS

rsvd

SD1/2 Timeout Configuration

Non-Volatile Storage Signature

00h

F7h-FBh

FCh-FFh

NVSTORE_SIG

ATA2

 2012-2021 Microchip Technology Inc.

DS60001253F-page 23

USB82642

7.5.2.1

00h-19h: USB Serial Number Option

Byte

25:0

7.5.2.2

Name

Description

USB_SER_NUM

Maximum string length is 12 hex digits. Must be unique to each device.

1Ah-1Bh: USB Vendor Identifier Option

Byte

Name

Description

1:0

USB_VID

This ID is unique for every vendor, where the vendor ID is assigned by the

USB Implementer’s Forum.

7.5.2.3

1Ch-1Dh: USB Product Identifier Option

Byte

Name

Description

1:0

USB_PID

This ID is unique for every product, where the product ID is assigned by the

vendor.

7.5.2.4

1Eh-21h: USB Language Identifier Option

Byte

Name

Description

3:0

USB_LANG_ID

English language code = 0409

7.5.2.5

22h-5Dh: USB Manufacturer String Length

Byte

Name

59:0

USB_MFR_STR

Maximum string length is 29 characters.

7.5.2.6

5Eh-99h: USB Product String Length

Byte

Name

59:0

USB_PRD_STR

This string is used during the USB enumeration process by Windows^®. The

maximum string length is 29 characters.

DS60001253F-page 24

 2012-2021 Microchip Technology Inc.

USB82642

7.5.2.7

9Ah: USB BmAttribute (1 byte)

Bit

7:0

Name

Description

USB_BM_ATT

Self- or Bus-Power: Selects between self- and bus-powered operation.

The hub is either self-powered (draws less than 2 mA of upstream bus power)

or bus-powered (limited to a 100 mA maximum of upstream power prior to

being configured by the host controller).

When configured as a bus-powered device, the Microchip hub consumes less

than 100 mA of current prior to being configured. After configuration, the bus-

powered Microchip hub (along with all associated hub circuitry, any embed-

ded devices if part of a compound device, and 100 mA per externally avail-

able downstream port) must consume no more than 500 mA of upstream

VBUS current. The current consumption is system dependent, and the OEM

must ensure that the USB 2.0 specifications are not violated.

When configured as a self-powered device, <1 mA of upstream VBUS current

is consumed and all ports are available, with each port being capable of

sourcing 500 mA of current.

80= Bus-powered operation

C0= Self-powered operation

A0= Bus-powered operation with remote wake-up

E0= Self-powered operation with remote wake-up

7.5.2.8

9Bh: USB MaxPower (1 byte)

Bit

Name

Description

7:0

USB_MAX_PWR

USB Max Power per USB Specification [3]. Do NOT set this value greater

than 100 mA.

 2012-2021 Microchip Technology Inc.

DS60001253F-page 25

USB82642

7.5.2.9

9Ch-9Fh: Attribute Byte Descriptions

Bit

Number

Byte

Name

Description

0

ATT_LB

3:0

4

Always read as 0

Inquire Manufacturer and Product ID Strings

1: use the Inquiry Manufacturer and Product ID Strings.

0: (default) - use the USB Descriptor Manufacturer and Product ID Strings.

5

6

Always read as 0

Reverse SD Card Write Protect Sense

1: (default) - SD cards will be write protected when SW_nWP is high, and

writable when SW_nWP is low.

0: SD cards will be write protected when SW_nWP is low, and writable

when SW_nWP is high.

7

7:0

0

Always read as 0

1

2

rsvd

ATT_LHB

Attach on Card Insert/Detach on Card Removal

1: attach on Insert is enabled

0: (default) - attach on Insert is disabled

1

2

Always read as 0

Use LUN Power Configuration

1: custom LUN Power Configuration stored in the NVSTORE is used

0: (default) - default LUN Power Configuration is used.

7:3

7:0

Always read as 0

3

ATT_HB

7.5.2.10

A0h-A3h: Reserved

Byte

Name

Description

3:0

rsvd

DS60001253F-page 26

 2012-2021 Microchip Technology Inc.

USB82642

7.5.2.11

A4h-A5h: LUN 0 Power Configuration

The USB82642 has one internal FET which can be utilized for card power. The settings are stored in NVSTORE and

provide the following features:

1. A card can be powered by an external FET or by an internal FET.

2. The power limit is set to 200 mA default for the internal FET, but can be set to 100 mA.

Each media uses two bytes to store its LUN power configuration. Bit 3 selects between internal or external. For internal

FETs bits 0 through 2 are used for the power limit. Only 2 of the possible 8 values are currently specified.

TABLE 7-4:

FET CONFIGURATION

FET

Type

Bits

Bit Type

Low Nibble

Description

0

1

2

FET Lo

Byte

3:0

7:4

3:0

rsvd

High Nibble

FET Hi

Byte

Low Nibble

0000b Disabled

0001b External FET enabled

1000b Internal FET with 100 mA power limit

1010b Internal FET with 200 mA power limit

3

7:4

High Nibble

rsvd

7.5.2.12

A6h-BEh: Reserved

Byte

Name

Description

25:0

rsvd

7.5.3

DEVICE ID STRINGS

7.5.3.1

BFh-C5h: Device 3 Identifier String

Byte

6:0

Name

Description

DEV3_ID_STR

These bytes are used to specify the LUN descriptor returned by the device.

These bytes are used in combination with the LUN to device mapping bytes

in applications where the OEM wishes to reorder and rename the LUNs. If

this device is configured to be part of a COMBO LUN then this string is

ignored for the appropriate CLUNx_ID_STR.

7.5.3.2

C6h-CDh: Inquiry Vendor String

Byte

Name

Description

7:0

INQ_VEN_STR

If bit 4 of the 1st attribute byte is set, the device will use these strings in

response to a USB inquiry command, instead of the USB descriptor manufac-

turer and product ID strings.

 2012-2021 Microchip Technology Inc.

DS60001253F-page 27

USB82642

7.5.3.3

CEh-D2h: Inquiry Product String

Byte

4:0

Name

Description

INQ_PRD_STR

If bit 4 of the 1st attribute byte is set, the device will use these strings in

response to a USB inquiry command, instead of the USB descriptor manufac-

turer and product ID strings.

7.5.3.4

D3h: Dynamic Number of LUNs

Bit

Name

Description

7:0

DYN_NUM_LUN

This byte is used to specify the number of LUNs the device exposes to the

host. These bytes are also used for icon sharing by assigning more than one

LUN to a single icon. This is used in applications where the device utilizes a

combo socket and the OEM wishes to have only a single icon displayed for

one or more interfaces.

If this field is set to FF, the program assumes that you are using the default

value and icons will be configured per the default configuration.

7.5.3.5

D4h-D7h: LUN to Device Mapping

Byte

Name

Description

3:0

LUN_DEV_MAP

These bytes are used to specify the number of LUNs the device exposes to

the host. These bytes are also used for icon sharing by assigning more than

one LUN to a single icon. This is used in applications where the device uti-

lizes a combo socket and the OEM wishes to have only a single icon dis-

played for one or more interfaces.

If this field is set to FF, the program assumes that you are using the default

values and LUNs will be configured per the default configuration.

7.5.3.6

D8h-DAh: Reserved

Byte

Name

Description

2:0

rsvd

7.5.3.7

DBh-DDh: SD/MMC Bus Timing Control

Byte

Name

Description

2:0

SD_MMC_BUS_

TIMING

The values for these bytes are set internally and must not be altered.

7.5.3.8

DEh: Vendor ID (LSB)

Bit

Name

Description

7:0

VID_LSB

Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely

identifies the vendor of the user device (assigned by USB Implementer’s

Forum).

DS60001253F-page 28

 2012-2021 Microchip Technology Inc.

USB82642

7.5.3.9

DFh: Vendor ID (MSB)

Bit

Name

Description

7:0

VID_MSB

Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely

identifies the vendor of the user device (assigned by USB Implementer’s

Forum).

7.5.3.10

E0h: Product ID (LSB)

Bit

Name

Description

7:0

PID_LSB

Least Significant Byte of the Product ID. This is a 16-bit value that the vendor

can assign that uniquely identifies this particular product.

7.5.3.11

E1h: Product ID (MSB)

Bit

Name

Description

7:0

PID_MSB

Most Significant Byte of the Product ID. This is a 16-bit value that the vendor

can assign that uniquely identifies this particular product.

7.5.3.12

E2h: Device ID (LSB)

Bit

Name

Description

7:0

DID_LSB

Least Significant Byte of the Device ID. This is a 16-bit device release num-

ber in BCD (binary coded decimal) format.

7.5.3.13

E3h: Device ID (MSB)

Bit

Name

Description

7:0

DID_MSB

Most Significant Byte of the Device ID. This is a 16-bit device release number

in BCD format.

 2012-2021 Microchip Technology Inc.

DS60001253F-page 29

USB82642

7.5.3.14

E4h: Configuration Data Byte 1 (CFG_DAT_BYT1)

Bit

Name

Description

7

SELF_BUS_PWR