VN2210N3G [MICROCHIP]

N-Channel Enhancement-Mode Vertical DMOS FET;


型号：	VN2210N3G
厂家：	MICROCHIP
描述：	N-Channel Enhancement-Mode Vertical DMOS FET
文件：	总14页 (文件大小：566K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VN2210

N-Channel Enhancement-Mode Vertical DMOS FET

Features

General Description

• Free from Secondary Breakdown

• Low Power Drive Requirement

• Ease of Paralleling

VN2210 is an Enhancement-mode (normally-off)

transistor that utilizes

a vertical Double-diffused

Metal-Oxide Semiconductor (DMOS) structure and a

well-proven silicon gate manufacturing process. This

combination produces a device with the power

handling capabilities of bipolar transistors as well as

the high input impedance and positive temperature

coefficient inherent in MOS devices. Characteristic of

all MOS structures, this device is free from thermal

runaway and thermally induced secondary breakdown.

• Low C_ISSand Fast Switching Speeds

• Excellent Thermal Stability

• Integral Source-drain Diode

• High Input Impedance and High Gain

Applications

Vertical DMOS Field-Effect Transistors (FETs) are

ideally suited to a wide range of switching and

amplifying applications where high breakdown voltage,

high input impedance, low input capacitance and fast

switching speeds are desired.

• Motor Controls

• Converters

• Amplifiers

• Switches

• Power Supply Circuits

• Drivers (Relays, Hammers, Solenoids, Lamps,

Memory, Displays, Bipolar Transistors, etc.)

Package Types

TO-92

TO-39

DRAIN

GATE

SOURCE

DRAIN

GATE

 2016 Microchip Technology Inc.

DS20005559A-page 1

VN2210

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Drain-to-source Voltage ........................................................................................................................................BV_DSS

Drain-to-gate Voltage ............................................................................................................................................BV_DGS

Gate-to-source Voltage ........................................................................................................................................... ±20V

Operating and Storage Temperatures ................................................................................................. –55°C to +150°C

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions above those

indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for

extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: T_A= 25°C unless otherwise specified.

Parameters

Sym.

Min. Typ. Max. Units

Conditions

DC PARAMETERS (Note 1 unless otherwise specified)

Drain-to-source Breakdown Voltage

Gate Threshold Voltage

BV_DSS

V_GS(th)

∆V_GS(th)

I_GSS

100

0.8

—

V_GS= 0V, I_D= 10 mA

V_GS= V_DS, I_D= 10 mA

2.4

Change in V_GS(th)with Temperature

Gate Body Leakage Current

–4.3 –5.5 mV/°C V_GS= V_DS, I_D= 10 mA (Note 2)

—

100

µA

V_GS= ±20V, V_DS= 0V

—

V_GS= 0V, V_DS= Maximum rating

Zero Gate Voltage Drain Current

I_DSS

—

V_DS= 0.8 maximum rating,

—

V_GS= 0V, T_A= 125°C (Note 2)

V_GS= 5V, V_DS= 25V

V_GS= 10V, V_DS= 25V

V_GS= 5V, I_D= 1A

4.5

—

ON-State Drain Current

I_D(ON)

—

0.4

0.5

Static Drain-to-source ON-State Resis-

tance

R_DS(ON)

Ω

0.27 0.35

V_GS= 10V, I_D= 4A

Change in R_DS(ON)with Temperature ∆R_DS(ON)

0.85

1.2

%/°C V_GS= 10V, I_D= 4A (Note 2)

AC PARAMETERS (Note 2)

Forward Transconductance

Input Capacitance

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

1200

—

300

125

—

500

200

mmho V_DS= 25V, I_D= 2A

Common Source Output Capacitance

Reverse Transfer Capacitance

Turn-on Time

—

V_GS= 0V, V_DS= 25V, f = 1 MHz

—

Rise Time

—

V_DD= 25V, I_D= 2A,

R_GEN= 10ꢀ

Turn-off Time

t_d(OFF)

t_f

—

Fall Time

—

DIODE PARAMETERS

Diode Forward Voltage Drop

Reverse Recovery Time

V_SD

t_rr

—

1.6

—

V_GS= 0V, I_SD= 4A (Note 1)

V_GS= 0V, I_SD= 1A (Note 2)

500

Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. 

(Pulse test: 300 µs pulse, 2% duty cycle)

2: Specification is obtained by characterization and is not 100% tested.

DS20005559A-page 2

 2016 Microchip Technology Inc.

VN2210

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise specified, for all specifications T_A=T_J= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

TEMPERATURE RANGES

Operating Temperature

Storage Temperature

PACKAGE THERMAL RESISTANCES

TO-39

T_A

T_S

–55

—

+150

°C

_JA

—

N/A

132

—

TO-92

°C/W

THERMAL CHARACTERISTICS

I_D(Note 1)

(Continuous)

(A)

I_D

Power Dissipation at

T_C= 25°C

I_DR(Note 1)

I_DRM

(A)

Package

(Pulsed)

(A)

(W)

TO-39

TO-92

1.7

1.2

0.36

0.74

1.7

1.2

Note 1: I_D(continuous) is limited by maximum T_j.

 2016 Microchip Technology Inc.

DS20005559A-page 3

VN2210

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g. outside specified power supply range) and therefore outside the warranted range.

1.0

1.1

V_GS= 5.0V

0.8

0.6

0.4

0.2

V_GS= 10V

1.0

0.9

-50

100

150

4.0

8.0

T_j(^OC)

I_D(amperes)

FIGURE 2-1:

Te m pe ra tu re .

Variation with

DSS

FIGURE 2-4:

Current.

1.2

On-resistance vs. Drain

V_DS= 25^OC

R_DS(ON)@ 10V, 4.0A

2.0

1.6

1.2

0.8

0.4

8.0

6.0

4.0

2.0

1.1

1.0

0.9

0.8

T_A= -55^OC

25^OC

150^OC

V_GS(th)@ 10mA

100

0.7

-50

2.0

4.0

6.0

8.0

150

V_GS(volts)

T_j(^OC)

FIGURE 2-2:

Transfer Characteristics.

FIGURE 2-5:

and RV Variation

with Temperature.

500

f = 1.0MHz

V_DS= 10V

8.0

6.0

4.0

2.0

375

250

125

C_ISS

900 pF

V_DS= 40V

C_OSS

300 pF

C_RSS

2.0

4.0

6.0

8.0

V_DS(volt)

Q_G(nanocoulombs)

FIGURE 2-3:

Drain-to-source Voltage.

Capacitance vs.

FIGURE 2-6:

Characteristics.

Gate Drive Dynamic

DS20005559A-page 4

 2016 Microchip Technology Inc.

VN2210

8.0

4.0

8.0

4.0

V_GS= 10V

2.0

4.0

6.0

8.0

V_DS(volts)

FIGURE 2-7:

Output Characteristics.

FIGURE 2-10:

Saturation Characteristics.

4.0

V_DS= 25^OC

8.0

3.2

2.4

1.6

0.8

TO-39

6.0

T_A= 55^OC

25^OC

4.0

150^OC

2.0

TO-92

100

125

150

0.8

1.6

2.4

3.2

4.0

I_D(amperes)

T_C(^OC)

FIGURE 2-8:

Current.

Transconductance vs. Drain

FIGURE 2-11:

Temperature.

1.0

Power Dissipation vs. Case

TO-39 (pulsed)

TO-92 (pulsed)

0.8

0.6

0.4

0.2

TO-39 (DC)

TO-92 (DC)

1.0

0.1

TO-92

P^C_D= 1.0W

= 25^OC

T_C= 25^OC

0.01

0.001

0.01

0.1

1.0

0.1

1.0

100

V_DS(volts)

t_P(seconds)

FIGURE 2-9:

Maximum Rated Safe

FIGURE 2-12:

Thermal Response

Operating Area.

Characteristics.

 2016 Microchip Technology Inc.

DS20005559A-page 5

VN2210

3.0

PIN DESCRIPTION

Table 3-1 shows the description of pins in TO-39 and

TO-92.

TABLE 3-1:

Pin Number

TO-39/TO-92 PIN FUNCTION TABLE

TO-39

TO-92

Description

Source

Gate

Source

Gate

Source

Gate

Drain

DS20005559A-page 6

 2016 Microchip Technology Inc.

VN2210

4.0

FUNCTIONAL DESCRIPTION

Figure 4-1 illustrates the switching waveforms and test

circuit for VN2210.

10V

VDD

90%

INPUT

Pulse

R_L

10%

Generator

OUTPUT

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

R_GEN

t_f

t_r

VDD

OUTPUT

INPUT

D.U.T.

10%

90%

FIGURE 4-1:

Switching Waveforms and Test Circuit.

PRODUCT SUMMARY

R_DS(ON)

(Maximum)

(Ω)

V_GS(th)

(Maximum)

(V)

BV_DSS/BV_DGS

(V)

100

0.35

2.4

 2016 Microchip Technology Inc.

DS20005559A-page 7

VN2210

5.0

5.1

PACKAGING INFORMATION

Package Marking Information

3-Lead TO-39

Example

XXXXXXXXXX

YYWW

VN2210

1611

NNN

789

3-lead TO-92

Example

XXXXXX

VN2210

YWWNNN

613347

Legend: XX...X Product Code or Customer-specific information

Year code (last digit of calendar year)

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Pre-plated

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for product code or customer-specific information. Package may or

not include the corporate logo.

DS20005559A-page 8

 2016 Microchip Technology Inc.

VN2210

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2016 Microchip Technology Inc.

DS20005559A-page 9

VN2210

3-Lead TO-92 Package Outline (L/LL/N3)

ꢎ

ꢒ

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ꢀꢁ ꢂꢃꢄꢅꢆꢇꢈꢉꢂꢅꢁ

ꢏ

ꢑ

ꢐ

ꢁꢊ

ꢁ

ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉ

ꢊꢇꢋ ꢈꢅꢆꢇꢈꢉ

ꢍ

ꢍꢊ

ꢌ

ꢊ

ꢋ

ꢌ ꢂꢄꢄꢂꢍ ꢅꢆꢇꢈꢉ

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

Symbol

.170

.014^†

.175

.125

.080

.095

.045

.500

MIN

NOM

MAX

.014^†

Dimensions

(inches)

.210

.022^†

.205

.165

.105

.055

.610*

JEDEC Registration TO-92.

* This dimension is not speciﬁed in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

DS20005559A-page 10

 2016 Microchip Technology Inc.

VN2210

APPENDIX A: REVISION HISTORY

Revision A (June 2016)

• Converted Supertex Doc# DSFP-VN2210 to

Microchip DS20005559A.

• Made minor text changes throughout the docu-

ment.

DS20005559A-page 11

 2016 Microchip Technology Inc.

VN2210

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Examples:

PART NO.

Device

a) VN2210N2:

N-Channel Enhancement-Mode

Vertical DMOS FET, 3-lead TO-39

Package, 500/Bag

Package

Options

Environmental

Media Type

b) VN2210N3-G:

N-Channel Enhancement-Mode

Vertical DMOS FET, 3-lead TO-92

Package, 1000/Bag

Device:

VN2210

N-Channel Enhancement-Mode Vertical

DMOS FET

Packages:

3-lead TO-39

3-lead TO-92

Environmental:

Media Type:

Lead (Pb)-free/RoHS-compliant Package

(blank)

500/Bag for N2 Package

1000/Bag for N3 Package

Note: VN2210N2 does not include a “-G” designator. However, the package is an

RoHS-compliant product.

 2016 Microchip Technology Inc.

DS20005559A-page 12

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip

Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,

Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

CERTIFIEDꢀBYꢀDNVꢀ

ISBN: 978-1-5224-0686-0

== ISO/TSꢀ16949ꢀ==ꢀ

 2016 Microchip Technology Inc.

DS20005559A-page 13

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07/14/15

DS20005559A-page 14

 2016 Microchip Technology Inc.

VN2210N3G [MICROCHIP]

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