ZL40272LDG1 [MICROCHIP]
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control;型号: | ZL40272LDG1 |
厂家: | MICROCHIP |
描述: | Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control |
文件: | 总54页 (文件大小:2747K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ZL40272
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/
LVPECL Fanout Buffer with Per-Output Enable Control
Features
• 3-to-1 input Multiplexer: Two Inputs Accept Any
Differential (LVPECL, HCSL, LVDS, SSTL, CML,
LVCMOS) or a Single-Ended Signal and the Third
Input Accepts a Crystal or a Single-Ended Signal
Applications
• PCIe Gen1/2/3/4/5 Clock Distribution
• Wired Communications: OTN, SONET/SDH, GE,
10 GE, FC, and 10G FC
• Twelve Differential HCSL/LVDS/LVPECL Outputs
• General Purpose Clock Distribution
• Low Jitter Clock Trees
• Ultra-Low Additive Jitter: 24 fs (Integration Band:
12 kHz to 20 MHz at 625 MHz Clock Frequency)
• Logic Translation
• Supports Clock Frequencies from 0 GHz to
1.5 GHz
• Clock and Data Signal Restoration
• Wireless Communications
• Supports 2.5V or 3.3V Power Supplies on HCSL/
LVDS/LVPECL Outputs
• High Performance Microprocessor Clock Distribu-
tion
• Embedded Low Drop Out (LDO) Voltage Regula-
tor Provides Superior Power Supply Noise Rejec-
tion
• Test Equipment
• Maximum Output to Output Skew of 50 ps
• Device Controlled via I2C or Hardware Control
Pins
• Factory Configurable Default Settings via OTP
• Transparent for Spread Spectrum Clock
SEL
OUT0_p
HW_CTRL/SMBus
IN_SEL0
I2C_SA_0
OUT0_n
IN_SEL0/
I2C_SA_0
IN_SEL1/
I2C_SA_1
Registers:
xtal_buf_gain[7:0]
xtal_drive_level[7:0]
xtal_load_cap[7:0]
xtal_normal_run
input_select[1:0]
output_drive_low[7:0]
output_drive_low[11:8]
vcm_sel
OUT1_p
OUT1_n
IN_SEL1
I2C_SA_0
OUT2_p
OUT2_n
OUT_TYPE_SEL0
I2C_SCL
dev_addr[2:0]
Device ID
OUT_TYPE_SEL0/
I2C_SCL
OUT3_p
OUT3_n
OUT_TYPE_SEL1
I2C_SDA
OUT_TYPE_SEL1
/I2C_SDA
OUT4_p
OUT4_n
OE_b[11:0]
OUT5_p
OUT5_n
IN0_p
IN0_n
OUT6_p
OUT6_n
IN1_p
IN1_n
OUT7_p
OUT7_n
XOUT
OUT8_p
OUT8_n
XIN
ZL40272
OUT9_p
OUT9_n
IREF
OUT10_p
OUT10_n
RH
OUT11_p
OUT11_n
FIGURE 0-1:
Functional Block Diagram.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 1
ZL40272
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DS20006408B-page 2
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE OF CONTENTS
1.0 “Pin Description and Configuration” .................................................................... 6
2.0 “Functional Description”....................................................................................... 11
2.1 “Clock Inputs” ............................................................................................. 11
2.2 “Clock Outputs” .......................................................................................... 13
2.3 “Crystal Oscillator Input” ........................................................................... 13
2.4 “Termination of Unused Inputs and Outputs”.......................................... 14
2.5 “Power Consumption”................................................................................ 14
2.6 “Power Supply Filtering”............................................................................ 15
2.7 “Power Supplies and Power-Up Sequence”............................................. 15
2.8 “Host Interface”........................................................................................... 15
2.9 “I2C Bus Byte Read/Write”......................................................................... 17
2.10 “I2C Bus Burst Read/Write” ..................................................................... 18
2.11 “Typical Phase Noise Characteristics”................................................... 19
3.0 “Register Map”....................................................................................................... 21
4.0 “Electrical Characteristics”................................................................................... 27
5.0 “Package Outline”.................................................................................................. 47
5.1 “Package Marking Information”................................................................. 47
Appendix A: “Data Sheet Revision History” ............................................................. 50
“Product Identification System”................................................................................ 51
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 3
ZL40272
List of Figures
FIGURE 0-1: “Functional Block Diagram.”.............................................................................................................. 1
FIGURE 1-1: “56-Lead 8 mm x 8 mm QFN.” ............................................................................................................ 6
FIGURE 2-1: “Input Driven by a Single-Ended Output for vcm_sel = 0 and 1.”................................................. 11
FIGURE 2-2: “Input Driven by DC-Coupled LVPECL Output for vcm_sel = 0.” ................................................. 11
FIGURE 2-3: “Input Driven by DC-Coupled LVPECL Output for vcm_sel = 0 (Alternative Termination).”...... 12
FIGURE 2-4: “Input Driven by AC-Coupled LVPECL Output for vcm_sel = 0 and 1.”....................................... 12
FIGURE 2-5: “Input Driven by HCSL Output for vcm_sel = 1.” ........................................................................... 12
FIGURE 2-6: “Input Driven by LVDS Output for vcm_sel = 0.” ........................................................................... 12
FIGURE 2-7: “Input Driven by AC-Coupled LVDS for vcm_sel = 0 and 1.” ........................................................ 13
FIGURE 2-8: “Input Driven by an SSTL Output for vcm_sel = 1.”....................................................................... 13
FIGURE 2-9: “Driving a Load via Transformer.”................................................................................................... 13
FIGURE 2-10: “Crystal Oscillator Circuit in Hardware Controlled Mode.”......................................................... 14
FIGURE 2-11: “Power Supply Filtering.” ............................................................................................................... 15
FIGURE 2-12: “Output Disable.”............................................................................................................................. 16
FIGURE 2-13: “Output Enable.”.............................................................................................................................. 16
FIGURE 2-14: “I2C Bus Slave Interface.” .............................................................................................................. 16
FIGURE 2-15: “I2C Bus Byte Read.” ...................................................................................................................... 17
FIGURE 2-16: “I2C Bus Byte Write.”...................................................................................................................... 17
FIGURE 2-17: “I2C Bus Burst Read.”..................................................................................................................... 18
FIGURE 2-18: “I2C Bus Burst Write.” .................................................................................................................... 18
FIGURE 2-19: “100 MHz HCSL Output Phase Noise.”.......................................................................................... 19
FIGURE 2-20: “156.25 MHz LVDS Output Phase Noise.”..................................................................................... 19
FIGURE 2-21: “625 MHz LVPECL Output Phase Noise.” ..................................................................................... 20
FIGURE 2-22: “Phase Noise with 156.25 MHz Crystal.”....................................................................................... 20
FIGURE 4-1: “Single-Ended Measurement Points for Absolute Cross Point and Swing.”............................... 39
FIGURE 4-2: “Single-Ended Measurement Points for Delta Cross Point.” ........................................................ 39
FIGURE 4-3: “Single-Ended Measurement Points for Rise and Fall Time Matching.”...................................... 39
FIGURE 4-4: “Differential Measurement Points for Rise and Fall Time.”........................................................... 39
FIGURE 4-5: “Differential Measurement Points for Ringback.” .......................................................................... 40
FIGURE 4-6: “PCIe Test Circuit.” ........................................................................................................................... 40
FIGURE 4-7: “I2C Bus Timing.”.............................................................................................................................. 45
DS20006408B-page 4
2020 - 2021 Microchip Technology Inc. and its subsidiaries
List of Tables
TABLE 1-1: “Pin Descriptions”.................................................................................................................................7
TABLE 2-1: “Input Clock Selection”.......................................................................................................................15
TABLE 2-2: “Output Type Selection” .....................................................................................................................15
TABLE 2-3: “I2C Bus Address Table” ....................................................................................................................17
TABLE 3-1: “Register Map”.....................................................................................................................................21
TABLE 3-2: “0x00 XTALBG - XTAL Buffer Gain” ..................................................................................................21
TABLE 3-3: “0x01 XTALDL - XTAL Drive Level” ...................................................................................................22
TABLE 3-4: “0x02 XTALLC - XTAL Load Capacitance”........................................................................................22
TABLE 3-5: “0x03 XTALNR - XTAL Normal Run”..................................................................................................23
TABLE 3-6: “0x04 OUTLOWALL - Output Low All”...............................................................................................23
TABLE 3-7: “0x05 INSEL - Input Select Register”.................................................................................................23
TABLE 3-8: “0x07 DRVTYPE0 - Output Type Select (Outputs 0 to 3)”................................................................24
TABLE 3-9: “0x08 DRVTYPE1 - Output Type Select (Outputs 4 to 7)”................................................................24
TABLE 3-10: “0x09 DRVTYPE2 - Output Type Select (outputs 8 to 11)” ............................................................24
TABLE 3-11: “0x0A OUTLOW0 - Output Drive Low (Outputs 0 to 7)”.................................................................25
TABLE 3-12: “0x0B OUTLOW1 - Output Drive Low (Outputs 8 to 11)”...............................................................25
TABLE 3-13: “0x0C COMMODSEL - Common Mode Select” ...............................................................................26
TABLE 3-14: “0x0E DEVADDR - I2C Bus Slave Device Address” .......................................................................26
TABLE 3-15: “0x11 DEVID - Device Identification” ...............................................................................................26
TABLE 4-1: “Absolute Maximum Ratings” ............................................................................................................27
TABLE 4-2: “Recommended Operating Conditions”............................................................................................27
TABLE 4-3: “Current Consumption” ......................................................................................................................27
TABLE 4-4: “Input Characteristics”........................................................................................................................28
TABLE 4-5: “Crystal Oscillator Characteristics”...................................................................................................29
TABLE 4-6: “Power Supply Rejection Ratio for VDD = VDDO = 3.3V”................................................................29
TABLE 4-7: “Power Supply Rejection Ratio for VDD = VDDO = 2.5V”................................................................30
TABLE 4-8: “LVPECL Output Characteristics for VDDO = 3.3V”.........................................................................30
TABLE 4-9: “LVPECL Output Characteristics for VDDO = 2.5V”.........................................................................31
TABLE 4-10: “LVDS Outputs for VDDO = 3.3V” ....................................................................................................32
TABLE 4-11: “LVDS Outputs for VDDO = 2.5V” ....................................................................................................33
TABLE 4-12: “HCSL Outputs (PCIe electrical characteristics) for vddo = 3.3v”................................................34
TABLE 4-13: “HCSL (PCIe) jitter performance for vddo = 3.3v” ..........................................................................35
TABLE 4-14: “HCSL Outputs (PCIe electrical characteristics) for vddo = 2.5v”................................................36
TABLE 4-15: “HCSL (PCIe) jitter performance for vddo = 2.5v” ..........................................................................38
TABLE 4-16: “LVPECL Output Phase Noise with 25 MHz XTAL”........................................................................40
TABLE 4-17: “LVDS Output Phase Noise with 25 MHz XTAL”.............................................................................41
TABLE 4-18: “HCSL Output Phase Noise with 25 MHz XTAL” ............................................................................41
TABLE 4-19: “LVPECL Output Phase Noise with 125 MHz XTAL”......................................................................42
TABLE 4-20: “LVDS Output Phase Noise with 125 MHz XTAL”...........................................................................42
TABLE 4-21: “HCSL Output Phase Noise with 125 MHz XTAL” ..........................................................................43
TABLE 4-22: “LVPECL Output Phase Noise with 156.25 MHz XTAL”.................................................................43
TABLE 4-23: “LVDS Output Phase Noise with 156.25 MHz XTAL”......................................................................44
TABLE 4-24: “HCSL Output Phase Noise with 156.25 MHz XTAL” .....................................................................44
TABLE 4-25: “I2C Bus Electrical Characteristics”................................................................................................45
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 5
ZL40272
1.0
PIN DESCRIPTION AND CONFIGURATION
Pin#1
Corner
56
55
54
53
52
51
50
49
48
47
46
45
44
43
OUT0_p
OUT0_n
VDDO
1
2
42
41
OUT11_n
OUT11_p
VDDO
3
4
40
39
38
37
36
35
34
33
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
OUT4_p
OUT4_n
VDDO
OUT10_n
OUT10_p
OUT9_n
OUT9_p
OUT8_n
OUT8_p
OUT7_n
5
6
7
Exposed Ground Pad
8
9
10
11
12
13
14
32 OUT7_p
31
VDDO
OUT5_p
OUT5_n
30
OUT6_n
29
OUT6_p
15
16
17
18
19
20
21
23
24
25
26
27
28
22
FIGURE 1-1:
56-Lead 8 mm x 8 mm QFN.
DS20006408B-page 6
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
All device inputs and outputs are LVPECL, unless described otherwise. The I/O column uses the following symbols:
I – input, IPU – input with 300 kΩ internal pull-up resistor, IPD – input with 300 kΩ internal pull-down resistor,
IAPU – input with 31 kΩ internal pull-up resistor, IAPD – input with 30 kΩ internal pull-down resistor, IAPU/APD – input
biased to VDD/2 with 60 kΩ internal pull-up and pull-down resistors (30 kΩ equivalent), O – output, I/OOD – Input/Open-
Drain Output pin, NC – No connect, P – power supply pin.
TABLE 1-1:
PIN DESCRIPTIONS
Pin
Number
Pin Name
Type
Description
Input References
20
21
25
IN0_p
IAPD
IAPU/APD
IAPD
Differential/Single-Ended References 0 and 1
IN0_n
IN1_p
Input frequency range from 0 Hz to 1.5 GHz.
Non-inverting inputs (_p) are pulled down with internal 30 kΩ pull-down
resistors.
Inverting inputs (_n) are pulled up and pulled down with 60 kΩ internal
resistors (30 kΩ equivalent) to keep inverting input voltages at VDD/2
when inverting inputs are left floating (device fed with a single-ended ref-
erence).
24
IN1_n
IAPU/APD
Output Clocks
1
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
OUT4_p
OUT4_n
OUT5_p
OUT5_n
OUT6_p
OUT6_n
OUT7_p
OUT7_n
OUT8_p
OUT8_n
OUT9_p
OUT9_n
OUT10_p
OUT10_n
OUT11_p
OUT11_n
2
4
5
6
7
8
9
Ultra-Low Additive Jitter Differential LVPECL/HCSL/LVDS Outputs 0
to 11
10
11
13
14
29
30
32
33
34
35
36
37
38
39
41
42
Output frequency range 0 Hz to 1.5 GHz
In I2C bus controlled mode (SEL pin pulled high on the power up) type
(LVPECL/HCSL/LVDS/High-Z) of each output is programmable via I2C
Bus
O
In Hardware control mode (SEL pin pulled low on the power up) type
(LVPECL/HCSL/LVDS/High-Z) of each output is controlled via
OUT_TYPE_SEL0/1 pins.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 7
ZL40272
TABLE 1-1:
PIN DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Name
Type
Description
Control
Input Select 0 or I2C Address. When SEL pin is low, this pin is Input
Select 0 hardware control input. When SEL pin is high, this pin together
with pin 51 provides address for I2C Bus. This pin is pulled-down with
300 kΩ resistor.
IN_SEL1
IN_SEL0
OUTN
IN_SEL0/
I2C_SA_0
52
IPD
0
0
0
1
Input 0 (IN0)
Input 1 (IN1)
Crystal Oscillator or
Overdrive
1
0
1
1
Crystal Bypass
Input Select 1 or Serial Interface Input. When SEL pin is low, this pin
is Input Select 1 hardware control pin. When SEL pin is high, this pin
together with pin 45 provides address for I2C Bus.
This pin is pulled down with 300 kΩ resistor.
Output Signal Type or I2C Bus Clock.
IN_SEL1/
I2C_SA_1
51
50
49
IPD
When SEL pin is low, this pin and pin 49 selects output type.
When SEL pin is high, this pin is I2C Bus Clock.
OUT_TYPE_-
SEL0
/I2C_SCL
OUT_TYPE_SEL_1
OUT_TYPE_SEL_0
Output [11:0]
HCSL
I/O
0
0
1
1
0
1
0
1
LVDS
LVPECL
High-Z (disabled)
Output Signal Type or I2C Bus I/O Data
When SEL pin is low, this pin and pin 50 selects output type.
When SEL pin is high, this pin is an I/O pin (Input/Open-Drain) for I2C
Bus.
OUT_TYPE_-
SEL1
/I2C_SDA
I
I/OOD
56
55
54
17
16
15
27
26
19
45
44
43
OE0_b
OE1_b
OE2_b
OE3_b
OE4_b
OE5_b
OE6_b
OE7_b
OE8_b
OE9_b
OE10_b
OE11_b
Output Enable Control.
When OEn_b is low, the output n where n = {0,..,11} is active.
When OEn_b is high, the output is disabled (High-Z)
OEn_b pins are pulled-down with 300 kΩ resistor
IPD
Crystal Oscillator
Crystal Oscillator Input or Crystal Bypass Mode or Crystal Over-
drive Mode:
If crystal circuit is not used, pull-down this pin or connect it to the ground.
22
23
XIN
XOUT
I
O
Crystal Oscillator Output
DS20006408B-page 8
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 1-1:
PIN DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Name
Type
Description
Hardware/I2C Bus Control selection
Select Control.
When this pin is low, the device is controlled via hardware pins, IN_-
SEL0/1 and OE.
48
28
SEL
I
I
When this pin is high, the device is controlled via I2C Bus port.
Any change of SEL pin value requires power cycle. Hence, SEL pin can-
not be changed on the fly.
Output Current Select.
Connect this pin to the ground via resistor R:
HCSL/LVDS/LVPECL for 100Ω differential transmission line:
R = 536Ω
IREF
HCSL for 85 Ω differential transmission line:
R = 422Ω
Power and Ground
18
46
53
3
VDD
P
P
Positive Supply Voltage. Connect to 3.3V or 2.5V supply.
Positive Supply Voltage for Differential Outputs. Connect to 3.3V or
2.5V power supply. These pins power up differential outputs
OUT[11:0]_p/n.
12
31
40
VDDO
Positive Supply Voltage for Programming OTP Memory. This pin is
used for generating custom configurations on ATE. Connect to ground
for normal operation.
47
VPP
P
P
ePad
GND
Ground. Connect to the ground.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 9
ZL40272
NOTES:
DS20006408B-page 10
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
2.0
FUNCTIONAL DESCRIPTION
The ZL40272 is an I2C Bus programmable or hardware pin controlled low additive jitter, low power 3 x 12 HCSL/LVDS/
LVPECL fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML) or single-ended (LVPECL or LVCMOS)
format; the third input can accept a single-ended signal or it can be used to build a crystal oscillator by connecting an
external crystal resonator between its XIN and XOUT pins. All the other components for building a crystal oscillator are
built into the device, such as load capacitance, series resistors, and shunt resistors.
The ZL40272 has twelve HCSL/LVDS/LVPECL outputs that can be powered from a 3.3V or 2.5V supply. Each output
can be independently enabled/disabled via OEn_b pins or via I2C Bus. The type of each output driver can be pro-
grammed to be LVPECL, HCSL or LVDS. Hence, the device can be configured to support different signaling formats
depending on the application.
The device operates from 2.5V ±5% or 3.3V ±5% supply. Its operation is guaranteed over the industrial temperature
range of –40°C to +85°C.
2.1
Clock Inputs
The following block diagrams show how to terminate different signals fed to the ZL40272 inputs.
The device has programmable common mode input voltage. The common mode voltage can be programmed in COM-
MODSEL register at address 0x0C:
COMMODSEL.vcm_sel = 1 (default) for inputs with common mode between 0V and 1V, such as HCSL.
COMMODSEL.vcm_sel = 0 for inputs with common mode voltage between 1V and 2V, such as LVPECL and LVDS.
For devices intended to be used in hardware pin controlled mode, the default common mode voltage can be changed
in factory by programming OTP.
Figure 2-1 shows how to terminate a single-ended output such as LVCMOS. Resistors R1 and R2 should present 50Ω
equivalent resistance to the line and RO + RS should be 50Ω so that the transmission line is terminated at both ends
with characteristic impedance. If the driving strength of the output driver is not sufficient to drive low impedance (stan-
dard LVCMOS output, for example), the value of series resistor RS should be increased. This will reduce the voltage
swing at the input, but this should be fine as long as the input voltage swing requirement is not violated (Table 9). The
source resistors of RS = 330Ω could be used for a standard LVCMOS driver. This will provide 471 mV of voltage swing
for 3.3V LVCMOS driver with the peak load current of (3.3V* 0.85) *(1/(330Ω + 50Ω)) = 7.3 mA for common mode volt-
age biased at 0.5V. For common mode voltage of VDD/2, the peak current will be lower.
For optimum performance both differential input pins (_p and _n) need to be DC biased to the same voltage. Hence, the
ratio R1/R2 should be equal to the ratio R3/R4.
VDD
VDD
VDD
VDD
OpƟonal AC coupling
R3
R1
R2
capacitor
0.1 μF
Rs
Ro
Z0 = 50 ё
R1/R2 =R2/R4
MSCC Device
0.1 μF
R4
Example for vcm_sel = 1 (vcm =0.75V):
R1 = 59ё, R2 = 330ё
Example for vcm_sel = 0 (vcm = Vdd/2):
R1 = R2 = 100ё
R3 = R4 = 1kё
R3 = 590ё, R4 = 3.3kё
Rs = 330ё for standard LVCMOS output
FIGURE 2-1:
Input Driven by a Single-Ended Output for vcm_sel = 0 and 1.
VDD
VDD
VDD
RUP
RUP
VDD
Z0 = 50 ё
Z0 = 50 ё
LVPECL
RDWN
RDWN
MSCC Device
VDD
3.3V
RUP
RDWN
127 ё
82 ё
2.5V 250 ё
62.5 ё
FIGURE 2-2:
Input Driven by DC-Coupled LVPECL Output for vcm_sel = 0.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 11
ZL40272
VDD
VDD
Z0 = 50 ё
Z0 = 50 ё
LVPECL
LVPECL
50ё
50ё
MSCC Device
VDD
3.3V
2.5V
RDWN
50 ё
22 ё
RDWN
FIGURE 2-3:
Input Driven by DC-Coupled LVPECL Output for vcm_sel = 0 (Alternative
Termination).
VDD
VDD
VDD
VDD
RUP
RUP
10 nF
10 nF
Z0 = 50 ё
Z0 = 50 ё
LVPECL
200 ё
200 ё
RDWN
MSCC Device
RDWN
vcm_sel
0
1
RUP
100 ё
330 ё
RDWN
100 ё
59 ё
FIGURE 2-4:
Input Driven by AC-Coupled LVPECL Output for vcm_sel = 0 and 1.
VDD
VDD
50 ё
Z0 = 50 ё
HCSL
50 ё
Z0 = 50 ё
50 ё
50 ё
MSCC Device
FIGURE 2-5:
Input Driven by HCSL Output for vcm_sel = 1.
VDD
VDD
Z0 = 50 ё
100ё
LVDS
Z0 = 50 ё
MSCC Device
FIGURE 2-6:
Input Driven by LVDS Output for vcm_sel = 0.
DS20006408B-page 12
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
VDD
VDD
VDD
RUP
RUP
VDD
10 nF
10 nF
Z0 = 50 ё
Z0 = 50 ё
100 ё
LVDS
MSCC Device
RDWN
RDWN
vcm_sel
0
1
RUP
RDWN
1 kё
590 ё
1 kё
3.3 kё
FIGURE 2-7:
Input Driven by AC-Coupled LVDS for vcm_sel = 0 and 1.
VDD
VDD
VDD
120ё
120ё
VDD
Z0 = 60 ё
Z0 = 60 ё
SSTL
120ё
120ё
MSCC Device
FIGURE 2-8:
Input Driven by an SSTL Output for vcm_sel = 1.
2.2
Clock Outputs
Differential outputs LVPECL, LVDS, and HCSL should have same termination as corresponding outputs described in
previous section.
The device is designed to drive differential input of semiconductor devices. In applications that use a transformer to con-
vert from the differential to the single-ended output (for example, driving an oscilloscope 50Ω input), a resistor larger
than 10Ω should be added at the center tap of the primary winding to achieve optimum jitter performance as shown in
Figure 2-9. This is to provide a nominal common mode impedance of 10Ω or higher, which is typical for differential ter-
minations.
Add resistor to the ground or leave open
VDD
2 : 1
Z0 = 50 ё
10 nF
Z0 = 50 ё
Z0 = 50 ё
24.9 ё
LVPECL
10 nF
50 ё
200 ё
200 ё
FIGURE 2-9:
Driving a Load via Transformer.
2.3
Crystal Oscillator Input
The crystal oscillator circuit can work with crystal resonators from 8 MHz to 160 MHz. To be able support crystal reso-
nators with different characteristics, all internal components are programmable.
The load capacitors can be programmed from 0 pF to 21.75 pF (4 pF default) with resolution of 0.25 pF, which not only
meets load requirement for most crystal resonator but also allows for fine tuning of the crystal resonator frequency. The
amplifier gain can be adjusted in five steps and series resistor can be adjusted as parallel combination of seven different
resistors: 0Ω, 10.5Ω, 21Ω, 42Ω, 84Ω, 161Ω, and 312Ω. (84Ω default) Although the first resistor is 0Ω, the series resis-
tance RS will be slightly higher than 0Ω due to parasitic resistance of the switch that connects to the resistor. Hence, the
minimum series resistance is achieved when all seven resistors are connected in parallel. The shunt resistor is fixed
and its value is 500 kΩ.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 13
ZL40272
In Hardware Controlled mode, the capacitive load is set at 4 pF, internal series resistance to 84Ω and they cannot be
changed. For Crystals that require higher load or series resistance, additional capacitance and/or series resistance can
be added externally as shown in the Figure 2-10.
C1
XIN
Crystal
Rs
XOUT
C2
Load capacitors C1 and C2
should be as per crystal
speciĮcaƟon
MSCC Device
FIGURE 2-10:
Crystal Oscillator Circuit in Hardware Controlled Mode.
2.4
Termination of Unused Inputs and Outputs
Unused inputs can be left unconnected or alternatively IN_0/1 can be pulled-down by a 1 kΩ resistor. Unused outputs
should be left unconnected.
2.5
Power Consumption
The device total power consumption can be calculated as:
EQUATION 2-1:
PT = PS + PXTAL + PC + PO_DIFF
Where:
PS = VDD x IS: is the core power consumed by input buffers. If XTAL is running this power, it should be set to zero.
The static current (IS) is specified in Table 4-2.
PXTAL = VDD x IDD_XTAL: is the core power consumption of the XTAL circuit. The current of the XTAL circuit is provided
in Table 4-2. If XTAL is not used, the power consumption is equal to zero.
PC = VDDO x IDD_CM: Common output power shared among all twelve outputs. The current IDD_CM is specified in
Table 4-2.
PO_DIFF = VDDO x (IDD_LVDS x N1 + IDD_LVPECL x N2 + IDD_HCSL x N3): Output power where the output current are
specified in Table 4-2. N1, N2, and N3 are the
number of enabled LVPECL, LVDS, and HCSL
outputs respectively and N1 + N2 + N3 is less
than or equal to 12.
Power dissipated inside the device can be calculated by subtracting power dissipated in termination/biasing resistors
from the power consumption.
EQUATION 2-2:
PD = PT – N1 PLVPECL – N2 PLVDS – N3 PHCSL
Where:
N1, N2, N3 = The number of enabled LVPECL, LVDS and HSCL outputs respectively. Because there are twelve
differential outputs N1 + N2 + N3 will be less or equal to 12.
PLVPECL = (VSW / 50Ω) x (VSW + VB): VSW is the voltage swing of the LVPECL output. VB is the LVPECL bias voltage
equal to VDD – 2V.
P
P
LVDS = VSW / 100Ω: VSW is the voltage swing of the LVDS output.
HCSL = (VSW / 50Ω)2 x (50Ω + 50Ω): VSW is the voltage swing of the HCSL output. 50Ω is the termination resistance
and 50Ω is the series resistance of the HCSL output.
DS20006408B-page 14
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ZL40272
2.6
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with a 0.1 µF capacitor with minimum equivalent series resis-
tance (ESR) and minimum series inductance (ESL). For example, 0402 X5R Ceramic Capacitors with 6.3V minimum
rating could be used. These capacitors should be placed as close as possible to the power pins. To reduce the power
noise from adjacent digital components on the board, each power supply could be further insulated with a low resistance
ferrite bead with two capacitors. The ferrite bead will also insulate adjacent components from the noise generated from
the device. Figure 2-11 shows recommended decoupling for each power pin.
Board Supply
10uF
Ferrite Bead
1uF
VDD or VDDO
0.1uF
FIGURE 2-11:
Power Supply Filtering.
2.7
Power Supplies and Power-Up Sequence
The device has two different power supplies: VDD and VDDO, which are mutually independent. Voltages supported by
each of these power supplies are specified in Table 1-1.
The device is not sensitive to the power-up sequence. For example, a commonly used sequence where higher voltage
comes up before or at the same time as the lower voltages can be used (or any other sequence).
2.8
Host Interface
ZL40272 can be controlled via hardware pins (SEL pin tied low) or via I2C Bus (SEL pin tied high). The mode shall be
selected during power up and it cannot be changed on-the-fly.
2.8.1
HARDWARE CONTROL MODE
In this mode, ZL40272 is controlled via Input Select pins (IN_SEL[1:0]) that select which one of three inputs is fed to
outputs as show in Table 2-1, OUT_TYPE_SEL[1:0] pins which select signal level (HCSL, LVDS, LVPECL or Hi-Z) and
output enable pins (OE_b) for each output as shown in Table 2-2.
All input control pins have low input threshold voltage so they can be driven from the device with low output voltage
(FPGA/CPLD). Supported voltages are between 1.2V and VDD (2.5V or 3.3V).
TABLE 2-1:
INPUT CLOCK SELECTION
IN_SEL1
IN_SEL0
Selected Input
0
0
1
0
1
X
IN0_p, IN0_n
IN1_p, IN1_n
XIN (crystal input pin)
TABLE 2-2:
OUTPUT TYPE SELECTION
OE_N_b
OUT_TYPE_SEL[1:0]
Output
0
0
0
1
X
00
HCSL
LVDS
01
10
00 or 01 or 10
11
LVPECL
High-Z (on output N)
High-Z (on all outputs)
Output is disabled synchronously and depending of the input frequency it can take up to 5 clock cycles to disable the
output (t2 – t1 ≤ 5*T, where T is the input clock period) as shown in Figure 2-12.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
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ZL40272
INn_n
INn_p
INn_p - INn_n
OE_N_b
It takes up to 5
cycles to disable
the output
OUTN_n
OUTN_p
t1
t2
FIGURE 2-12:
Output Disable.
Any outputs can be enabled by pulling the corresponding OE_b pin low. As soon as OE_N_b pin goes low (t1) the output
N will go from high-Z to low (OUTN_p = low, OUTN_n = high) and will start to track the input after up to 5 input clock
cycles (t2 – t1 ≤ 5*T, where T is the input clock period) depending on the frequency of the input clock as shown in
Figure 2-13.
INn_n
INn_p
INn_p - INn_n
OE_N_b
OUTN_n
OUTN_p
t1
t2
FIGURE 2-13:
Output Enable.
2.8.2
I2C BUS CONTROL MODE
ZL40272 is controlled via four pin I2C Bus slave interface as shown in the following figure.
SCL
SDA
MSCC Device
SA_0
SA_1
FIGURE 2-14:
I2C Bus Slave Interface.
The address selection is done via SA_0 and SA_1 hardware pins, which select the appropriate address for the device.
DS20006408B-page 16
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ZL40272
TABLE 2-3:
I2C BUS ADDRESS TABLE
SA_1
SA_0
I2C Bus Address
0
0
1
1
0
1
0
1
0x34
0x35
0x36
0x37
2.9
I2C Bus Byte Read/Write
Reading or writing a register or registers in a I2C Bus slave device is MSB first and LSB last in one-byte blocks.
The access from I2C master starts with the start condition followed by the slave address and the write indicator bit. This
is then followed by the command byte which in bits [6:0] contains the address of the register to be accessed for byte
mode or the first register to be accessed in the burst mode. The most significant bit in the command byte must be set
to 1.
Byte Read. The standard byte read is as shown in Figure 2-15. The command byte is followed the slave address and
read indication bit. The device (slave) will respond by sending the requested byte.
Byte
Byte
Byte
Byte
Data Byte 0
Rd/Wr Command
T
Slave
Wr
A
Command
A
r
Slave
Rd
A
N
P
Notack
Stop
CondiƟon
Rd/Wr Command
Repeat start
Acknowledge
Register address to read
MSB = 1
{1'b1,register_address[6:0]}
Start
CondiƟon
Master
drives Bus
Slave
drives Bus
FIGURE 2-15:
I2C Bus Byte Read.
Write. Figure 2-16 illustrates the standard byte write After the written byte has been acknowledged by the device, the
master will assert the stop signal.
Byte
Byte
Byte
T
Slave
Wr A Command
A
Data Byte 0
Acknowledge
A
P
Rd/Wr Command
Register address to write
MSB = 1
{1'b1,register_address[6:0]}
Start
CondiƟon
Stop
Master
drives Bus
Slave
drives Bus
FIGURE 2-16:
I2C Bus Byte Write.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 17
ZL40272
2.10 I2C Bus Burst Read/Write
Burst Read and Write are very similar to Byte Read and Write.
Burst Read. Figure 2-17 illustrates the Burst Read. The I2C master acknowledges after each received byte and finally
sends a Not Acknowledge (NACK) followed with Stop Condition.
Byte
Byte
Byte
Command
T
Slave
Wr
A
A
r
Slave
Rd
A
Repeat start
Acknowledge
Rd/Wr Command
Rd/Wr Command
Register address to read
MSB = 1
{1'b1,register_address[6:0]}
Start
CondiƟon
Byte
Byte
Byte
Data Byte 0
A
Data Byte 1
A
Data Byte 2
N
P
Notack
Stop
Master
drives Bus
CondiƟon
Slave
drives Bus
FIGURE 2-17:
I2C Bus Burst Read.
Burst Write. Figure 2-18 illustrates the Burst Write. The I2C master will send the Stop Condition after the last data byte.
Byte
Byte
T
Slave
Wr A Command
A
Master
drives Bus
Slave
drives Bus
Rd/Wr Command
Acknowledge
Register address to write
MSB = 1
{1'b1,register_address[6:0]}
Start
CondiƟon
Byte
Byte
Byte
Data Byte 0
A
Data Byte 1
A
Data Byte 2
A
P
Acknowledge
Stop
FIGURE 2-18:
I2C Bus Burst Write.
DS20006408B-page 18
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ZL40272
2.11 Typical Phase Noise Characteristics
FIGURE 2-19:
100 MHz HCSL Output Phase Noise.
FIGURE 2-20:
156.25 MHz LVDS Output Phase Noise.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 19
ZL40272
FIGURE 2-21:
625 MHz LVPECL Output Phase Noise.
FIGURE 2-22:
Phase Noise with 156.25 MHz Crystal.
DS20006408B-page 20
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ZL40272
3.0
REGISTER MAP
The device is controlled by accessing registers through the serial interface. The following table provides a summary of
the registers available for the configuration of the device. The default settings can be modified via factory programmable
OTP memory.
TABLE 3-1:
REGISTER MAP
Name
Address
I2C A[6:0]
Hex (0x)
Data D[7:0]
00
01
XTALBG
XTALDL
xtal_buf_gain[7:0]
xtal_drive_level[7:0]
xtal_load_cap[7:0]
xtal_normal_run
out_low_all
02
XTALLC
03
XTALNR
04
OUTLOWALL
INSEL
05
input_select[1:0]
Not used.
06
—
07
DRVTYPE0
DRVTYPE1
DRVTYPE2
OUTLOW0
OUTLOW1
COMMODSEL
—
driver_type[7:0] (differential output OUT3, OUT2, OUT1, OUT0)
08
driver_type[15:8] (differential output OUT7, OUT6, OUT5, OUT4)
09
driver_type[23:16] (differential output OUT11, OUT10, OUT9, OUT8)
0A
0B
0C
0D
0E
0F
10
output_drive_low[7:0]
output_drive_low[11:8]
vcm_sel
Not used.
DEVADDR
Reserved
Reserved
DEVICEID
Reserved
dev_addr[2:0]
Reserved
Reserved
11
Device Identification
Reserved
12-1F
TABLE 3-2:
Bit
0X00 XTALBG - XTAL BUFFER GAIN
Name
Description
Type
Reset
Programs crystal buffer (inverting amplifier) gain.
Every bit pair (bits: 01, 23, 45, 67) of this register corre-
spond to additional equal gain block which can be added
(bits set) or removed (bits cleared).
Minimum gain is 0x00 (default) and 0xFF is maximum
gain
When reference input mode is “bypass XTAL mode” or
“differential input modes” with HIGH xtal_normal_run bit,
the buffer is disabled and follows “Input Selection”.
When xtal_normal_run bit is LOW, XTAL buffer is in the
“xtal forced run” mode and keep running.
7:0
xtal_buf_gain[7:0]
RW
FF
8’b0000_0000: default crystal buffer strength.
8’b0000_0011: enable additional buffer strength
8’b0000_1100: enable additional buffer strength
8’b0011_0000: enable additional buffer strength
8’b1100_0000: enable additional buffer strength
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ZL40272
TABLE 3-3:
Bit
0X01 XTALDL - XTAL DRIVE LEVEL
Name
Description
Type
Reset
Internal damping resistance of crystal circuit to limit
external crystal’s drive level µW.
The value of damping resistor is determined by crystal’s
motion resistance of crystal’s equivalent circuit.
Drive level should be lower than crystal manufacturer’s
specification.
Crystal’s equivalent values should be requested to the
manufacturer, (motion resistance and shunt capaci-
tance).
The selected resistors are connected to XOUT.
Multiple bit combinations available by 7-bit control.
Because they use parallel connections, 0xFF is the
smallest resistance and 0x01 is the highest resistance.
7:0
xtal_drive_level[7:0]
RW
04
8’b0000_0000: disable all resistors
8’b0000_0001: 312Ω resistor
8’b0000_0010: 161Ω resistor
8’b0000_0100: 84Ω resistor
8’b0000_1000: 42Ω resistor
8’b0001_0000: 21Ω resistor
8’b0010_0000: 10.5Ω resistor
8’b0100_0000: 0Ω connection
8’b1000_0000: not used
TABLE 3-4:
Bit
0X02 XTALLC - XTAL LOAD CAPACITANCE
Name
Description
Type
Reset
Internal load capacitance of crystal circuit (0 pF to
21.75 pF with the resolution of 0.25 pF).
XIN and XOUT have each capacitor connected to GND.
Multiple bit combinations available between 8 capaci-
tors.
8’b0000_0000: disable all xtal load capacitors
8’b0000_0001: enable capacitor 0.25 pF
8’b0000_0010: enable capacitor 0.5 pF
8’b0000_0100: enable capacitor 1 pF
8’b0000_1000: enable capacitor 2 pF
8’b0001_0000: enable capacitor 2 pF
8’b0010_0000: enable capacitor 4 pF
8’b0100_0000: enable capacitor 4 pF
8’b1000_0000: enable capacitor 8 pF
7:0
xtal_load_cap[7:0]
RW
40
DS20006408B-page 22
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ZL40272
TABLE 3-5:
Bit
0X03 XTALNR - XTAL NORMAL RUN
Name
Description
Type
Reset
7:1
Unused
Unused
R
0000000
When this bit is set high crystal oscillator circuit is run-
ning only if input_select[1:0] register at address 0x05
selects crystal mode (2’b10). This value is recom-
mended because it provides best jitter performance--XO
circuit is running only when it is needed.
0
xtal_normal_run
RW
1
When this bit is set low the crystal oscillator will keep
running even if crystal oscillator is not selected in
input_select[1:0] register at address 0x05. This mode
should only be used when fast switching between input
references and crystal oscillator is required.
TABLE 3-6:
Bit
0X04 OUTLOWALL - OUTPUT LOW ALL
Name
Description
Type
Reset
7:1
Unused
Unused
R
0000000
OUTLOWALL affects OUTLOW0 and OUTLOW1 regis-
ters.
1’b0: Output0 to Output11 are according to their driver_-
type[n+1, n] values
1’b1: Output0 to Output11 will drive logic LOW.
OTP value load to this bit and/or I2C write to this bit in
the SCM mode, will affect all the values at OUTLOW0
and OUTLOW1 registers. In other words, loading value
of 1’b0 from OTP or writing it from I2C, will cause all val-
ues in OUTLOW0 and OUTLOW1 registers to be 0’s.
Same thing for 1’b1.
0
out_low_all
RW
0
In SCM, the output_low values per output are controlled
individually by accessing the bits in OUTLOW0 and
OUTLOW1 registers. However, any subsequent write to
this bit will affect the values in those registers (OUT-
LOW0 and OUTLOW1)
TABLE 3-7:
Bit
0X05 INSEL - INPUT SELECT REGISTER
Name
Description
Type
Reset
7:2
Unused
Unused
R
000000
Input reference clock selection.
Proper external coupling and termination are required.
2’b00: differential input from IN0_p and IN0_n
2’b01: differential input from IN1_p and IN1_n
2’b10: fundamental XTAL mode with XIN and XOUT
(Use internal crystal oscillator circuits) or XTAL overdrive
mode (single-ended clock signal fed to XIN)
2’b11: XTAL bypass mode (single-ended clock signal
with XIN and disabled internal crystal buffer circuit in the
analog block)
1:0
input_select[1:0]
00
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DS20006408B-page 23
ZL40272
TABLE 3-8:
Bit
0X07 DRVTYPE0 - OUTPUT TYPE SELECT (OUTPUTS 0 TO 3)
Name
Description
Type
Reset
Output driver type of differential OUT3.
7:6
5:4
3:2
driver_type[7:6]
driver_type[5:4]
driver_type[3:2]
RW
11
The same bit configuration with OUT0.
Output driver type of differential OUT2.
RW
RW
11
11
The same bit configuration with OUT0.
Output driver type of differential OUT1.
The same bit configuration with OUT0.
Output driver type of differential OUT0.
2’b00: HCSL outputs
2’b01: LVDS outputs
2’b10: LVPECL outputs
2’b11: Outputs disabled
1:0
driver_type[1:0]
RW
11
TABLE 3-9:
Bit
0X08 DRVTYPE1 - OUTPUT TYPE SELECT (OUTPUTS 4 TO 7)
Name
Description
Type
Reset
Output driver type of differential OUT7.
7:6
5:4
3:2
1:0
driver_type[15:14]
driver_type[13:12]
driver_type[11:10]
driver_type[9:8]
RW
11
The same bit configuration with OUT0.
Output driver type of differential OUT6.
RW
RW
RW
11
11
11
The same bit configuration with OUT0.
Output driver type of differential OUT5.
The same bit configuration with OUT0.
Output driver type of differential OUT4.
The same bit configuration with OUT0.
TABLE 3-10: 0X09 DRVTYPE2 - OUTPUT TYPE SELECT (OUTPUTS 8 TO 11)
Bit
Name
Description
Type
Reset
driver_type[23:22]
Output driver type of differential OUT11.
7:6
RW
11
The same bit configuration with OUT0.
Output driver type of differential OUT10.
driver_type[21:20]
driver_type[19:18]
driver_type[17:16]
5:4
3:2
1:0
RW
RW
RW
11
11
11
The same bit configuration with OUT0.
Output driver type of differential OUT9.
The same bit configuration with OUT0.
Output driver type of differential OUT8.
The same bit configuration with OUT0.
DS20006408B-page 24
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ZL40272
TABLE 3-11: 0X0A OUTLOW0 - OUTPUT DRIVE LOW (OUTPUTS 0 TO 7)
Bit
Name
Description
Type
Reset
Output driver type of differential OUT7.
7
output_drive_low[7]
RW
0
The same bit configuration with OUT0.
Output driver type of differential OUT6.
6
5
4
3
2
1
output_drive_low[6]
output_drive_low[5]
output_drive_low[4]
output_drive_low[3]
output_drive_low[2]
output_drive_low[1]
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
The same bit configuration with OUT0.
Output driver type of differential OUT5.
The same bit configuration with OUT0.
Output driver type of differential OUT4.
The same bit configuration with OUT0.
Output driver type of differential OUT3.
The same bit configuration with OUT0.
Output driver type of differential OUT2.
The same bit configuration with OUT0.
Output driver type of differential OUT1.
The same bit configuration with OUT0.
When this bit is set to 1, and when OUT0 is enabled, the
OUT0_p will drive low and OUT0_n will drive high volt-
age levels for corresponding type of the output. For
example, if output type for OUT0 is set to HCSL (driver_-
type = 2’b00), the OUT0_p will drive 0V and OUT0_n will
drive 0.75V.
When OUT0 is in high-Z mode (driver_type[1:0] = 2’b11),
this bit is ignored and the output will stay high-Z.
0
output_drive_low[0]
If this bit is set to 0, drive low function is disabled.
RW
0
output_drive_low[0]
driver_type[1:0] OUT0
0
0
0
0
1
1
1
1
00
01
10
11
00
01
HCSL
LVDS
LVPECL
Hi-Z
HCSL_drive_low
LVDS_drive_low
10 LVPECL_drive_low
11 Hi-Z
TABLE 3-12: 0X0B OUTLOW1 - OUTPUT DRIVE LOW (OUTPUTS 8 TO 11)
Bit
Name
Description
Type
Reset
7:4
Unused
Unused
R
0
Output driver type of differential OUT11.
3
2
output_drive_low[11]
output_drive_low[10]
The same bit configuration with OUT0.
Output driver type of differential OUT10.
The same bit configuration with OUT0.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 25
ZL40272
TABLE 3-12: 0X0B OUTLOW1 - OUTPUT DRIVE LOW (OUTPUTS 8 TO 11) (CONTINUED)
Bit
Name
Description
Type
Reset
Output driver type of differential OUT9.
1
output_drive_low[9]
The same bit configuration with OUT0.
Output driver type of differential OUT8.
0
output_drive_low[8]
The same bit configuration with OUT0.
TABLE 3-13: 0X0C COMMODSEL - COMMON MODE SELECT
Bit
Name
Description
Type
Reset
7:1
Unused
vcm_sel
Unused
R
0000000
The bit determines the range of the input VCM
0
1’b0: the input VCM is from 1V to 2V
RW
1
1’b1: the input VCM is from 0.1V to 0.8V (for HCSL for-
mat)
TABLE 3-14: 0X0E DEVADDR - I2C BUS SLAVE DEVICE ADDRESS
Bit
Name
Description
Type
Reset
7:3
Unused
Unused
R
00000
These three bits contributes as the following to the 7 bits
of the I2C Bus slave address {2'b01,
2:0
dev_addr[2:0]
dev_addr[2:0],SA1,SA0}, where SA0 and SA1 are from
pins IN_SEL0_I2C_SA_0 and IN_SEL0_I2C_SA_0
respectively.
RW
101
TABLE 3-15: 0X11 DEVID - DEVICE IDENTIFICATION
Bit
Name
Description
Type
Reset
7:5
4:0
Unused
dev_id
Unused
R
000
Device ID
RO
00011
DS20006408B-page 26
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ZL40272
4.0
ELECTRICAL CHARACTERISTICS
TABLE 4-1:
ABSOLUTE MAXIMUM RATINGS
Note 1, Note 2, Note 3
Parameter
Symbol
Min.
Max.
Units
Supply Voltage, 3.3V
Supply Voltage, 2.5V
VDD/VDDO
VDD/VDDO
TST
–0.5
–0.5
–55
+4.6
+3.5
+125
V
V
Storage Temperature Range
°C
Note 1: Exceeding these values may cause permanent damage.
2: Functional operation under these conditions is not implied.
3: Voltages are with respect to ground (GND) unless otherwise stated.
TABLE 4-2:
RECOMMENDED OPERATING CONDITIONS
Note 1, Note 2
Parameter
Symbol
Min.
Typ.
Max.
Units
Supply Voltage 3.3V
Supply Voltage 2.5V
Operating Temperature
Input Voltage
VDD/VDDO
VDD/VDDO
TA
3.135
2.375
–40
3.3
2.5
+25
—
3.465
2.625
V
V
+85
°C
V
VDD-IN
–0.3
VDD + 0.3
Note 1: Voltages are with respect to ground (GND) unless otherwise stated.
2: The device core supports two power supply modes (3.3V and 2.5V).
TABLE 4-3:
CURRENT CONSUMPTION
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
IS_3.3V
IS_2.5V
—
—
—
163
153
128
197
187
154
mA
mA
mA
VDD = 3.3V+5%
VDD = 2.5V+5%
VDD = 3.3V+5%
Core Device Current (all outputs
and XTAL disabled)
Core Device Current (all outputs
disabled) XTAL Circuit Enabled
with 25 MHz Crystal Connected
between XIN and XOUT
IDD_XTAL_3.3V
IDD_XTAL_2.5V
—
124
150
mA
VDD = 2.5V+5%
IDD_CM_3.3V
IDD_CM_2.5V
—
—
—
—
—
—
—
17.9
16.6
21.5
21.5
6.73
6.87
21
18.9
17.5
25.7
25.6
8
mA
mA
mA
mA
mA
mA
mA
VDDO = 3.3V+5%
VDDO = 2.5V+5%
VDDO = 3.3V+5%
VDDO = 2.5V+5%
VDDO = 3.3V+5%
VDDO = 2.5V+5%
VDDO = 3.3V+5%
Common Output Current
IDD_LVPECL_3.3V
IDD_LVPECL_2.5V
IDD_LVDSL_3.3V
IDD_LVDS_2.5V
IDD_85HCSL_3.3V
Current Dissipation per LVPECL
Output
Current Dissipation per LVDS
Output
7.83
22.8
Current Dissipation per HCSL
Output (IREF pin pulled down
with 422Ω)
IDD_85HCSL_2.5V
IDD_100HCSL_3.3V
IDD_100HCSL_2.5V
—
—
—
20
17.6
17
21.4
19.2
18.4
mA
mA
mA
VDDO = 2.5V+5%
VDDO = 3.3V+5%
VDDO = 2.5V+5%
Current Dissipation per HCSL
Output (IREF pin pulled down
with 536Ω)
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 27
ZL40272
TABLE 4-4:
INPUT CHARACTERISTICS
Note 1, Note 2, Note 3
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
CMOS High-Level Input Voltage for Control
Inputs
VCIH
1.05
—
—
V
—
—
CMOS Low-Level Input Voltage for Control
Inputs
VCIL
—
—
—
0.45
50
V
CMOS Input Leakage Current for Control
Inputs (includes current due to pull down
resistors)
IIL
–25
µA
VI = VDD or 0V
Differential Input Common Mode Voltage for
IN0_p/n and IN1_p/n
vcm_sel bit = 0
(reg 0x0C)
VCM
VCM
VID
1
—
—
—
—
2
V
V
V
V
Differential Input Common Mode Voltage for
IN0_p/n and IN1_p/n (HCSL common mode)
vcm_sel bit = 1
(reg 0x0C)
0.1
0.8
1.3
1.3
Differential Input Voltage Swing for IN0_p/n
and IN1_p/n; f < 1 GHz
0.15
0.35
—
—
Differential Input Voltage Swing for IN0_p/n
and IN1_p/n for 1 GHz < f < 1.5 GHz
VID
Differential Input Leakage Current for IN0_p/
n and IN1_p/n (includes current due to pull-
up and pull-down resistors)
IIL
–150
—
150
µA
VI = 2V or 0V
—
Single-Ended Input Voltage for IN0_p and
IN1_p
VSI
–0.3
1
—
—
—
—
2.7
2
V
V
V
V
Single-Ended Input Common Mode Voltage
(IN0_p and IN1_p)
vcm_sel bit = 0
(reg 0x0C)
VSIC
VSIC
VSID
Single-Ended Input Common Mode Voltage
(IN0_p and IN1_p) (HCSL common mode)
vcm_sel bit = 1
(reg 0x0C)
0.1
0.3
0.8
0.8
Single-Ended Input Voltage Swing for IN0_p
and IN1_p
—
Input Frequency (differential)
Input Frequency (single-ended)
Input Duty Cycle
fIN
0
0
—
—
—
2
1500
400
65
MHz
MHz
%
—
—
—
—
fIN_SE
DC
35
—
Input Slew Rate
tSLEW
—
V/ns
Input Pull-Up/Pull-Down Resistance for
IN0_p/IN0_n and IN1_p/IN1_n
RPU/RPD
RPD
—
—
—
60
30
—
—
—
kΩ
kΩ
kΩ
—
—
—
Input Pull-Down Resistance for INx_p
Control Input (OE_b[11:0]) Pull-Down Resis-
tance
RPDD
300
—
—
—
—
–90
–75
–61
–52
—
—
—
—
fIN = 100 MHz
fIN = 200 MHz
fIN = 400 MHz
fIN = 800 MHz
Input Multiplexer Isolation IN0_p/n to IN1_p/n
and Vice-Versa. Power on Both Inputs
0 dBm, fOFFSET > 50 kHz
ISO
dBc
Note 1: Values are over Recommended Operating Conditions.
2: Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V).
3: Input mux isolation is measured as amplitude of fOFFSET spur in dBc on the output clock phase noise plot
(1) low frequency only.
DS20006408B-page 28
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-5:
CRYSTAL OSCILLATOR CHARACTERISTICS
Note 1, Note 2
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Mode of Oscillation
Frequency
—
f
Fundamental
—
—
8
0
—
—
160
MHz
pF
On-Chip Load Capacitance
in I2C Bus Controlled Mode
CL
CL
RS
21.75
—
Programmable
Fixed
On-Chip Load Capacitance
in Pin Controlled Mode
—
0
4
pF
Ω
On-Chip Series Resistor in
I2C Bus Controlled Mode
—
312
Programmable
On-Chip Series Resistor in
Pin Controlled Mode
RS
R
—
—
84
—
—
Ω
Fixed
—
On-Chip Shunt Resistor
500
kΩ
Functional, but may not meet AC
parameters. Minimum depends
on AC coupling capacitor (0.1 µF
assumed).
Frequency in Overdrive
Mode (Note 3)
fOV
0.1
0
—
—
250
250
MHz
MHz
Frequency in Bypass Mode
(Note 4)
Functional, but may not meet AC
parameters.
fBP
Note 1: Values are over Recommended Operating Conditions.
2: Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V).
3: Maximum input level is 2V.
4: Maximum output level is VDD
.
TABLE 4-6:
POWER SUPPLY REJECTION RATIO FOR VDD = VDDO = 3.3V
Note 1, Note 2, Note 3
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
–79
–81
–84
–91
–88
–81
–95
–93
–84
—
—
—
—
—
—
—
—
—
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 100 MHz
fIN = 133 MHz
fIN = 400 MHz
PSRR for LVPECL Output
PSRR for LVDS Output
PSRR for HCSL Output
PSRRLVPECL
dBc
PSRRLVDS
PSRRHCSL
dBc
dBc
Note 1: Values are over Recommended Operating Conditions.
2: Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVPP
3: PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot.
.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 29
ZL40272
TABLE 4-7:
POWER SUPPLY REJECTION RATIO FOR VDD = VDDO = 2.5V
Note 1, Note 2, Note 3
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
–82
–71
–68
–97
–79
–78
–89
–94
–82
—
—
—
—
—
—
—
—
—
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 100 MHz
fIN = 133 MHz
fIN = 400 MHz
PSRR for LVPECL Output
PSRRLVPECL
dBC
PSRR for LVDS Output
PSRR for HCSL Output
PSRRLVDS
PSRRHCSL
dBc
dBc
Note 1: Values are over Recommended Operating Conditions.
2: Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVPP
3: PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot.
.
TABLE 4-8:
LVPECL OUTPUT CHARACTERISTICS FOR VDDO = 3.3V
Note 1
Characteristics
Symbol
Min
Typ.
Max.
Units
Notes
Output High Voltage
VLVPECL_OH
VLVPECL_OL
VLVPECL_SW
1.9
1.2
0.6
2.08
1.36
0.72
2.5
1.7
0.9
V
V
V
DC Measurement
DC Measurement
DC Measurement
Output Low Voltage
Output Differential Swing (Note 2)
Variation of VLVPECL_SW for Com-
plementary Output States
∆VLVPECL_SW
VCM
0
0.02
1.72
—
0.07
2.1
V
V
—
—
—
Common Mode Output
1.6
—
Output Frequency when
VLVPECL_SW ≥ 0.6V
fMAX_0.6VSW
800
MHz
Output Frequency when
VLVPECL_SW ≥ 0.4V
fMAX_0.4VSW
—
—
1500
MHz
—
Rise or Fall Time (20% to 80%)
Output Frequency
tr, tf
fO
—
0
110
—
—
—
1
170
1500
40
ps
MHz
ps
—
—
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
Output Enable Time
tOOSK
tDOOSK
tIOD
—
—
0.8
—
—
120
1.2
5
ps
ns
tEN
—
—
cycles
cycles
Output Disable Time
tDIS
5
Input clock:
100 MHz
—
—
—
—
—
—
63
41
21
67
46
27
81
56
32
89
67
46
Additive RMS Jitter in 1 MHz to
20 MHz band
Input clock:
156.25 MHz
tj_1M_20M
fs
fs
Input clock:
625 MHz
Input clock:
100 MHz
Additive RMS Jitter in 12 kHz to
20 MHz band
Input clock:
156.25 MHz
tj_12k_20M
Input clock:
625 MHz
DS20006408B-page 30
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-8:
LVPECL OUTPUT CHARACTERISTICS FOR VDDO = 3.3V (CONTINUED)
Note 1
Characteristics
Symbol
Min
Typ.
Max.
Units
Notes
Input clock:
100 MHz
—
–163
–161
Input clock:
156.25 MHz
Noise Floor
NF
—
—
–163
–158
–161
–156
dBc/Hz
Input clock:
625 MHz
Note 1: Values are over Recommended Operating Conditions.
2: Output differential swing is calculated as VSW = VOH – VOL. It should not be confused with
VSW = 2 * (VOH – VOL) sometimes used in some data sheets.
TABLE 4-9:
LVPECL OUTPUT CHARACTERISTICS FOR VDDO = 2.5V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Output High Voltage
VLVPECL_OH
VLVPECL_OL
VLVPECL_SW
1.1
0.4
0.6
1.28
0.57
0.71
1.7
0.9
1
V
V
V
DC Measurement
DC Measurement
DC Measurement
Output Low Voltage
Output Differential Swing (Note 2)
Variation of VLVPECL_SW for Com-
plementary Output States
∆VLVPECL_SW
VCM
0
0.02
0.92
—
0.05
1.2
V
V
—
—
—
Common Mode Output
0.8
—
Output Frequency when
VLVPECL_SW ≥ 0.6V
fMAX_0.6VSW
800
MHz
Output Frequency when
VLVPECL_SW ≥ 0.4V
fMAX_0.4VSW
—
—
1500
MHz
—
Rise or Fall Time (20% to 80%)
Output Frequency
tr, tf
fO
—
0
120
—
—
—
1
170
1500
40
ps
MHz
ps
—
—
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
Output Enable Time
tOOSK
tDOOSK
tIOD
—
—
0.8
—
—
120
1.2
5
ps
ns
tEN
—
—
cycles
cycles
Output Disable Time
tDIS
5
Input clock:
100 MHz
—
—
—
—
—
—
60
40
21
64
45
27
77
55
33
86
89
47
Additive RMS Jitter in 1 MHz to
20 MHz band
Input clock:
156.25 MHz
tj_1M_20M
fs
fs
Input clock:
625 MHz
Input clock:
100 MHz
Additive RMS Jitter in 12 kHz to
20 MHz band
Input clock:
156.25 MHz
tj_12k_20M
Input clock:
625 MHz
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 31
ZL40272
TABLE 4-9:
LVPECL OUTPUT CHARACTERISTICS FOR VDDO = 2.5V (CONTINUED)
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Input clock:
100 MHz
—
–164
–162
Input clock:
156.25 MHz
Noise Floor
NF
—
—
–164
–158
–161
–156
dBc/Hz
Input clock:
625 MHz
Note 1: Values are over Recommended Operating Conditions.
2: Output differential swing is calculated as VSW = VOH – VOL. It should not be confused with
SW = 2 * (VOH – VOL) sometimes used in some data sheets.
V
TABLE 4-10: LVDS OUTPUTS FOR VDDO = 3.3V
Note 1
Characteristics
Output High Voltage
Symbol
Min.
Typ.
Max.
Units
Notes
VLVDS_OH
VLVDS_OL
VLVDS_SW
1.3
1.0
1.39
1.07
0.32
1.48
1.15
0.39
V
V
V
DC Measurement
DC Measurement
DC Measurement
Output Low Voltage
Output Differential Swing (Note 2)
0.25
Variation of VLVDS_SW for Comple-
mentary Output States
∆VLVDS_SW
VCM
0
1.15
0
0.002
1.23
0.01
1.3
V
V
V
—
—
—
Common Mode Output
Variation of VCM for Complemen-
tary Output States
∆VCM
0.001
0.01
Output Frequency when
VLVDS_SW ≥ 0.6V
fMAX_0.6VSW
fMAX_0.4VSW
—
—
—
—
800
MHz
MHz
—
—
Output Frequency when
VLVDS_SW ≥ 0.4V
1500
Rise or Fall Time (20% to 80%)
Output Frequency
tr, tf
fO
—
0
110
—
—
—
1
170
1500
20
ps
MHz
ps
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
tOOSK
tDOOSK
tIOD
—
—
0.8
130
1.2
ps
ns
Single-ended out-
puts shorted to
GND
Output Short Circuit Current Single-
Ended
IS
–24
—
24
mA
Output Short Circuit Current Differ-
ential
Complementary
outputs shorted
ISD
–24
—
24
mA
Output Enable Time
Output Disable Time
tEN
—
—
—
—
5
5
cycles
cycles
—
—
tDIS
Input clock:
100 MHz
—
—
—
87
46
21
102
58
Additive RMS Jitter in 1 MHz to
20 MHz band
Input clock:
156.25 MHz
tj_1M_20M
fs
Input clock:
625 MHz
32
DS20006408B-page 32
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-10: LVDS OUTPUTS FOR VDDO = 3.3V (CONTINUED)
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Input clock:
100 MHz
—
91
108
Additive RMS Jitter in 12 kHz to
20 MHz band
Input clock:
156.25 MHz
tj_12k_20M
—
—
—
—
—
51
69
fs
Input clock:
625 MHz
27
48
Input clock:
100 MHz
–161
–162
–158
–159
–161
–156
Input clock:
156.25 MHz
Noise Floor
NF
dBc/Hz
Input clock:
625 MHz
Note 1: Values are over Recommended Operating Conditions.
2: Output differential swing is calculated as VSW = VOH – VOL. It should not be confused with
SW = 2 * (VOH – VOL) sometimes used in some data sheets.
V
TABLE 4-11: LVDS OUTPUTS FOR VDDO = 2.5V
Note 1
Characteristics
Output High Voltage
Symbol
Min.
Typ.
Max.
Units
Notes
VLVDS_OH
VLVDS_OL
VLVDS_SW
1.3
1.4
1.5
V
V
V
DC Measurement
DC Measurement
DC Measurement
Output Low Voltage
0.97
0.25
1.05
0.35
1.13
0.44
Output Differential Swing (Note 2)
Variation of VLVDS_SW for Comple-
mentary Output States
∆VLVDS_SW
VCM
0
1.15
0
0.001
1.23
0.01
1.3
V
V
V
—
—
—
Common Mode Output
Variation of VCM for Complemen-
tary Output States
∆VCM
0.001
0.01
Output Frequency when
VLVDS_SW ≥ 0.6V
fMAX_0.6VSW
fMAX_0.4VSW
—
—
—
—
800
MHz
MHz
—
—
Output Frequency when
VLVDS_SW ≥ 0.4V
1500
Rise or Fall Time (20% to 80%)
Output Frequency
tr, tf
fO
—
0
110
—
—
—
1
170
1500
20
ps
MHz
ps
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
tOOSK
tDOOSK
tIOD
—
—
0.8
130
1.2
ps
ns
Single-ended out-
puts shorted to
GND
Output Short Circuit Current Single-
Ended
IS
–24
—
24
mA
Output Short Circuit Current Differ-
ential
Complementary
outputs shorted
ISD
–24
—
24
mA
Output Enable Time
Output Disable Time
tEN
—
—
—
—
3
3
cycles
cycles
—
—
tDIS
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 33
ZL40272
TABLE 4-11: LVDS OUTPUTS FOR VDDO = 2.5V (CONTINUED)
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Input clock:
100 MHz
—
81
100
Additive RMS Jitter in 1 MHz to
20 MHz band
Input clock:
156.25 MHz
tj_1M_20M
—
—
—
—
—
—
—
—
44
21
58
34
fs
Input clock:
625 MHz
Input clock:
100 MHz
85
107
70
Additive RMS Jitter in 12 kHz to
20 MHz band
Input clock:
156.25 MHz
tj_12k_20M
48
fs
Input clock:
625 MHz
27
50
Input clock:
100 MHz
–161
–163
–158
–159
–161
–156
Input clock:
156.25 MHz
Noise Floor
NF
dBc/Hz
Input clock:
625 MHz
Note 1: Values are over Recommended Operating Conditions.
2: Output differential swing is calculated as VSW = VOH – VOL. It should not be confused with
SW = 2 * (VOH – VOL) used in some data sheets.
V
TABLE 4-12: HCSL OUTPUTS (PCIe ELECTRICAL CHARACTERISTICS) FOR VDDO = 3.3V
Note 1
Characteristics
Rising Edge Rate
Symbol
Min.
Typ.
Max.
Units
Notes
Rise_Rate
Fall_Rate
VIH
1.4
1.4
0.6
—
1.75
1.75
—
4
4
V/ns
V/ns
V
Note 3, Note 4
Note 3, Note 4
Note 3
Falling Edge Rate
Differential High Voltage
Differential Low Voltage
Single-Ended High Voltage
Single-Ended Low Voltage
—
VIL
—
–0.6
0.85
20
V
Note 3
VSIH
0.65
–20
0.75
0
V
DC Measurement
DC Measurement
VSIL
mV
Note 2, Note 5,
Note 6
Absolute Crossing Voltage
VCROSS
0.25
—
—
—
0.55
V
V
Variation of VCROSS over All Rising
Clock Edges
Note 2, Note 5,
Note 10
∆VCROSS
0.140
Ringback Voltage Margin
Time before VRB is Allowed
Cycle-to-Cycle Additive Jitter
Absolute Maximum Voltage
Absolute Minimum Voltage
VRB
tSTABLE
tJCC
–0.55
4.6
—
—
0.55
—
V
ns
Note 3, Note 12
Note 3, Note 12
Note 3
—
4.6
—
5.8
1.15
—
psPP
V
VMAX
VMIN
—
Note 2, Note 8
Note 2, Note 9
–0.3
—
V
Output Duty Cycle (When Input has
50% of Duty Cycle)
ODC
48
—
—
50
—
50
52
20
—
%
%
Ω
Note 3
Rising to Falling Edge Matching
r/f match
ZC-DC_CK
Note 2, Note 13
DC Measurement,
Note 2
Clock Source DC Impedance (CK)
DS20006408B-page 34
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-12: HCSL OUTPUTS (PCIe ELECTRICAL CHARACTERISTICS) FOR VDDO = 3.3V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
DC Measurement,
Note 2
Clock Source DC Impedance (CK#)
ZC-DC_CK#
—
50
—
Ω
Output Frequency
fOUT
tOOSK
tDOOSK
tIOD
0
—
—
0.8
—
—
—
—
—
1
400
50
129
1.2
5
MHz
ps
—
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
Output Enable Time
ps
ps
tEN
—
—
cycles
cycles
Output Disable Time
tDIS
5
Note 1: Values are over Recommended Operating Conditions.
2: Measurement taken from single-ended waveform.
3: Measurement taken from differential waveform.
4: Measured from –150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The sig-
nal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement
window is centered on the differential zero crossing. See Figure 28.
5: Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the fall-
ing edge of CK#. See Figure 25.
6: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing. Refers to all crossing points for this measurement. See Figure 25.
7: This requirement, from PCI Express Base Specification, Revision 4.0 is applicable only to clock genera-
tors and not to buffers. A clock buffer is a transparent device whose output clock period follows the input
clock period.
8: Defined as the maximum instantaneous voltage including overshoot. See Figure 25.
9: Defined as the minimum instantaneous voltage including undershoot. See Figure 25.
10: Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum
allowed variance in VCROSS for any particular system. See Figure 26.
11: The PPM requirement from PCI Express Base Specification, Revision 4.0 is related to clock generation
devices. This requirement is not applicable to buffers because the buffer’s output frequency accuracy is
identical to the frequency accuracy of the source driving the buffer.
12: tSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after 20 ris-
ing/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 29.
13: Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV
window centered on the median cross point where CKx rising meets CK#x falling. The median cross point
is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed differ-
ence should not exceed 20% of the slowest edge rate. See Figure 27.
TABLE 4-13: HCSL (PCIe) JITTER PERFORMANCE FOR VDDO = 3.3V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Additive Jitter as per PCIe 1.0
(1.5 MHz to 22 MHz)
Input clock:
100 MHz
tjPCIe_1.0
—
99
122
fsRMS
Additive Jitter as per PCIe 2.0 High
Band (1.5 MHz to 50 MHz)
Input clock:
100 MHz
tjPCIe_2.0_high
tjPCIe_2.0_low
tjPCIe_2.0_mid
—
—
—
98
26
77
120
36
fsRMS
fsRMS
fsRMS
Additive Jitter as per PCIe 2.0 Low
Band (10 kHz to 1.5 MHz)
Input clock:
100 MHz
Additive Jitter as per PCIe 2.0 Mid
Band (5 MHz to 16 MHz)
Input clock:
100 MHz
94
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 35
ZL40272
TABLE 4-13: HCSL (PCIe) JITTER PERFORMANCE FOR VDDO = 3.3V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Additive Jitter as per PCIe 3.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
Input clock:
100 MHz
tjPCIe_3.0
—
24
30
fsRMS
Additive Jitter as per PCIe 4.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
Input clock:
100 MHz
tjPCIe_4.0
—
—
24
10
30
12
fsRMS
Additive Jitter as per PCIe 5.0
(PLL_BW = 0.5 MHz to 1.8 MHz,
CDR for 32 GT/s CC)
Input clock:
100 MHz
tjPCIe_5.0
fsRMS
Additive Jitter as per Intel QPI
9.6 Gbps
Input clock:
100 MHz
tjQPI
—
—
—
—
—
—
—
—
—
—
45
64
55
75
fsRMS
Input clock:
100 MHz
Additive RMS Jitter in 1 MHz to
20 MHz Band
Input clock:
133 MHz
tj_1M_20M
tj_12k_20M
NF
48
60
fsRMS
Input clock:
400 MHz
26
33
Input clock:
100 MHz
68
83
Additive RMS Jitter in 12 kHz to
20 MHz Band
Input clock:
133 MHz
52
66
fsRMS
Input clock:
400 MHz
31
43
Input clock:
100 MHz
–163
–164
–160
–161
–162
–158
Input clock:
133 MHz
Noise Floor
dBc/Hz
Input clock:
400 MHz
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-14: HCSL OUTPUTS (PCIe ELECTRICAL CHARACTERISTICS) FOR VDDO = 2.5V
Note 1
Characteristics
Rising Edge Rate
Symbol
Min.
Typ.
Max.
Units
Notes
Rise_Rate
Fall_Rate
VIH
1.4
1.4
0.6
—
1.75
1.75
—
4
4
V/ns
V/ns
V
Note 3, Note 4
Note 3, Note 4
Note 3
Falling Edge Rate
Differential High Voltage
Differential Low Voltage
Single-Ended High Voltage
Single-Ended Low Voltage
—
VIL
—
–0.6
0.85
20
V
Note 3
VSIH
0.65
–20
0.75
0
V
DC Measurement
DC Measurement
VSIL
mV
Note 2, Note 5,
Note 6
Absolute Crossing Voltage
VCROSS
0.25
—
—
—
0.55
V
V
Variation of VCROSS over All Rising
Clock Edges
Note 2, Note 5,
Note 10
∆VCROSS
0.140
Ringback Voltage Margin
Time before VRB is Allowed
Cycle-to-Cycle Additive Jitter
VRB
tSTABLE
tJCC
–0.55
4.6
—
—
0.55
—
V
ns
Note 3, Note 12
Note 3, Note 12
Note 3
—
4.6
5.8
psPP
DS20006408B-page 36
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-14: HCSL OUTPUTS (PCIe ELECTRICAL CHARACTERISTICS) FOR VDDO = 2.5V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Absolute Maximum Voltage
Absolute Minimum Voltage
VMAX
VMIN
—
—
—
1.15
—
V
V
Note 2, Note 8
Note 2, Note 9
–0.3
Output Duty Cycle (When Input has
50% of Duty Cycle)
ODC
48
—
—
50
—
50
52
20
—
%
%
Ω
Note 3
Rising to Falling Edge Matching
r/f match
ZC-DC_CK
Note 2, Note 13
DC Measurement,
Note 2
Clock Source DC Impedance (CK)
DC Measurement,
Note 2
Clock Source DC Impedance (CK#)
ZC-DC_CK#
—
50
—
Ω
Output Frequency
fOUT
tOOSK
tDOOSK
tIOD
0
—
—
0.8
—
—
—
—
—
1
400
50
129
1.2
5
MHz
ps
—
—
—
—
—
—
Output-to-Output Skew
Device-to-Device Output Skew
Input-to-Output Delay
Output Enable Time
ps
ps
tEN
—
—
cycles
cycles
Output Disable Time
tDIS
5
Note 1: Values are over Recommended Operating Conditions.
2: Measurement taken from single-ended waveform.
3: Measurement taken from differential waveform.
4: Measured from –150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The sig-
nal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement
window is centered on the differential zero crossing. See Figure 28.
5: Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the fall-
ing edge of CK#. See Figure 25.
6: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing. Refers to all crossing points for this measurement. See Figure 25.
7: This requirement, from PCI Express Base Specification, Revision 4.0 is applicable only to clock genera-
tors and not to buffers. A clock buffer is a transparent device whose output clock period follows the input
clock period.
8: Defined as the maximum instantaneous voltage including overshoot. See Figure 25.
9: Defined as the minimum instantaneous voltage including undershoot. See Figure 25.
10: Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum
allowed variance in VCROSS for any particular system. See Figure 26.
11: The PPM requirement from PCI Express Base Specification, Revision 4.0 is related to clock generation
devices. This requirement is not applicable to buffers because the buffer’s output frequency accuracy is
identical to the frequency accuracy of the source driving the buffer.
12: tSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after 20 ris-
ing/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 29.
13: Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV
window centered on the median cross point where CKx rising meets CK#x falling. The median cross point
is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed differ-
ence should not exceed 20% of the slowest edge rate. See Figure 27.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 37
ZL40272
TABLE 4-15: HCSL (PCIe) JITTER PERFORMANCE FOR VDDO = 2.5V
Note 1
Characteristics
Symbol
Min.
Typ.
Max.
Units
Notes
Additive Jitter as per PCIe 1.0
(1.5 MHz to 22 MHz)
Input clock:
100 MHz
tjPCIe_1.0
—
86
110
fsRMS
Additive Jitter as per PCIe 2.0 High
Band (1.5 MHz to 50 MHz)
Input clock:
100 MHz
tjPCIe_2.0_high
tjPCIe_2.0_low
tjPCIe_2.0_mid
—
—
—
85
23
67
108
38
fsRMS
fsRMS
fsRMS
Additive Jitter as per PCIe 2.0 Low
Band (10 kHz to 1.5 MHz)
Input clock:
100 MHz
Additive Jitter as per PCIe 2.0 Mid
Band (5 MHz to 16 MHz)
Input clock:
100 MHz
85
Additive Jitter as per PCIe 3.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
Input clock:
100 MHz
tjPCIe_3.0
—
—
—
21
21
8
27
27
11
fsRMS
Additive Jitter as per PCIe 4.0
(PLL_BW = 2 MHz to 5 MHz, CDR
= 10 MHz)
Input clock:
100 MHz
tjPCIe_4.0
fsRMS
Additive Jitter as per PCIe 5.0
(PLL_BW = 0.5 MHz to 1.8 MHz,
CDR for 32 GT/s CC)
Input clock:
100 MHz
tjPCIe_5.0
fsRMS
Additive Jitter as per Intel QPI
9.6 Gbps
Input clock:
100 MHz
tjQPI
—
—
—
—
—
—
—
—
—
—
40
56
50
70
fsRMS
Input clock:
100 MHz
Additive RMS Jitter in 1 MHz to
20 MHz Band
Input clock:
133 MHz
tj_1M_20M
tj_12k_20M
NF
45
58
fsRMS
Input clock:
400 MHz
25
34
Input clock:
100 MHz
60
77
Additive RMS Jitter in 12 kHz to
20 MHz Band
Input clock:
133 MHz
49
65
fsRMS
Input clock:
400 MHz
30
45
Input clock:
100 MHz
–164
–164
–160
–161
–162
–158
Input clock:
133 MHz
Noise Floor
dBc/Hz
Input clock:
400 MHz
Note 1: Values are over Recommended Operating Conditions.
DS20006408B-page 38
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
Vmax = 1.15V
OUTx_n
Vcross_max = 550mV
Vcross_min = 250mV
OUTx_p
Vmax = -0.3V
FIGURE 4-1:
Single-Ended Measurement Points for Absolute Cross Point and Swing.
OUTx_n
Vcross_delta = 250mV
OUTx_p
FIGURE 4-2:
Single-Ended Measurement Points for Delta Cross Point.
tfall
OUTx_n
Vcross_median + 75mV
Vcross_median
Vcross_median
Vcross_median – 75mV
OUTx_p
trise
Rise/fall match = MIN[|trise – tfall|/trise,|trise – tfall|/tfall]*100%
FIGURE 4-3:
Single-Ended Measurement Points for Rise and Fall Time Matching.
OUTx_p -OUTx_n
slew_rise = 0.3V/trise_edge_rate [V/ns]
slew_fall = 0.3V/tfall_edge_rate [V/ns]
Differential Measurement Points for Rise and Fall Time.
FIGURE 4-4:
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 39
ZL40272
OUTx_p - OUTx_n
FIGURE 4-5:
Differential Measurement Points for Ringback.
15 dB loss at 4 GHz
Refclk Margins
CK
DUT
CK#
DiīerenƟal PCB trace
DIFF = 100ё 10%
2 pF 5%
2 pF 5%
Z
FIGURE 4-6:
PCIe Test Circuit.
TABLE 4-16: LVPECL OUTPUT PHASE NOISE WITH 25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
DD = 3.3V, VDDO = 3.3V
VDD = 2.5V, VDDO = 2.5V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
265
213
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
Jitter RMS in 12 kHz to 5 MHz
Band
–102
–127
–153
–158
–158
–158
–96
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
Noise Floor
–122
–151
–160
–160
–160
Note 1: Values are over Recommended Operating Conditions.
DS20006408B-page 40
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-17: LVDS OUTPUT PHASE NOISE WITH 25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
172
177
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
VDD = 2.5V, VDDO = 2.5V
–102
–126
–153
–160
–161
–160
–96
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
Noise Floor
–123
–152
–161
–161
–160
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-18: HCSL OUTPUT PHASE NOISE WITH 25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
235
143
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
VDD = 2.5V, VDDO = 2.5V
–102
–126
–153
–158
–159
–158
–97
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
Noise Floor
–123
–153
–162
–162
–163
Note 1: Values are over Recommended Operating Conditions.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 41
ZL40272
TABLE 4-19: LVPECL OUTPUT PHASE NOISE WITH 125 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
62
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
67
VDD = 2.5V, VDDO = 2.5V
–95
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–124
–144
–155
–161
–161
–163
–164
–95
Noise Floor
–125
–143
–154
–160
–160
–162
–163
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-20: LVDS OUTPUT PHASE NOISE WITH 125 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
74
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
75
VDD = 2.5V, VDDO = 2.5V
–93
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–124
–145
–155
–159
–159
–161
–162
–95
Noise Floor
–124
–144
–155
–159
–159
–161
–161
Note 1: Values are over Recommended Operating Conditions.
DS20006408B-page 42
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-21: HCSL OUTPUT PHASE NOISE WITH 125 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
63
VDD = 2.5V, VDDO = 2.5V
–93
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–125
–145
–156
–161
–160
–163
–163
–94
Noise Floor
–124
–144
–156
–161
–160
–163
–163
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-22: LVPECL OUTPUT PHASE NOISE WITH 156.25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
49
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
53
VDD = 2.5V, VDDO = 2.5V
–86
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–117
–141
–153
–160
–163
–163
–164
–85
Noise Floor
–119
–142
–154
–160
–162
–163
–163
Note 1: Values are over Recommended Operating Conditions.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 43
ZL40272
TABLE 4-23: LVDS OUTPUT PHASE NOISE WITH 156.25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
53
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
55
VDD = 2.5V, VDDO = 2.5V
–85
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–118
–143
–154
–160
–162
–163
–163
–87
Noise Floor
–119
–142
–154
–159
–162
–162
–162
Note 1: Values are over Recommended Operating Conditions.
TABLE 4-24: HCSL OUTPUT PHASE NOISE WITH 156.25 MHZ XTAL
Note 1
Characteristics
Min.
Typ.
Max.
Units
Notes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs
fs
V
DD = 3.3V, VDDO = 3.3V
Jitter RMS in 12 kHz to 5 MHz
Band
50
VDD = 2.5V, VDDO = 2.5V
–85
dBc/Hz @100 Hz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 kHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @1 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @5 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @10 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @20 MHz, VDD = 3.3V, VDDO = 3.3V
dBc/Hz @100 Hz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @100 kHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @1 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @5 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @10 MHz, VDD = 2.5V, VDDO = 2.5V
dBc/Hz @20 MHz, VDD = 2.5V, VDDO = 2.5V
–117
–143
–155
–161
–163
–164
–164
–86
Noise Floor
–119
–142
–154
–160
–163
–163
–163
Note 1: Values are over Recommended Operating Conditions.
DS20006408B-page 44
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
TABLE 4-25: I2C BUS ELECTRICAL CHARACTERISTICS
Characteristics
Nominal Bus Voltage
Symbol
Min.
Typ.
Max.
Units
Notes
VDDI2C
VIL
2.375
—
—
—
—
—
—
—
—
5.5
0.7
V
V
Note 1
Input Low Voltage
—
Input High Voltage
VIH
1.5
—
VDDI2C
0.4
V
—
Output Low Voltage
Input Leakage Current
Current Sinking at VOL(MAX)
Pin Capacitive Load
VOL
V
At IPULLUP(MAX)
ILEAK
IPULLUP
CL
—
±10
—
µA
mA
pF
—
—
—
4
—
1
Signal Noise Immunity from 10 MHz
to 100 MHz
VNOISE
300
—
—
mVPP
—
Noise Spike Suppression Time
I2C Bus Operating Frequency
tSPIKE
fOC
0
0
—
—
50
ns
Note 3
—
400
kHz
Bus Free Time between Start and
Stop Conditions
tBUF
1.3
0.6
0.6
—
—
—
—
—
—
µs
µs
µs
—
After this period,
the first clock is
generated
Hold Time after (Repeated) Start
Condition
tHD:STA
Repeated Start Condition Setup
Time
tSU:STA
—
Stop Condition Setup Time
Data Hold Time
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
0.6
0
—
—
—
—
—
—
—
0.9
—
µs
µs
ns
ms
µs
µs
—
Note 4
—
Data Setup Time
100
25
Detect Clock Low Timeout
Clock Low Period
35
—
—
1.3
0.6
—
Clock High Period
tHIGH
—
—
20 +
0.1*Cb
Clock/Data Fall Time
tF
—
—
250
250
ns
ns
Note 2
Note 2
20 +
0.1*Cb
Clock /Data Rise Time
tR
Note 1: 3V to 5V ±10%
2: Rise and fall time is defined as follows: tR = (VIL(MAX) – 0.15) to (VIH(MIN) + 0.15); tF = (VIH(MIN) – 0.15) to
(VIL(MAX) + 0.15)
3: Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.
4: The maximum hold time has to be less than the maximum data valid or data valid acknowledge time as
per Table 10, note [4] of I2C bus Rev. 6 specification.
FIGURE 4-7:
I2C Bus Timing.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 45
ZL40272
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Maximum Ambient Temperature
Maximum Junction Temperature
TA(MAX)
TJ(MAX)
—
—
—
—
+85
°C
°C
—
—
+125
Package Thermal Resistance, 8x8 QFN-56Ld
—
—
19.5
15.7
13.9
6.3
—
—
—
—
—
°C/W Still-air
Junction to Ambient Thermal
θJA
°C/W 1 m/s airflow
°C/W 2.5 m/s airflow
Resistance (Note 1)
—
—
—
Junction to Board Thermal Resistance
Junction to Case Thermal Resistance
θJB
θJC
°C/W
°C/W
—
—
11
Junction to Pad Thermal Resistance
(Note 2)
θJP
—
—
3.6
0.2
—
—
°C/W Still-air
°C/W Still-air
Junction to Top-Center Thermal
Characterization Parameter
ΨJT
Note 1: Theta-JA (θJA) is the thermal resistance from junction to ambient when the package is mounted on a 8-
layer JEDEC standard test board and dissipating maximum power.
2: Theta-JP (θJP) is the thermal resistance from junction to the center exposed pad on the bottom of the
package.
DS20006408B-page 46
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
5.0
5.1
PACKAGE OUTLINE
Package Marking Information
Example
56-Lead QFN*
XXXXXXX
X X
YYWWNNN
ZL40272
Z Z
2041971
Legend: XX...X Product code or customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
e3)
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar (‾) symbol may not be to scale.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 47
ZL40272
56-Lead 8 mm x 8 mm QFN Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20006408B-page 48
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
NOTES:
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 49
ZL40272
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
Correction
Converted Microsemi data sheet ZL40272 to Micro-
chip DS20006408A. Minor text changes throughout.
DS20006408A (09-09-20)
DS20006408B (12-03-21)
—
Corrected values in the figure for when vcm_sel = 1.
RUP is 3.3 kΩ and RDOWN is 590Ω.
Figure 2-7
DS20006408B-page 50
2020 - 2021 Microchip Technology Inc. and its subsidiaries
ZL40272
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
Device
X
X
X
X
a) ZL40272LDG1:
Low-Skew, Low Additive Jitter,
Part
Number
Chip Carrier
Type
Package
Media Type
Finish
12 Output HCSL/LVDS/LVPECL
Fanout Buffer with Per-Output
Enable Control, Leadless Chip
Carrier, 56-Lead QFN, 260/Tray,
Pb Free with Matte Sn lead finish,
RoHS e3 Compliant
Device:
ZL40272: Low-Skew, Low Additive Jitter, 12 Output HCSL/
LVDS/LVPECL Fanout Buffer with Per-Output
Enable Control
b) ZL40272LDF1:
Chip Carrier Type: L = Leadless Chip Carrier
Low-Skew, Low Additive Jitter,
12 Output HCSL/LVDS/LVPECL
Fanout Buffer with Per-Output
Enable Control, Leadless Chip
Carrier, 56-Lead QFN, 2,700/Reel,
Pb Free with Matte Sn lead finish,
RoHS e3 Compliant
Package:
D = 56-Lead 8 mm x 8 mm QFN
Media Type:
G = 260/Tray
F = 2,700/Reel
Finish:
1 = Pb Free with Matte Sn lead finish, RoHS e3 Compliant
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 51
ZL40272
NOTES:
DS20006408B-page 52
2020 - 2021 Microchip Technology Inc. and its subsidiaries
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip
products with your application. Use of this information in any other manner violates these terms. Information regarding device applications
is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets
with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https://www.micro-
chip.com/en-us/support/design-help/client-support-services.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF
ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMA-
TION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FIT-
NESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL
LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER
CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFOR-
MATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION.
Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify
and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF,
dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA,
SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are
registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion,
SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling,
Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart,
PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS,
SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense,
VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2020 - 2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved.
ISBN: 978-1-5224-9422-5
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
2020 - 2021 Microchip Technology Inc. and its subsidiaries
DS20006408B-page 53
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DS20006408B-page 54
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09/14/21
相关型号:
ZL40293LDF1
Low Skew Clock Driver, 4000/14000/40000 Series, 40 True Output(s), 0 Inverted Output(s), CMOS
MICROCHIP
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