dsPIC33FJ09GS302 [MICROCHIP]
16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators; 16位微控制器和数字信号控制器与高速PWM ， ADC和比较器
| 型号： | dsPIC33FJ09GS302 |
| 厂家： | 
MICROCHIP |
| 描述： | 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators |
| 文件： | 总352页 (文件大小：3423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, ADC and Comparators
Operating Conditions
Advanced Analog Features (Continued)
• ADC module:
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
- 10-bit resolution with Successive Approximation
Register (SAR) converter (2 Msps) and three
Sample-and-Hold (S&H) circuits
- Up to 8 input channels grouped into four conversion
pairs, plus two inputs for monitoring voltage references
- Flexible and independent ADC trigger sources
- Dedicated Result register for each
analog channel
Core: 16-Bit dsPIC33F CPU
• Code Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
Timers/Output Compare/Input Capture
• Two 16-Bit General Purpose Timers/Counters
• Input Capture module
• Output Compare module
• ±2% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
• Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (10 Mbps):
- With support for LIN/J2602 protocols and IrDA
Power Management
®
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 2.0 mA/MHz Dynamic Current (typical)
• 135 µA IPD Current (typical)
• 4-Wire SPI module
2
• I C™ module (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
Input/Output
• Constant Current Source:
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 1.04 ns PWM Resolution for Dead Time, Duty Cycle,
Phase and Frequency
- Constant current generator (10 µA nominal)
• Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• External Interrupts on 16 I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned
• Class B Safety Library, IEC 60730
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
Debugger Development Support
• In-Circuit and In-Application Programming
• Two Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
• Two High-Speed Comparators with Direct Connection to
the PWM module:
- Buffered/amplified output drive
- Independent 10-bit DAC for each comparator
- Rail-to-rail comparator operation
- DACOUT amplifier (1x, 1.8x)
- Selectable hysteresis
- Programmable output polarity
- Interrupt generation capability
2011-2012 Microchip Technology Inc.
DS75018C-page 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 PRODUCT
FAMILIES
The device names, pin counts, memory sizes and periph-
eral availability of each device are listed in Table 1. The
following pages show their pinout diagrams.
TABLE 1:
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES
Remappable Peripherals
ADC
Device
PDIP,
SOIC
18
20
18
20
dsPIC33FJ06GS001
dsPIC33FJ06GS101A
6
6
256
256
8
8
2
2
0
0
0
1
0
1
0
1
2x2
2x2
2
0
3
3
0
0
0
0
0
1
1
1
1
1
2
3
6
6
13
13
SSOP
PDIP,
SOIC
SSOP
SPDIP,
SOIC,
SSOP,
QFN-S
28
36
28
36
28
36
dsPIC33FJ06GS102A
dsPIC33FJ06GS202A
dsPIC33FJ09GS302
6
6
9
256 16
1K 16
1K 16
2
2
2
0
1
1
1
1
1
1
1
1
1
1
1
2x2
2x2
3x2
0
2
2
3
3
3
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
3
3
3
6
6
8
21
21
21
VTLA
SPDIP,
SOIC,
SSOP,
QFN-S
VTLA
SPDIP,
SOIC,
SSOP,
QFN-S
VTLA
Note 1:
2:
INT0 is not remappable.
The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices.
DS75018C-page 2
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams
= Pins are up to 5V tolerant
18-Pin SOIC, PDIP
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
1
2
3
4
5
18
17
16
15
14
VDD
VSS
PWM1L/RA3
PWM1H/RA4
VCAP
AN2/CMP1C/CMP2A/RA2
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
(1)
OSC1/CLKI/AN6/RP1 /CN1/RB1
VSS
6
7
8
13
12
11
(1)
(1)
OSC2/CLKO/AN7/RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
(1)
(1)
PGED2/TCK/INT0/RP3 /CN3/RB3
PGED1/TDI/SCL1/RP6 /CN6/RB6
(1)
(1)
9
10
PGEC2/TMS/EXTREF/RP4 /CN4/RB4
TDO/RP5 /CN5/RB5
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
1
2
3
4
5
18
17
16
15
14
VDD
VSS
PWM1L/RA3
PWM1H/RA4
VCAP
(1)
AN3/RP0 /CN0/RB0
(1)
OSC1/CLKI/AN6/RP1 /CN1/RB1
VSS
6
7
8
13
12
11
(1)
(1)
OSC2/CLKO/AN7/RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
(1)
(1)
PGED1/TDI/SCL1/RP6 /CN6/RB6
PGED2/TCK/INT0/RP3 /CN3/RB3
(1)
(1)
PGEC2/TMS/RP4 /CN4/RB4
9
10
TDO/RP5 /CN5/RB5
= Pins are up to 5V tolerant
20-Pin SSOP
20
19
18
AVDD
MCLR
AN0/CMP1A/RA0
1
2
3
4
5
AVSS
PWM1L/RA3
PWM1H/RA4
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
17
16
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
VDD
VSS
VCAP
15
6
7
8
(1)
14
13
OSCI/CLKI/AN6/RP1 /CN1/RB1
VSS
(1)
(1)
OSCO/CLKO/AN7/RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
(1)
12
11
(1)
9
PGED2/TCK/INT0/RP3 /CN3/RB3
PGED1/TDI/SCL1/RP6 /CN6/RB6
(1)
(1)
TDO/RP5 /CN5/RB5
10
PGEC2/TMS/EXTREF/RP4 /CN4/RB4
AVDD
20
19
18
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
1
2
3
4
5
AVSS
PWM1L/RA3
PWM1H/RA4
17
16
(1)
AN3/RP0 /CN0/RB0
VDD
VSS
VCAP
15
6
7
8
(1)
14
13
OSCI/CLKI/AN6/RP1 /CN1/RB1
VSS
(1)
(1)
OSCO/CLKO/AN7/RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
(1)
12
11
(1)
PGED2/TCK/INT0/RP3 /CN3/RB3
9
PGED1/TDI/SCL1/RP6 /CN6/RB6
(1)
(1)
TDO/RP5 /CN5/RB5
10
PGEC2/TMS/RP4 /CN4/RB4
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2011-2012 Microchip Technology Inc.
DS75018C-page 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
28-Pin SOIC, SPDIP, SSOP
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14 /CN14/RB14
PWM2H/RP13 /CN13/RB13
TCK/RP12 /CN12/RB12
(1)
(1)
AN3/RP0 /CN0/RB0
AN4/RP9 /CN9/RB9
AN5/RP10 /CN10/RB10
(1)
(1)
(1)
(1)
(1)
TMS/RP11 /CN11/RB11
VSS
(1)
OSC1/CLKI/RP1 /CN1/RB1
OSC2/CLKO/RP2 /CN2/RB2
PGED2/INT0/RP3 /CN3/RB3
9
VCAP
VSS
(1)
10
11
12
13
14
(1)
(1)
PGEC1/SDA1/RP7 /CN7/RB7
PGED1/TDI/1SCL1/RP6 /CN6/RB6
TDO/RP5 /CN5/RB5
PGEC3/RP15 /CN15/RB15
(1)
(1)
PGEC2/RP4 /CN4/RB4
(1)
VDD
(1)
(1)
PGED3/RP8 /CN8/RB8
= Pins are up to 5V tolerant
28-Pin SPDIP, SOIC, SSOP
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14 /CN14/RB14
PWM2H/RP13 /CN13/RB13
TCK/RP12 /CN12/RB12
TMS/RP11 /CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7 /CN7/RB7
PGED1/TDI/SCL1/RP6 /CN6/RB6
AN2/CMP1C/CMP2A/RA2
(1)
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
(1)
(1)
AN4/CMP2C/RP9 /CN9/RB9
(1)
(1)
AN5/CMP2D/RP10 /CN10/RB10
(1)
VSS
(1)
OSC1/CLKI/RP1 /CN1/RB1
OSC2/CLKO/RP2 /CN2/RB2
PGED2/DACOUT/INT0/RP3 /CN3/RB3
9
(1)
10
11
12
13
14
(1)
(1)
(1)
(1)
PGEC2/EXTREF/RP4 /CN4/RB4
(1)
VDD
TDO/RP5 /CN5/RB5
PGEC3/RP15 /CN15/RB15
(1)
(1)
PGED3/RP8 /CN8/RB8
28-Pin SPDIP, SOIC, SSOP
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
MCLR
AN0/CMP1A/RA0
AN1/CMP1B1/RA1
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14 /CN14/RB14
PWM2H/RP13 /CN13/RB13
TCK/RP12 /CN12/RB12
AN2/CMP1C/CMP2A/RA2
(1)
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
(1)
(1)
AN4/ISRC4/CMP2C/RP9 /CN9/RB9
(1)
(1)
AN5/ISRC3/CMP2D/RP10 /CN10/RB10
(1)
TMS/RP11 /CN11/RB11
VSS
(1)
9
OSC1/CLKI/AN6/ISRC2/RP1 /CN1/RB1
OSC2/CLKO/AN7/ISRC1/RP2 /CN2/RB2
PGED2/DACOUT/INT0/RP3 /CN3/RB3
VCAP
VSS
(1)
10
11
12
13
14
(1)
(1)
PGEC1/SDA1/RP7 /CN7/RB7
PGED1/TDI/SCL1/RP6 /CN6/RB6
TDO/RP5 /CN5/RB5
PGEC3/RP15/CN15/RB15
(1)
(1)
PGEC2/EXTREF/RP4 /CN4/RB4
(1)
VDD
(1)
PGED3/RP8 /CN8/RB8
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
DS75018C-page 4
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
(1)
AN2/RA2
1
2
3
4
5
6
7
21
PWM2L/RP14 /CN14/RB14
(1)
(1)
AN3/RP0 /CN0/RB0
AN4/RP9 /CN9/RB9
20 PWM2H/RP13 /CN13/RB13
(1)
(1)
19 TCK/RP12 /CN12/RB12
(1)
(1)
dsPIC33FJ06GS102A
TMS/RP11 /CN11/RB11
AN5/RP10 /CN10/RB10
18
17
16
15
VSS
VCAP
VSS
(1)
OSC1/CLKI/RP1 /CN1/RB1
(1)
(1)
PGEC1/SDA1/RP7 /CN7/RB7
OSC2/CLKO/RP2 /CN2/RB2
8
9 10 11 12 13 14
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
(1)
AN2/CMP1C/CMP2A/RA2
1
2
3
4
5
6
7
21 PWM2L/RP14 /CN14/RB14
(1)
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
PWM2H/RP13 /CN13/RB13
20
(1)
(1)
AN4/CMP2C/RP9 /CN9/RB9
19 TCK/RP12 /CN12/RB12
(1)
(1)
AN5/CMP2D/RP10 /CN10/RB10
18 TMS/RP11 /CN11/RB11
dsPIC33FJ06GS202A
VSS
17
16
15
VCAP
VSS
(1)
OSC1/CLKI/RP1 /CN1/RB1
(1)
(1)
OSC2/CLKO/RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
8
9 10 11 12 13 14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
(1)
AN2/CMP1C/CMP2A/RA2
1
2
3
4
5
6
7
21
PWM2L/RP14 /CN14/RB14
(1)
(1)
AN3/CMP1D/CMP2B/RP0 /CN0/RB0
20 PWM2H/RP13 /CN13/RB13
(1)
(1)
AN4/ISRC4/CMP2C/RP9 /CN9/RB9
19
18
17
16
15
TCK/RP12 /CN12/RB12
(1)
(1)
AN5/ISRC3/CMP2D/RP10 /CN10/RB10
dsPIC33FJ09GS302
TMS/RP11 /CN11/RB11
VSS
VCAP
VSS
(1)
OSC1/CLKI/AN6/ISRC2/RP1 /CN1/RB1
(1)
(1)
OSC2/CLKO/AN7/ISRC1//RP2 /CN2/RB2
PGEC1/SDA1/RP7 /CN7/RB7
8
9 10 11 12 13 14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS75018C-page 6
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
= Pins are up to 5V tolerant
(1)
36
1
34 33 32 31 30 29 28 27
26
35
PWM2L/RP14 /CN14/RB14
(1)
(1)
AN4/RP9 /CN9/RB9
PWM2H/RP13 /CN13/RB13
(1)
(1)
2
3
4
5
6
7
8
9
25
24
AN5/RP10 /CN10/RB10
TCK/RP12 /CN12/RB12
(1)
NC
NC
TMS/RP11 /CN11/RB11
23
VDD
dsPIC33FJ06GS102A
VDD
22
VCAP
VSS
21 VSS
(1)
OSCI/CLKI/RP1 /CN1/RB1
N/C
PGEC1/SDA1/RP7 /CN7/RB7
20
19
(1)
(1)
OSCO/CLKO/RP2 /CN2/RB2
NC
18
10 11 12 13 14 15 16 17
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 7
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
= Pins are up to 5V tolerant
(1)
36
1
34 33 32 31 30 29 28 27
26
35
PWM2L/RP14 /CN14/RB14
(1)
(1)
AN4/CMP2C/RP9 /CN9/RB9
PWM2H/RP13 /CN13/RB13
(1)
(1)
2
3
4
5
6
7
8
9
25
24
AN5/CMP2D/RP10 /CN10/RB10
TCK/RP12 /CN12/RB12
(1)
NC
NC
TMS/RP11 /CN11/RB11
23
VDD
VCAP
VSS
dsPIC33FJ06GS202A
VDD
VSS
22
21
(1)
OSCI/CLKI/RP1 /CN1/RB1
20 N/C
(1)
(1)
OSCO/CLKO/RP2 /CN2/RB2
19
PGEC1/SDA1/RP7 /CN7/RB7
18
10 11 12 13 14 15 16 17
NC
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
DS75018C-page 8
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
= Pins are up to 5V tolerant
(1)
36
1
34 33 32 31 30 29 28 27
26
35
PWM2L/RP14 /CN14/RB14
(1)
(1)
AN4/ISRC4/CMP2C/RP9 /CN9/RB9
PWM2H/RP13 /CN13/RB13
(1)
(1)
2
3
4
5
6
7
8
9
25
24
AN5/ISRC3/CMP2D/RP10 /CN10/RB10
TCK/RP12 /CN12/RB12
(1)
NC
NC
TMS/RP11 /CN11/RB11
23 VDD
22 VCAP
dsPIC33FJ09GS302
VDD
VSS
VSS
N/C
21
20
(1)
OSCI/CLKI/AN6/ISRC2/RP1 /CN1/RB1
(1)
(1)
OSCO/CLKO/AN7/ISRC1/RP2 /CN2/RB2
19
18
PGEC1/SDA1/RP7 /CN7/RB7
10 11 12 13 14 15 16 17
NC
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 17
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization................................................................................................................................................................. 37
5.0 Flash Program Memory.............................................................................................................................................................. 75
6.0 Resets ....................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 87
8.0 Oscillator Configuration ......................................................................................................................................................... 123
9.0 Power-Saving Features............................................................................................................................................................ 137
10.0 I/O Ports ................................................................................................................................................................................... 145
11.0 Timer1 ...................................................................................................................................................................................... 173
12.0 Timer2 Features....................................................................................................................................................................... 175
13.0 Input Capture............................................................................................................................................................................ 177
14.0 Output Compare....................................................................................................................................................................... 179
15.0 High-Speed PWM..................................................................................................................................................................... 183
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 211
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 219
19.0 High-Speed 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................. 225
20.0 High-Speed Analog Comparator .............................................................................................................................................. 243
21.0 Constant Current Source.......................................................................................................................................................... 249
22.0 Special Features ...................................................................................................................................................................... 251
23.0 Instruction Set Summary.......................................................................................................................................................... 259
24.0 Development Support............................................................................................................................................................... 267
25.0 Electrical Characteristics.......................................................................................................................................................... 271
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 315
27.0 Packaging Information.............................................................................................................................................................. 319
Appendix A: Revision History............................................................................................................................................................. 339
Index ................................................................................................................................................................................................. 341
DS75018C-page 10
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2011-2012 Microchip Technology Inc.
DS75018C-page 11
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered the primary reference for the operation of a
particular module or device feature.
Note: To access the documents listed below,
visit
the
Microchip
web
site
(www.microchip.com).
• Section 1. “Introduction” (DS70197)
• Section 2. “CPU” (DS70204)
• Section 3. “Data Memory” (DS70202)
• Section 4. “Program Memory” (DS70203)
• Section 5. “Flash Programming” (DS70191)
• Section 8. “Reset” (DS70192)
• Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
• Section 10. “I/O Ports” (DS70193)
• Section 11. “Timers” (DS70205)
• Section 12. “Input Capture” (DS70198)
• Section 13. “Output Compare” (DS70209)
• Section 17. “UART” (DS70188)
• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
• Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
• Section 24. “Programming and Diagnostics” (DS70207)
• Section 25. “Device Configuration” (DS70194)
• Section 41. “Interrupts (Part IV)” (DS70300)
• Section 42. “Oscillator (Part IV)” (DS70307)
• Section 43. “High-Speed PWM” (DS70323)
• Section 44. “High-Speed 10-Bit ADC” (DS70321)
• Section 45. “High-Speed Analog Comparator” (DS70296)
DS75018C-page 12
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices contain extensive
1.0
DEVICE OVERVIEW
Note:
This data sheet summarizes the features of
the dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 families of
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit microcontroller (MCU)
architecture.
devices. It is not intended to be
a
Figure 1-1 shows a general block diagram of the core
andperipheralmodulesinthedevices.Table 1-1liststhe
functions of the various pins shown in the pinout
diagrams.
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest “dsPIC33F/PIC24H Family
Reference Manual” sections.
This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
• dsPIC33FJ06GS001
• dsPIC33FJ06GS101A
• dsPIC33FJ06GS102A
• dsPIC33FJ06GS202A
• dsPIC33FJ09GS302
2011-2012 Microchip Technology Inc.
DS75018C-page 13
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 1-1:
dsPIC33FJ06GS001/101A/102A/202AanddsPIC33FJ09GS302BLOCKDIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
16
Data Latch
Data Latch
X RAM
23
PCH PCL
Y RAM
PCU
23
Program Counter
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
16
23
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program
Memory
EA MUX
Data Latch
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
16 x 16
Power-up
Timer
W Register Array
Divide Support
16
Timing
Generation
OSC2/CLKO
OSC1/CLKI
Oscillator
Start-up Timer
Power-on
Reset
FRC/LPRC
Oscillators
16-Bit ALU
Watchdog
Timer
16
Brown-out
Reset
Voltage
Regulator
VCAP
VDD, VSS
MCLR
Constant
Current
Source
PWM
3 x 2
Timer1,2
ADC1
UART1
OC1
I2C1
Analog
Comparator 1, 2
Reference
Clock
SPI1
IC1
CNx
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
DS75018C-page 14
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1:
Pin Name
AN0-AN7
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
Capable
Description
I
I
Analog
No
No
Analog input channels.
CLKI
ST/CMOS
External clock source input. Always associated with OSC1 pin
function.
CLKO
O
—
No
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes. Always associated with OSC2 pin function.
OSC1
OSC2
I
ST/CMOS
—
No
No
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes.
I/O
CN0-CN15
IC1
I
I
ST
ST
No
Change notification inputs. Can be software programmed for
internal weak pull-ups on all inputs.
Yes
Capture Input 1.
OCFA
OC1
I
O
ST
—
Yes
Yes
Compare Fault A input (for Compare Channel 1).
Compare Output 1.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
RA0-RA4
I/O
I/O
I/O
ST
ST
ST
No
No
No
PORTA is a bidirectional I/O port.
PORTB is a bidirectional I/O port.
Remappable I/O pins.
RB0-RB15(1)
RP0-RP15(1)
T1CK
T2CK
I
I
ST
ST
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
U1CTS
U1RTS
U1RX
I
O
I
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
U1TX
O
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
ST
ST
—
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
I/O
ST
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
I/O
I/O
ST
ST
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
TMS
TCK
TDI
I
I
I
TTL
TTL
TTL
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
TDO
O
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
Analog = Analog input
P = Power
PPS = Peripheral Pin Select
I = Input
O = Output
— = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
2011-2012 Microchip Technology Inc.
DS75018C-page 15
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
PPS
Description
Type
Capable
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A.
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
DACOUT
O
O
—
—
No
DAC output voltage.
ACMP1-ACMP2
Yes
DAC trigger to PWM module.
ISRC1(2)
ISRC2(2)
ISRC3(2)
ISRC4(2)
O
O
O
O
—
—
—
—
No
No
No
No
Constant Current Source Output 1.
Constant Current Source Output 2.
Constant Current Source Output 3.
Constant Current Source Output 4.
EXTREF
I
Analog
—
No
External voltage reference input for the reference DACs.
REFCLKO
O
Yes
REFCLKO output signal is a postscaled derivative of the system
clock.
FLT1-FLT8
I
ST
Yes
Fault inputs to PWM module.
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM4L
PWM4H
I
ST
—
—
—
—
—
—
—
Yes
Yes
No
No
No
No
Yes
Yes
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM4 low output.
PWM4 high output.
O
O
O
O
O
O
O
PGED1
PGEC1
I/O
I
ST
ST
No
No
Data I/O pin for programming/debugging Communication Channel 1.
Clock input pin for programming/debugging Communication
Channel 1.
PGED2
PGEC2
I/O
I
ST
ST
No
No
Data I/O pin for programming/debugging Communication Channel 2.
Clock input pin for programming/debugging Communication
Channel 2.
Data I/O pin for programming/debugging Communication Channel 3.
Clock input pin for programming/debugging Communication
Channel 3.
PGED3(1)
PGEC3(1)
I/O
I
ST
ST
No
No
MCLR
AVDD
AVSS
I/P
P
ST
P
No
No
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
Positive supply for analog modules. This pin must be connected
at all times. AVDD is connected to VDD on 18 and 28-pin devices.
P
P
Ground reference for analog modules. AVSS is connected to VSS
on 18 and 28-pin devices.
VDD
VCAP
VSS
P
P
P
—
—
—
No
No
No
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
Analog = Analog input
P = Power
PPS = Peripheral Pin Select
I = Input
O = Output
— = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
DS75018C-page 16
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
CONTROLLERS
Consider the following criteria when using decoupling
capacitors:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible;
for example, 0.1 µF in parallel with 0.001 µF.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ06GS001/101A/
102A/202A and dsPIC33FJ09GS302 family of 16-bit
Digital Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
• All AVDD and AVSS pins, regardless if ADC module
is not used
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• MCLR pin
inductance.
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP™ Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2011-2012 Microchip Technology Inc.
DS75018C-page 17
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.3
Capacitor on Internal Voltage
Regulator (VCAP)
0.1 µF
Ceramic
A low-ESR (<0.5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage regulator
output voltage. The VCAP pin must not be connected to
VDD, and must have a capacitor between 4.7 µF and
10 µF, 16V connected to ground. The type can be
ceramic or tantalum. Refer to Section 25.0 “Electrical
Characteristics” for additional information.
10 µF
Tantalum
VDD
R
R1
MCLR
C
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 22.2
“On-Chip Voltage Regulator” for details.
dsPIC33F
VDD
VSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
• Device Reset
• Device Programming and Debugging
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
Where:
FCNV
(i.e., ADC conversion rate/2)
f = -------------
2
1
f = -----------------------
For example, as shown in Figure 2-2, it is recommended
that the capacitor, C, be isolated from the MCLR pin
during programming and debugging operations.
2 LC
1
2
---------------------
L =
2f C
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
2.2.1
TANK CAPACITORS
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits including DSCs to supply a
local power source. The value of the tank capacitor
should be determined based on the trace resistance
that connects the power supply source to the device,
and the maximum current drawn by the device in the
application. In other words, select the tank capacitor so
that it meets the acceptable voltage sag at the device;
typical values range from 4.7 µF to 47 µF.
VDD
R(1)
R1(2)
MCLR
JP
C
dsPIC33F
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are
met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin VIH and VIL specifications are met.
DS75018C-page 18
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2.5
ICSP™ Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging
purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins, are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and tim-
ing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and Input Voltage High (VIH)
and Input Voltage Low (VIL) pin requirements.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Ensure that the “Communication Channel Select”
(i.e., PGECx/PGEDx pins), programmed into the
device matches the physical connections for the ICSP
to MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on MPLAB ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web site
(www.microchip.com):
Main Oscillator
Guard Ring
13
14
15
16
17
18
19
20
• “Using MPLAB® ICD 3” (poster) (DS51765)
Guard Trace
• “Multi-Tool Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” (DS51616)
• “Using MPLAB® REAL ICE™” (poster) (DS51749)
Secondary
Oscillator
2011-2012 Microchip Technology Inc.
DS75018C-page 19
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
If your application needs to use certain Analog-to-Digital
2.7
Oscillator Value Conditions on
Device Start-up
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the ADPCFG register during initialization of the ADC
module.
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside of this range, the
application must start up in the FRC mode first. The
default PLL settings after a POR, with an oscillator
frequency outside of this range, will violate the device
operating speed.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG register. Automatic
initialization of these registers is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all Analog-to-Digital pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins, and drive the output to logic low.
2.10 Typical Application Connection
Examples
If MPLAB ICD 3 or REAL ICE is selected as a debug-
ger, it automatically initializes all of the Analog-to-Digital
input pins (ANx) as “digital” pins, by setting all bits in the
ADPCFG register.
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-8.
The bits in the registers that correspond to the
Analog-to-Digital pins that are initialized by MPLAB
ICD 3 or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
DS75018C-page 20
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 2-4:
DIGITAL PFC
IPFC
VHV_BUS
|VAC|
k1
k3
VAC
FET
Driver
k2
ADC Channel
ADC Channel
ADC Channel PWM Output
dsPIC33FJ06GS001
FIGURE 2-5:
BOOST CONVERTER IMPLEMENTATION
IPFC
VINPUT
VOUTPUT
k1
k3
FET
Driver
k2
ADC Channel
ADC Channel
ADC
Channel
PWM
Output
dsPIC33FJ06GS001
2011-2012 Microchip Technology Inc.
DS75018C-page 21
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 2-6:
SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
12V Input
5V Output
I5V
FET
Driver
k7
k2
k1
ADC
Channel
Analog
Comp.
ADC
Channel
dsPIC33FJ06GS202A
FIGURE 2-7:
INTERLEAVED PFC
VOUT+
|VAC|
k4
VAC
k3
k1
k2
VOUT-
FET
Driver
FET
Driver
ADC Channel
ADC Channel
PWM ADC
Channel
PWM
ADC
Channel
ADC
Channel
dsPIC33FJ06GS202A
DS75018C-page 22
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 2-8:
PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
Gate 1
VOUT+
VOUT-
S1
S3
Gate 2
VIN-
Gate 4
Gate 5
Gate 5
FET
Driver
k2
k1
Analog
Ground
Gate 1
S1
FET
Driver
PWM
PWM
ADC
PWM
ADC
Channel
Channel
Gate 3
dsPIC33FJ09GS302
FET
Driver
S3
Gate 2
Gate 4
2011-2012 Microchip Technology Inc.
DS75018C-page 23
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 24
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.1
Data Addressing Overview
3.0
CPU
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through
the X memory AGU, which accesses the entire
memory map as one linear data space. Certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y data space
boundary is device-specific.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU Circular Addressing can be used with any of
the MCU class of instructions. The X AGU also supports
Bit-Reversed Addressing to greatly simplify input or
output data reordering for radix-2 FFT algorithms.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The CPU module has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including
significant support for DSP. The CPU has a 24-bit
instruction word with a variable length opcode field. The
Program Counter (PC) is 23 bits wide and addresses up
to 4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
from device to device. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute in
a single cycle, with the exception of instructions that
change the program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DOand
REPEAT instructions, both of which are interruptible at
any point.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, 40-bit ALU, two 40-bit saturating
a
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits, right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MACinstruction and other asso-
ciated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices have sixteen, 16-bit
working registers in the programmer’s model. Each of the
working registers can serve as a Data, Address or
Address Offset register. The sixteenth working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
There are two classes of instruction: MCU and DSP.
These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed
for optimum C compiler efficiency. For most instruc-
tions, the devices are capable of executing a data
(or program data) memory read, a working register
(data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be sup-
ported, allowing A + B = C operations to be executed
in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model is shown in Figure 3-2.
2011-2012 Microchip Technology Inc.
DS75018C-page 25
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The 16/16 and 32/16 divide operations are supported,
3.3
Special MCU Features
both fractional and integer. All divide instructions are
iterative operations. They must be executed within a
REPEAT loop, resulting in a total execution time of
19 instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss of
data.
A 17-bit by 17-bit single-cycle multiplier is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for special
operations, such as (-1.0) x (-1.0).
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
16
16
8
16
Data Latch
Data Latch
X RAM
23
16
PCH PCL
Program Counter
PCU
Y RAM
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
16
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
16 x 16
W Register Array
Divide Support
16
16-Bit ALU
16
To Peripheral Modules
DS75018C-page 26
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 3-2:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD15
AD39
AD31
AD0
DSP
Accumulators
ACCA
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
DOLoop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
RA
N
Z
C
IPL2 IPL1 IPL0
OV
STATUS Register
SRL
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA(1)
R/C-0
SB(1)
R-0
R/C-0
SAB(1,4)
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(3)
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clearable bit
S = Settable bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
OA: Accumulator A Overflow Status bit
1= Accumulator A overflowed
0= Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B overflowed
0= Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulators A or B have overflowed
0= Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4)
1= Accumulators A or B are saturated or have been saturated at some time in the past
0= Neither Accumulator A or B are saturated
DA: DOLoop Active bit
1= DOloop in progress
0= DOloop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when
IPL3 = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1(INTCON1<15>).
4: Clearing this bit will clear SA and SB.
DS75018C-page 28
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation that affects the Z bit has set it at some time in the past
0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when
IPL3 = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1(INTCON1<15>).
4: Clearing this bit will clear SA and SB.
2011-2012 Microchip Technology Inc.
DS75018C-page 29
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
bit 12
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1= DSP engine multiplies are unsigned
0= DSP engine multiplies are signed
bit 11
EDT: Early DOLoop Termination Control bit(1)
1= Terminate executing DOloop at end of current loop iteration
0= No effect
bit 10-8
DL<2:0>: DOLoop Nesting Level Status bits
111= 7 DOloops active
•
•
•
001= 1 DOloop active
000= 0 DOloops active
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SATA: ACCA Saturation Enable bit
1= Accumulator A saturation is enabled
0= Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit
1= Accumulator B saturation is enabled
0= Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data space write saturation is enabled
0= Data space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1= Program space is visible in data space
0= Program space is not visible in data space
RND: Rounding Mode Select bit
1= Biased (conventional) rounding is enabled
0= Unbiased (convergent) rounding is enabled
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode enabled for DSP multiply ops
0= Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS75018C-page 30
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The ALU is 16 bits wide and is capable of addition,
subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU can affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC) Status
bits in the SR register. The C and DC Status bits operate
as Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The DSP engine consists of a high-speed, 17-bit x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices feature a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow is
not possible. However, some MCU ALU and DSP engine
resources can be used concurrently by the same
instruction (for example, ED, EDAC).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The DSP engine can also perform inherent
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUBand
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
Refer to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
• Fractional or Integer DSP Multiply (IF)
The CPU incorporates hardware support for both multipli-
cation and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit divisor division.
• Signed or Unsigned DSP Multiply (US)
• Conventional or Convergent Rounding (RND)
• Automatic Saturation On/Off for ACCA (SATA)
• Automatic Saturation On/Off for ACCB (SATB)
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
• Accumulator Saturation mode Selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
TABLE 3-1:
Instruction
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
CLR
A = 0
Yes
No
ED
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
3.5.2
DIVIDER
EDAC
MAC
No
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
Yes
No
MAC
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
MOVSAC
MPY
No change in A
A = x * y
A = x2
Yes
No
MPY
No
MPY.N
MSC
A = – x * y
No
The quotient for all divide instructions ends up in W0 and
the remainder in W1. 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit
A = A – x * y
Yes
divisor (Wn) and any
W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
2011-2012 Microchip Technology Inc.
DS75018C-page 31
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
S
a
40-Bit Accumulator A
40-Bit Accumulator B
40
t 16
40
Round
Logic
u
r
a
t
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
e
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS75018C-page 32
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• Overflow from bit 39: This is a catastrophic
overflow in which the sign of the accumulator is
destroyed
• Overflow into guard bits, 32 through 39: This is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that controls
accumulator data saturation, if selected. It uses the result
of the adder, the Overflow Status bits described
previously and the SAT<A:B> (CORCON<7:6>) and
ACCSAT (CORCON<4>) mode control bits to determine
when and to what value to saturate.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF)
Six STATUS register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
1.31 product that has a precision of 4.65661 x 10-10
.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed-sign multiply operations.
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data passes
through the adder/subtracter. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic warn-
ing trap when set and the corresponding Overflow Trap
Enable bits (OVATE, OVBTE) in the INTCON1 register
are set (refer to Section 7.0 “Interrupt Controller”).
This allows the user application to take immediate
action, for example, to correct system gain.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destination.
For the ADDand LACinstructions, the data to be accumu-
lated or loaded can be optionally scaled using the barrel
shifter prior to accumulation.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow and thus, indicate that a cata-
strophic overflow has occurred. If the COVTE bit in the
INTCON1 register is set, SA and SB bits will generate
an arithmetic warning trap when saturation is disabled.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented)
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented
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The Overflow and Saturation Status bits can optionally be
viewed in the STATUS Register (SR) as the logical OR of
OA and OB (in bit OAB) and the logical OR of SA and SB
(in bit SAB). Programmers can check one bit in the
STATUS Register to determine if either accumulator has
overflowed, or one bit to determine if either accumulator
has saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
3.6.3.1
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
Conventional rounding zero-extends bit 15 of the accu-
mulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive
9.31 (0x7FFFFFFFFF) or maximally negative
9.31 value (0x8000000000) into the target accumu-
lator. The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides
protection against erroneous data or unexpected
algorithm problems (such as gain calculations).
• If the ACCxL word (bits 0 through 15 of the
accumulator) is between 0x8000 and 0xFFFF
(0x8000 included), ACCxH is incremented
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged
A consequence of this algorithm is that over a
succession of random rounding operations, the value
tends to be biased slightly positive.
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative
1.31 value (0x0080000000) into the target accumu-
lator. The SA or SB bit is set and remains set until
cleared by the user application. When this Satura-
tion mode is in effect, the guard bits are not used,
so the OA, OB or OAB bits are never set.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (bit 16 of the accumulator) of ACCxH is
examined:
• If it is ‘1’, ACCxH is incremented
• If it is ‘0’, ACCxH is not modified
• Bit 39 Catastrophic Overflow:
Bit 39 Overflow Status bit, from the adder, is used
to set the SA or SB bit, which remains set until
cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the
X
bus, subject to data saturation (see
3.6.3
ACCUMULATOR ‘WRITE BACK’
Section 3.6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.‘
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
DS75018C-page 34
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.6.3.2
Data Space Write Saturation
3.6.4
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space write
saturation logic block accepts a 16-bit, 1.15 fractional
value from the round logic block as its input, together with
overflow status from the original source (accumulator)
and the 16-bit round adder. These inputs are combined
and used to select the appropriate 1.15 fractional value
as output to write to data space memory.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
15 for left shifts.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 value, 0x8000
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 35
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 36
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
4.1
Program Address Space
4.0
MEMORY ORGANIZATION
The device program address memory space is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 4.7
“Interfacing Program and Data Memory Spaces”.
Note:
This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70203) in the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the constant current source trim value
and Device ID sections of the configuration memory
space.
The device architecture features separate program and
data memory spaces and buses. This architecture also
allows the direct access to program memory from the
data space during code execution.
The device memory maps are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM MEMORY MAPS FOR dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 DEVICES
dsPIC33FJ06GS001/101A/102A/202A
dsPIC33FJ09GS302
0x000000
0x000000
0x000002
0x000004
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
0x000002
0x000004
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Alternate Vector Table
Alternate Vector Table
User Program
Flash Memory
User Program
Flash Memory
(1784 instructions)
(2808 instructions)
0x000FEE
0x000FF0
0x000FFE
0x001000
0x0017EE
0x0017F0
0x0017FE
0x001800
Configuration
Configuration
Unimplemented
Unimplemented
(Read ‘0’s)
(Read ‘0’s)
0x7FFFFE
0x800000
0x7FFFFE
0x800000
Constant Current
Source Trim Value
Constant Current
Source Trim Value
0x800840
0x800840
Reserved
Reserved
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
DEVID (2)
Reserved
DEVID (2)
Reserved
2011-2012 Microchip Technology Inc.
DS75018C-page 37
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
INTERRUPT AND TRAP VECTORS
All devices reserve the addresses between 0x00000 and
0x000200 for hard-coded program execution vectors. A
hardware Reset vector is provided to redirect code execu-
tion from the default value of the PC on device Reset to
the actual start of code. A GOTO instruction is pro-
grammed by the user application at 0x000000, with the
actual address for the start of code at 0x000002.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (see Figure 4-2).
The devices also have two interrupt vector tables, located
from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF.
These vector tables allow each of the device interrupt
sources to be handled by separate Interrupt Service
Routines (ISRs). A more detailed discussion of the
interrupt vector tables is provided in Section 7.1
“Interrupt Vector Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during the code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS75018C-page 38
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
4.2
Data Address Space
The CPU has a separate, 16-bit wide data memory
space. The data space is accessed using separate
Address Generation Units (AGUs) for read and write
operations. The data memory maps are shown in
Figure 4-3.
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.7.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
All devices implement up to 1 Kbyte of data memory.
Should an EA point to a location outside of this area, an
all-zero word or byte will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the core and
peripheral modules for controlling the operation of the
device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the instruction set supports both word and
byte operations. As a consequence of byte accessibil-
ity, all Effective Address calculations are internally
scaled to step through word-aligned memory. For
example, the core recognizes Post-Modified Register
Indirect Addressing mode [Ws++], which results in a
value of Ws + 1 for byte operations and Ws + 2 for word
operations.
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to the
corresponding device tables and pinout
diagrams for device-specific information.
4.2.4
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Data byte reads will read the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and reg-
isters are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register that matches the byte
address.
2011-2012 Microchip Technology Inc.
DS75018C-page 39
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJ06GS001/101A/102A DEVICES WITH
256 BYTES OF RAM
MSB
Address
LSB
Address
16 bits
MSb
LSb
0x0000
0x0001
2-Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
Y Data RAM (Y)
8-Kbyte
Near Data
Space
0x087F
0x0881
0x087E
0x0880
256-Byte
SRAM Space
0x08FF
0x0901
0x08FE
0x0900
0x1FFE
0x2000
0x1FFF
0x2001
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
DS75018C-page 40
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 4-4:
DATA MEMORY MAP FOR THE dsPIC33FJ09GS302 DEVICE WITH 1 KB RAM
MSB
Address
LSB
Address
16 bits
MSb
LSb
0x0000
0x0001
2-Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
Y Data RAM (Y)
8-Kbyte
Near Data
Space
0x09FF
0x0A01
0x09FE
0x0A00
1-Kbyte
SRAM Space
0x0BFF
0x0C01
0x0BFE
0x0C00
0x1FFE
0x2000
0x1FFF
0x2001
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
2011-2012 Microchip Technology Inc.
DS75018C-page 41
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms,
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, included in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MACclass).
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
DS75018C-page 42
2011-2012 Microchip Technology Inc.
4.3
Special Function Register Maps
TABLE 4-1:
CPU CORE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
0000
xxxx
xxxx
xxxx
00xx
xxxx
00xx
0000
Stack Pointer Limit Register
ACCAL
ACCAL
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
ACCAH
0026 ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39>
ACCAU
0028
002A
ACCBL
ACCBH
002C ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39>
ACCBU
002E
0030
0032
0034
0036
0038
003A
Program Counter Low Word Register
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter High Byte Register
Table Page Address Pointer Register
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
Program Memory Visibility Page Address Pointer Register
Repeat Loop Counter Register
DCOUNT<15:0>
DOSTARTL<15:1>
0
0
C
DOSTARTH 003C
—
—
—
—
—
—
—
DOENDL<15:1>
—
—
—
—
—
DOSTARTH<5:0>
DOENDH
DOENDL
DOENDH
SR
003E
0040
0042
—
—
—
—
—
—
—
—
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL<2:0>
RA
N
OV
Z
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1:
CPU CORE REGISTER MAP (CONTINUED)
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
CORCON
MODCON
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
0044
0046
0048
004A
004C
004E
0050
0052
—
—
—
—
US
—
EDT
DL<2:0>
SATA SATB SATDW ACCSAT IPL3
YWM<3:0>
PSV
RND
IF
0020
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
XMODEN
YMODEN
BWM<3:0>
XS<15:1>
XWM<3:0>
0
1
0
1
XE<15:1>
YS<15:1>
YE<15:1>
BREN
—
XB<14:0>
Disable Interrupts Counter Register
DISICNT
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A
SFR
Addr
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNPU1
0060
0068
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
CN7PUE CN6PUE CN5PUE CN4PUE
CN3PUE CN2PUE CN1PUE CN0PUE
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A, AND dsPIC33FJ09GS302
File
Name Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1 0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
Legend: x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS001 DEVICES ONLY
All
Reset
s
File
Name Addr.
SFR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2EP
—
INT1EP
INT0EP 0000
INT0IF 0000
SI2C1IF 0000
IFS0
0084
0086
008A
008C
008E
—
—
—
—
—
ADIF
—
—
—
T1IF
—
IFS1
—
INT2IF
—
—
INT1IF
CNIF
AC1IF
—
MI2C1IF
IFS3
—
—
PSEMIF
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
IFS4
—
—
—
—
—
—
—
—
—
IFS5
PWM1IF
—
—
—
—
—
—
—
—
JTAGIF
—
IFS6
0090 ADCP1IF ADCP0IF
—
—
AC2IF
—
—
—
—
—
PWM4IF
IFS7
0092
0094
0096
009A
009C
009E
—
—
—
—
—
—
—
—
—
—
—
ADCP6IF
—
—
ADCP3IF
—
IEC0
IEC1
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC3
IPC4
IPC5
IPC7
IPC14
IPC20
IPC23
IPC24
IPC25
IPC27
IPC28
IPC29
ADIE
—
T2IE
—
—
—
INT1IE
—
T1IE
—
—
INT0IE
—
INT2IE
—
—
CNIE
AC1IE
—
MI2C1IE
SI2C1IE 0000
—
—
PSEMIE
—
—
—
—
—
—
0000
0000
0000
0000
0000
4004
4000
0040
4444
0004
0040
0040
0004
0400
0040
4400
4000
0040
0004
0000
—
—
—
—
—
—
—
—
—
PWM1IE
—
—
—
—
—
—
—
—
JTAGIE
—
00A0 ADCP1IE ADCP0IE
—
—
AC2IE
—
—
—
—
—
PWM4IE
00A2
00A4
00A6
00AA
00AC
00AE
00B2
00C0
00CC
00D2
00D4
00D6
00DA
00DC
00DE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP6IE
—
—
—
ADCP3IE
—
T1IP<2:0>
—
—
—
—
—
INT0IP<2:0>
T2IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
-—
—
ADIP<2:0>
—
—
CNIP<2:0>
AC1IP<2:0>
MI2C1IP<2:0>
—
SI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
INT2IP<2:0>
—
—
—
—
—
—
—
—
—
PSEMIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
JTAGIP<2:0>
—
PWM1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWM4IP<2:0>
—
—
AC2IP<2:0>
—
—
—
—
—
—
—
—
—
ADCP1IP<2:0>
ADCP0IP<2:0>
—
—
ADCP3IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP6IP<2:0>
INTTREG 00E0
Legend:
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101A DEVICES ONLY
File
Name
SFR
Addr.
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
INT0EP
INT0IF
SI2C1IF
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
4404
4000
4440
0044
4044
0004
0040
0040
0040
0004
0400
0040
4400
0040
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
U1TXIF
—
—
U1RXIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
—
T2IE
—
—
—
—
—
—
—
—
—
-—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2EP
OC1IF
—
INT1EP
IFS0
0084
0086
008A
008C
008E
—
—
—
—
—
ADIF
SPI1IF SPI1EIF
—
T1IF
—
IFS1
—
INT2IF
—
—
—
—
—
—
—
PSEMIF
—
—
INT1IF
—
CNIF
MI2C1IF
IFS3
—
—
—
—
—
—
—
—
IFS4
—
—
—
—
—
—
—
—
U1EIF
—
IFS5
PWM1IF
—
—
—
—
—
—
—
—
—
JTAGIF
—
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
—
—
—
—
PWM4IF
IFS7
0092
0094
0096
009A
009C
009E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP3IF
—
IEC0
IEC1
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC7
IPC14
IPC16
IPC20
IPC23
IPC24
IPC27
IPC28
ADIE
U1TXIE
—
U1RXIE
—
SPI1IE SPI1EIE
—
—
T1IE
OC1IE
—
—
INT0IE
SI2C1IE
—
—
INT2IE
—
—
—
—
—
—
—
—
INT1IE
—
CNIE
MI2C1IE
—
—
—
—
PSEMIE
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIE
—
PWM1IE
—
—
—
—
—
—
—
—
—
JTAGIE
—
00A0 ADCP1IE ADCP0IE
—
—
—
—
—
—
—
—
PWM4IE
00A2
00A4
00A6
00A8
00AA
00AC
00AE
00B2
00C0
00C4
00CC
00D2
00D4
00DA
00DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP3IE
—
T1IP<2:0>
—
OC1IP<2:0>
—
—
INT0IP<2:0>
T2IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
U1RXIP<2:0>
—
SPI1IP<2:0>
SPI1EIP<2:0>
ADIP<2:0>
MI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1TXIP<2:0>
CNIP<2:0>
—
—
—
SI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
INT2IP<2:0>
PSEMIP<2:0>
U1EIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JTAGIP<2:0>
—
—
PWM1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP0IP<2:0>
—
—
—
PWM4IP<2:0>
—
—
ADCP1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
ADCP3IP<2:0>
INTTREG 00E0
Legend:
ILR<3:0>
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102A DEVICES ONLY
File
Name
SFR
Addr.
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
INT0EP
INT0IF
SI2C1IF
—
0000
0000
0000
0000
0000
0000
0000
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
U1TXIF
—
—
U1RXIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
—
T2IE
—
—
—
—
—
—
—
—
—
-—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1IF
CNIF
—
INT2EP
OC1IF
—
INT1EP
IFS0
IFS1
IFS3
0084
0086
008A
008C
—
—
—
—
ADIF
SPI1IF SPI1EIF
—
—
—
INT2IF
—
—
—
—
—
—
—
PSEMIF
—
—
INT1IF
—
MI2C1IF
—
—
—
—
—
—
—
IFS4
—
—
—
—
—
—
—
—
U1EIF
—
IFS5
008E PWM2IF PWM1IF
0090 ADCP1IF ADCP0IF
—
—
—
—
—
—
—
—
—
JTAGIF
—
IFS6
IFS7
IEC0
IEC1
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC7
IPC14
IPC16
IPC20
IPC23
IPC27
IPC28
—
—
—
—
—
—
—
—
—
0092
0094
0096
009A
009C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP2IF 0000
ADIE
U1TXIE
—
U1RXIE
—
SPI1IE SPI1EIE
—
—
T1IE
CNIE
—
OC1IE
—
—
INT0IE
SI2C1IE
—
0000
0000
0000
0000
0000
0000
INT2IE
—
—
—
—
—
—
—
—
INT1IE
—
MI2C1IE
—
—
—
PSEMIE
—
—
—
—
—
—
—
—
—
—
—
U1EIE
—
009E PWM2IE PWM1IE
00A0 ADCP1IE ADCP0IE
—
—
—
—
—
—
—
—
—
JTAGIE
—
—
—
—
—
—
—
—
—
—
00A2
00A4
00A6
00A8
00AA
00AC
00AE
00B2
00C0
00C4
00CC
00D2
00DA
00DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP2IE 0000
T1IP<2:0>
—
OC1IP<2:0>
—
—
—
INT0IP<2:0>
4404
T2IP<2:0>
—
—
—
—
—
SPI1EIP<2:0>
ADIP<2:0>
MI2C1IP<2:0>
—
—
—
—
—
—
—
—
4000
4440
0044
4044
0004
0040
0040
0040
0004
4400
4400
0004
0000
U1RXIP<2:0>
—
SPI1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1TXIP<2:0>
CNIP<2:0>
—
—
—
SI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
INT2IP<2:0>
PSEMIP<2:0>
U1EIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JTAGIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
PWM2IP<2:0>
—
PWM1IP<2:0>
ADCP0IP<2:0>
—
—
—
—
—
—
—
ADCP1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP2IP<2:0>
INTTREG 00E0
Legend:
ILR<3:0>
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS202A DEVICES ONLY
File
Name
SFR
Addr.
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
INT0EP
INT0IF
SI2C1IF
—
0000
0000
0000
0000
0000
0000
0000
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
U1TXIF
—
—
U1RXIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2EP
OC1IF
AC1IF
—
INT1EP
IFS0
0084
0086
008A
008C
—
—
—
—
ADIF
SPI1IF SPI1EIF
—
—
T1IF
IC1IF
IFS1
—
INT2IF
—
—
—
—
—
—
—
PSEMIF
—
—
INT1IF
CNIF
MI2C1IF
IFS3
—
—
—
—
—
—
—
—
—
IFS4
—
—
—
—
—
—
—
—
—
U1EIF
—
IFS5
008E PWM2IF PWM1IF
0090 ADCP1IF ADCP0IF
—
—
—
—
—
—
—
—
—
—
—
JTAGIF
—
IFS6
—
—
—
—
AC2IF
—
—
—
—
—
IFS7
0092
0094
0096
009A
009C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP6IF
—
—
—
—
ADCP2IF 0000
IEC0
IEC1
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC7
IPC14
IPC16
IPC20
IPC23
IPC25
IPC27
IPC28
IPC29
ADIE
U1TXIE
—
U1RXIE
—
SPI1IE SPI1EIE
T2IE
—
—
T1IE
OC1IE
AC1IE
—
IC1IE
INT0IE
SI2C1IE
—
0000
0000
0000
0000
0000
0000
INT2IE
—
—
—
—
—
—
—
—
INT1IE
—
CNIE
MI2C1IE
—
—
—
PSEMIE
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIE
—
009E PWM2IE PWM1IE
00A0 ADCP1IE ADCP0IE
—
—
—
—
—
—
—
—
—
—
JTAGIE
—
—
—
—
—
AC2IE
—
—
—
—
—
—
00A2
00A4
00A6
00A8
00AA
00AC
00AE
00B2
00C0
00C4
00CC
00D2
00D6
00DA
00DC
00DE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP6IE
—
—
—
ADCP2IE 0000
T1IP<2:0>
—
OC1IP<2:0>
—
IC1IP<2:0>
—
INT0IP<2:0>
4444
T2IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4000
4440
0044
4444
0004
0040
0040
0040
0004
4400
4000
4400
0004
0004
0000
U1RXIP<2:0>
—
SPI1IP<2:0>
—
SPI1EIP<2:0>
—
—
—
—
—
—
—
-—
—
ADIP<2:0>
—
U1TXIP<2:0>
CNIP<2:0>
—
AC1IP<2:0>
MI2C1IP<2:0>
—
SI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
—
INT2IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
PSEMIP<2:0>
—
—
—
—
—
—
U1EIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JTAGIP<2:0>
PWM2IP<2:0>
—
PWM1IP<2:0>
—
—
—
—
—
—
—
—
—
AC2IP<2:0>
—
—
—
—
—
—
—
ADCP1IP<2:0>
—
ADCP0IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP2IP<2:0>
ADCP6IP<2:0>
—
—
INTTREG 00E0
Legend:
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ09GS302 DEVICES ONLY
File
Name
SFR
Addr.
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
INT0EP
INT0IF
SI2C1IF
—
0000
0000
0000
0000
0000
0000
0000
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
U1TXIF
—
—
U1RXIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2EP
OC1IF
AC1IF
—
INT1EP
IC1IF
MI2C1IF
—
IFS0
0084
0086
008A
008C
—
—
—
—
ADIF
SPI1IF SPI1EIF
—
—
T1IF
IFS1
—
INT2IF
—
—
—
—
—
—
—
PSEMIF
—
—
INT1IF
CNIF
IFS3
—
—
—
—
—
—
—
—
IFS4
—
—
—
—
—
—
—
—
—
U1EIF
—
—
IFS5
008E PWM2IF PWM1IF
0090 ADCP1IF ADCP0IF
—
—
—
—
—
—
—
—
—
—
JTAGIF
—
IFS6
—
—
—
—
AC2IF
—
—
—
—
PWM4IF
IFS7
0092
0094
0096
009A
009C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP6IF
—
—
—
ADCP3IF ADCP2IF 0000
IEC0
IEC1
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC7
IPC14
IPC16
IPC20
IPC23
IPC24
IPC25
IPC27
IPC28
IPC29
ADIE
U1TXIE
—
U1RXIE
—
SPI1IE SPI1EIE
T2IE
—
—
T1IE
OC1IE
AC1IE
—
IC1IE
MI2C1IE
—
INT0IE
SI2C1IE
—
0000
0000
0000
0000
0000
0000
INT2IE
—
—
—
—
—
—
—
—
INT1IE
—
CNIE
—
—
—
PSEMIE
—
—
—
—
—
—
—
—
—
—
—
—
U1EIE
—
—
009E PWM2IE PWM1IE
00A0 ADCP1IE ADCP0IE
—
—
—
—
—
—
—
—
—
JTAGIE
—
—
—
—
—
AC2IE
—
—
—
—
—
PWM4IE
00A2
00A4
00A6
00A8
00AA
00AC
00AE
00B2
00C0
00C4
00CC
00D2
00D4
00D6
00DA
00DC
00DE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC1IP<2:0>
—
ADCP6IE
—
—
ADCP3IE ADCP2IE 0000
T1IP<2:0>
—
OC1IP<2:0>
—
—
INT0IP<2:0>
4444
4000
4440
0044
4444
0004
0040
0040
0040
0004
4400
0040
4000
4400
0044
0004
0000
T2IP<2:0>
—
—
—
—
—
—
—
—
-—
—
—
—
—
—
U1RXIP<2:0>
—
SPI1IP<2:0>
—
SPI1EIP<2:0>
ADIP<2:0>
MI2C1IP<2:0>
—
—
—
—
—
—
-—
—
—
-—
—
—
U1TXIP<2:0>
CNIP<2:0>
AC1IP<2:0>
—
SI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
—
INT2IP<2:0>
PSEMIP<2:0>
U1EIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
JTAGIP<2:0>
PWM2IP<2:0>
—
PWM1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWM4IP<2:0>
—
—
—
AC2IP<2:0>
—
—
—
—
—
—
—
—
ADCP1IP<2:0>
—
ADCP0IP<2:0>
-—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCP3IP<2:0>
—
—
—
ADCP2IP<2:0>
ADCP6IP<2:0>
—
—
—
INTTREG 00E0
Legend:
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
TIMER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
0100
0102
0104
0106
010C
0110
Timer1 Register
Period Register 1
0000
FFFF
0000
0000
FFFF
0000
PR1
T1CON
TMR2
PR2
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
—
—
TSYNC
—
TCS
TCS
—
—
Timer2 Register
Period Register 2
T2CON
Legend:
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
SFR
Name
All
Resets
SFR Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1BUF
IC1CON
Legend:
0140
Input Capture 1 Register
xxxx
0000
0142
—
—
ICSIDL
—
—
—
—
—
—
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A
AND dsPIC33FJ09GS302
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1RS
OC1R
0180
0182
0184
Output Compare 1 Secondary Register
Output Compare 1 Register
xxxx
xxxx
0000
OC1CON
Legend:
—
—
OCSIDL
—
—
—
—
—
—
—
—
OCFLT
—
OCM<2:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12: HIGH-SPEED PWM REGISTER MAP
Addr
Offset
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTCON
PTCON2
PTPER
0400
0402
0404
PTEN
—
—
—
PTSIDL
—
SESTAT
—
SEIEN
—
EIPU
—
SYNCPOL SYNCOEN SYNCEN
—
—
SYNCSRC<1:0>
SEVTPS<3:0>
PCLKDIV<2:0>
0000
0000
FFF8
0000
0000
0000
—
—
—
—
—
—
PTPER<15:0>
SEVTCMP 0406
SEVTCMP<15:3>
—
—
—
—
—
MDC
040A
041A CHPCLKEN
MDC<15:0>
—
—
—
—
—
CHOPCLK<6:0>
—
CHOP
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP
Addr
Offset
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CAM
Bit 1
Bit 0
PWMCON1 0420
FLTSTAT
PENH
CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTC<1:0>
—
—
—
XPRES
SWAP
IUE
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
IOCON1
FCLCON1
PDC1
0422
0424
0426
0428
042A
042C
042E
0430
0432
0434
0436
PENL
POLH
POLL
PMOD<1:0>
OVRENH OVRENL OVRDAT<1:0>
FLTDAT<1:0>
CLDAT<1:0>
FLTPOL
OSYNC
IFLTMOD
CLSRC<4:0>
CLPOL CLMOD FLTSRC<4:0>
FLTMOD<1:0>
PDC1<15:0>
PHASE1
DTR1
PHASE1<15:0>
—
—
—
—
DTR1<13:0>
ALTDTR1<13:0>
SDC1<15:0>
ALTDTR1
SDC1
SPHASE1
TRIG1
SPHASE1<15:0>
TRGCMP<15:3>
—
—
—
TRGCON1
STRIG1
TRGDIV<3:0>
—
—
—
—
DTM
—
TRGSTRT<5:0>
STRGCMP<15:3>
PWMCAP1<15:3>
—
—
—
—
—
—
—
—
—
PWMCAP1 0438
LEBCON1
AUXCON1
Legend:
043A
043E
PHR
PHF
PLR
PLF
—
FLTLEBEN CLLEBEN
LEB<6:0>
—
HRPDIS
HRDDIS
—
—
—
—
—
—
CHOPSEL<3:0>
CHOPHEN CHOPLEN 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
Addr
Offset
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTC<1:0>
OVRDAT<1:0>
FLTSRC<4:0>
—
—
—
CAM
XPRES
SWAP
IUE
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
IOCON2
FCLCON2
PDC2
0442
PENH
PENL
POLH
POLL
PMOD<1:0>
OVRENH OVRENL
FLTDAT<1:0>
CLDAT<1:0>
FLTPOL
OSYNC
0444 IFLTMOD
0446
CLSRC<4:0>
CLPOL
CLMOD
FLTMOD<1:0>
PDC2<15:0>
PHASE2<15:0>
PHASE2
DTR2
0448
044A
044C
044E
0450
0452
0454
0456
—
—
—
—
DTR2<13:0>
ALTDTR2
SDC2
ALTDTR2<13:0>
SDC2<15:0>
SPHASE2<15:0>
SPHASE2
TRIG2
TRGCMP<15:3>
—
—
—
TRGCON2
STRIG2
TRGDIV<3:0>
—
—
—
—
DTM
—
TRGSTRT<5:0>
STRGCMP<15:3>
PWMCAP2<15:3>
—
—
—
—
—
—
—
—
—
PWMCAP2 0458
LEBCON2
AUXCON2
Legend:
045A
PHR
PHF
PLR
—
PLF
—
FLTLEBEN CLLEBEN
LEB<6:0>
—
045E HRPDIS HRDDIS
—
—
—
—
—
CHOPSEL<3:0>
CHOPHEN CHOPLEN 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS001, dsPIC33FJ06GS101A AND
dsPIC33FJ09GS302
Addr
Offset
All
Resets
File Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTC<1:0>
—
—
—
CAM
XPRES
SWAP
IUE
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
IOCON4
FCLCON4
PDC4
0482
PENH
PENL
POLH
POLL
PMOD<1:0>
OVRENH OVRENL OVRDAT<1:0>
FLTDAT<1:0>
FLTSRC<4:0>
CLDAT<1:0>
FLTPOL
OSYNC
0484 IFLTMOD
0486
CLSRC<4:0>
CLPOL
CLMOD
FLTMOD<1:0>
PDC4<15:0>
PHASE4<15:0>
PHASE4
DTR4
0488
048A
048C
048E
0490
0492
0494
0496
—
—
—
—
DTR4<13:0>
ALTDTR4<13:0>
SDC4<15:0>
SPHASE4<15:0>
ALTDTR4
SDC4
SPHASE4
TRIG4
TRGCMP<15:3>
—
—
—
TRGCON4
STRIG4
TRGDIV<3:0>
—
—
—
—
DTM
—
TRGSTRT<5:0>
STRGCMP<15:3>
PWMCAP4<15:3>
—
—
—
—
—
—
—
—
—
PWMCAP4 0498
LEBCON4
AUXCON4
Legend:
049A
PHR
PHF
PLR
PLF
—
FLTLEBEN CLLEBEN
LEB<6:0>
—
049E HRPDIS HRDDIS
—
—
—
—
—
—
CHOPSEL<3:0>
CHOPHEN CHOPLEN 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: I2C1 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
0200
0202
0204
0206
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
I2C1STAT 0208 ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
ADD10
IWCOL
I2C1ADD
I2C1MSK 020C
Legend:
020A
—
—
—
—
Address Register
AMSK<9:0>
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17: UART1 REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UEN0
TRMT
WAKE
LPBACK ABAUD
ADDEN
URXINV
RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
0222 UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN UTXBF
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
0224
0226
0228
—
—
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: SPI1 REGISTER MAP FOR dsPIC33FJ06GS101A, dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240
0242
0244
0248
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF SPIRBF 0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMDLY —
0000
0000
0000
FRMEN SPIFSD FRMPOL
—
—
—
—
—
—
SPI1 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: CONSTANT CURRENT SOURCE REGISTER MAP
All
Resets
File Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ISRCCON
0500
ISRCEN
—
—
—
—
OUTSEL<2:0>
—
—
ISRCCAL<5:0>
0000
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON
0300 ADON
—
—
—
ADSIDL SLOWCLK
—
—
—
GSWTRG
—
—
—
FORM
—
EIE
PCFG7
—
ORDER SEQSAMP ASYNCSAMP
—
ADCS<2:0>
0003
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
ADPCFG
ADSTAT
0302
0306
0308
—
—
—
—
—
—
—
—
PCFG6
P6RDY
—
—
—
—
PCFG3 PCFG2 PCFG1 PCFG0
—
P3RDY
—
P1RDY P0RDY
—
ADBASE
ADCPC0
ADCPC1
ADCPC3
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADBASE<15:1>
IRQEN0
030A IRQEN1 PEND1 SWTRG1
030C IRQEN3 PEND3 SWTRG3
TRGSRC1<4:0>
TRGSRC3<4:0>
—
PEND0
—
SWTRG0
—
TRGSRC0<4:0>
—
—
—
—
—
—
0310
0320
0322
0324
0326
—
—
—
—
—
—
—
IRQEN6
PEND6
SWTRG6
TRGSRC6<4:0>
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 12
ADC Data Buffer 13
ADCBUF6 032C
ADCBUF7 032E
ADCBUF12 0338
ADCBUF13 033A
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-21: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102A AND dsPIC33FJ06GS202A
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON
0300 ADON
—
—
—
ADSIDL SLOWCLK
—
—
—
GSWTRG
—
—
—
FORM
—
EIE
—
ORDER SEQSAMP ASYNCSAMP
—
ADCS<2:0>
0003
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
ADPCFG
ADSTAT
0302
0306
0308
—
—
—
—
—
—
—
—
—
PCFG5
—
PCFG4
—
PCFG3 PCFG2 PCFG1 PCFG0
—
—
P6RDY
—
P2RDY P1RDY P0RDY
—
ADBASE
ADCPC0
ADCPC1
ADCPC3
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADCBUF4
ADCBUF5
ADBASE<15:1>
IRQEN0
030A IRQEN1 PEND1 SWTRG1
TRGSRC1<4:0>
PEND0
PEND2
PEND6
SWTRG0
SWTRG2
SWTRG6
TRGSRC0<4:0>
TRGSRC2<4:0>
TRGSRC6<4:0>
030C
0310
0320
0322
0324
0326
0328
032A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IRQEN2
IRQEN6
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 12
ADC Data Buffer 13
ADCBUF12 0338
ADCBUF13 033A
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ09GS302
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON
0300 ADON
—
—
—
ADSIDL SLOWCLK
—
—
—
GSWTRG
—
—
—
FORM
—
EIE
PCFG7
—
ORDER SEQSAMP ASYNCSAMP
—
ADCS<2:0>
0003
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
ADPCFG
ADSTAT
0302
0306
0308
—
—
—
—
—
—
—
—
PCFG6
P6RDY
PCFG5
—
PCFG4
—
PCFG3 PCFG2 PCFG1 PCFG0
P3RDY P2RDY P1RDY P0RDY
—
—
ADBASE
ADCPC0
ADCPC1
ADCPC3
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADCBUF4
ADCBUF5
ADBASE<15:1>
IRQEN0
030A IRQEN1 PEND1 SWTRG1
030C IRQEN3 PEND3 SWTRG3
TRGSRC1<4:0>
TRGSRC3<4:0>
—
PEND0
PEND2
PEND6
SWTRG0
SWTRG2
SWTRG6
TRGSRC0<4:0>
IRQEN2
IRQEN6
TRGSRC2<4:0>
0310
0320
0322
0324
0326
0328
032A
—
—
—
—
—
—
—
TRGSRC6<4:0>
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 12
ADC Data Buffer 13
ADCBUF6 032C
ADCBUF7 032E
ADCBUF12 0338
ADCBUF13 033A
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-23: ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS001, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
All
Resets
File Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CMPCON1
CMPDAC1
CMPCON2
CMPDAC2
0540
0542
0544
0546
CMPON
—
—
—
—
—
CMPSIDL
—
HYSSEL<1:0>
FLTREN FCLKSEL DACOE
INSEL<1:0>
INSEL<1:0>
EXTREF HYSPOL CMPSTAT HGAIN CMPPOL RANGE
0000
0000
0000
0000
—
—
—
CMREF<9:0>
(1)
CMPON
—
CMPSIDL
—
HYSSEL<1:0>
FLTREN FCLKSEL DACOE
—
EXTREF HYSPOL CMPSTAT HGAIN CMPPOL RANGE
CMREF<9:0>
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This bit is not available in the dsPIC33FJ06GS001 device.
TABLE 4-24: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS001
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
RPINR1
RPINR2
RPINR3
RPINR29
RPINR30
RPINR31
RPINR32
RPINR33
RPINR34
Legend:
0680
0682
0684
0686
06BA
06BC
06BE
06C0
06C2
06C4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3F00
003F
3F00
003F
3F00
3F3F
3F3F
3F3F
3F3F
003F
—
—
—
—
—
—
—
—
—
—
INT2R<5:0>
T1CKR<5:0>
—
—
—
—
—
—
—
—
—
—
—
T2CKR<5:0>
FLT1R<5:0>
FLT3R<5:0>
FLT5R<5:0>
FLT7R<5:0>
—
—
FLT2R<5:0>
FLT4R<5:0>
FLT6R<5:0>
FLT8R<5:0>
SYNCI2R<5:0>
SYNCI1R<5:0>
—
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS101A AND dsPIC33FJ06GS102A
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
0680
0682
0684
0686
0696
06A4
06A8
06AA
06BA
06BC
06BE
06C0
06C2
06C4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3F00
003F
3F00
003F
003F
3F3F
3F3F
003F
3F00
3F3F
3F3F
3F3F
3F3F
003F
RPINR1
—
—
—
—
—
INT2R<5:0>
RPINR2
T1CKR<5:0>
—
—
—
—
—
—
—
RPINR3
—
—
—
—
—
—
—
—
—
—
T2CKR<5:0>
OCFAR<5:0>
U1RXR<5:0>
SDI1R<5:0>
SS1R<5:0>
RPINR11
RPINR18
RPINR20
RPINR21
RPINR29
RPINR30
RPINR31
RPINR32
RPINR33
RPINR34
Legend:
—
U1CTSR<5:0>
SCK1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
FLT1R<5:0>
FLT3R<5:0>
FLT5R<5:0>
FLT7R<5:0>
—
—
—
—
—
—
FLT2R<5:0>
FLT4R<5:0>
FLT6R<5:0>
FLT8R<5:0>
SYNCI2R<5:0>
SYNCI1R<5:0>
—
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-26: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
RPINR1
RPINR2
RPINR3
RPINR7
RPINR11
RPINR18
RPINR20
RPINR21
RPINR29
RPINR30
RPINR31
RPINR32
RPINR33
RPINR34
Legend:
0680
0682
0684
0686
068E
0696
06A4
06A8
06AA
06BA
06BC
06BE
06C0
06C2
06C4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3F00
003F
3F00
003F
003F
003F
3F3F
3F3F
003F
3F00
3F3F
3F3F
3F3F
3F3F
003F
—
—
—
—
—
INT2R<5:0>
T1CKR<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2CKR<5:0>
IC1R<5:0>
—
—
OCFAR<5:0>
U1RXR<5:0>
SDI1R<5:0>
SS1R<5:0>
U1CTSR<5:0>
SCK1R<5:0>
—
—
—
—
—
—
FLT1R<5:0>
FLT3R<5:0>
FLT5R<5:0>
FLT7R<5:0>
—
—
—
—
—
—
FLT2R<5:0>
FLT4R<5:0>
FLT6R<5:0>
FLT8R<5:0>
SYNCI2R<5:0>
SYNCI1R<5:0>
—
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPOR0
RPOR1
RPOR2
RPOR3
RPOR16
RPOR17
Legend:
06D0
06D2
06D4
06D6
06F0
06F2
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<5:0>
0000
0000
0000
0000
0000
0000
RP3R<5:0>
RP5R<5:0>
RP7R<5:0>
RP33R<5:0>
RP35R<5:0>
RP2R<5:0>
RP4R<5:0>
RP6R<5:0>
RP32R<5:0>
RP34R<5:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND
dsPIC33FJ09GS302
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
RPOR16
RPOR17
Legend:
06D0
06D2
06D4
06D6
06D8
06DA
06DC
06DE
06F0
06F2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<5:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
RP3R<5:0>
RP5R<5:0>
RP7R<5:0>
RP9R<5:0>
RP11R<5:0>
RP13R<5:0>
RP15R<5:0>
RP33<5:0>
RP35<5:0>
RP2R<5:0>
RP4R<5:0>
RP6R<5:0>
RP8R<5:0>
RP10R<5:0>
RP12R<5:0>
RP14R<5:0>
RP32<5:0>
RP34<5:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29: PORTA REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
02C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1 TRISA0
001F
xxxx
0000
0000
RA1
LATA1
—
RA0
LATA0
—
LATA4
ODCA4
LATA3
ODCA3
LATA2
—
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-30: PORTB REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C8
02CA
02CC
02CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISB7 TRISB6
TRISB5
RB5
TRISB4
RB4
TRISB3
RB3
TRISB2
RB2
TRISB1 TRISB0
00FF
xxxx
0000
0000
RB7
RB6
RB1
LATB1
—
RB0
LATB0
—
LATB7
LATB6
LATB5
—
LATB4
—
LATB3
—
LATB2
—
ODCB
Legend:
ODCB7 ODCB6
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-31: PORTB REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6
TRISB5
RB5
TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
FFFF
xxxx
0000
0000
02CA
02CC
RB15
RB14
RB13
RB12
RB11
RB10
LATB10
—
RB9
LATB9
—
RB8
RB7
RB6
RB4
LATB4
—
RB3
LATB3
—
RB2
LATB2
—
RB1
LATB1
—
RB0
LATB0
—
LATB15
LATB14
LATB13
LATB12
LATB11
LATB8
LATB7
LATB6
LATB5
—
ODCB
Legend:
02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11
ODCB8 ODCB7 ODCB6
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-32: SYSTEM CONTROL REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
RCON
0740
0742
0744
0746
0748
074C
074E
0750
TRAPR IOPUWR
—
COSC<2:0>
DOZE<2:0>
—
—
—
—
—
CM
VREGS
EXTR
SWR
SWDTEN WDTO
SLEEP
CF
IDLE
—
BOR
—
POR
xxxx
(2)
OSCCON
CLKDIV
PLLFBD
OSCTUN
LFSR
—
NOSC<2:0>
CLKLOCK IOLOCK
PLLPOST<1:0>
LOCK
—
—
OSWEN 0300
3040
ROI
DOZEN
—
FRCDIV<2:0>
PLLPRE<4:0>
—
—
—
—
—
—
—
—
—
—
PLLDIV<8:0>
0030
—
—
—
—
—
—
TUN<5:0>
0000
—
LFSR<14:0>
—
0000
REFOCON
ACLKCON
ROON
—
ROSSLP ROSEL
RODIV<3:0>
APSTSCLR<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
ENAPLL APLLCK SELACLK
—
—
ASRCSEL FRCSEL
Legend:
Note 1:
2:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The RCON register Reset values are dependent on the type of Reset.
The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on type of Reset.
TABLE 4-33: NVM REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
NVMCON
NVMKEY
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
ERASE
—
—
NVMOP<3:0>
0000
NVMKEY<7:0>
0000
Legend:
Note 1:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-34: PMD REGISTER MAP FOR dsPIC33FJ06GS001
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
0770
0774
0776
077A
077C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2MD
—
T1MD
—
CMPMD
—
PWMMD
—
—
I2C1MD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCMD 0000
PMD3
PMD4
PMD6
PMD7
Legend:
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
—
—
0000
0000
0000
0000
—
—
—
PWM4MD
—
—
—
PWM1MD
CMPMD1
—
—
CMPMD2
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-35: PMD REGISTER MAP FOR dsPIC33FJ06GS101A
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
0770
0772
0776
077A
—
—
—
—
—
—
—
—
—
—
—
—
T2MD
—
T1MD
—
—
—
—
—
PWMMD
—
—
I2C1MD
—
—
—
—
U1MD
—
—
—
—
—
SPI1MD
—
—
—
—
—
—
—
—
—
ADCMD 0000
PMD2
PMD4
PMD6
Legend:
—
—
—
—
—
—
OC1MD
0000
0000
0000
—
—
—
—
REFOMD
—
—
—
—
PWM4MD
PWM1MD
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-36: PMD REGISTER MAP FOR dsPIC33FJ06GS102A
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
0770
0772
0776
077A
—
—
—
—
—
—
—
—
—
—
—
—
T2MD
—
T1MD
—
—
—
—
—
PWMMD
—
—
—
I2C1MD
—
—
—
—
U1MD
—
—
—
—
—
SPI1MD
—
—
—
—
—
—
—
—
—
ADCMD 0000
PMD2
PMD4
PMD6
Legend:
—
—
—
—
—
OC1MD
0000
0000
0000
—
—
—
REFOMD
—
—
—
—
—
PWM2MD PWM1MD
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-37: PMD REGISTER MAP FOR dsPIC33FJ06GS202A
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
0770
0772
0774
0776
077A
077C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2MD
—
T1MD
—
—
—
PWMMD
—
IC1MD
—
I2C1MD
—
—
—
—
—
—
U1MD
—
—
—
—
—
—
—
SPI1MD
—
—
—
—
—
—
—
—
—
—
—
—
ADCMD 0000
PMD2
PMD3
PMD4
PMD6
PMD7
Legend:
—
—
—
—
—
—
—
—
—
OC1MD
0000
0000
0000
0000
0000
—
—
CMPMD
—
—
—
REFOMD
—
—
—
—
—
—
—
—
—
—
—
—
PWM2MD PWM1MD
CMP2MD CMP1MD
—
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-38: PMD REGISTER MAP FOR dsPIC33FJ09GS302
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
0770
0772
0774
0776
077A
077C
077E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2MD
—
T1MD
—
—
PWMMD
—
IC1MD
—
I2C1MD
—
—
—
—
—
—
—
U1MD
—
—
—
—
—
—
—
—
SPI1MD
—
—
—
—
—
—
—
—
—
ADCMD 0000
OC1MD 0000
PMD2
PMD3
PMD4
PMD6
PMD7
PMD8
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
CMPMD
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
—
—
PWM4MD
—
—
—
REFOMD
—
—
—
PWM2MD PWM1MD
CMP2MD CMP1MD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCSMD
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
4.3.1
SOFTWARE STACK
4.4
Instruction Addressing Modes
In addition to its use as a working register, the W15
register in the devices is also used as a software Stack
Pointer. The Stack Pointer always points to the first
available free word and grows from lower to higher
addresses. It predecrements for stack pops and post-
increments for stack pushes, as shown in Figure 4-5.
For a PC push during any CALLinstruction, the MSb of
the PC is zero-extended before the push, ensuring that
the MSb is always clear.
The addressing modes shown in Table 4-39 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.4.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x1000 in RAM, initialize the SPLIM with the value
0x0FFE.
4.4.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
Note:
Not all instructions support all of the
addressing modes shown above.
FIGURE 4-5:
CALL STACK FRAME
Individual instructions can support
different subsets of these addressing
modes.
0x0000
15
0
PC<15:0>
000000000
W15 (before CALL)
PC<22:16>
<Free Word>
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
DS75018C-page 66
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 4-39: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the File register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA).
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
4.4.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
4.4.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also referred
to as MACinstructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared by both source and
destination (but typically only used by
one).
Note:
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by move and accumulator instructions:
In summary, the following addressing modes are
supported by the MACclass of instructions:
• Register Direct
• Register Indirect
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-Bit Literal
• Register Indirect Post-modified by 2
• Register Indirect Post-modified by 4
• Register Indirect Post-modified by 6
• Register Indirect with Register Offset (Indexed)
4.4.5
OTHER INSTRUCTIONS
• 16-Bit Literal
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISIinstruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
2011-2012 Microchip Technology Inc.
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4.5.1
START AND END ADDRESS
4.5
Modulo Addressing
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
Modulo Addressing mode is a method used to provide
an automated means to support circular data buffers
using hardware. The objective is to remove the need
for software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Note:
Y
space Modulo Addressing EA
calculations assume word-sized data
(LSb of every EA is always clear).
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.5.2
W ADDRESS REGISTER SELECTION
In general, any particular circular buffer can be
configured to operate in only one direction as there are
certain restrictions on the buffer start address (for
incrementing buffers), or end address (for
decrementing buffers), based upon the direction of the
buffer.
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as
well as a W register field to specify the W Address
registers. The XWM and YWM fields select the
registers that will operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
• If YWM = 15, Y AGU Modulo Addressing is
disabled
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
FIGURE 4-6:
MODULO ADDRESSING OPERATION EXAMPLE
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
Byte
Address
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x1100
MOV
MOV
#0x0000, W0
#0x1110, W1
DO
MOV
AGAIN, #0x31
W0, [W1++]
;fill the 50 buffer locations
;fill the next location
0x1163
AGAIN: INC W0, W0
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 32 words
DS75018C-page 68
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
4.5.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
• Upper boundary addresses for incrementing buffers
• Lower boundary addresses for decrementing buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the Regis-
ter Indirect Addressing mode is ignored. In addition, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
Note:
The modulo corrected Effective Address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (such as
[W7 + W2]) is used, Modulo Addressing
correction is performed but the contents of
the register remain unchanged.
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU; Modulo Addressing will be dis-
abled. However, Modulo Addressing will
continue to function in the X RAGU.
4.6
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.6.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when all of
these conditions are met:
• BWMx bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• BREN bit is set in the XBREV register
• Addressing mode used is Register Indirect with
Pre-increment or Post-increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
2011-2012 Microchip Technology Inc.
DS75018C-page 69
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 4-7:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-40: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
DS75018C-page 70
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
4.7.1
ADDRESSING PROGRAM SPACE
4.7
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The device architecture uses a 24-bit wide program space
and a 16-bit wide data space. The architecture is also a
modified Harvard scheme, meaning that data can also be
present in the program space. To use this data success-
fully, it must be accessed in a way that preserves the
alignment of information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside from normal execution, the device architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
For remapping operations, the 8-bit Program Space
Visibility Register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look ups
from a large table of static data. The application can
only access the least significant word of the program
word.
Table 4-41 and Figure 4-8 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
TABLE 4-41: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
0
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
2011-2012 Microchip Technology Inc.
DS75018C-page 71
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FIGURE 4-8:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.
DS75018C-page 72
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when byte select is ‘1’; the lower
byte is selected when it is ‘0’.
4.7.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDHand TBLWTHaccess the space that
contains the upper data byte.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL
instruction. The data is always ‘0’ when the
upper ‘phantom’ byte is selected (Byte
Select = 1).
Similarly, two table instructions, TBLWTHand TBLWTL,
are used to write individual bytes or words to a program
space address. The details of their operation are
explained in Section 5.0 “Flash Program Memory”.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
• TBLRDL(Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space location
(P<15:0>) to a data address (D<15:0>)
FIGURE 4-9:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
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Although each data space address 0x8000 and higher
maps directly into a corresponding program memory
address (see Figure 4-10), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
4.7.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDLor TBLRDH).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEATloop, the MOVand MOV.Dinstructionsrequire
one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEATloop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
FIGURE 4-10:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
...whilethelower15bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
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pin pairs: PGECx/PGEDx), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
5.0
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
This allows customers to manufacture boards with
unprogrammed devices and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
of the dsPIC33FJ06GS001/101A/
102A/202A and dsPIC33FJ09GS302
families of devices. It is not intended
to be
a comprehensive reference
source. To complement the informa-
tion in this data sheet, refer to
Section 5. “Flash Programming”
(DS70191) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write a single program memory word at
a time, and erase program memory in blocks or ‘pages’
of 512 instructions (1536 bytes) at a time.
5.1
Table Instructions and Flash
Programming
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits<7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
These devices contain internal Flash program memory for
storing and executing application code. The memory is
readable, writable and erasable during normal operation
over the entire VDD range.
Flash memory can be programmed in two ways:
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits<15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
ICSP allows a dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 device to be serially
programmed while in the end application circuit. This is
done with two lines for programming clock and
programming data (one of the alternate programming
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
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For example, if the device is operating at +125°C, the
5.2
RTSP Operation
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 8-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 Flash program memory array is
organized into rows of 64 instructions or 192 bytes. RTSP
allows the user application to erase a page of mem-
ory, which consists of eight rows (512 instructions) at
a time, and to program one row or one word at a time.
Table 25-12 shows typical erase and programming times.
The 8-row erase pages and single row write rows are
edge-aligned from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
EQUATION 5-2:
MINIMUM PAGE
ERASE TIME
168517 Cycles
----------------------------------------------------------------------------------------------
= 21.85ms
TRW
=
7.37 MHz 1 + 0.05 1 – 0.00375
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM PAGE
ERASE TIME
168517 Cycles
---------------------------------------------------------------------------------------------
= 24.16ms
TRW
=
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
7.37 MHz 1 – 0.05 1 – 0.00375
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are writ-
ten. A programming cycle is required for programming
each row.
5.4
Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
The programming time depends on the FRC accuracy
(see Table 25-19) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 25-12).
EQUATION 5-1:
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------
7.37 MHz FRC Accuracy% FRC Tuning%
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
5.5
Flash Memory Control Registers
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0
WR(1)
R/W-0
WREN(1)
R/W-0
WRERR(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-0
ERASE(1)
U-0
—
U-0
—
R/W-0
R/W-0
NVMOP<3:0>(1,2)
R/W-0
bit 7
Legend:
SO = Settable Only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
WR: Write Control bit(1)
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete. This bit can only be set (not cleared) in software.
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit(1)
1= Enables Flash program/erase operations
0= Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit(1)
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit(1)
1= Performs the erase operation specified by NVMOP<3:0> on the next WR command
0= Performs the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(1,2)
If ERASE = 1:
1111= No operation
1101= Erase general segment
0011= No operation
0010= Memory page erase operation
0001= Reserved
0000= Reserved
If ERASE = 0:
1111= No operation
1101= No operation
0011= Memory word program operation
0010= No operation
0001= Reserved
0000= Reserved
Note 1: These bits can only be reset on a Power-on Reset (POR).
2: All other combinations of NVMOP<3:0> are unimplemented.
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REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY<7:0>: Key Register bits (write-only)
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A simplified block diagram of the Reset module is
shown in Figure 6-1.
6.0
RESETS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70192) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this data sheet for
register Reset states.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A POR clears all the bits (except for the POR
(RCON<0> bit) that are set. The user application can
set or clear any bit, at any time, during code execution.
The RCON bits only serve as status bits. Setting a
particular Reset status bit in software does not cause a
device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• POR: Power-on Reset
• BOR: Brown-out Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
• MCLR: Master Clear Pin Reset
• SWR: Software RESETInstruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
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6.1
Reset Control Register
(1)
REGISTER 6-1:
R/W-0
RCON: RESET CONTROL REGISTER
R/W-0
U-0
—
U-0
—
U-0
U-0
—
R/W-0
CM
R/W-0
TRAPR
IOPUWR
—
VREGS
bit 15
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A Configuration Mismatch Reset has occurred
0= A Configuration Mismatch Reset has NOT occurred
bit 8
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
bit 7
bit 6
EXTR: External Reset Pin (MCLR) bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset Flag (Instruction) bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
bit 5
bit 4
bit 3
bit 2
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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(1)
REGISTER 6-1:
RCON: RESET CONTROL REGISTER (CONTINUED)
bit 1
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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A warm Reset is the result of all the other Reset
6.2
System Reset
sources, including the RESET instruction. On warm
Reset, the device will continue to operate from the
current clock source, as indicated by the Current
Oscillator Selection bits (COSC<2:0>) in the Oscillator
Control register (OSCCON<14:12>).
There are two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC Configuration bits in the FOSC Configuration
register select the device clock source.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is provided in Figure 6-2.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator
Oscillator
Start-up Timer
Oscillator Mode
PLL Lock Time
Total Delay
Start-up Delay
(1)
(1)
FRC, FRCDIV16, FRCDIVN
TOSCD
—
—
—
TOSCD
(1)
(3)
(1,3)
FRCPLL
XT
TOSCD
TLOCK
TOSCD + TLOCK
(1)
(2)
(1,2)
(1,2)
TOSCD
TOST
—
—
—
TOSCD + TOST
TOSCD + TOST
—
(1)
(2)
HS
TOSCD
TOST
EC
—
—
(1)
(2)
(3)
(1,2,3)
XTPLL
HSPLL
ECPLL
LPRC
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
TOSCD + TOST + TLOCK
(1)
(2)
(3)
(1,2,3)
TOSCD
TOST
TLOCK
(3)
(3)
—
—
—
TLOCK
TLOCK
(1)
(1)
TOSCD
—
TOSCD
Note 1: TOSCD = Oscillator start-up delay (1.1 s max. for FRC, 70 s max. for LPRC). Crystal oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: TOST = Oscillator Start-up Timer (OST) delay (1024 oscillator clock period). For example, TOST = 102.4 s
for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.
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FIGURE 6-2:
SYSTEM RESET TIMING
VBOR
VPOR
VDD
TPOR
1
POR
BOR
TBOR
2
3
TPWRT
SYSRST
4
Oscillator Clock
TOSCD
TOST
TLOCK
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay, TPOR, has elapsed.
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the
delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable.
3: PWRT Timer: The programmable Power-up Timer continues to hold the processor in Reset for a specific period of time (TPWRT)
after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed oper-
ation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start
generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to
Section 8.0 “Oscillator Configuration” for more information.
5: When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay,
TFSCM, has elapsed.
TABLE 6-2:
OSCILLATOR PARAMETERS
Note:
When the device exits the Reset con-
dition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
Symbol
Parameter
Value
VPOR
TPOR
VBOR
TBOR
POR threshold
1.8V nominal
POR extension time 30 s maximum
BOR threshold 2.65V nominal
BOR extension time 100 s maximum
TPWRT Programmable
Power-up Time delay
0-128 ms nominal
operating
specification.
parameters
within
the
TFSCM
Fail-Safe Clock Mon- 900 s maximum
itor delay
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6.3
Power-on Reset (POR)
6.4
Brown-out Reset (BOR) and
Power-up Timer (PWRT)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay, TPOR,
has elapsed. The delay, TPOR, ensures the internal
device bias circuits become stable.
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses the
VBOR threshold and the delay, TBOR, has elapsed. The
delay, TBOR, ensures the voltage regulator output
becomes stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 25.0 “Electrical Characteristics” for details.
The BOR status bit in the Reset Control (RCON<1>)
register is set to indicate the Brown-out Reset.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
The device will not run at full speed after a BOR, as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides a Power-up Time Delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD Dips Before PWRT Expires
VDD
VBOR
TBOR + TPWRT
SYSRST
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6.5
External Reset (EXTR)
6.8
Trap Conflict Reset
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 25.0 “Electrical Characteristics” for
minimum pulse width specifications. The external
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
If a lower priority hard trap occurs, while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of
Priority Level 13 through Level 15, inclusive. The
address error (Level 13) and oscillator error (Level 14)
traps fall into this category.
The Trap Reset (TRAPR) flag in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
6.5.1
EXTERNAL SUPERVISORY
CIRCUIT
6.9
Illegal Condition Device Reset
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of the system is reset.
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
6.5.2
INTERNAL SUPERVISORY CIRCUIT
The illegal opcode or Uninitialized W Access Reset
(IOPUWR) flag in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
When using the internal power supervisory circuit to
reset the device, the external Reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.9.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
6.6
Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will still remain. SYSRST is
released at the next instruction cycle and the Reset
vector fetch will commence.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
The Software Reset (SWR) flag (instruction) in the
Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.9.2
UNINITIALIZED W REGISTER
RESET
Any attempt to use the uninitialized W register as an
Address Pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.7
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog Timer time-out occurs, the
device will asynchronously assert SYSRST. The clock
source will remain unchanged. A WDT time-out during
Sleep or Idle mode will wake-up the processor, but will
not reset the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Timer Reset. Refer to Section 22.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
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Table 6-3 provides a summary of the Reset flag bit
operation.
6.10 Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value, after a
device Reset, will be meaningful.
TABLE 6-3:
Flag Bit
RESET FLAG BIT OPERATION
Set by:
Cleared by:
TRAPR (RCON<15>)
IOPWR (RCON<14>)
Trap conflict event
POR, BOR
POR, BOR
Illegal opcode or uninitialized W register
access or Security Reset
CM (RCON<9>)
Configuration Mismatch
MCLR Reset
POR, BOR
POR
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
RESETinstruction
WDT time-out
POR, BOR
PWRSAVinstruction, CLRWDTinstruction,
POR, BOR
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #SLEEPinstruction
PWRSAV #IDLEinstruction
POR, BOR
POR, BOR
POR, BOR
—
—
POR
Note: All Reset flag bits can be set or cleared by user software.
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Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 will take priority over interrupts at any
other vector address.
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 41. “Interrupts
(Part IV)” (DS70300) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
The devices implement up to 28 unique interrupts and
four non-maskable traps. These are summarized in
Table 7-1.
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The interrupt controller reduces the numerous peripheral
interrupt request signals to a single interrupt request
signal to the CPU. The controller has the following
features:
The AIVT supports debugging by providing a means to
switch between an application and
a
support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
• Up to eight processor exceptions and
software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process. A
device clears its registers in response to a Reset, which
forces the PC to zero. The digital signal controller then
begins program execution at location, 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors, consisting of
eight non-maskable trap vectors, plus up to 118 sources
of interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
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FIGURE 7-1:
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 INTERRUPT
VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
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TABLE 7-1:
Vector
INTERRUPT VECTORS
Interrupt
IVT Address
AIVT Address
Interrupt Source
Number Request (IQR)
Highest Natural Order Priority
8
9
0
1
0x000014
0x000114
0x000116
0x000118
0x00011A
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer1
0x000016
0x000018
0x00001A
10
2
11
3
12-14
15
4-6
7
0x00001C-0x000020 0x00011C-0x000120 Reserved
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
T2 – Timer2
16
8
Reserved
17
9
SPI1E – SPI1 Error
18
10
11
12
13
14
15
16
17
18
19
20
21-28
29
30-56
57
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Group Convert Done
Reserved
19
20
21
22
23
Reserved
24
SI2C1 – I2C1 Slave Event
MI2C1 – I2C1 Master Event
CMP1 – Analog Comparator 1 Interrupt
CN – Input Change Notification Interrupt
INT1 – External Interrupt 1
25
26
27
28
29-36
37
0x00003E-0x0004C 0x00013E-0x00014C Reserved
0x00004E 0x00014E INT2 – External Interrupt 2
0x000050-0x000084 0x000150-0x000184 Reserved
38-64
65
0x000086
0x000186
PSEM – PWM Special Event Match
Interrupt
66-72
73
58-64
65
0x000088-0x000094 0x000188-0x000194 Reserved
0x000096 0x000196 U1E – UART1 Error Interrupt
0x000098-0x0000B2 0x000198-0x0001B2 Reserved
0x0000B4 0x0001B4 JTAG – Data Ready
0x0000B6-0x0000CE 0x0001B6-0x0001CE Reserved
74-87
88
66-79
80
89-101
102
81-93
94
0x0000D0
0x0000D2
0x0000D4
0x0000D6
0x0001D0
0x0001D2
0x0001D4
0x0001D6
PWM1 – PWM1 Interrupt
PWM2 – PWM2 Interrupt
Reserved
103
95
104
96
105
97
PWM4 – PWM4 Interrupt
106-110
111
98-102
103
104-109
110
0x0000D8-0x0000E0 0x0001D8-0x0001E0 Reserved
0x0000E2 0x00001E2 CMP2 – Analog Comparator 2 Interrupt
0x0000E4-0x0000EE 0x0001E4-0x0001EE Reserved
112-117
118
0x0000F0
0x0000F2
0x0000F4
0x0000F6
0x0000F8
0x0000FA
0x0000FC
0x0000FE
0x0001F0
0x0001F2
0x0001F4
0x0001F6
0x0001F8
0x0001FA
0x0001FC
0x0001FE
ADC Pair 0 Convert Done
ADC Pair 1 Convert Done
ADC Pair 2 Convert Done
ADC Pair 3 Convert Done
Reserved
119
111
120
112
121
113
122
114
123
115
Reserved
124
116
ADC Pair 6 Convert Done
Reserved
125
117
Lowest Natural Order Priority
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7.3.5
INTTREG
7.3
Interrupt Control and Status
Registers
The INTTREG register contains the associated interrupt
vector number and the new CPU Interrupt Priority Level,
which are latched into the Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt Priority
Level is the priority of the pending interrupt.
The following registers are implemented for the interrupt
controller:
• INTCON1
• INTCON2
• IFSx
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit is found in IEC0<0> and the
INT0IP bits are found in the first position of IPC0
(IPC0<2:0>).
• IECx
• IPCx
• INTTREG
7.3.1
INTCON1 AND INTCON2
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.6
STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
7.3.2
IFSx
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user can
change the current CPU priority level by writing to
the IPL bits.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
• The CORCON register contains the IPL3 bit,
which together with IPL<2:0>, indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
7.3.3
IECx
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
All Interrupt registers are described in Register 7-1
through Register 7-35.
7.3.4
IPCx
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
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(1)
REGISTER 7-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
R/C-0
SAB
R-0
DA
R/W-0
DC
OAB
bit 15
R/W-0(3)
bit 7
Legend:
bit 8
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
C = Clearable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
R = Readable bit
‘1’ = Bit is set
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU Interrupt Priority Level is 7 (15), user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.
3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1.
(1)
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
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REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR
OVBERR
COVAERR COVBERR
OVATE
OVBTE
COVTE
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
MATHERR ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap is disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap is disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B is enabled
0= Trap is disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Divide-by-Zero Error Trap Status bit
1= Math error trap was caused by a divide-by-zero
0= Math error trap was not caused by a divide-by-zero
bit 5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Math Error Trap Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
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REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
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REGISTER 7-4:
R/W-0
INTCON2: INTERRUPT CONTROL REGISTER 2
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ALTIVT
DISI
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Uses alternate vector table
0= Uses standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
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REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
U-0
—
R/W-0
ADIF
R/W-0
U1TXIF(1)
R/W-0
U1RXIF(1)
R/W-0
SPI1IF(1)
R/W-0
SPI1EIF(1)
U-0
—
bit 15
bit 8
R/W-0
T2IF
U-0
—
U-0
—
U-0
—
R/W-0
T1IF
R/W-0
OC1IF(1)
R/W-0
IC1IF(2)
R/W-0
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ADIF: ADC Group Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
bit 10
bit 9
U1TXIF: UART1 Transmitter Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Error Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
bit 7
Unimplemented: Read as ‘0’
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6-4
bit 3
Unimplemented: Read as ‘0’
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit(2)
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Note 1: This bit is not implemented in the dsPIC33FJ06GS001 device.
2: This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 95
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0
—
U-0
—
R/W-0
INT2IF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
R/W-0
AC1IF(1
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-5
bit 4
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
bit 2
bit 1
bit 0
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
AC1IF: Analog Comparator 1 Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
DS75018C-page 96
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-7:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
PSEMIF
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
Unimplemented: Read as ‘0’
PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8-0
Unimplemented: Read as ‘0’
REGISTER 7-8:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U1EIF(1)
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
U1EIF: UART1 Error Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 97
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-9:
R/W-0
PWM2IF(1)
IFS5: INTERRUPT FLAG STATUS REGISTER 5
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PWM1IF
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
JTAGIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
PWM2IF: PWM2 Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
PWM1IF: PWM1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13-1
bit 0
Unimplemented: Read as ‘0’
JTAGIF: JTAG Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
DS75018C-page 98
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ADCP1IF
ADCP0IF
bit 15
bit 8
bit 0
R/W-0
AC2IF(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PWM4IF(2)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13-8
bit 7
Unimplemented: Read as ‘0’
AC2IF: Analog Comparator 2 Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6-2
bit 1
Unimplemented: Read as ‘0’
PWM4IF: PWM4 Interrupt Flag Status bit(2)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 99
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
ADCP6IF
ADCP3IF(1) ADCP2IF(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3-2
bit 1
Unimplemented: Read as ‘0’
ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit(2)
1= Interrupt request has occurred
0= Interrupt request has not occurred
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
DS75018C-page 100
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
ADIE
R/W-0
U1TXIE(1)
R/W-0
U1RXIE(1)
R/W-0
SPI1IE(1)
R/W-0
SPI1EIE(1)
U-0
—
bit 15
bit 8
R/W-0
T2IE
U-0
—
U-0
—
U-0
—
R/W-0
T1IE
R/W-0
OC1IE(1)
R/W-0
IC1IE(2)
R/W-0
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ADIE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12
bit 11
bit 10
bit 9
U1TXIE: UART1 Transmitter Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPI1IE: SPI1 Event Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPI1EIE: SPI1 Event Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8
bit 7
Unimplemented: Read as ‘0’
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6-4
bit 3
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit(2)
1= Interrupt request is enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices.
2: This bit is not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 101
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
INT2IE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CNIE
R/W-0
AC1IE(1)
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12-5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 3
bit 2
bit 1
bit 0
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
AC1IE: Analog Comparator 1 Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
DS75018C-page 102
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
PSEMIE
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
Unimplemented: Read as ‘0’
PSEMIE: PWM Special Event Match Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8-0
Unimplemented: Read as ‘0’
REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U1EIE(1)
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
U1EIE: UART1 Error Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 103
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
R/W-0
PWM2IE(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PWM1IE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
JTAGIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
PWM2IE: PWM2 Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
PWM1IE: PWM1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13-1
bit 0
Unimplemented: Read as ‘0’
JTAGIE: JTAG Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
DS75018C-page 104
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ADCP1IE
ADCP0IE
bit 15
bit 8
bit 0
R/W-0
AC2IE(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PWM4IE(2)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13-8
bit 7
Unimplemented: Read as ‘0
AC2IE: Analog Comparator 2 Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6-2
bit 1
Unimplemented: Read as ‘0’
PWM4IE: PWM4 Interrupt Enable bit(2)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 105
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
ADCP6IE
ADCP3IE(1) ADCP2IE(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 3-2
bit 1
Unimplemented: Read as ‘0’
ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit(2)
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
DS75018C-page 106
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
OC1IP<2:0>(1)
R/W-0
bit 8
R/W-0
bit 0
T1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
IC1IP<2:0>(2)
R/W-0
U-0
—
R/W-1
R/W-0
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits(2)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
2: These bits are not implemented in dsPIC33FJ06GS001/101A/102A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 107
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
T2IP<2:0>
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
DS75018C-page 108
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
U1RXIP<2:0>(1)
R/W-0
U-0
—
R/W-1
R/W-0
SPI1IP<2:0>(1)
R/W-0
bit 8
bit 15
U-0
—
R/W-1
R/W-0
SPI1EIP<2:0>(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 109
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
U1TXIP<2:0>(1)
ADIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
DS75018C-page 110
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AC1IP<2:0>(1)
R/W-0
bit 8
R/W-0
bit 0
CNIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
Note 1: These bits are not implemented in dsPIC33FJ06GS101A/102A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 111
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
INT1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
REGISTER 7-25: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
U-1
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
INT2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS75018C-page 112
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PSEMIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
U1EIP<2:0>(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
U1EIP<2:0>: UART1 Error Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 113
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-28: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
JTAGIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
JTAGIP<2:0>: JTAG Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS75018C-page 114
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-29: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23
U-0
—
R/W-1
R/W-0
PWM2IP(1)
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
PWM1IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
PWM2IP<2:0>: PWM2 Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PWM1IP<2:0>: PWM1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 115
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-30: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
PWM4IP(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
PWM4IP<2:0>: PWM4 Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in dsPIC33FJ06GS102A/202A devices.
DS75018C-page 116
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-31: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0
—
R/W-1
R/W-0
AC2IP<2:0>(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in dsPIC33FJ06GS101A/102A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 117
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-32: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
ADCP1IP<2:0>
ADCP0IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS75018C-page 118
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
ADCP3IP<2:0>(1)
R/W-0
U-0
—
R/W-1
R/W-0
ADCP2IP<2:0>(2)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits(1)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits(2)
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
Note 1: These bits are not implemented in dsPIC33FJ06GS102A/202A devices.
2: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 119
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
ADCP6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS75018C-page 120
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111= Interrupt vector pending is Number 135
•
•
•
0000001= Interrupt vector pending is Number 9
0000000= Interrupt vector pending is Number 8
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
7.4.3
TRAP SERVICE ROUTINE
7.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.1
INITIALIZATION
Complete the following steps to configure an interrupt
source at initialization:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
7.4.4
INTERRUPT DISABLE
The following steps outline the procedure to disable all
user interrupts:
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value, 0xE0 with SRL.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
Note: At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to Priority Level 4.
Note:
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(Level 8-Level 15) cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
4. Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development toolsuite used to develop the
application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
the interrupt that the ISR handles; otherwise, the pro-
gram will re-enter the ISR immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and the old
CPU priority level.
DS75018C-page 122
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The oscillator system provides:
• External and internal oscillator options as clock
8.0 OSCILLATORCONFIGURATION
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 42. “Oscillator
(Part IV)” (DS70307) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
sources
• An on-chip Phase Lock Loop (PLL) to scale the
internal operating frequency to the required system
clock frequency
• An internal FRC oscillator that can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and takes fail-safe measures
• An Oscillator Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
• An auxiliary PLL for ADC and PWM
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1:
OSCILLATOR SYSTEM DIAGRAM
DOZE<2:0>
Primary Oscillator
POSCCLK
OSC1
XT, HS, EC
S2
(2)
R
XTPLL, HSPLL,
ECPLL, FRCPLL
(3)
FCY
S3
(1)
S1/S3
PLL
S1
(1)
FVCO
OSC2
POSCMD<1:0>
(3)
FP
FRCDIVN
FRC
Oscillator
÷ 2
FRCCLK
S7
FOSC
FRCDIV<2:0>
FRCDIV16
FRC
S6
S0
TUN<5:0>
÷ 16
LPRC
LPRC
Oscillator
S5
Reference Clock Generation
POSCCLK
Clock Switch
Reset
Clock Fail
S7
REFCLKO
÷ N
FOSC
WDT, PWRT,
NOSC<2:0> FNOSC<2:0>
RPx
FSCM
ROSEL RODIV<3:0>
Auxiliary Clock Generation
FRCCLK
(1)
FVCO
POSCCLK
(1)
APLL
x16
(1)
To PWM/ADC
ACLK, FADC
÷ N
To LFSR
ASRCSEL
FRCSEL
ENAPLL
SELACLK
APSTSCLR<2:0>
Note 1: See Section 8.1.3 “PLL Configuration” and Section 8.2 “Auxiliary Clock Generation” for configuration restrictions.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this
document, FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is
used in any ratio other than 1:1, which is the default.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
output frequencies for device operation. PLL
configuration is described in Section 8.1.3 “PLL
Configuration”.
8.1
CPU Clocking System
The devices provide six system clock options:
• Fast RC (FRC) Oscillator
The FRC frequency depends on the FRC accuracy
(see Table 25-20) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with Postscaler
8.1.2
SYSTEM CLOCK SELECTION
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
Oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer
to Section 22.1 “Configuration Bits” for further
details.) The initial Oscillator Selection Configuration
bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
8.1.1
SYSTEM CLOCK SOURCES
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
Oscillator
Mode
Select
Configuration
bits,
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC
primary oscillator is the default (unprogrammed)
selection.
The primary oscillator can use one of the following as
its clock source:
• XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
The Configuration bits allow users to choose among
12 different clock modes, shown in Table 8-1.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected), FOSC, is divided by 2
to generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device and speeds up to
40 MHz are supported by the device architecture.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 32 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
The LPRC internal oscIllator runs at a nominal
frequency of 32.768 kHz. It is also used as a reference
clock by the Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
Instruction execution speed or device operating
frequency, FCY, is given by Equation 8-1.
EQUATION 8-1:
DEVICE OPERATING
FREQUENCY
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Lock Loop (PLL) to provide a wide range of
FCY = FOSC/2
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Note
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Low-Power RC Oscillator (LPRC)
Reserved
Internal
Internal
Internal
Reserved
Primary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
xx
xx
xx
xx
10
01
00
10
01
00
xx
xx
111
110
101
100
011
011
011
010
010
010
001
000
1, 2
1
1
—
—
—
1
Primary Oscillator (HS) with PLL (HSPLL)
Primary Oscillator (XT) with PLL (XTPLL)
Primary Oscillator (EC) with PLL (ECPLL)
Primary Oscillator (HS)
—
—
1
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
1
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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• If PLLPOST<1:0> = 00, then N2 = 2. This pro-
vides a FOSC of 160/2 = 80 MHz. The resultant
device operating speed is 80/2 = 40 MIPS.
8.1.3
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
EQUATION 8-3:
XT WITH PLL MODE
EXAMPLE
FOSC
1
2
10000000 * 32
FCY =
=
= 40 MIPS
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2,
3, ... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor, ‘N1’, is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
(
)
2
2 * 2
8.2
Auxiliary Clock Generation
The auxiliary clock generation is used for a peripherals
that need to operate at a frequency unrelated to the
system clock, such as a PWM or ADC.
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The primary oscillator and internal FRC oscillator
sources can be used with an auxiliary PLL to obtain the
auxiliary clock. The auxiliary PLL has a fixed 16x
multiplication factor.
The auxiliary clock has the following configuration
restrictions:
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
• For proper PWM operation, auxiliary clock genera-
tion must be configured for 120 MHz (see
Parameter OS56 in Table 25-18 in Section 25.0
“Electrical Characteristics”). If a slower frequency
is desired, the PWM Input Clock Prescaler (Divider)
Select bits (PCLKDIV<2:0>) should be used.
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’, is given by Equation 8-2.
• To achieve 1.04 ns PWM resolution, the auxiliary
clock must use the 16x auxiliary PLL (APLL). All
other clock sources will have a minimum PWM
resolution of 8 ns.
EQUATION 8-2:
FOSC CALCULATION
M
N1 * N2
FOSC = FIN *
(
)
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be
configured up to a maximum operation of 30 MIPS
or less
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL (see
Equation 8-3).
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
8.3
Reference Clock Generation
The reference clock output logic provides the user with
the ability to output a clock signal based on the system
clock or the crystal oscillator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
FIGURE 8-2: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PLL BLOCK DIAGRAM
FVCO
0.8-8.0 MHz
Here
12.5-80 MHz
Here
100-200 MHz
(1)
(1)
(1)
Here
Source (Crystal, External
Clock or Internal RC)
FOSC
PLLPRE
VCO
PLLPOST
X
PLLDIV
N2
N1
Divide by
2-33
Divide by
2, 4, 8
M
Divide by
2-513
Note 1: This frequency range must be satisfied at all times.
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8.4
Oscillator Control Registers
(1,3)
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
NOSC<2:0>(2)
R/W-y
bit 8
COSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
R/W-0
R-0
U-0
—
R/C-0
CF
U-0
—
U-0
—
R/W-0
IOLOCK
LOCK
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
111= Fast RC Oscillator (FRC) with divide-by-n
110= Fast RC Oscillator (FRC) with divide-by-16
101= Low-Power RC Oscillator (LPRC)
100= Reserved
011= Primary Oscillator (XT, HS, EC) with PLL
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator (FRC) with PLL
000= Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
111= Fast RC Oscillator (FRC) with divide-by-n
110= Fast RC Oscillator (FRC) with divide-by-16
101= Low-Power RC Oscillator (LPRC)
100= Reserved
011= Primary Oscillator (XT, HS, EC) with PLL
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator (FRC) with PLL
000= Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, FCKSM<1:0> (FOSC<7:6>) bits = 0b01):
1= Clock switching is disabled, system clock source is locked
0= Clock switching is enabled, system clock source can be modified by clock switching
bit 6
bit 5
IOLOCK: Peripheral Pin Select Lock bit
1= Peripherial Pin Select is locked, write to Peripheral Pin Select registers is not allowed
0= Peripherial Pin Select is not locked, write to Peripheral Pin Select registers is allowed
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-
ted. This applies to clock switches in either direction. In these instances, the application must switch to
FRC mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).
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(1,3)
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
(CONTINUED)
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
bit 2-1
bit 0
Unimplemented: Read as ‘0’
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-
ted. This applies to clock switches in either direction. In these instances, the application must switch to
FRC mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).
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(2)
REGISTER 8-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
111= FCY/128
110= FCY/64
101= FCY/32
100= FCY/16
011= FCY/8 (default)
010= FCY/4
001= FCY/2
000= FCY/1
bit 11
DOZEN: Doze Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio is forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111= FRC divide-by-256
110= FRC divide-by-64
101= FRC divide-by-32
100= FRC divide-by-16
011= FRC divide-by-8
010= FRC divide-by-4
001= FRC divide-by-2
000= FRC divide-by-1 (default)
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11= Output/8
10= Reserved
01= Output/4 (default)
00= Output/2
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
11111= Input/33
•
•
•
00001= Input/3
00000= Input/2 (default)
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: This register is reset only on a Power-on Reset (POR).
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(1)
REGISTER 8-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PLLDIV8
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111= 513
•
•
•
000110000= 50 (default)
•
•
•
000000010= 4
000000001= 3
000000000= 2
Note 1: This register is reset only on a Power-on Reset (POR).
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(2)
REGISTER 8-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Center frequency + 11.625% (8.23 MHz)
011110= Center frequency + 11.25% (8.20 MHz)
•
•
•
000001= Center frequency + 0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency – 0.375% (7.345 MHz)
•
•
•
100001= Center frequency – 11.625% (6.52 MHz)
100000= Center frequency – 12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
2: This register is reset only on a Power-on Reset (POR).
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(1)
REGISTER 8-5:
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0
R-0
R/W-1
U-0
—
U-0
—
R/W-1
R/W-1
APSTSCLR<2:0>(2)
R/W-1
bit 8
ENAPLL
APLLCK
SELACLK
bit 15
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ASRCSEL
FRCSEL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
ENAPLL: Auxiliary PLL Enable bit
1= APLL is enabled
0= APLL is disabled
APLLCK: APLL Locked Status bit (read-only)
1= Indicates that auxiliary PLL is in lock
0= Indicates that auxiliary PLL is not in lock
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1= Auxiliary oscillators provides the source clock for auxiliary clock divider
0= Primary PLL (FVCO) provides the source clock for auxiliary clock divider
bit 12-11
bit 10-8
Unimplemented: Read as ‘0’
APSTSCLR<2:0>: Auxiliary Clock Output Divider bits(2)
111= Divided by 1
110= Divided by 2
101= Divided by 4
100= Divided by 8
011= Divided by 16
010= Divided by 32
001= Divided by 64
000= Divided by 256
bit 7
ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1= Primary oscillator is the clock source
0= No clock input is selected
bit 6
FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1= Selects FRC clock for auxiliary PLL
0= Input clock source is determined by ASRCSEL bit setting
bit 5-0
Unimplemented: Read as ‘0’
Note 1: This register is reset only on a Power-on Reset (POR).
2: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper
operation of the PWM module.
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REGISTER 8-6:
R/W-0
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
ROON
ROSSLP
ROSEL
RODIV<3:0>(1)
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROON: Reference Oscillator Output Enable bit
1= Reference oscillator output is enabled on REFCLK0 pin(2)
0= Reference oscillator output is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ROSSLP: Reference Oscillator Run in Sleep bit
1= Reference oscillator output continues to run in Sleep
0= Reference oscillator output is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1= Oscillator crystal used as the reference clock
0= System clock used as the reference clock
bit 11-8
RODIV<3:0>: Reference Oscillator Divider bits(1)
1111= Reference clock divided by 32,768
1110= Reference clock divided by 16,384
1101= Reference clock divided by 8,192
1100= Reference clock divided by 4,096
1011= Reference clock divided by 2,048
1010= Reference clock divided by 1,024
1001= Reference clock divided by 512
1000= Reference clock divided by 256
0111= Reference clock divided by 128
0110= Reference clock divided by 64
0101= Reference clock divided by 32
0100= Reference clock divided by 16
0011= Reference clock divided by 8
0010= Reference clock divided by 4
0001= Reference clock divided by 2
0000= Reference clock
bit 7-0
Unimplemented: Read as ‘0’
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable; refer to Section 10.6 “Peripheral Pin Select (PPS)” for more information.
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REGISTER 8-7:
LFSR: LINEAR FEEDBACK SHIFT REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
LFSR<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
LFSR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
LFSR<14:0>: Pseudo Random FRC Trim Value bits
bit 14-0
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Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
8.5
Clock Switching Operation
Applications are free to switch among any of the four
clock sources (primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, devices have a safeguard lock
built into the switch process.
1. The clock switching hardware compares the
COSC<2:0> status bits with the new value of the
NOSC<2:0> control bits. If they are the same,
the clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0>
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
2. If a valid clock switch has been initiated, the
LOCK
(OSCCON<5>)
and
the
CF
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
8.5.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 22.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is unpro-
grammed (‘1’), the clock switching function and Fail-Safe
Clock Monitor function are disabled. This is the default
setting.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSC<2:0> bit values are transferred to the
COSC<2:0> status bits.
The NOSC<2:0> control bits (OSCCON<10:8>) do not
control the clock selection when clock switching
is disabled. However, the COSC<2:0> bits
(OSCCON<14:12>) reflect the clock source selected
by the FNOSC Configuration bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled).
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 42. “Oscillator
(Part IV)” (DS70307) in the “dsPIC33F/
PIC24H Family Reference Manual” for
details.
8.5.2
OSCILLATOR SWITCHING SEQUENCE
To perform a clock switch, the following basic sequence
is required:
1. If desired, read the COSC<2:0> bits to
determine the current oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC<2:0>
control bits for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate the
oscillator switch.
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8.6
Fail-Safe Clock Monitor (FSCM)
8.7
Pseudo-Random Generator
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate, even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
The pseudo-random generator is implemented with a
15-bit Linear Feedback Shift Register (LFSR), which is
a shift register with a few exclusive OR gates. The shift
register is clocked by the PWM clock and is a read-only
register. The purpose of this feature is to provide the
ability to randomly change the period or the active
portion of the PWM.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then, the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
A firmware routine can be used to read “n” random bits
from the LFSR register and combine them, by either
summing or performing another logical operation with
the PWM period of the Duty Cycle registers. The result
will be a PWM signal whose nominal period (or duty
cycle) is the desired one, but whose effective value
changes randomly. This capability will help in reducing
the EMI/EMC emissions by spreading the power over a
wider frequency range.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Figure 8-3 provides a block diagram of the LFSR.
FIGURE 8-3:
LFSR BLOCK DIAGRAM
All Zero Detect
LFSR
15
D
D
Q0
Q
Q1
Q
D
D
D
D
D
D
D
D
D
D
D
D
D
Q14
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q6
Q
Q7
Q
Q8
Q
Q9
Q
Q10
Q11
Q12
Q13
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Q
Q
Q
Q
Q
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NOTES:
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9.2
Instruction-Based Power-Saving
Modes
9.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer (WDT) and Power-Saving
Modes” (DS70196) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
The devices have two special power-saving modes that
are entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 9-1.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
9.2.1
SLEEP MODE
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
These devices provide the ability to manage power
consumption by selectively managing clocking to the
CPU and the peripherals. In general, a lower clock
frequency and a reduction in the number of circuits being
clocked constitutes lower consumed power. Devices can
manage power consumption in four different ways:
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate
since the system clock source is disabled.
• Clock Frequency
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
• Some device features or peripherals may continue
to operate. This includes items, such as the Input
Change Notification (ICN) on the I/O ports or
peripherals that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
9.1
Clock Frequency and Clock
Switching
The device will wake-up from Sleep mode on any of
these events:
These devices allow a wide range of clock frequencies
to be selected under application control. If the system
clock configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSC<2:0> bits (OSCCON<10:8>). The
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
process of changing
a
system clock during
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
operation, as well as limitations to the process, are
discussed in more detail in Section 8.0 “Oscillator
Configuration”.
EXAMPLE 9-1:
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
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Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
9.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Module Disable”).
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake-up from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
9.4
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAVinstruction, or the first instruction in the ISR.
9.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAVinstruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
9.3
Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some
circumstances, this may not be practical. For example,
it may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
Note:
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
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9.5
PMD Control Registers
REGISTER 9-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
T2MD
R/W-0
T1MD
U-0
—
R/W-0
PWMMD(1)
U-0
—
bit 15
bit 8
R/W-0
I2C1MD
bit 7
U-0
—
R/W-0
U1MD(2)
U-0
—
R/W-0
SPI1MD(2)
U-0
—
U-0
—
R/W-0
ADCMD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
bit 11
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
bit 10
bit 9
Unimplemented: Read as ‘0’
PWMMD: PWM Module Disable bit(1)
1= PWM module is disabled
0= PWM module is enabled
bit 8
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
bit 6
bit 5
Unimplemented: Read as ‘0’
U1MD: UART1 Module Disable bit(2)
1= UART1 module is disabled
0= UART1 module is enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
SPI1MD: SPI1 Module Disable bit(2)
1= SPI1 module is disabled
0= SPI1 module is enabled
bit 2-1
bit 0
Unimplemented: Read as ‘0’
ADCMD: ADC Module Disable bit
1= ADC module is disabled
0= ADC module is enabled
Note 1: Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be
re-initialized.
2: This bit is not implemented in the dsPIC33FJ06GS001 device.
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REGISTER 9-2:
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IC1MD(1)
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
OC1MD(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
IC1MD: Input Capture 1 Module Disable bit(1)
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7-1
bit 0
Unimplemented: Read as ‘0’
OC1MD: Output Compare 1 Module Disable bit(2)
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices.
2: This bit is not implemented in the dsPIC33FJ06GS001 device.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 9-3:
PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CMPMD(1)
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CMPMD: Analog Comparator Module Disable bit(1)
1= Analog comparator module is disabled
0= Analog comparator module is enabled
bit 9-0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
REGISTER 9-4:
PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
REFOMD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
REFOMD: Reference Clock Generator Module Disable bit
1= Reference clock generator module is disabled
0= Reference clock generator module is enabled
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 9-5:
PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PWM4MD(1)
U-0
—
R/W-0
R/W-0
PWM2MD(2) PWM1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11
Unimplemented: Read as ‘0’
PWM4MD: PWM Generator 4 Module Disable bit(1)
1= PWM Generator 4 module is disabled
0= PWM Generator 4 module is enabled
bit 10
bit 9
Unimplemented: Read as ‘0’
PWM2MD: PWM Generator 2 Module Disable bit(2)
1= PWM Generator 2 module is disabled
0= PWM Generator 2 module is enabled
bit 8
PWM1MD: PWM Generator 1 Module Disable bit
1= PWM Generator 1 module is disabled
0= PWM Generator 1 module is enabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 9-6:
PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CMP2MD(1) CMP1MD(1)
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
Unimplemented: Read as ‘0’
CMP2MD: Analog Comparator 2 Module Disable bit(1)
1= Analog Comparator 2 module is disabled
0= Analog Comparator 2 module is enabled
bit 8
CMP1MD: Analog Comparator 1 Module Disable bit(1)
1= Analog Comparator 1 module is disabled
0= Analog Comparator 1 module is enabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 9-7:
PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCSMD(1)
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
CCSMD: Constant Current Source Module Disable bit(1)
1= Constant current source module is disabled
0= Constant current source module is enabled
bit 0
Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A/202A devices.
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When a peripheral is enabled and the peripheral is
10.0 I/O PORTS
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “I/O Ports”
(DS70193) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
10.1 Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
2011-2012 Microchip Technology Inc.
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FIGURE 10-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
I/O
Peripheral Module Enable
1
Output Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
0
1
0
Output Data
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR PORT
CK
Data Latch
Read LAT
Input Data
Read PORT
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10.2 Open-Drain Configuration
10.4 I/O Port Write/Read Timing
In addition to the PORT, LAT and TRIS registers for
data control, some digital only port pins can also be
individually configured for either digital or open-drain
output. This is controlled by the Open-Drain Control
register, ODCx, associated with each port. Setting any
of the bits configures the corresponding pin to act as an
open-drain output.
Oneinstructioncycleisrequiredbetweenaportdirection
change or port write operation and a read operation of
the same port. Typically, this instruction would be a NOP.
An example is shown in Example 10-1.
10.5 Input Change Notification
The Input Change Notification function of the I/O
ports allows devices to generate interrupt requests to
the processor in response to a Change-of-State (COS)
on selected input pins. This feature can detect input
Change-of-States (COS), even in Sleep mode when
the clocks are disabled. Depending on the device pin
count, up to 16 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a Change-of-State.
The open-drain feature allows the generation of
outputs higher than VDD (for example, 5V), on any
desired 5V tolerant pins, by using external pull-up
resistors. The maximum open-drain voltage allowed is
the same as the maximum VIH specification.
Refer to the “Pin Diagrams” section for the available
pins and their functionality.
10.3 Configuring Analog Port Pins
Four control registers are associated with the CN
module. The CNEN1 register contains the interrupt
enable control bits for each of the CN input pins. Setting
any of these bits enables a CN interrupt for the
corresponding pin.
The ADPCFG and TRIS registers control the operation
of the Analog-to-Digital port pins. The port pins that are
to function as analog inputs must have their corre-
sponding TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin and eliminate the need for external resistors when
the push button or keypad devices are connected. The
pull-ups are enabled separately, using the CNPU1 reg-
ister, which contains the control bits for each of the CN
pins. Setting any of the control bits enables the weak
pull-ups for the corresponding pins.
The ADPCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin, defined as a
digital input (including the ANx pins), can cause the
input buffer to consume current that exceeds the
device specifications.
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
EXAMPLE 10-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
0xFF00, W0
W0, TRISBB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
BTSS PORTB, #13
; Next Instruction
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10.6.2.1
Input Mapping
10.6 Peripheral Pin Select (PPS)
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. A control register
associated with a peripheral dictates the pin it will be
mapped to. The RPINRx registers are used to configure
peripheral input mapping (see Register 10-1 through
Register 10-15). Each register contains sets of 6-bit
fields, with each set associated with one of the
Peripheral Pin Select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The Peripheral Pin Select configuration feature operates
over a fixed subset of digital I/O pins. Programmers can
independently map the input and/or output of most
digital peripherals to any one of these I/O pins.
Peripheral Pin Select is performed in software and gen-
erally does not require the device to be reprogrammed.
Hardware safeguards are included that prevent acciden-
tal or spurious changes to the peripheral mapping once
it has been established.
remappable peripherals. Programming
a given
peripheral’s bit field with an appropriate 6-bit value maps
the RPn pin with that value to that peripheral. For any
given device, the valid range of values for any bit field
corresponds to the maximum number of Peripheral Pin
Selections supported by the device.
Figure 10-2 illustrates the remappable pin selection for
the U1RX input.
Note:
For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
10.6.1
AVAILABLE PINS
The Peripheral Pin Select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the Peripheral Pin Select feature include the
designation, “RPn”, in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
FIGURE 10-2:
REMAPPABLE MUX
INPUT FOR U1RX
10.6.2
CONTROLLING PERIPHERAL PIN
SELECT
U1RXR<5:0>
0
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
RP0
RP1
RP2
1
U1RX Input
to Peripheral
2
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
15
RP15
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TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Configuration
Input Name
Function Name
Register
Bits
External Interrupt 1
External Interrupt 2
Timer1 External Clock
Timer2 External Clock
Input Capture 1
INT1
INT2
RPINR0
RPINR1
INT1R<5:0>
INT2R<5:0>
T1CKR<5:0>
T2CKR<5:0>
IC1R<5:0>
T1CK
T2CK
IC1
RPINR2
RPINR3
RPINR7
Output Compare Fault A
UART1 Receive
OCFA
U1RX
U1CTS
SDI1
RPINR11
RPINR18
RPINR18
RPINR20
RPINR20
RPINR21
RPINR29
RPINR30
RPINR30
RPINR31
RPINR31
RPINR32
RPINR32
RPINR33
RPINR33
RPINR34
OCFAR<5:0>
U1RXR<5:0>
U1CTSR<5:0>
SDI1R<5:0>
SCK1R<5:0>
SS1R<5:0>
UART1 Clear-to-Send
SPI Data Input 1
SPI Clock Input 1
SCK1
SS1
SPI Slave Select Input 1
PWM Fault Input
FLT1
FLT1R<5:0>
FLT2R<5:0>
FLT3R<5:0>
FLT4R<5:0>
FLT5R<5:0>
FLT6R<5:0>
FLT7R<5:0>
FLT8R<5:0>
SYNCI1R<5:0>
SYNCI2R<5:0>
PWM Fault Input
FLT2
PWM Fault Input
FLT3
PWM Fault Input
FLT4
PWM Fault Input
FLT5
PWM Fault Input
FLT6
PWM Fault Input
FLT7
PWM Fault Input
FLT8
External Synchronization Signal to PWM Master Time Base
External Synchronization Signal to PWM Master Time Base
SYNCI1
SYNCI2
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10.6.2.2
Output Mapping
FIGURE 10-3:
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 6-bit fields, with each set associated with one RPn
pin (see Register 10-16 through Register 10-25). The
value of the bit field corresponds to one of the
peripherals and that peripheral’s output is mapped to
the pin (see Table 10-2 and Figure 10-3).
RPORn<5:0>
Default
0
3
4
U1TX Output Enable
U1RTS Output Enable
Output Enable
The list of peripherals for output mapping also includes
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
OC1 Output Enable
18
45
PWM4L Output Enable
Default
0
3
4
U1TX Output
U1RTS Output
RPn
Output Data
OC1 Output
18
45
PWM4L Output
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
NULL
RPORn<5:0>
Output Name
000000
000011
000100
000111
001000
001001
010010
100101
100110
100111
101000
101100
101101
RPn tied to default port pin
RPn tied to UART1 transmit
U1TX
U1RTS
SDO1
RPn tied to UART1 Ready-to-Send
RPn tied to SPI1 data output
SCK1
RPn tied to SPI1 clock output
RPn tied to SPI1 slave select output
RPn tied to Output Compare 1
SS1
OC1
SYNCO1
REFCLKO
ACMP1
ACMP2
PWM4H
PWM4L
RPn tied to external device synchronization signal via PWM master time base
REFCLK output signal
RPn tied to Analog Comparator 1 output
RPn tied to Analog Comparator 2 output
RPn tied to PWM output pins associated with PWM Generator 4
RPn tied to PWM output pins associated with PWM Generator 4
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Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
10.6.2.3
Virtual Pins
Four virtual RPn pins (RP32, RP33, RP34 and RP35)
are supported, which are identical in functionality to all
other RPn pins, with the exception of pinouts. These
four pins are internal to the devices and are not
connected to a physical device pin.
These pins provide a simple way for inter-peripheral
connection without utilizing a physical pin. For example,
the output of the analog comparator can be connected to
RP32 and the PWM Fault input can be configured for
RP32 as well. This configuration allows the analog
comparator to trigger PWM Faults without the use of an
actual physical pin on the device.
10.6.3.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.6.3
CONTROLLING CONFIGURATION
CHANGES
10.6.3.3
Configuration Bit Pin Select Lock
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) Configuration bit blocks the IOLOCK bit
from being cleared, after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the Peripheral Pin Select Control
registers cannot be written to. The only way to clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.6.3.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Note:
MPLAB® C30 provides built-in
C
language functions for unlocking the
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See the MPLAB C30 Help files for more
information.
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4. Each CN pin has a configurable internal weak
10.7 I/O Helpful Tips
pull-up resistor. The pull-ups act as a current
1. In some cases, certain pins, as defined in
source connected to the pin and eliminates the
Table 25-9 under “Injection Current”, have internal
need for external resistors in certain applica-
protection diodes to VDD and VSS. The term,
tions. The internal pull-up is to ~(VDD – 0.8), not
“Injection Current”, is also referred to as “Clamp
VDD. This is still above the minimum VIH of
Current”. On designated pins, with sufficient exter-
CMOS and TTL devices.
nal current limiting precautions by the user, I/O pin
5. When driving LEDs directly, the I/O pin can
input voltages are allowed to be greater or less
source or sink more current than what is
than the data sheet absolute maximum ratings
specified in the VOH/IOH and VOL/IOL DC Char-
with respect to the VSS and VDD supplies. Note
acteristics specification. The respective IOH and
that when the user application forward biases
IOL current rating only applies to maintaining the
either of the high or low side internal input clamp
corresponding output at or above the VOH, and
diodes, that the resulting current being injected
at or below the VOL levels. However, for LEDs,
into the device that is clamped internally by the
unlike digital inputs of an externally connected
VDD and VSS power rails, may affect the ADC
device, they are not governed by the same min-
accuracy by four to six counts.
imum VIH/VIL levels. An I/O pin output can safely
sink or source any current less than that listed in
the “Absolute Maximum Ratings(1)” in
Section 25.0, Electrical Characteristics of this
2. I/O pins that are shared with any analog input pin
(i.e., ANx) are always analog pins by default after
any Reset. Consequently, any pin(s) configured as
an analog input pin, automatically disables the dig-
ital input pin buffer. As such, any attempt to read a
data sheet. For example:
VOH = 2.4V @ IOL = -6 mA and VDD = 3.3V
digital input pin will always return a ‘0’, regardless
of the digital logic level on the pin if the analog pin
is configured. To use a pin as a digital I/O pin on a
shared ANx pin, the user application needs to con-
figure the Analog Pin register in the ADC module
(i.e., ADPCFG) by setting the appropriate bit that
corresponds to that I/O port pin to a ‘1’. On devices
with more than one ADC, both analog pin configu-
rations for both ADC modules must be configured
as a digital I/O pin for that pin to function as a
digital I/O pin.
The maximum output current sourced by any
4x I/O pin = 15 mA.
LED source current <15 mA is technically permitted.
Refer to the VOH/IOH graphs in Section 26.0 “DC
and AC Device Characteristics Graphs” for
additional information.
10.8 I/O Resources
Many useful resources related to I/O are provided on
the Microchip web site (www.microchip.com).
Note:
Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.
10.8.1
KEY RESOURCES
• “dsPIC33F/PIC24H Family Reference Manual”,
Section 10. “I/O Ports” (DS70193)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” Sections
3. Most I/O pins have multiple functions. Referring to
the device pin diagrams in the data sheet, the
priorities of the functions allocated to any pins are
indicated by reading the pin name from left-to-right.
The left most function name takes precedence over
any function to its right in the naming convention; for
example: AN2/CMP1C/CMP2A/RA2. This indi-
cates that AN2 is the highest priority in this example
and will supersede all other functions to its right in
the list. Those other functions to its right, even if
enabled, would not work as long as any other func-
tion to its left was enabled. This rule applies to all of
the functions listed for a given pin.
• Development Tools
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Not all Output Remappable Peripheral registers are
10.9 Peripheral Pin Select Registers
implemented on all devices. See the register
The following registers are implemented for remappable
description of the specific register for further details.
peripheral configuration:
• 15 Input Remappable Peripheral Registers
• 19 Output Remappable Peripheral Registers
Note:
Input and output register values can only
be changed if IOLOCK (OSCCON<6>) = 0.
See Section 10.6.3.1 “Control Register
Lock” for a specific command sequence.
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
INT1R<5:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
INT2R<5:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
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REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
T1CKR<5:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
T1CKR<5:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 10-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T2CKR<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
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REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC1R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A/102A devices.
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REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
OCFAR<5:0>: Assign Output Compare A (OCFA) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
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REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
U1CTSR<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR<5:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
U1RXR<5:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
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REGISTER 10-8: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
SCK1R<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
SDI1R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
SCK1R<5:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
DS75018C-page 160
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS1R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
SS1R<5:0>: Assign SPI1 Slave Select Input (SS1) to the Corresponding RPn Pin bits(1)
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
Note 1: These bits are not implemented in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 161
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-10: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
FLT1R<5:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FLT1R<5:0>: Assign PWM Fault Input 1 (FLT1) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
DS75018C-page 162
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-11: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
FLT3R<5:0>
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLT2R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FLT3R<5:0>: Assign PWM Fault Input 3 (FLT3) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FLT2R<5:0>: Assign PWM Fault Input 2 (FLT2) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
2011-2012 Microchip Technology Inc.
DS75018C-page 163
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-12: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
FLT5R<5:0>
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLT4R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FLT5R<5:0>: Assign PWM Fault Input 5 (FLT5) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FLT4R<5:0>: Assign PWM Fault Input 4 (FLT4) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
DS75018C-page 164
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-13: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
FLT7R<5:0>
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLT6R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FLT7R<5:0>: Assign PWM Fault Input 7 (FLT7) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FLT6R<5:0>: Assign PWM Fault Input 6 (FLT6) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
2011-2012 Microchip Technology Inc.
DS75018C-page 165
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-14: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
SYNCI1R<5:0>
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLT8R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
SYNCI1R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the
Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FLT8R<5:0>: Assign PWM Fault Input 8 (FLT8) to the Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
DS75018C-page 166
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-15: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SYNCI2R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
SYNCI2R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the
Corresponding RPn Pin bits
111111= Input tied to VSS
100011= Input tied to RP35
100010= Input tied to RP34
100001= Input tied to RP33
100000= Input tied to RP32
•
•
•
00000= Input tied to RP0
2011-2012 Microchip Technology Inc.
DS75018C-page 167
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-16: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP1R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP0R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP1R<5:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP0R<5:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-17: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP3R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
RP2R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP3R<5:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP2R<5:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits
(see Table 10-2 for peripheral function numbers)
DS75018C-page 168
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-18: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP5R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP4R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP5R<5:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-19: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP7R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
RP6R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP7R<5:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP6R<5:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits
(see Table 10-2 for peripheral function numbers)
2011-2012 Microchip Technology Inc.
DS75018C-page 169
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-20: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP9R<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP8R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP9R<5:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP8R<5:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
REGISTER 10-21: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP11R<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
RP10R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP11R<5:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP10R<5:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
DS75018C-page 170
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-22: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP13R<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP12R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP13R<5:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP12R<5:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
REGISTER 10-23: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP15R<5:0>(1)
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
RP14R<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP15R<5:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP14R<5:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits(1)
(see Table 10-2 for peripheral function numbers)
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.
2011-2012 Microchip Technology Inc.
DS75018C-page 171
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 10-24: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP33R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP32R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP32R<5:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-25: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP35R<5:0>
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
RP34R<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RP34R<5:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits
(see Table 10-2 for peripheral function numbers)
DS75018C-page 172
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The unique features of Timer1 allow it to be used for
Real-Time Clock applications. A block diagram of
Timer1 is shown in Figure 11-1.
11.0 TIMER1
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer1 modes are determined by the following bits:
• Timer1 Clock Source Control bit: TCS (T1CON<1>)
• Timer1 Synchronization Control bit: TSYNC
(T1CON<2>)
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC) or
operate as a free-running interval timer/counter.
• Timer1 Gate Control bit: TGATE (T1CON<6>)
The Timer1 control bit settings for different operating
modes are given in the Table 11-1.
The Timer1 module has the following unique features
over other timers:
TABLE 11-1: TIMER1 MODE SETTINGS
• Can be operated from the low-power 32 kHz
crystal oscillator available on the device
Mode
Timer1
TCS
TGATE
TSYNC
• Can be operated in Asynchronous Counter mode
from an external clock source
0
0
1
0
1
x
x
x
1
Gated Timer1
• The Timer1 External Clock Input (T1CK) can
optionally be synchronized to the internal device
clock and the clock synchronization is performed
after the prescaler
Synchronous
Counter
Asynchronous
Counter
1
x
0
FIGURE 11-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Falling Edge
Gate
Sync
1
0
Detect
Set T1IF Flag
FP
10
Prescaler
(/n)
TGATE
Reset
Equal
TMR1
00
x1
TCKPS<1:0>
0
1
T1CK
Prescaler
(/n)
Comparator
PR1
Sync
TGATE
TCS
TSYNC
TCKPS<1:0>
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
11.1
Timer1 Control Register
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronizes external clock input
0= Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from T1CK pin (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
12.0 TIMER2 FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
In Synchronous Counter mode, the input clock is
derived from the external clock input at the TxCK pin.
The Timer modes are determined by the following bits:
• TCS (TxCON<1>): Timer Clock Source Control bit
• TGATE (TxCON<6>): Timer Gate Control bit
The Timer control bit settings for different operating
modes are given in Table 12-1.
TABLE 12-1: TIMER MODE SETTINGS
Mode
TCS
TGATE
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Timer
0
0
1
0
1
x
Gated Timer
Synchronous Counter
12.1 16-Bit Operation
Timer2 is a Type B timer with an external clock input
(TxCK) that is always synchronized to the internal
device clock and the clock synchronization is
performed after the prescaler.
To configure any of the timers for individual 16-bit
operation:
1. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
The Timer2 module can operate in one of the following
modes:
2. Set the Clock and Gating modes using the TCS
and TGATE bits.
• Timer mode
3. Load the Timer Period value into the PRx
register.
• Gated Timer mode
• Synchronous Counter mode
4. If interrupts are required, set the Timerx Interrupt
Enable bit, TxIE. Use the priority bits,
TxIP<2:0>, to set the interrupt priority.
5. Set the TON bit.
FIGURE 12-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2)
Falling Edge
Detect
Gate
Sync
1
Set TxIF Flag
FP
10
00
0
Prescaler
(/n)
Reset
Equal
TMRx
Comparator
PRx
TCKPS<1:0>
Sync
TGATE
Prescaler
(/n)
x1
TxCK
TCKPS<1:0>
TGATE
TCS
2011-2012 Microchip Technology Inc.
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12.2 Timer2 Control Register
REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timerx On bit
1= Starts 16-bit timer
0= Stops 16-bit timer
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinues timer operation when device enters Idle mode
0= Continues timer operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit
1= External clock from T2CK pin
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
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2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
• Simple Capture Event modes:
13.0 INPUT CAPTURE
- Capture timer value on every falling edge of
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “Input Cap-
ture” (DS70198) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
input at IC1 pin
- Capture timer value on every rising edge of
input at IC1 pin
• Capture timer value on every edge (rising
and falling)
• Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at IC1 pin
- Capture timer value on every 16th rising
edge of input at IC1 pin
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The input capture module uses the Timer2 module
as its timer; however, it can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
• Interrupt on input capture event
• 4-word FIFO buffer for capture values:
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the IC1 pin. The events that cause a capture event
are listed below in three categories:
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
FIGURE 13-1:
INPUT CAPTURE BLOCK DIAGRAM
TMR2
16
Edge Detection Logic
and
Clock Synchronizer
FIFO
R/W
Logic
Prescaler
Counter
(1, 4, 16)
IC1 Pin
ICM<2:0> (IC1CON<2:0>)
3
Mode Select
ICOV, ICBNE (IC1CON<4:3>)
IC1BUF
ICI<1:0>
Interrupt
Logic
IC1CON
System Bus
Set Flag IC1IF
(in IFS0 Register)
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
13.1 Input Capture Registers
REGISTER 13-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
bit 0
R/W-0
ICTMR(1)
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
ICI<1:0>
ICM<2:0>
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module halts in CPU Idle mode
0= Input capture module continues to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bit(1)
1= TMR2 contents are captured on capture event
0= Reserved
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode. Rising edge
detect only; all other control bits are not applicable.
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling). ICI<1:0> bits do not control interrupt generation
for this mode.
000= Input capture module is turned off
Note 1: This bit is not available in dsPIC33FJ06GS001/101A/102A devices.
DS75018C-page 178
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
output pulse, or a sequence of output pulses, by
changing the state of the output pin on the compare
14.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Output
Compare” (DS70209) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
match events. The output compare module can also
generate interrupts on compare match events.
The output compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without Fault Protection
• PWM mode with Fault Protection
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note:
The output compare module is not
implemented in the dsPIC33FJ06GS001
device.
If a Fault condition is detected on the OCFA pin, the
output pin(s) of the output compare module are placed
in tri-state. The user may elect to use a pull-down or
pull-up resistor on the PWM pin to provide for a desired
state if a Fault condition occurs.
The output compare module can select either Timer1 or
Timer2 for its time base. The module compares the
value of the timer with the value of one or two Compare
registers, depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the Output Compare register value. The
output compare module generates either a single
FIGURE 14-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit,
OC1IF
OC1RS
OC1R
Output
Logic
S
R
Q
OC1
Output Enable
3
OCM<2:0>
Mode Select
OCFA
Comparator
16
TMR2
TMR2
Rollover
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
application must disable the associated timer when
writing to the Output Compare Control registers to
Configure the Output Compare modes by setting the
avoid malfunctions.
14.1 Output Compare Modes
appropriate Output Compare Mode (OCM<2:0>) bits in
Note:
Refer to Section 13. “Output Compare”
(DS70209) in the “dsPIC33F/PIC24H
Family Reference Manual” for OC1R and
OC1RS register restrictions.
the Output Compare Control (OC1CON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
TABLE 14-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
Module Disabled
OC1 Pin Initial State
OC1 Interrupt Generation
000
001
010
011
100
101
110
Controlled by GPIO register
—
Active-Low One-Shot
Active-High One-Shot
Toggle
0
1
OC1 rising edge
OC1 falling edge
Current output is maintained OC1 rising and falling edge
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
0
0
OC1 falling edge
OC1 falling edge
No interrupt
‘0’ if OC1R is zero,
‘1’ if OC1R is non-zero
111
PWM with Fault Protection
‘0’ if OC1R is zero,
OCFA falling edge for OC1 to OC4
‘1’ if OC1R is non-zero
FIGURE 14-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode Enabled
Timerx is Reset on
Period Match
OC1RS
OC1R
TMRx
Active-Low One-Shot
(OCM<2:0> = 001)
Active-High One-Shot
(OCM<2:0> = 010)
Toggle
(OCM<2:0> = 011)
Delayed One-Shot
(OCM<2:0> = 100)
Continuous Pulse
(OCM<2:0> = 101)
PWM
(OCM<2:0> = 110or 111)
DS75018C-page 180
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
14.2 Output Compare Control Registers
REGISTER 14-1: OC1CON: OUTPUT COMPARE 1 CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R-0, HC
OCFLT
U-0
—
R/W-0
R/W-0
OCM<2:0>
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare 1 halts in CPU Idle mode
0= Output Compare 1 continues to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OC1, Fault pin is enabled
110= PWM mode on OC1, Fault pin is disabled
101= Initializes OC1 pin low, generates continuous output pulses on OC1 pin
100= Initializes OC1 pin low, generates single output pulse on OC1 pin
011= Compare event toggles OC1 pin
010= Initializes OC1 pin high, compare event forces OC1 pin low
001= Initializes OC1 pin low, compare event forces OC1 pin high
000= Output compare channel is disabled
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 182
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
• Supported PWM modes:
15.0 HIGH-SPEED PWM
- Standard Edge-Aligned
Note 1: This data sheet summarizes the features
- True Independent Output
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
- Complementary
- Center-Aligned
- Push-Pull
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 43. “High-Speed
PWM” (DS70323) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
- Multiphase
- Variable Phase
- Fixed Off Time
- Current Reset
- Current Limit
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Independent Fault/Current-Limit inputs for each of
the six PWM outputs
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
The high-speed PWM module supports a wide variety
of PWM modes and output formats. This PWM module
is ideal for power conversion applications, such as:
• Dual trigger from PWM to ADC
• PWMxH, PWMxL output pin swapping
• Remappable PWM4H, PWM4L pins
• AC/DC Converters
• DC/DC Converters
• Power Factor Correction (PFC)
• Uninterruptible Power Supply (UPS)
• Inverters
• On-the-fly PWM frequency, duty cycle and
phase-shift changes
• Disabling of individual PWM generators to reduce
power consumption
• Leading-Edge Blanking (LEB) functionality
• Battery Chargers
• PWM output chopping (see Note 1)
• Digital Lighting
Note 1: The chopping function performs a logical
AND of the PWM outputs with a very
high-frequency clock signal. The chop-
ping frequency is typically hundreds or
thousands of time higher in frequency, as
compared to the PWM frequency. Chop-
ping a PWM signal constrains the use of
a pulse transformer to cross the isolation
barrier.
15.1 Features Overview
The high-speed PWM module incorporates the
following features:
• Two to three PWM generators with four to six
outputs
• Individual time base and duty cycle for each of the
six PWM outputs
Figure 15-1 conceptualizes the PWM module in a
simplified block diagram. Figure 15-2 illustrates how
the module hardware is partitioned for each PWM out-
put pair for the Complementary PWM mode. Each
functional unit of the PWM module is discussed in
subsequent sections.
• Dead time for rising and falling edges:
• Duty cycle resolution of 1.04 ns(1,2)
• Dead-time resolution of 1.04 ns(1,2)
• Phase-shift resolution of 1.04 ns(1,2)
• Frequency resolution of 1.04 ns(1,2)
The PWM module contains three PWM generators.
The module has up to six PWM output pins: PWM1H,
PWM1L, PWM2H, PWM2L, PWM4H and PWM4L. For
complementary outputs, these six I/O pins are grouped
into H/L pairs.
Note 1: Resolution is 8.32 ns in Center-Aligned
PWM mode.
2: Resolution is 8.32 ns for
dsPIC33FJ06GS001 devices.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
A multiphase PWM is often used to improve DC/DC
Converter load transient response, and reduce the size
of output filter capacitors and inductors. Multiple DC/
DC Converters are often operated in parallel, but
15.2 Feature Description
The PWM module is designed for applications that
require:
• High-resolution at high PWM frequencies
phase-shifted in time. A single PWM output, operating
at 250 kHz, has a period of 4 s, but an array of four
PWM channels staggered by 1 s each, yields an
effective switching frequency of 1 MHz. Multiphase
• The ability to drive Standard, Edge-Aligned,
Center-Aligned Complementary mode, and
Push-Pull mode outputs
PWM applications typically use
relationship.
a
fixed-phase
• The ability to create multiphase PWM outputs
For Center-Aligned mode, the duty cycle, period, phase
and dead-time resolutions will be 8.32 ns.
A variable phase PWM is useful in Zero Voltage
Transition (ZVT) power converters. Here, the PWM
duty cycle is always 50%, and the power flow is
controlled by varying the relative phase-shift between
the two PWM generators.
Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
PWM output signal to be switched between alternate
pins, as provided by the Push-Pull PWM mode.
A phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specifiable and changeable.
DS75018C-page 184
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 15-1:
SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM
Pin and Mode Control
PWMCONx
LEBCONx
TRGCONx
Control for Blanking External Input Signals
ADC Trigger Control
Dead-Time Control
ALTDTRx, DTRx
PTCON
PWM Enable and Mode Control
MDC
Master Duty Cycle Register
PDC1
MUX
Latch
PWM
Generator 1
PWM1H
PWM1L
Channel 1
Dead-Time Generator
Comparator
Timer
Phase
PDC2
MUX
Latch
PWM2H
PWM2L
Channel 2
Dead-Time Generator
PWM
Generator 2
(2)
Comparator
Timer
Phase
PDC4
PWM
Generator 4
MUX
Latch
(3)
Channel 4
Dead-Time Generator
(1)
PWM4H
Comparator
Timer
(1)
PWM4L
CHOP
Chop Clock
Generator
Timer Period
Phase
Fault Control
Logic
(1)
FLTX
Master Time Base
PTPER
(1)
SYNCO1
External Time Base
Synchronization
PTMR
(1)
SYNCIX
Special Event
Postscaler
Special Event
Trigger
Comparator
Special Event
Comparison Value
Pin Override Control
SEVTCMP
IOCONx
Fault Mode and Pin Control
FCLCONx
Note 1: These pins are remappable.
2: This PWM generator is not available in dsPIC33FJ06GS001/101A devices.
3: This PWM generator is only available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302A devices.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 15-2:
PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE
Phase Offset
TMRx < PDC
M
U
X
PWM
Override
Logic
Dead-Time
Logic
PWMXH
PWMXL
Timer/Counter
Duty Cycle Comparator
M
U
X
Channel Override Values
PWM Duty Cycle Register
Fault Override Values
Fault Active
Fault Pin Assignment Logic
Fault Pin
• TRGCONx: PWMx Trigger Control Register
• IOCONx: PWMx I/O Control Register
15.3 PWM Control Registers
The following registers control the operation of the
high-speed PWM module.
• FCLCONx: PWMx Fault Current-Limit Control
Register
• PTCON: PWM Time Base Control Register
• PTCON2: PWM Clock Divider Select Register 2
• PTPER: PWM Master Time Base Register(1)
• TRIGx: PWMx Primary Trigger Compare Value
Register
• STRIGx: PWMx Secondary Trigger Compare
Value Register
• SEVTCMP: PWM Special Event Compare
Register
• LEBCONx: PWMx Leading-Edge Blanking
Control Register
• MDC: PWM Master Duty Cycle Register
• PWMCONx: PWMx Control Register
• PWMCAPx: Primary PWMx Time Base Capture
Register
• PDCx: PWMx Generator Duty Cycle Register(1)
• PHASEx: PWMx Primary Phase Shift Register
• DTRx: PWMx Dead-Time Register
• CHOP: PWM Chop Clock Generator Register
• AUXCONx: PWMx Auxiliary Control Register
• ALTDTRx: PWMx Alternate Dead-Time Register
• SDCx: PWMx Secondary Duty Cycle Register(1)
• SPHASEx: PWMx Secondary Phase Shift
Register
DS75018C-page 186
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
U-0
—
R/W-0
HS/HC-0
SESTAT
R/W-0
SEIEN
R/W-0
R/W-0
R/W-0
PTSIDL
EIPU(1) SYNCPOL(1) SYNCOEN(1)
bit 15
bit 8
R/W-0
SYNCEN(1)
U-0
—
R/W-0
SYNCSRC<1:0>(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
SEVTPS<3:0>(1)
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PTEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1= PWM time base halts in CPU Idle mode
0= PWM time base runs in CPU Idle mode
bit 12
bit 11
bit 10
bit 9
SESTAT: Special Event Interrupt Status bit
1= Special event interrupt is pending
0= Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1= Special event interrupt is enabled
0= Special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit(1)
1= Active Period register is updated immediately
0= Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronization Input/Output Polarity bit(1)
1= SYNCIx and SYNCO1 polarity is inverted (active-low)
0= SYNCIx and SYNCO1 are active-high
bit 8
SYNCOEN: Primary Time Base Sync Enable bit(1)
1= SYNCO1 output is enabled
0= SYNCO1 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1= External synchronization of primary time base is enabled
0= External synchronization of primary time base is disabled
bit 6
Unimplemented: Read as ‘0’
SYNCSRC<1:0>: Synchronous Source Selection bits(1)
bit 5-4
11= Reserved
10= Reserved
01= SYNCI2
00= SYNCI1
bit 3-0
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)
1111= 1:16 Postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001= 1:2 Postscaler generates a Special Event Trigger on every second compare match event
0000= 1:1 Postscaler generates a Special Event Trigger on every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2011-2012 Microchip Technology Inc.
DS75018C-page 187
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PCLKDIV<2:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111= Reserved
110= Divide-by-64, maximum PWM timing resolution
101= Divide-by-32, maximum PWM timing resolution
100= Divide-by-16, maximum PWM timing resolution
011= Divide-by-8, maximum PWM timing resolution
010= Divide-by-4, maximum PWM timing resolution
001= Divide-by-2, maximum PWM timing resolution
000= Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
(1)
REGISTER 15-3: PTPER: PWM MASTER TIME BASE REGISTER
R/W-1
bit 15
R/W-1
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
bit 8
R/W-0
bit 0
PTPER <15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
PTPER <7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTPER<15:0>: PWM Master Time Base (PMTMR) Period Value bits
Note 1: The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is 0xFFF8.
DS75018C-page 188
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
SEVTCMP <15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
SEVTCMP <7:3>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
SEVTCMP<15:3>: Special Event Compare Count Value bits
Unimplemented: Read as ‘0’
REGISTER 15-5: MDC: PWM MASTER DUTY CYCLE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
MDC<15:8>(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC<7:0>(1,2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
MDC<15:0>: Master PWM Duty Cycle Value bits(1,2)
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSb to 3 LSbs.
2011-2012 Microchip Technology Inc.
DS75018C-page 189
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0
FLTSTAT(1)
HS/HC-0
CLSTAT(1)
HS/HC-0
R/W-0
R/W-0
CLIEN
R/W-0
R/W-0
ITB(3)
R/W-0
MDCS(3)
TRGSTAT
FLTIEN
TRGIEN
bit 15
bit 8
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
CAM(2,3)
R/W-0
XPRES(4)
R/W-0
IUE
DTC<1:0>
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
FLTSTAT: Fault Interrupt Status bit(1)
1= Fault interrupt is pending
0= No Fault interrupt is pending; this bit is cleared by setting FLTIEN = 0
CLSTAT: Current-Limit Interrupt Status bit(1)
1= Current-limit interrupt is pending
0= No current-limit interrupt is pending; this bit is cleared by setting CLIEN = 0
TRGSTAT: Trigger Interrupt Status bit
1= Trigger interrupt is pending
0= No trigger interrupt is pending; this bit is cleared by setting TRGIEN = 0
FLTIEN: Fault Interrupt Enable bit
1= Fault interrupt is enabled
0= Fault interrupt is disabled and the FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1= Current-limit interrupt is enabled
0= Current-limit interrupt is disabled and the CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1= A trigger event generates an interrupt request
0= Trigger event interrupts are disabled and the TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit(3)
1= PHASEx/SPHASEx register provides time base period for this PWM generator
0= PTPER register provides timing for this PWM generator
bit 8
MDCS: Master Duty Cycle Register Select bit(3)
1= MDC register provides duty cycle information for this PWM generator
0= PDCx/SDCx register provides duty cycle information for this PWM generator
bit 7-6
DTC<1:0>: Dead-Time Control bits
11= Reserved
10= Dead-time function is disabled
01= Negative dead time actively applied for all output modes
00= Positive dead time actively applied for all output modes
bit 5-3
Unimplemented: Read as ‘0’
Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To operate in External Period Reset mode, configure the CLMOD (FCLCONx<8>) bit = 0and
ITB (PWMCONx<9>) bit = 1.
DS75018C-page 190
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
bit 2
bit 1
bit 0
CAM: Center-Aligned Mode Enable bit(2,3)
1= Center-Aligned mode is enabled
0= Center-Aligned mode is disabled
XPRES: External PWM Reset Control bit(4)
1= Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode
0= External pins do not affect PWM time base
IUE: Immediate Update Enable bit
1= Updates to the active MDC/PDCx/SDCx registers are immediate
0= Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base
Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To operate in External Period Reset mode, configure the CLMOD (FCLCONx<8>) bit = 0and
ITB (PWMCONx<9>) bit = 1.
2011-2012 Microchip Technology Inc.
DS75018C-page 191
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
(1)
REGISTER 15-7: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
PDCx<15:8>(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDCx<15:0>: PWMx Generator # Duty Cycle Value bits(2)
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In Complementary,
Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and
PWMxL. The smallest pulse width that can be generated on the PWM output corresponds to a value of
0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.
(1)
REGISTER 15-8: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
SDCx<15:8>(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits(2)
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle. The smallest pulse width that can be generated on the
PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to
a value of Period-0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.
DS75018C-page 192
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-9: PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
PHASEx<15:8>(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
PHASEx<7:0>(1,2)
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PHASEx<15:0>: PWMx Phase Shift Value or Independent Time Base Period for PWM Generator bits(1,2)
Note 1: If the ITB (PWMCONx<9>) bit = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), PHASEx<15:0> = Phase shift value for PWMxH and PWMxL outputs.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Phase shift value for PWMxL only.
2: If the ITB (PWMCONx<9>) bit = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Independent time base period value for PWMxL only.
•
The smallest pulse width that can be generated on the PWM output corresponds to a value of
0x0008, while the maximum pulse width generated corresponds to a value of Period-0x0008.
2011-2012 Microchip Technology Inc.
DS75018C-page 193
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
SPHASEx<15:8>(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
SPHASEx<7:0>(1,2)
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits(1,2)
(used in Independent PWM mode only)
Note 1: If the ITB (PWMCONx<9>) bit = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), SPHASEx<15:0> = Not used.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Phase shift value for PWMxL only.
2: If the ITB (PWMCONx<9>) bit = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), SPHASEx<15:0> = Not used.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Independent time base period value for PWMxL only.
DS75018C-page 194
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
.
REGISTER 15-11: DTRx: PWMx DEAD-TIME REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DTRx<13:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-0
Unimplemented: Read as ‘0’
DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 15-12: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
ALTDTRx<13:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTR <7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-0
Unimplemented: Read as ‘0’
ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
2011-2012 Microchip Technology Inc.
DS75018C-page 195
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
TRGDIV<3:0>
bit 15
bit 8
R/W-0
bit 0
R/W-0
DTM(1)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSTRT<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
TRGDIV<3:0>: Trigger # Output Divider bits
1111= Trigger output for every 16th trigger event
1110= Trigger output for every 15th trigger event
1101= Trigger output for every 14th trigger event
1100= Trigger output for every 13th trigger event
1011= Trigger output for every 12th trigger event
1010= Trigger output for every 11th trigger event
1001= Trigger output for every 10th trigger event
1000= Trigger output for every 9th trigger event
0111= Trigger output for every 8th trigger event
0110= Trigger output for every 7th trigger event
0101= Trigger output for every 6th trigger event
0100= Trigger output for every 5th trigger event
0011= Trigger output for every 4th trigger event
0010= Trigger output for every 3rd trigger event
0001= Trigger output for every 2nd trigger event
0000= Trigger output for every trigger event
bit 11-8
bit 7
Unimplemented: Read as ‘0’
DTM: Dual Trigger Mode bit(1)
1= Secondary trigger event is combined with the primary trigger event to create the PWM trigger.
0= Secondary trigger event is not combined with the primary trigger event to create the PWM trigger;
two separate PWM triggers are generated
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111= Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010= Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001= Wait 1 PWM cycle before generating the first trigger event after the module is enabled
000000= Wait 0 PWM cycle before generating the first trigger event after the module is enabled
Note 1: The secondary generator cannot generate PWM trigger interrupts.
DS75018C-page 196
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER
R/W-0
PENH
R/W-0
PENL
R/W-0
POLH
R/W-0
POLL
R/W-0
R/W-0
R/W-0
R/W-0
PMOD<1:0>(1)
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
FLTDAT<1:0>(2)
R/W-0
R/W-0
R/W-0
R/W-0
SWAP
R/W-0
OVRDAT<1:0>
CLDAT<1:0>(2)
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PENH: PWMxH Output Pin Ownership bit
1= PWM module controls PWMxH pin
0= GPIO module controls PWMxH pin
bit 14
PENL: PWMxL Output Pin Ownership bit
1= PWM module controls PWMxL pin
0= GPIO module controls PWMxL pin
bit 13
POLH: PWMxH Output Pin Polarity bit
1= PWMxH pin is active-low
0= PWMxH pin is active-high
bit 12
POLL: PWMxL Output Pin Polarity bit
1= PWMxL pin is active-low
0= PWMxL pin is active-high
bit 11-10
PMOD<1:0>: PWMx I/O Pin Mode bits(1)
11= PWM I/O pin pair is in the True Independent Output mode
10= PWM I/O pin pair is in the Push-Pull Output mode
01= PWM I/O pin pair is in the Redundant Output mode
00= PWM I/O pin pair is in the Complementary Output mode
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1= OVRDAT<1> provides data for output on PWMxH pin
0= PWM generator provides data for PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1= OVRDAT<0> provides data for output on PWMxL pin
0= PWM generator provides data for PWMxL pin
bit 7-6
bit 5-4
OVRDAT<1:0>: Data for PWMxH and PWMxL Pins if Override is Enabled bits
If OVERENH = 1then OVRDAT<1> provides data for PWMxH.
If OVERENL = 1then OVRDAT<0> provides data for PWMxL.
FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0, Normal Fault mode:
If Fault is active, then FLTDAT<1> provides the state for PWMxH.
If Fault is active, then FLTDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1, Independent Fault mode:
If current-limit is active, then FLTDAT<1> provides the state for PWMxH.
If Fault is active, then FLTDAT<0> provides the state for PWMxL.
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: State represents the active/inactive state of the PWM module depending on the POLH and POLL bit
settings.
2011-2012 Microchip Technology Inc.
DS75018C-page 197
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED)
bit 3-2
CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0, Normal Fault mode:
If current-limit is active, then CLDAT<1> provides the state for PWMxH.
If current-limit is active, then CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1, Independent Fault mode:
CLDAT<1:0> is ignored.
bit 1
bit 0
SWAP<1:0>: SWAP PWMxH and PWMxL pins
1= PWMxH output signal is connected to PWMxL pin and PWMxL signal is connected to PWMxH pins
0= PWMxH and PWMxL pins are mapped to their respective pins
OSYNC: Output Override Synchronization bit
1= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0= Output overrides via the OVRDAT<1:0> bits occur on next CPU clock boundary
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: State represents the active/inactive state of the PWM module depending on the POLH and POLL bit
settings.
DS75018C-page 198
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFLTMOD
CLSRC<4:0>(2,3)
CLPOL(1)
CLMOD
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
FLTSRC<4:0>(2,3)
R/W-0
R/W-0
R/W-0
FLTPOL(1)
R/W-0
FLTMOD<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
IFLTMOD: Independent Fault Mode Enable bit
1= Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input
maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions.
0= Normal Fault mode: Current-limit feature maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs. The PWM Fault feature maps FLTDAT<1:0> to the PWMxH and PWMxL outputs.
bit 14-10
CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx # Generator bits(2,3)
11111= Reserved
•
•
•
01000= Reserved
00111= Fault 8
00110= Fault 7
00101= Fault 6
00100= Fault 5
00011= Fault 4
00010= Fault 3
00001= Fault 2
00000= Fault 1
bit 9
bit 8
CLPOL: Current-Limit Polarity for PWMx Generator # bit(1)
1= The selected current-limit source is active-low
0= The selected current-limit source is active-high
CLMOD: Current-Limit Mode Enable bit for PWMx Generator # bit
1= Current-limit function is enabled
0= Current-limit function is disabled
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD<1:0> = 1), and Fault 1 is used for Current-Limit
mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an
unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD<1:0> = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL outputs.
2011-2012 Microchip Technology Inc.
DS75018C-page 199
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED)
bit 7-3
FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3)
11111= Reserved
•
•
•
01000= Reserved
00111= Fault 8
00110= Fault 7
00101= Fault 6
00100= Fault 5
00011= Fault 4
00010= Fault 3
00001= Fault 2
00000= Fault 1
bit 2
FLTPOL: Fault Polarity for PWMx Generator # bit(1)
1= The selected Fault source is active-low
0= The selected Fault source is active-high
bit 1-0
FLTMOD<1:0>: Fault Mode for PWMx Generator # bits
11= Fault input is disabled
10= Reserved
01= The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
00= The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD<1:0> = 1), and Fault 1 is used for Current-Limit
mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an
unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
3: When Independent Fault mode is enabled (IFLTMOD<1:0> = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL outputs.
DS75018C-page 200
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
TRGCMP<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
TRGCMP<7:3>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
TRGCMP<15:3>: Trigger Control Value bits
When primary PWM functions in local time base, this register contains the compare values that can
trigger the ADC module.
Unimplemented: Read as ‘0’
REGISTER 15-17: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
STRGCMP<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
STRGCMP<7:3>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
STRGCMP<15:3>: Secondary Trigger Control Value bits
When secondary PWM functions in local time base, this register contains the compare values that can
trigger the ADC module.
Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc.
DS75018C-page 201
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-18: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER
R/W-0
PHR
R/W-0
PHF
R/W-0
PLR
R/W-0
PLF
R/W-0
R/W-0
R/W-0
R/W-0
FLTLEBEN
CLLEBEN
LEB<6:5>
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
LEB<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
PHR: PWMxH Rising Edge Trigger Enable bit
1= Rising edge of PWMxH will trigger LEB counter
0= LEB ignores rising edge of PWMxH
PHF: PWMxH Falling Edge Trigger Enable bit
1= Falling edge of PWMxH will trigger LEB counter
0= LEB ignores falling edge of PWMxH
PLR: PWMxL Rising Edge Trigger Enable bit
1= Rising edge of PWMxL will trigger LEB counter
0= LEB ignores rising edge of PWMxL
PLF: PWMxL Falling Edge Trigger Enable bit
1= Falling edge of PWMxL will trigger LEB counter
0= LEB ignores falling edge of PWMxL
FLTLEBEN: Fault Input LEB Enable bit
1= Leading-edge blanking is applied to selected Fault input
0= Leading-edge blanking is not applied to selected Fault input
CLLEBEN: Current-Limit LEB Enable bit
1= Leading-edge blanking is applied to selected current-limit input
0= Leading-edge blanking is not applied to selected current-limit input
bit 9-3
bit 2-0
LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Inputs bits
The value is 8.32 nsec increments.
Unimplemented: Read as ‘0’
DS75018C-page 202
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWMCAP<15:8>(1,2)
bit 8
bit 0
R-0
R-0
R-0
R-0
U-0
—
U-0
—
U-0
—
PWMCAP<7:3>(1,2)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2)
The value in this register represents the captured PWM time base value when a leading edge is
detected on the current-limit input.
Unimplemented: Read as ‘0’
Note 1: The capture feature is only available on primary output (PWMxH).
2: This feature is active only after LEB processing on the current-limit input signal is complete.
REGISTER 15-20: CHOP: PWM CHOP CLOCK GENERATOR REGISTER
R/W-0
CHPCLKEN
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CHOPCLK<6:5>
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
CHOPCLK<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CHPCLKEN: Enable Chop Clock Generator bit
1= Chop clock generator is enabled
0= Chop clock generator is disabled
bit 14-10
bit 9-3
Unimplemented: Read as ‘0’
CHOPCLK<6:0>: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression:
Chop Frequency = 1/(16.64 * (CHOPCLK<6:0> + 1) * Primary Master PWM Input Clock/PCLKDIV<2:0>)
bit 2-0
Unimplemented: Read as ‘0’
2011-2012 Microchip Technology Inc.
DS75018C-page 203
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-21: AUXCONx: PWMx AUXILIARY CONTROL REGISTER
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
UW-0
—
HRPDIS
HRDDIS
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHOPLEN
bit 0
CHOPSEL<3:0>
CHOPHEN
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
HRPDIS: High-Resolution PWMx Period Disable bit
1= High-resolution PWMx period is enabled
0= High-resolution PWMx period is disabled
HRDDIS: High-Resolution PWMx Duty Cycle Disable bit
1= High-resolution PWMx duty cycle is enabled
0= High-resolution PWMx duty cycle is disabled
bit 13-6
bit 5-2
Unimplemented: Read as ‘0’
CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (CHOP) the selected PWMx outputs.
1001= Reserved
1000= Reserved
0111= Reserved
0110= Reserved
0101= Reserved
0100= PWM4H is selected as CHOP clock source
0011= Reserved
0010= PWM2H is selected as CHOP clock source
0001= PWM1H is selected as CHOP clock source
0000= Chop clock generator is selected as CHOP clock source
bit 1
bit 0
CHOPHEN: PWMxH Output Chopping Enable bit
1= PWMxH chopping function is enabled
0= PWMxH chopping function is disabled
CHOPLEN: PWMxL Output Chopping Enable bit
1= PWMxL chopping function is enabled
0= PWMxL chopping function is disabled
DS75018C-page 204
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The Serial Peripheral Interface (SPI) module is a
16.0 SERIAL PERIPHERAL
synchronous serial interface useful for communicating
INTERFACE (SPI)
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
Note 1: This data sheet summarizes the features
registers, display drivers, Analog-to-Digital Converters,
of the dsPIC33FJ06GS001/101A/102A/
etc. The SPI module is compatible with Motorola® SPI
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a compre-
and SIOP.
hensive reference source. To complement
the information in this data sheet, refer to
Section 18. “Serial Peripheral Interface
(SPI)” (DS70206) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of 4 pins:
• SDIx (serial data input)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active-low slave select)
In Master mode operation, SCKx is a clock output; in
Slave mode, it is a clock input.
FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM
SCKx
SSx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
2011-2012 Microchip Technology Inc.
DS75018C-page 205
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
To avoid invalid slave read data to the master, the
16.1 SPI Helpful Tips
user’s master software must ensure enough time for
1. In Frame mode, if there is a possibility that the
slave software to fill its write buffer before the user
master may not be initialized before the slave:
application initiates a master write/read cycle. It is
a) If FRMPOL (SPIxCON2<13>) = 1, use a
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPI Shift register
and is empty once the data transmission begins.
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
Note:
This insures that the first frame
transmission after initialization is not
shifted or corrupted.
16.2 SPI Resources
Many useful resources related to SPI are provided on
the Microchip web site (www.microchip.com).
2. In Non-Framed 3-Wire mode, (i.e., not using
SSx from a master):
16.2.1
KEY RESOURCES
a) If CKP (SPIxCON1<6>) = 1, always place a
•
Section 18. “Serial Peripheral Interface (SPI)”
pull-up resistor on SSx.
(DS70206)
b) If CKP = 0, always place a pull-down
• Code Samples
• Application Notes
• Software Libraries
• Webinars
resistor on SSx.
Note:
This will insure that during power-up and
initialization the master/slave will not lose
Sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
• All related “dsPIC33F/PIC24H Family Reference
Manual” Sections
• Development Tools
3. FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
Note:
Not all third-party devices support Frame
mode timing. Refer to the SPI electrical
characteristics for details.
4. In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
DS75018C-page 206
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
16.3
SPI Control Registers
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded; the user software has not read the previous
data in the SPIxBUF register
0= No overflow has occurred
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive is complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads the SPIxBUF location, reading SPIxRXB.
2011-2012 Microchip Technology Inc.
DS75018C-page 207
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN(3)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
SPRE<2:0>(2)
R/W-0
R/W-0
R/W-0
MSTEN
PPRE<1:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1= Internal SPI clock is disabled; pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx Pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data is sampled at end of data output time
0= Input data is sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)(3)
1= SSx pin is used for Slave mode
0= SSx pin is not used by module; pin is controlled by port function
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: This bit is not used in Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
DS75018C-page 208
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
•
•
•
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: This bit is not used in Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
2011-2012 Microchip Technology Inc.
DS75018C-page 209
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as Frame Sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame Sync pulse input (slave)
0= Frame Sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame Sync pulse is active-high
0= Frame Sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame Sync pulse coincides with first bit clock
0= Frame Sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
17.1 Operating Modes
17.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 19. “Inter-Integrated Circuit
(I2C™)” (DS70195) in the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available on the Microchip web site
(www.microchip.com).
The following types of I2C operation are supported:
• I2C slave operation with 7-bit addressing
• I2C slave operation with 10-bit addressing
• I2C master operation with 7-bit or 10-bit addressing
For details about the communication sequence in each
of these modes, please see the Microchip web site
(www.microchip.com) for the latest “dsPIC33F/PIC24H
Family Reference Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Inter-Integrated Circuit™ (I2C™) module provides
complete hardware support for both Slave and
Multi-Master modes of the I2C serial communication
standard with a 16-bit interface.
The I2C module has a 2-pin interface:
• The SCL1 pin is the clock
• The SDA1 pin is data
The I2C module offers the following key features:
• I2C interface supporting both Master and Slave
modes of operation
• I2C Slave mode supports 7-bit and
10-bit addressing
• I2C Master mode supports 7-bit and
10-bit addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I2C supports multi-master operation, detects bus
collision and arbitrates accordingly
2011-2012 Microchip Technology Inc.
DS75018C-page 211
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2
FIGURE 17-1:
I C™ BLOCK DIAGRAM
Internal
Data Bus
I2C1RCV
Read
Shift
Clock
SCL1
SDA1
I2C1RSR
LSb
Address Match
Write
Read
Match Detect
I2C1MSK
Write
Read
I2C1ADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2C1STAT
I2C1CON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2C1TRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2C1BRG
DS75018C-page 212
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
17.2 I2C Registers
• I2C1TRN is the transmit register to which bytes
are written during a transmit operation
I2C1CON and I2C1STAT are control and status
registers, respectively. The I2C1CON register is
readable and writable. The lower six bits of I2C1STAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• The I2C1ADD register holds the slave address
• A status bit, ADD10, indicates 10-Bit Address
mode
• The I2C1BRG acts as the Baud Rate Generator
(BRG) reload value
• I2C1RSR is the shift register used for shifting data
internal to the module and the user application
has no access to it
In receive operations, I2C1RSR and I2C1RCV
together form
a double-buffered receiver. When
I2C1RSR receives a complete byte, it is transferred to
I2C1RCV, and an interrupt pulse is generated.
• I2C1RCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read
REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1, HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0, HC R/W-0, HC
ACKEN RCEN
R/W-0, HC
PEN
R/W-0, HC
RSEN
R/W-0, HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
I2CEN: I2C1 Enable bit
1= Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins
0= Disables the I2C1 module; all I2C pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinues module operation when device enters an Idle mode
0= Continues module operation in Idle mode
bit 12
SCLREL: SCL1 Release Control bit (when operating as I2C slave)
1= Releases SCL1 clock
0= Holds SCL1 clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at beginning of slave transmission. Hardware is clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode is disabled
A10M: 10-Bit Slave Address bit
1= I2C1ADD is a 10-bit slave address
0= I2C1ADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control is disabled
0= Slew rate control is enabled
2011-2012 Microchip Technology Inc.
DS75018C-page 213
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED)
bit 8
SMEN: SMBus Input Levels bit
1= Enables I/O pin thresholds compliant with SMBus specification
0= Disables SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enables interrupt when a general call address is received in the I2C1RSR
(module is enabled for reception)
0= General call address is disabled
bit 6
bit 5
bit 4
STREN: SCL1 Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enables software or receives clock stretching
0= Disables software or receives clock stretching
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1= Sends NACK during Acknowledge
0= Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit.
Hardware is clear at end of master Acknowledge sequence.
0= Acknowledge sequence is not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware is clear at end of eighth bit of master receive data byte.
0= Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiates Stop condition on SDA1 and SCL1 pins. Hardware is clear at end of master Stop sequence.
0= Stop condition is not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiates Repeated Start condition on SDA1 and SCL1 pins. Hardware is clear at end of master
Repeated Start sequence.
0= Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiates Start condition on SDA1 and SCL1 pins. Hardware is clear at end of master Start
sequence.
0= Start condition is not in progress
DS75018C-page 214
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER
R-0, HSC
ACKSTAT
bit 15
R-0, HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0, HSC
BCL
R-0, HSC
GCSTAT
R-0, HSC
ADD10
bit 8
R/C-0, HS R/C-0, HS
IWCOL I2COV
bit 7
R-0, HSC
D_A
R/C-0, HSC
P
R/C-0, HSC
S
R-0, HSC
R_W
R-0, HSC
RBF
R-0, HSC
TBF
bit 0
Legend:
HS = Hardware Settable bit’ HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’ C = Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1= NACK is received from slave
0= ACK is received from slave
Hardware is set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware is set at beginning of master transmission. Hardware is clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware is set at detection of bus collision.
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware is set when address matches general call address. Hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware is set at match of 2nd byte of matched 10-bit address. Hardware is clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write to the I2C1TRN register failed because the I2C module is busy
0= No collision
Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2C1RCV register is still holding the previous byte
0= No overflow
Hardware is set at attempt to transfer I2C1RSR to I2C1RCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was the device address
Hardware is clear at device address match. Hardware is set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
2011-2012 Microchip Technology Inc.
DS75018C-page 215
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware is set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive is complete, I2C1RCV is full
0= Receive is not complete, I2C1RCV is empty
Hardware is set when I2C1RCV is written with received byte. Hardware is clear when software reads
I2C1RCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit is in progress, I2C1TRN is full
0= Transmit is complete, I2C1TRN is empty
Hardware is set when software writes I2C1TRN. Hardware is clear at completion of data transmission.
DS75018C-page 216
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK<9:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address bit x Select bits
1= Enables masking for bit x of incoming message address; bit match not required in this position
0= Disables masking for bit x; bit match required in this position
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 218
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The primary features of the UART module are:
18.0 UNIVERSAL ASYNCHRONOUS
• Full-duplex, 8-bit or 9-bit data transmission
through the U1TX and U1RX pins
RECEIVER TRANSMITTER
(UART)
• Even, Odd or No Parity options (for 8-bit data)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70188) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
• One or two Stop bits
• Hardware flow control option with U1CTS and
U1RTS pins
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
• Baud rates ranging from 10 Mbps to 38 bps at
40 MIPS
• 4-deep First-In First-Out (FIFO) transmit data
buffer
• 4-deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Support for 9-bit mode with address detect
(9th bit = 1)
• Transmit and Receive interrupts
• Separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for Sync and Break characters
• Support for automatic baud rate detection
• IrDA encoder and decoder logic
The Universal Asynchronous Receiver Transmitter
(UART) module is a serial I/O module. The UART is a
full-duplex, asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
U1CTS and U1RTS pins, and also includes an IrDA®
encoder and decoder.
• 16x baud clock output for IrDA® support
A simplified block diagram of the UART module is
shown in Figure 18-1. The UART module consists of
these key hardware elements:
• BRG
Note:
The dsPIC33FJ06GS001 device does not
have a UART module.
• Asynchronous transmitter
• Asynchronous receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UART Receiver
U1RTS/BCLK
U1CTS
U1RX
U1TX
UART Transmitter
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
18.1 UART Helpful Tips
18.2 UART Resources
1. In multinode, direct-connect UART networks,
UART receive inputs react to the complemen-
tary logic level defined by the URXINV bit
(U1MODE<4>), which defines the Idle state, the
default of which is logic high, (i.e., URXINV = 0).
Because remote devices do not initialize at the
same time, it is likely that one of the devices,
because the RX line is floating, will trigger a
Start bit detection and will cause the first byte
received after the device has been initialized to
be invalid. To avoid this situation, the user
should use a pull-up or pull-down resistor on the
RX pin, depending on the value of the URXINV
bit.
Many useful resources related to UART are provided
on the Microchip web site (www.microchip.com).
18.2.1
KEY RESOURCES
• Section 17. “UART” (DS70188) in the
“dsPIC33F/PIC24H Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
Manual” Sections
• Development Tools
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.
2. The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UART module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the time
the oscillator system has restarted and stabilized
from Sleep mode, the baud rate bit sampling
clock, relative to the incoming UxRX bit timing, is
no longer synchronized. This results in the first
character being invalid; this is to be expected.
DS75018C-page 220
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
18.3 UART Registers
REGISTER 18-1: U1MODE: UART1 MODE REGISTER
R/W-0
UARTEN(1,3)
bit 15
U-0
—
R/W-0
USIDL(3)
R/W-0
IREN(2,3)
R/W-0
RTSMD(3)
U-0
—
R/W-0
R/W-0
UEN<1:0>(3)
bit 8
R/W-0, HC
WAKE(3)
bit 7
R/W-0
LPBACK(3)
R/W-0, HC
ABAUD(3)
R/W-0
URXINV(3)
R/W-0
BRGH(3)
R/W-0
R/W-0
R/W-0
STSEL(3)
PDSEL<1:0>(3)
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15
UARTEN: UART1 Enable bit(1,3)
1= UART1 is enabled; all UART1 pins are controlled by UART1, as defined by UEN<1:0>
0= UART1 is disabled; all UART1 pins are controlled by port latches; UART1 power consumption
is minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit(3)
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2,3)
1= IrDA® encoder and decoder are enabled
0= IrDA® encoder and decoder are disabled
RTSMD: Mode Selection for U1RTS Pin bit(3)
1= U1RTS pin is in Simplex mode
0= U1RTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UART1 Pin Enable bits(3)
11= U1TX, U1RX and BCLK pins are enabled and used; U1CTS pin is controlled by port latches
10= U1TX, U1RX, U1CTS and U1RTS pins are enabled and used
01= U1TX, U1RX and U1RTS pins are enabled and used; U1CTS pin is controlled by port latches
00= U1TX and U1RX pins are enabled and used; U1CTS and U1RTS/BCLK pins are controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit(3)
1= UART1 will continue to sample the U1RX pin; interrupt is generated on falling edge; bit is cleared
in hardware on following rising edge
0= No wake-up is enabled
bit 6
bit 5
LPBACK: UART1 Loopback Mode Select bit(3)
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit(3)
1= Enable baud rate measurement on the next character – requires reception of a Sync field (0x55)
before other data; cleared in hardware upon completion
0= Baud rate measurement is disabled or completed
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This bit is not available in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
DS75018C-page 221
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 18-1: U1MODE: UART1 MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit(3)
1= U1RX Idle state is ‘0’
0= U1RX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit(3)
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits(3)
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit(3)
1= Two Stop bits
0= One Stop bit
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This bit is not available in the dsPIC33FJ06GS001 device.
DS75018C-page 222
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1(2)
bit 15
R/W-0
UTXINV(2)
R/W-0
UTXISEL0(2)
U-0
—
R/W-0, HC
UTXBRK(2) UTXEN(1,2) UTXBF(2)
R/W-0
R-0
R-1
TRMT(2)
bit 8
R/W-0
URXISEL<1:0>(2)
R/W-0
R/W-0
ADDEN(2)
R-1
RIDLE(2)
R-0
PERR(2)
R-0
FERR(2)
R/C-0
OERR(2)
R-0
URXDA(2)
bit 0
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15,13
‘1’ = Bit is set
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits(2)
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies that there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit(2)
If IREN = 0:
1= U1TX Idle state is ‘0’
0= U1TX Idle state is ‘1’
If IREN = 1:
1= IrDA® encoded U1TX Idle state is ‘1’
0= IrDA encoded U1TX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit(2)
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit(1,2)
1= Transmit is enabled, U1TX pin is controlled by UART1
0= Transmit is disabled, any pending transmission is aborted and buffer is reset; U1TX pin is
controlled by port
bit 9
bit 8
UTXBF: Transmit Buffer Full Status bit (read-only)(2)
1= Transmit buffer is full
0= Transmit buffer is not full; at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)(2)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
2: This bit is not available in the dsPIC33FJ06GS001 device.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits(2)
11= Interrupt is set on U1RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on U1RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the U1RSR to the receive
buffer; receive buffer has one or more characters
bit 5
bit 4
bit 3
bit 2
ADDEN: Address Character Detect bit (bit 8 of received data = 1)(2)
1= Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)(2)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)(2)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)(2)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)(2)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0transition) will reset
the receiver buffer and the U1RSR to the empty state.
URXDA: Receive Buffer Data Available bit (read-only)(2)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
2: This bit is not available in the dsPIC33FJ06GS001 device.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Up to three inputs may be sampled at a time (two inputs
from the dedicated Sample-and-Hold circuits and one
from the shared Sample-and-Hold circuit). If multiple
inputs request conversion, the ADC will convert them in
19.0 HIGH-SPEED 10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
a sequential manner, starting with the lowest order
Note 1: This data sheet summarizes the features
input.
of the dsPIC33FJ06GS001/101A/102A/
This ADC design provides each pair of analog inputs
(AN1, AN0), (AN3, AN2),..., the ability to specify its own
trigger source out of a maximum of sixteen different
trigger sources. This capability allows this ADC to
sample and convert analog inputs that are associated
with PWM generators operating on independent time
bases.
202A and dsPIC33FJ09GS302 families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 44. “High-Speed 10-Bit
ADC” (DS70321) in the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available on the Microchip web site
(www.microchip.com).
The user application typically requires synchronization
between analog data sampling and PWM output to the
application circuit. The very high-speed operation of
this ADC module allows “data on demand”.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP-based application:
• Result alignment options
• Automated sampling
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 family of devices provides
high-speed successive approximation, Analog-to-Digital
conversions to support applications such as AC-to-DC
and DC-to-DC Power Converters.
• External conversion start control
• Two internal inputs to monitor INTREF and
EXTREF input signals (not available in
dsPIC33FJ06GS101A/102A devices)
Block diagrams of the ADC module are shown in
Figure 19-1 through Figure 19-5.
19.1 Features Overview
The ADC module comprises the following features:
19.3 Module Functionality
• 10-bit resolution
The high-speed, 10-bit ADC module is designed to
support power conversion applications when used with
the high-speed PWM module. The ADC has one SAR
and only one conversion can be processed at a time,
yielding a conversion rate of 2 Msps or the equivalent of
one 10-bit conversion, in half a microsecond (0.5 µs).
• Unipolar inputs
• One Successive Approximation Register (SAR)
• Up to eight external input channels
• Up to two internal analog inputs
• Dedicated result register for each analog input
• ±1 LSB accuracy at 3.3V
The ADC module supports up to eight external analog
inputs and two internal analog inputs. To monitor
reference voltage, two internal inputs, AN12 and AN13,
are connected to the EXTREF and INTREF voltages,
respectively.
• Single supply operation
• 2 Msps conversion rate at 3.3V
• Low-power CMOS technology
Note:
The dsPIC33FJ06GS101A/102A devices
do not have the internal connection to
EXTREF.
19.2 Module Description
This ADC module is designed for applications that
require low latency between the request for conversion
and the resultant output data. Typical applications
include:
The analog reference voltage is defined as the device
supply voltage (AVDD/AVSS).
• AC/DC Power Supplies
• DC/DC Converters
• Power Factor Correction (PFC)
This ADC works with the high-speed PWM module in
power control applications that require high-frequency
control loops. This small conversion delay reduces the
“phase lag” between measurement and control system
response.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 19-1:
ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS001 DEVICE
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
Eight
16-Bit
Registers
SAR
Core
(1)
AN12
(EXTREF)
AN1
AN2
AN3
AN6
Shared Sample-and-Hold
AN7
(2)
AN13
(INTREF)
Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the
comparator reference.
2: AN13 (INTREF) is an internal analog input and is not available on a pin.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 19-2:
ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS101A DEVICE
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
AN2
Eight
16-Bit
Registers
SAR
Core
AN1
AN3
AN6
Shared Sample-and-Hold
AN7
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FIGURE 19-3:
ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102A DEVICE
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
AN2
Eight
16-Bit
Registers
SAR
Core
AN1
AN3
AN4
AN5
Shared Sample-and-Hold
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 19-4:
ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202A DEVICE
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
AN2
(1)
AN12
Eight
16-Bit
Registers
SAR
Core
(EXTREF)
AN1
AN3
AN4
AN5
Shared Sample-and-Hold
(2)
AN13
(INTREF)
Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the
comparator reference.
2: AN13 (INTREF) is an internal analog input and is not available on a pin.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 19-5:
ADC BLOCK DIAGRAM FOR dsPIC33FJ09GS302 DEVICE
Even Numbered Inputs with Dedicated
Sample-and-Hold (S&H) Circuits
AN0
AN2
(1)
AN12
Eight
16-Bit
Registers
SAR
Core
(EXTREF)
AN1
AN3
Shared Sample-and-Hold
AN4
AN5
AN6
AN7
(2)
AN13
(INTREF)
Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the
comparator reference.
2: AN13 (INTREF) is an internal analog input and is not available on a pin.
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19.4 ADC Control Registers
Note:
A unique feature of the ADC module is its
ability to sample inputs in an asynchronous
The ADC module uses the following control and status
registers:
manner.
Individual
Sample-and-Hold
circuits can be triggered independently of
each other.
• ADCON: ADC Control Register
• ADSTAT: ADC Status Register
• ADBASE: ADC Base Register(1)
• ADPCFG: ADC Port Configuration Register
• ADCPC0: ADC Convert Pair Control Register 0
• ADCPC1: ADC Convert Pair Control Register 1
• ADCPC3: ADC Convert Pair Control Register 3(1)
The ADCON register controls the operation of the
ADC module. The ADSTAT register displays the
status of the conversion processes. The ADPCFG
register configures the port pins as analog inputs or
as digital I/Os. The ADCPCx registers control the
triggering of the ADC conversions. See Register 19-1
through Register 19-7 for detailed bit configurations.
REGISTER 19-1: ADCON: ADC CONTROL REGISTER
R/W-0
ADON
U-0
—
R/W-0
R/W-0
SLOWCLK(1)
U-0
—
R/W-0
U-0
—
R/W-0
FORM(1)
ADSIDL
GSWTRG
bit 15
bit 8
R/W-1
bit 0
R/W-0
EIE(1)
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-1
ADCS<2:0>(1)
ORDER(1) SEQSAMP(1) ASYNCSAMP(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC module is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
SLOWCLK: Enable Slow Clock Divider bit(1)
1= ADC is clocked by the auxiliary PLL (ACLK)
0= ADC is clocked by the primary PLL (FVCO)
bit 11
bit 10
Unimplemented: Read as ‘0’
GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this
bit is not auto-clearing).
bit 9
Unimplemented: Read as ‘0’
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).
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REGISTER 19-1: ADCON: ADC CONTROL REGISTER (CONTINUED)
bit 8
bit 7
bit 6
bit 5
FORM: Data Output Format bit(1)
1= Fractional (DOUT = dddd dddd dd00 0000)
0= Integer (DOUT = 0000 00dd dddd dddd)
EIE: Early Interrupt Enable bit(1)
1= Interrupt is generated after first conversion is completed
0= Interrupt is generated after second conversion is completed
ORDER: Conversion Order bit(1)
1= Odd numbered analog input is converted first, followed by conversion of even numbered input
0= Even numbered analog input is converted first, followed by conversion of odd numbered input
SEQSAMP: Sequential Sample Enable bit(1)
1= Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if
ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.
0= Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle.
bit 4
ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1)
1= The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0= The dedicated S&H starts sampling when the trigger event is detected and completes the sampling
process in two ADC clock cycles
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1)
111= FADC/8
110= FADC/7
101= FADC/6
100= FADC/5
011= FADC/4 (default)
010= FADC/3
001= FADC/2
000= FADC/1
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).
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REGISTER 19-2: ADSTAT: ADC STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/C-0, HS
P6RDY
U-0
—
U-0
—
R/C-0, HS
P3RDY(1)
R/C-0, HS
P2RDY(2)
R/C-0, HS
P1RDY
R/C-0, HS
P0RDY
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15-7
bit 6
Unimplemented: Read as ‘0’
P6RDY: Conversion Data for Pair 6 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 5-4
bit 3
Unimplemented: Read as ‘0’
P3RDY: Conversion Data for Pair 3 Ready bit(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P2RDY: Conversion Data for Pair 3 Ready bit(2)
bit 2
bit 1
bit 0
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P1RDY: Conversion Data for Pair 1 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P0RDY: Conversion Data for Pair 0 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
(1)
REGISTER 19-3: ADBASE: ADC BASE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
ADBASE<15:8>(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
ADBASE<7:1>(2)
R/W-0
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
ADBASE<15:1>: ADC Base Register bits(2)
This register contains the base address of the user’s ADC Interrupt Service Routine (ISR) jump table.
This register, when read, contains the sum of the ADBASE register contents and the encoded value
of the PxRDY status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits, where P0RDY is the
highest priority and P6RDY is the lowest priority.
bit 0
Unimplemented: Read as ‘0’
Note 1: As an alternative to using the ADBASE register, the ADCP0-6 ADC Pair Conversion Complete Interrupts
can be used to invoke A to D conversion completion routines for individual ADC input pairs.
2: The encoding results are shifted left two bits, so bits 1-0 of the result are always zero.
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REGISTER 19-4: ADPCFG: ADC PORT CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
PCFG7(1)
R/W-0
PCFG6(1)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
PCFG<7:6>: Analog-to-Digital Port Configuration Control bits(1)
1= Port pin is in Digital mode; port read input is enabled; Analog-to-Digital input multiplexer is
connected to AVSS
0= Port pin is in Analog mode; port read input is disabled; Analog-to-Digital samples pin voltage
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
PCFG<3:0>: Analog-to-Digital Port Configuration Control bits
1= Port pin is in Digital mode; port read input is enabled; Analog-to-Digital input multiplexer is
connected to AVSS
0= Port pin is in Analog mode; port read input is disabled; Analog-to-Digital samples pin voltage
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 19-5: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IRQEN1
PEND1
SWTRG1
TRGSRC1<4:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN0
PEND0
SWTRG0
TRGSRC0<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
IRQEN1: Interrupt Request Enable 1 bit
1= Enables IRQ generation when requested conversion of channels AN3 and AN2 is completed
0= IRQ is not generated
PEND1: Pending Conversion Status 1 bit
1= Conversion of channels AN3 and AN2 is pending; set when selected trigger is asserted
0= Conversion is complete
SWTRG1: Software Trigger 1 bit
1= Starts conversion of AN3 and AN2 (if selected by the TRGSRCx bits)(1)
This bit is automatically cleared by hardware when the PEND1 bit is set.
0= Conversion has not started
bit 12-8
TRGSRC1<4:0>: Trigger 1 Source Selection bits
Selects trigger source for conversion of analog channels AN3 and AN2.
11111= Timer2 period match
•
•
•
11011= Reserved
11010= PWM Generator 4 current-limit ADC trigger
11001= Reserved
11000= PWM Generator 2 current-limit ADC trigger
10111= PWM Generator 1 current-limit ADC trigger
10110= Reserved
•
•
•
10010= Reserved
10001= PWM Generator 4 secondary trigger is selected
10000= Reserved
01111= PWM Generator 2 secondary trigger is selected
01110= PWM Generator 1 secondary trigger is selected
01101= Reserved
01100= Timer1 period match
•
•
•
01000= Reserved
00111= PWM Generator 4 primary trigger is selected
00110= Reserved
00101= PWM Generator 2 primary trigger is selected
00100= PWM Generator 1 primary trigger is selected
00011= PWM Special Event Trigger is selected
00010= Global software trigger is selected
00001= Individual software trigger is selected
00000= No conversion is enabled
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, then conversion will be performed when the conversion resources are available.
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REGISTER 19-5: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED)
bit 7
bit 6
bit 5
IRQEN0: Interrupt Request Enable 0 bit
1= Enables IRQ generation when requested conversion of channels AN1 and AN0 is completed
0= IRQ is not generated
PEND0: Pending Conversion Status 0 bit
1= Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted
0= Conversion is complete
SWTRG0: Software Trigger 0 bit
1= Starts conversion of AN1 and AN0 (if selected by the TRGSRCx bits)(1)
This bit is automatically cleared by hardware when the PEND0 bit is set.
0= Conversion has not started
bit 4-0
TRGSRC0<4:0>: Trigger 0 Source Selection bits
Selects trigger source for conversion of analog channels AN1 and AN0.
11111= Timer2 period match
•
•
•
11011= Reserved
11010= PWM Generator 4 current-limit ADC trigger
11001= Reserved
11000= PWM Generator 2 current-limit ADC trigger
10111= PWM Generator 1 current-limit ADC trigger
10110= Reserved
•
•
•
10010= Reserved
10001= PWM Generator 4 secondary trigger is selected
10000= Reserved
01111= PWM Generator 2 secondary trigger is selected
01110= PWM Generator 1 secondary trigger is selected
01101= Reserved
01100= Timer1 period match
•
•
•
01000= Reserved
00111= PWM Generator 4 primary trigger is selected
00110= Reserved
00101= PWM Generator 2 primary trigger is selected
00100= PWM Generator 1 primary trigger is selected
00011= PWM Special Event Trigger is selected
00010= Global software trigger is selected
00001= Individual software trigger is selected
00000= No conversion is enabled
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, then conversion will be performed when the conversion resources are available.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 19-6: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1
R/W-0
IRQEN3(1)
R/W-0
PEND3(1)
R/W-0
SWTRG3(1)
R/W-0
R/W-0
R/W-0
TRGSRC3<4:0>(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
bit 15
R/W-0
IRQEN2(2)
R/W-0
PEND2(2)
R/W-0
SWTRG2(2)
R/W-0
R/W-0
R/W-0
TRGSRC2<4:0>(2)
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
IRQEN3: Interrupt Request Enable 3 bit(1)
1= Enables IRQ generation when requested conversion of channels AN7 and AN6 is completed
0= IRQ is not generated
PEND3: Pending Conversion Status 3 bit(1)
1= Conversion of channels AN7 and AN6 is pending; set when selected trigger is asserted
0= Conversion is complete
SWTRG3: Software Trigger 3 bit(1)
1= Starts conversion of AN7 and AN6 (if selected by the TRGSRCx bits)(3)
This bit is automatically cleared by hardware when the PEND3 bit is set.
0= Conversion has not started
bit 12-8
TRGSRC3<4:0>: Trigger 3 Source Selection bits(1)
Selects trigger source for conversion of analog channels AN7 and AN6.
11111= Timer2 period match
•
•
•
11011= Reserved
11010= PWM Generator 4 current-limit ADC trigger
11001= Reserved
11000= PWM Generator 2 current-limit ADC trigger
10111= PWM Generator 1 current-limit ADC trigger
10110= Reserved
•
•
•
10010= Reserved
10001= PWM Generator 4 secondary trigger is selected
10000= Reserved
01111= PWM Generator 2 secondary trigger is selected
01110= PWM Generator 1 secondary trigger is selected
01101= Reserved
01100= Timer1 period match
•
•
•
01000= Reserved
00111= PWM Generator 4 primary trigger is selected
00110= Reserved
00101= PWM Generator 2 primary trigger is selected
00100= PWM Generator 1 primary trigger is selected
00011= PWM Special Event Trigger is selected
00010= Global software trigger is selected
00001= Individual software trigger is selected
00000= No conversion is enabled
Note 1: This bit is available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices only.
2: This bit is available in dsPIC33FJ06GS102A/201A and dsPIC33FJ09GS302 devices only.
3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, conversion will be performed when the conversion resources are available.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 19-6: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED)
bit 7
bit 6
bit 5
IRQEN2: Interrupt Request Enable 2 bit(2)
1= Enables IRQ generation when requested conversion of channels AN5 and AN4 is completed
0= IRQ is not generated
PEND2: Pending Conversion Status 2 bit(2)
1= Conversion of channels AN5 and AN4 is pending; set when selected trigger is asserted.
0= Conversion is complete
SWTRG2: Software Trigger 2 bit(2)
1= Starts conversion of AN5 and AN4 (if selected by the TRGSRCx bits)(3)
This bit is automatically cleared by hardware when the PEND2 bit is set.
0= Conversion has not started
bit 4-0
TRGSRC2<4:0>: Trigger 2 Source Selection bits(2)
Selects trigger source for conversion of analog channels AN5 and AN4.
11111= Timer2 period match
•
•
•
11011= Reserved
11010= PWM Generator 4 current-limit ADC trigger
11001= Reserved
11000= PWM Generator 2 current-limit ADC trigger
10111= PWM Generator 1 current-limit ADC trigger
10110= Reserved
•
•
•
10010= Reserved
10001= PWM Generator 4 secondary trigger is selected
10000= Reserved
01111= PWM Generator 2 secondary trigger is selected
01110= PWM Generator 1 secondary trigger is selected
01101= Reserved
01100= Timer1 period match
•
•
•
01000= Reserved
00111= PWM Generator 4 primary trigger is selected
00110= Reserved
00101= PWM Generator 2 primary trigger is selected
00100= PWM Generator 1 primary trigger is selected
00011= PWM Special Event Trigger is selected
00010= Global software trigger is selected
00001= Individual software trigger is selected
00000= No conversion is enabled
Note 1: This bit is available in dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices only.
2: This bit is available in dsPIC33FJ06GS102A/201A and dsPIC33FJ09GS302 devices only.
3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions
are in progress, conversion will be performed when the conversion resources are available.
2011-2012 Microchip Technology Inc.
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(1)
REGISTER 19-7: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN6
PEND6
SWTRG6
TRGSRC6<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
IRQEN6: Interrupt Request Enable 6 bit
1= Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed
0= IRQ is not generated
bit 6
bit 5
PEND6: Pending Conversion Status 6 bit
1= Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted
0= Conversion is complete
SWTRG6: Software Trigger 6 bit
1= Starts conversion of AN13 (INTREF) and AN12 (EXTREF) if selected by TRGSRC bits(2)
This bit is automatically cleared by hardware when the PEND6 bit is set.
0= Conversion has not started
Note 1: If other conversions are in progress, conversion will be performed when the conversion resources are
available.
2: AN13 is internally connected to Vref in all devices. AN12 is internally connected to the EXTREF pin in the
dsPIC33FJ06001/202A and dsPIC33FJ09GS302 devices. The dsPIC33FJ06GS101A/102A devices not
have an EXTREF pin; therefore, any data read on the corresponding AN12 input will be invalid.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
(1)
REGISTER 19-7: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED)
bit 4-0
TRGSRC6<4:0>: Trigger 6 Source Selection bits
Selects trigger source for conversion of analog channels AN13 and AN12.
11111= Timer2 period match
•
•
•
11011= Reserved
11010= PWM Generator 4 current-limit ADC trigger
11001= Reserved
11000= PWM Generator 2 current-limit ADC trigger
10111= PWM Generator 1 current-limit ADC trigger
10110= Reserved
•
•
•
10010= Reserved
10001= PWM Generator 4 secondary trigger is selected
10000= Reserved
01111= PWM Generator 2 secondary trigger is selected
01110= PWM Generator 1 secondary trigger is selected
01101= Reserved
01100= Timer1 period match
•
•
•
01000= Reserved
00111= PWM Generator 4 primary trigger is selected
00110= Reserved
00101= PWM Generator 2 primary trigger is selected
00100= PWM Generator 1 primary trigger is selected
00011= PWM Special Event Trigger is selected
00010= Global software trigger is selected
00001= Individual software trigger is selected
00000= No conversion is enabled
Note 1: If other conversions are in progress, conversion will be performed when the conversion resources are
available.
2: AN13 is internally connected to Vref in all devices. AN12 is internally connected to the EXTREF pin in the
dsPIC33FJ06001/202A and dsPIC33FJ09GS302 devices. The dsPIC33FJ06GS101A/102A devices not
have an EXTREF pin; therefore, any data read on the corresponding AN12 input will be invalid.
2011-2012 Microchip Technology Inc.
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NOTES:
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• DACOUT pin to provide DAC output
20.0 HIGH-SPEED ANALOG
• DACOUT amplifier (1x, 1.8x)
COMPARATOR
• Selectable hysteresis
Note 1: This data sheet summarizes the features
• DAC has three ranges of operation:
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
- AVDD/2
- Internal Reference (INTREF)
- External Reference (EXTREF)
• ADC sample and convert trigger capability
• Disable capability reduces power consumption
• Functional support for PWM module:
- PWM duty cycle control
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 45. “High-Speed
Analog Comparator” (DS70296) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
- PWM period control
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- PWM Fault detect
20.2 Module Description
Figure 20-1 shows a functional block diagram of one
analog comparator from the high-speed analog
comparator module. The analog comparator provides
high-speed operation with a typical delay of 20 ns. The
comparator has a typical offset voltage of ±5 mV. The
negative input of the comparator is always connected
to the DAC circuit. The positive input of the comparator
is connected to an analog multiplexer that selects the
desired source pin.
The high-speed analog comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
20.1 Features Overview
The SMPS comparator module offers the following
major features:
The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter
(ADC) module. Both the comparator and the ADC can
use the same pins at the same time. This capability
enables a user to measure an input voltage with the
ADC and detect voltage transients with the
comparator.
• Eight selectable comparator inputs
• Up to two analog comparators
• 10-bit DAC for each analog comparator
• Programmable output polarity
• Interrupt generation capability
FIGURE 20-1:
HIGH-SPEED ANALOG COMPARATOR MODULE BLOCK DIAGRAM
INSEL<1:0>
CMPxA(1)
CMPxB(1)
Trigger to PWM
M
U
X
CMPx(1)
Pulse Stretcher
and
Digital Filter
0
1
CMPxC(1)
CMPxD(1)
Status
CMPPOL
RANGE
Interrupt Request
DACOUT
AVDD/2
INTREF(2)
M
U
X
DAC
AMP
HGAIN
AVSS
10
CMREF
Output
Buffer(3)
EXTREF(2)
DACOE
Note 1: x = 1 and 2.
2: For the INTREF and EXTREF values, refer to the DAC Module Specifications (Table 25-42) in Section 25.0
“Electrical Characteristics”.
3: The output buffer is shared between the DACs and only one DAC can be enabled to drive this buffer.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
20.3 Module Applications
20.5 DAC Buffer Gain
This module provides a means for the SMPS dsPIC
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
The output of the DAC is buffered/amplified via the
DAC buffer. The block functions as a 1x gain amplifier
or as a 1.8x gain amplifier. The gain selection is con-
trolled via the HGAIN bit in the CMPCONx register.
Using the 1.8x gain option will raise the reference
voltage to the analog comparator to a maximum of
2.8V. Using a higher reference voltage for the analog
comparator can improve the signal-to-noise ratio in an
application.
The comparator module has a high-speed comparator,
an associated 10-bit DAC and a DAC output amplifier
that provide a programmable reference voltage to the
inverting input of the comparator. The polarity of the
comparator output is user-programmable. The output
of the module can be used in the following modes:
20.6 Comparator Input Range
The comparator has an input voltage range from -0.2V
to AVDD + 0.2V, making it a rail-to-rail input.
• Generate an Interrupt
• Trigger an ADC Sample and Convert Process
• Truncate the PWM Signal (current limit)
• Truncate the PWM Period (current minimum)
• Disable the PWM Outputs (Fault latch)
20.7 Digital Logic
The CMPCONx register (see Register 20-1) provides
the control logic that configures the High-Speed Analog
Comparator module. The digital logic provides a pulse
stretcher. The analog comparator can respond to very
fast transient signals. After the comparator output is
given the desired polarity, the signal is passed to this
pulse stretching circuit. The pulse stretching circuit has
an asynchronous set function and a delay circuit that
insure the minimum pulse width is three system clock
cycles wide so that the attached circuitry can properly
respond.
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and con-
vert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
The stretch circuit is followed by a digital filter. The
digital filter is enabled via the FLTREN bit in the
CMPCONx register. The digital filter operates with the
clock specified via the FCLKSEL bit in the CMPCONx
register. The comparator signal must be stable in a high
or low state for at least three of the selected clock
cycles for it to pass through the digital filter.
20.4 DAC
The range of the DAC is controlled via an analog
multiplexer that selects either AVDD/2, an internal
reference source, INTREF, or an external reference
source, EXTREF. The full range of the DAC (AVDD/2)
will typically be used when the chosen input source pin
is shared with the ADC. The reduced range option
(INTREF) will likely be used when monitoring current
levels using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V); therefore, the option of using a reduced
reference range for the comparator extends the
available DAC resolution in these applications. The
use of an external reference enables the user to
During Sleep mode, the clock signal inputs to the
module are disabled. However, the module’s analog
components may continue to function in a reduced
power manner to allow the user to wake-up the device
when a signal is applied to a comparator input.
In Sleep mode, the clocks are stopped; however, the
analog comparator signal has an asynchronous con-
nection across the filter that allows interrupts to be
generated regardless of the stopped clocks.
connect to
application.
a reference that better suits their
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple compar-
ators, and any CMPSIDL bit is set, the entire group of
comparators will be disabled while in Idle mode. The
advantage is reduced power consumption. Moreover,
this behavior reduces complexity in the design of the
clock control logic for this module.
DACOUT, shown in Figure 20-1, can only be
associated with a single comparator at a given time.
Note:
It should be ensured in software that
multiple DACOE bits are not set. The
output on the DACOUT pin will be indeter-
minate if multiple comparators enable the
DAC output.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
20.8 Hysteresis
20.9 Interaction with I/O Buffers
An additional feature of the module is hysteresis con-
trol. Hysteresis can be enabled or disabled and its
amplitude can be controlled by the HYSSEL<1:0> bits
in the CMPCONx register. Three different values are
available: 15 mV, 30 mV and 45 mV. It is also possible
to select the edge (rising or falling) to which hysteresis
is to be applied.
If the module is enabled and a pin has been selected
as the source for the comparator, then the chosen I/O
pad must disable the digital input buffer associated
with the pad to prevent excessive currents in the digital
buffer due to analog input voltages.
20.10 DAC Output Range
Hysteresis control prevents the comparator output from
continuously changing state because of small
perturbations (noise) at the input (see Figure 20-2).
The DAC has a limitation for the maximum reference
voltage input of (AVDD – 1.5) volts. An external
reference voltage input should not exceed this value or
the reference DAC output will become indeterminate.
FIGURE 20-2:
HYSTERESIS CONTROL
20.11 Analog Comparator Registers
Output
The high-speed analog comparator module is
controlled by the following registers:
• CMPCONx: Comparator Control x Register
• CMPDACx: Comparator DAC Control x Register
Hysteresis Range
(15 mV/30 mV/45 mV)
Input
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER
R/W-0
CMPON(1)
U-0
—
R/W-0
CMPSIDL(1)
R/W-0
HYSSEL<1:0>(1)
R/W-0
R/W-0
FLTREN(1)
R/W-0
FCLKSEL(1) DACOE(1)
bit 8
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HGAIN(1)
R/W-0
CMPPOL(1)
R/W-0
RANGE(1)
bit 0
INSEL<1:0>(1)
EXTREF(1) HYSPOL(1) CMPSTAT(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMPON: Comparator Operating Mode bit(1)
1= Comparator module is enabled
0= Comparator module is disabled (reduces power consumption)
bit 14
bit 13
Unimplemented: Read as ‘0’
CMPSIDL: Stop in Idle Mode bit(1)
1= Discontinues module operation when device enters Idle mode.
0= Continues module operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit that is set to ‘1’ disables all comparators while
in Idle mode.
bit 12-11
HYSSEL<1:0>: Comparator Hysteresis Select bits(1)
11= 45 mV hysteresis
10= 30 mV hysteresis
01= 15 mV hysteresis
00= No hysteresis is selected
bit 10
bit 9
FLTREN: Digital Filter Enable bit(1)
1= Digital filter is enabled
0= Digital filter is disabled
FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit(1)
1= Digital filter and pulse stretcher operate with the PWM clock
0= Digital filter and pulse stretcher operate with the system clock
bit 8
DACOE: DAC Output Enable(1)
1= DAC analog voltage is output to DACOUT pin(2)
0= DAC analog voltage is not connected to DACOUT pin
bit 7-6
INSEL<1:0>: Input Source Select for Comparator bits(1)
11= Select CMPxD input pin
10= Select CMPxC input pin
01= Select CMPxB input pin
00= Select CMPxA input pin
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: DACOUT can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
3: For the INTREF value, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical
Characteristics”.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER (CONTINUED)
bit 5
EXTREF: Enable External Reference bit(1)
1= External source provides reference to DAC (maximum DAC voltage determined by external
voltage source)
0= Internal reference sources provide reference to DAC (maximum DAC voltage determined by
RANGE bit setting)
bit 4
HYSPOL: Comparator Hysteresis Polarity Select bit(1)
1= Hysteresis is applied to the falling edge of the comparator output
0= Hysteresis is applied to the rising edge of the comparator output
bit 3
bit 2
CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit(1)
HGAIN: DAC Gain Enable bit(1)
1= Reference DAC output to comparator is scaled at 1.8x
0= Reference DAC output to comparator is scaled at 1.0x
bit 1
bit 0
CMPPOL: Comparator Output Polarity Control bit(1)
1= Output is inverted
0= Output is non-inverted
RANGE: Selects DAC Output Voltage Range bit(1)
1= High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD
0= Low Range: Max DAC Value = INTREF(3)
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: DACOUT can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DAC output by setting their respective DACOE bit.
3: For the INTREF value, refer to the DAC Module Specifications (Table 25-42) in Section 25.0 “Electrical
Characteristics”.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 20-2: CMPDACx: COMPARATOR DAC CONTROL x REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CMREF<9:8>(1)
R/W-0
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
CMREF<7:0>(1)
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
CMREF<9:0>: Comparator Reference Voltage Select bits(1)
1111111111= (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on RANGE
bit or (CMREF * EXTREF/1024) if EXTREF is set
•
•
•
0000000000= 0.0 volts
Note 1: These bits are not implemented in dsPIC33FJ06GS101A/102A devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
The constant current source module is a precision
current generator and is used in conjunction with ADC
to measure the resistance of external resistors
21.0 CONSTANT CURRENT
SOURCE
connected to device pins.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
21.1 Features Overview
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to Section 19.
“Inter-Integrated Circuit (I2C™)”
(DS70195) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
The constant current source module offers the following
major features:
• Constant current generator (10 µA nominal)
• Internal selectable connection to one out of four pins
• Enable/disable bit
21.2 Module Description
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Figure 21-1 shows a functional block diagram of the
constant current source module. It consists of a
precision current generator with a nominal value of
10 µA. The module can be enabled and disabled using
the ISRCEN bit in the ISRCCON register. The output
of the current generator is internally connected to one
out of up to 4 pins. The OUTSEL<2:0> bits in the
ISRCCON register allow selection of the target pin.
The current source is calibrated during testing.
FIGURE 21-1:
CONSTANT CURRENT SOURCE MODULE BLOCK DIAGRAM
Constant Current Source
ISRC1
ISRC2
ISRC3
M
U
X
ISRC4
ISRCEN
OUTSEL<2:0>
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
21.3 Current Source Control Register
(1)
REGISTER 21-1: ISRCCON: CONSTANT CURRENT SOURCE CONTROL REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
bit 8
ISRCEN
OUTSEL<2:0>
bit 15
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ISRCCAL<5:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ISRCEN: Current Source Enable bit
1= Current source is enabled
0= Current source is disabled
bit 14-11
bit 10-8
Unimplemented: Read as ‘0’
OUTSEL<2:0>: Output Current Select bits
111= Reserved
110= Reserved
101= Reserved
100= Select input pin, ISRC4 (AN4)
011= Select input pin, ISRC3 (AN5)
010= Select input pin, ISRC2 (AN6)
001= Select input pin, ISRC1 (AN7)
000= No output is selected
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ISRCCAL<5:0>: Current Source Calibration bits
The calibration value must be copied from Flash address, 0x800840, into these bits. Refer to the
Constant Current Source Calibration Register (Register 22-1) in Section 22.0 “Special Features”
for more information.
Note 1: This register is available in the dsPIC33FJ09GS302 device only.
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22.1 Configuration Bits
22.0 SPECIAL FEATURES
The configuration bytes are implemented as volatile
memory. This means that configuration data must be
programmed each time the device is powered up. Con-
figuration data is stored in the words at the top of the
on-chip program memory space, known as the Flash
Configuration Words. Their specific locations are
shown in Table 22-1 and Table 22-2. The configuration
data is automatically loaded from the Flash Configura-
tion Words to the proper Configuration registers during
device Resets.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 24. “Programming and Diag-
nostics” (DS70207) and Section 25.
“Device Configuration” (DS70194)
in the “dsPIC33F/PIC24H Family
Reference Manual”, which are avail-
able from the Microchip web site
(www.microchip.com).
Note:
Configuration data is reloaded on all types
of device Resets.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration byte for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper 2 bytes of all Flash Configuration Words in
program memory should always be ‘1111 1111 1111
1111’. This makes them appear to be NOPinstructions
in the remote event that their locations are ever exe-
cuted by accident. Since Configuration bits are not
implemented in the corresponding locations, writing
‘1’s to these locations has no effect on device
operation.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 family of devices includes several
features that are included to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These features are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
Note:
Performing a page erase operation on the
last page of program memory, clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
• Brown-out Reset (BOR)
The Configuration Flash Byte maps are shown in
Table 22-1 and Table 22-2.
The Constant Current Source Calibration register is
shown in Register 22-1.
2011-2012 Microchip Technology Inc.
DS75018C-page 251
TABLE 22-1: CONFIGURATION FLASH BYTES FOR dsPIC33FJ06GS001/101A/X02A DEVICES
Address
Name
Bits 23-8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
000FF0 FICD
000FF4 FWDT
000FF6 FOSC
000FF8 FOSCSEL
000FFA FGS
—
—
—
—
—
Reserved(1)
FWDTEN
—
—
JTAGEN
PLLKEN
IOL1WAY
—
Reserved(2)
—
—
ICS<1:0>
WDTPRE
WDTPOST<3:0>
FCKSM<1:0>
—
—
—
—
—
—
OSCIOFNC
—
POSCMD<1:0>
FNOSC<2:0>
IESO
—
—
—
—
GCP
GWRP
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved for use by development tools.
2: This bit is reserved; program as ‘0’.
TABLE 22-2: CONFIGURATION FLASH BYTES FOR dsPIC33FJ09GS302 DEVICES
Address
Name
Bits 23-8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0017F0 FICD
0017F4 FWDT
0017F6 FOSC
0017F8 FOSCSEL
0017FA FGS
—
—
—
—
—
Reserved(1)
FWDTEN
—
—
JTAGEN
PLLKEN
IOL1WAY
—
Reserved(2)
—
—
ICS<1:0>
WDTPRE
WDTPOST<3:0>
FCKSM<1:0>
—
—
—
—
—
—
OSCIOFNC
—
POSCMD<1:0>
FNOSC<2:0>
GCP
IESO
—
—
—
—
GWRP
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved for use by development tools.
2: This bit is reserved; program as ‘0’.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 22-1: CONSTANT CURRENT SOURCE CALIBRATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
CCSCAL<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-6
bit 5-0
Unimplemented: Read as ‘0’
CCSCAL<5:0>: Constant Current Source Calibration bits
The value of these bits must be copied into the ISRCCAL<5:0> bits (ISRCCON<5:0>). Refer to the
Current Source Control register (Register 21-1) in Section 21.0 “Constant Current Source”.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION
Bit Field
Description
General Segment Code-Protect bit
GCP
1= User program memory is not code-protected
0= Code protection is enabled for the entire program memory space
GWRP
IESO
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
Two-Speed Oscillator Start-up Enable bit
1= Start up device with FRC, then automatically switch to the user-selected oscillator source
when ready
0= Start up device with user-selected oscillator source
FNOSC<2:0>
Oscillator Selection bits
111= Fast RC Oscillator with divide-by-N (FRCDIVN)
110= Reserved; do not use
101= Low-Power RC Oscillator (LPRC)
100= Reserved; do not use
011= Primary Oscillator with PLL module (MS + PLL, EC + PLL)
010= Primary Oscillator (MS, HS, EC)
001= Fast RC Oscillator with divide-by-N with PLL module
(FRCDIVN + PLL)
000= Fast RC Oscillator (FRC)
FCKSM<1:0>
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
OSCIOFNC
POSCMD<1:0>
OSC2 Pin Function bit (except in MS and HS modes)
1= OSC2 is the clock output
0= OSC2 is the general purpose digital I/O pin
Primary Oscillator Mode Select bits
11= Primary Oscillator is disabled
10= HS Crystal Oscillator mode (10 MHz-32 MHz)
01= MS Crystal Oscillator mode (3 MHz-10 MHz)
00= EC (External Clock) mode (DC-32 MHz)
FWDTEN
Watchdog Timer Enable bit
1= Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN
bit in the RCON register will have no effect)
0= Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing
the SWDTEN bit in the RCON register)
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
•
•
•
0001= 1:2
0000= 1:1
DS75018C-page 254
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
PLLKEN
Description
PLL Lock Enable bit
1= Clock switch to PLL source will wait until the PLL lock signal is valid
0= Clock switch will not wait for the PLL lock signal
JTAGEN
ICS<1:0>
JTAG Enable bit
1= JTAG is enabled
0= JTAG is disabled
ICD Communication Channel Select bits
11= Communicate on PGEC1 and PGED1
10= Communicate on PGEC2 and PGED2
01= Communicate on PGEC3 and PGED3
00= Reserved, do not use
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
22.2 On-Chip Voltage Regulator
22.3 Brown-out Reset (BOR)
The devices power their core digital logic at a nominal
2.5V. This can create a conflict for designs that are
required to operate at a higher typical voltage, such as
3.3V. To simplify system design, all devices incorporate
an on-chip regulator that allows the device to run its core
logic from VDD.
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 22-1). This helps to maintain the stability of the
regulator. The recommended value for the filter
capacitor is provided in Table 25-13, located in
Section 25.1 “DC Characteristics”.
A BOR generates a Reset pulse which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until the OST expires. If the PLL is used, the clock
is held until the LOCK bit (OSCCON<5>) is ‘1’.
Note: It is important for the low-ESR capacitor to be
placed as close as possible to the VCAP pin.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0and
a crystal oscillator is being used, then a nominal delay
of, TFSCM = 100, is applied. The total delay in this case
is TFSCM.
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and resets the
device should VDD fall below the BOR threshold
voltage.
FIGURE 22-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
(1,2,3)
3.3V
dsPIC33F
VDD
VCAP
VSS
CEFC
10
µF
Tantalum
Note 1: These are typical operating voltages. Refer to
Table 25-13 located in Section 25.1 “DC
Characteristics” for the full operating ranges
of VDD.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
3: Typical VCAP pin voltage = 2.5V when
VDD VDDMIN.
DS75018C-page 256
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
22.4.2
SLEEP AND IDLE MODES
22.4 Watchdog Timer (WDT)
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP bit (RCON<3>)
or IDLE bit (RCON<2>) will need to be cleared in
software after the device wakes up.
The Watchdog Timer (WDT) is driven by the LPRC
oscillator. When the WDT is enabled, the clock source is
also enabled.
22.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit
(FWDT<4>). With a 32 kHz input, the prescaler yields
a nominal WDT time-out period (TWDT) of 1 ms in 5-bit
mode or 4 ms in 7-bit mode.
22.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register
(FWDT<7>). When the FWDTEN Configuration bit is
set, the WDT is always enabled.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC<2:0> bits) or by
hardware (i.e., Fail-Safe Clock Monitor)
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 22-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPOST<3:0>
WDTPRE
Prescaler
SWDTEN
FWDTEN
WDT
Wake-up
1
RS
RS
Postscaler
(Divide-by-N1)
(Divide-by-N2)
WDT
Reset
LPRC Clock
0
WDT Window Select
CLRWDTInstruction
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
22.5 JTAG Interface
22.7 In-Circuit Debugger
A JTAG interface is implemented, which supports
boundary scan device testing, as well as in-circuit
programming. Detailed information on this interface will
be provided in future revisions of this document.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices provide simple debug-
ging functionality through the PGECx (Emulation/
Debug Clock) and PGEDx (Emulation/Debug Data) pin
functions.
22.6
In-Circuit Serial Programming
Any of the three pairs of debugging clock/data pins can
be used:
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 family of digital signal controllers
can be serially programmed while in the end
application circuit. This is done with two lines for clock
and data, and three other lines for power, ground and
the programming sequence. Serial programming
allows customers to manufacture boards with
unprogrammed devices and then program the digital
signal controller just before shipping the product. Serial
programming also allows the most recent firmware or a
custom firmware to be programmed. Refer to the
“dsPIC33F/PIC24H Flash Programming Specification”
(DS70152) for details about In-Circuit Serial
Programming (ICSP™).
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS75018C-page 258
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
23.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
“dsPIC33F/PIC24H Family Reference
Manual” sections.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The instruction set for this family of dsPIC33F devices
is identical to the instruction set for dsPIC30F devices.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
• The first source operand, which is a register ‘Wb’
without any address modifier
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
The MACclass of DSP instructions can use some of the
following operands:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• The accumulator (A or B) to be used (required
operand)
• DSP operations
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
• Control operations
Table 23-1 shows the general symbols used in
describing the instructions.
The dsPIC33F instruction set summary in Table 23-2
lists all the instructions, along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The amount of shift specified by a W register,
‘Wn’, or a literal value
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
The control instructions can use some of the following
operands:
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
• A program memory address
• The mode of the table read and table write
instructions
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could be either the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Most instructions are
a
single word. Certain
(unconditional/computed branch), indirect CALL/GOTO,
all table reads and writes and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve
skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles.
double-word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
Note:
For more details on the instruction set,
refer to the “16-Bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means “literal defined by text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double-Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
4-bit bit selection field (used in word-addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
C, DC, N, OV, Z
Expr
f
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16384}
lit14
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
Field does not require an entry, can be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (Direct Addressing)
DS75018C-page 260
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Wm*Wn
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 Destination Working registers {W0...W15}
One of 16 Source Working registers {W0...W15}
W0 (Working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
Wy
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
16-bit Signed Add to Accumulator
f = f + WREG + (C)
1
2
3
4
ADDC
AND
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
Wd = Wb + lit5 + (C)
1
f = f .AND. WREG
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
1
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
Wd = Wb .AND. Ws
1
N,Z
Wd = Wb .AND. lit5
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N,Z
5
6
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if Greater Than or Equal
Branch if Unsigned Greater Than or Equal
Branch if Greater Than
Branch if Unsigned Greater Than
Branch if Less Than or Equal
Branch if Unsigned Less Than or Equal
Branch if Less Than
None
None
None
None
None
None
None
Branch if Unsigned Less Than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Accumulator A Overflow
Branch if Accumulator B Overflow
Branch if Overflow
None
None
None
Branch if Accumulator A Saturated
Branch if Accumulator B Saturated
Branch Unconditionally
Branch if Zero
None
None
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
7
8
9
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
1
None
Bit Toggle Ws
1
None
DS75018C-page 262
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
10
BTSC
BTSS
BTST
BTSC
BTSC
BTSS
BTSS
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test f, Skip if Clear
1
1
1
1
1
None
None
None
None
(2 or 3)
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
(2 or 3)
11
12
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
C
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Ws,Wb
Z
13
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call Indirect Subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, Skip if =
Compare Wb with Wn, Skip if >
Compare Wb with Wn, Skip if <
Compare Wb with Wn, Skip if
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = Decimal Adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
DEC
Wd = Ws – 1
27
28
DEC2
DISI
DEC2
DEC2
DEC2
DISI
f = f – 2
f,WREG
Ws,Wd
#lit14
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k Instruction Cycles
2011-2012 Microchip Technology Inc.
DS75018C-page 263
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
29
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
Wm,Wn
Signed 16/16-bit Integer Divide
1
1
1
1
1
2
2
1
18
18
18
18
18
2
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
Wm,Wn
Signed 32/16-bit Integer Divide
Wm,Wn
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit14 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
DO
2
None
32
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to Address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to Indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link Frame Pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f
f = Logical Right Shift f
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate
,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
None
None
None
None
None
None
None
None
None
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit Literal to Wn
Move 8-bit Literal to Wn
Move Wn to f
MOV.b
MOV
MOV
Wso,Wdo
Move Ws to Wd
MOV
WREG,f
Move WREG to f
MOV.D
MOV.D
MOVSAC
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Prefetch and Store Accumulator
Ws,Wnd
47
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
DS75018C-page 264
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
48
MPY
MPY
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
1
1
1
1
1
1
1
1
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
OA,OB,OAB,
SA,SB,SAB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
49
50
MPY.N
MSC
MPY.N
-(Multiply Wm by Wn) to Accumulator
None
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
,
AWB
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
52
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
All
None
None
None
None
WDTO,Sleep
None
None
None
None
None
None
None
None
C,N,Z
C,N,Z
C,N,Z
N,Z
55
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
1
PUSH
Wso
Wns
1
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
2
1
56
57
PWRSAV
RCALL
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
2
Computed Call
2
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software Device Reset
1
1
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
1
Return from interrupt
3 (2)
#lit10,Wn
Return with Literal in Wn
3 (2)
Return from Subroutine
3 (2)
1
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
RLC
f,WREG
Ws,Wd
f
1
RLC
1
64
65
RLNC
RRC
RLNC
1
RLNC
f,WREG
Ws,Wd
f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
1
N,Z
RLNC
1
N,Z
RRC
1
C,N,Z
C,N,Z
C,N,Z
RRC
f,WREG
Ws,Wd
1
RRC
1
2011-2012 Microchip Technology Inc.
DS75018C-page 265
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
66
RRNC
SAC
RRNC
RRNC
RRNC
SAC
f
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
N,Z
f,WREG
Ws,Wd
N,Z
67
Acc,#Slit4,Wdo
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = Sign-Extended Ws
f = 0xFFFF
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
71
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
WREG = Left Shift f
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
72
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
SUB
SUB
Wd = Wb – Ws
SUB
Wd = Wb – lit5
73
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
f = f – WREG – (C)
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
74
75
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
Wd = lit5 – Wb – (C)
Wn = Nibble Swap Wn
Wn = Byte Swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
76
SWAP
Wn
None
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
None
XOR
f
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
Wnd = Zero-Extend Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
N,Z
83
ZE
ZE
C,Z,N
DS75018C-page 266
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
24.1 MPLAB Integrated Development
Environment Software
24.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2011-2012 Microchip Technology Inc.
DS75018C-page 267
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
24.2 MPLAB C Compilers for Various
Device Families
24.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
24.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
24.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS75018C-page 268
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
24.7 MPLAB SIM Software Simulator
24.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
24.10 PICkit 3 In-Circuit Debugger/
Programmer and
24.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer’s PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2011-2012 Microchip Technology Inc.
DS75018C-page 269
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
24.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
24.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
24.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS75018C-page 270
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
25.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 electrical
characteristics. Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings are listed below. Exposure to these maximum rating conditions for extended periods may
affect device reliability. Functional operation of the device at these or any other conditions above the parameters
indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS(3).................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS, when VDD 3.0V(3).................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3)........................................ -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA
Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2).
3: See the “Pin Diagrams” section for 5V tolerant pins.
2011-2012 Microchip Technology Inc.
DS75018C-page 271
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
25.1 DC Characteristics
TABLE 25-1: OPERATING MIPS vs. VOLTAGE
Maximum MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
Characteristic
dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302
—
—
VBOR-3.6V(1)
VBOR-3.6V(1)
-40°C to +85°C
-40°C to +125°C
40
40
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 25-11 for BOR values.
TABLE 25-2: THERMAL OPERATING CONDITIONS
Rating
Industrial Temperature Devices
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Extended Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 25-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 18-Pin SOIC
Package Thermal Resistance, 18-pin PDIP
Package Thermal Resistance, 20-pin SSOP
Package Thermal Resistance, 28-Pin QFN-S
Package Thermal Resistance, 28-pin SSOP
Package Thermal Resistance, 28-Pin SOIC
Package Thermal Resistance, 28-Pin SPDIP
Package Thermal Resistance, 36-Pin VTLA
JA
JA
JA
JA
JA
JA
JA
JA
57
66
64
34
71
47
45
29
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS75018C-page 272
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
Operating Voltage
DC10 VDD
DC12 VDR
Supply Voltage(4)
VBOR
1.8
—
—
3.6
—
V
V
Industrial and Extended
RAM Data Retention
Voltage(2)
DC16 VPOR
DC17 SVDD
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VDD Rise Rate(3)
—
—
—
VSS
—
V
0.03
V/ms 0-3.0V in 0.1s
to Ensure Internal
Power-on Reset Signal
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: This is the limit to which VDD may be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
4: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to
Parameter BO10 in Table 25-11 for BOR values.
2011-2012 Microchip Technology Inc.
DS75018C-page 273
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Operating Current (IDD)(2)
Typical(1)
Max.
Units
Conditions
DC20d
DC20a
DC20b
DC20c
DC21d
DC21a
DC21b
DC21c
DC22d
DC22a
DC22b
DC22c
DC23d
DC23a
DC23b
DC23c
DC24d
DC24a
DC24b
DC24c
DC25d
DC25a
DC25b
DC25c
15
15
15
15
23
23
23
23
25
25
25
25
34
34
34
34
43
43
43
43
83
83
83
83
23
23
23
23
34
34
34
34
38
38
38
38
51
51
51
51
64
64
64
64
125
125
125
125
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
10 MIPS
16 MIPS(3)
20 MIPS(3)
30 MIPS(3)
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
40 MIPS(3)
40 MIPS
See Note 2, except PWM and ADC
are operating at maximum speed
(PTCON2 = 0x0000)
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD; WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are
all zeroed)
• CPU is executing while(1)statement
3: These parameters are characterized but not tested in manufacturing.
DS75018C-page 274
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Typical(1)
Max.
Units
Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(2)
DC40d
DC40a
DC40b
DC40c
DC41d
DC41a
DC41b
DC41c
DC42d
DC42a
DC42b
DC42c
DC43d
DC43a
DC43b
DC43c
DC44d
DC44a
DC44b
DC44c
13
13
13
13
16
16
16
16
17
17
17
17
20
20
20
20
23
23
23
23
21
21
21
21
24
24
24
24
27
27
27
27
32
32
32
32
37
37
37
37
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
10 MIPS
16 MIPS(3)
20 MIPS(3)
30 MIPS(3)
40 MIPS
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Base Idle current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD; WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are
all zeroed)
3: These parameters are characterized but not tested in manufacturing.
2011-2012 Microchip Technology Inc.
DS75018C-page 275
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Power-Down Current (IPD)(2,4)
Typical(1)
Max.
Units
Conditions
DC60d
DC60a
DC60b
DC60c
DC61d
DC61a
DC61b
DC61c
125
135
235
565
40
500
500
500
950
50
A
A
A
A
A
A
A
A
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
Base Power-Down Current
40
50
+25°C
+85°C
+125°C
(3)
Watchdog Timer Current: IWDT
40
50
80
90
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IPD current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ‘1’s)
• VREGS bit (RCON<8>) = 1(i.e., core regulator is set to standby while the device is in Sleep mode)
3: The current is the additional current consumed when the WDT module is enabled. This current should
be added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
DS75018C-page 276
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Typical(1)
Max.
Doze Ratio
Units
Conditions
Doze Current (IDOZE)(2)
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
DC72a
DC72f
DC72g
30
45
23
23
45
23
23
45
23
23
45
23
23
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
16
16
30
16
16
30
16
16
30
16
16
-40°C
+25°C
+85°C
+125°C
3.3V
40 MIPS
40 MIPS
40 MIPS
40 MIPS
1:64
1:128
1:2
3.3V
3.3V
3.3V
1:64
1:128
1:2
1:64
1:128
Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on
the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD; WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are
all zeroed)
• CPU is executing while(1)statement
2011-2012 Microchip Technology Inc.
DS75018C-page 277
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Input Low Voltage
Min.
Typ.(1) Max. Units
Conditions
VIL
DI10
I/O Pins
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.8
V
V
V
V
V
DI15
MCLR
DI16
I/O Pins with OSC1
SDA1, SCL1
SDA1, SCL1
Input High Voltage
DI18
SMBus disabled
SMBus enabled
DI19
VIH
DI20
DI21
I/O Pins Not 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
I/O Pins 5V Tolerant(4)
DI28
DI29
SDA1, SCL1
SDA1, SCL1
0.7 VDD
2.1
—
—
5.5
5.5
V
V
SMBus disabled
SMBus enabled
ICNPU
CNx Pull-up Current
DI30
IIL
—
250
—
A VDD = 3.3V, VPIN = VSS
Input Leakage Current(2,3,4)
DI50
I/O Pins:
4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
—
—
—
—
±2
±8
A
A
VSS VPIN VDD,
Pin at high-impedance
16x Sink Driver Pins
RA3, RA4, RB3, RB4, RB11-RB14
VSS VPIN VDD,
Pin at high-impedance
DI55
DI56
MCLR
OSC1
—
—
—
—
±2
±2
A VSS VPIN VDD
A VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3); characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit; characterized but not tested.
DS75018C-page 278
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.(1) Max. Units
Conditions
IICL
Input Low Injection Current
DI60a
0
—
-5(5,8)
mA All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP and RB5
IICH
Input High Injection Current
DI60b
0
—
+5(6,7,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, RB5 and digital 5V
tolerant designated pins
IICT
Total Input Injection Current
DI60c
(sum of all I/O and control pins)
-20(9)
—
+20(9)
mA Absolute instantaneous
sum of all ± input
injection currents from
all I/O pins
( | IICL + | IICH | )
IICT
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3); characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit; characterized but not tested.
2011-2012 Microchip Technology Inc.
DS75018C-page 279
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
Min.
Typ. Max. Units
Conditions
DO10 VOL
—
—
—
—
—
0.4
0.4
—
V
V
V
V
V
IOL 6 mA, VDD = 3.3V(1)
Output Low Voltage
I/O Pins:
16x Sink Driver Pins – RA3, RA4,
RB3, RB4, RB11-RB14
—
IOL 18 mA, VDD = 3.3V(1)
IOH -6 mA, VDD = 3.3V(1)
IOH -18 mA, VDD = 3.3V(1)
DO20 VOH
Output High Voltage
I/O Pins:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
2.4
2.4
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
—
DO20A VOH1
Output High Voltage
I/O Pins:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
1.5
2.0
3.0
1.5
2.0
3.0
—
—
—
—
—
—
—
—
—
—
—
—
IOH -12 mA, VDD = 3.3V(1)
IOH -11 mA, VDD = 3.3V(1)
IOH -3 mA, VDD = 3.3V(1)
IOH -30 mA, VDD = 3.3V(1)
IOH -25 mA, VDD = 3.3V(1)
IOH -8 mA, VDD = 3.3V(1)
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
V
Note 1: These parameters are characterized, but not tested.
TABLE 25-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V(3)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param.
Symbol
Characteristic
Min.(1) Typ.
Max.
Units
Conditions
BO10
VBOR
BOR Event on VDD Transition
High-to-Low
2.55
—
2.96
V
(See Note 2)
BOR Event is Tied to VDD Core
Voltage Decrease
Note 1: These parameters are for design guidance only and are not tested in manufacturing.
2: The device will operate as normal until the VDDMIN threshold is reached.
3: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS75018C-page 280
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min. Typ.(1) Max. Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10,000
VMIN
—
—
—
E/W -40C to +125C
VPR
VDD for Read
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
—
—
—
—
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications
are violated, -40C to +125C
Supply Current during
Programming
—
—
mA
D137a TPE
D137b TPE
D138a TWW
D138b TWW
Page Erase Time
20.1
19.5
42.3
41.1
26.5
27.3
55.9
57.6
ms TPE = 168517 FRC cycles,
TA = +85°C(2)
Page Erase Time
ms TPE = 168517 FRC cycles,
TA = +125°C(2)
Word Write Cycle Time
Word Write Cycle Time
µs TWW = 355 FRC cycles,
TA = +85°C(2)
µs TWW = 355 FRC cycles,
TA = +125°C(2)
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = ‘b011111(for Minimum), TUN<5:0> = ‘b100000(for
Maximum). This parameter depends on the FRC accuracy (see Table 25-20) and the value of the FRC
Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.
TABLE 25-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristics
Min.
Typ.
Max.
Units
Comments
CEFC
External Filter Capacitor
Value(1)
4.7
10
—
F
Capacitor must be low
series resistance
(< 0.5 Ohms)
Note 1: Typical VCAP voltage = 2.5 volts when VDD VDDMIN.
2011-2012 Microchip Technology Inc.
DS75018C-page 281
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
25.2 AC Characteristics and Timing Parameters
This section defines dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 AC characteristics and timing
parameters.
TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Table 25-1.
FIGURE 25-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 25-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param. Symbol
Characteristic
OSC2 Pin
Min.
Typ. Max. Units
Conditions
DO50 COSCO
—
—
15
pF In XT and HS modes when external
clock is used to drive OSC1
DO56 CIO
DO58 CB
All I/O Pins and OSC2
SCL1, SDA1
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
DS75018C-page 282
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS25
OS30 OS30
OS31 OS31
OS41
OS40
TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.0
10
—
—
10
32
MHz XT
MHz HS
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2)
12.5
25
—
—
—
DC
DC
ns
ns
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
0.625 x TOSC
ns
EC
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
OS40
OS41
OS42
TckR
TckF
GM
CLKO Rise Time(3)
CLKO Fall Time(3)
—
—
14
5.2
5.2
16
—
—
18
ns
ns
External Oscillator
mA/V VDD = 3.3V
TA = +25ºC
Transconductance(4)
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
2011-2012 Microchip Technology Inc.
DS75018C-page 283
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz ECPLL, XTPLL modes
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
mS
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)(2)
0.9
-3
1.5
0.5
3.1
3
%
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula:
DCLK
Peripheral Clock Jitter = -----------------------------------------------------------------------
FOSC
-------------------------------------------------------------
Peripheral Bit Rate Clock
For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz.
DCLK
3%
3%
-------
-----------------------------
---------
SPI SCK Jitter =
=
=
= 0.75%
4
16
32 MHz
--------------------
2 MHz
TABLE 25-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
OS56
OS57
OS58
FHPOUT On-Chip 16x PLL CCO
Frequency
112
118
120
MHz
FHPIN
On-Chip 16x PLL Phase
Detector Input Frequency
7.0
—
7.37
—
7.5
10
MHz
µs
TSU
Frequency Generator Lock
Time
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
DS75018C-page 284
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Param.
Characteristic
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
F20b
FRC
FRC
-2
-5
—
—
+2
+5
%
%
-40°C TA +85°C
VDD = 3.0-3.6V
-40°C TA +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 25-20: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Characteristic
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
F21b
LPRC
LPRC
-20
-70
—
—
+20
+70
%
%
-40°C TA +85°C
VDD = 3.0-3.6V
-40°C TA +125°C VDD = 3.0-3.6V
Note 1: The change of LPRC frequency as VDD changes.
2011-2012 Microchip Technology Inc.
DS75018C-page 285
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.(1) Max. Units
Conditions
DO31
TIOR
I/O Pins: 4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
—
10
25
ns
Refer to Figure 25-1
for test conditions
I/O Pins: 16x Sink Driver Pins
RA3, RA4, RB3, RB4, RB11-RB14
—
—
6
15
25
ns
ns
DO32
TIOF
I/O Pins: 4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
10
Refer to Figure 25-1
for test conditions
I/O Pins: 16x Sink Driver Pins
—
6
15
ns
RA3, RA4, RB3, RB4, RB11-RB14
DI35
DI40
TINP
INTx Pin High or Low Time (input)
CNx High or Low Time (input)
20
2
—
—
—
—
ns
TRBP
TCY
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS75018C-page 286
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2)
Max. Units
Conditions
SY10
SY11
SY12
SY13
TMCL
TPWRT
TPOR
TIOZ
MCLR Pulse Width (low)
Power-up Timer Period
Power-on Reset Delay
2
—
3
—
64
—
—
s
ms
s
s
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
10
30
1.2
I/O High-Impedance from MCLR 0.68
Low or Watchdog Timer Reset
0.72
SY30
TOST
Oscillator Start-up Time
—
1024 TOSC
—
—
TOSC = OSC1 period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2011-2012 Microchip Technology Inc.
DS75018C-page 287
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-5:
TIMER1 AND TIMER2 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 25-1 for load conditions.
(1)
TABLE 25-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic
TxCK High Synchronous,
Min.
Typ.
Max.
Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TCY + 20
—
—
ns Must also meet
Parameter TA15,
Time
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
—
—
ns
TxCK Low Synchronous,
TCY + 20
ns Must also meet
Parameter TA15,
Time
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
—
—
ns
TxCK Input Synchronous,
2 TCY + 40
ns
Period
no prescaler
Synchronous,
with prescaler
Greater of:
40 ns or
—
—
—
N = prescale
value
(2 TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
40
—
—
—
ns
OS60 Ft1
T1CK Oscillator Input
Frequency Range
DC
50
kHz
(oscillator enabled by setting
bit, TCS (T1CON<1>))
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
0.75 TCY + 40
—
1.75 TCY + 40
—
Increment
Note 1: Timer1 is a Type A.
DS75018C-page 288
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param.
Symbol
TTXH
Characteristic
Min.
Typ.
Max. Units
Conditions
TB10
TxCK High Time Synchronous
Greater of:
20 ns or
(TCY + 20)/N
—
—
—
—
ns Must also meet
Parameter TB15
N = prescale
value (1, 8, 64, 256)
TB11
TB15
TTXL
TTXP
TxCK Low Time
Synchronous
Greater of:
20 ns or
(TCY + 20)/N
—
—
ns Must also meet
Parameter TB15
N = prescale
value (1, 8, 64, 256)
TxCK Input Period Synchronous,
no prescaler
TCY + 40
ns N = prescale
value (1, 8, 64, 256)
Synchronous, Greater of:
with prescaler
20 ns or
(TCY + 40)/N
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
2011-2012 Microchip Technology Inc.
DS75018C-page 289
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-6:
INPUT CAPTURE (CAP1) TIMING CHARACTERISTICS
IC1
IC10
IC11
IC15
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Max.
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
IC1 Input Low Time No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
IC1 Input High Time No prescaler
With prescaler
0.5 TCY + 20
10
IC1 Input Period
(TCY + 40)/N
N = prescale value
(1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 25-7:
OUTPUT COMPARE MODULE (OC1) TIMING CHARACTERISTICS
OC1
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10 TccF
OC11 TccR
OC1 Output Fall Time
OC1 Output Rise Time
—
—
—
—
—
—
ns
ns
See Parameter DO32
See Parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
DS75018C-page 290
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC1
OC15
Active
Tri-State
TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC15
OC20
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20
ns
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1: These parameters are characterized but not tested in manufacturing.
2011-2012 Microchip Technology Inc.
DS75018C-page 291
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-9:
HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTx
MP20
PWMx
FIGURE 25-10:
HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-28: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
MP10
MP11
TFPWM
TRPWM
TFD
PWM Output Fall Time
PWM Output Rise Time
—
—
—
2.5
2.5
—
—
—
15
ns
ns
ns
Fault Input to PWM
I/O Change
MP20
MP30
TFH
Minimum PWM Fault Pulse
Width
8
—
—
ns
ns
DTC<10> = 10
ACLK = 120 MHz
MP31
MP32
TPDLY
ACLK
Tap Delay
1.04
—
—
—
—
PWM Input Clock
120
MHz See Note 2, Note 3
Note 1: These parameters are characterized but not tested in manufacturing.
2: This parameter is a maximum allowed input clock for the PWM module.
3: The maximum value for this parameter applies to dsPIC33FJ06GS101A/102A/202A/302 devices only.
DS75018C-page 292
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Master
Transmit Only
(Half-Duplex)
Master
Slave
Maximum
Data Rate
Transmit/Receive Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
(Full-Duplex)
15 MHz
9 MHz
Table 25-30
—
—
0,1
1
0,1
0,1
0,1
0
0,1
1
—
—
—
—
—
—
Table 25-31
—
9 MHz
Table 25-32
—
0
1
15 MHz
11 MHz
15 MHz
11 MHz
—
—
—
—
Table 25-33
Table 25-34
Table 25-35
Table 25-36
1
0
1
1
0
0
1
0
0
0
0
FIGURE 25-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP30, SP31
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 293
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
SP30, SP31
MSb
LSb
SDOx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
SP20
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
15
—
MHz See Note 3
TscF
TscR
TdoF
TdoR
ns
ns
ns
ns
ns
ns
See Parameter DO32
and Note 4
SP21
SP30
SP31
SP35
SP36
SCKx Output Rise Time
—
—
—
—
30
—
—
—
6
—
—
—
20
—
See Parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
TdiV2scH, SDOx Data Output Setup to
—
TdiV2scL
First SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 294
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
LSb
SDOx
SDIx
SP30, SP31
SP40
MSb In
SP41
LSb In
Bit 14 - - - -1
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
SP20
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
9
MHz See Note 3
TscF
TscR
TdoF
TdoR
—
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
and Note 4
SP21
SP30
SP31
SP35
SP36
SP40
SP41
SCKx Output Rise Time
—
—
—
—
30
30
30
—
—
—
6
—
—
—
20
—
—
—
See Parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
2011-2012 Microchip Technology Inc.
DS75018C-page 295
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30, SP31
MSb In
SP30, SP31
LSb In
Bit 14 - - - -1
SP40
SP41
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
Maximum SCKx Frequency
—
—
9
MHz -40ºC to +125ºC and
see Note 3
SP20
SP21
SP30
SP31
SP35
SP36
SP40
SP41
TscF
TscR
TdoF
TdoR
SCKx Output Fall Time
—
—
—
—
—
30
30
30
—
—
—
—
6
—
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
and Note 4
SCKx Output Rise Time
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 296
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP72
SP73
SP73
SP72
SCKx
(CKP = 1)
SP35
MSb
LSb
SDOx
SDIx
Bit 14 - - - - - -1
SP30,SP31
SP51
MSb In
SP41
LSb In
Bit 14 - - - -1
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 297
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP72
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
MHz See Note 3
TscF
TscR
TdoF
TdoR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter
DO32 and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter
DO31 and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter
DO32 and Note 4
—
See Parameter
DO31 and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
30
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
TssH2doZ SSx to SDOx Output
10
1.5 TCY + 40
—
See Note 4
See Note 4
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 298
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP72
SP73
SP70
SP73
SP72
SCKx
(CKP = 1)
SP35
SP52
MSb
LSb
Bit 14 - - - - - -1
SDOx
SDIx
SP30,SP31
SP51
MSb In
SP41
LSb In
Bit 14 - - - -1
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 299
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP72
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
MHz See Note 3
TscF
TscR
TdoF
TdoR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter
DO32 and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter
DO31 and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter
DO32 and Note 4
—
See Parameter
DO31 and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
30
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
TssH2doZ SSx to SDOx Output
10
1.5 TCY + 40
—
See Note 4
See Note 4
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 300
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-17:
SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP72
SP73
SP73
SP72
SCKX
(CKP = 1)
SP35
LSb
MSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 301
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP72
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
MHz See Note 3
TscF
TscR
TdoF
TdoR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter
DO32 and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter
DO31 and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter
DO32 and Note 4
—
See Parameter
DO31 and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
30
120
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
TssH2doZ SSx to SDOx Output
10
See Note 4
See Note 4
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 302
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP72
SP73
SP72
SCKX
(CKP = 1)
SP73
SP35
MSb
LSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 303
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP72
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
MHz See Note 3
TscF
TscR
TdoF
TdoR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter
DO32 and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter
DO31 and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter
DO32 and Note 4
—
See Parameter
DO31 and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
30
120
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
TssH2doZ SSx to SDOx Output
10
See Note 4
See Note 4
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS75018C-page 304
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-19:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL1
SDA1
IM31
IM34
IM30
IM33
Start
Condition
Stop
Condition
Note: Refer to Figure 25-1 for load conditions.
FIGURE 25-20:
I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL1
IM11
IM26
IM10
IM33
IM25
SDA1
In
IM45
IM40
IM40
SDA1
Out
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 305
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-37: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.(1)
Max.
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
s
s
pF
ns
1 MHz mode(2) TCY/2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDA1 and SCL1 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 pF to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
SDA1 and SCL1 100 kHz mode
—
CB is specified to be
from 10 pF to 400 pF
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
250
100
40
0
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
IM50
IM51
CB
Bus Capacitive Loading
400
390
TPGD
Pulse Gobbler Delay
65
See Note 3
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit
(I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
DS75018C-page 306
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-21:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL1
SDA1
IS34
IS31
IS30
IS33
Stop
Condition
Start
Condition
FIGURE 25-22:
I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL1
IS30
IS26
IS31
IS33
IS25
SDA1
In
IS45
IS40
IS40
SDA1
Out
2011-2012 Microchip Technology Inc.
DS75018C-page 307
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-38: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Max. Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
s
s
IS11
THI:SCL Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1 MHz mode(2)
0.6
—
s
Device must operate at a
minimum of 10 MHz
0.5
—
300
300
100
1000
300
300
—
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
s
s
pF
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL
TR:SCL
SDA1 and SCL1 100 kHz mode
—
CB is specified to be from
10 pF to 400 pF
Fall Time
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
—
SDA1 and SCL1 100 kHz mode
CB is specified to be from
10 pF to 400 pF
Rise Time
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
250
100
100
0
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
THD:STO Stop Condition
Hold Time
—
—
TAA:SCL Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
Note 1: Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
DS75018C-page 308
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
=
TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V and 3.6V
(unless otherwise stated)
Operating temperature
(2)
AC CHARACTERISTICS
Param. Symbol
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ.
Max.
Units
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
—
—
—
—
—
AVDD is internally connected
to VDD on 18-pin and 28-pin
devices. See parameters
(DC10) in Table 25-4.
—
—
—
AVSS is internally connected to
VSS on 18-pin and 28-pin
devices
Analog Input
AD10
AD11
AD12
AD13
VINH-VINL Full-Scale Input Span
VSS
AVSS
—
—
VDD
AVDD
—
V
V
VIN
IAD
Absolute Input Voltage
Operating Current
Leakage Current
—
8
mA
—
—
±0.6
—
A VINL = AVSS = 0V,
AVDD = 3.3V,
Source Impedance = 100
AD17
RIN
Recommended Impedance
of Analog Voltage Source
—
—
100
DC Accuracy @ 1.5 Msps for 18 and 28-Pin Devices
AD20a Nr
AD21a INL
Resolution
10 data bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-0.5
-0.9
—
-0.3/+0.5
±0.6
10
+1.2
+0.9
20
LSb See Note 3
LSb See Note 3
LSb See Note 3
LSb See Note 3
AD22a DNL
AD23a GERR
AD24a EOFF
Offset Error
—
10
20
(1)
AD25a
—
Monotonicity
—
—
—
—
Guaranteed
DC Accuracy @ 2.0 Msps for 18 and 28-Pin Devices
AD20b Nr
Resolution
10 data bits
AD21b INL
AD22b DNL
AD23b GERR
AD24b EOFF
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
-1.5
—
±1.5
±2
+2.8
+2.8
20
LSb
LSb
LSb
LSb
—
10
Offset Error
—
10
20
(1)
AD25b
—
Monotonicity
—
—
—
Guaranteed
DC Accuracy @ 2.0 Msps for 20 and 36-Pin Devices
AD20c Nr
Resolution
10 data bits
AD21c INL
AD22c DNL
AD23c GERR
AD24c EOFF
Integral Nonlinearity
Differential Nonlinearity
Gain Error
> -2
> -1
—
±0.5
±0.5
10
< 2
< 1
20
20
—
LSb See Note 3
LSb See Note 3
LSb See Note 3
LSb See Note 3
Offset Error
—
10
(1)
AD25c
—
Monotonicity
—
—
—
Guaranteed
Note 1: The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog
modules, such as the ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
Parameter BO10 in Table 25-11 for BOR values.
3: These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2012 Microchip Technology Inc.
DS75018C-page 309
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V and 3.6V
(unless otherwise stated)
Operating temperature
(2)
AC CHARACTERISTICS
Param. Symbol
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ.
Max.
Units
Conditions
Dynamic Performance
AD30
AD31
AD32
AD33
AD34
THD
Total Harmonic Distortion
Signal to Noise and Distortion
Spurious Free Dynamic Range
Input Signal Bandwidth
—
—
—
—
—
-73
58
—
—
—
1
dB
dB
SINAD
SFDR
FNYQ
-73
—
dB
MHz
bits
ENOB
Effective Number of Bits
9.4
—
Note 1: The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog
modules, such as the ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
Parameter BO10 in Table 25-11 for BOR values.
3: These parameters are characterized by similarity, but are not tested in manufacturing.
TABLE 25-40: 10-BIT HIGH-SPEED ADC MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic
Min.
Clock Parameters
Typ.(1)
Max.
Units
Conditions
AD50b TAD
ADC Clock Period
35.8
—
—
—
ns
—
Conversion Rate
AD55b tCONV
AD56b FCNV
Conversion Time
—
14 TAD
Throughput Rate
Devices with Single SAR
—
—
2.0
10
Msps
s
Timing Parameters
1.0 —
AD63b tDPU
Time to Stabilize Analog Stage
from ADC Off to ADC On
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 25-23:
ANALOG-TO-DIGITAL CONVERSION TIMING PER INPUT
tCONV
Trigger Pulse
TAD
1
ADC Clock
ADC Data
9
8
2
0
Old Data
New Data
ADBUFxx
CONV
DS75018C-page 310
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-41: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS(2)
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic
Min.
Typ.
Max.
Units
Comments
CM10
CM11
VIOFF
VICM
Input Offset Voltage
-58
0
+14/-40
—
66
mV
V
Input Common-Mode
Voltage Range(1)
AVDD
CM14
TRESP
Large Signal Response
21
30
49
ns V+ input step of 100 mv while
V- input held at AVDD/2. Delay
measured from analog input pin to
PWM output pin.
Note 1: These parameters are for design guidance only and are not tested in manufacturing.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 25-11 for BOR values.
TABLE 25-42: DAC MODULE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
AC and DC CHARACTERISTICS(2)
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic
Min.
Typ.
Max.
Units
Comments
DA01
DA08
DA02
DA03
EXTREF External Voltage Reference(1)
INTREF Internal Voltage Reference(1)
0
—
AVDD – 1.6
1.35
V
V
1.15
1.25
CVRES
INL
Resolution
10
Bits
Integral Nonlinearity Error
-7
-1
+7
LSB AVDD = 3.3V,
DACREF = (AVDD/2)V
DA04
DA05
DA06
DA07
DNL
EOFF
EG
Differential Nonlinearity Error
Offset Error
-5
-0.5
-0.8
+5
2.6
LSB
%
0.4
0.4
711
Gain Error
Settling Time(1)
-1.8
5.2
%
TSET
1551
2100
ns
Measured when
RANGE = 1(high range)
and the CMREF<9:0> bits
transition from 0x1FF to
0x300
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to
Parameter BO10 in Table 25-11 for BOR values.
2011-2012 Microchip Technology Inc.
DS75018C-page 311
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-43: DAC OUTPUT (DACOUT PIN) DC SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS(1)
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic
Min.
Typ.
Max.
Units
Comments
DA11 RLOAD
CLOAD
DA12 IOUT
Resistive Output Load
Impedance
3K
—
—
Ohm
—
Output Load
Capacitance
—
—
300
—
35
—
pF Including output pin
capacitance
Output Current Drive
Strength
200
µA Sink and source
DA13 VRANGE Output Drive Voltage AVSS + 250 mV
Range at Current
AVDD – 900 mV
V
Drive of 200 mA
DA14 VLRANGE Output Drive Voltage
Range at Reduced
AVSS + 5 mV
—
—
—
AVDD – 500 mV
1.3 x IOUT
V
Current Drive of 50 mA
DA15 IDD
Current Consumed
when Module Is
Enabled
µA Module will always con-
sume this current even if
no load is connected to
the output
DA16 ROUTON Output Impedance
when Module is
—
—
820
—
Ohms
Enabled
DA30 VOFFSET Input Offset Voltage
10
10
mV
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 25-11 for BOR values.
TABLE 25-44: DAC GAIN STAGE TO COMPARATOR SPECIFICATIONS
Standard Operating Conditions
(unless otherwise stated)
DC CHARACTERISTICS(1)
Operating temperature: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic
Min.
Typ.
Max.
Units
Conditions
DA15
IDD
Current Consumed when
Module Is Enabled.
—
60
—
µA Module will always consume this
current even if no load is
connected to the output
DA32
DA33
G
Amplifier Gain
—
—
—
1.0
1.8
2.0
—
—
—
—
—
GBWP
Gain Bandwidth Product
MHz At 1 pF load capacitance.
Measured with sine wave output
signal of 1V peak-to-peak with a
midpoint value of 1.2V. Voltage
excursion from 0.7 to 1.7V.
DA34
DA07
SR
TS
Slew Rate
—
—
5
—
—
V/µs Slew rate between 10% and 90%
of AVDD
Settling Time
200
ns
Settling time to 3%
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 25-11 for BOR values.
DS75018C-page 312
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-45: CONSTANT CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions
(unless otherwise stated)
Operating temperature: -40°C TA +85°C for Industrial
DC CHARACTERISTICS(1)
-40°C TA +125°C for Extended
Param. Symbol Characteristic
Min.
Typ. Max. Units
Conditions
CC01
CC02
IDD
Current Consumption
—
—
30
±3
—
—
µA
%
IREG
Regulation of Current with
Voltage On
CC03
IOUT
Current Output at Terminal
—
10
—
µA
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer
to Parameter BO10 in Table 25-11 for BOR values.
2011-2012 Microchip Technology Inc.
DS75018C-page 313
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 314
2011-2012 Microchip Technology Inc.
26.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 26-1:
VOH – 4x DRIVER PINS
FIGURE 26-3:
.
VOL – 4x DRIVER PINS
3.6V
3.6V
3.3V
3.3V
3V
3V
Absolute Maximum
Absolute Maximum
FIGURE 26-4:
VOL – 16x DRIVER PINS
FIGURE 26-2:
VOH – 16x DRIVER PINS
3.6V
3.6V
3.3V
3.3V
3V
Absolute Maximum
3V
Absolute Maximum
FIGURE 26-5:
TYPICAL IPD CURRENT @ VDD = 3.3V
FIGURE 26-7:
TYPICAL IDD CURRENT @ VDD = 3.3V, +25ºC
450
400
350
300
250
200
150
100
50
90
85
80
75
70
65
60
55
0
50
10
15
20
25
30
35
40
-40
-20
0
20
40
60
80
100
120
Temperature (Celsius)
TYPICAL IDOZE CURRENT @ VDD = 3.3V
MIPS
FIGURE 26-6:
FIGURE 26-8:
TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25ºC
40
35
30
25
20
15
10
5
20
18
16
14
12
10
8
6
4
2
0
10
15
20
25
30
35
40
0
1:1
1:2
1:8
1:128
MIPS
1:64
Doze Ratio
FIGURE 26-9:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 26-11:
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
7.38
32.6
32.55
32.5
7.36
7.34
7.32
7.3
32.45
32.4
32.35
32.3
-40
7.28
-20
0
20
40
60
80
100
120
Temperature (Celsius)
7.26
-40
-20
0
20
40
60
80
100
120
Temperature (Celsius)
FIGURE 26-10:
TYPICAL INTREF @ VDD = 3.3V
1.25
1.24
1.24
1.23
1.23
1.22
1.22
1.21
1.21
1.20
-40
-20
0
20
40
60
80
100
120
Temperature (Celsius)
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 318
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
18-Lead PDIP
Example
dsPIC30F3012
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
30I/P
e3
0610017
18-Lead SOIC (.300”)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
dsPIC33FJ06
GS101-I/SO
e
3
YYWWNNN
0830235
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
dsPIC33FJ12
MC201-I/SS
e
3
YYWWNNN
0730235
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
2011-2012 Microchip Technology Inc.
DS75018C-page 319
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
27.1 Package Marking Information (Continued)
28-Lead SPDIP
Example
dsPIC33FJ16MC
102-E/SP
0730235
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
e
3
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
dsPIC33FJ16MC
102-E/SO
e
3
0730235
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
33FJ16MC
102-E/SS
e
3
YYWWNNN
0730235
28-Lead QFN-S
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33FJJ16MC
102E/MM
0730235
e3
36-Lead VTLA
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33FJJ16MC
102E/TL
0730235
e
3
DS75018C-page 320
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
27.2 Package Details
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2011-2012 Microchip Technology Inc.
DS75018C-page 321
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS75018C-page 322
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc.
DS75018C-page 323
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS75018C-page 324
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
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2011-2012 Microchip Technology Inc.
DS75018C-page 325
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS75018C-page 326
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
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ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ
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ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ
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2011-2012 Microchip Technology Inc.
DS75018C-page 327
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS75018C-page 328
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc.
DS75018C-page 329
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS75018C-page 330
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2012 Microchip Technology Inc.
DS75018C-page 331
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
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DS75018C-page 332
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2011-2012 Microchip Technology Inc.
DS75018C-page 333
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 334
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
!ꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ)ꢏꢅꢆꢇ*ꢉꢅꢋ+ꢇꢜꢘꢇꢃꢄꢅꢆꢇꢈꢅꢍ%ꢅ,ꢄꢇꢒ--ꢓꢇMꢇ././ꢕ(0ꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ)*ꢜꢂ"ꢛ
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ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ
2011-2012 Microchip Technology Inc.
DS75018C-page 335
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 336
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2011-2012 Microchip Technology Inc.
DS75018C-page 337
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 338
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Where applicable, new sections were added to each
peripheral chapter that provide information and links to
APPENDIX A: REVISION HISTORY
related resources, as well as helpful tips. For
examples, see Section 18.1 “UART Helpful Tips”
Revision A (July 2011)
and Section 18.1 “UART Helpful Tips”.
This is the initial released version of this document.
The data sheet status was updated from Advance
Information to Preliminary.
Revision B (February 2012)
In addition, all occurrences to the package known as
TLA were updated to VTLA.
This revision includes formatting changes and minor
typographical updates throughout the data sheet text.
All other major changes are referenced by their
respective section in Table A-1.
TABLE A-1:
Section Name
“16-Bit Microcontrollers and
MAJOR SECTION UPDATES
Update Description
The previous content was reorganized and is now presented as the first page of
Digital Signal Controllers with the data sheet.
High-Speed PWM, ADC and
Comparators”
Relocated the Referenced Sources content, which was previously presented in
Section 1.0 “Device Overview”.
Section 2.0 “Guidelines for
Getting Started with 16-Bit
Digital Signal Controllers”
Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Section 4.0 “Memory
Organization”
Updated the Program Memory Map (see Figure 4-1).
Updated bits 10-8 in IPC27 of the Interrupt Controller Register Map for
dsPIC33FJ06GS001 Devices (see Table 4-4).
Renamed the CHOPCLK<6:0> bits in the CHOP register to: CHOP<6:0> in the
High-Speed PWM Register Map (see Table 4-12).
Removed RPINR11 from the Peripheral Pin Select Input Register Map for the
dsPIC33FJ06GS001 Device (see Table 4-24).
Added the REFOMD bit to PMD4 in the PMD Register Map for the
dsPIC33FJ06GS001 device (see Table 4-34).
Section 21.0 “Constant Current Added the Current Source Calibration bits (ISRCCAL<5:0>) to the Current
Source” Source Control register (see Register 21-1).
Section 22.0 “Special Features” Added the Constant Current Source Calibration Register (see Register 22-1).
Section 25.0 “Electrical
Characteristics”
Updated the Absolute Maximum Ratings(1).
Added Note 1 to the Operating MIPS vs. Voltage specification (see Table 25-1).
Updated all DC Characteristics: I/O Pin Output Specifications (see Table 25-10).
Updated the typical value for Parameters F20a and F20b in the Internal FRC
Accuracy specification (see Table 25-19).
Updated the minimum and maximum values for Parameter TA20, and the
minimum value for Parameter TA11 in the Timer1 External Clock Timing
Requirements (see Table 25-23).
Updated the OC/PWM Module Timing Characteristics diagram (see Figure 25-8).
Updated the minimum and maximum values for the Simple OC/PWM Mode
Timing Requirements (see Table 25-27).
Added Note 4 and Note 5 to the 10-Bit, High-Speed ADC Module Specifications
(see Table 25-39).
Section 26.0 “DC and AC
Added new chapter.
Device Characteristics Graphs”
2011-2012 Microchip Technology Inc.
DS75018C-page 339
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Revision C (August 2012)
This revision includes minor typographical updates and
content corrections. Major changes include new figures
in Section 26.0 “DC and AC Device Characteristics
Graphs”, updated values in Table 25-39 in Section 25.0
“Electrical Characteristics” and updated package
drawings in Section 27.0 “Packaging Information”.
DS75018C-page 340
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
INDEX
A
C
AC Characteristics ............................................................ 282
Internal LPRC Accuracy............................................ 285
Internal RC Accuracy................................................ 285
Load Conditions........................................................ 282
Temperature and Voltage Specifications.................. 282
Alternate Interrupt Vector Table (AIVT) .............................. 87
Arithmetic Logic Unit (ALU)................................................. 31
Assembler
C Compilers
MPLAB C18.............................................................. 268
Capacitor on Internal Voltage Regulator (VCAP)................. 18
Clock Switching ................................................................ 134
Enabling.................................................................... 134
Sequence ................................................................. 134
Code Examples
Port Write/Read........................................................ 147
PWRSAV Instruction Syntax .................................... 137
Code Protection................................................................ 251
Configuration Bits ............................................................. 251
Description................................................................ 254
Configuring Analog Port Pins............................................ 147
Constant Current Source
MPASM Assembler................................................... 268
Auxiliary Clock Generation................................................ 125
B
Bit-Reversed Addressing .................................................... 69
Example...................................................................... 70
Implementation ........................................................... 69
Sequence Table (16-Entry)......................................... 70
Block Diagrams
Description................................................................ 249
Features ................................................................... 249
CPU
16-Bit Timer1 Module................................................ 173
Boost Converter Implementation ................................ 21
Connections for On-Chip Voltage Regulator............. 256
Constant Current Source .......................................... 249
CPU Core.................................................................... 26
Digital PFC.................................................................. 21
DSP Engine ................................................................ 32
dsPIC33FJ06GS001 Device ADC ............................ 226
Barrel Shifter............................................................... 35
Control Registers........................................................ 28
Data Addressing Overview......................................... 25
DSP Engine Overview................................................ 25
MCU Special Features ............................................... 26
Special Features....................................................... 251
CPU Clocking System ...................................................... 124
PLL Configuration..................................................... 125
Selection................................................................... 124
Sources .................................................................... 124
Customer Change Notification Service............................. 346
Customer Notification Service .......................................... 346
Customer Support............................................................. 346
dsPIC33FJ06GS001/101A/102A/202A
and
dsPIC33FJ09GS302........................................... 14
dsPIC33FJ06GS101A Device ADC.......................... 227
dsPIC33FJ06GS102A Device ADC.......................... 228
dsPIC33FJ06GS202A Device ADC.......................... 229
dsPIC33FJ09GS302 Device ADC ............................ 230
High-Speed Analog Comparator............................... 243
Hysteresis Control..................................................... 245
I2C............................................................................. 212
Input Capture ............................................................ 177
Interleaved PFC.......................................................... 22
MCLR Pin Connections............................................... 18
Multiplexing of Remappable Output for RPn............. 150
Oscillator System...................................................... 123
Output Compare ....................................................... 179
Partitioned Output Pair, Complementary
D
DAC.................................................................................. 244
Buffer Gain ............................................................... 244
Output Range ........................................................... 245
Data Accumulators and Adder/Subtracter .......................... 33
Data Space Write Saturation...................................... 35
Overflow and Saturation............................................. 33
Round Logic ............................................................... 34
Write Back .................................................................. 34
Data Address Space........................................................... 39
Alignment.................................................................... 39
Memory Map for Devices with 1 Kbyte of RAM.......... 41
Memory Map for Devices with 256 Bytes of RAM ...... 40
Near Data Space........................................................ 39
Software Stack ........................................................... 66
Width .......................................................................... 39
X and Y Data .............................................................. 42
DC and AC Characteristics
PWM Mode....................................................... 186
Phase-Shifted Full-Bridge Converter .......................... 23
PLL............................................................................ 125
Recommended Minimum Connection......................... 18
Remappable MUX Input for U1RX............................ 148
Reset System.............................................................. 79
Shared Port Structure ............................................... 146
Simplified Conceptual High-Speed PWM ................. 185
Single-Phase Synchronous Buck Converter............... 22
SPI ............................................................................ 205
Type B Timer2 .......................................................... 175
UART ........................................................................ 219
Watchdog Timer (WDT)............................................ 257
Brown-out Reset (BOR)............................................ 251, 256
Graphs and Tables................................................... 315
DC Characteristics
Doze Current (IDOZE)................................................ 277
I/O Pin Input Specifications ...................................... 278
I/O Pin Output Specifications.................................... 280
Idle Current (IIDLE).................................................... 275
Operating Current (IDD) ............................................ 274
Operating MIPS vs. Voltage ..................................... 272
Power-Down Current (IPD)........................................ 276
Program Memory...................................................... 281
Temperature and Voltage Specifications.................. 273
2011-2012 Microchip Technology Inc.
DS75018C-page 341
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DC Specifications
DAC Output (DACOUT Pin)......................................312
Instruction Addressing Modes ............................................ 66
File Register Instructions ............................................ 66
Fundamental Modes Supported ................................. 67
MAC Instructions ........................................................ 67
MCU Instructions ........................................................ 66
Move and Accumulator Instructions............................ 67
Other Instructions ....................................................... 67
Instruction Set
Overview................................................................... 262
Summary .................................................................. 259
Instruction-Based Power-Saving Modes........................... 137
Idle............................................................................ 138
Sleep ........................................................................ 137
Interfacing Program and Data Memory Spaces.................. 71
Internal RC Oscillator
Use with WDT........................................................... 257
Internet Address ............................................................... 346
Interrupt Control and Status Registers ............................... 90
IECx............................................................................ 90
IFSx ............................................................................ 90
INTCON1.................................................................... 90
INTCON2.................................................................... 90
INTTREG.................................................................... 90
IPCx............................................................................ 90
Interrupt Setup Procedures............................................... 122
Initialization............................................................... 122
Interrupt Disable ....................................................... 122
Interrupt Service Routine.......................................... 122
Trap Service Routine................................................ 122
Interrupt Vector Table (IVT)................................................ 87
Interrupts Coincident with Power Save Instructions ......... 138
Development Support .......................................................267
Doze Mode........................................................................138
DSC Guidelines...................................................................17
Basic Connection Requirements.................................17
Decoupling Capacitors................................................17
DSP Engine.........................................................................31
Multiplier......................................................................33
E
Electrical Characteristics...................................................271
Absolute Maximum Ratings ......................................271
Equations
Device Operating Frequency ....................................124
FOSC Calculation.......................................................125
Maximum Page Erase Time........................................76
Minimum Page Erase Time.........................................76
XT with PLL Mode Example......................................125
Errata ..................................................................................11
F
Fail-Safe Clock Monitor (FSCM) .......................................135
Flash Program Memory.......................................................75
Control Registers ........................................................76
Operations ..................................................................76
Table Instructions........................................................75
Flexible Configuration .......................................................251
H
High-Speed 10-Bit ADC ....................................................225
Description................................................................225
Features....................................................................225
Functionality..............................................................225
High-Speed Analog Comparator.......................................243
Applications...............................................................244
Control Registers ......................................................245
DAC ..........................................................................244
Digital Logic ..............................................................244
Hysteresis .................................................................245
Input Range ..............................................................244
Interaction with I/O Buffers........................................245
High-Speed PWM .............................................................183
Control Registers ......................................................186
J
JTAG Boundary Scan Interface........................................ 251
JTAG Interface.................................................................. 258
L
LEBCONx (PWMx Leading-Edge Blanking Control) ........ 202
M
Master Clear (MCLR).......................................................... 18
Memory Organization ......................................................... 37
Microchip Internet Web Site.............................................. 346
Modulo Addressing............................................................. 68
Applicability................................................................. 69
Operation Example..................................................... 68
Start and End Address ............................................... 68
W Address Register Selection.................................... 68
MPLAB ASM30 Assembler, Linker, Librarian................... 268
MPLAB Integrated Development
I
I/O Ports............................................................................145
Helpful Tips...............................................................152
Parallel I/O (PIO).......................................................145
Resources.................................................................152
Write/Read Timing ....................................................147
I2C
Operating Modes ......................................................211
Registers...................................................................213
In-Circuit Debugger...........................................................258
In-Circuit Emulation...........................................................251
In-Circuit Serial Programming (ICSP) .......................251, 258
Analog, Digital Pins Configuration ..............................20
Pins.............................................................................19
Input Capture ....................................................................177
Input Change Notification..................................................147
Environment Software .............................................. 267
MPLAB PM3 Device Programmer .................................... 270
MPLAB REAL ICE In-Circuit Emulator System ................ 269
MPLINK Object Linker/MPLIB Object Librarian................ 268
O
Open-Drain Configuration................................................. 147
Oscillator
External Pins .............................................................. 19
Value Conditions on Start-up...................................... 20
Oscillator Configuration .................................................... 123
Output Compare ............................................................... 179
DS75018C-page 342
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
IFS0 (Interrupt Flag Status 0)..................................... 95
P
IFS1 (Interrupt Flag Status 1)..................................... 96
IFS3 (Interrupt Flag Status 3)..................................... 97
IFS4 (Interrupt Flag Status 4)..................................... 97
IFS5 (Interrupt Flag Status 5)..................................... 98
IFS6 (Interrupt Flag Status 6)..................................... 99
IFS7 (Interrupt Flag Status 7)................................... 100
INTCON1 (Interrupt Control 1) ................................... 92
INTCON2 (Interrupt Control 2) ................................... 94
INTTREG (Interrupt Control and Status) .................. 121
IOCONx (PWMx I/O Control).................................... 197
IPC0 (Interrupt Priority Control 0)............................. 107
IPC1 (Interrupt Priority Control 1)............................. 108
IPC14 (Interrupt Priority Control 14)......................... 113
IPC16 (Interrupt Priority Control 16)......................... 113
IPC2 (Interrupt Priority Control 2)............................. 109
IPC20 (Interrupt Priority Control 20)......................... 114
IPC23 (Interrupt Priority Control 23)......................... 115
IPC24 (Interrupt Priority Control 24)......................... 116
IPC25 (Interrupt Priority Control 25)......................... 117
IPC27 (Interrupt Priority Control 27)......................... 118
IPC28 (Interrupt Priority Control 28)......................... 119
IPC29 (Interrupt Priority Control 29)......................... 120
IPC3 (Interrupt Priority Control 3)............................. 110
IPC4 (Interrupt Priority Control 4)............................. 111
IPC5 (Interrupt Priority Control 5)............................. 112
IPC7 (Interrupt Priority Control 7)............................. 112
ISRCCON (Constant Current Source Control) ......... 250
LFSR (Linear Feedback Shift).................................. 133
MDC (PWM Master Duty Cycle)............................... 189
NVMCON (Flash Memory Control)............................. 77
NVMKEY (Nonvolatile Memory Key).......................... 78
OC1CON (Output Compare 1 Control)..................... 181
OSCCON (Oscillator Control)................................... 126
OSCTUN (Oscillator Tuning).................................... 130
PDCx (PWMx Generator Duty Cycle)....................... 192
PHASEx (PWMx Primary Phase Shift)..................... 193
PLLFBD (PLL Feedback Divisor) ............................. 129
PMD1 (Peripheral Module Disable Control 1) .......... 139
PMD2 (Peripheral Module Disable Control 2) .......... 140
PMD3 (Peripheral Module Disable Control 3) .......... 141
PMD4 (Peripheral Module Disable Control 4) .......... 141
PMD6 (Peripheral Module Disable Control 6) .......... 142
PMD7 (Peripheral Module Disable Control 7) .......... 143
PMD8 (Peripheral Module Disable Control 8) .......... 144
PTCON (PWM Time Base Control).......................... 187
PTCON2 (PWM Clock Divider Select 2)................... 188
PTPER (PWM Master Time Base) ........................... 188
PWMCAPx (Primary PWMx Time Base Capture) .... 203
PWMCONx (PWMx Control) .................................... 190
RCON (Reset Control)................................................ 80
REFOCON (Reference Oscillator Control)............... 132
RPINR0 (Peripheral Pin Select Input 0) ................... 153
RPINR1 (Peripheral Pin Select Input 1) ................... 154
RPINR11 (Peripheral Pin Select Input 11) ............... 158
RPINR18 (Peripheral Pin Select Input 18) ............... 159
RPINR2 (Peripheral Pin Select Input 2) ................... 155
RPINR20 (Peripheral Pin Select Input 20) ............... 160
RPINR21 (Peripheral Pin Select Input 21) ............... 161
RPINR29 (Peripheral Pin Select Input 29) ............... 162
RPINR3 (Peripheral Pin Select Input 3) ................... 156
RPINR30 (Peripheral Pin Select Input 30) ............... 163
RPINR31 (Peripheral Pin Select Input 31) ............... 164
RPINR32 (Peripheral Pin Select Input 32) ............... 165
RPINR33 (Peripheral Pin Select Input 33) ............... 166
RPINR34 (Peripheral Pin Select Input 34) ............... 167
Packaging ......................................................................... 319
Details....................................................................... 321
Marking ..................................................................... 319
Peripheral Module Disable (PMD) .................................... 138
Peripheral Pin Select (PPS).............................................. 148
Registers................................................................... 153
Pinout I/O Descriptions ....................................................... 15
Power-on Reset (POR)....................................................... 84
Power-Saving Features .................................................... 137
Clock Frequency and Switching................................ 137
Program Address Space..................................................... 37
Construction................................................................ 71
Data Access from Program Memory Using
Program Space Visibility..................................... 74
Data Access from Program Memory Using
Table Instructions ............................................... 73
Data Access from, Address Generation...................... 72
Memory Maps ............................................................. 37
Table Read Instructions
TBLRDH ............................................................. 73
TBLRDL.............................................................. 73
Visibility Operation ...................................................... 74
Program Memory
Interrupt Vector ........................................................... 38
Organization................................................................ 38
Reset Vector ............................................................... 38
Pseudo-Random Generator.............................................. 135
R
Reader Response............................................................. 347
Reference Clock Generation............................................. 125
Register Maps
Configuration Flash Bytes
(dsPIC33FJ06GS001/101A/X02A) ................... 252
Configuration Flash Bytes
(dsPIC33FJ09GS302) ...................................... 252
Registers
ACLKCON (Auxiliary Clock Divisor Control)............. 131
ADCON (ADC Control) ............................................. 231
ADCPC0 (ADC Convert Pair Control 0).................... 236
ADCPC1 (ADC Convert Pair Control 1).................... 238
ADCPC3 (ADC Convert Pair Control 3).................... 240
ADPCFG (ADC Port Configuration).......................... 235
ADSTAT (ADC Status).............................................. 233
ALTDTRx (PWMx Alternate Dead-Time).................. 195
AUXCONx (PWM Auxiliary Control) ......................... 204
CHOP (PWM Chop Clock Generator)....................... 203
CLKDIV (Clock Divisor)............................................. 128
CMPCONx (Comparator Control x) .......................... 246
CMPDACx (Comparator DAC Control x) .................. 248
Constant Current Source Calibration........................ 253
CORCON (Core Control) ...................................... 30, 91
DTRx (PWMx Dead-Time)........................................ 195
FCLCONx (PWMx Fault Current-Limit Control)........ 199
I2C1CON (I2C1 Control)........................................... 213
I2C1MSK (I2C1 Slave Mode Address Mask)............ 217
I2C1STAT (I2C1 Status)........................................... 215
IC1CON (Input Capture 1 Control)............................ 178
IEC0 (Interrupt Enable Control 0) ............................. 101
IEC1 (Interrupt Enable Control 1) ............................. 102
IEC3 (Interrupt Enable Control 3) ............................. 103
IEC4 (Interrupt Enable Control 4) ............................. 103
IEC5 (Interrupt Enable Control 5) ............................. 104
IEC6 (Interrupt Enable Control 6) ............................. 105
IEC7 (Interrupt Enable Control 7) ............................. 106
2011-2012 Microchip Technology Inc.
DS75018C-page 343
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
RPINR7 (Peripheral Pin Select Input 7)....................157
RPOR0 (Peripheral Pin Select Output 0)..................168
RPOR1 (Peripheral Pin Select Output 1)..................168
RPOR16 (Peripheral Pin Select Output 16)..............172
RPOR17 (Peripheral Pin Select Output 17)..............172
RPOR2 (Peripheral Pin Select Output 2)..................169
RPOR3 (Peripheral Pin Select Output 3)..................169
RPOR4 (Peripheral Pin Select Output 4)..................170
RPOR5 (Peripheral Pin Select Output 5)..................170
RPOR6 (Peripheral Pin Select Output 6)..................171
RPOR7 (Peripheral Pin Select Output 7)..................171
SDCx (PWMx Secondary Duty Cycle)......................192
SEVTCMP (PWM Special Event Compare)..............189
SPHASEx (PWMx Secondary Phase Shift) ..............194
SPIxCON1 (SPIx Control 1)......................................208
SPIxCON2 (SPIx Control 2)......................................210
SPIxSTAT (SPIx Status and Control) .......................207
SR (CPU STATUS).....................................................91
SR (CPU Status).........................................................28
STRIGx (PWMx Secondary Trigger
High-Speed PWM Generator 2 for
dsPIC33FJ06GS102A, dsPIC33FJ06GS202A,
dsPIC33FJ09GS302...............................................53
High-Speed PWM Generator 4 for dsPIC33FJ06GS001,
dsPIC33FJ06GS101A, dsPIC33FJ09GS302 ........54
I2C1 .................................................................................55
Input Capture for dsPIC33FJ06GS202A,
dsPIC33FJ09GS302...............................................51
Interrupt Controller for dsPIC33FJ06GS001 ..................46
Interrupt Controller for dsPIC33FJ06GS002A................48
Interrupt Controller for dsPIC33FJ06GS101A................47
Interrupt Controller for dsPIC33FJ06GS202A................49
Interrupt Controller for dsPIC33FJ09GS302 ..................50
NVM.................................................................................63
Output Compare for dsPIC33FJ06GS101A,
dsPIC33FJ06GS102A, dsPIC33FJ06GS202A,
dsPIC33FJ09GS302...............................................51
Peripheral Pin Select Input for dsPIC33FJ06GS001 .....59
Peripheral Pin Select Input for dsPIC33FJ06GS101A,
dsPIC33FJ06GS102A ............................................59
Peripheral Pin Select Input for dsPIC33FJ06GS202A,
dsPIC33FJ09GS302...............................................60
Peripheral Pin Select Output for dsPIC33FJ06GS001,
dsPIC33FJ06GS101A ............................................60
Peripheral Pin Select Output for dsPIC33FJ06GS102A,
dsPIC33FJ06GS202A, dsPIC33FJ09GS302 ........61
PMD for dsPIC33FJ06GS001..................................... 64
PMD for dsPIC33FJ06GS101A .................................. 64
PMD for dsPIC33FJ06GS102A .................................. 64
PMD for dsPIC33FJ06GS202A .................................. 65
PMD for dsPIC33FJ09GS302..................................... 65
PORTA ....................................................................... 62
PORTB for dsPIC33FJ06GS001,
Compare Value)................................................201
T1CON (Timer1 Control)...........................................174
T2CON (Timer2 Control)...........................................176
TRGCONx (PWMx Trigger Control)..........................196
TRIGx (PWMx Primary Trigger Compare Value)......201
U1MODE (UART1 Mode) .........................................221
U1STA (UART1 Status and Control) ........................223
Reset
Brown-out Reset (BOR)........................................79, 84
Configuration Mismatch Reset (CM)...........................79
Illegal Condition Device Reset (IOPUWR)..................79
Illegal Opcode.....................................................79
Security...............................................................79
Uninitialized W Register......................................79
Illegal Device Reset ....................................................85
Illegal Opcode.............................................................85
Master Clear Reset (MCLR) .......................................79
Power-on Reset (POR)...............................................79
Power-up Timer Reset (PWRT) ..................................84
Software RESET Instruction .......................................79
System Reset
dsPIC33FJ06GS101A ............................................62
PORTB for dsPIC33FJ06GS102A,
dsPIC33FJ06GS202A, dsPIC33FJ09GS302 ........62
SPI1 for dsPIC33FJ06GS101A, dsPIC33FJ06GS102A,
dsPIC33FJ09GS202A, dsPIC33FJ09GS302 ........55
System Control................................................................63
Timers..............................................................................51
UART1 for dsPIC33FJ06GS101A,
Cold Reset ..........................................................82
Warm Reset........................................................82
Trap Conflict................................................................85
Trap Conflict Reset (TRAPR)......................................79
Uninitialized W Register..............................................85
Watchdog Timer Out Reset (WDTO)..........................79
Reset Sequence..................................................................87
Revision History ................................................................339
dsPIC33FJ06GS102A, dsPIC33FJ06GS202A,
dsPIC33FJ09GS302 ........................................... 55
Software RESET Instruction (SWR) ................................... 85
Software Simulator (MPLAB SIM) .................................... 269
Software Stack Pointer, Frame Pointer
CALL Stack Frame ..................................................... 66
Symbols Used in Opcode Descriptions ............................ 260
T
S
Thermal Packaging Characteristics.................................. 272
Timer1............................................................................... 173
Timer2............................................................................... 175
Timing Diagrams
Serial Peripheral Interface (SPI) .......................................205
SFR Maps
Change Notification for
dsPIC33FJ06GS001, dsPIC33FJ06GS101A......45
Change Notification for dsPIC33FJ06GS102A,
dsPIC33FJ06GS202A, dsPIC33FJ09GS302......45
Constant Current Source ............................................56
CPU Core....................................................................43
High-Speed 10-Bit ADC for dsPIC33FJ06GS001,
dsPIC33FJ06GS101A.........................................56
High-Speed 10-Bit ADC for dsPIC33FJ06GS102A,
dsPIC33FJ06GS202A.........................................57
High-Speed 10-Bit ADC for dsPIC33FJ09GS302.......58
High-Speed PWM .......................................................52
High-Speed PWM Generator 1...................................52
Analog-to-Digital Conversion per Input..................... 310
Brown-out Situations................................................... 84
External Clock........................................................... 283
High-Speed PWM..................................................... 292
High-Speed PWM Fault............................................ 292
I/O............................................................................. 286
I2C1 Bus Data (Master Mode).................................. 305
I2C1 Bus Data (Slave Mode).................................... 307
I2C1 Bus Start/Stop Bits (Master Mode)................... 305
I2C1 Bus Start/Stop Bits (Slave Mode)..................... 307
Input Capture (CAP1) ............................................... 290
OC/PWM................................................................... 291
DS75018C-page 344
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Output Compare (OC1)............................................. 290
Reset, Watchdog Timer, Oscillator Start-up
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Timer and Power-up Timer............................... 287
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ........................................... 296
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 295
SPIx Master Mode (Half-Duplex, Transmit Only,
CKE = 0) ........................................................... 293
SPIx Master Mode (Half-Duplex, Transmit Only,
CKE = 1) ........................................................... 294
SPIx Slave Mode (Full-Duplex, CKE = 0,
Reset Requirements......................................... 287
Simple OC/PWM Mode Requirements..................... 291
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements.................... 296
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements.................... 295
SPIx Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 294
SPIx Maximum Data Clock Rate Summary.............. 293
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 303
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 304
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 301
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 302
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 297
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 298
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 299
System Reset.............................................................. 83
Timer1, Timer2 External Clock ................................. 288
Timing Specifications
CKP = 1, SMP = 0) Requirements.................... 300
Timer1 External Clock Requirements....................... 288
Timer2 External Clock Requirements....................... 289
U
10-Bit High-Speed ADC............................................ 309
10-Bit High-Speed ADC Requirements..................... 310
Auxiliary PLL Clock................................................... 284
Capacitive Loading Requirements on
Universal Asynchronous Receiver
Transmitter (UART) .................................................. 219
Helpful Tips............................................................... 220
Resources ................................................................ 220
Using the RCON Status Bits............................................... 86
Output Pins....................................................... 282
Constant Current Source .......................................... 313
DAC .......................................................................... 311
DAC Gain Stage to Comparator ............................... 312
External Clock Requirements ................................... 283
High-Speed ADC Comparator .................................. 311
High-Speed PWM Requirements.............................. 292
I/O Requirements...................................................... 286
I2C1 Bus Data Requirements (Master Mode)........... 306
I2C1 Bus Data Requirements (Slave Mode)............. 308
Input Capture Requirements..................................... 290
Output Compare Requirements................................ 290
PLL Clock.................................................................. 284
V
Voltage Regulator (On-Chip) ............................................ 256
W
Watchdog Timer (WDT)............................................ 251, 257
Watchdog Timer Time-out Reset (WDTO) ......................... 85
WWW Address ................................................................. 346
WWW, On-Line Support ..................................................... 11
2011-2012 Microchip Technology Inc.
DS75018C-page 345
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 346
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
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Technical support is available through the web site
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registration instructions.
2011-2012 Microchip Technology Inc.
DS75018C-page 347
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
READER RESPONSE
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dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302
DS75018C
Literature Number:
Device:
Questions:
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DS75018C-page 348
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
dsPIC 33 FJ 06 GS0 01 T - E / SP - XXX
a) dsPIC33FJ06GS001-I/SS:
SMPS dsPIC33, 6-Kbyte program
memory, 20-pin, Industrial
temp.,SSOP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
=
16-bit Digital Signal Controller
Flash program memory, 3.3V
Flash Memory Family: FJ
Product Group:
GS0
=
=
=
=
Switch Mode Power Supply (SMPS) family
Switch Mode Power Supply (SMPS) family
Switch Mode Power Supply (SMPS) family
Switch Mode Power Supply (SMPS) family
GS1
GS2
GS3
Pin Count:
01
02
=
=
18-pin, 20-pin
28-pin, 36-pin
Temperature Range:
Package:
I
=
=
-40C to+85C (Industrial)
-40C to+125C (Extended)
E
P
=
=
=
=
=
=
Plastic Dual In-line – 300 mil (PDIP)
SO
SS
SP
MM
TL
Plastic Small Outline – Wide – 7.50 mm body (SOIC)
Plastic Shrink Small Outline – 5.30 mm body (SSOP)
Skinny Plastic Dual In-Line – 300 mil body (SPDIP)
Plastic Quad Flat, No Lead Package – 6x6x0.9 mm body (QFN-S)
Very Thin Leadless Array – 5x5x0.9 mm body (VTLA)
2011-2012 Microchip Technology Inc.
DS75018C-page 349
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 350
2011-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-494-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2011-2012 Microchip Technology Inc.
DS75018C-page 351
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Korea - Seoul
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/11
DS75018C-page 352
2011-2012 Microchip Technology Inc.
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