JS28F00AP33BFA_技术文档

512Mb, 1Gb, 2Gb: P33-65nm

Features

Micron Parallel NOR Flash Embedded

Memory (P33-65nm)

JS28F512P33BFD, JS28F512P33TFA, JS28F512P33EFA

PC28F512P33BFD, PC28F512P33TFA, PC28F512P33EFA

JS28F00AP33BFA, JS28F00AP33TFA, JS28F00AP33EFA

PC28F00AP33BFA, PC28F00AP33TFA, PC28F00AP33EFA,

PC28F00BP33EFA

• Security

Features

• High performance

– One-time programmable register: 64 OTP bits,

programmed with unique information from Mi-

cron; 2112 OTP bits available for customer pro-

gramming

• Easy BGA package features

– 95ns initial access for 512Mb, 1Gb Easy BGA

– 100ns initial access for 2Gb Easy BGA

– 25ns 16-word asychronous page read mode

– 52 MHz (Easy BGA) with zero WAIT states and

17ns clock-to-data output synchronous burst

read mode

– 4-, 8-, 16-, and continuous word options for burst

mode

• TSOP package features

– Absolute write protection: V_PP= V_SS

– Power-transition erase/program lockout

– Individual zero-latency block locking

– Individual block lock-down

– Password access

• Software

– 25μs (TYP) program suspend

– 25μs (TYP) erase suspend

– 105ns initial access for 512Mb, 1Gb TSOP

• Both Easy BGA and TSOP package features

– Buffered enhanced factory programming (BEFP)

at 2 MB/s (TYP) using a 512-word buffer

– 3.0V buffered programming at 1.46 MB/s (TYP)

using a 512-word buffer

– Flash Data Integrator optimized

– Basic command set and extended function Inter-

face (EFI) command set compatible

– Common flash interface

• Density and Packaging

– 56-lead TSOP package (512Mb, 1Gb)

– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)

– 16-bit wide data bus

• Quality and reliabilty

– JESD47 compliant

• Architecture

– MLC: highest density at lowest cost

– Symmetrically blocked architecture (512Mb, 1Gb,

2Gb)

– Asymmetrically blocked architecture (512Mb,

1Gb); four 32KB parameter blocks: top or bottom

configuration

– Operating temperature: –40°C to +85°C

– Minimum 100,000 ERASE cycles per block

– 65nm process technology

– 128KB main blocks

– Blank check to verify an erased block

• Voltage and power

– V_CC(core) voltage: 2.3–3.6V

– V_CCQ(I/O) voltage: 2.3–3.6V

– Standy current: 70µA (TYP) for 512Mb; 75µA

(TYP) for 1Gb

– 52 MHz continuous synchronous read current:

21mA (TYP), 24mA (MAX)

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p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb, 1Gb, 2Gb: P33-65nm

Features

Discrete and MCP Part Numbering Information

Devices are shipped from the factory with memory content bits erased to 1. For available options, such as pack-

ages or for further information, contact your Micron sales representative. Part numbers can be verified at www.mi-

cron.com. Feature and specification comparison by device type is available at www.micron.com/products. Con-

tact the factory for devices not found.

Note: Not all part numbers listed here are available for ordering.

Table 1: Discrete Part Number Information

Part Number Category

Category Details

Package

JS = 56-lead TSOP, lead free

PC = 64-ball Easy BGA, lead-free

28F = Micron Flash memory

Product Line

Density

512 = 512Mb

00A = 1Gb

00B = 2Gb

Product Family

P33 (V_CC= 2.3–3.6V; V_CCQ= 2.3–3.6V)

Parameter Location

B/T = Bottom/Top parameter

E = Symmetrical Blocks

Lithography

Features

F = 65nm

*

1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration infor-

mation. Sample part number: JS28F512P33EF*

Note:

Table 2: Standard Part Numbers

Density

Configuration

Medium

Tray

JS

PC

512Mb

Bottom boot

JS28F512P33BFD

PC28F512P33BFD

Tape & Reel

Tray

–

Top boot

Uniform

JS28F512P33TFA

PC28F512P33TFA

Tape & Reel

Tray

–

JS28F512P33EFA

PC28F512P33EFA

Tape & Reel

Tray

–

1Gb

Bottom boot

Top boot

Uniform

JS28F00AP33BFA

PC28F00AP33BFA

Tape & Reel

Tray

–

JS28F00AP33TFA

PC28F00AP33TFA

Tape & Reel

Tray

–

JS28F00AP33EFA

PC28F00AP33EFA

Tape & Reel

Tray

–

2Gb

Uniform

PC28F00BP33EFA

–

Tape & Reel

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p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2

512Mb, 1Gb, 2Gb: P33-65nm

Features

Contents

General Description ......................................................................................................................................... 7

Virtual Chip Enable Description ........................................................................................................................ 8

Memory Map ................................................................................................................................................... 9

Package Dimensions ....................................................................................................................................... 11

Pinouts and Ballouts ....................................................................................................................................... 13

Signal Descriptions ......................................................................................................................................... 15

Bus Operations ............................................................................................................................................... 17

Read .......................................................................................................................................................... 17

Write .......................................................................................................................................................... 17

Output Disable ........................................................................................................................................... 17

Standby ..................................................................................................................................................... 17

Reset .......................................................................................................................................................... 18

Device Command Codes ................................................................................................................................. 19

Device Command Bus Cycles .......................................................................................................................... 22

Read Operations ............................................................................................................................................. 24

Asynchronous Single Word Read ..................................................................................................................... 24

Asynchronous Page Mode Read (Easy BGA Only) ............................................................................................. 24

Synchronous Burst Mode Read (Easy BGA Only) .............................................................................................. 25

Read CFI ........................................................................................................................................................ 25

Read Device ID ............................................................................................................................................... 25

Device ID Codes ............................................................................................................................................. 26

Program Operations ....................................................................................................................................... 27

Word Programming (40h) ........................................................................................................................... 27

Buffered Programming (E8h, D0h) .............................................................................................................. 27

Buffered Enhanced Factory Programming (80h, D0h) ................................................................................... 28

Program Suspend ....................................................................................................................................... 30

Program Resume ........................................................................................................................................ 31

Program Protection .................................................................................................................................... 31

Erase Operations ............................................................................................................................................ 32

BLOCK ERASE Command ........................................................................................................................... 32

BLANK CHECK Command .......................................................................................................................... 32

ERASE SUSPEND Command ....................................................................................................................... 33

ERASE RESUME Command ........................................................................................................................ 33

Erase Protection ......................................................................................................................................... 33

Security Operations ........................................................................................................................................ 34

Block Locking ............................................................................................................................................. 34

BLOCK LOCK Command ............................................................................................................................ 34

BLOCK UNLOCK Command ....................................................................................................................... 34

BLOCK LOCK DOWN Command ................................................................................................................. 34

Block Lock Status ....................................................................................................................................... 34

Block Locking During Suspend ................................................................................................................... 35

Selectable OTP Blocks ................................................................................................................................. 36

Password Access ......................................................................................................................................... 36

Status Register ................................................................................................................................................ 37

Read Status Register ................................................................................................................................... 37

Clear Status Register ................................................................................................................................... 38

Configuration Register .................................................................................................................................... 39

Read Configuration Register ....................................................................................................................... 39

Read Mode ................................................................................................................................................. 39

Latency Count ............................................................................................................................................ 40

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512Mb, 1Gb, 2Gb: P33-65nm

Features

End of Wordline Considerations .................................................................................................................. 41

WAIT Signal Polarity and Functionality ........................................................................................................ 42

WAIT Delay ................................................................................................................................................ 43

Burst Sequence .......................................................................................................................................... 43

Clock Edge ................................................................................................................................................. 44

Burst Wrap ................................................................................................................................................. 44

Burst Length .............................................................................................................................................. 44

One-Time Programmable Registers ................................................................................................................. 45

Read OTP Registers ..................................................................................................................................... 45

Program OTP Registers ............................................................................................................................... 46

Lock OTP Registers ..................................................................................................................................... 46

Common Flash Interface ................................................................................................................................ 48

READ CFI Structure Output ........................................................................................................................ 48

Flowcharts ..................................................................................................................................................... 62

Power and Reset Specifications ....................................................................................................................... 71

Power Supply Decoupling ........................................................................................................................... 72

Maximum Ratings and Operating Conditions .................................................................................................. 73

DC Electrical Specifications ............................................................................................................................ 74

AC Test Conditions and Capacitance ............................................................................................................... 76

AC Read Specifications ................................................................................................................................... 78

AC Write Specifications ................................................................................................................................... 85

Program and Erase Characteristics .................................................................................................................. 91

Revision History ............................................................................................................................................. 92

Rev. C – 12/13 ............................................................................................................................................. 92

Rev. B – 11/13 ............................................................................................................................................. 92

Rev. A – 8/13 ............................................................................................................................................... 92

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512Mb, 1Gb, 2Gb: P33-65nm

Features

List of Figures

Figure 1: Easy BGA Block Diagram ................................................................................................................... 8

Figure 2: Memory Map – 512Mb and 1Gb ......................................................................................................... 9

Figure 3: Memory Map – 2Gb ......................................................................................................................... 10

Figure 4: 56-Pin TSOP – 14mm x 20mm .......................................................................................................... 11

Figure 5: 64-Ball Easy BGA – 8mm x 10mm x 1.2mm ....................................................................................... 12

Figure 6: 56-Lead TSOP Pinout – 512Mb and 1Gb ........................................................................................... 13

Figure 7: 64-Ball Easy BGA (Top View – Balls Down) – 512Mb, 1Gb, and 2Gb .................................................... 14

Figure 8: Example V_PPSupply Connections .................................................................................................... 31

Figure 9: Block Locking State Diagram ........................................................................................................... 35

Figure 10: First Access Latency Count ............................................................................................................ 40

Figure 11: Example Latency Count Setting Using Code 3 ................................................................................. 41

Figure 12: End of Wordline Timing Diagram ................................................................................................... 41

Figure 13: OTP Register Map .......................................................................................................................... 46

Figure 14: Word Program Procedure ............................................................................................................... 62

Figure 15: Buffer Program Procedure .............................................................................................................. 63

Figure 16: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 64

Figure 17: Block Erase Procedure ................................................................................................................... 65

Figure 18: Program Suspend/Resume Procedure ............................................................................................ 66

Figure 19: Erase Suspend/Resume Procedure ................................................................................................. 67

Figure 20: Block Lock Operations Procedure ................................................................................................... 68

Figure 21: OTP Register Programming Procedure ............................................................................................ 69

Figure 22: Status Register Procedure .............................................................................................................. 70

Figure 23: Reset Operation Waveforms ........................................................................................................... 72

Figure 24: AC Input/Output Reference Timing ................................................................................................ 76

Figure 25: Transient Equivalent Load Circuit .................................................................................................. 76

Figure 26: Clock Input AC Waveform .............................................................................................................. 76

Figure 27: Asynchronous Single-Word Read (ADV# LOW) ................................................................................ 80

Figure 28: Asynchronous Single-Word Read (ADV# Latch) ............................................................................... 80

Figure 29: Asynchronous Page Mode Read ...................................................................................................... 81

Figure 30: Synchronous Single-Word Array or Nonarray Read .......................................................................... 82

Figure 31: Continuous Burst Read with Output Delay ..................................................................................... 83

Figure 32: Synchronous Burst Mode 4-Word Read ........................................................................................... 84

Figure 33: Write to Write Timing .................................................................................................................... 87

Figure 34: Asynchronous Read to Write Timing ............................................................................................... 87

Figure 35: Write to Asynchronous Read Timing ............................................................................................... 88

Figure 36: Synchronous Read to Write Timing ................................................................................................ 89

Figure 37: Write to Synchronous Read Timing ................................................................................................ 90

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512Mb, 1Gb, 2Gb: P33-65nm

Features

List of Tables

Table 1: Discrete Part Number Information ...................................................................................................... 2

Table 2: Standard Part Numbers ....................................................................................................................... 2

Table 3: Virtual Chip Enable Truth Table for Easy BGA Packages ........................................................................ 8

Table 4: TSOP and Easy BGA Signal Descriptions ............................................................................................ 15

Table 5: Bus Operations ................................................................................................................................. 17

Table 6: Command Codes and Definitions ...................................................................................................... 19

Table 7: Command Bus Cycles ....................................................................................................................... 22

Table 8: Device ID Information ...................................................................................................................... 25

Table 9: Device ID codes ................................................................................................................................ 26

Table 10: BEFP Requirements ........................................................................................................................ 29

Table 11: BEFP Considerations ...................................................................................................................... 29

Table 12: Status Register Description .............................................................................................................. 37

Table 13: Read Configuration Register ............................................................................................................ 39

Table 14: End of Wordline Data and WAIT State Comparison ........................................................................... 42

Table 15: WAIT Functionality Table ................................................................................................................ 42

Table 16: Burst Sequence Word Ordering ........................................................................................................ 43

Table 17: Example of CFI Output (x16 device) as a Function of Device and Mode ............................................. 48

Table 18: CFI Database: Addresses and Sections ............................................................................................. 49

Table 19: CFI ID String ................................................................................................................................... 49

Table 20: System Interface Information .......................................................................................................... 50

Table 21: Device Geometry ............................................................................................................................ 51

Table 22: Block Region Map Information ........................................................................................................ 51

Table 23: Primary Vendor-Specific Extended Query ........................................................................................ 52

Table 24: Optional Features Field ................................................................................................................... 54

Table 25: One Time Programmable (OTP) Space Information .......................................................................... 54

Table 26: Burst Read Information ................................................................................................................... 55

Table 27: Partition and Block Erase Region Information .................................................................................. 56

Table 28: Partition Region 1 Information: Top and Bottom Offset/Address ....................................................... 57

Table 29: Partition Region 1 Information ........................................................................................................ 57

Table 30: Partition Region 1: Partition and Erase Block Map Information ......................................................... 60

Table 31: CFI Link Information – 2Gb ............................................................................................................. 61

Table 32: Power and Reset .............................................................................................................................. 71

Table 33: Maximum Ratings ........................................................................................................................... 73

Table 34: Operating Conditions ...................................................................................................................... 73

Table 35: DC Current Characteristics .............................................................................................................. 74

Table 36: DC Voltage Characteristics .............................................................................................................. 75

Table 37: Test Configuration: Worst-Case Speed Condition .............................................................................. 76

Table 38: Capacitance .................................................................................................................................... 77

Table 39: AC Read Specifications .................................................................................................................... 78

Table 40: AC Write Specifications ................................................................................................................... 85

Table 41: Program and Erase Specifications .................................................................................................... 91

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512Mb, 1Gb, 2Gb: P33-65nm

General Description

The Micron Parallel NOR Flash memory is the latest generation of Flash memory devi-

ces. Benefits include more density in less space, high-speed interface device, and sup-

port for code and data storage. Features include high-performance synchronous-burst

read mode, fast asynchronous access times, low power, flexible security options, and

three industry-standard package choices. The product family is manufactured using Mi-

cron 65nm process technology.

The NOR Flash device provides high performance at low voltage on a 16-bit data bus.

Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the read configuration register enables synchronous burst-

mode reads. In synchronous burst mode, output data is synchronized with a user-sup-

plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technol-

ogy that enables fast factory PROGRAM and ERASE operations. Designed for low-volt-

age systems, the devIce supports READ operations with V_CCat the low voltages, and

ERASE and PROGRAM operations with V_PPat the low voltages or V_PPH. Buffered en-

hanced factory programming (BEFP) provides the fastest Flash array programming per-

formance with V_PPat V_PPH, which increases factory throughput. With V_PPat low voltag-

es, V_CCand V_PPcan be tied together for a simple, ultra low-power design. In addition to

voltage flexibility, a dedicated V_PPconnection provides complete data protection when

V_PP≤ V_PPLK

.

A command user interface is the interface between the system processor and all inter-

nal operations of the device. The device automatically executes the algorithms and tim-

ings necessary for block erase and program. A status register indicates ERASE or PRO-

GRAM completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation.

Each ERASE operation erases one block. The erase suspend feature enables system soft-

ware to pause an ERASE cycle to read or program data in another block. Program sus-

pend enables system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

The protection register enables unique device identification that can be used to in-

crease system security. The individual block lock feature provides zero-latency block

locking and unlocking. The device includes enhanced protection via password access;

this new feature supports write and/or read access protection of user-defined blocks. In

addition, the device also provides the full-device OTP security feature.

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512Mb, 1Gb, 2Gb: P33-65nm

Virtual Chip Enable Description

The 2Gb device employs a virtual chip enable feature, which combines two 1Gb die

with a common chip enable, CE# for Easy BGA packages. The maximum address bit is

then used to select between the die pair with CE# asserted. When CE# is asserted and

the maximum address bit is LOW, the lower parameter die is selected; when CE# is as-

serted and the maximum address bit is HIGH, the upper parameter die is selected.

Table 3: Virtual Chip Enable Truth Table for Easy BGA Packages

Die Selected

CE#

A[MAX]

Lower parameter die

Upper parameter die

L

H

Figure 1: Easy BGA Block Diagram

Easy BGA (Dual Die) Top/Bottom

Parameter Configuration

Top Parameter Die

CE#

WP#

OE#

RST#

V

CC

V

WE#

CLK

PP

V

CCQ

Bottom Parameter Die

V

ADV#

SS

DQ[15:0]

WAIT

A[MAX:1]

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512Mb, 1Gb, 2Gb: P33-65nm

Memory Map

Figure 2: Memory Map – 512Mb and 1Gb

A[25:1] 512Mb and A[26:1] 1Gb

64 KWord Block 1026

64 KWord Block 514

64 KWord Block 258

64 KWord Block 1023

64 KWord Block 511

3FF0000 - 3FFFFFF

1FF0000 - 1FFFFFF

3FF0000 - 3FFFFFF

1FF0000 - 1FFFFFF

FF0000 - FFFFFF

1Gb

512Mb

1Gb

512Mb

FF0000 - FFFFFF

020000 - 02FFFF

64 KWord Block 255

64 KWord Block 5

64 KWord Block 4

16 KWord Block 3

16 KWord Block 2

16 KWord Block 1

16 KWord Block 0

010000 - 01FFFF

00C000 - 00FFFF

008000 - 00BFFF

004000 - 007FFF

000000 - 003FFF

030000 - 03FFFF

020000 - 02FFFF

010000 - 01FFFF

000000 - 00FFFF

64 KWord Block 3

64 KWord Block 2

64 KWord Block 1

64 KWord Block 0

Bottom Boot 512Mb and 1Gb, World-Wide x16 Mode

Symetrically Blocked 512Mb and 1Gb, World-Wide x16 Mode

1FFC000 - 1FFFFFF

16 KWord Block 514

16 KWord Block 513

16 KWord Block 512

16 KWord Block 511

64 KWord Block 510

3FFC000 - 3FFFFFF

3FF8000 - 3FFBFFF

3FF4000 - 3FF7FFF

3FF0000 - 3FF3FFF

3FE0000 - 3FEFFFF

16 KWord Block 1026

16 KWord Block 1025

16 KWord Block 1024

16 KWord Block 1023

64 KWord Block 1022

1FF8000 - 1FFBFFF

1FF4000 - 1FF7FFF

1FF0000 - 1FF3FFF

1FE0000 - 1FEFFFF

512Mb

1Gb

010000 - 01FFFF

000000 - 00FFFF

64 KWord Block 1

64 KWord Block 0

010000 - 01FFFF

000000 - 00FFFF

64 KWord Block 1

64 KWord Block 0

Top Boot 512Mb, World Wide x16 Mode

Top Boot 1Gb, World Wide x16 Mode

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512Mb, 1Gb, 2Gb: P33-65nm

Memory Map

Figure 3: Memory Map – 2Gb

A[27:1] 2Gb (1Gb/1Gb)

64 KWord Block 2047

7FF0000 - 7FFFFFF

4011000 - 401FFFF

4000000 - 400FFFF

3FF0000 - 3FFFFFF

64 KWord Block 1025

64 KWord Block 1024

64 KWord Block 1023

1FF0000 - 1FFFFFF

FF0000 - FFFFFF

64 KWord Block 511

64 KWord Block 255

2Gb

1Gb

512Mb

020000 - 02FFFF

010000 - 01FFFF

000000 - 00FFFF

64 KWord Block 2

64 KWord Block 1

64 KWord Block 0

World-Wide x16 Mode

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512Mb, 1Gb, 2Gb: P33-65nm

Package Dimensions

Figure 4: 56-Pin TSOP – 14mm x 20mm

20 ±0.2

18.4 ±0.2

0.995 ±0.03

Pin #1 index

See notes 2

See note 2

0.5 TYP

14.00 ±0.2

0.22 ±0.05

See note 2

0.25 ±0.1

0.15 ±0.05

0.10

+2°

3°

-3°

See Detail A

Seating

plane

1.20 MAX

0.05 MIN

0.60 ±0.10

Detail A

1. All dimensions are in millimeters. Drawing not to scale.

Notes:

2. One dimple on package denotes pin 1; if two dimples, then the larger dimple denotes

pin 1. Pin 1 will always be in the upper left corner of the package, in reference to the

product mark.

3. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05.

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512Mb, 1Gb, 2Gb: P33-65nm

Package Dimensions

Figure 5: 64-Ball Easy BGA – 8mm x 10mm x 1.2mm

0.78 TYP

0.25 MIN

Seating

plane

0.1

Ball A1 ID

1.00 TYP

64X Ø0.43 ±0.1

1.5 ±0.1

Ball A1 ID

8

7

6

5

4

3

2

1

0.5 ±0.1

A

B

C

D

E

8 ±0.1

F

1.00 TYP

G

H

10 ±0.1

1.20 MAX

1. All dimensions are in millimeters. Drawing not to scale.

Notes:

2. The 512Mb device does not contain the A1 ID ball located on the back side of the de-

vice.

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512Mb, 1Gb, 2Gb: P33-65nm

Pinouts and Ballouts

Figure 6: 56-Lead TSOP Pinout – 512Mb and 1Gb

WAIT

A17

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

A 16

A 15

DQ15

DQ7

DQ14

DQ 6

DQ13

DQ5

DQ12

DQ4

ADV#

CLK

A 14

A 13

A 12

A 11

A 10

A 9

A 23

A 22

A 21

VSS

RFU

WE #

WP #

A 20

A 19

A 18

A 8

A 7

A 6

A 5

A 4

A 3

A 2

A24

A25

A26

56-Lead TSOP Pinout

14mm x 20mm

RST#

VPP

DQ11

DQ 3

DQ10

DQ 2

VCCQ

DQ 9

DQ1

DQ 8

DQ 0

VCC

Top View

OE#

VSS

CE#

A 1

1. A1 is the least significant address bit.

Notes:

2. ADV# must be tied to V_SSor driven to LOW throughout the asynchronous read mode.

3. A25 is valid for 512Mb densities and above; otherwise, it is a no connect (NC).

4. A26 is valid for 1Gb densities and above; otherwise, it is a no connect (NC).

5. One dimple on package denotes Pin 1 which will always be in the upper left corner of

the package, in reference to the product mark.

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512Mb, 1Gb, 2Gb: P33-65nm

Pinouts and Ballouts

Figure 7: 64-Ball Easy BGA (Top View – Balls Down) – 512Mb, 1Gb, and 2Gb

1

2

3

4

5

6

7

8

A

B

C

D

E

A1

A2

A6

A8

A9

V

A13

A14

V

A18 A22

PP

CC

V

CE#

A25 A19 A26

SS

A3

A4

A7

A5

A10 A12

A15 WP#

A20 A21

A16 A17

A11 RST# V

V

CCQ

DQ8 DQ1 DQ9 DQ3 DQ4

CLK DQ15 RFU

F

RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#

G

H

A23 RFU DQ2 V

DQ5 DQ6 DQ14 WE#

CCQ

A27

DQ13

DQ7 A24

V

SS

CC

SS

1. A1 is the least significant address bit.

Notes:

2. A25 is valid for 512Mb densities and above; otherwise, it is a no connect (NC).

3. A26 is valid for 1Gb densities and above; otherwise, it is a no connect (NC).

4. A27 is valid for 2Gb densities and above; otherwise, it is a no connect (NC).

5. One dimple on package denotes Pin 1 which will always be in the upper left corner of

the package, in reference to the product mark.

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Signal Descriptions

Table 4: TSOP and Easy BGA Signal Descriptions

Symbol

Type

Name and Function

A[MAX:1]

Input

Address inputs: Device address inputs.

Note: Unused active address pins should not be left floating; tie them to V_CCQor V_SSac-

cording to specific design requirements.

ADV#

CE#

Input

Address valid: Active LOW input. During synchronous READ operations, addresses are

latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-

ever occurs first. In asynchronous mode, the address is latched when ADV# goes HIGH or

continuously flows through if ADV# is held LOW.

Note: Designs not using ADV# must tie it to V_SSto allow addresses to flow through.

Chip enable: Active LOW input. CE# LOW selects the associated die. When asserted, inter-

nal control logic, input buffers, decoders, and sense amplifiers are active. When de-asser-

ted, the associated die is deselected, power is reduced to standby levels, data and wait

outputs are placed in High-Z.

Note: CE# must be driven HIGH when device is not in use.

CLK

Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.

During synchronous READs, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# LOW, whichever occurs first.

Note: Designs not using CLK for synchronous read mode must tie it to V_CCQor V_SS.

OE#

Input

Output enable: Active LOW input. OE# LOW enables the device’s output data buffers

during READ cycles. OE# HIGH places the data outputs and WAIT in High-Z.

RST#

Reset: Active LOW input. RST# resets internal automation and inhibits WRITE operations.

This provides data protection during power transitions. RST# HIGH enables normal opera-

tion. Exit from reset places the device in asynchronous read array mode.

WP#

Input

Write protect: Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in

lock-down cannot be unlocked with the Unlock command. WP# HIGH overrides the lock-

down function enabling blocks to be erased or programmed using software commands.

Note: Designs not using WP# for protection could tie it to V_CCQor V_SSwithout additional

capacitor.

WE#

V_PP

Input

Write enable: Active LOW input. WE# controls writes to the device. Address and data are

latched on the rising edge of WE# or CE#, whichever occurs first.

Power/Input Erase and program power: A valid voltage on this pin allows erasing or programming.

Memory contents cannot be altered when V_PP≤ V_PPLK. Block erase and program at invalid

V_PPvoltages should not be attempted.

Set V_PP= V_PPLfor in-system PROGRAM and ERASE operations. To accommodate resistor or

diode drops from the system supply, the V_IHlevel of V_PPcan be as low as V_PPL,min. V_PPmust

remain above V_PPL,minto perform in-system modification. V_PPmay be 0V during READ op-

erations.

V_PPcan be connected to 9V for a cumulative total not to exceed 80 hours. Extended use of

this pin at 9V may reduce block cycling capability.

DQ[15:0]

Input/Output Data input/output: Inputs data and commands during WRITE cycles; outputs data during

memory, status register, protection register, and read configuration register reads. Data

balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.

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Signal Descriptions

Table 4: TSOP and Easy BGA Signal Descriptions (Continued)

Symbol

Type

Name and Function

WAIT

Output

Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-

tion register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active

output is V_OLor V_OHwhen CE# and OE# are V_IL. WAIT is High-Z if CE# or OE# is V_IH.

• In synchronous array or non-array read modes, this signal indicates invalid data when as-

serted and valid data when de-asserted.

• In asynchronous page mode, and all write modes, this signal is de-asserted.

V_CC

Power

Device core power supply: Core (logic) source voltage. Writes to the array are inhibited

when V_CC≤ V_LKO. Operations at invalid V_CCvoltages should not be attempted.

V_CCQ

V_SS

Power

—

Output power supply: Output-driver source voltage.

Ground: Connect to system ground. Do not float any V_SSconnection.

RFU

Reserved for future use: Reserved by Micron for future device functionality and en-

hancement. These should be treated in the same way as a DU signal.

DU

NC

—

Do not use: Do not connect to any other signal, or power supply; must be left floating.

No connect: No internal connection; can be driven or floated.

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Bus Operations

CE# LOW and RST# HIGH enable READ operations. The device internally decodes up-

per address inputs to determine the accessed block. ADV# LOW opens the internal ad-

dress latches. OE# LOW activates the outputs and gates selected data onto the I/O bus.

Bus cycles to/from the device conform to standard microprocessor bus operations. Bus

operations and the logic levels that must be applied to the device control signal inputs

are shown here.

Table 5: Bus Operations

Bus Operation

RST#

H

CLK

ADV#

CE#

OE#

WE#

H

WAIT

De-asserted

Driven

DQ[15:0]

Output

Notes

READ

Asynchronous

Synchronous

X

L

-

H

Run-

ning

H

Output

WRITE

H

L

X

L

H

X

L

H

X

High-Z

Input

High-Z

1

2

OUTPUT DISABLE

STANDBY

X

H

X

2

RESET

2, 3

1. Refer to the Device Command Bus Cycles for valid DQ[15:0] during a WRITE operation.

2. X = "Don’t Care" (H or L).

Notes:

3. RST# must be at V_SS± 0.2V to meet the maximum specified power-down current.

Read

To perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#

are asserted. CE# is the device-select control. When asserted, it enables the device. OE#

is the data-output control. When asserted, the addressed flash memory data is driven

onto the I/O bus.

Write

To perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# are

de-asserted. During a WRITE operation, address and data are latched on the rising edge

of WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the bus

cycle sequence for each of the supported device commands, while the Command Codes

and Definitions table describes each command.

Note: WRITE operations with invalid V_CCand/or V_PPvoltages can produce spurious re-

sults and should not be attempted.

Output Disable

Standby

When OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Z

state, WAIT is also placed in High-Z.

When CE# is de-asserted the device is deselected and placed in standby, substantially

reducing power consumption. In standby, the data outputs are placed in High-Z, inde-

pendent of the level placed on OE#. Standby current (I_CCS) is the average current meas-

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Bus Operations

ured over any 5ms time interval, 5μs after CE# is de-asserted. During standby, average

current is measured over the same time interval 5μs after CE# is de-asserted.

When the device is deselected (while CE# is de-asserted) during a PROGRAM or ERASE

operation, it continues to consume active power until the PROGRAM or ERASE opera-

tion is completed.

Reset

As with any automated device, it is important to assert RST# when the system is reset.

When the system comes out of reset, the system processor attempts to read from the

device if it is the system boot device. If a CPU reset occurs with no device reset, improp-

er CPU initialization may occur because the device may be providing status informa-

tion rather than array data. Micron devices enable proper CPU initialization following a

system reset through the use of the RST# input. RST# should be controlled by the same

low-true reset signal that resets the system CPU.

After initial power-up or reset, the device defaults to asynchronous read array mode,

and the status register is set to 0x80. Asserting RST# de-energizes all internal circuits,

and places the output drivers in High-Z. When RST# is asserted, the device shuts down

the operation in progress, a process which takes a minimum amount of time to com-

plete. When RST# has been de-asserted, the device is reset to asynchronous read array

state.

When device returns from a reset (RST# de-asserted), a minimum wait is required be-

fore the initial read access outputs valid data. Also, a minimum delay is required after a

reset before a write cycle can be initiated. After this wake-up interval passes, normal op-

eration is restored.

Note: If RST# is asserted during a PROGRAM or ERASE operation, the operation is ter-

minated and the memory contents at the aborted location (for a program) or block (for

an erase) are no longer valid, because the data may have been only partially written or

erased.

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Device Command Codes

The system CPU provides control of all in-system READ, WRITE, and ERASE operations

of the device via the system bus. The device manages all block-erase and word-program

algorithms.

Device commands are written to the CUI to control all device operations. The CUI does

not occupy an addressable memory location; it is the mechanism through which the

device is controlled.

Note: For a dual device, all setup commands should be re-issued to the device when a

different die is selected.

Table 6: Command Codes and Definitions

Mode

Device Mode

Read array

Code

0xFF

Description

Read

Places the device in read array mode. Array data is output on DQ[15:0].

Read status register

0x70

Places the device in read status register mode. The device enters this

mode after a PROGRAM or ERASE command is issued. Status register

data is output on DQ[7:0].

Read device ID or

read configuration

register

0x90

Places device in read device identifier mode. Subsequent reads output

manufacturer/device codes, configuration register data, block lock sta-

tus, or protection register data on DQ[15:0].

Read CFI

0x98

0x50

0x40

Places the device in read CFI mode. Subsequent reads output CFI infor-

mation on DQ[7:0].

Clear status register

Word program setup

The device sets status register error bits. The clear status register com-

mand is used to clear the SR error bits.

Write

First cycle of a 2-cycle programming command; prepares the CUI for a

WRITE operation. On the next write cycle, the address and data are

latched and the device executes the programming algorithm at the ad-

dressed location. During PROGRAM operations, the device responds

only to READ STATUS REGISTER and PROGRAM SUSPEND commands.

CE# or OE# must be toggled to update the status register in asynchro-

nous read. CE# or ADV# must be toggled to update the status register

data for synchronous non-array reads. The READ ARRAY command

must be issued to read array data after programming has finished.

Buffered program

0xE8

0xD0

This command loads a variable number of words up to the buffer size

of 512 words onto the program buffer.

Buffered program

confirm

The CONFIRM command is issued after the data streaming for writing

into the buffer is completed. The device then performs the buffered

program algorithm, writing the data from the buffer to the memory

array.

BEFP setup

0x80

0xD0

First cycle of a two-cycle command; initiates buffered enhanced factory

program mode (BEFP). The CUI then waits for the BEFP CONFIRM com-

mand, 0xD0, that initiates the BEFP algorithm. All other commands are

ignored when BEFP mode begins.

BEFP confirm

If the previous command was BEFP SETUP (0x80), the CUI latches the

address and data, and prepares the device for BEFP mode.

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Device Command Codes

Table 6: Command Codes and Definitions (Continued)

Mode

Device Mode

Code

Description

Erase

Block erase setup

0x20

First cycle of a two-cycle command; prepares the CUI for a BLOCK

ERASE operation. The device performs the erase algorithm on the

block addressed by the ERASE CONFIRM command. If the next com-

mand is not the ERASE CONFIRM (0xD0) command, the CUI sets status

register bits SR4 and SR5, and places the device in read status register

mode.

Block erase confirm

0xD0

0xB0

If the first command was BLOCK ERASE SETUP (0x20), the CUI latches

the address and data, and the device erases the addressed block. Dur-

ing BLOCK ERASE operations, the device responds only to READ STATUS

REGISTER and ERASE SUSPEND commands. CE# or OE# must be toggled

to update the status register in asynchronous read. CE# or ADV# must

be toggled to update the status register data for synchronous non-ar-

ray reads.

Suspend

Program or erase

suspend

This command issued to any device address initiates a suspend of the

currently-executing program or BLOCK ERASE operation. The status

register indicates successful suspend operation by setting either SR2

(program suspended) or SR6 (erase suspended), along with SR7 (ready).

The device remains in the suspend mode regardless of control signal

states (except for RST# asserted).

Suspend resume

Block lock setup

0xD0

0x60

This command issued to any device address resumes the suspended

PROGRAM or BLOCK ERASE operation.

Protection

First cycle of a two-cycle command; prepares the CUI for block lock con-

figuration changes. If the next command is not BLOCK LOCK (0x01),

BLOCK UNLOCK (0xD0), or BLOCK LOCK DOWN (0x2F), the CUI sets sta-

tus register bits SR5 and SR4, indicating a command sequence error.

Block lock

0x01

0xD0

If the previous command was BLOCK LOCK SETUP (0x60), the addressed

block is locked.

Block unlock

If the previous command was BLOCK LOCK SETUP (0x60), the addressed

block is unlocked. If the addressed block is in a lock down state, the op-

eration has no effect.

Block lock down

0x2F

0xC0

If the previous command was BLOCK LOCK SETUP (0x60), the addressed

block is locked down.

OTP register or lock

register program set-

up

First cycle of a two-cycle command; prepares the device for a OTP REG-

ISTER or LOCK REGISTER PROGRAM operation. The second cycle latches

the register address and data, and starts the programming algorithm

to program data the OTP array.

Configuration Read configuration

register setup

0x60

0x03

First cycle of a two-cycle command; prepares the CUI for device read

configuration. If the SET READ CONFIGURATION REGISTER command

(0x03) is not the next command, the CUI sets status register bits SR4

and SR5, indicating a command sequence error.

Read configuration

register

If the previous command was READ CONFIGURATION REGISTER SETUP

(0x60), the CUI latches the address and writes A[16:1] to the read con-

figuration register for Easy BGA and TSOP, A[15:0] for QUAD+. Follow-

ing a CONFIGURE READ CONFIGURATION REGISTER command, subse-

quent READ operations access array data.

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Device Command Codes

Table 6: Command Codes and Definitions (Continued)

Mode

Device Mode

Code

Description

Blank Check

Block blank check

0xBC

First cycle of a two-cycle command; initiates the BLANK CHECK opera-

tion on a main block.

Block blank check

confirm

0xD0

0xEB

Second cycle of blank check command sequence; it latches the block

address and executes blank check on the main array block.

EFI

Extended function

interface

First cycle of a multiple-cycle command; initiate operation using exten-

ded function interface. The second cycle is a Sub-Op-Code, the data

written on third cycle is one less than the word count; the allowable

value on this cycle are 0–511. The subsequent cycles load data words in-

to the program buffer at a specified address until word count is ach-

ieved.

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Device Command Bus Cycles

Device operations are initiated by writing specific device commands to the command

user interface (CUI). Several commands are used to modify array data including WORD

PROGRAM and BLOCK ERASE commands. Writing either command to the CUI initiates

a sequence of internally timed functions that culminate in the completion of the re-

quested task. However, the operation can be aborted by either asserting RST# or by is-

suing an appropriate suspend command.

Table 7: Command Bus Cycles

First Bus Cycle

Second Bus Cycle

Bus

Cycles

Mode

Command

Op

Addr¹

DnA

WA

Data²

Op

–

Addr¹

Data²

Read

READ ARRAY

1

≥2

2

WRITE

0xFF

0x90

0x98

0x70

0x50

0x40

0xE8

0x80

–

READ DEVICE IDENTIFIER

READ CFI

READ

DBA + IA

ID

READ DBA + CFI-A

CFI-D

SRD

–

READ STATUS REGISTER

CLEAR STATUS REGISTER

WORD PROGRAM

BUFFERED PROGRAM³

READ

–

DnA

–

1

Program

2

WRITE

WA

WD

N - 1

0xD0

>2

WA

BUFFERED ENHANCED

FACTORY PROGRAM

(BEFP)⁴

WA

Erase

BLOCK ERASE

2

1

2

WRITE

BA

DnA

BA

0x20

0xB0

0xD0

0x60

0xC0

0x60

WRITE

–

BA

–

0xD0

–

Suspend

PROGRAM/ERASE SUSPEND

PROGRAM/ERASE RESUME

BLOCK LOCK

–

Protection

WRITE

BA

0x01

0xD0

0x2F

OTP-D

LRD

0x03

BLOCK UNLOCK

BA

BLOCK LOCK DOWN

PROGRAM OTP REGISTER

PROGRAM LOCK REGISTER

BA

PRA

LRA

RCD

OTP-RA

LRA

RCD

Configuration CONFIGURE READ

CONFIGURATION REGISTER

BLOCK BLANK CHECK

Blank Check

EFI

2

WRITE

BA

0xBC

0xEB

WRITE

Write

BA

D0

EXTENDED FUNCTION

INTERFACE ⁵

>2

WA

Sub-Op code

1. First command cycle address should be the same as the operation’s target address. DBA

= Device base address (needed for dual die 512Mb device); DnA = Address within the de-

vice; IA = Identification code address offset; CFI-A = Read CFI address offset; WA = Word

address of memory location to be written; BA = Address within the block; OTP-RA = Pro-

tection register address; LRA = Lock register address; RCD = Read configuration register

data on A[16:1] for Easy BGA and TSOP, A[15:0] for QUAD+ package.

Notes:

2. ID = Identifier data; CFI-D = CFI data on DQ[15:0]; SRD = Status register data; WD = Word

data; N = Word count of data to be loaded into the write buffer; OTP-D = Protection

register data; LRD = Lock register data.

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Device Command Bus Cycles

3. The second cycle of the BUFFERED PROGRAM command is the word count of the data to

be loaded into the write buffer. This is followed by up to 512 words of data. Then the

CONFIRM command (0xD0) is issued, triggering the array programming operation.

4. The CONFIRM command (0xD0) is followed by the buffer data.

5. The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 512.

The subsequent cycles load data words into the program buffer at a specified address

until word count is achieved, after the data words are loaded, the final cycle is the con-

firm cycle 0xD0).

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Read Operations

The device supports two read modes: asynchronous page mode and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a re-

set. Under asynchronous page mode, the device can also perform single word read. The

read configuration register must be configured to enable synchronous burst reads of the

array.

The device can be in any of four read states: read array, read identifier, read status, or

read CFI. Upon power-up, or after a reset, the device defaults to read array. To change

the read state, the appropriate READ command must be written to the device.

Asynchronous Single Word Read

To perform an asynchronous single word read, an address is driven onto the address

bus, and CE# is asserted.

Note: To perform an asynchronous single word read for a TSOP package, ADV# must be

LOW throughout the READ cycle. For an Easy BGA package, ADV# can be driven HIGH

to latch the address or be held LOW throughout the READ cycle.

WE# and RST# must already have been de-asserted. WAIT is set to a de-asserted state

during single word mode, as determined by bit 10 of the read configuration register.

CLK is not used for asynchronous single word reads, and is ignored. If asynchronous

reads are to be performed only, CLK should be tied to a valid V_IHor V_SSlevel, WAIT can

be floated, and ADV# must be tied to ground. After OE# is asserted, the data is driven

onto DQ[15:0] after an initial access time ^tAVQV or ^tGLQV delay.

Asynchronous Page Mode Read (Easy BGA Only)

Note: Asynchronous Page Mode Read is supported only in the main array.

Following a device power-up or reset, asynchronous page mode is the default read

mode and the device is set to read array. However, to perform array reads after any other

device operation (WRITE operation), the READ ARRAY command must be issued in or-

der to read from the array.

Asynchronous page mode reads can only be performed when read configuration regis-

ter bit RCR15 is set.

To perform an asynchronous page-mode read, an address is driven onto the address

bus, and CE# and ADV# are asserted. WE# and RST# must already have been de-asser-

ted. WAIT is de-asserted during asynchronous page mode. ADV# can be driven HIGH to

latch the address, or it must be held LOW throughout the READ cycle. CLK is not used

for asynchronous page mode reads, and is ignored. If only asynchronous reads are to be

performed, CLK should be tied to a valid V_IHor V_SSlevel, WAIT signal can be floated,

and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial ac-

cess time ^tAVQV delay.

In asynchronous page mode, 16 data words are “sensed” simultaneously from the array

and loaded into an internal page buffer. The buffer word corresponding to the initial

address on the address bus is driven onto DQ[15:0] after the initial access delay. The

lowest four address bits determine which word of the 16-word page is output from the

data buffer at any given time.

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Synchronous Burst Mode Read (Easy BGA Only)

Read configuration register bits RCR[15:0] must be set before synchronous burst opera-

tion can be performed. Synchronous burst mode can be performed for both array and

non-array reads such as read ID, read status, or read query.

To perform a synchronous burst read, an initial address is driven onto the address bus,

and CE# and ADV# are asserted. WE# and RST# must already have been de-asserted.

ADV# is asserted, and then de-asserted to latch the address. Alternately, ADV# can re-

main asserted throughout the burst access, in which case the address is latched on the

next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay. Subsequent

data is output on valid CLK edges following a minimum delay. However, for a synchro-

nous non-array read, the same word of data will be output on successive clock edges

until the burst length requirements are satisfied. Refer to the timing diagrams for more

detailed information.

Read CFI

The READ CFI command instructs the device to output CFI data when read. See Com-

mon Flash Interface for details on issuing the READ CFI command, and for details on

addresses and offsets within the CFI database.

Read Device ID

The READ DEVICE IDENTIFIER command instructs the device to output manufacturer

code, device identifier code, block lock status, protection register data, or configuration

register data.

Table 8: Device ID Information

Item

Address

Data

Manufacturer code

Device ID code

0x00

0x01

0x89

ID (see the Device ID Codes table )

Block lock configuration

Block is unlocked

Block is locked

Block is not locked down

Block is locked down

Block base address + 0x02

Lock bit

DQ₀= 0b0

DQ₀= 0b1

DQ₁= 0b0

DQ₁= 0b1

Read configuration register

General purpose register

Lock register 0

0x05

Device base address + 0x07

0x80

RCR contents

General purpose register data

PR-LK0 data

64-bit factory-programmed OTP register

64-bit user-programmable OTP register

Lock register 1

0x81–0x84

Factory OTP register data

User OTP register data

PR-LK1 OTP register lock data

OTP register data

0x85–0x88

0x89

128-bit user-programmable protection regis-

ters

0x8A–0x109

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Device ID Codes

Table 9: Device ID codes

Device Identifier Codes

Device

ID Code Type

Density

512Mb

1Gb

–T (Top Parameter)

–B (Bottom Parameter)

–E/F (Symmetrical Blocks)

Device Code

8964

8966

8965

8967

899E

899F

1. The 2Gb devices do not have a unique device ID associated with them. Each die within

the stack can be identified by device ID codes.

Note:

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Program Operations

Successful programming requires the addressed block to be unlocked. If the block is

locked down, WP# must be de-asserted and the block must be unlocked before at-

tempting to program the block. Attempting to program a locked block causes a program

error (SR4 and SR1 set) and termination of the operation. See Security Modes for details

on locking and unlocking blocks.

Word Programming (40h)

Word programming operations are initiated by writing the WORD PROGRAM SETUP

command to the device (see the Command Codes and Definitions table). This is fol-

lowed by a second write to the device with the address and data to be programmed. The

device outputs status register data when read (see the Word Program Flowchart). V_PP

must be above V_PPLK, and within the specified V_PPLMIN/MAX values.

During programming, the device executes a sequence of internally-timed events that

program the desired data bits at the addressed location, and verifies that the bits are

sufficiently programmed. Programming the array changes 1s to 0s. Memory array bits

that are 0s can be changed to 1s only by erasing the block (see Erase Operations).

The status register can be examined for programming progress and errors by reading at

any address. The device remains in the read status register state until another com-

mand is written to the device.

SR7 indicates the programming status while the sequence executes. Commands that

can be issued to the device during programming are PROGRAM SUSPEND, READ STA-

TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and READ ARRAY (this returns

unknown data).

When programming has finished, SR4 (when set) indicates a programming failure. If

SR3 is set, the device could not perform the WORD PROGRAMMING operation because

V_PPwas outside of its acceptable limits. If SR1 is set, the WORD PROGRAMMING opera-

tion attempted to program a locked block, causing the operation to abort.

Before issuing a new command, the status register contents should be examined and

then cleared using the CLEAR STATUS REGISTER command. Any valid command can

follow, when word programming has completed.

Buffered Programming (E8h, D0h)

The device features a 512-word buffer to enable optimum programming performance.

For buffered programming, data is first written to an on-chip write buffer. Then the buf-

fer data is programmed into the array in buffer-size increments. This can improve sys-

tem programming performance significantly over non-buffered programming.

When the BUFFERED PROGRAMMING SETUP command is issued, status register in-

formation is updated and reflects the availability of the buffer. SR7 indicates buffer

availability: if set, the buffer is available; if cleared, the buffer is not available.

Note: The device default state is to output SR data after the BUFFERED PROGRAM-

MING SETUP command. CE# and OE# LOW drive device to update status register. It is

not allowed to issue 70h to read SR data after E8h command; otherwise, 70h would be

counted as word count.

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Program Operations

On the next write, a word count is written to the device at the buffer address. This tells

the device how many data words will be written to the buffer, up to the maximum size

of the buffer.

On the next write, a device start address is given along with the first data to be written to

the flash memory array. Subsequent writes provide additional device addresses and da-

ta. All data addresses must lie within the start address plus the word count. Optimum

programming performance and lower power usage are obtained by aligning the starting

address at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy BGA and TSOP,

A[8:0] for QUAD+ package; see Part Numbering Information). The maximum buffer size

would be 256-word if the misaligned address range is crossing a 512-word boundary

during programming.

After the last data is written to the buffer, the BUFFERED PROGRAMMING CONFIRM

command must be issued to the original block address. The device begins to program

buffer contents to the array. If a command other than the BUFFERED PROGRAMMING

CONFIRM command is written to the device, a command sequence error occurs and

SR[7,5,4] are set. If an error occurs while writing to the array, the device stops program-

ming, and SR[7,4] are set, indicating a programming failure.

When buffered programming has completed, additional buffer writes can be initiated

by issuing another BUFFERED PROGRAMMING SETUP command and repeating the

buffered program sequence. Buffered programming may be performed with V_PP= V_PPL

or V_PPH(see Operating Conditions for limitations when operating the device with V_PP

V_PPH).

=

If an attempt is made to program past an erase-block boundary using the BUFFERED

PROGRAM command, the device aborts the operation. This generates a command se-

quence error, and SR[5,4] are set.

If buffered programming is attempted while V_PPis at or below V_PPLK, SR[4,3] are set. If

any errors are detected that have set status register bits, the status register should be

cleared using the CLEAR STATUS REGISTER command.

Buffered Enhanced Factory Programming (80h, D0h)

Buffered enhanced factory programming (BEFP) speeds up multilevel cell (MLC) pro-

gramming. The enhanced programming algorithm used in BEFP eliminates traditional

programming elements that drive up overhead in device programmer systems.

BEFP consists of three phases: setup, program/verify, and exit (see the BEFP Flowchart).

It uses a write buffer to spread MLC program performance across 512 data words. Verifi-

cation occurs in the same phase as programming to accurately program the cell to the

correct bit state.

A single two-cycle command sequence programs the entire block of data. This en-

hancement eliminates three write cycles per buffer: two commands and the word count

for each set of 512 data words. Host programmer bus cycles fill the device write buffer

followed by a status check. SR0 indicates when data from the buffer has been program-

med into sequential array locations.

Following the buffer-to-flash array programming sequence, the device increments in-

ternal addressing to automatically select the next 512-word array boundary. This aspect

of BEFP saves host programming equipment the address bus setup overhead.

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Program Operations

With adequate continuity testing, programming equipment can rely on the device’s in-

ternal verification to ensure that the device has programmed properly. This eliminates

the external post-program verification and its associated overhead.

Table 10: BEFP Requirements

Parameter/Issue

Case temperature

V_CC

Requirement

Notes

T_C= 30°C ± 10°C

Nominal V_CC

V_PP

Driven to V_PPH

Setup and confirm

Programming

Target block must be unlocked before issuing the BEFP Setup and Confirm commands.

The first-word address (WA0) of the block to be programmed must be held constant

from the setup phase through all data streaming into the target block, until transition

to the exit phase is desired.

Buffer alignment

WA0 must align with the start of an array buffer boundary.

1

1. Word buffer boundaries in the array are determined by the lowest 9 address bits (0x000

through 0x1FF). The alignment start point is 0x000.

Note:

Table 11: BEFP Considerations

Parameter/Issue

Requirement

Notes

Cycling

For optimum performance, cycling must be limited below 50 ERASE cycles per block.

1

2

Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block.

Suspend BEFP cannot be suspended.

Programming the ar- Programming to the array can occur only when the buffer is full.

ray

3

1. Some degradation in performance may occur if this limit is exceeded, but the internal

algorithm continues to work properly.

Notes:

2. If the internal address counter increments beyond the block's maximum address, ad-

dressing wraps around to the beginning of the block.

3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.

BEFP Setup Phase: After receiving the BEFP SETUP and CONFIRM command se-

quence, SR7 (ready) is cleared, indicating that the device is busy with BEFP algorithm

startup. A delay before checking SR7 is required to allow the device enough time to per-

form all of its setups and checks (block lock status, V_PPlevel, etc.). If an error is detected,

SR4 is set and BEFP operation terminates. If the block was found to be locked, SR1 is

also set. SR3 is set if the error occurred due to an incorrect V_PPlevel.

Note: Reading from the device after the BEFP SETUP and CONFIRM command se-

quence outputs status register data. Do not issue the READ STATUS REGISTER com-

mand; it will be interpreted as data to be loaded into the buffer.

BEFP Program/Verify Phase: After the BEFP setup phase has completed, the host pro-

gramming system must check SR[7,0] to determine the availability of the write buffer

for data streaming. SR7 cleared indicates the device is busy and the BEFP program/veri-

fy phase is activated. SR0 indicates the write buffer is available.

Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer

data programming to the array. For BEFP, the count value for buffer loading is always

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Program Operations

the maximum buffer size of 512 words. During the buffer-loading sequence, data is stor-

ed to sequential buffer locations starting at address 0x00. Programming of the buffer

contents to the array starts as soon as the buffer is full. If the number of words is less

than 512, the remaining buffer locations must be filled with 0xFFFF.

Note: The buffer must be completely filled for programming to occur. Supplying an ad-

dress outside of the current block's range during a buffer-fill sequence causes the algo-

rithm to exit immediately. Any data previously loaded into the buffer during the fill cy-

cle is not programmed into the array.

The starting address for data entry must be buffer size aligned; if not, the BEFP algo-

rithm will be aborted, the program fails, and the (SR4) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the ar-

ray; programming continues from where the previous buffer sequence ended. The host

programming system must poll SR0 to determine when the buffer program sequence

completes. SR0 cleared indicates that all buffer data has been transferred to the array;

SR0 set indicates that the buffer is not available yet for the next fill cycle. The host sys-

tem may check full status for errors at any time, but it is only necessary on a block basis

after BEFP exit. After the buffer fill cycle, no WRITE cycles should be issued to the de-

vice until SR0 = 0 and the device is ready for the next buffer fill.

Note: Any spurious writes are ignored after a BUFFER FILL operation and when internal

program is proceeding.

The host programming system continues the BEFP algorithm by providing the next

group of data words to be written to the buffer. Alternatively, it can terminate this phase

by changing the block address to one outside of the current block’s range.

The program/verify phase concludes when the programmer writes to a different block

address; data supplied must be 0xFFFF. Upon program/verify phase completion, the de-

vice enters the BEFP exit phase.

Program Suspend

Issuing the PROGRAM SUSPEND command while programming suspends the pro-

gramming operation. This allows data to be accessed from the device other than the

one being programmed. The PROGRAM SUSPEND command can be issued to any de-

vice address. A PROGRAM operation can be suspended to perform reads only. Addition-

ally, a PROGRAM operation that is running during an erase suspend can be suspended

to perform a READ operation.

When a programming operation is executing, issuing the PROGRAM SUSPEND com-

mand requests the device to suspend the programming algorithm at predetermined

points. The device continues to output status register data after the PROGRAM SUS-

PEND command is issued. Programming is suspended when SR[7,2] are set.

To read data from the device, the READ ARRAY command must be issued. READ ARRAY,

READ STATUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and PROGRAM RE-

SUME valid commands during a program suspend.

During a program suspend, de-asserting CE# places the device in standby, reducing ac-

tive current. V_PPmust remain at its programming level, and WP# must remain un-

changed while in program suspend. If RST# is asserted, the device is reset.

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Program Operations

Program Resume

The RESUME command instructs the device to continue programming, and automati-

cally clears SR[7,2]. This command can be written to any address. If error bits are set,

the status register should be cleared before issuing the next command. RST# must re-

main de-asserted.

Program Protection

When V_PP= V_IL, absolute hardware write protection is provided for all device blocks. If

V_PPis at or below V_PPLK, programming operations halt and SR3 is set, indicating a V_PP

level error. Block lock registers are not affected by the voltage level on V_PP; they may still

be programmed and read, even if V_PPis less than V_PPLK

-

.

Figure 8: Example V_PPSupply Connections

V_CC

V_PP

V_CC

V_PP

V_CC

V_PP

PROT#

<

10K Ω

-Factory programming with V_PP= V_PPH

-Complete with program/erase

-Low voltage programming only

-Logic control of device protection

protection when V_PP

<

V_PPLK

V_CC

V_PP

V_CC

V_PP

V

PPH

=

-Low voltage and factory programming

-Low voltage programming only

-Full device protection unavailable

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Erase Operations

BLOCK ERASE Command

ERASE operations are performed on a block basis. An entire block is erased each time a

BLOCK ERASE command sequence is issued, and only one block is erased at a time.

When a block is erased, each bit within that block reads as a logical 1.

A BLOCK ERASE operation is initiated by writing the BLOCK ERASE SETUP command

to the address of the block to be erased, followed by the BLOCK ERASE CONFIRM com-

mand. If the device is placed in standby (CE# de-asserted) during a BLOCK ERASE oper-

ation, the device completes the operation before entering standby. The V_PPvalue must

be above V_PPLKand the block must be unlocked.

During a BLOCK ERASE operation, the device executes a sequence of internally-timed

events that conditions, erases, and verifies all bits within the block. Erasing the array

changes the value in each cell from a 1 to a 0. Memory block array cells that with a value

of 1 can be changed to 0 only by programming the block.

The status register can be examined for block erase progress and errors by reading any

address. The device remains in the read status register state until another command is

written. SR0 indicates whether the addressed block is erasing. SR7 is set upon erase

completion.

SR7 indicates block erase status while the sequence executes. When the BLOCK ERASE

operation has completed, SR5 = 1 (set) indicates an erase failure. SR3 = 1 indicates that

the device could not perform the BLOCK ERASE operation because V_PPwas outside of

its acceptable limits. SR1 = 1 indicates that the BLOCK ERASE operation attempted to

erase a locked block, causing the operation to abort.

Before issuing a new command, the status register contents should be examined and

then cleared using the CLEAR STATUS REGISTER command. Any valid command can

follow after the BLOCK ERASE operation has completed.

The BLOCK ERASE operation is aborted by performing a reset or powering down the

device. In either case, data integrity cannot be ensured, and it is recommended to erase

again the blocks aborted.

BLANK CHECK Command

The BLANK CHECK operation determines whether a specified main block is blank; that

is, completely erased. Other than a BLANK CHECK operation, only a BLOCK ERASE op-

eration can ensure a block is completely erased. BLANK CHECK is especially useful

when a BLOCK ERASE operation is interrupted by a power loss event.

A BLANK CHECK operation can apply to only one block at a time. The only operation

allowed simultaneously is a READ STATUS REGISTER operation. SUSPEND and RE-

SUME operations and a BLANK CHECK operation are mutually exclusive.

A BLANK CHECK operation is initiated by writing the BLANK CHECK SETUP command

to the block address, followed by the CHECK CONFIRM command. When a successful

command sequence is entered, the device automatically enters the read status state.

The device then reads the entire specified block and determines whether any bit in the

block is programmed or over-erased.

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Erase Operations

BLANK CHECK operation progress and errors are determined by reading the status reg-

ister at any address within the block being accessed. SR7 = 0 is a BLANK CHECK busy

status. SR7 = 1 is a BLANK CHECK operation complete status. The status register should

be checked for any errors and then cleared. If the BLANK CHECK operation fails, mean-

ing the block is not completely erased, SR5 = 1. CE# or OE# toggle (during polling) up-

dates the status register.

The READ STATUS REGISTER command must always be followed by a CLEAR STATUS

REGISTER command. The device remains in status register mode until another com-

mand is written to the device. Any command can follow once the BLANK CHECK com-

mand is complete.

ERASE SUSPEND Command

The ERASE SUSPEND command suspends a BLOCK ERASE operation that is in pro-

gress, enabling access to data in memory locations other than the one being erased. The

ERASE SUSPEND command can be issued to any device address. A BLOCK ERASE oper-

ation can be suspended to perform a WORD or BUFFER PROGRAM operation, or a

READ operation within any block except the block that is erase suspended.

When a BLOCK ERASE operation is executing, issuing the ERASE SUSPEND command

requests the device to suspend the erase algorithm at predetermined points. The device

continues to output status register data after the ERASE SUSPEND command is issued.

Block erase is suspended when SR[7,6] are set.

To read data from the device (other than an erase-suspended block), the READ ARRAY

command must be issued. During erase suspend, a PROGRAM command can be issued

to any block other than the erase-suspended block. Block erase cannot resume until

program operations initiated during erase suspend complete. READ ARRAY, READ STA-

TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and ERASE RESUME are valid

commands during erase suspend. Additionally, CLEAR STATUS REGISTER, PROGRAM,

PROGRAM SUSPEND, BLOCK LOCK, BLOCK UNLOCK, and BLOCK LOCK DOWN are

valid commands during an ERASE SUSPEND operation.

During an erase suspend, de-asserting CE# places the device in standby, reducing active

current. V_PPmust remain at a valid level, and WP# must remain unchanged while in

erase suspend. If RST# is asserted, the device is reset.

ERASE RESUME Command

The ERASE RESUME command instructs the device to continue erasing, and automati-

cally clears SR[7,6]. This command can be written to any address. If status register error

bits are set, the status register should be cleared before issuing the next instruction.

RST# must remain de-asserted.

Erase Protection

When V_PP= V_IL, absolute hardware erase protection is provided for all device blocks. If

V_PPis at or below V_PPLK, ERASE operations halt and SR3 is set indicating a V_PP-level er-

ror.

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Security Operations

Block Locking

Individual instant block locking is used to protect user code and/or data within the

flash memory array. All blocks power-up in a locked state to protect array data from be-

ing altered during power transitions. Any block can be locked or unlocked with no la-

tency. Locked blocks cannot be programmed or erased; they can only be read.

Software-controlled security is implemented using the BLOCK LOCK and BLOCK UN-

LOCK commands. Hardware-controlled security can be implemented using the BLOCK

LOCK DOWN command along with asserting WP#. Also, V_PPdata security can be used

to inhibit PROGRAM and ERASE operations.

BLOCK LOCK Command

To lock a block, issue the BLOCK LOCK SETUP command, followed by the BLOCK LOCK

command issued to the desired block’s address. If the SET READ CONFIGURATION

REGISTER command is issued after the BLOCK LOCK SETUP command, the device

configures the RCR instead.

BLOCK LOCK and UNLOCK operations are not affected by the voltage level on V_PP. The

block lock bits may be modified and/or read even if V_PPis at or below V_PPLK

.

BLOCK UNLOCK Command

The BLOCK UNLOCK command is used to unlock blocks. Unlocked blocks can be read,

programmed, and erased. Unlocked blocks return to a locked state when the device is

reset or powered down. If a block is in a lock-down state, WP# must be de-asserted be-

fore it can be unlocked.

BLOCK LOCK DOWN Command

A locked or unlocked block can be locked-down by writing the BLOCK LOCK DOWN

command sequence. Blocks in a lock-down state cannot be programmed or erased;

they can only be read. However, unlike locked blocks, their locked state cannot be

changed by software commands alone. A locked-down block can only be unlocked by

issuing the BLOCK UNLOCK command with WP# de-asserted. To return an unlocked

block to locked-down state, a BLOCK LOCK DOWN command must be issued prior to

changing WP# to V_IL. Locked-down blocks revert to the locked state upon reset or power

up the device.

Block Lock Status

The READ DEVICE IDENTIFIER command is used to determine a block’s lock status.

DQ[1:0] display the addressed block’s lock status; DQ0 is the addressed block’s lock bit,

while DQ1 is the addressed block’s lock-down bit.

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Security Operations

Figure 9: Block Locking State Diagram

(Power-up/

Reset default)

[000]

D0h

01h

[001]

2Fh

Program/Erase Allowed

WP# = V_IL= 0

Program/Erase Prevented

2Fh

WP# = V_IL= 0

WP# toggle

D0h, 01h, or 2Fh

[010]

[011] (Locked down)

(Virtual lock-down)

WP# toggle

(Lock down

disabled,

D0h

[110]

[100]

01h/2Fh

[111]

WP# = V_IH

)

Program/Erase Allowed

WP# = V_IH= 1

Program/Erase Prevented

WP# = V_IH= 1

2Fh

01h

2Fh

(Power-up/

Reset default)

[101]

1. D0h = UNLOCK command; 01h = LOCK command; 60h (not shown) LOCK SETUP com-

mand; 2Fh = LOCK DOWN command.

Note:

Block Locking During Suspend

Block lock and unlock changes can be performed during an erase suspend. To change

block locking during an ERASE operation, first issue the ERASE SUSPEND command.

Monitor the status register until SR7 and SR6 are set, indicating the device is suspended

and ready to accept another command.

Next, write the desired lock command sequence to a block, which changes the lock

state of that block. After completing BLOCK LOCK or BLOCK UNLOCK operations, re-

sume the ERASE operation using the ERASE RESUME command.

Note:

A BLOCK LOCK SETUP command followed by any command other than BLOCK LOCK,

BLOCK UNLOCK, or BLOCK LOCK DOWN produces a command sequence error and

set SR4 and SR5. If a command sequence error occurs during an erase suspend, SR4 and

SR5 remains set, even after the erase operation is resumed. Unless the Status Register is

cleared using the CLEAR STATUS REGISTER command before resuming the ERASE op-

eration, possible erase errors may be masked by the command sequence error.

If a block is locked or locked-down during an erase suspend of the same block, the lock

status bits change immediately. However, the ERASE operation completes when it is re-

sumed. BLOCK LOCK operations cannot occur during a program suspend.

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Security Operations

Selectable OTP Blocks

The OTP security feature on the device is backward-compatible to the earlier genera-

tion devices. Contact your local Micron representative for details about its implementa-

tion.

Password Access

The password access is a security enhancement offered on the device. This feature pro-

tects information stored in array blocks by preventing content alteration or reads until a

valid 64-bit password is received. The password access may be combined with nonvola-

tile protection and/or volatile protection to create a multi-tiered solution.

Contact your Micron sales office for further details concerning password access.

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Status Register

Read Status Register

To read the status register, issue the READ STATUS REGISTER command at any address.

Status register information is available at the address that the READ STATUS REGISTER,

WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-

matically made available following a word program, block erase, or block lock com-

mand sequence. Reads from the device after any of these command sequences will out-

put the devices status until another valid command is written (e.g. READ ARRAY com-

mand).

The status register is read using single asynchronous mode or synchronous burst mode

reads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In

asynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updates

and latches the status register contents. However, when reading the status register in

synchronous burst mode, CE# or ADV# must be toggled to update status data.

The device write status bit (SR7) provides the overall status of the device. SR[6:1]

present status and error information about the PROGRAM, ERASE, SUSPEND, V_PP, and

BLOCK LOCK operations.

Note: Reading the status register is a nonarray READ operation. When the operation oc-

curs in asynchronous page mode, only the first data is valid and all subsequent data are

undefined. When the operation occurs in synchronous burst mode, the same data word

requested will be output on successive clock edges until the burst length requirements

are satisfied.

Table 12: Status Register Description

Notes apply to entire table

Bits Name

Bit Settings

Description

7

Device write status

(DWS)

0 = Busy

1 = Ready

Status bit: Indicates whether a PROGRAM or

ERASE command cycle is in progress.

6

Erase Suspend Status

(ESS)

0 = Not in effect

1 = In effect

Status bit: Indicates whether an ERASE operation

has been or is going to be suspended.

5:4

Erase/Blank check status 00 = PROGRAM/ERASE successful Status/Error bit: Indicates whether an ERASE/

(ES)

01 = PROGRAM error

10 = ERASE/BLANK CHECK error

11 = Command sequence error

BLANK CHECK or PROGRAM operation was success-

ful. When an error is returned, the operation is

aborted.

Program status (PS)

3

2

1

0

V_PPstatus (VPPS)

0 = Within limits

1 = Exceeded limits (V_PP≤ V_PPLK

Status bit: Indicates whether a PROGRAM/ERASE

operation is within acceptable voltage range limits.

)

Program suspend status 0 = Not in effect

(PSS)

Status bit: Indicates whether a PROGRAM opera-

tion has been or is going to be suspended.

1 = In effect

Block lock status (BLS)

0 = Not locked

1 = Locked (operation aborted)

Status bit: Indicates whether a block is locked

when a PROGRAM or ERASE operation is initiated.

BEFP status (BWS)

Notes:

0 = BEFP complete

1 = BEFP in progress

Status bit: Indicates whether BEFP data has com-

pleted loading into the buffer.

1. Default value = 0x80.

2. Always clear the status register prior to resuming ERASE operations. This eliminates sta-

tus register ambiguity when issuing commands during ERASE SUSPEND. If a command

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512Mb, 1Gb, 2Gb: P33-65nm

Status Register

sequence error occurs during an ERASE SUSPEND, the status register contains the com-

mand sequence error status (SR[7,5,4] set). When the ERASE operation resumes and fin-

ishes, possible errors during the operation cannot be detected via the status register be-

cause it contains the previous error status.

3. When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-

ISTER 50h) or a RESET command must be issued with a 15µs delay.

Clear Status Register

The CLEAR STATUS REGISTER command clears the status register. It functions inde-

pendently of V_PP. The device sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without

clearing them. The status register should be cleared before starting a command se-

quence to avoid any ambiguity. A device reset also clears the status register.

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Configuration Register

Read Configuration Register

The read configuration register (RCR) is a 16-bit read/write register used to select bus

read mode (synchronous or asynchronous) and to configure device synchronous burst

read characteristics. To modify RCR settings, use the CONFIGURE READ CONFIGURA-

TION REGISTER command. RCR contents can be examined using the READ DEVICE

IDENTIFIER command and then reading from offset 0x05. On power-up or exit from re-

set, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-

low.

Note: Reading the configuration register is a nonarray READ operation. When the oper-

ation occurs in asynchronous page mode, only the first data is valid, and all subsequent

data are undefined. When the operation occurs in synchronous burst mode, the same

word of data requested will be output on successive clock edges until the burst length

requirements are satisfied.

Table 13: Read Configuration Register

Bits Name

Settings/Description

15 Read mode (RM)

0 = Synchronous burst mode read

1 = Asynchronous page mode read (default)

14:11 Latency count

(LC[3:0])

0000 = Code 0 (reserved)

0001 = Code 1 (reserved)

0010 = Code 2 (reserved)

0011 = Code 3

0110 = Code 6

0111 = Code 7

1000 = Code 8

1001 = Code 9

1010 = Code 10

1011 = Code11

1100 = Code 12

1101 = Code 13

1110 = Code 14

0100 = Code 4

1111 = Code 15 (default)

0101 = Code 5

10 WAIT polarity (WP)

0 = WAIT signal is active LOW (default)

1 = WAIT signal is active HIGH

9

8

Reserved (R)

Default 0, Nonchangeable

WAIT delay (WD)

0 = WAIT de-asserted with valid data

1 = WAIT de-asserted one data cycle before valid data (default)

7

6

Burst sequence (BS)

Clock edge (CE)

Default 0, Nonchangeable

0 = Falling edge

1 = Rising edge (default)

5:4 Reserved (R)

Burst wrap (BW)

Default 0, Nonchangeable

3

0 = Wrap; Burst accesses wrap within burst length set by BL[2:0]

1 = No Wrap; Burst accesses do not wrap within burst length (default)

2:0 Burst length (BL[2:0]) 001 = 4-word burst

010 = 8-word burst

011 = 16-word burst

111 = Continuous burst (default)

(Other bit settings are reserved)

Read Mode

The read mode (RM) bit selects synchronous burst mode or asynchronous page mode

operation for the device. When the RM bit is set, asynchronous page mode is selected

(default). When RM is cleared, synchronous burst mode is selected.

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Configuration Register

Latency Count

The latency count (LC) bits tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the

first valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-

mine this value. The First Access Latency Count figure shows the data output latency for

different LC settings.

Figure 10: First Access Latency Count

CLK [C]

Valid

Address [A]

Address

ADV# [V]

Code 0 (Reserved

)

Valid

DQ[15:0] [D/Q]

Output

Code

1

(Reserved)

Valid

DQ[15:0] [D/Q]

Output

Code

2

(Reserved)

Valid

Output

Code

3

4

5

6

7

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

1. First Access Latency Count Calculation:

Note:

• 1 / CLK frequency = CLK period (ns)

• n x (CLK period) ≥ ^tAVQV (ns) – ^tCHQV (ns)

• Latency Count = n

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Configuration Register

Figure 11: Example Latency Count Setting Using Code 3

t

Data

0

1

2

3

4

CLK

CE#

ADV#

Address

A[MAX:1]

Code 3

High-Z

D[15:0]

Data

R103

End of Wordline Considerations

End of wordline (EOWL) wait states can result when the starting address of the burst op-

eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does not

equal 0x0. The figure below illustrates the end of wordline wait state(s) that occur after

the first 16-word boundary is reached. The number of data words and wait states is

summarized in the table below.

Figure 12: End of Wordline Timing Diagram

Latency Count

CLK

Address

A[MAX:1]

DQ[15:0]

ADV#

Data

OE#

EOWL

WAIT#

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Configuration Register

Table 14: End of Wordline Data and WAIT State Comparison

130nm

65nm

Latency Count

Data Words

WAIT States

Not Supported

0 to 1

Data Words

WAIT States

Not Supported

0 to 4

1

2

Not Supported

4

Not Supported

3

4

0 to 2

Not Supported

4

0 to 3

Not Supported

5

4

0 to 4

16

6

4

0 to 5

7

4

0 to 6

8

Not Supported

0 to 7

9

0 to 8

10

11

12

13

14

15

0 to 9

0 to 10

0 to 11

0 to 12

0 to 13

0 to 14

WAIT Signal Polarity and Functionality

The WAIT polarity (WP) bit, RCR10 determines the asserted level (V_OHor V_OL) of WAIT.

When WP is set, WAIT is asserted HIGH (default). When WP is cleared, WAIT is asserted

LOW. The WAIT signal changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# de-asserted).

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR15 = 0). The WAIT signal is only de-asserted when data is valid on the bus. When

the device is operating in synchronous nonarray read mode, such as read status, read

ID, or read CFI, the WAIT signal is also de-asserted when data is valid on the bus. WAIT

behavior during synchronous nonarray reads at the end of wordline works correctly on-

ly on the first data access. When the device is operating in asynchronous page mode,

asynchronous single word read mode, and all write operations, WAIT is set to a de-as-

serted state as determined by RCR10.

Table 15: WAIT Functionality Table

Condition

WAIT

High-Z

Notes

CE# = 1, OE# = X or CE# = 0, OE# = 1

CE# = 0, OE# = 0

1

Active

Synchronous Array Reads

Synchronous Nonarray Reads

All Asynchronous Reads

Active

De-asserted

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Configuration Register

Table 15: WAIT Functionality Table (Continued)

Condition

WAIT

Notes

All Writes

High-Z

1, 2

1. Active means that WAIT is asserted until data becomes valid, then deasserts.

2. When OE# = V_IHduring writes, WAIT = High-Z.

Notes:

WAIT Delay

The WAIT delay (WD) bit controls the WAIT assertion delay behavior during synchro-

nous burst reads. WAIT can be asserted either during or one data cycle before valid data

is output on DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid

data (default). When WD is cleared, WAIT is de-asserted during valid data.

Burst Sequence

The burst sequence (BS) bit selects linear burst sequence (default). Only linear burst se-

quence is supported. The synchronous burst sequence for all burst lengths, as well as

the effect of the burst wrap (BW) setting are shown below.

Table 16: Burst Sequence Word Ordering

Burst Addressing Sequence (DEC)

Start

Address

(DEC)

Burst

Wrap

(RCR3)

4-Word Burst

(BL[2:0] =

0b001)

8-Word Burst

16-Word Burst

(BL[2:0] = 0b011)

Continuous Burst

(BL[2:0] = 0b111)

(BL[2:0] = 0b010)

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

⋮

0

1

2

3

4

5

6

7

⋮

0

⋮

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4…14-15

1-2-3-4-5…15-0

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12-…

7-8-9-10-11-12-13…

⋮

2-3-4-5-6…15-0-1

3-4-5-6-7…15-0-1-2

4-5-6-7-8…15-0-1-2-3

5-6-7-8-9…15-0-1-2-3-4

6-7-8-9-10…15-0-1-2-3-4-5

7-8-9-10…15-0-1-2-3-4-5-6

⋮

14

15

⋮

0

⋮

14-15-0-1-2…12-13

15-0-1-2-3…13-14

⋮

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

⋮

0

1

2

3

1

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

0-1-2-3-4…14-15

1-2-3-4-5…15-16

2-3-4-5-6…16-17

3-4-5-6-7…17-18

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

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Configuration Register

Table 16: Burst Sequence Word Ordering (Continued)

Burst Addressing Sequence (DEC)

Start

Address

(DEC)

Burst

Wrap

(RCR3)

4-Word Burst

(BL[2:0] =

0b001)

8-Word Burst

(BL[2:0] = 0b010)

16-Word Burst

(BL[2:0] = 0b011)

Continuous Burst

(BL[2:0] = 0b111)

4

5

1

⋮

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

⋮

4-5-6-7-8…18-19

5-6-7-8-9…19-20

6-7-8-9-10…20-21

7-8-9-10-11…21-22

⋮

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12-…

7-8-9-10-11-12-13…

⋮

6

7

⋮

14

15

1

14-15-16-17-18…28-29

15-16-17-18-19…29-30

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

Clock Edge

Burst Wrap

The clock edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This

clock edge is used at the start of a burst cycle to output synchronous data and to

assert/de-assert WAIT.

The burst wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length

accesses wrap within the selected word length boundaries or cross word length boun-

daries. When BW is set, burst wrapping does not occur (default). When BW is cleared,

burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may

occur when the burst sequence crosses its first device row (16-word) boundary. If the

burst sequence’s start address is 4-word aligned, then no delay occurs. If the start ad-

dress is at the end of a 4-word boundary, the worst-case output delay is one clock cycle

less than the first access latency count. This delay can take place only once and doesn’t

occur if the burst sequence does not cross a device row boundary. WAIT informs the

system of this delay when it occurs.

Burst Length

The burst length bits (BL[2:0]) select the linear burst length for all synchronous burst

reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, or con-

tinuous.

Continuous burst accesses are linear only and do not wrap within any word length

boundaries. When a burst cycle begins, the device outputs synchronous burst data until

it reaches the end of the “burstable” address space.

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One-Time Programmable Registers

Read OTP Registers

The device contains 17 OTP registers that can be used to implement system security

measures and/or device identification. Each OTP register can be individually locked.

The first 128-bit OTP register is comprised of two 64-bit (8-word) segments. The lower

64-bit segment is preprogrammed at the Micron factory with a unique 64-bit number.

The upper 64-bit segment, as well as the other sixteen 128-bit OTP registers, are blank.

Users can program them as needed. Once programmed, users can also lock the OTP

register(s) to prevent additional bit programming (see the OTP Register Map figure be-

low).

The OTP registers contain OTP bits; when programmed, PR bits cannot be erased. Each

OTP register can be accessed multiple times to program individual bits, as long as the

register remains unlocked.

Each OTP register has an associated lock register bit. When a lock register bit is pro-

grammed, the associated OTP register can only be read; it can no longer be program-

med. Additionally, because the lock register bits themselves are OTP, when program-

med, they cannot be erased. Therefore, when an OTP register is locked, it cannot be un-

locked.

The OTP registers can be read from an OTP-RA address. To read the OTP register, a

READ DEVICE IDENTIFIER command is issued at an OTP-RA address to place the de-

vice in the read device identifier state. Next, a READ operation is performed using the

address offset corresponding to the register to be read. The Device Identifier Informa-

tion table shows the address offsets of the OTP registers and lock registers. PR data is

read 16 bits at a time.

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512Mb, 1Gb, 2Gb: P33-65nm

One-Time Programmable Registers

Figure 13: OTP Register Map

0x109

128-bit OTP

Register 16

User Programmable

0x102

0x91

128-bit OTP

Register 1

User Programmable

Lock Register 1

0x8A

0x89

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x88

64-bit Segment

User Programmable

128-bit OTP

Register 0

0x85

0x84

64-bit Segment

Factory Programed

0x81

0x80

Lock Register 0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Program OTP Registers

To program an OTP register, a PROGRAM OTP REGISTER command is issued at the pa-

rameter’s base address plus the offset of the desired OTP register location. Next, the de-

sired OTP register data is written to the same OTP register address.

The device programs the 64-bit and 128-bit user-programmable OTP register data 16

bits at a time. Issuing the PROGRAM OTP REGISTER command outside of the OTP reg-

ister’s address space causes a program error (SR4 set). Attempting to program a locked

OTP register causes a program error (SR4 set) and a lock error (SR1 set).

Lock OTP Registers

Each OTP register can be locked by programming its respective lock bit in the lock regis-

ter. The corresponding bit in the lock register is programmed by issuing the PROGRAM

LOCK REGISTER command, followed by the desired lock register data. The physical ad-

dresses of the lock registers are 0x80 for register 0 and 0x89 for register 1; these address-

es are used when programming the lock registers.

Bit 0 of lock register 0 is programmed during the manufacturing process, locking the

lower-half segment of the first 128-bit OTP register. Bit 1 of lock register 0, which corre-

sponds to the upper-half segment of the first 128-bit OTP register, can be programmed

by the user . When programming bit 1 of lock register 0, all other bits need to be left as 1

such that the data programmed is 0xFFFD.

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512Mb, 1Gb, 2Gb: P33-65nm

One-Time Programmable Registers

Lock register 1 controls the the upper sixteen 128-bit OTP registers. Each bit of lock reg-

ister 1 corresponds to a specific 128-bit OTP register. Programming a bit in lock register

1 locks the corresponding 128-bit OTP register; e.g., programming LR1.0 locks the corre-

sponding OTP register 1.

Note: Once locked, the OTP registers cannot be unlocked.

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

The CFI is part of an overall specification for multiple command-set and control-inter-

face descriptions. System software can parse the CFI database structure to obtain infor-

mation about the device, such as block size, density, bus width, and electrical specifica-

tions. The system software determines which command set to use to properly perform a

WRITE command, a BLOCK ERASE or READ command, and to otherwise control the

device. Information in the CFI database can be viewed by issuing the READ CFI com-

mand.

READ CFI Structure Output

The READ CFI command obtains CFI database structure information and always out-

puts it on the lower byte, DQ[7:0], for a word-wide (x16) device. This CFI-compliant de-

vice always outputs 00h data on the upper byte (DQ[15:8]).

The numerical offset value is the address relative to the maximum bus width the device

supports. For this device family, the starting address is a 10h, which is a word address

for x16 devices. For example, at this starting address of 10h, a READ CFI command out-

puts an ASCII Q in the lower byte and 00h in the higher byte as shown here.

In all the CFI tables shown here, address and data are represented in hexadecimal nota-

tion. In addition, because the upper byte of word-wide devices is always 00h, as shown

in the example here, the leading 00 has been dropped and only the lower byte value is

shown. Following is a table showing the CFI output for a x16 device, beginning at ad-

dress 10h and a table showing an overview of the CFI database sections with their ad-

dresses.

Table 17: Example of CFI Output (x16 device) as a Function of Device and Mode

Hex

Offset

Hex

Code

ASCII Value

(DQ[15:8])

ASCII Value

(DQ[7:0])

Device

Address

00010:

00011:

00012:

00013:

00014:

00015:

00016:

00017:

00018:

51

52

00

Q

R

59

Y

P_ID_LO

P_ID_HI

P_LO

Primary vendor ID

Primary vendor table address

Alternate vendor ID

P_HI

A_ID_LO

A_ID_HI

:

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 18: CFI Database: Addresses and Sections

Address

00001:Fh

00010h

Section Name

Description

Reserved

Reserved for vendor-specific information

CFI ID string

Flash device command set ID (identification) and vendor da-

ta offset

0001Bh

00027h

P

System interface information

Device geometry definition

Flash device timing and voltage

Flash device layout

Primary Micron-specific extended query Vendor-defined informaton specific to the primary vendor

algorithm (offset 15 defines P which points to the primary

Micron-specific extended query table.)

Table 19: CFI ID String

Hex

Code

ASCII Value

(DQ[7:0])

Offset

Length

Description

Address

10:

10h

3

Query unique ASCII string “QRY”

- -51

- -52

- -59

- -01

- -00

Q

11:

R

12:

Y

13h

2

Primary vendor command set and control

interface ID code. 16-bit ID code for ven-

dor-specified algorithms.

13:

Primary vendor ID number

14:

15h

17h

2

Extended query table primary algorithm

address.

15:

16:

17:

18:

- -0A

- -01

- -00

Primary vendor table ad-

dress, primary algorithm

Alternate vendor command set and control

interface ID code. 0000h means no second

vendor-specified algorithm exists.

Alternate vendor ID number

19h

2

Secondary algorithm extended query table

address. 0000h means none exists.

19:

- -00

Primary vendor table ad-

dress, secondary algorithm

1A:

1. The CFI ID string provides verification that the device supports the CFI specification. It

also indicates the specification version and supported vendor-specific command sets.

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 20: System Interface Information

Hex

Code

ASCII Value

(DQ[7:0])

Offset

Length

Description

Address

1Bh

1

V_CClogic supply minimum program/erase voltage.

bits 0 - 3 BCD 100 mV

1Bh

- -23

2.3V

bits 4 - 7 BCD volts

1Ch

1Dh

1Eh

1

V_CClogic supply maximum program/erase volt-

age.

bits 0 - 3 BCD 100 mV

bits 4 - 7 BCD volts

1Ch

1Dh

1Eh

- -36

3.6V

V_PP[programming] supply minimum program/

erase voltage.

bits 0 - 3 BCD 100 mV

- -85

- -95

8.5V

9.5V

bits 4 - 7 hex volts

V_PP[programming] supply maximum program/

erase voltage.

bits 0 - 3 BCD 100 mV

bits 4 - 7 hex volts

1Fh

20h

1

“n” such that typical single word program time-

1Fh

20h

- -09

- -0A

512µs

out = 2ⁿμs.

“n” such that typical full buffer write timeout =

2ⁿμs.

1024µs

21h

22h

1

“n” such that typical block erase timeout = 2ⁿms.

“n” such that typical full chip erase timeout = 2ⁿ

ms.

21h

22h

- -0A

- -00

1s

NA

23h

24h

25h

26h

1

“n” such that maximum word program timeout =

2ⁿtimes typical.

23h

24h

25h

26h

- -01

- -02

- -00

1024µs

4096µs

4s

“n” such that maximum buffer write timeout =

2ⁿtimes typical.

“n” such that maximum block erase timeout = 2ⁿ

times typical.

“n” such that maximum chip erase timeout = 2ⁿ

times typical.

NA

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 21: Device Geometry

Hex

Code

ASCII Value

(DQ[7:0])

Offset Length

Description

n such that device size in bytes = 2ⁿ.

Address

27:

27h

28h

1

2

See Note 1

x16

Flash device interface code assignment: n such that n + 1

specifies the bit field that represents the flash device width

capabilities as described here:

bit 0: x8

28:

- -01

- -00

29:

bit 1: x16

bit 2: x32

bit 3: x64

bits 4 - 7: –

bits 8 - 15: –

2Ah

2Ch

2

1

n such that maximum number of bytes in write buffer = 2ⁿ.

2Ah

2Bh

2Ch

- -0A

- -00

1024

Number of erase block regions (x) within the device:

1) x = 0 means no erase blocking; the device erases in bulk.

2) x specifies the number of device regions with one or more

contiguous, same-size erase blocks.

See Note 1

3) Symmetrically blocked partitions have one blocking region.

2Dh

31h

35h

4

Erase block region 1 information:

bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.

bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.

2D:

2E:

2F:

30:

See Note 1

Erase block region 2 information:

bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.

bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.

31:

32:

33:

34:

Reserved for future erase block region information.

35:

36:

37:

38:

1. See Block Region Map Information table.

Note:

Table 22: Block Region Map Information

512Mb

1Gb

Bottom

2Gb

Symmetrical

--1B

Address

27:

Top

--1A

--01

--00

--0A

--00

--02

--FE

Bottom

--1A

--01

Symmetrical

--1A

Top

--1B

--01

--00

--0A

--00

--02

--FE

Symmetrical

--1B

--01

--00

--0A

--00

--02

--03

--1B

--01

--00

--0A

--00

--01

--FF

28:

--01

29:

--00

2A:

--0A

--00

--0A

2B:

--00

2C:

--02

--01

2D:

--03

--FF

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51

512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 22: Block Region Map Information (Continued)

512Mb

1Gb

Bottom

2Gb

Symmetrical

--03

Address

2E:

Top

--01

--00

--02

--03

--00

--80

--00

Bottom

--00

Symmetrical

--01

Top

--03

--00

--02

--03

--00

--80

--00

Symmetrical

--00

--80

--00

--FE

--03

--00

--02

--00

--03

--00

--02

--00

2F:

--80

--00

30:

--00

--02

31:

--FE

--00

32:

--01

--00

33:

--00

34:

--02

--00

35:~38:

--00

Table 23: Primary Vendor-Specific Extended Query

Hex Offset

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address Hex Code

(P+0)h

(P+1)h

(P+2)h

3

Primary extended query table, unique ASCII

string: PRI

10A:

10B:

10C:

10D:

10E:

- -50

- -52

- -49

- -31

- -35

P

R

I

(P+3)h

(P+4)h

1

Major version number, ASCII

Minor version number, ASCII

1

5

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52

512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 23: Primary Vendor-Specific Extended Query (Continued)

Hex Offset

ASCII Value

P = 10Ah

Length

Description

Address Hex Code

(DQ[7:0])

(P+5)h

(P+6)h

(P+7)h

(P+8)h

4

Optional feature and command support (1 = yes;

0 = no)

Bits 11 - 29 are reserved; undefined bits are 0

If bit 31 = 1, then another 31-bit field of optional

features follows at the end of the bit 30 field.

10F:

110:

111:

112:

- -E6

- -01

–

- -00

See Note 1

Bit 0: Chip erase supported.

bit 0 = 0

No

Yes

No

Yes

No

Yes

Bit 1: Suspend erase supported.

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 1

bit 8 = 1

bit 9 = 0

Bit 2: Suspend program supported.

Bit 3: Legacy lock/unlock supported.

Bit 4: Queued erase supported.

Bit 5: Instant individual block locking supported.

Bit 6: OTP bits supported.

Bit 7: Page mode read supported.

Bit 8: Synchronous read supported.

Bit 9: Simultaneous operations supported.

Bit 10: Extended Flash array block supported.

bit 10 = 0

bit 11 = 0

Bit 11: Permanent block locking of up to full

main array supported.

Bit 12: Permanent block locking of up to partial

main array supported.

bit 12 = 0

No

Bit 30: CFI links to follow:

bit 30

bit 31

See Note 1

Bit 31: Another optional features field to follow.

(P+9)h

1

2

Supported functions after SUSPEND: READ AR-

RAY, STATUS, QUERY. Other supported options in-

clude:

113:

- -01

–

Bits 1 - 7: Reserved; undefined bits are 0.

Bit 0: Program supported after ERASE SUSPEND.

bit 0 = 1

Yes

–

(P+A)h

(P+B)h

Block Status Register mask:

Bits 2 - 15 are reserved; undefined bits are 0.

114:

115:

- -03

- -00

–

Bit 0: Block lock-bit status register active.

Bit 1: Block lock-down bit status active.

Bit 4: EFA block lock-bit status register active.

Bit 5: EFA block lock-bit status active.

bit 0 = 1

bit 1 = 1

bit 4 = 0

bit 5 = 0

Yes

No

3.0V

(P+C)h

1

V_CClogic supply highest performance program/

erase voltage.

116:

- -30

bits 0 - 3 BCD 100 mV

bits 4 - 7 hex value in volts

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 23: Primary Vendor-Specific Extended Query (Continued)

Hex Offset

ASCII Value

P = 10Ah

Length

Description

Address Hex Code

(DQ[7:0])

(P+D)h

1

V_PPoptimum program/erase voltage.

bits 0 - 3 BCD 100mV

117:

- -90

9.0V

bits 4 - 7 hex value in volts

1. See Optional Features Fields table.

Note:

Table 24: Optional Features Field

Discrete

2Gb

Address

Bottom

Top

–

Bottom

Top

–

die 1 (B)

40:

die 2 (T)

--00

die 1 (T)

--40

die 2 (B)

--00

112:

--00

Table 25: One Time Programmable (OTP) Space Information

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

(P+E)h

1

Number of OTP block fields in JEDEC ID space.

00h indicates that 256 OTP fields are available.

118:

- -02

2

OTP Field 1: OTP Description:

119:

11A:

1B:

- -80

- -00

- -03

80h

00h

This field describes user-available OTP bytes.

Some are preprogrammed with device-unique se-

rial numbers. Others are user-programmable.

Bits 0-15 point to the OTP Lock byte (the first

byte).

8 byte

11C:

(P+F)h

(P+10)h

(P+11)h

(P+12)h

The following bytes are factory preprogrammed

and user-programmable:

Bits 0 - 7 = Lock/bytes JEDEC plane physical low

address.

4

Bits 8 - 15 = Lock/bytes JEDEC plane physical high

address.

Bits 16 - 23 = n where 2ⁿequals factory preprog-

rammed bytes.

Bits 24 - 31 = n where 2ⁿequals user-programma-

ble bytes.

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 25: One Time Programmable (OTP) Space Information (Continued)

Hex Offset

P = 10Ah

Hex

Code

ASCII Value

(DQ[7:0])

Length

Description

Address

11D:

(P+13)h

(P+14)h

(P+15)h

(P+16)h

10

Protection field 2: protection description

Bits 0 - 31 point to the protection register physi-

cal lock word address in the JEDEC plane.

The bytes that follow are factory or user-progam-

mable.

- -89

- -00

89h

00h

11E:

11F:

120:

(P+17)h

(P+18)h

(P+19)h

Bits 32 - 39 = n where n equals factory program-

med groups (low byte).

Bits 40 - 47 = n where n equals factory program-

med groups (high byte).

121:

122:

123:

- -00

0

Bits 48 - 55 = n where 2n equals factory program-

med bytes/groups.

(P+1A)h

(P+1B)h

(P+1C)h

Bits 56 - 63 = n where n equals user programmed

groups (low byte).

Bits 64 - 71 = n where n equals user programmed

groups (high byte).

Bits 72 - 79 = n where 2ⁿequals user programma-

ble bytes/groups.

124:

125:

126:

- -10

- -00

- -04

16

0

16

Table 26: Burst Read Information

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

1

Page Mode Read capability:

127:

- -05

32 byte

Bits 7 - 0 = n where 2ⁿhex value represents the

number of read-page bytes. See offset 28h for

device word width to determine page-mode data

output width. 00h indicates no read page buffer.

(P+1D)h

1

Number of synchronous mode read configuration

128:

- -04

(P+1E)h

fields that follow. 00h indicates no burst capabili-

ty.

4

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 26: Burst Read Information (Continued)

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

1

Synchronous mode read capability configuration

1:

129:

- -01

Bits 3 - 7 = Reserved.

Bits 0 - 2 = n where 2ⁿ⁺¹hex value represents the

maximum number of continuous synchronous

reads when the device is configured for its maxi-

mum word width.

A value of 07h indicates that the device is capa-

ble of continuous linear bursts that will output

data until the internal burst counter reaches the

end of the device’s burstable address space.

This fields’s 3-bit value can be written directly to

the Read Configuration Register bits 0 - 2 if the

device is configured for its maximum word width.

See offset 28h for word width to determine the

burst data output width.

(P+1F)h

4

1

Synchronous mode read capability configuration

2.

12A:

12B:

12C:

- -02

- -03

- -07

8

16

(P+20)h

(P+21)h

(P+22)

Synchronous mode read capability configuration

3.

Synchronous mode read capability configuration

4.

Continued

Table 27: Partition and Block Erase Region Information

Hex Offset

P = 10Ah

Address

Bottom

12D:

Description

Optional Flash features and commands

Bottom

Top

Length

Top

(P+23)h

Number of device hardware-partition regions

within the device:

1

12D:

x = 0: a single hardware partition device (no

fields follow).

x specifies the number of device partition regions

containing one or more contiguous erase block

regions

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 28: Partition Region 1 Information: Top and Bottom Offset/Address

Hex Offset

P = 10Ah

Address

Bottom

Description

Optional Flash features and commands

Bottom

Top

Length

Top

12E:

12F:

(P+24)h

(P+25)h

(P+24)h

(P+25)h

Data size of this Partition Region information field

(number of addressable locations, including this

field.

2

12E:

12F:

(P+26)h

(P+27)h

(P+26)h

(P+27)h

Number of identical partitions within the partition

region.

2

1

130:

131:

132:

130:

131:

132:

(P+28)h

(P+29)h

(P+28)h

(P+29)h

Number of program or erase operations allowed in a

partition:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

Bits 4 - 7 = Number of simultaneous erase operations.

Simultaneous program or erase operations allowed

in other partitions while a partition in this region is

in program mode:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

1

133:

134:

135:

133:

134:

135:

Bits 4 - 7 = Number of simultaneous erase operations.

(P+2A)h

(P+2B)h

(P+2A)h

(P+2B)h

Simultaneous program or erase operations allowed

in other partitions while a partition in this region is

in erase mode:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

Bits 4 - 7 = Number of simultaneous erase operations.

Types of erase block regions in this partition region:

x=0: No erase blocking; the partition region erases in

bulk.

x = Number of erase block regions with contiguous,

same-size erase blocks.

Symmetrically blocked partitions have one blocking

region.

Partition size = (Type 1 blocks) x (Type 1 block sizes) +

(Type 2 blocks) x (Type 2 block sizes) +...+ (Type n

blocks) x (Type n block sizes).

Table 29: Partition Region 1 Information

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+2C)h

(P+2D)h

(P+2E)h

(P+2F)h

Partition region 1 erase block type 1 information:

Bits 0-15 = y, y+1 = Number of identical-sized erase blocks in a

partition.

4

136:

137:

138:

139:

Bits 16-31 = z, where region erase block(s) size is z x 256 bytes.

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 29: Partition Region 1 Information (Continued)

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+30)h

(P+31)h

Partition 1 (erase block type 1):

Minimum block erase cycles x 1000

2

13A:

13B:

(P+32)h

(P+33)h

Partition 1 (erase block type 1) bits per cell; internal ECC:

Bits 0 - 3 = bits per cell in erase region

Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

Bit 5 - 7 = reserved for future use

1

13C:

Partition 1 (erase block type 1) page mode and synchronous

mode capabilities:

13D:

Bits 0 = page-mode host reads permitted (1=yes, 0=no)

Bit 1 = synchronous host reads permitted (1=yes, 0=no)

Bit 2 = synchronous host writes permitted (1=yes, 0=no)

Bit 3 - 7 = reserved for future use

(P+34)h

(P+35)h

(P+36)h

(P+37)h

(P+38)h

(P+39)h

Partition 1 (erase block type 1) programming region information:

Bits 0 - 7 = x, 2^x: programming region aligned size (bytes)

Bit 8-14 = reserved for future use

Bit 15 = legacy flash operation; ignore 0:7

Bit 16 - 23 = y: control mode valid size (bytes)

Bit 24 - 31 = reserved for future use

6

13E:

13F:

140:

141:

142:

143:

Bit 32 - 39 = z: control mode invalid size (bytes)

Bit 40 - 46 = reserved for future use

Bit 47 = legacy flash operation (ignore 23:16 and 39:32)

(P+3A)h

(P+3B)h

(P+3C)h

(P+3D)h

Partition 1 erase block type 2 information:

Bits 0-15 = y, y+1 = Number of identical-size erase blocks in a par-

tition.

Bits 16 - 31 = z, where region erase block(s) size is z x 256 bytes.

(bottom parameter device only)

4

144:

145:

146:

147:

(P+3E)h

(P+3F)h

Partition 1 (erase block type 2)

Minimum block erase cycles x 1000

2

1

148:

149:

14A:

(P+40)h

Partition 1 (erase block type 2) bits per cell, internal EDAC:

Bits 0 - 3 = bits per cell in erase region

Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

Bits 5 - 7 = reserved for future use

(P+41)h

Partition 1 (erase block type 2) page mode and synchronous

mode capabilities:

1

14B:

Bit 0 = page-mode host reads permitted (1=yes, 0=no)

Bit 1 = synchronous host reads permitted (1=yes, 0=no)

Bit 2 = synchronous host writes permitted (1=yes, 0=no)

Bits 3-7 = reserved for future use

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512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 29: Partition Region 1 Information (Continued)

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+42)h

(P+43)h

(P+44)h

(P+45)h

(P+46)h

(P+47)h

Partition 1 (erase block type 2) programming region information:

Bits 0-7 = x, 2ⁿx = Programming region aligned size (bytes)

Bits 8-14 = reserved for future use

Bit 15 = legacy flash operation (ignore 0:7)

Bits 16 - 23 = y = Control mode valid size in bytes Bits 24 - 31 =

reserved

6

14C:

14D:

14E:

14F:

150:

Bits 32 - 39 = z = Control mode invalid size in bytes

Bits 40 - 46 = reserved

151:

Bit 47 = legacy flash operation (ignore 23:16 and 39:32)

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59

512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 30: Partition Region 1: Partition and Erase Block Map Information

Add.

512Mb

1Gb

2Gb

Symm.

Top

--01

--24

--00

--01

--00

--11

--00

--02

--FE

--01

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

Bottom

Symm.

--01

--14

--00

--01

--00

--11

--00

--01

--FF

--01

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--FF

Top

--01

--24

--00

--01

--00

--11

--00

--02

--FE

--03

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

Bottom

--01

--24

--00

--01

--00

--11

--00

--02

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--FE

--03

--00

--02

--64

--00

--02

--03

--00

--80

--00

Symm.

--01

--14

--00

--01

--00

--11

--00

--01

--FF

--03

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--FF

Upper Die

Lower Die

12D:

12E:

12F:

130:

131:

132:

133:

134:

135:

136:

137:

138:

139:

13A:

13B:

13C:

13D*:

13E:

13F:

140:

141:

142:

143:

144:

145:

146:

147:

148:

149:

14A:

14B:

14C:

14D:

14E:

14F:

150:

--01

--24

--00

--01

--00

--11

--00

--02

--03

--00

--80

--00

--64

--00

--02

--03

--00

--80

--00

--80

--FE

--01

--00

--02

--64

--00

--02

--03

--00

--80

--00

--01

--14

--00

--01

--00

--11

--00

--01

--FF

--03

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--FF

--01

--14

--00

--01

--00

--11

--00

--01

--FF

--03

--00

--02

--64

--00

--02

--03

--00

--80

--00

--80

--10

--C8

--00

--10

--FF

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60

512Mb, 1Gb, 2Gb: P33-65nm

Common Flash Interface

Table 30: Partition Region 1: Partition and Erase Block Map Information (Continued)

Add.

512Mb

1Gb

2Gb

Symm.

Top

Bottom

--80

Symm.

Top

Bottom

Symm.

Upper Die

Lower Die

151:

--80

--FF

--80

--FF

Table 31: CFI Link Information – 2Gb

ASCII Value

(DQ[7:0])

Length

Description

Address

4

CFI Link field bit definitions:

144:

145:

146:

147

See Note 1

Bits 0 - 9 = Address offset (within 32Mb segment of referenced CFI table)

Bits 10 - 27 = nth 32Mb segment of referenced CFI table

Bits 28 - 30 = Memory Type

Bit 31 = Another CFI link field immediately follows

1

CFI Link field quantity subfield definitions:

Bits 0 - 3 = Quantity field (n such that n+1 equals quantity)

Bit 4 = Table and die relative location

Bit 5 = Link field and table relative location

Bits 6 - 7 = Reserved

148:

1. See "Partition Region 1: Partition and Erase Block Map Information" table.

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

Flowcharts

Figure 14: Word Program Procedure

Start

Command Cycle

- Issue PROGRAM command

- Address = location to program

- Data = 0x40

Data Cycle

- Address = location to program

- Data = data to program

Check Ready Status

- READ STATUS REGISTER command not required

- Perform READ operation

- Read ready status on signal D7

No

Program suspend

(See Suspend/Resume

Flowchart

No

Yes

D7 = 1?

Suspend?

Errors?

Yes

Read Status Register

- Toggle CE# or OE# to update status register

- See Status Register Flowchart

Error-handler

user-defined routine

Progam

complete

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512Mb, 1Gb, 2Gb: P33-65nm

Flowcharts

Figure 15: Buffer Program Procedure

Start

X = X + 1

Write buffer data,

start address

Write buffer data,

(at block address)

within buffer range

Device

supports buffer

writes?

No

Use single word

programming

X = 0

No

Yes

Abort

bufferred program

?

No

X = N

Yes

Set timeout or

loop counter

Yes

Get next

target address

Write confirm D0h

(at block address)

Write to another

block address

Buffered program

aborted

Read status register

(at block address)

CE# and OE# LOW

Issue WRITE-to-BUFFER

command E8h

(at block address)

updates status register

No

Yes

SR7?

1 = Ready

0 = Busy

0

Suspend

program loop

Suspend

program

Read status register

SR7 = Valid

(at block address )

1

No

Full status

check (if desired)

Device

ready? SR7 = 0/1

Timeout

or count expired?

0 = No

Yes

Another

buffered

programming

?

Yes

1 = Yes

Write word count (N-1)

N = 0 corresponds to

count = 1

No

(at block address)

Program

complete

1. Word count values on DQ0:DQ15 are loaded into the count register. Count ranges for

this device are N = 0000h to 01FFh.

Notes:

2. Device outputs the status register when read.

3. Write buffer contents will be programmed at the device start or destination address.

4. Align the start address on a write buffer boundary for maximum programming perform-

ance; that is, A[9:1] of the start address = 0).

5. Device aborts the BUFFERED PROGRAM command if the current address is outside the

original block address.

6. Status register indicates an improper command sequence if the BUFFERED PROGRAM

command is aborted. Follow this with a CLEAR STATUS REGISTER command.

7. Device defaults to SR output data after BUFFERED PROGRAMMING SETUP command

(E8h) is issued . CE# or OE# must be toggled to update the status register . Don’t issue

the READ SR command (70h); it is interpreted by the device as buffer word count.

8. Full status check can be done after erase and write sequences complete. Write FFh after

the last operation to reset the device to read array mode.

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Flowcharts

Figure 16: Buffered Enhanced Factory Programming (BEFP) Procedure

Setup Phase

Program and Verify Phase

Exit Phase

Read status

register

Read status

register

Start

Issue BEFP SETUP

Data = 0x80

Buffer ready?

BEFP exited?

No (SR0 = 1)

No (SR7 = 0)

Yes (SR7 = 1)

Yes (SR0 = 0)

Issue BEFP CONFIRM

Data = 00D0h

Full status

register check

for errors

Write data

word to buffer

BEFP setup

delay

No

Buffer full?

Yes

Finish

Read status

register

Read status

register

Yes (SR7 = 0)

BEFP setup

done?

No (SR0 = 1)

Program

done?

No (SR7 = 1)

SR error-handler

user-defined

Yes (SR0 = 0)

Yes

Program

more data

Exit

?

No

Write 0xFFFF

outside block

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Flowcharts

Figure 17: Block Erase Procedure

Start

Command Cycle

- Issue ERASE command

- Address = block to be erased

- Data = 0x20

Confirm Cycle

- Issue CONFIRM command

- Address = block to be erased

- Data = erase confirm (0xD0)

Check Ready Status

- READ STATUS REGISTER

command not required

- Perform READ operation

- Read ready status on SR7

No

Erase Suspend

See Suspend/

Resume Flowchart

Yes

No

SR7 = 1?

Suspend?

Errors?

Yes

Read Status Register

- Toggle CE# or OE#

to update status register

- See Status Register Flowchart

Error Handler

user-defined

routine

End

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Flowcharts

Figure 18: Program Suspend/Resume Procedure

Start

=

SR2

0

Program

Completed

1 = Suspended

0 = Completed

Read Status

Write 70h

1

Any Address

Read Array

Program Suspend

Write FFh

Any Address

Write B0h

Any Address

Read Array Data

from a block other than

from the one being

programmed

Read Status Register

Initiate Read cycle to

update the status register

(Address = Block to suspend)

Done

No

Reading

=

SR7

0

Yes

1 = Ready

0 = Busy

Read Array

Write FFh

Program Resume

1

Write D0h

Any Address

Program

Resumed

Read Array

Data

Read Status

Write 70h

Any Address

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Flowcharts

Figure 19: Erase Suspend/Resume Procedure

=

SR6

Start

0

Erase

Completed

1 = Suspended

0 = Completed

Read Status

1

Write 70h

Any Address

Read

Program

Erase Suspend

Read/Program?

(FFh/40h)

Write B0h

Any Address

Read Array Data from

a block other than the

one being erased

Program Loop: to a

block other than the

one being erased

No

Done?

Address = X

Read Status Register

Toggle CE#/OE# to

update the

status register

Yes

Erase Resume

=

SR7

0

1 = Ready

0 = Busy

Read Array

Write D0h

Any Address

1

Write FFh

1

Erase

Resumed

Read Array

Data

Read Status

Write 70h

Any Address

1. The ^tERS/SUSP timing between the initial BLOCK ERASE or ERASE RESUME command and

a subsequent ERASE SUSPEND command should be followed.

Note:

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Flowcharts

Figure 20: Block Lock Operations Procedure

Start

Lock Setup

Write 60h

Block Address

Lock Confirm

Write 01h, D0h, 2Fh

Block Address

Read ID Plane

Write 90h

Read Block

Lock Status

Optional

No

Locking

Change?

Yes

Read Array

Write FFh

Any Address

Lock Change

Complete

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Flowcharts

Figure 21: OTP Register Programming Procedure

Start

OTP Program Setup

- Write 0xC0

- OTP Address

Confirm Data

- Write OTP Address and Data

Check Ready Status

- READ STATUS REGISTER

command not required

- Perform READ operation

- Read ready status on SR7

No

SR7 = 1?

Yes

Read Status Register

- Toggle CE# or OE#

to update status register

- See Status Register Flowchart

End

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Flowcharts

Figure 22: Status Register Procedure

Start

Command Cycle

- Issue STATUS REGISTER command

- Address = any device address

- Data = 0x70

Data Cycle

- Read Status Register SR[7:0]

No

SR7 = 1

Yes

Erase Suspend

See Suspend/

Yes

SR6 = 1

Resume Flowchart

No

Program Suspend

See Suspend/

Resume Flowchart

Yes

SR2 = 1

No

Error

Command

sequence

No

SR5 = 1

SR4 = 1

Yes

Error

Erase failure

No

Yes

Error

Program failure

SR4 = 1

No

Error

V

/V

<

SR3 = 1

PEN PP

/V

PENLK PPLK

No

Error

Block locked

SR1 = 1

No

End

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Power and Reset Specifications

V_CCshould attain V_CCminfrom V_SSsimultaneously with or before applying V_CCQ, V_PP

during power up. V_CCshould attain V_SSduring power down. Device inputs should not

be driven before supply voltage = V_CCmin

.

Power supply transitions should only occur when RST# is LOW. This protects the device

from accidental programming or erasure during power transitions.

Asserting RST# during a system reset is important with automated program/erase devi-

ces because systems typically expect to read from the device when coming out of reset.

If a CPU reset occurs without a device reset, proper CPU initialization may not occur.

This is because the device may be providing status information, instead of array data as

expected. Connect RST# to the same active LOW reset signal used for CPU initialization.

Because the device is disabled when RST# is asserted, it ignores its control inputs dur-

ing power-up/down. Invalid bus conditions are masked, providing a level of memory

protection.

Table 32: Power and Reset

Parameter

Symbol

^tPLPH

Min

100

–

Max

–

Unit

ns

Notes

RST# pulse width LOW

1, 2, 3, 4

1, 3, 4, 7

1, 4, 5, 6

RST# LOW to device reset during erase

RST# LOW to device reset during program

V_CCPower valid to RST# de-assertion (HIGH)

25

–

us

–

^tVCCPH

300

1. These specifications are valid for all device versions (packages and speeds).

2. The device may reset if ^tPLPH is < ^tPLPH MIN, but this is not guaranteed.

Notes:

3. Not applicable if RST# is tied to V_CC

4. Sampled, but not 100% tested.

.

5. When RST# is tied to the V_CCsupply, device will not be ready until ^tVCCPH after V_CC

≥

V_CCMIN

6. When RST# is tied to the V_CCQsupply, device will not be ready until ^tVCCPH after V_CC

V_CCMIN

.

≥

.

7. Reset completes within ^tPLPH if RST# is asserted while no ERASE or PROGRAM operation

is executing.

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Power and Reset Specifications

Figure 23: Reset Operation Waveforms

^tPLPH

^tPLRH

^tPHQV

V_IH

V_IL

(A) Reset during

RST#

read mode

Abort

^tPHQV

complete

V_IH

V_IL

(B) Reset during

RST#

program or block erase

≤

P1 P2

^tPLRH

^tPHQV

Abort

complete

V_IH

V_IL

(C) Reset during

program or block erase

≥

P1 P2

^tVCCPH

(D) V power-up to

V_CC

0V

CC

V

CC

RST# HIGH

Power Supply Decoupling

The device requires careful power supply de-coupling. Three basic power supply cur-

rent considerations are 1) standby current levels, 2) active current levels, and 3) transi-

ent peaks produced when CE# and OE# are asserted and de-asserted.

When the device is accessed, internal conditions change. Circuits within the device ena-

ble charge pumps, and internal logic states change at high speed. These internal activi-

ties produce transient signals. Transient current magnitudes depend on the device out-

puts’ capacitive and inductive loading. Two-line control and correct de-coupling capac-

itor selection suppress transient voltage peaks.

Because the devices draw their power from V_CC, V_PP, and V_CCQ, each power connection

should have a 0.1µF and a 0.01µF ceramic capacitor to ground. High-frequency, inher-

ently low-inductance capacitors should be placed as close as possible to package leads.

Additionally, for every eight devices used in the system, a 4.7µF electrolytic capacitor

should be placed between power and ground close to the devices. The bulk capacitor is

meant to overcome voltage droop caused by PCB trace inductance.

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Maximum Ratings and Operating Conditions

Stresses greater than those listed can cause permanent damage to the device. This is

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated is not guaranteed.

Table 33: Maximum Ratings

Parameter

Maximum Rating

–40°C to + 85 °C

–65°C to + 125 °C

–2V to +5.6V

–2V to +11.5V

–2V to +5.6V

100mA

Notes

Temperature under bias

Storage temperature

Voltage on any signal (except V_CC, V_PP, and V_CCQ

V_PPvoltage

)

1

1, 2

1

V_CCvoltage

V_CCQvoltage

1

Output short circuit current

3

1. Voltages shown are specified with respect to V_SS. During infrequent nonperiodic transi-

Notes:

tions, the level may undershoot to –2V for periods less than 20ns or overshoot to V_CC

2V or V_CCQ+ 2V or V_PP+ 2V for periods less than 20ns.

+

2. Program/erase voltage is typically 2.3–3.6V. 9.0V can be applied for 80 hours maximum

total, to any blocks for 1000 cycles maximum. 9.0V program/erase voltage may reduce

block cycling capability.

3. Output is shorted for no more than one second, and more than one output is not shor-

ted at one time.

Table 34: Operating Conditions

Symbol

T_A

Parameter

Min

–40

2.3

Max

+85

3.6

9.5

80

Unit Notes

Operating temperature

V_CCsupply voltage

I/O supply voltage

°C

V

1

V_CC

V_CCQ

CMOS inputs

TTL inputs

2.3

2.4

V_PPL

V_PPH

^tPPH

V_PPvoltage supply (logic level)

1.5

2

Buffered enhanced factory programming V_PP

Maximum V_PPhours

8.5

V_PP= V_PPH

V_PP= V_PPL

V_PP= V_PPH

–

Hours

Cycles

BLOCK

ERASE cycles

Array blocks

100,000

–

1000

1. T_A= ambient temperature.

Notes:

2. In typical operation, V_PPprogram voltage is V_PPL

.

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DC Electrical Specifications

Table 35: DC Current Characteristics

CMOS Inputs

(V_CCQ= 2.3–

3.6V)

TTL Inputs

(V_CCQ= 2.4–

3.6V)

Parameter

Symbol Typ

Max

Typ

Max Unit Test Conditions

Notes

Input load current 512Mb

1Gb

I_LI

–

±1

–

±2

µA V_CC= V_CC(MAX)

V_CCQ= V_CCQ(MAX)

V_IN= V_CCQor V_SS

1, 6

2Gb

–

±2

±1

–

±4

Output leakage

current

512Mb

1Gb

I_LO

±10

µA V_CC= V_CC(MAX)

V_CCQ= V_CCQ(MAX)

V_IN= V_CCQor V_SS

DQ[15:0], WAIT

2Gb

–

±2

–

±20

225

240

480

V_CCstandby,

power-down

512Mb

1Gb

I_CCS

I_CCD

,

70

225

240

480

70

µA V_CC= V_CC(MAX)

V_CCQ= V_CCQ(MAX)

CE# = V_CCQ

1. 2

75

2Gb

150

RST# = V_CCQ(for I_CCS

)

RST# = V_SS(for I_CCD

WP# = V_IH

)

Average Asynchronous

V_CCread single-word

current f = 5 MHz (1 CLK)

I_CCR

26

12

19

16

31

16

22

18

26

12

19

16

31

16

22

18

mA 16-word read V_CC= V_CC(MAX)

1

CE# = V_IL

OE# = V_IH

mA 8-word read

Inputs:

mA 16-word read

Page mode read

f = 13 MHz (17 CLK)

mA 16-word read

V_ILor V_IH

Synchronous burst

f = 52 MHz, LC = 4

21

35

24

50

21

35

24

50

mA Continuous

read

V_CCprogram current,

V_CCerase current

I_CCW,

I_CCE

mA V_PP= V_PPL

program/erase in progress

V_PP= V_PPH

program/erase in progress

µA CE# = V_CCQ, suspend in progress 1, 3, 4

,

1, 3, 5

,

1, 3, 5

V_CCprogram sus-

pend current,

V_CCerase suspend

current

512Mb

I_CCWS,

I_CCES

70

75

225

240

70

75

225

240

1Gb

2Gb

V_PPstandby current 512Mb

I_PPS

0.2

0.4

0.2

5

0.2

0.4

0.2

5

µA V_PP= V_PPL

,

1, 3, 7

in standby mode

1Gb

2Gb

10

5

10

5

V_PPprogram suspend current,

V_PPerase suspend current

µA V_PP= V_PPL

,

I_PPWS,

I_PPES

suspend in progress

V_PPread

I_PPR

2

15

0.1

2

15

0.1

µA V_PP= V_PPL

1, 3

3

V_PPprogram current

I_PPW

0.05

mA V_PP= V_PPL, program in progress

V_PP= V_PPH, program in progress

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DC Electrical Specifications

Table 35: DC Current Characteristics (Continued)

CMOS Inputs

(V_CCQ= 2.3–

3.6V)

TTL Inputs

(V_CCQ= 2.4–

3.6V)

Parameter

Symbol Typ

Max

0.1

Typ

Max Unit Test Conditions

Notes

V_PPerase current

I_PPE

0.05

0.1

mA V_PP= V_PPL, erase in progress

V_PP= V_PPH, erase in progress

mA V_PP= V_PPL

3

0.1

V_PPblank check

I_PPBC

0.1

3

0.1

V_PP= V_PPH

1. All currents are RMS unless noted. Typical values at TYP V_CC, T_C= +25°C.

Notes:

2. I_CCSis the average current measured over any 5ms time interval 5µs after CE# is de-asser-

ted.

3. Sampled, not 100% tested.

4. I_CCESis specified with the device deselected. If device is read while in erase suspend, cur-

rent is I_CCESplus I_CCR

.

5. I_CCW, I_CCEmeasured over TYP or MAX times specified in (page 0 ).

6. if V_IN> V_CC, the input load current increases to 10µA MAX.

7. the I_{PPS, PPWS, PPES}

I

will increase to 200µA when V_PP/WP# is at V_PPH

.

Table 36: DC Voltage Characteristics

CMOS Inputs

TTL Inputs¹

(V_CCQ= 2.3–3.6V)

(V_CCQ= 2.4–3.6V)

Parameter

Symbol

V_IL

Min

Max

Min

–0.5

2

Max

0.6

Unit Test Conditions

Notes

Input low voltage

Input high voltage

Output low voltage

–0.5

0.4

V

2

V_IH

V_CCQ- 0.4 V_CCQ+ 0.5

V_CCQ+ 0.5

0.2

V_OL

–

V_CCQ- 0.2

–

0.2

–

V

V_CC= V_CC(MIN)

V_CCQ= V_CCQ(MIN)

I_OL= 100µA

Output high voltage

V_PPlock out voltage

V_OH

–

V_CCQ– 0.2

–

V_CC= V_CC(MIN)

V_CCQ= V_CCQ(MIN)

I_OH= –100µA

V_PPLK

0.4

–

0.4

3

1. Synchronous read mode is not supported with TTL inputs.

Notes:

2. V_ILcan undershoot to –1.0V for durations of 2ns or less and V_IHcan overshoot to V_CCQ

1.0V for durations of 2ns or less.

+

3. V_PP≤ V_PPLKinhibits ERASE and PROGRAM operations. Do not use V_PPLand V_PPHoutside

their valid ranges.

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AC Test Conditions and Capacitance

Figure 24: AC Input/Output Reference Timing

V_CCQ

Input V

/2

Test points

V

/2 output

CCQ

0V

1. AC test inputs are driven at V_CCQfor logic 1 and at 0V for logic 0. Input/output timing

begins/ends at V_CCQ/2. Input rise and fall times (10% to 90%) <5ns. Worst-case speed oc-

curs at V_CC= V_CC(MIN).

Note:

Figure 25: Transient Equivalent Load Circuit

Device under

test

Out

C

L

1. See the Test Configuration for Worst-Case Speed Conditions table for component values.

2. CL includes jig capacitance.

Notes:

Table 37: Test Configuration: Worst-Case Speed Condition

Test Configuration

C_L(pF)

V_CCQ(MIN) standard test

30

Figure 26: Clock Input AC Waveform

^tCLK

V_IH

CLK

V_IL

^tCH/CL

^tFCLK/RCLK

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AC Test Conditions and Capacitance

Table 38: Capacitance

Sym-

Parameter

bol

Signal

Density

512Mb

1Gb

Min

Typ

7

Max Unit

Condition

Notes

Input

Capacitance

C_IN

Address, Data,

CE#, WE#, OE#,

RST#, CLK,

3

4

6

8

9

pF

TYP temp = 25°C; MAX

temp = 85°C

V_CC= 0–2.0V, V_CCQ= 0–

3.6V

1

8

2Gb

16

18

ADV#, WP#

Discrete silicon die

Output

Capacitance

C_OUT

Data, WAIT

512Mb

1Gb

3

6

5

7

6

2Gb

10

12

1. Sampled, but not 100% tested.

Note:

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AC Read Specifications

Table 39: AC Read Specifications

Parameter

Symbol

Min

Max

Unit

Notes

Asynchronous Specifications

READ cycle time

^tAVAV

^tAVQV

^tELQV

Easy BGA

512Mb/1Gb

2Gb

95

100

105

–

ns

–

TSOP

512Mb/1Gb

2Gb

–

Address to output valid

CE# LOW to output valid

Easy BGA

95

100

105

95

100

105

25

150

–

ns

–

TSOP

512Mb/1Gb

2Gb

–

Easy BGA

–

TSOP

512Mb/1Gb

–

ns

–

1, 2

1

OE# LOW to output valid

^tGLQV

^tPHQV

^tELQX

^tGLQX

^tEHQZ

^tGHQZ

^tOH

-

RST# HIGH to output valid

CE# LOW to output in Low-Z

OE# LOW to output in Low-Z

CE# HIGH to output in High-Z

OE# HIGH to output in High-Z

-

0

1, 3

1, 2, 3

1, 3

0

–

20

15

–

Output hold from first occur-

ring address, CE#, or OE#

change

0

CE# pulse width HIGH

^tEHEL

^tELTV

^tEHTZ

^tGLTV

^tGLTX

^tGHTZ

17

–

ns

1

CE# LOW to WAIT valid

CE# HIGH to WAIT High-Z

OE# LOW to WAIT valid

OE# LOW to WAIT in Low-Z

OE# HIGH to WAIT in High-Z

17

20

17

–

1, 3

1

–

0

–

1, 3

20

Latching Specifications (Easy BGA)

Address setup to ADV# HIGH

CE# LOW to ADV# HIGH

^tAVVH

^tELVH

^tVLQV

10

–

ns

1

ADV# LOW to output valid

Easy BGA

TSOP

512Mb/1Gb

2Gb

95

100

105

–

512Mb/1Gb

–

ns

ADV# pulse width LOW

^tVLVH

^tVHVL

^tVHAX

^tAPA

10

9

ADV# pulse width HIGH

–

Address hold from ADV# HIGH

Page address access

–

1, 4

1

–

25

-

RST# HIGH to ADV# HIGH

Clock Specifications (Easy BGA)

^tPHVH

30

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AC Read Specifications

Table 39: AC Read Specifications (Continued)

Parameter

Symbol

^tCLK

^tCH/CL

^tFCLK/RCLK

Min

–

Max

Unit

MHz

ns

Notes

CLK frequency

CLK period

52

–

1, 3, 5, 6

19.2

5

CLK HIGH/LOW time

CLK fall/rise time

–

ns

0.3

3

ns

Synchronous Specifications (Easy BGA)⁵

Address setup to CLK

ADV# LOW setup to CLK

CE# LOW setup to CLK

CLK to output valid

^tAVCH/L

^tVLCH/L

^tELCH/L

^tCHQV /

^tCLQV

9

–

ns

1, 6

–

17

Output hold from CLK

Address hold from CLK

CLK to WAIT valid

^tCHQX

^tCHAX

^tCHTV

^tCHVL

^tCHTX

3

10

–

-

ns

1, 6

1, 4, 6

1, 6

1

17

–

CLK valid to ADV# setup

WAIT hold from CLK

3

–

1, 6

1. See AC Test Conditions for timing measurements and maximum allowable input slew

rate.

Notes:

2. OE# may be delayed by up to ^tELQV – ^tGLQV after CE#’s falling edge without impact to

^tELQV.

3. Sampled, not 100% tested.

4. Address hold in synchronous burst mode is ^tCHAX or ^tVHAX, whichever timing specifica-

tion is satisfied first.

5. Synchronous read mode is not supported with TTL level inputs.

6. Applies only to subsequent synchronous reads.

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AC Read Specifications

Figure 27: Asynchronous Single-Word Read (ADV# LOW)

^tAVAV

^tAVQV

A

ADV#

^tELQV

CE#

^tEHQZ

^tGHQZ

^tGLQV

OE#

^tGLTV

^tGHTZ

WAIT

^tGLQX

^tELQX

DQ

^tPHQV

RST#

1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted

LOW).

Note:

Figure 28: Asynchronous Single-Word Read (ADV# Latch)

^tAVAV

^tAVQV

A[MAX:5]

A[4:1]

^tAVVH

^tVHAX

^tVHVL

ADV#

CE#

^tELQV

^tEHQZ

^tGLQV

^tGHQZ

OE#

^tGHTZ

^tGLTV

WAIT

^tGLQX

^tOH

^tELQX

DQ

1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted

LOW).

Note:

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AC Read Specifications

Figure 29: Asynchronous Page Mode Read

^tAVQV

Valid address

A[MAX:5]

^tOH

A[4:1]

ADV#

0

1

2

F

^tAVVH

^tVHVL

^tVHAX

^tELQV

^tGLQV

^tEHQZ

^tGHQZ

CE#

OE#

WAIT

DQ

^tELQX

^tAPA

^tEHTZ

Q16

Q1

Q2

Q3

1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted

LOW).

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

AC Read Specifications

Figure 30: Synchronous Single-Word Array or Nonarray Read

^tAVCH

^tCHAX

^tAVQV

CLK

A

^tAVVH

^tVHVL

^tELCH

^tVHAX

^tVLVH

ADV#

^tELVH

^tEHQZ

^tGHQZ

^tELQV

CE#

OE#

^tGLQX

^tGLTX

^tCHTV

^tCHQV

^tGHTZ

^tCHTX

WAIT

^tGLQV

^tCHQX

DQ

1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be

configured to assert either during or one data cycle before valid data.

Notes:

2. In this example, an n-word burst is initiated to the flash memory array and is terminated

by CE# deassertion after the first word in the burst.

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AC Read Specifications

Figure 31: Continuous Burst Read with Output Delay

^tAVCH

^tVLCH ^tCHAX

CLK

^tCHQV

^tAVQV

^tAVVH

A

^tVHAX

^tVHVL

ADV#

^tELCH

^tELVH

^tELQV

CE#

OE#

^tGLTX

^tCHTV

^tCHQV

^tCHTX

^tCHQX

WAIT

DQ

^tGLQV

^tGLQX

^tCHQX

1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be

configured to assert either during or one data cycle before valid data.

Notes:

2. At the end of a wordline; the delay incurred when a burst access crosses a 16-word

boundary and the starting address is not 4-word boundary aligned.

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512Mb, 1Gb, 2Gb: P33-65nm

AC Read Specifications

Figure 32: Synchronous Burst Mode 4-Word Read

^tAVCH

Latency count

^tVLCH ^tCHAX

CLK

^tAVQV

^tAVVH

A

^tVHAX

^tVHVL

^tELVH

ADV#

^tELCH

^tEHQZ

^tGHQZ

^tELQV

CE#

OE#

^tGLTV

^tCHTV

^tCHQV

^tGHTZ

WAIT

DQ

^tCHQV

^tCHQX

^tGLQV

^tGLQX

^tOH

Q0

Q1

Q2

Q3

1. WAIT is driven per OE# assertion during synchronous array or nonarray read. WAIT as-

serted during initial latency and deasserted during valid data (RCR10 = 0, WAIT asserted

LOW).

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

AC Write Specifications

Table 40: AC Write Specifications

Parameter

Symbol

^tPHWL

^tELWL

Min

Max

Unit

ns

Notes

1, 2, 3

1, 2, 4

1, 2, 12

1, 2

RST# HIGH recovery to WE# LOW

CE# setup to WE# LOW

150

-

0

WE# write pulse width LOW

Data setup to WE# HIGH

^tWLWH

^tDVWH

^tAVWH

^tWHEH

^tWHDX

^tWHAX

^tWHWL

^tVPWH

^tQVVL

50

Address setup to WE# HIGH

CE# hold from WE# HIGH

Data hold from WE# HIGH

Address hold from WE# HIGH

WE# pulse width HIGH

50

0

20

1, 2, 5

V_PPsetup to WE# HIGH

200

1, 2, 3, 7

V_PPhold from status read

WP# hold from status read

WP# setup to WE# HIGH

0

^tQVBL

0

200

1, 2, 3, 7

^tBHWH

^tWHGL

^tWHQV

WE# HIGH to OE# LOW

0

1, 2, 9

WE# HIGH to read valid

t_AVQV+ 35

1, 2, 3, 6, 10

Write to Asynchronous Read Specifications

WE# HIGH to address valid

Write to Synchronous Read Specifications

WE# HIGH to clock valid

^tWHAV

0

-

ns

1, 2, 3, 6, 8

^tWHCH/L

^tWHVH

^tWHVL

19

7

-

ns

1, 2, 3, 6, 10

WE# HIGH to ADV# HIGH

WE# HIGH to ADV# LOW

Write Specification with Clock Active

ADV# HIGH to WE# LOW

Clock HIGH to WE# LOW

^tVHWL

^tCHWL

-

20

ns

1, 2, 3, 11

1. Write timing characteristics during erase suspend are the same as WRITE-only opera-

tions.

Notes:

2. A WRITE operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width LOW (^tWLWH or ^tELEH) is defined from CE# or WE# LOW (whichever

occurs last) to CE# or WE# HIGH (whichever occurs first). Thus, ^tWLWH = ^tELEH = ^tWLEH

= ^tELWH.

5. Write pulse width HIGH ^tWHWL or ^tEHEL) is defined from CE# or WE# HIGH whichever

occurs first) to CE# or WE# LOW whichever occurs last). Thus, ^tWHWL = ^tEHEL = t_WHEL

^tEHWL).

=

6. ^tWHVH or ^tWHCH/L must be met when transitioning from a WRITE cycle to a synchro-

nous BURST read.

7. V_PPand WP# should be at a valid level until erase or program success is determined.

8. This specification is only applicable when transitioning from a WRITE cycle to an asyn-

chronous read. See spec ^tWHCH/L and ^tWHVH for synchronous read.

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AC Write Specifications

9. When doing a READ STATUS operation following any command that alters the status

register, ^tWHGL is 20ns.

10. Add 10ns if the WRITE operation results in an RCR or block lock status change, for the

subsequent READ operation to reflect this change.

11. These specs are required only when the device is in a synchronous mode and the clock is

active during an address setup phase.

12. This specification must be complied with customer’s writing timing. The result would be

unpredictable if there is any violation to this timing specification.

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AC Write Specifications

Figure 33: Write to Write Timing

Figure 34: Asynchronous Read to Write Timing

^tAVAV

^tAVQV

^tAVWH

^tWHAX

A

^tEHQZ

^tELQV

CE#

^tGLQV

^tGHQZ

OE#

^tELWL

^tWLWH

^tWHEH

WE#

^tGLTV

^tGHTZ

^tOH

WAIT

^tGLQX

^tELQX

^tWHDX

^tDVWH

DQ

Q

D

^tPHQV

RST#

1. WAIT de-asserted during asynchronous read and during write. WAIT High-Z during write

per OE# deasserted.

Note:

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AC Write Specifications

Figure 35: Write to Asynchronous Read Timing

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AC Write Specifications

Figure 36: Synchronous Read to Write Timing

^tAVCH

Latency count

^tVLCH ^tCHAX

CLK

^tAVQV

^tAVVH

^tWHAV

^tAVWH

A

^tVHVL

^tVHAX

^tELVH

^tVLVH

^tEHEL

ADV#

^tELCH

^tELQV

^tEHTZ

^tWHEH

CE#

^tGHQZ

^tGLQV

OE#

^tVHWL

^tCHWL

^tVLWH

^tVHWL

^tWHAX

^tWLWH

^tCHWL

^tELWL

^tWHWL

WE#

^tGLTX

^tCHTV

WAIT

^tCHTX

^tCHQX

^tCHQV

^tWHDX

^tGLQX

DQ

Q

D

1. WAIT shown de-asserted and High-Z per OE# de-assertion during WRITE operation

(RCR10 = 0, WAIT asserted LOW). Clock is ignored during WRITE operation.

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

AC Write Specifications

Figure 37: Write to Synchronous Read Timing

Latency count

^tVLCH

^tAVCH

^tAVQV

CLK

^tAVWH

^tWHAX

^tCHAX

^tVHAX

A

^tVLVH

ADV#

^tELWL

^tWHEH

^tEHEL ^tELCH

CE#

^tWHAV

^tWHCH/L

^tWHVH

^tWLWH

WE#

OE#

^tGLQV

^tGLTX

^tELQV

^tCHTV

WAIT

^tCHQV

^tCHQX

^tCHQV

^tDVWH

^tWHDX

DQ

D

Q

^tPHWL

RST#

1. WAIT shown de-asserted and High-Z per OE# de-assertion during WRITE operation

(RCR10 = 0, WAIT asserted LOW).

Note:

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512Mb, 1Gb, 2Gb: P33-65nm

Program and Erase Characteristics

Table 41: Program and Erase Specifications

V_PPL

Typ

V_PPH

Parameter

Symbol

Min

Max

Min

Typ

Max Unit Notes

Conventional Word Programming

Program

time

Single word

^tPROG/W

–

270

456

–

270

456

µs

1

Buffered Programming

Program

time

Aligned, BP time (32

words)

^tPROG

–

310

375

505

900

716

900

–

310

375

505

900

716

900

Aligned, BP time (64

words)

Aligned, BP time (128

words)

1140

1690

3016

1140

1690

3016

Aligned, BP time (256

words)

One full buffer, BP time

(512 words)

Buffered Enhanced Factory Programming

Program

Single byte

BEFP Setup

^tBEFP/B

^tBEFP/SETUP

N/A

–

0.5

–

µs

1, 2

1

20

Erase and Suspend

Erase time 32KB parameter

128KB main

^tERS/PB

^tERS/MB

^tSUSP/P

^tSUSP/E

^tERS/SUSP

–

0.8

25

4.0

30

–

0.8

25

4.0

30

–

s

1

Suspend la- Program suspend

µs

tency

Erase suspend

25

Erase-to-suspend

500

1, 3

Blank Check

Blank check Main array block

^tBC/MB

–

3.2

–

3.2

–

ms

1. Typical values measured at T_C= +25°C and nominal voltages. Performance numbers are

valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested.

Notes:

2. Averaged over entire device.

3. ^tERS/SUSP is the typical time between an initial BLOCK ERASE or ERASE RESUME com-

mand and the a subsequent ERASE SUSPEND command. Violating the specification re-

peatedly during any particular block erase may cause erase failures.

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Revision History

Rev. C – 12/13

• On cover page, corrected erase suspend (TYP) from 30μs to 25μs.

• Revised timings

Rev. B – 11/13

Rev. A – 8/13

• Added the following part number disclaimer: "Not all part numbers listed here are

available for ordering."

• Initial Micron brand release

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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92


型号：	JS28F00AP33BFA
厂家：	MICRON TECHNOLOGY
描述：	Micron Parallel NOR Flash Embedded Memory (P33-65nm) 光电二极管内存集成电路闪存
文件：	总92页 (文件大小：987K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

JS28F00AP33BFA [MICRON]

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