M25PX80-VMP6TG [MICRON]
M25PX80 NOR Serial Flash Embedded Memory;
| 型号： | M25PX80-VMP6TG |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | M25PX80 NOR Serial Flash Embedded Memory 时钟 光电二极管 内存集成电路 |
| 文件： | 总56页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25PX80 Serial Flash Embedded Memory
Features
M25PX80 NOR Serial Flash Embedded
Memory
8Mb, Dual I/O, 4KB Subsector Erase, 3V Serial Flash Memory
with 75 MHz SPI Bus Interface
• Write protections
– Software write protection: applicable to every
Features
• SPI bus compatible serial interface
• 75 MHz (maximum) clock frequency
• 2.3V to 3.6V single supply voltage
• Dual input/output instructions resulting in an
equivalent clock frequency of 150MHz
– Dual output fast read instruction
– Dual input fast program instruction
• 8Mb flash memory
– Uniform 4KB subsectors
– Uniform 64KB sectors
• Additional 64-byte user-lockable, one-time pro-
grammable (OTP) area
• Erase capability
64KB sector (volatile lock bit)
– Hardware write protection: protected area size
defined by non-volatile bits BP0, BP1, BP2
• Deep power down: 5µA (TYP)
• Electronic signature
– JEDEC standard 2-byte signature (7114h)
– Unique ID code (UID) with 16-byte read-only
space, available upon request
• More than 100,000 write cycles per sector
• More than 20 years data retention
• Packages (RoHS compliant)
– VFQFPN8 (MP) 6mm x 5mm
– SO8W (MW) 208mils
– SO8N (MN) 150mils
• Automotive grade parts available
– Subsector (4KB granularity)
– Sector (64KB granularity)
– Bulk erase (8Mb) in 8 s (TYP)
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Products and specifications discussed herein are subject to change by Micron without notice.
M25PX80 Serial Flash Embedded Memory
Features
Contents
Functional Description ..................................................................................................................................... 6
Signal Descriptions ........................................................................................................................................... 8
Serial Peripheral Interface Modes ...................................................................................................................... 9
Operating Features ......................................................................................................................................... 11
Page Programming ..................................................................................................................................... 11
Dual Input Fast Program ............................................................................................................................. 11
Subsector Erase, Sector Erase, Bulk Erase ..................................................................................................... 11
Polling during a Write, Program, or Erase Cycle ............................................................................................ 11
Active Power, Standby Power, and Deep Power-Down .................................................................................. 11
Status Register ............................................................................................................................................ 12
Data Protection by Protocol ........................................................................................................................ 12
Software Data Protection ............................................................................................................................ 12
Hardware Data Protection .......................................................................................................................... 13
Hold Condition .......................................................................................................................................... 14
Memory Configuration and Block Diagram ...................................................................................................... 15
Memory Map – 8Mb Density ........................................................................................................................... 16
Command Set Overview ................................................................................................................................. 17
WRITE ENABLE .............................................................................................................................................. 19
WRITE DISABLE ............................................................................................................................................. 20
READ ID ........................................................................................................................................................ 21
READ STATUS REGISTER ................................................................................................................................ 22
WIP Bit ...................................................................................................................................................... 22
WEL Bit ...................................................................................................................................................... 22
Block Protect Bits ....................................................................................................................................... 23
Top/Bottom Bit .......................................................................................................................................... 23
SRWD Bit ................................................................................................................................................... 23
WRITE STATUS REGISTER .............................................................................................................................. 24
READ DATA BYTES ......................................................................................................................................... 26
READ DATA BYTES at HIGHER SPEED ............................................................................................................ 27
DUAL OUTPUT FAST READ ............................................................................................................................ 28
READ LOCK REGISTER ................................................................................................................................... 29
READ OTP ...................................................................................................................................................... 30
PAGE PROGRAM ............................................................................................................................................ 31
DUAL INPUT FAST PROGRAM ........................................................................................................................ 32
PROGRAM OTP .............................................................................................................................................. 33
WRITE to LOCK REGISTER ............................................................................................................................. 35
SUBSECTOR ERASE ....................................................................................................................................... 36
SECTOR ERASE .............................................................................................................................................. 37
BULK ERASE .................................................................................................................................................. 38
DEEP POWER-DOWN ..................................................................................................................................... 39
RELEASE from DEEP POWER-DOWN .............................................................................................................. 40
Power-Up/Down and Supply Line Decoupling ................................................................................................. 41
Maximum Ratings and Operating Conditions .................................................................................................. 43
Electrical Characteristics ................................................................................................................................ 44
AC Characteristics .......................................................................................................................................... 45
Package Information ...................................................................................................................................... 52
Device Ordering Information .......................................................................................................................... 55
Revision History ............................................................................................................................................. 56
Rev. C – 1/2014 ........................................................................................................................................... 56
Rev. B – 3/2013 ........................................................................................................................................... 56
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M25PX80 Serial Flash Embedded Memory
Features
Rev. A – 11/2012 .......................................................................................................................................... 56
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M25PX80 Serial Flash Embedded Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 6
Figure 2: Pin Connections: VFQFPN, SO8N ...................................................................................................... 7
Figure 3: Bus Master and Memory Devices on the SPI Bus ............................................................................... 10
Figure 4: SPI Modes ....................................................................................................................................... 10
Figure 5: Hold Condition Activation ............................................................................................................... 14
Figure 6: Block Diagram ................................................................................................................................ 15
Figure 7: WRITE ENABLE Command Sequence .............................................................................................. 19
Figure 8: WRITE DISABLE Command Sequence ............................................................................................. 20
Figure 9: READ ID: Command Sequence ........................................................................................................ 21
Figure 10: READ STATUS REGISTER Command Sequence .............................................................................. 22
Figure 11: STATUS REGISTER Format ............................................................................................................ 22
Figure 12: WRITE STATUS REGISTER Command Sequence ............................................................................. 24
Figure 13: READ DATA BYTES Command Sequence ........................................................................................ 26
Figure 14: READ DATA BYTES AT HIGHER SPEED Command Sequence .......................................................... 27
Figure 15: DUAL OUTPUT FAST READ Command Sequence ........................................................................... 28
Figure 16: READ LOCK REGISTER Command Sequence ................................................................................. 29
Figure 17: READ OTP Command Sequence .................................................................................................... 30
Figure 18: PAGE PROGRAM Command Sequence ........................................................................................... 31
Figure 19: DUAL INPUT FAST PROGRAM Command Sequence ....................................................................... 32
Figure 20: PROGRAM OTP Command Sequence ............................................................................................. 33
Figure 21: How to Permanently Lock the OTP Bytes ........................................................................................ 34
Figure 22: WRITE to LOCK REGISTER Instruction Sequence ........................................................................... 35
Figure 23: SUBSECTOR ERASE Command Sequence ...................................................................................... 36
Figure 24: SECTOR ERASE Command Sequence ............................................................................................. 37
Figure 25: BULK ERASE Command Sequence ................................................................................................. 38
Figure 26: DEEP POWER-DOWN Command Sequence ................................................................................... 39
Figure 27: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 40
Figure 28: Power-Up Timing .......................................................................................................................... 42
Figure 29: AC Measurement I/O Waveform ..................................................................................................... 45
Figure 30: Serial Input Timing ........................................................................................................................ 49
Figure 31: Write Protect Setup and Hold during WRSR when SRWD=1 Timing ................................................. 49
Figure 32: Hold Timing .................................................................................................................................. 50
Figure 33: Output Timing .............................................................................................................................. 50
Figure 34: VPPH Timing ................................................................................................................................. 51
Figure 35: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 52
Figure 36: SO8W 208 mils Body Width ............................................................................................................ 53
Figure 37: SO8N 150 mils Body Width ............................................................................................................ 54
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M25PX80 Serial Flash Embedded Memory
Features
List of Tables
Table 1: Signal Descriptions ............................................................................................................................. 8
Table 2: SPI Modes .......................................................................................................................................... 9
Table 3: Software Protection Truth Table ........................................................................................................ 13
Table 4: Sectors 0 to 16, Protected Area Sizes – Upper Area Protection .............................................................. 13
Table 5: Sectors 0 to 16, Protected Area Sizes – Lower Area Protection .............................................................. 13
Table 6: Sectors 15:0 ...................................................................................................................................... 16
Table 7: Command Set Codes ........................................................................................................................ 18
Table 8: READ ID :Data Out Sequence ............................................................................................................ 21
Table 9: Status Register Protection Modes ...................................................................................................... 25
Table 10: Lock Register Out ............................................................................................................................ 29
Table 11: Lock Register In .............................................................................................................................. 35
Table 12: Absolute Maximum Ratings ............................................................................................................. 43
Table 13: Operating Conditions ...................................................................................................................... 43
Table 14: Data Retention and Endurance ........................................................................................................ 43
Table 15: Power Up Timing Specifications ...................................................................................................... 44
Table 16: DC Current Specifications ............................................................................................................... 44
Table 17: DC Voltage Specifications ................................................................................................................ 44
Table 18: AC Measurement Conditions ........................................................................................................... 45
Table 19: Capacitance .................................................................................................................................... 45
Table 20: AC Specifications (75MHz) .............................................................................................................. 46
Table 21: AC Specifications (50 MHz) ............................................................................................................. 47
Table 22: Part Number Information Scheme ................................................................................................... 55
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M25PX80 Serial Flash Embedded Memory
Functional Description
Functional Description
The M25PX80 is an 8Mb (1Mb x 8) serial Flash memory device, with advanced write
protection mechanisms, accessed by a high speed SPI-compatible bus. The device sup-
ports two high-performance dual input/output commands that double the transfer
bandwidth for read and program operations:
• DUAL OUTPUT FAST READ command reads data at up to 75MHz by using both pin
DQ1 and pin DQ0 as outputs.
• DUAL INPUT FAST PROGRAM command programs data at up to 75MHz by using
both pin DQ1 and pin DQ0 as inputs.
Note: 75MHz operation is available only in VCC range 2.7V to 3.6V.
The memory can be programmed 1 to 256 bytes at a time, using the PAGE PROGRAM
command. It is organized as 16 sectors that are each further divided into 16 subsectors
(256 subsectors in total).
The memory can be erased a 4Kb subsector at a time, a 64Kb sector at a time, or as a
whole. It can be write protected by software using a mix of volatile and non-volatile pro-
tection features, depending on the application needs. The protection granularity is of
64Kb (sector granularity).
The device has 64 one-time-programmable bytes (OTP bytes) that can be read and pro-
grammed using two dedicated commands, READ OTP and PROGRAM OTP, respectively.
These 64 bytes can be locked permanently by a particular PROGRAM OTP sequence.
Once they have been locked, they become read-only and this state cannot be reverted.
Further features are available as additional security options. More information on these
security features is available, upon completion of an NDA (nondisclosure agreement),
and are, therefore, not described in this datasheet. For more details of this option con-
tact your nearest Micron sales office.
Figure 1: Logic Diagram
V
CC
DQ0
C
DQ1
S#
W#/V
PP
HOLD#
V
SS
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M25PX80 Serial Flash Embedded Memory
Functional Description
Signal Name
Function
Direction
Input
C
Serial clock
DQ0
Serial data input
I/O
(Serves as output during DUAL OUTPUT FAST READ operation)
DQ1
Serial data output
I/O
(Serves as input during DUAL INPUT FAST PROGRAM operation)
S#
Chip select
Input
Input
Input
–
W#/VPP
HOLD#
VCC
Write protect or enhanced program supply voltage
Hold
Supply voltage
Ground
VSS
–
Figure 2: Pin Connections: VFQFPN, SO8N
V
1
2
3
4
8
7
6
5
S#
DQ1
CC
HOLD#
C
W#/VPP
V
DQ0
SS
There is an exposed central pad on the underside of the VFQFPN package. This is pulled
internally to VSS, and must not be connected to any other voltage or signal line on the
PCB. The Package Mechanical section provides information on package dimensiions
and how to identify pin 1.
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M25PX80 Serial Flash Embedded Memory
Signal Descriptions
Signal Descriptions
Table 1: Signal Descriptions
Signal
Type
Description
DQ1
Output
Serial data: The DQ1 output signal is used to transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock (C). During the DUAL INPUT
FAST PROGRAM command, pin DQ1 is used as an input. It is latched on the rising edge
of C.
DQ0
Input
Serial data: The DQ0 input signal is used to transfer data serially into the device. It
receives commands, addresses, and the data to be programmed. Values are latched on
the rising edge of the serial clock (C). During the DUAL OUTPUT FAST READ command,
pin DQ0 is used as an output. Data is shifted out on the falling edge of C.
C
Input
Input
Clock: The C input signal provides the timing of the serial interface. Commands, ad-
dresses, or data present at serial data input (DQ0) is latched on the rising edge of the
serial clock (C). Data on DQ1 changes after the falling edge of C.
S#
Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at
HIGH impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy-
cle is in progress, the device will be in the standby power mode (not the DEEP POWER-
DOWN mode). Driving S# LOW enables the device, placing it in the active power
mode. After power-up, a falling edge on S# is required prior to the start of any com-
mand.
HOLD#
W#/VPP
Input
Input
Hold: The HOLD# signal is used to pause any serial communications with the device
without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C
are "Don’t Care." To start the hold condition, the device must be selected, with S#
driven LOW.
Write protect/enhanced program supply voltage:The W#/VPP signal is both a con-
trol input and a power supply pin. The two functions are selected by the voltage
range applied to the pin. If the W#/VPP input is kept in a low voltage range (0 V to
VCC) the pin is seen as a control input. The W# input signal is used to freeze the size of
the area of memory that is protected against program or erase commands as specified
by the values in BP2, BP1, and BP0 bits of the Status Register. VPP acts as an additional
power supply if it is in the range of VPPH, as defined in the AC Measurement Condi-
tions table. Avoid applying VPPH to the W#/VPP pin during a Bulk Erase operation.
VCC
VSS
Power
Device core power supply: Source voltage.
Ground: Reference for the VCC supply voltage.
Ground
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M25PX80 Serial Flash Embedded Memory
Serial Peripheral Interface Modes
Serial Peripheral Interface Modes
The device can be driven by a microcontroller while its serial peripheral interface (SPI)
is in either of the two modes shown here. The difference between the two modes is the
clock polarity when the bus master is in standby mode and not transferring data. Input
data is latched in on the rising edge of the clock, and output data is available from the
falling edge of the clock.
Table 2: SPI Modes
SPI Modes
Clock Polarity
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
C remains at 0 for (CPOL = 0, CPHA = 0)
C remains at 1 for (CPOL = 1, CPHA = 1)
The following figure is an example of three memory devices in a simple connection to
an MCU on an SPI bus. Because only one device is selected at a time, that one device
drives DQ1, while the other devices are HIGH-Z.
Resistors ensure the device is not selected if the bus master leaves S# HIGH-Z. The bus
master might enter a state in which all input/output is HIGH-Z simultaneously, such as
when the bus master is reset. Therefore, the serial clock must be connected to an exter-
nal pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW.
This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH
is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp =
parasitic capacitance of the bus line), is shorter than the time the bus master leaves the
SPI bus in HIGH-Z.
Example: Cp = 50 pF, that is R × Cp = 5μs. The application must ensure that the bus
master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs. W# and
HOLD# should be driven either HIGH or LOW, as appropriate.
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M25PX80 Serial Flash Embedded Memory
Serial Peripheral Interface Modes
Figure 3: Bus Master and Memory Devices on the SPI Bus
VSS
VCC
R
SDO
SDI
SPI interface:
(CPOL, CPHA) =
(0, 0) or (1, 1)
SCK
C
VCC
VCC
VCC
C
C
VSS
VSS
VSS
SPI bus master
DQ1 DQ0
DQ1 DQ0
DQ1 DQ0
SPI memory
device
SPI memory
device
SPI memory
device
R
R
R
CS3
CS2 CS1
S#
S#
S#
W# HOLD#
W# HOLD#
W# HOLD#
Figure 4: SPI Modes
CPOL CPHA
0
1
0
1
C
C
MSB
DQ0
MSB
DQ1
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M25PX80 Serial Flash Embedded Memory
Operating Features
Operating Features
Page Programming
To program one data byte, two commands are required: WRITE ENABLE, which is one
byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by
the internal PROGRAM cycle of duration tPP. To spread this overhead, the PAGE PRO-
GRAM command allows up to 256 bytes to be programmed at a time (changing bits
from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To
optimize timings, it is recommended to use the PAGE PROGRAM command to program
all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM
sequences with each containing only a few bytes.
Dual Input Fast Program
The DUAL INPUT FAST PROGRAM command makes it possible to program up to 256
bytes using two input pins at the same time (by changing bits from 1 to 0). For opti-
mized timings, it is recommended to use the DUAL INPUT FAST PROGRAM command
to program all consecutive targeted bytes in a single sequence than to use several DUAL
INPUT FAST PROGRAM sequences each containing only a few bytes.
Subsector Erase, Sector Erase, Bulk Erase
The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-
ieved a subsector at a time using the SUBSECTOR ERASE command, a sector at a time
using the SECTOR ERASE command, or throughout the entire memory using the BULK
ERASE command. This starts an internal ERASE cycle of duration tSSE, tSE or tBE. The
ERASE command must be preceded by a WRITE ENABLE command.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE).
• WRITE STATUS REGISTER
• PROGRAM OTP
• PROGRAM
• DUAL INPUT FAST PROGRAM
• ERASE (SUBSECTOR ERASE, SECTOR ERASE, BULK ERASE)
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.
When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER
mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS
REGISTER). The device then goes in to the STANDBY POWER mode. The device con-
sumption drops to ICC1
.
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M25PX80 Serial Flash Embedded Memory
Operating Features
The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command
is executed. The device consumption drops further to ICC2. The device remains in this
mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in
the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see DEEP POWER-DOWN.
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific commands. For a detailed description of the status register
bits, see READ STATUS REGISTER.
Data Protection by Protocol
Non-volatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they
are accepted for execution to ensure they consist of a number of clock pulses that is a
multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit.
In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-
fers extra software protection since all WRITE, PROGRAM, and ERASE commands are
ignored when the device is in this mode.
Software Data Protection
Memory can be configured as read-only using the top/bottom bit and the block protect
bits (BP2, BP1, BP0) as shown in the Protected Area Sizes table.
Memory sectors can be protected by specific lock registers assigned to each 64KB sec-
tor. These lock registers can be read and written using the READ LOCK REGISTER and
WRITE to LOCK REGISTER commands. In each lock register the following two bits con-
trol the protection of each sector:
• Write lock bit: This bit determines whether the contents of the sector can be modified
using the WRITE, PROGRAM, and ERASE commands. When the bit is set to ‘1’, the
sector is write protected, and any operations that attempt to change the data in the
sector will fail. When the bit is reset to ‘0’, the sector is not write protected by the lock
register, and may be modified.
• Lock down bit: This bit provides a mechanism for protecting software data from sim-
ple hacking and malicious attack. When the bit is set to '1’, further modification to the
write lock bit and lock down bit cannot be performed. A power-up, is required before
changes to these bits can be made. When the bit is reset to ‘0’, the write lock bit and
lock down bit can be changed.
The software protection truth table shows the lock down bit and write lock bit settings
and the sector protection status.
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M25PX80 Serial Flash Embedded Memory
Operating Features
Table 3: Software Protection Truth Table
Sector Lock Register
Bits
Lock Down Write Lock
Protection Status
0
0
1
0
1
0
Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status reversible
Sector protected from PROGRAM / ERASE / WRITE operations; protection status reversible
Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status cannot be
changed except by a power-up.
1
1
Sector protected from PROGRAM / ERASE / WRITE operations; protection status cannot be
changed except by a power-up.
Hardware Data Protection
Hardware data protection is implemented using the write protect signal applied on the
W#/VPP pin. This freezes the status register in a read-only mode, protecting the block
protect (BP) bits and the status register write disable bit (SRWD). The device is ready to
accept a BULK ERASE command only if all block protect bits are 0.
Table 4: Sectors 0 to 16, Protected Area Sizes – Upper Area Protection
Status Register Content
Memory Content
Unprotected Area
Top/Bottom Bit
BP2
0
BP1
0
BP0
0
Protected Area
None
0
0
0
0
0
0
0
0
All sectors 1
0
0
1
Upper 16th (sector 15)
Upper 8th (sectors 14 to 15)
Upper 4th (sectors 12 to 15)
Upper half (sectors 8 to 15)
All sectors
Lower 15/16ths (sectors 0 to 14)
Lower 7/8ths (sectors 0 to 13 )
Lower 3/4ths (sectors 0 to 11)
Lower half (sectors 0 to 7)
None
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
All sectors
None
1
1
1
All sectors
None
1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0.
Note:
Table 5: Sectors 0 to 16, Protected Area Sizes – Lower Area Protection
Status Register Content
Memory Content
Top/Bottom Bit
BP2
0
BP1
0
BP0
0
Protected Area
None
Unprotected Area
All sectors 1
1
1
1
1
1
1
1
0
0
1
Lower 16th (sector 0)
Lower 8th (sectors 0 to 1)
Lower 4th (sectors 0 to 3)
Lower half (sectors 3 to 7)
All sectors
Upper 15/16ths (sectors 1 to 15)
Upper 7/8ths (sectors 2 to 15 )
Upper 3/4ths (sectors 4 to 15)
Upper half (sectors 8 to 15)
None
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
All sectors
None
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M25PX80 Serial Flash Embedded Memory
Operating Features
Table 5: Sectors 0 to 16, Protected Area Sizes – Lower Area Protection (Continued)
Status Register Content
Memory Content
Unprotected Area
None
Top/Bottom Bit
BP2
BP1
BP0
Protected Area
1
1
1
1
All sectors
1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0.
Note:
Hold Condition
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
To enter the hold condition, the device must be selected, with S# LOW. The hold condi-
tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C)
being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co-
incides with C being LOW. If the falling edge does not coincide with C being LOW, the
hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin-
cide with C being LOW, the hold condition ends after C next goes LOW.
During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don’t Care.
Typically, the device remains selected with S# driven LOW for the duration of the hold
condition. This ensures that the state of the internal logic remains unchanged from the
moment of entering the hold condition. If S# goes HIGH while the device is in the hold
condition, the internal logic of the device is reset. To restart communication with the
device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents
the device from going back to the hold condition.
Figure 5: Hold Condition Activation
C
HOLD#
HOLD condition (standard use)
HOLD condition (nonstandard use)
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M25PX80 Serial Flash Embedded Memory
Memory Configuration and Block Diagram
Memory Configuration and Block Diagram
Each page of memory can be individually programmed; bits are programmed from 1 to
0. The device is subsector, sector, or bulk-erasable, but not page-erasable; bits are
erased from 0 to 1.. The memory is configured as follows:
• 1,048,576 bytes (8 bits each)
• 256 subsectors (4KB each)
• 16 sectors (64KB each)
• 4,096 pages (256 bytes each)
• 64 OTP bytes located outside the main memory array
Figure 6: Block Diagram
HOLD#
High Voltage
Generator
V
Control Logic
PP
64 OTP bytes
S#
C
DQ0
DQ1
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
0FFFFFh
00000h
000FFh
256 bytes (page size)
X Decoder
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M25PX80 Serial Flash Embedded Memory
Memory Map – 8Mb Density
Memory Map – 8Mb Density
Table 6: Sectors 15:0
Address Range
Sector
Subsector
Start
End
15
255
254
253
⋮
000F F000
000F E000
000F D000
⋮
000F FFFF
000F EFFF
000F DFFF
⋮
242
241
240
239
238
237
⋮
000F 2000
000F 1000
000F 0000
000E F000
000E E000
000E D000
⋮
000F 2FFF
000F 1FFF
000F 0FFF
000E FFFF
000E EFFF
000E DFFF
⋮
14
226
225
224
⋮
000E 2000
000E 1000
000E 0000
⋮
000E 2FFF
000E 1FFF
000E 0FFF
⋮
⋮
1
31
30
29
⋮
0001 F000
0001 E000
0001 D000
⋮
0001 FFFF
0001 EFFF
0001 DFFF
⋮
18
17
16
15
14
13
⋮
0001 2000
0001 1000
0001 0000
0000 F000
0000 E000
0000 D000
⋮
0001 2FFF
0001 1FFF
0001 0FFF
0000 FFFF
0000 EFFF
0000 DFFF
⋮
0
2
0000 2000
0000 1000
0000 0000
0000 2FFF
0000 1FFF
0000 0FFF
1
0
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M25PX80 Serial Flash Embedded Memory
Command Set Overview
Command Set Overview
All commands, addresses, and data are shifted in and out of the device, most significant
bit first.
Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C)
after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted
in to the device, most significant bit first, on DQ0 and DQ1, each bit being latched on
the rising edges of C.
Every command sequence starts with a one-byte command code. Depending on the
command, this command code might be followed by address or data bytes, by address
and data bytes, or by neither address or data bytes. For the following commands, the
shifted-in command sequence is followed by a data-out sequence. S# can be driven
HIGH after any bit of the data-out sequence is being shifted out.
• READ DATA BYTES (READ)
• READ DATA BYTES at HIGHER SPEED
• DUAL OUTPUT FAST READ
• READ OTP
• READ LOCK REGISTERS
• READ STATUS REGISTER
• READ IDENTIFICATION
• RELEASE from DEEP POWER-DOWN
For the following commands, S# must be driven HIGH exactly at a byte boundary. That
is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must
be driven HIGH. Otherwise, the command is rejected and not executed.
• PAGE PROGRAM
• PROGRAM OTP
• DUAL INPUT FAST PROGRAM
• SUBSECTOR ERASE
• SECTOR ERASE
• BULK ERASE
• WRITE STATUS REGISTER
• WRITE to LOCK REGISTER
• WRITE ENABLE
• WRITE DISABLE
• DEEP POWER-DOWN
All attempts to access the memory array are ignored during a WRITE STATUS REGISTER
command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addi-
tion, the internal cycle for each of these commands continues unaffected.
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M25PX80 Serial Flash Embedded Memory
Command Set Overview
Table 7: Command Set Codes
Bytes
One-Byte
Command Code
0000
Command Name
Address
Dummy
Data
WRITE ENABLE
06h
04h
9Fh
9Eh
05h
01h
E5h
E8h
03h
0Bh
3Bh
4Bh
42h
02h
A2h
20h
D8h
C7h
B9h
ABh
0
0
0
0110
WRITE DISABLE
0000
0100
0
0
0
0
0
1 to 20
1 to 20
1 to ∞
1
READ IDENTIFICATION
1001
1111
1001
1110
READ STATUS REGISTER
0000
0101
0
0
3
3
3
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
WRITE STATUS REGISTER
WRITE to LOCK REGISTER
READ LOCK REGISTER
0000
0001
1110
0101
1
1110
1000
1
READ DATA BYTES
0000
0011
1 to ∞
1 to ∞
1 to ∞
1 to 65
1 to 65
1 to 256
1 to 256
0
READ DATA BYTES at HIGHER SPEED
DUAL OUTPUT FAST READ
READ OTP (Read 64 bytes of OTP area)
0000
1011
0011
1011
0100
1011
PROGRAM OTP (Program 64 bytes of OTP
area)
0100
0010
PAGE PROGRAM
0000
0010
DUAL INPUT FAST PROGRAM
SUBSECTOR ERASE
1010
0010
0010
0000
SECTOR ERASE
1101
1000
0
BULK ERASE
1100
0111
0
DEEP POWER-DOWN
RELEASE from DEEP POWER-DOWN
1011
1001
0
1010
1011
0
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M25PX80 Serial Flash Embedded Memory
WRITE ENABLE
WRITE ENABLE
The WRITE ENABLE command sets the write enable latch (WEL) bit.
The WEL bit must be set before execution of every PROGRAM, ERASE, and WRITE com-
mand.
The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the
command code, and then driving S# HIGH.
Figure 7: WRITE ENABLE Command Sequence
0
1
2
3
4
5
6
7
C
S#
Command bits
LSB
DQ[0]
DQ1
0
0
0
0
0
1
1
0
MSB
High-Z
Don’t Care
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M25PX80 Serial Flash Embedded Memory
WRITE DISABLE
WRITE DISABLE
The WRITE DISABLE command resets the write enable latch (WEL) bit.
The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the
command code, and then driving S# HIGH.
The WEL bit is reset under the following conditions:
• Power-up
• Completion of any ERASE operation
• Completion of any PROGRAM operation
• Completion of any WRITE REGISTER operation
• Completion of WRITE DISABLE operation
Figure 8: WRITE DISABLE Command Sequence
0
1
2
3
4
5
6
7
C
S#
Command bits
LSB
DQ[0]
DQ1
0
0
0
0
0
1
0
0
MSB
High-Z
Don’t Care
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M25PX80 Serial Flash Embedded Memory
READ ID
READ ID
The READ IDENTIFICATION command reads the following device identification data:
• Manufacturer identification (1 byte): This is assigned by JEDEC.
• Device identification (2 bytes): This is assigned by device manufacturer; the first byte
indicates memory type and the second byte indicates device memory capacity.
• A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte
contains length of data to follow; the remaining 16 bytes contain optional Customized
Factory Data (CFD) content.
Table 8: READ ID :Data Out Sequence
Device ID
Memory Capacity
14h
UID
Manufacturer ID
Memory Type
CFD Length
CFD Content
20h
71h
10h
16 bytes
1. The CFD bytes are read-only and can be programmed with customer data upon demand.
If customers do not make requests, the devices are shipped with all the CFD bytes pro-
grammed to zero.
Note:
A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cy-
cle is in progress and has no effect on a cycle in progress. The READ IDENTIFICATION
command must not be issued while the device is in DEEP POWER-DOWN mode. The
device is first selected by driving S# LOW. Then the 8-bit command code is shifted in
and content is shifted out on DQ1 as follows: the 24-bit device identification that is stor-
ed in the memory, the 8-bit CFD length, followed by 16 bytes of CFD content. Each bit is
shifted out during the falling edge of serial clock (C). The READ IDENTIFICATION com-
mand is terminated by driving S# HIGH at any time during data output. When S# is
driven HIGH, the device is put in the STANDBY POWER mode and waits to be selected
so that it can receive, decode, and execute commands.
Figure 9: READ ID: Command Sequence
0
7
8
15
16
31
32
C
LSB
DQ0
Command
High-Z
MSB
LSB
LSB
LSB
DOUT
MSB
DOUT
DOUT
MSB
DOUT
DOUT
MSB
DOUT
DQ1
Manufacturer
identification
Device
identification
UID
Don’t Care
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M25PX80 Serial Flash Embedded Memory
READ STATUS REGISTER
READ STATUS REGISTER
The READ STATUS REGISTER command allows the status register to be read. The status
register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS
REGISTER cycle is in progress. When one of these cycles is in progress, it is recommen-
ded to check the write in progress (WIP) bit before sending a new command to the de-
vice. It is also possible to read the status register continuously.
Figure 10: READ STATUS REGISTER Command Sequence
0
7
8
9
10
11
12
13
14
15
C
DQ0
DQ1
LSB
Command
High-Z
MSB
LSB
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Don’t Care
Figure 11: STATUS REGISTER Format
b7
b0
BP2
BP1
BP0
WEL
WIP
0
TB
SRWD
Status register write protect
Top/bottom bit
Block protect bits
Write enable latch bit
Write in progress bit
WIP Bit
WEL Bit
The write in progress (WIP) bit indicates whether the memory is busy with a WRITE
STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set
to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress.
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is
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M25PX80 Serial Flash Embedded Memory
READ STATUS REGISTER
set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO-
GRAM, or ERASE command is accepted.
Block Protect Bits
The block protect bits are non-volatile. They define the size of the area to be software
protected against PROGRAM and ERASE commands. The block protect bits are written
with the WRITE STATUS REGISTER command.
When one or more of the block protect bits is set to 1, the relevant memory area, as de-
fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and
SECTOR ERASE commands. The block protect bits can be written provided that the
HARDWARE PROTECTED mode has not been set. The BULK ERASE command is execu-
ted only if all block protect bits are 0.
Top/Bottom Bit
The top/bottom (TB) bit is non-volatile. It can be set and reset with the WRITE STATUS
REGISTER command provided that the WRITE ENABLE command has been issued. The
TB bit is used in conjunction with the block protect bits to determine if the protected
area defined by the block protect bits starts from the top or the bottom of the memory
array:
• When TB is reset to 0 (default value), the area protected by the block protect bits starts
from the top of the memory array.
• When TB is set to 1, the area protected by the block protect bits starts from the bot-
tom of the memory array.
The TB bit cannot be written when the status register write disable (SRWD) bit is set to 1
and the W# pin is driven LOW.
SRWD Bit
The status register write disable (SRWD) bit is operated in conjunction with the write
protect (W#/VPP) signal. When the SRWD bit is set to 1 and W#/VPP is driven LOW, the
device is put in the hardware protected mode. In the hardware protected mode, the
non-volatile bits of the status register (SRWD, and the block protect bits) become re-
adonly bits and the WRITE STATUS REGISTER command is no longer accepted for exe-
cution.
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M25PX80 Serial Flash Embedded Memory
WRITE STATUS REGISTER
WRITE STATUS REGISTER
The WRITE STATUS REGISTER command allows new values to be written to the status
register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN-
ABLE command must have been executed previously. After the WRITE ENABLE com-
mand has been decoded and executed, the device sets the write enable latch (WEL) bit.
The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,
followed by the command code and the data byte on serial data input (DQ0). The
WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the sta-
tus register. The status register b6 is b5, and b4 are always read as ‘0’. S# must be driven
HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS
REGISTER command is not executed.
Figure 12: WRITE STATUS REGISTER Command Sequence
0
7
8
9
10
11
12
13
14
15
C
LSB
LSB
D
D
D
D
D
D
D
D
D
IN
DQ0
Command
IN
IN
IN
IN
IN
IN
IN
IN
MSB
MSB
As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-
ated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the sta-
tus register may still be read to check the value of the write in progress (WIP) bit. The
WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the
cycle is completed. Also, when the cycle is completed, the WEL bit is reset.
The WRITE STATUS REGISTER command allows the user to change the values of the
block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area
that is to be treated as read-only, as defined in the Protected Area Sizes table.
The WRITE STATUS REGISTER command also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the write protect (W#/VPP) signal.
The SRWD bit and the W#/VPP signal allow the device to be put in the HARDWARE PRO-
TECED (HPM) mode. The WRITE STATUS REGISTER command is not executed once
the HPM is entered. The options for enabling the status register protection modes are
summarized here.
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M25PX80 Serial Flash Embedded Memory
WRITE STATUS REGISTER
Table 9: Status Register Protection Modes
Memory Content
W#/VPP
Signal
SRWD
Bit
Protection
Mode (PM)
Status Register
Write Protection
Protected
Area
Unprotected
Area
Notes
1, 2, 3
1
0
1
0
0
0
1
1
SOFTWARE
PROTECTED mode
(SPM)
Software protection
Commands not
accepted
Commands
accepted
HARDWARE
PROTECTED mode
(HPM)
Hardware protection
Commands not
accepted
Commands
accepted
3, 4, 5,
1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can
be changed) if the WRITE ENABLE command has set the WEL bit.
Notes:
2. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.
3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.
4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values
cannot be changed).
5. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.
When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to
write to the status register provided that the WEL bit has been set previously by a WRITE
ENABLE command, regardless of whether the W#/VPP signal is driven HIGH or LOW.
When the status register SRWD bit is set to 1, two cases need to be considered depend-
ing on the state of the W#/VPP signal:
• If the W#/VPP signal is driven HIGH, it is possible to write to the status register provi-
ded that the WEL bit has been set previously by a WRITE ENABLE command.
• If the W#/VPP signal is driven LOW, it is not possible to write to the status register even
if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-
tempts to write to the status register are rejected, and are not accepted for execution.
The result is that all the data bytes in the memory area that have been put in SPM by
the status register block protect bits (BP2, BP1, BP0) are also hardware protected
against data modification.
Regardless of the order of the two events, the HPM can be entered in either of the fol-
lowing ways:
• Setting the status register SRWD bit after driving the W#/VPP signal LOW
• Driving the W#/VPP signal LOW after setting the status register SRWD bit.
The only way to exit the HPM is to pull the W#/VPP signal HIGH. If the W#/VPP signal is
permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is
available, using the status register block protect bits (BP2, BP1, BP0).
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M25PX80 Serial Flash Embedded Memory
READ DATA BYTES
READ DATA BYTES
The device is first selected by driving chip select (S#) LOW. The command code for
READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of serial clock (C). Then the memory contents at that address is
shifted out on serial data output (DQ1), each bit being shifted out at a maximum fre-
quency fR during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES command. When the highest ad-
dress is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven
HIGH at any time during data output. Any READ DATA BYTES command issued while
an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on
the cycle that is in progress.
Figure 13: READ DATA BYTES Command Sequence
0
7
8
Cx
C
LSB
A[MIN]
DQ[0]
DQ1
Command
High-Z
MSB
A[MAX]
LSB
DOUT DOUT
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Don’t Care
1. Cx = 7 + (A[MAX] + 1).
Note:
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M25PX80 Serial Flash Embedded Memory
READ DATA BYTES at HIGHER SPEED
READ DATA BYTES at HIGHER SPEED
The device is first selected by driving chip select (S#) LOW. The command code for the
READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock
(C). Then the memory contents at that address are shifted out on serial data output
(DQ1) at a maximum frequency fC, during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES at HIGHER SPEED command.
When the highest address is reached, the address counter rolls over to 000000h, allow-
ing the read sequence to be continued indefinitely.
The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH.
S# can be driven HIGH at any time during data output. Any READ DATA BYTES at
HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in
progress is rejected without any effect on the cycle that is in progress.
Figure 14: READ DATA BYTES AT HIGHER SPEED Command Sequence
0
7
8
Cx
C
LSB
A[MIN]
DQ0
Command
MSB
A[MAX]
LSB
DOUT DOUT
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DQ1
High-Z
Dummy cycles
Don’t Care
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M25PX80 Serial Flash Embedded Memory
DUAL OUTPUT FAST READ
DUAL OUTPUT FAST READ
The DUAL OUTPUT FAST READ command is similar to the READ DATA BYTES at
HIGHER SPEED command, except that data is shifted out on two pins (DQ0 and DQ1)
instead of one. Outputting the data on two pins doubles the data transfer bandwidth
compared to the READ DATA BYTES at HIGHER SPEED command. The device is first
selected by driving chip select S# LOW. The command code for the DUAL OUTPUT
FAST READ command is followed by a 3-byte address (A23-A0) and a dummy byte, each
bit being latched-in during the rising edge of serial clock (C). Then the memory con-
tents at that address are shifted out on DQ0 and DQ1 at a maximum frequency fC, dur-
ing the falling edge of C.
Figure 15: DUAL OUTPUT FAST READ Command Sequence
0
7
8
Cx
C
LSB
A[MIN]
LSB
DOUT DOUT
DOUT
DOUT
DOUT
DQ0
Command
High-Z
MSB
A[MAX]
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DQ1
Dummy cycles
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next higher address after each byte of data is shifted out on DQ0 and DQ1.
Therefore, the entire memory can be read with a single DUAL OUTPUT FAST READ
command. When the highest address is reached, the address counter rolls over to 00
0000h so that the read sequence can be continued indefinitely.
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M25PX80 Serial Flash Embedded Memory
READ LOCK REGISTER
READ LOCK REGISTER
The device is first selected by driving chip select (S#) LOW. The command code for the
READ LOCK REGISTER command is followed by a 3-byte address (A23-A0) pointing to
any location inside the concerned sector. Each address bit is latched-in during the ris-
ing edge of serial clock (C). Then the value of the lock register is shifted out on serial
data output (DQ1), each bit being shifted out at a maximum frequency fC during the
falling edge of C.
The READ LOCK REGISTER command is terminated by driving S# HIGH at any time
during data output.
Figure 16: READ LOCK REGISTER Command Sequence
0
7
8
Cx
C
LSB
A[MIN]
DQ[0]
DQ1
Command
High-Z
MSB
A[MAX]
LSB
DOUT DOUT
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Don’t Care
1. Cx = 7 + (A[MAX] + 1).
Note:
Any READ LOCK REGISTER command issued while an ERASE, PROGRAM, or WRITE
cycle is in progress is rejected without any effect on the cycle that is in progress.
Values of b1 and b0 after power-up are defined in Power-Up/Down and Supply Line De-
coupling (page 41).
Table 10: Lock Register Out
Bit
Bit name
Value
Function
b7-b2 Reserved
b1
b0
Sector lock down
1
The write lock and lock-down bits cannot be changed. Once a value of 1 is writ-
ten to the lock-down bit, it cannot be cleared to a value of 0 except by a power-
up.
0
1
0
The write lock and lock-down bits can be changed by writing new values to
them.
Sector write lock
WRITE, PROGRAM, and ERASE operations in this sector will not be executed. The
memory contents will not be changed.
WRITE, PROGRAM, or ERASE operations in this sector are executed and will
modify the sector contents.
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M25PX80 Serial Flash Embedded Memory
READ OTP
READ OTP
The device is first selected by driving chip select (S#) LOW. The command code for the
READ OTP (one-time programmable) command is followed by a 3-byte address (A23-
A0) and a dummy byte. Each bit is latched in on the rising edge of serial clock (C). Then
the memory contents at that address are shifted out on serial data output (DQ1). Each
bit is shifted out at the maximum frequency fCmax on the falling edge of C. The address
is automatically incremented to the next higher address after each byte of data is shifted
out.
There is no rollover mechanism with the READ OTP command. This means that the
READ OTP command must be sent with a maximum of 65 bytes to read because once
the 65th byte has been read, the same 65th byte continues to be read on the DQ1 pin.
The READ OTP command is terminated by driving S# HIGH. S# can be driven HIGH at
any time during data output. Any READ OTP command issued while an ERASE, PRO-
GRAM, or WRITE cycle is in progress is rejected without having any effect on the cycle
that is in progress.
Figure 17: READ OTP Command Sequence
0
7
8
C
x
C
LSB
A[MIN]
DQ0
Command
MSB
A[MAX]
LSB
D
D
D
D
D
D
D
D
D
OUT
DQ1
High-Z
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MSB
Dummy cycles
Don’t Care
1. Cx = 7 + (A[MAX] + 1).
Note:
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M25PX80 Serial Flash Embedded Memory
PAGE PROGRAM
PAGE PROGRAM
The PAGE PROGRAM command allows bytes in the memory to be programmed, which
means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac-
cepted a WRITE ENABLE command must be executed. After the WRITE ENABLE com-
mand has been decoded, the device sets the write enable latch (WEL) bit.
The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by
the command code, three address bytes, and at least one data byte on serial data input
(DQ0).
If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page; that is, from the address whose eight least significant bits (A7-A0) are all
zero. S# must be driven LOW for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and
the last 256 data bytes are guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested addresses without any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the PAGE PROGRAM command to
program all consecutive targeted bytes in a single sequence rather than to use several
PAGE PROGRAM sequences, each containing only a few bytes.
S# must be driven HIGH after the eighth bit of the last data byte has been latched in.
Otherwise the PAGE PROGRAM command is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-
cles's duration is tPP. While the PAGE PROGRAM cycle is in progress, the status register
may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during
the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some un-
specified time before the cycle is completed, the write enable latch (WEL) bit is reset.
A PAGE PROGRAM command is not executed if it applies to a page protected by the
block protect bits BP2, BP1, and BP0.
Figure 18: PAGE PROGRAM Command Sequence
0
7
8
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
D
D
D
D
IN
DQ[0]
Command
IN
IN
IN
IN
IN
IN
IN
IN
MSB
A[MAX]
MSB
1. Cx = 7 + (A[MAX] + 1).
Note:
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M25PX80 Serial Flash Embedded Memory
DUAL INPUT FAST PROGRAM
DUAL INPUT FAST PROGRAM
The DUAL INPUT FAST PROGRAM command is similar to the PAGE PROGRAM com-
mand, except that data is entered on two pins (DQ0 and DQ1) instead of one, doubling
the data transfer bandwidth.
The DUAL INPUT FAST PROGRAM command is entered by driving Chip Select S# LOW,
followed by the command code, three address bytes, and at least one data byte on serial
data input (DQ0).
If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page is programmed from the start address of the
same page; that is, from the address whose eight least significant bits (A7-A0) are all
zero. S# must be driven LOW for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data is discarded and
the last 256 data bytes are guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested addresses without any effect on other bytes in the same page.
For optimized timings, it is recommended to use the DUAL INPUT FAST PROGRAM
command to program all consecutive targeted bytes in a single sequence than to use
several DUAL INPUT FAST PROGRAM sequences, each containing only a few bytes.
S# must be driven HIGH after the eighth bit of the last data byte has been latched in.
Otherwise the DUAL INPUT FAST PROGRAM command is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-
cle's duration is tPP. While the DUAL INPUT FAST PROGRAM cycle is in progress, the
status register may be read to check the value of the write In progress (WIP) bit. The
WIP bit is 1 during the self-timed PAGE PROGRAM cycle, and 0 when the cycle is com-
pleted. At some unspecified time before the cycle is completed, the write enable latch
(WEL) bit is reset.
A DUAL INPUT FAST PROGRAM command is not executed if it applies to a page protec-
ted by the block protect bits BP2, BP1, and BP0.
Figure 19: DUAL INPUT FAST PROGRAM Command Sequence
0
7
8
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
D
D
D
D
D
DQ0
Command
IN
IN
IN
IN
IN
MSB
A[MAX]
High-Z
DQ1
IN
IN
IN
IN
IN
MSB
1. For the M25PX16, the DUAL INPUT FAST PROGRAM command is available only in VCC
range 2.7 V - 3.6 V.
Notes:
2. Cx = 7 + (A[MAX] + 1).
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M25PX80 Serial Flash Embedded Memory
PROGRAM OTP
PROGRAM OTP
The PROGRAM OTP command allows a maximum of 64 bytes in the OTP memory area
to be programmed, which means the bits are changed from 1 to 0. Before a PROGRAM
OTP command can be accepted, a WRITE ENABLE command must have been executed
previously. After the WRITE ENABLE command has been decoded, the device sets the
write enable latch (WEL) bit.
The PROGRAM OTP command is entered by driving chip select (S#) LOW, followed by
the command opcode, three address bytes, and at least one data byte on serial data in-
put (DQ0).
S# must be driven HIGH after the eighth bit of the last data byte has been latched in.
Otherwise the PROGRAM OTP command is not executed.
There is no rollover mechanism with the PROGRAM OTP command. This means that
the PROGRAM OTP command must be sent with a maximum of 65 bytes to program.
When all 65 bytes have been latched in, any following byte will be discarded.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-
cle's duration is tPP. While the PROGRAM OTP cycle is in progress, the status register
may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during
the self-timed PROGRAM OTP cycle, and 0 when when the cycle is completed. At some
unspecified time before the cycle is complete, the WEL bit is reset.
Figure 20: PROGRAM OTP Command Sequence
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQ[0]
Command
MSB
A[MAX]
MSB
1. Cx = 7 + (A[MAX] + 1).
Note:
The OTP control byte is byte 64. Bit 0 of this OTP control byte is used to permanently
lock the OTP memory array.
• When bit 0 of the OTP control byte = 1, the 64 bytes of the OTP memory array can be
programmed.
• When bit 0 of the OTP control byte = 0, the 64 bytes of the OTP memory array are
read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to 0, it can no longer be set to 1.
Therefore, as soon as bit 0 of the control byte is set to 0, the 64 bytes of the OTP memory
array is set permanently as read-only.
Any PROGRAM OTP command issued while an ERASE, PROGRAM, or WRITE cycle is in
progress is rejected without any effect on the cycle that is in progress.
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M25PX80 Serial Flash Embedded Memory
PROGRAM OTP
Figure 21: How to Permanently Lock the OTP Bytes
64 data bytes
OTP control byte
byte byte
byte byte byte
0
1
2
63
64
X
X
X
X
X
X
X
bit 0 When bit 0 = 0
the 64 OTP bytes
become READ only
Bit 1 to bit 7 are NOT
programmable
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M25PX80 Serial Flash Embedded Memory
WRITE to LOCK REGISTER
WRITE to LOCK REGISTER
The WRITE to LOCK REGISTER instruction allows the lock register bits to be changed.
Before the WRITE to LOCK REGISTER instruction can be accepted, a WRITE ENABLE
instruction must have been executed previously. After the WRITE ENABLE instruction
has been decoded, the device sets the write enable latch (WEL) bit.
The WRITE to LOCK REGISTER instruction is entered by driving chip select (S#) LOW,
followed by the instruction code, three address bytes, and one data byte on serial data
input (DQ0). The address bytes must point to any address in the targeted sector. S#
must be driven HIGH after the eighth bit of the data byte has been latched in. Otherwise
the WRITE to LOCK REGISTER instruction is not executed.
Lock register bits are volatile, and therefore do not require time to be written. When the
WRITE to LOCK REGISTER instruction has been successfully executed, the WEL bit is
reset after a delay time of less than tSHSL minimum value.
Any WRITE to LOCK REGISTER instruction issued while an ERASE, PROGRAM, or
WRITE cycle is in progress is rejected without any effect on the cycle that is in progress.
Figure 22: WRITE to LOCK REGISTER Instruction Sequence
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQ[0]
Command
MSB
A[MAX]
MSB
1. Cx = 7 + (A[MAX] + 1).
Note:
Table 11: Lock Register In
Sector
Bit
Value
All sectors
All sectors
All sectors
b7–b2
b1
0
Sector lock-down bit value
Sector write lock bit value
b0
Note: Values of b1 and b0 after power-up are defined in Power-Up/Down and Supply
Line Decoupling (page 41). For the sector lock down and sector write lock values, see
the Lock Register Out table in READ LOCK REGISTER (page 29).
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M25PX80 Serial Flash Embedded Memory
SUBSECTOR ERASE
SUBSECTOR ERASE
The SUBSECTOR ERASE command sets to 1 (FFh) all bits inside the chosen subsector.
Before the SUBSECTOR ERASE command can be accepted, a WRITE ENABLE com-
mand must have been executed previously. After the WRITE ENABLE command has
been decoded, the device sets the write enable latch (WEL) bit.
The SUBSECTOR ERASE command is entered by driving chip select (S#) LOW, followed
by the command code, and three address bytes on serial data input (DQ0). Any address
inside the subsector is a valid address for the SUBSECTOR ERASE command. S# must
be driven LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.
Otherwise the SUBSECTOR ERASE command is not executed. As soon as S# is driven
HIGH, the self-timed SUBSECTOR ERASE cycle is initiated; the cycle's duration is tSSE
While the SUBSECTOR ERASE cycle is in progress, the status register may be read to
.
check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed
SUBSECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified
time before the cycle is complete, the WEL bit is reset.
A SUBSECTOR ERASE command issued to a sector that is hardware or software protec-
ted is not executed.
Any SUBSECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle
is in progress is rejected without any effect on the cycle that is in progress.
Figure 23: SUBSECTOR ERASE Command Sequence
0
7
8
C
x
C
LSB
A[MIN]
DQ0
Command
MSB
A[MAX]
1. Cx = 7 + (A[MAX] + 1).
Note:
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M25PX80 Serial Flash Embedded Memory
SECTOR ERASE
SECTOR ERASE
The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before
the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have
been executed previously. After the WRITE ENABLE command has been decoded, the
device sets the write enable latch (WEL) bit.
The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by
the command code, and three address bytes on serial data input (DQ0). Any address in-
side the sector is a valid address for the SECTOR ERASE command. S# must be driven
LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.
Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is tSE. While the
SECTOR ERASE cycle is in progress, the status register may be read to check the value of
the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE
cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is
completed, the WEL bit is reset.
A SECTOR ERASE command is not executed if it applies to a sector that is hardware or
software protected.
Figure 24: SECTOR ERASE Command Sequence
0
7
8
C
x
C
LSB
A[MIN]
DQ0
Command
MSB
A[MAX]
1. Cx = 7 + (A[MAX] + 1).
Note:
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M25PX80 Serial Flash Embedded Memory
BULK ERASE
BULK ERASE
The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command
can be accepted, a WRITE ENABLE command must have been executed previously. Af-
ter the WRITE ENABLE command has been decoded, the device sets the write enable
latch (WEL) bit.
The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the
command code on serial data input (DQ0). S# must be driven LOW for the entire dura-
tion of the sequence.
S# must be driven HIGH after the eighth bit of the command code has been latched in.
Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed BULK ERASE cycle is initiated; the cycle's duration is tBE. While the BULK
ERASE cycle is in progress, the status register may be read to check the value of the write
In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0
when the cycle is completed. At some unspecified time before the cycle is completed,
the WEL bit is reset.
The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are
0. The BULK ERASE command is ignored if one or more sectors are protected.
Figure 25: BULK ERASE Command Sequence
0
7
C
LSB
DQ0
MSB
Command
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M25PX80 Serial Flash Embedded Memory
DEEP POWER-DOWN
DEEP POWER-DOWN
Executing the DEEP POWER-DOWN command is the only way to put the device in the
lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWER-
DOWN command can also be used as a software protection mechanism while the de-
vice is not in active use because in the DEEP POWER-DOWN mode the device ignores
all WRITE, PROGRAM, and ERASE commands.
Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER
mode if there is no internal cycle currently in progress. Once in STANDBY POWER
mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWER-
DOWN command, subsequently reducing the standby current from ICC1 to ICC2
.
To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POW-
ER-DOWN command must be issued. Other commands must not be issued while the
device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops auto-
matically at power-down. The device always powers up in STANDBY POWER mode.
The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the
command code on serial data input (DQ0). S# must be driven LOW for the entire dura-
tion of the sequence.
S# must be driven HIGH after the eighth bit of the command code has been latched in.
Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven
HIGH, it requires a delay of tDP before the supply current is reduced to ICC2 and the
DEEP POWER-DOWN mode is entered.
Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cy-
cle is in progress is rejected without any effect on the cycle that is in progress.
Figure 26: DEEP POWER-DOWN Command Sequence
0
7
C
tDP
LSB
DQ0
Command
MSB
Standby Mode
Deep Power-Down Mode
Don’t Care
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M25PX80 Serial Flash Embedded Memory
RELEASE from DEEP POWER-DOWN
RELEASE from DEEP POWER-DOWN
Once the device has entered DEEP POWER-DOWN mode, all commands are ignored ex-
cept RELEASE from DEEP POWER-DOWN and READ ELECTRONIC SIGNATURE. Exe-
cuting either of these commands takes the device out of the DEEP POWER-DOWN
mode.
The RELEASE from DEEP POWER-DOWN command is entered by driving chip select
(S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven
LOW for the entire duration of the sequence.
The RELEASE from DEEP POWER-DOWN command is terminated by driving S# HIGH.
Sending additional clock cycles on serial clock C while S# is driven LOW causes the
command to be rejected and not executed.
After S# has been driven HIGH, followed by a delay, tRES, the device is put in the STAND-
BY mode. S# must remain HIGH at least until this period is over. The device waits to be
selected so that it can receive, decode, and execute commands.
Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PRO-
GRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in
progress.
Figure 27: RELEASE from DEEP POWER-DOWN Command Sequence
0
7
C
DQ0
DQ1
tRDP
LSB
Command
High-Z
MSB
Deep Power-Down Mode
Standby Mode
Don’t Care
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M25PX80 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Power-Up/Down and Supply Line Decoupling
At power-up and power-down, the device must not be selected; that is, chip select (S#)
must follow the voltage applied on VCC until VCC reaches the correct value:
• VCC,min at power-up, and then for a further delay of tVSL
• VSS at power-down
A safe configuration is provided in the SPI Modes section.
To avoid data corruption and inadvertent write operations during power-up, a power-
on-reset (POR) circuit is included. The logic inside the device is held reset while VCC is
less than the POR threshold voltage, VWI – all operations are disabled, and the device
does not respond to any instruction. Moreover, the device ignores the following instruc-
tions until a time delay of tPUW has elapsed after the moment that VCC rises above the
VWI threshold:
• WRITE ENABLE
• PAGE PROGRAM
• DUAL INPUT FAST PROGRAM
• PROGRAM OTP
• SUBSECTOR ERASE
• SECTOR ERASE
• BULK ERASE
• WRITE STATUS REGISTER
• WRITE to LOCK REGISTER
However, the correct operation of the device is not guaranteed if, by this time, VCC is still
below VCC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should
be sent until:
t
• PUW after VCC has passed the VWI threshold
t
• VSL after VCC has passed the VCC,min level
If the time, tVSL, has elapsed, after VCC rises above VCC,min, the device can be selected
for READ instructions even if the tPUW delay has not yet fully elapsed.
VPPH must be applied only when VCC is stable and in the VCC,min to VCC,max voltage
range.
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M25PX80 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Figure 28: Power-Up Timing
V
CC
V
CC,max
PROGRAM, ERASE, and WRITE commands are rejected by the device
Chip selection not allowed
V
CC,min
tVSL
READ access allowed
Device fully
accessible
RESET state
of the
device
V
WI
tPUW
Time
After power-up, the device is in the following state:
• Standby power mode (not the deep power-down mode)
• Write enable latch (WEL) bit is reset
• Write in progress (WIP) bit is reset
• Write lock bit = 0
• Lock down bit = 0
Normal precautions must be taken for supply line decoupling to stabilize the VCC sup-
ply. Each device in a system should have the VCC line decoupled by a suitable capacitor
close to the package pins; generally, this capacitor is of the order of 100 nF.
At power-down, when VCC drops from the operating voltage to below the POR threshold
voltage VWI, all operations are disabled and the device does not respond to any instruc-
tion.
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,
some data corruption may result.
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M25PX80 Serial Flash Embedded Memory
Maximum Ratings and Operating Conditions
Maximum Ratings and Operating Conditions
Caution: Stressing the device beyond the absolute maximum ratings may cause perma-
nent damage to the device. These are stress ratings only and operation of the device be-
yond any specification or condition in the operating sections of this datasheet is not
recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 12: Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage temperature
Min
–65
—
Max
150
Units
°C
Notes
TLEAD
VIO
Lead temperature during soldering
See note
VCC+0.6
°C
1
Input and output voltage (with respect to
ground)
–0.6
V
VCC
VPP
Supply voltage
–0.6
–0.2
4.0
V
V
V
FAST PROGRAM / ERASE voltage
10.0
2000
2
3
VESD
Electrostatic discharge voltage (Human Body
model)
–2000
1. The TLEAD signal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb as-
sembly), the Micron RoHS compliant 7191395 specification, and the European directive
on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Notes:
2. Avoid applying VPPH to the W#/VPP pin during the BULK ERASE operation.
3. The VESD signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
Table 13: Operating Conditions
Symbol
Parameter
Min
2.3
Max
3.6
3.6
9.5
85
Unit
V
VCC
Supply voltage
Supply voltage (automotive grade 6 and grade 3)
Supply voltage on VPP pin
2.7
V
VPPH
TA
8.5
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
–40
–40
°C
°C
125
Table 14: Data Retention and Endurance
Parameter
Condition
Min
Max
Unit
PROGRAM and ERASE cycles Grade 3; Autograde 6; Grade
6
100,000
–
Cycles per sector
Data Retention
at 55°C
20
–
years
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M25PX80 Serial Flash Embedded Memory
Electrical Characteristics
Electrical Characteristics
Table 15: Power Up Timing Specifications
Symbol
tVSL
tPUW
Parameter
Min
30
Max
–
Units
µs
VCC[MIN] to S# LOW
Time delay to WRITE command
Write Inhibit voltage
1
10
ms
V
VWI
1.5
2.1
1. These parameters are characterized only.
Note:
Table 16: DC Current Specifications
Device Grade 6 Device Grade 3
Symbol
ILI
Parameter
Test Condition
Min
Max
±2
Min
Max
±2
Units
Input leakage current
Output leakage current
Standby current
–
–
–
–
–
–
–
–
–
–
–
µA
µA
µA
µA
mA
ILO
–
±2
±2
ICC1
S# = VCC, VIN = VSS or VCC
S# = VCC, VIN = VSS or VCC
50
100
100
12
ICC2
Deep power-down current
Operating current (READ)
10
ICC3
C = 0.1VCC / 0.9VCC at 75MHz,
DQ1 = open
12
C = 0.1VCC / 0.9VCC at 33MHz,
DQ1 = open
–
–
–
–
–
–
–
4
–
–
–
–
–
–
–
4
mA
mA
mA
mA
mA
mA
mA
Operating current
(DUAL OUTPUT FAST READ)
C = 0.1VCC / 0.9VCC at 75MHz,
DQ1 = open
15
15
15
15
15
15
15
15
15
15
15
15
ICC4
Operating current
(PAGE PROGRAM)
S# = VCC
S# = VCC
S# = VCC
S# = VCC
S# = VCC
Operating current
(DUAL INPUT FAST PROGRAM)
ICC5
ICC6
ICC7
Operating current
(WRITE STATUS REGISTER)
Operating current
(SECTOR ERASE)
Operating current
(BULK ERASE)
Table 17: DC Voltage Specifications
Symbol Parameter
Test Conditons
Min
Max
0.3VCC
Units
VIL
VIH
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
–
–0.5
V
V
V
V
–
0.7VCC VCC+0.4
VOL
VOH
IOL = 1.6mA
IOL = –100µA
–
0.4
–
VCC–0.2
1. All specifications apply to both device grade 6 and device grade 3.
Note:
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
AC Characteristics
In the following AC specifications, output HIGH-Z is defined as the point where data
out is no longer driven; however, this is not applicable to the M25PX64 device.
Table 18: AC Measurement Conditions
Symbol
Parameter
Min
30
Max
30
Unit
pF
ns
V
CL
Load capacitance
Input rise and fall times
Input pulse voltages
–
5
0.2VCC
0.3VCC
VCC / 2
0.8VCC
0.7VCC
VCC / 2
Input timing reference voltages
Output timing reference voltages
V
V
Figure 29: AC Measurement I/O Waveform
Input levels
0.8VCC
Input and output
timing reference levels
0.7VCC
0.5VCC
0.3VCC
0.2VCC
Table 19: Capacitance
Symbol Parameter
Test condition
VOUT = 0 V
Min
Max
Unit
pF
Notes
CIN/OUT Input/output capacitance (DQ0/DQ1)
–
–
8
6
1
CIN
Input capacitance (other pins)
VIN = 0 V
pF
1. Values are sampled only, not 100% tested, at TA=25°C and a frequency of 33MHz.
Note:
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Table 20: AC Specifications (75MHz)
Symbol
fC
Alt.
fC
Parameter
Min
D.C.
D.C.
6
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
75
33
–
Unit
MHz
MHz
ns
Notes
Clock frequency for all commands (except READ)
Clock frequency for READ command
fR
–
tCH
tCLH Clock HIGH time
tCLL Clock LOW time
2
tCL
6
–
ns
2
tCLCH
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ
tCLQV
–
–
Clock rise time (peak to peak)
Clock fall time (peak to peak)
0.1
0.1
5
–
V/ns
V/ns
ns
3, 4
3, 4
–
tCSS S# active setup time (relative to C)
S# not active hold time (relative to C)
tDSU Data In setup time
–
5
–
ns
2
–
ns
tDH
–
Data In hold time
5
–
ns
S# active hold time (relative to C)
S# not active setup time (relative to C)
5
–
ns
–
5
–
ns
tCSH S# deselect time
80
–
–
ns
tDIS
tV
Output disable time
8
ns
3
Clock LOW to output valid under 30 pF
Clock LOW to output valid under 10 pF
Output hold time
–
8
ns
–
6
ns
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tWHSL
tSHWL
tVPPHSL
tHO
–
0
–
ns
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# to output LOW-Z
5
–
ns
–
5
–
ns
–
5
–
ns
–
5
–
ns
tLZ
tHZ
–
–
8
ns
3
3
5
5
6
HOLD# to output HIGH-Z
–
8
ns
WRITE PROTECT setup time
WRITE PROTECT hold time
20
100
200
–
ns
–
–
ns
–
Enhanced program supply voltage HIGH (VPPH) to S#
LOW
–
ns
tDP
tRDP
tW
–
–
–
–
S# HIGH to DEEP POWER-DOWN mode
S# HIGH to STANDBY mode
–
–
–
–
–
3
30
15
5
μs
μs
3
3
–
WRITE STATUS REGISTER cycle time
PAGE PROGRAM cycle time (256 bytes)
1.3
0.8
ms
ms
tPP
7
7, 10
7
0.9
5
tPP
–
–
PAGE PROGRAM cycle time (n bytes)
PROGRAM OTP cycle time (64 bytes)
–
–
int(n/8)
× 0.025
ms
ms
0.9
5
7, 8, 10
7
tPP
0.2
0.9
150
3
7, 10
tSSE
tSE
–
–
SUBSECTOR ERASE cycle time
SECTOR ERASE cycle time
–
–
70
ms
s
0.6
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Table 20: AC Specifications (75MHz) (Continued)
Symbol
Alt.
Parameter
Min
Typ
Max
Unit
Notes
tBE
–
BULK ERASE cycle time
–
8
80
s
1. Applies to the entire table: the AC specification values for 75MHz operations shown
here are allowed only on the VCC range 2.7V - 3.6V. Typical values are given for TA =
25°C.
Notes:
2. The tCH and tCL signal values must be greater than or equal to 1/fC.
3. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and tRDP signal values are guaranteed by charac-
terization, not 100% tested in production.
4. The tCLCH and tCHCL signals clock rise and fall time values are expressed as a slew-rate.
5. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS
REGISTER command when SRWD bit is set at 1.
6. The tVPPHSL signal value for VPPH should be kept at a valid level until the program or
erase operation has completed and its result (success or failure) is known. Avoid apply-
ing VPPH to the W/VPP pin during the BULK ERASE operation.
7. To obtain optimized timings (tPP) when programming consecutive bytes with the PAGE
PROGRAM command, use one sequence including all the bytes versus several sequences
of only a few bytes (1 is less than or equal to n is less than or equal to 256).
8. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) =
4 int(15.3) =16.
9. OE# may be delayed by up to tELQV - tGLQV after CE#’s falling edge without impact to
tELQV.
10. Specified values applicable for production parts with date-code 346 or higher (Novem-
ber 2013 and later).
Table 21: AC Specifications (50 MHz)
Symbol
fC
Alt.
fC
Parameter
Clock frequency for commands (See note)
Clock frequency for READ command
Min
D.C.
D.C.
9
Typ
–
Max
50
25
–
Unit
MHz
MHz
ns
Notes
2
fR
–
–
tCH
tCLH Clock HIGH time
tCLL Clock LOW time
–
3
tCL
9
–
–
ns
3
tCLCH
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ
tCLQV
tCLQX
tHLCH
–
–
Clock rise time (peak to peak)
Clock fall time (peak to peak)
0.1
0.1
5
–
–
V/ns
V/ns
ns
4, 5
4, 5
–
–
tCSS S# active setup time (relative to C)
S# not active hold time (relative to C)
tDSU Data in setup time
–
–
—
5
–
–
ns
2
–
–
ns
tDH
–
Data in hold time
5
–
–
ns
S# active hold time (relative to C)
S# not active setup time (relative to C)
5
–
–
ns
–
5
–
–
ns
tCSH S# deselect time
100
–
–
–
ns
tDIS
tV
Output disable time
–
8
ns
4
Clock LOW to output valid
Output hold time
–
–
8
ns
tHO
–
0
–
–
ns
HOLD# setup time (relative to C)
5
–
–
ns
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Table 21: AC Specifications (50 MHz) (Continued)
Symbol
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tWHSL
tSHWL
tDP
Alt.
–
Parameter
HOLD# hold time (relative to C)
Min
5
Typ
–
Max
Unit
ns
Notes
–
–
–
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# to output LOW-Z
5
–
ns
–
5
–
–
ns
tLZ
tHZ
–
–
–
8
ns
4
4
6
6
4
4
HOLD# to output HIGH-Z
–
–
8
ns
WRITE PROTECT setup time
WRITE PROTECT hold time
20
100
–
–
–
ns
–
–
–
ns
–
S# HIGH to DEEP POWER-DOWN mode
–
3
μs
tRES1
–
S# HIGH to STANDBY mode without electronic signature
read
–
–
30
μs
tRES2
–
S# HIGH to STANDBY mode with electronic signature
read
–
–
30
μs
4
1. Applies to the entire table: the AC specification values for 50MHz operations are al-
lowed on the VCC range 2.3V - 2.7V and 2.7V - 3.6V. Typical values are given for TA =
25°C.
Notes:
2. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,
DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,
READ/WRITE STATUS REGISTER
3. The tCH and tCL signals must be greater than or equal to 1/fC.
4. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, tRES1, and tRES2 signal values are guaranteed by
characterization, not 100% tested in production.
5. The tCLCH and tCHCLsignals clock rise and fall time values are expressed as a slew-rate.
6. The tWHSL and tSHWLsignals are only applicable as a constraint for a WRITE STATUS REGIS-
TER command when SRWD bit is set at 1.
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Figure 30: Serial Input Timing
tSHSL
S#
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
DQ0
DQ1
MSB IN
LSB IN
high impedance
Figure 31: Write Protect Setup and Hold during WRSR when SRWD=1 Timing
W#/V
PP
tSHWL
tWHSL
S#
C
DQ0
high impedance
DQ1
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Figure 32: Hold Timing
S#
tHLCH
tHHCH
tCHHL
C
tCHHH
tHLQZ
tHHQX
DQ1
DQ0
HOLD#
Figure 33: Output Timing
S#
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
DQ1
DQ0
tQLQH
tQHQL
ADDRESS
LSB IN
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M25PX80 Serial Flash Embedded Memory
AC Characteristics
Figure 34: VPPH Timing
end of command
(identified by WIP polling)
S#
C
DQ0
V
PPH
V
PP
tVPPHSL
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M25PX80 Serial Flash Embedded Memory
Package Information
Package Information
Figure 35: VFQFPN8 (MLP8) 6mm x 5mm
0.15 C A
6 TYP
A
0.10 MAX/
0 MIN
B
5.75 TYP
Pin one
indicator
4.75 TYP
5 TYP
+0.30
-0.20
1.27
TYP
4
2x
0.10 C B
+0.08
-0.05
0.40
3.40 ±0.20
0.10 C A
+0.15
-0.10
0.60
θ
12°
0.05
+0.15
-0.05
0.20 TYP
0.85
0.65 TYP
C
0 MIN/
0.05 MAX
1. Drawing is not to scale.
Note:
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M25PX80 Serial Flash Embedded Memory
Package Information
Figure 36: SO8W 208 mils Body Width
1.70 MIN/
1.91 MAX
1.78 MIN/
2.16 MAX
0.15 MIN/
0.25 MAX
0.36 MIN/
0.48 MAX
0.10 MAX
1.27 TYP
5.08 MIN/
5.49 MAX
7.70 MIN/
8.10 MAX
8
1
5.08 MIN/
5.49 MAX
0.05 MIN/
0.25 MAX
0º MIN/
0.50 MIN/
0.80 MAX
10° MAX
1. Drawing is not to scale.
Note:
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M25PX80 Serial Flash Embedded Memory
Package Information
Figure 37: SO8N 150 mils Body Width
0.25 MIN/
x 45°
0.50 MAX
1.75 MAX/
1.25 MIN
0.17 MIN/
0.23 MAX
0.10 MAX
0.28 MIN/
0.48 MAX
1.27 TYP
0.25mm
Gauge plane
4.90 ±0.10
0o MIN/
8o MAX
8
1
6.00 ±0.20
3.90 ±0.10
0.10 MIN/
0.25 MAX
0.40 MIN/
1.27 MAX
1.04 TYP
1. Drawing is not to scale.
Note:
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M25PX80 Serial Flash Embedded Memory
Device Ordering Information
Device Ordering Information
Micron Serial NOR Flash devices are available in different configurations and densities.
Valid part numbers are at Micron’s part catalog (www.micron.com), and feature and
specification comparisons are at www.micron.com/products. Contact your sales repre-
sentative for devices not found. For more information on how to identify products and
top-side marking by the process identification letter, refer to technical note TN-12-24,
Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product
Families.
Table 22: Part Number Information Scheme
Part Number
Category
Category Details
M25PX = Serial Flash memory, 4KB and 64KB erasable sectors, dual I/O
80 = 8Mb (1Mb x 8-bit)
Notes
Device type
Density
Security features
– = No extra security
1
SO = OTP configurable
ST = OTP configurable plus protection at power-up
S = CFD programmed with UID
Operating voltage
Package
V = VCC = 2.3V to 3.6V (automotive parts available only in 2.7V to 3.6V)
MP = VFQFPN 6mm x 5mm (MLP8)
MW = SO8W (208 mils width)
MN = SO8N (150 mils width)
Grade
6 = Industrial temperature range: –40°C to 85°C. Device tested with standard test flow
(option A is not selected).
Device tested with high reliability certified test flow, if automotive grade option A is se-
lected.
3 = Automotive temperature range: –40°C to 125°C. Device tested with high reliability
certified test flow.
2
2
Plating technology
Lithography
P or G = RoHS compliant (G is not available for automotive commercial product)
B = 110nm, Fab 2 diffusion plant (Automotive only)
Blank = 110nm
Automotive grade
A = Automotive –40°C to 85°C (device grade 6). Device tested with high reliability certi-
fied test flow.
Blank = Automotive –40°C to 125°C
1. Secure options available upon customer request.
Notes:
2. Micron strongly recommends the use of the Automotive Grade devices (AutoGrade 6
and Grade 3) for use in an automotive environment. The High Reliability Certified Flow
(HRCF) is described in the quality note QNEE9801.
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M25PX80 Serial Flash Embedded Memory
Revision History
Revision History
Rev. C – 1/2014
• Added tPP = 0.9ms for parts having date-code 346 or higher.
Rev. B – 3/2013
Rev. A – 11/2012
• Replaced SO8W package dimension figure
• Revised text at the beginning of Ordering Information
• Initial Micron release with rebrand
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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