MT16LD1664A [MICRON]
DRAM MODULE; DRAM模块
| 型号： | MT16LD1664A |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | DRAM MODULE |
| 文件： | 总27页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
MT8LD864A X, MT16LD1664A X,
MT32LD3264A X
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
DRAM
MODULE
FEATURES
PIN ASSIGNMENT (Fro n t Vie w )
168-Pin DIMM
• Eight-CAS# ECC pinout in a 168-pin, dual in-line
memory module (DIMM)
(H-14; 64MB)
(H-17; 128MB)
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
256MB (32 Meg x 64)
• Nonbuffered
(H-30; 256MB)
• High-performance CMOS silicon-gate process
• Single +3.3V ±±.3V poꢀer supply
• All inputs, outputs and clocks are LVTTL-
compatible
• 4,±96-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• Extended Data-Out (EDO) PAGE MODE access cycle
• Serial presence-detect (SPD)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
VSS
DQ0
DQ1
DQ2
DQ3
VDD
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
VDD
85
86
VSS
DQ32
DQ33
DQ34
DQ35
VDD
127
128
VSS
2
RFU
3
87
129 NC/RAS3#**
4
5
6
7
8
9
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
CAS6#
CAS7#
RFU
VDD
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
RFU
NC
OPTIONS
• Package
MARKING
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
NC
NC
VSS
NC
NC
VDD
WE0#
CAS0#
CAS1#
RAS0#
OE0#
VSS
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
NC
VSS
NC
NC
NC
NC
168-pin DIMM (gold)
G
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
• Timing
5±ns access
6±ns access
-5
-6
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
RFU
NC
• Access Cycle
EDO PAGE MODE
X
KEY TIMING PARAMETERS
t
t
t
t
t
t
SPEED
-5
-6
RC
RAC
PC
AA
CAC
CAS
8ns
VSS
VSS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
NC
NC
VDD
RFU
CAS4#
CAS5#
10ns
PART NUMBERS
PARTNUMBER
CONFIGURATION
8 Meg x 64
SPEED
114 NC/RAS1#** 156
MT8LD864AG-5X
MT8LD864AG-6X
MT16LD1664AG-5X
MT16LD1664AG-6X
MT32LD3264AG-5X*
MT32LD3264AG-6X*
50ns
60ns
50ns
60ns
50ns
60ns
115
116
117
118
119
120
121
122
RFU
VSS
A1
A3
A5
A7
A9
A11
157
158
159
160
161
162
163
164
8 Meg x 64
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
A0
A2
A4
A6
A8
A10
NC
NC
NC
NC
39 NC (A12) 81
NC
SDA
SCL
123 NC (A13) 165
SA0
SA1
SA2
VDD
*Contact factory for availability
40
41
42
VDD
VDD
RFU
82
83
84
124
125
126
VDD
RFU
RFU
166
167
168
NOTE: Pin symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They are
for reference only.
VDD
**256MBversiononly
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
1
Micron is a registered trademark of Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
GENERAL DESCRIPTION
The Micron® MT8LD864A X, MT16LD1664A X
and MT32LD3264A X are randomly accessed 64MB,
128MB and 256MB memories organized in a x64 con-
figuration. They are specially processed to operate
from 3V to 3.6V for loꢀ-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22/23 address bits, ꢀhich are
entered 12 bits (A±-A11) at RAS# time and 11/12 bits
(A±-A11) at CAS# time.
toggle from valid data to High-Z and back to the same
valid data. If OE# is toggled or pulsed after CAS# goes
HIGH ꢀhile RAS# remains LOW, data ꢀill transition
to and remain High-Z.
During an application, if the DQ outputs are ꢀire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time ꢀill also tristate the outputs. Inde-
pendent of OE# control, the outputs ꢀill disable after
tOFF, ꢀhich is referenced from the rising edge of RAS#
or CAS#, ꢀhichever occurs last. (Refer to the 16 Meg x
4 [MT4LC16M4H9] DRAM data sheet for additional
information on EDO functionality.)
READ and WRITE cycles are selected ꢀith the WE#
input. A logic HIGH on WE# dictates read mode, ꢀhile
a logic LOW on WE# dictates ꢀrite mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, ꢀhichever occurs last. An EARLY
WRITE occurs ꢀhen WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs ꢀhen WE# falls after CAS# ꢀas taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) ꢀill
remain High-Z regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE#
must be taken HIGH to disable the data-outputs prior
to applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted ꢀhile keeping OE# LOW,
no WRITE ꢀill occur, and the data-outputs ꢀill drive
read data from the accessed location.
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
nextcycleduringtheRAS#HIGHtime. Correctmemory
cell data is preserved by maintaining poꢀer and ex-
ecuting any RAS# cycle (READ, WRITE) or RAS# RE-
FRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (A±-A1±/A11) are
executed at least every tREF, regardless of sequence. The
CBR REFRESH cycle ꢀill invoke the internal refresh
counter for automatic RAS# addressing.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back
HIGH. EDO provides for CAS# precharge time (tCP) to
occur ꢀithout the output data going invalid. This
elimination of CAS# output control provides for pipe-
line READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) ꢀith the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data ꢀill remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE#
is pulsed ꢀhile RAS# and CAS# are LOW, data ꢀill
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-
detect (SPD). The SPD function is implemented using
a 2,±48-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tꢀeen the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
ꢀith SA(2:±), ꢀhich provide 8 unique DIMM/EEPROM
addresses.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
2
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONALBLOCKDIAGRAM
MT8LD864A X (64MB)
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
DQ0-DQ7
DQ0-DQ7
U1
DQ0-DQ7
DQ0-DQ7
WE#
OE#
WE#
U2
OE#
WE#
WE#
WE0#
OE0#
U3
U4
OE#
OE#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
RAS#
CAS#
RAS#
RAS#
CAS#
RAS#
CAS#
A0ÐA11
CAS#
A0ÐA11
A0ÐA11
A0ÐA11
12
12
12
12
A0-A11
DQ32-DQ39
DQ0-DQ7
DQ40-DQ47
DQ0-DQ7
DQ48-DQ55
DQ0-DQ7
DQ56-DQ63
DQ0-DQ7
WE2#
OE2#
WE#
WE#
WE#
WE#
U5
U6
U7
U8
OE#
OE#
OE#
OE#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
RAS#
CAS#
RAS#
CAS#
RAS#
CAS#
RAS#
CAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
12
12
12
12
SPD
A1
U1-U8 = MT4LC8M8C2
SCL
SDA
A0
A2
SA0 SA1 SA2
V
DD
U1-U8
U1-U8
V
SS
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
3
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONALBLOCKDIAGRAM
MT16LD1664A X (128MB)
DQ0-DQ3
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE0#
OE0#
WE#
WE#
U1
U2
U3
U4
U5
U6
U7
U8
OE#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
12
12
12
A0-A11
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE2#
OE2#
U9
U10
OE#
U11
OE#
U12
OE#
U13
OE#
U14
OE#
U15
OE#
U16
OE#
OE#
RAS2#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS4#
CAS5#
CAS6#
CAS7#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
12
12
12
SPD
U1-U16 = MT4LC16M4H9
SCL
SDA
A0
A1
A2
SA0 SA1 SA2
V
DD
U1-U16
U1-U16
V
SS
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
4
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONALBLOCKDIAGRAM
MT32LD3264A X (256MB)
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE0#
OE0#
WE#
WE#
WE#
U3
OE#
WE#
U4
OE#
U1
U2
U5
U6
U7
U8
OE#
OE#
OE#
OE#
OE#
OE#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
RAS#
CAS#
RAS#
CAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
12
12
12
12
12
12
12
12
A0-A11
DQ32-DQ35
DQ0-DQ3
DQ36-DQ39
DQ0-DQ3
DQ40-DQ43
DQ0-DQ3
DQ44-DQ47
DQ0-DQ3
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE#
U9
OE#
WE#
U10
OE#
WE#
U11
OE#
WE#
U12
OE#
WE2#
OE2#
U13
U14
U15
U16
OE#
OE#
OE#
OE#
RAS2#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
CAS4#
CAS5#
CAS6#
CAS7#
12
12
12
12
12
12
12
12
DQ0-DQ3
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
DQ8-DQ11
DQ0-DQ3
DQ12-DQ15
DQ0-DQ3
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE#
WE#
WE#
U19
OE#
WE#
U20
OE#
U17
U18
U21
U22
U23
U24
OE#
OE#
OE#
OE#
OE#
OE#
RAS1#
RAS#
CAS#
RAS#
CAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
12
12
12
12
12
12
12
12
DQ32-DQ35
DQ0-DQ3
DQ36-DQ39
DQ0-DQ3
DQ40-DQ43
DQ0-DQ3
DQ44-DQ47
DQ0-DQ3
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
DQ0-DQ3
WE#
WE#
U25
OE#
WE#
U26
OE#
WE#
U27
OE#
WE#
U28
OE#
U29
U30
U31
U32
OE#
OE#
OE#
OE#
RAS3#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
A0ÐA11
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
CAS#
12
12
12
12
12
12
12
12
SPD
A1
U1-U32 = MT4LC16M4H9
SCL
SDA
A0
A2
SA0 SA1 SA2
V
DD
U1-U32
U1-U32
V
SS
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
5
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30, 45, 114, 129
RAS0#-RAS3#
Input
Row-Address Strobe: RAS# is used to clock-in the
row-address bits. Two RAS# inputs allow for one x64
bank or two x32 banks.
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
WE0#, WE2#
Input
Input
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output
buffers and strobe the data inputs on WRITE cycles.
Eight CAS# inputs allow byte access control for any
memory bank configuration.
27, 48
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ31. WE2# controls
DQ32-DQ63. If WE# is LOW prior to CAS# going
LOW, the access is an EARLY WRITE cycle. If WE# is
HIGH while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
31, 44
OE0#, OE2#
Input
Input
Output Enable: OE# is the input/output control for
the DQ pins. OE0# controls DQ0-DQ31. OE2# controls
DQ32-DQ63. These signals may be driven, allowing
LATE WRITE cycles.
33-38, 117-122
A0-A11
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#.
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
DQ0-DQ63
Input/
Output
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs
to the addressed DRAM location. BYTE WRITEs may
be performed by using the corresponding CAS#
select (x64 mode only). For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
42, 62, 111, 115,
125-126, 128, 132, 146
RFU
VDD
–
Reserved for Future Use: These pins should be left
unconnected.
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
Supply
Power Supply: +3.3V 0.3V.
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
VSS
SDA
Supply
Ground.
82
Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
83
SCL
Input
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs. These pins are used
to configure the presence-detect device.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
6
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).
SPD ACKNOWLEDGE
Acknoꢀledge is a softꢀare convention used to
indicate successful data transfers. The transmitting
device, either master or slave, ꢀill release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver ꢀill pull the SDA line LOW to acknoꢀledge
that it received the eight bits of data (Figure 3).
The SPD device ꢀill alꢀays respond ꢀith an ac-
knoꢀledge after recognition of a start condition and
its slave address. If both the device and a ꢀrite opera-
tion have been selected, the SPD device ꢀill respond
ꢀith an acknoꢀledge after the receipt of each subse-
quent eight-bit ꢀord. In the read mode the SPD device
ꢀill transmit eight bits of data, release the SDA line and
monitor the line for an acknoꢀledge. If an acknoꢀl-
edge is detected and no stop condition is generated by
the master, the slave ꢀill continue to transmit data.
If an acknoꢀledge is not detected, the slave ꢀill termi-
nate further data transmissions and aꢀait the stop
condition to return to standby poꢀer mode.
SPD START CONDITION
All commands are preceded by the start condition,
ꢀhich is a HIGH-to-LOW transition of SDA ꢀhen SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and ꢀill not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, ꢀhich is a LOW-to-HIGH transition of SDA
ꢀhen SCL is HIGH. The stop condition is also used to
place the SPD device into standby poꢀer mode.
SCL
SCL
SDA
SDA
START
BIT
STOP
BIT
DATA STABLE
DATA
CHANGE
DATA STABLE
Fig u re 1
Da t a Va lid it y
Fig u re 2
De fin it io n o f St a rt a n d St o p
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Fig u re 3
Ackn o w le d g e Re sp o n se Fro m Re ce ive r
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
7
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
ENTRY (VERSION) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
HEX
80
08
02
0C
0
1
2
3
4
NUMBEROFBYTESUSEDBYMICRON
TOTALNUMBEROFSPDMEMORYBYTES
MEMORYTYPE
NUMBEROFROWADDRESSES
NUMBEROFCOLUMNADDRESSES
128
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
0
0
0
256
EDOPAGEMODE
12
11(64MB)
12(128MB,256MB)
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0B
0C
5
NUMBEROFBANKS
1(64MB,128MB)
2(256MB)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
01
02
6
7
8
9
DATAWIDTH
DATAWIDTH(continued)
VOLTAGEINTERFACE
x64
NONE
LVTTL
50ns (-5)
60ns (-6)
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
40
00
01
32
3C
t
RAS#ACCESSTIME( RAC)
t
10
CAS#ACCESSTIME( CAC)
13ns (-5)
15ns (-6)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0D
0F
11
12
13
MODULECONFIGURATIONTYPE
REFRESHRATES
DRAMWIDTH(PRIMARYDRAM)
NONPARITY
15.625µs/NORMAL
x8(64MB)
x4(128MB,256MB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
08
10
14
ERRORCHECKINGDRAMDATAWIDTH
NONE
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
1
1
0
1
1
0
0
0
1
x
0
0
0
1
0
x
x
x
–
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
x
0
1
1
0
0
x
x
x
–
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
x
1
0
1
0
0
x
x
x
–
00
00
00
2A
36
33
3F
34
40
2C
FF
01
02
03
04
xx
01
02
03
04
00
xx
xx
xx
–
15-61 RESERVED
62
63
SPDREVISION
CHECKSUMFORBYTES0-62
REV. 0
64MB-5
64MB-6
128MB-5
128MB-6
256MB-5
256MB-6
MICRON
64
MANUFACTURER’SJEDECIDCODE
65-71 MANUFACTURER’SJEDECCODE(CONT.)
72 MANUFACTURINGLOCATION
73-90 MODULEPARTNUMBER(ASCII)
91
PCBIDENTIFICATIONCODE
1
2
3
4
0
92
93
94
IDENTIFICATIONCODE(CONT.)
YEAROFMANUFACTUREINBCD
WEEKOFMANUFACTUREINBCD
95-98 MODULESERIALNUMBER
99-125 MANUFACTURESPECIFICDATA(RSVD)
NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”
2. x = Variable Data.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
8
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
ABSOLUTEMAXIMUM RATINGS*
Voltage on VDD Pin Relative to VSS ........-1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS .................................-1V to +4.6V
Operating Temperature, TA (ambient) .. ±°C to +7±°C
Storage Temperature (plastic) ........... -55°C to +125°C
Poꢀer Dissipation ................................................... 8W
DCELECTRICALCHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL SIZE
MIN
3
MAX UNITS NOTES
SUPPLY VOLTAGE
VDD
VIH
VIL
ALL
ALL
ALL
3.6
VDD + 0.3
0.8
V
V
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
2
30
30
-0.5
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD + 0.3V
(All other pins not under test = 0V)
64MB
128MB
256MB
64MB
128MB
256MB
64MB
128MB
256MB
64MB
128MB
256MB
-2
-4
-8
-16
-32
-64
-8
-16
-32
-8
2
4
8
16
32
64
8
16
32
8
CAS0#-CAS7#
A0-A11
II1
II2
II3
II4
µA
µA
µA
µA
WE0#, WE2#,
OE0#, OE2#
RAS0#-RAS3#
-16
-16
16
16
OUTPUT LEAKAGE CURRENT:
DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V
64MB
128MB
256MB
-5
-5
-10
5
5
10
DQ0-DQ63
IOZ
µA
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
VOH
VOL
ALL
2.4
–
V
V
ALL
–
0.4
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
9
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V 0.3V)
M AX
PARAMETER/CONDITION
SYMBOL SIZE
-5
-6
UNITS NOTES
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
64MB
128MB
256MB
8
16
32
8
16
32
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
mA
STANDBY CURRENT: CMOS
(RAS# = CAS# = VDD - 0.2V)
64MB
128MB
256MB
4
8
16
4
8
16
mA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: RC = RC [MIN])
64MB 1,400 1,320
128MB 2,720 2,560
256MB 2,736 2,576
mA
mA
mA
mA
3, 24
3, 24
3, 24
3, 4
t
t
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: PC = PC [MIN])
64MB 1,240 1,000
128MB 2,400 1,920
256MB 2,416 1,936
t
t
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: RC = RC [MIN])
64MB 1,400 1,320
128MB 2,720 2,560
256MB 2,736 2,576
t
t
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: RC = RC [MIN])
64MB 1,320 1,240
128MB 2,560 2,400
256MB 2,576 2,416
t
t
CAPACITANCE
M AX
PARAMETER
SYMBOL 64MB 128MB 256MB UNITS NOTES
Input Capacitance: A0-A11
CI1
CI2
CI3
CI4
CI5
CIO
46
32
32
10
6
86
60
60
18
6
168
118
60
32
6
pF
pF
pF
pF
pF
pF
2
2
2
2
2
2
Input Capacitance: WE0#, WE2#, OE0#, OE2#
Input Capacitance: RAS0#-RAS3#
Input Capacitance: CAS0#-CAS7#
Input Capacitance: SCL, SA0-SA2
Input/Output Capacitance: DQ0-DQ63, SDA
12
12
22
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
10
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
ACCHARACTERISTICS
PARAMETER
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
NOTES
t
Access time from column address
Column-addresssetuptoCAS#
prechargeduringwrites
AA
25
30
t
ACH
12
15
t
Column-addressholdtime(referencedtoRAS#)
Column-addresssetuptime
Row-addresssetuptime
Column address to WE# delay time
Access time from CAS#
Column-addressholdtime
CAS#pulsewidth
CAS#holdtime(CBRRefresh)
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS#prechargetime
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
AR
38
0
0
45
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ASC
t
ASR
t
AWD
42
49
23
14
t
CAC
13
15
t
CAH
8
8
8
0
3
8
10
10
10
0
3
10
t
CAS
10,000
10,000
t
CHR
4
t
CLZ
t
COH
t
CP
15
t
CPA
CRP
28
35
t
5
38
5
5
45
5
t
CSH
t
CSR
4
t
CWD
CWL
30
8
8
0
0
35
10
10
0
23
t
t
DH
DS
22
22
t
Data-in setup time
Outputdisable
Outputenable
OE# hold time from WE# during
READ-MODIFY-WRITEcycle
t
OD
OE
12
12
0
15
15
t
t
OEH
8
10
t
OE# HIGH hold time from CAS# HIGH
OE#HIGHpulsewidth
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OE# setup prior to RAS#
duringHIDDENREFRESHcycle
OEHC
5
5
4
0
0
10
5
5
0
0
ns
ns
ns
ns
ns
t
OEP
t
OES
t
OFF
12
50
15
60
19, 27
19
t
ORD
t
EDO-PAGE-MODEREADorWRITEcycletime
EDO-PAGE-MODEREAD-WRITEcycletime
Access time from RAS#
RAS# to column-address delay time
Row-addressholdtime
PC
20
47
25
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PRWC
t
RAC
13
17
t
RAD
9
9
12
10
60
60
104
14
0
t
RAH
t
RAS#pulsewidth
RAS
50
50
84
11
0
10,000
125,000
10,000
125,000
t
RAS#pulsewidth(EDOPAGEMODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READcommandholdtime(referencedtoCAS#)
READcommandsetuptime
RASP
t
RC
RCD
RCH
RCS
t
16
18
t
t
0
0
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
11
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V 0.3V)
ACCHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
t
Refresh period (4,096 cycles)
RAS#prechargetime
RAS# to CAS# precharge time
READcommandholdtime(referencedtoRAS#)
RAS# hold time
REF
RP
64
64
t
30
5
0
13
116
67
13
2
40
5
0
t
RPC
t
RRH
18
23
t
RSH
15
140
79
15
2
10
45
0
t
READ-WRITEcycletime
RAS# to WE# delay time
RWC
t
RWD
RWL
t
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITEcommandholdtime
WRITEcommand hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE# (CAS# HIGH)
WRITEcommandpulsewidth
WE# pulse width for output
disablewhenCAS#HIGH
t
T
50
12
50
15
t
WCH
WCR
WCS
8
38
0
t
t
t
WHZ
t
WP
5
10
5
10
t
WPZ
t
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
WRH
WRP
8
8
10
10
ns
ns
t
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
12
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
VDD
VIH
MIN
MAX
UNITS NOTES
SUPPLYVOLTAGE
3
3.6
V
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN =GNDtoVDD
OUTPUTLEAKAGECURRENT:VOUT =GNDtoVDD
VDD x 0.7 VDD + 0.5
VIL
-1
–
VDD x 0.3
V
VOL
ILI
0.4
10
10
30
V
–
µA
µA
µA
ILO
–
STANDBYCURRENT:
ISB
–
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%
POWERSUPPLYCURRENT:
ICC
–
2
mA
SCL clock frequency = 100 KHz
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-outholdtime
SDA and SCL fall time
Data-in hold time
SYMBOL
MIN
0.3
4.7
MAX
UNITS NOTES
t
AA
3.5
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
t
BUF
t
DH
300
t
F
300
100
t
HD:DAT
HD:STA
0
4
4
t
Start condition hold time
ClockHIGHperiod
t
HIGH
t
Noise suppression time constant at SCL, SDA inputs
ClockLOWperiod
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
I
t
LOW
4.7
t
R
SCL
1
100
t
t
SU:DAT
SU:STA
250
4.7
4.7
t
t
SU:STO
t
WR
10
ms
28
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
13
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
NOTES
1. All voltages referenced to VSS.
19.tOFF (MAX) defines the time at ꢀhich the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
2±.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The maximum current ratings are based ꢀith the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half ꢀhen used in the x32
mode.
22.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading and cycle
rates. Specified values are obtained ꢀith minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at ꢀhich proper operation over
the full temperature range is ensured.
6. An initial pause of 1±±µs is required after poꢀer-
up, folloꢀed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR ꢀith WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle ꢀake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 2ns for -5 and 2.5ns
for -6.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured betꢀeen VIH and VIL (or betꢀeen VIL
and VIH).
9. In addition to meeting the transition rate
specification, all input signals must transit betꢀeen
VIH and VIL (or betꢀeen VIL and VIH) in a mono-
tonic manner.
1±.If CAS# and RAS# = VIH, data output is High-Z.
11.If CAS# = VIL, data output may contain data from
the last valid READ cycle.
23.tWCS, RWD, AWD and CWD are not restrictive
t
t
t
t
operating parameters. WCS applies to EARLY
WRITE cycles. If tWCS > tWCS (MIN), the cycle is
an EARLY WRITE cycle and the data output ꢀill
remain an open circuit throughout the entire
t
t
t
cycle. RWD, AWD and CWD define READ-
MODIFY-WRITE cycles. Meeting these limits
alloꢀs for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
t
t
LATE WRITE (OE#-controlled) cycle. WCS, RWD,
tCWD and AWD are not applicable in a LATE
t
WRITE cycle.
12.Measured ꢀith a load equivalent to tꢀo TTL gates
and 1±±pF and VOL = ±.8V and VOH = 2V.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
design.
t
13.Requires that tAA and CAC are not violated.
t
t
14.Requires that AA and RAC are not violated.
15.If CAS# is LOW at the falling edge of RAS#,
output data ꢀill be maintained from the previous
cycle. To initiate a neꢀ cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for tCP.
16.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) ꢀas specified as a reference point only. If
tRCD ꢀas greater than the specified tRCD (MAX)
limit, then access time ꢀas controlled exclusively
26.Measured ꢀith the specified current load and
1±±pF.
27.tOFF on an EDO module is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
28.The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a ꢀrite
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
29.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
t
by CAC (tRAC [MIN] no longer applied). With or
t
t
t
ꢀithout the RCD (MAX) limit, AA and CAC
must alꢀays be met.
17.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) ꢀas specified as a reference point only. If
tRAD ꢀas greater than the specified RAD (MAX)
t
limit, then access time ꢀas controlled exclusively
3±. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
ꢀidth ≤ 1±ns, and the pulse ꢀidth cannot be
greater than one third of the cycle rate. VIL
undershoot: VIL (MIN) = -2V for a pulse ꢀidth ≤
1±ns, and the pulse ꢀidth cannot be greater than
one third of the cycle rate.
t
t
by AA (tRAC and CAC no longer applied). With
t
t
t
or ꢀithout the RAD (MAX) limit, AA, RAC and
tCAC must alꢀays be met.
18.Either tRCH or tRRH must be satisfied for a READ
cycle.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
14
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ CYCLE
t
RC
t
t
RAS
RP
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
RSH
RRH
t
t
CAS
t
RCD
CRP
V
V
IH
IL
t
AR
t
t
t
CAH
RAD
ASC
t
t
RAH
t
ASR
ACH
V
V
IH
IL
ROW
ROW
COLUMN
ADDR
WE#
t
t
RCS
RCH
V
V
IH
IL
t
AA
t
RAC
NOTE 1
t
t
CAC
OFF
t
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
OE
t
OD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OFF
0
0
t
t
ACH
12
38
0
15
45
0
ns
RAC
50
60
ns
t
t
AR
ns
RAD
9
9
12
10
60
104
14
0
ns
t
t
ASC
ns
RAH
ns
t
t
ASR
0
0
ns
RAS
50
84
11
0
10,000
10,000
ns
t
t
CAC
13
15
ns
RC
ns
t
t
CAH
8
8
10
10
0
ns
RCD
ns
t
t
CAS
10,000
10,000
ns
RCH
ns
t
t
CLZ
0
ns
RCS
0
0
ns
t
t
CRP
5
5
ns
RP
30
0
40
0
ns
t
t
CSH
38
0
45
0
ns
RRH
ns
t
t
OD
12
12
15
15
ns
RSH
13
15
ns
t
OE
ns
t
NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
15
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
CSH
t
RSH
t
t
t
CAS
CRP
RCD
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
RWL
t
WCR
t
t
WCH
WCS
t
WP
WE#
V
V
IH
IL
t
DS
t
DH
V
V
IOH
IOL
DQ
VALID DATA
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
12
38
0
MAX
MIN
15
45
0
MAX
UNITS
ns
SYMBOL
MIN
9
MAX
10,000
MIN
10
60
104
14
40
15
15
10
45
0
MAX
UNITS
ns
t
t
ACH
RAH
t
t
AR
ns
RAS
50
84
11
30
13
13
8
10,000
ns
t
t
ASC
ns
RC
ns
t
t
ASR
0
0
ns
RCD
ns
t
t
CAH
8
10
10
5
ns
RP
ns
t
t
CAS
8
10,000
10,000
ns
RSH
ns
t
t
CRP
5
ns
RWL
ns
t
t
CSH
38
8
45
10
10
0
ns
WCH
ns
t
t
CWL
ns
WCR
38
0
ns
t
t
DH
8
ns
WCS
ns
t
t
DS
0
ns
WP
5
5
ns
t
RAD
9
12
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
16
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
PC
RSH
CSH
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
t
t
t
ACH
t
ACH
RAD
ACH
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
WE#
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RCS
t
RCH
V
V
IH
IL
t
t
RRH
AA
t
t
AA
t
AA
CPA
t
t
CPA
t
RAC
CAC
t
t
CAC
t
CLZ
CAC
t
OFF
t
t
OEHC
COH
t
CLZ
V
V
OH
OL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OPEN
OPEN
t
t
t
OE
OE
t
OD
OD
t
OES
t
V
V
OES
IH
IL
OE#
t
OEP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
5
MAX
MIN
10
5
MAX
UNITS
ns
t
t
AA
25
30
OEHC
t
t
ACH
12
38
0
15
45
0
ns
OEP
5
ns
t
t
AR
ns
OES
4
5
ns
t
t
ASC
ns
OFF
0
12
50
0
15
60
ns
t
t
ASR
0
0
ns
PC
20
25
ns
t
t
CAC
13
15
ns
RAC
ns
t
t
CAH
8
8
0
3
8
10
10
0
ns
RAD
9
9
12
10
60
14
0
ns
t
t
CAS
10,000
10,000
ns
RAH
ns
t
t
CLZ
ns
RASP
50
11
0
125,000
125,000
ns
t
t
COH
3
ns
RCD
ns
t
t
CP
10
ns
RCH
ns
t
t
CPA
28
35
ns
RCS
0
0
ns
t
t
CRP
5
38
0
5
45
0
ns
RP
30
0
40
0
ns
t
t
CSH
ns
RRH
ns
t
t
OD
12
12
15
15
ns
RSH
13
15
ns
t
OE
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
17
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE EARLY WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
t
ACH
AR
t
t
t
ACH
RAD
ACH
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
CWL
CWL
CWL
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
t
t
t
WP
WP
WP
V
V
IH
IL
WE#
t
t
WCR
RWL
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
V
V
IOH
IOL
DQ
VALID DATA
VALID DATA
VALID DATA
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
12
38
0
MAX
MIN
15
45
0
MAX
UNITS
ns
SYMBOL
MIN
20
9
MAX
MIN
25
12
10
60
14
40
15
15
10
45
0
MAX
UNITS
ns
t
t
ACH
PC
t
t
t
t
t
t
AR
ns
RAD
RAH
RASP
RCD
ns
t
ASC
ns
9
ns
t
ASR
0
0
ns
50
11
30
13
13
8
125,000
125,000
ns
t
CAH
8
10
10
10
5
ns
ns
t
CAS
8
10,000
10,000
ns
RP
ns
t
t
CP
8
ns
RSH
ns
t
t
t
t
t
t
CRP
5
ns
RWL
WCH
WCR
WCS
ns
t
CSH
38
8
45
10
10
0
ns
ns
t
CWL
ns
38
0
ns
t
DH
8
ns
ns
t
DS
0
ns
WP
5
5
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
18
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ-WRITE CYCLE
(LATEWRITEandREAD-MODIFY-WRITEcycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
CSH
t
RSH
t
t
t
t
CAS
CRP
ASR
RCD
V
V
IH
IL
t
AR
t
t
t
t
t
CAH
RAD
RAH
ASC
RCS
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
AWD
V
V
IH
IL
WE#
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
V
IOH
IOL
VALID D
VALID D
DQ
OPEN
OPEN
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OD
0
0
t
t
ACH
12
38
0
15
45
0
ns
OE
12
15
ns
t
t
AR
ns
OEH
8
10
ns
t
t
ASC
ns
RAC
50
60
ns
t
t
ASR
0
0
ns
RAD
9
9
12
10
60
14
0
ns
t
t
AWD
42
49
ns
RAH
ns
t
t
CAC
13
15
ns
RAS
50
11
0
10,000
10,000
ns
t
t
CAH
8
8
10
10
0
ns
RCD
ns
t
t
CAS
10,000
10,000
ns
RCS
ns
t
t
CLZ
0
ns
RP
30
13
116
67
13
5
40
15
140
79
15
5
ns
t
t
CRP
5
5
ns
RSH
ns
t
t
CSH
38
30
8
45
35
10
10
0
ns
RWC
ns
t
t
CWD
ns
RWD
ns
t
t
CWL
ns
RWL
ns
t
t
DH
8
ns
WP
ns
t
DS
0
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
19
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODEREAD-WRITECYCLE
(LATEWRITEandREAD-MODIFY-WRITEcycles)
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
RSH
t
NOTE 1
CSH
PC
PRWC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
RCS
t
t
CWL
t
CWL
CWL
t
t
t
WP
WP
AWD
WP
AWD
t
t
t
AWD
t
t
t
CWD
CWD
CWD
V
V
IH
IL
WE#
t
AA
t
t
AA
AA
t
RAC
t
DH
t
DH
t
DH
t
t
CPA
CPA
t
CAC
t
t
t
DS
DS
DS
t
t
CAC
CAC
t
t
t
CLZ
CLZ
OPEN
CLZ
V
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
DQ
OPEN
D
D
D
D
D
D
t
t
t
OD
OD
OD
t
t
t
OE
t
OE
OE
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OD
0
0
t
t
AR
38
0
45
0
OE
12
15
ns
t
t
ASC
OEH
8
10
25
56
ns
t
t
ASR
0
0
PC
20
47
ns
t
t
AWD
42
49
PRWC
ns
t
t
CAC
13
15
RAC
50
60
ns
t
t
CAH
8
8
0
8
10
10
0
RAD
9
9
12
10
60
14
0
ns
t
t
CAS
10,000
10,000
RAH
ns
t
t
CLZ
RASP
50
11
0
125,000
125,000
ns
t
t
CP
10
RCD
ns
t
t
CPA
28
35
RCS
ns
t
t
CRP
5
38
30
8
5
RP
30
13
67
13
5
40
15
79
15
5
ns
t
t
CSH
45
35
10
10
0
RSH
ns
t
t
CWD
RWD
ns
t
t
CWL
RWL
ns
t
t
DH
8
WP
ns
t
DS
0
t
NOTE: 1. PC is for LATE WRITE cycles only.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
20
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(PseudoREAD-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
t
t
RAD
ACH
CAH
t
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE#
ROW
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
RCH
t
t
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
AA
t
CPA
t
RAC
t
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
COH
V
V
IOH
IOL
VALID
DATA (B)
DQ
VALID DATA
IN
OPEN
VALID DATA (A)
t
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE
12
15
t
t
ACH
12
38
0
15
45
0
PC
20
25
ns
t
t
AR
RAC
50
60
ns
t
t
ASC
RAD
9
9
12
10
60
14
0
ns
t
t
ASR
0
0
RAH
ns
t
t
CAC
13
15
RASP
50
11
0
125,000
125,000
ns
t
t
CAH
8
8
3
8
10
10
3
RCD
ns
t
t
CAS
10,000
10,000
35
RCH
ns
t
t
COH
RCS
0
0
ns
t
t
CP
10
RP
30
13
8
40
15
10
0
ns
t
t
CPA
28
RSH
ns
t
t
CRP
5
38
8
5
45
10
0
WCH
ns
t
t
CSH
WCS
0
ns
t
t
DH
WHZ
12
15
ns
t
DS
0
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
21
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(withWE#-controlleddisable)
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
CAS
t
t
CP
RCD
CRP
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
V
V
IH
IL
ROW
COLUMN
COLUMN
ADDR
WE#
t
RCS
t
t
t
RCH
WPZ
RCS
V
V
IH
IL
t
AA
t
RAC
t
CAC
t
WHZ
t
t
CLZ
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
OE
t
OD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
t
t
AA
25
30
OD
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AR
38
0
45
0
ns
OE
12
15
t
t
ASC
ns
RAC
50
60
t
t
ASR
0
0
ns
RAD
9
9
12
10
14
0
t
t
CAC
13
15
ns
RAH
t
t
CAH
8
8
10
10
0
ns
RCD
11
0
t
t
CAS
10,000
10,000
ns
RCH
t
t
CLZ
0
ns
RCS
0
0
t
t
CP
8
10
5
ns
WHZ
12
15
t
t
CRP
5
ns
WPZ
10
10
t
CSH
38
45
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
22
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
RAS#-ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
t
RPC
CRP
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
V
OH
OL
DQ
OPEN
V
V
IH
IL
WE#
CBR REFRESH CYCLE
(Addresses, OE# = DON’T CARE)
t
t
t
t
RAS
RP
RAS
NOTE 1
RP
V
V
IH
IL
RAS#
t
RPC
t
t
t
t
t
t
CHR
RPC
CP
CSR
CHR
CSR
V
V
IH
IL
CAS#
DQ
V
V
OH
OL
OPEN
t
t
t
WRP
t
WRH
WRP
WRH
V
V
IH
IL
WE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
0
MAX
UNITS
ns
SYMBOL
MIN
50
84
30
5
MAX
MIN
60
MAX
10,000
UNITS
ns
t
t
ASR
0
8
8
5
5
9
RAS
10,000
t
t
CHR
10
10
5
ns
RC
104
40
ns
t
t
CP
ns
RP
ns
t
t
CRP
ns
RPC
5
ns
t
t
CSR
5
ns
WRH
8
10
ns
t
t
RAH
10
ns
WRP
8
10
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
23
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
20
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
t
RC
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS#
CAS#
t
t
t
t
CHR
RSH
CRP
RCD
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
RAC
t
OFF
t
CAC
t
CLZ
V
V
IOH
IOL
DQ
OPEN
VALID DATA
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
t
t
t
t
t
t
t
t
t
t
AA
25
30
OFF
ORD
RAC
RAD
RAH
RAS
RC
0
0
12
0
0
15
t
AR
38
0
45
0
ns
ns
t
ASC
ns
50
60
ns
t
ASR
0
0
ns
9
12
10
ns
t
CAC
13
15
ns
9
ns
t
CAH
8
8
0
5
0
10
10
0
ns
50
84
11
30
13
10,000
60
10,000
ns
t
CHR
ns
104
14
ns
t
CLZ
ns
RCD
ns
t
CRP
5
ns
RP
40
ns
t
t
OD
12
12
0
15
15
ns
RSH
15
ns
t
OE
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
24
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD EEPROM
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
MIN
0.3
MAX
UNITS
µs
SYMBOL
MIN
4
MAX
UNITS
µs
t
t
AA
3.5
HIGH
t
t
BUF
4.7
µs
LOW
4.7
µs
t
t
DH
300
ns
R
1
µs
t
t
F
300
ns
SU:DAT
250
4.7
4.7
ns
t
t
HD:DAT
0
4
µs
SU:STA
µs
t
t
HD:STA
µs
SU:STO
µs
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
25
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
168-PIN DIMM
DF-16(64MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.200 (5.08)
MAX
.079 (2.00) R
(2X)
1.105 (28.07)
1.095 (27.81)
.700 (17.78)
.118 (3.00)
(2X)
TYP
.118 (3.00) TYP
.054 (1.37)
.046 (1.17)
.250 (6.35) TYP
1.661 (42.18)
2.625 (66.68)
.128 (3.25)
.118 (3.00)
(2X)
.118 (3.00)
TYP
.039 (1.00)R (2X)
.039 (1.00)
TYP
.050 (1.27)
TYP
PIN 84 (PIN 168 ON BACKSIDE)
PIN 1 (PIN 85 ON BACKSIDE)
4.550 (115.57)
168-PIN DIMM
DF-27(128MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.350 (8.89)
MAX
.079 (2.00) R
(2X)
1.255 (31.88)
1.245 (31.62)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.054 (1.37)
.046 (1.17)
.250 (6.35) TYP
1.661 (42.18)
.128 (3.25)
.118 (3.00)
(2X)
.118 (3.00)
TYP
.039 (1.00)R (2X)
.039 (1.00)
TYP
.050 (1.27)
TYP
2.625 (66.68)
PIN 84 (PIN 168 ON BACKSIDE)
PIN 1 (PIN 85 ON BACKSIDE)
4.550 (115.57)
MAX
MIN
NOTE: All dimensions in inches (millimeters)
or typical where noted.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
26
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
168-PIN DIMM
DF-41(256MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.350 (8.89)
MAX
2.005 (51.93)
1.995 (50.67)
.079 (2.00) R
(2X)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.054 (1.37)
.046 (1.17)
.250 (6.35) TYP
1.661 (42.18)
2.625 (66.68)
.128 (3.25)
.118 (3.00)
(2X)
.118 (3.00)
TYP
.039 (1.00)R (2X)
.039 (1.00)
TYP
.050 (1.27)
TYP
PIN 84 (PIN 168 ON BACKSIDE)
PIN 1 (PIN 85 ON BACKSIDE)
4.550 (115.57)
MAX
MIN
NOTE: All dimensions in inches (millimeters)
or typical where noted.
8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900
E-m a il: p ro d m kt g @m icro n se m i.co m , In t e rn e t : h t t p ://w w w .m icro n se m i.co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
27
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