MT16VDDF6464HG-40B_技术文档

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Fe a t u re s

DDR SDRAM SODIMM

MT16VDDF6464H – 512MB

MT16VDDF12864H – 1GB

For component data sheets, refer to Micron’s Web site: www.micron.com

Fig u re 2:

1GB 200-Pin SODIMM (MO-244)

Fe a t u re s

• 200-pin, small-outline dual in-line memory module

PCB height: 31.75mm (1.25in)

(SODIMM)

• Fast data transfer rates: PC2100, PC2700, and PC3200

• 512MB (64 Meg x 64) and 1GB (128 Meg x 64)

• VDD = VDDQ = +2.5V

(-40B: VDD = VDDQ = +2.6V)

• VDDSPD = +2.3V to +3.6V

• 2.5V I/ O (SSTL_2-compatible)

• Internal, pipelined double data rate (DDR)

2n-prefetch architecture; two data accesses per clock

cycle

• Bidirectional data strobe (DQS) transmitted/ received

with data—that is, source-synchronous data capture

• Differential clock inputs CK and CK#

• Multiple internal device banks for concurrent

operation

• Dual rank

• Programmable burst lengths (BL): 2, 4, or 8

• Auto precharge option

• Auto refresh and self refresh modes: 7.8125µs

maximum average periodic refresh interval

• Serial presence-detect (SPD) with EEPROM

• Selectable CAS latency (CL) for maximum

compatibility

Op t io n s

• Self refresh current

– Standard

– Low power

• Operating temperature

– Commercial (0°C ≤ T ≤ +70°C)

– Industrial (–40°C ≤ T ≤ +85°C)

• Package

– 200-pin DIMM (standard)

– 200-pin DIMM (Pb-free)

• Memory clock, speed, CAS latency

– 5.0ns (200 MHz), 400 MT/ s, CL = 3

– 6.0ns (167 MHz), 333 MT/ s, CL = 2.5

– 7.5ns (133 MHz), 266 MT/ s, CL = 2.5

Ma rkin g

None

L

1

None

I

A

G

Y

2

• Gold edge contacts

-40B

-335

-265

200-Pin SODIMM Fig u re s

2

Notes: 1. See Table 9 on page 10 , Table 10 on page 11,

or Table 11 on page 12 for low power values.

Fig u re 1:

512MB 200-Pin SODIMM (MO-244)

PCB height: 31.75mm (1.25in)

2. Contact Micron for product availability.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Fe a t u re s

Ta b le 1:

Ke y Tim in g Pa ra m e t e rs

In d u st ry

Da t a Ra t e (MT/s)

CL = 2.5

Sp e e d

Gra d e

^tRCD

(n s)

^tRP

(n s)

^tRC

(n s)

No m e n cla t u re

CL = 3

CL = 2

No t e s

-40B

-335

-265

PC3200

PC2700

PC2100

400

–

333

266

t

266

200

15

18

20

15

18

20

55

60

65

1

–

Notes: 1. The values of ^tRCD and RP for -335 modules show 18ns to align with industry specifications;

actual DDR SDRAM device specifications are 15ns.

Ta b le 2:

Ad d re ssin g

Pa ra m e t e r

512MB

1GB

Refresh count

Row address

8K

8K (A0–A12)

4 (BA0, BA1)

256Mb (32 Meg x 8)

1K (A0–A9)

8K (A0–A12)

Device bank address

Device configuration

Column address

4 (BA0, BA1)

512Mb (64 Meg x 8)

2K (A0–A9, A11)

2 (S0#, S1#)

Module rank address

2 (S0#, S1#)

Ta b le 3:

Pa rt Nu m b e rs a n d Tim in g Pa ra m e t e rs – 512MB

Base device: MT46V32M8,¹256Mb DDR SDRAM

Mo d u le

De n sit y

Mo d u le

Ba n d w id t h

Me m o ry Clo ck/

Clo ck Cycle s

(CL-^tRCD-^tRP)

Pa rt Nu m b e r²

Co n fig u rat io n

Data Rat e

MT16VDDF6464HG-40B__

MT16VDDF6464HY-40B__

MT16VDDF6464(L)HG-335__

MT16VDDF6464HI-335

512MB

64 Meg x 64

3.2 GB/s

2.7 GB/s

2.1 GB/s

5.0ns/400 MT/s

6.0ns/333 MT/s

7.5ns/266 MT/s

3-3-3

2.5-3-3

MT16VDDF6464HY-335__

MT16VDDF6464(L)HG-265__

MT16VDDF6464HY-265__

Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes.

Example: MT16VDDF12864HY-335F2.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Fe a t u re s

Ta b le 4:

Pa rt Nu m b e rs a n d Tim in g Pa ra m e t e rs – 1GB

Base device: MT46V64M8,¹512Mb DDR SDRAM

Mo d u le

De n sit y

Mo d u le

Ba n d w id t h

Me m o ry Clo ck/

Data Rat e

Clo ck Cycle s

(CL-^tRCD-^tRP)

Pa rt Nu m b e r²

Co n fig u rat io n

MT16VDDF12864HG-40B__

MT16VDDF12864HY-40B__

MT16VDDF12864(L)HG-335__

MT16VDDF12864HI-335__

MT16VDDF12864H(I)Y-335__

MT16VDDF12864HG-265__

MT16VDDF12864HY-265__

1GB

128 Meg x 64

3.2 GB/s

2.7 GB/s

2.1 GB/s

5.0ns/400 MT/s

6.0ns/333 MT/s

7.5ns/266 MT/s

3-3-3

2.5-3-3

Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes.

Example: MT16VDDF12864HY-335F2.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Pin Assig n m e n t s a n d De scrip t io n s

Ta b le 5:

Pin Assig n m e n t s

200-Pin SODIMM Fro n t

200-Pin SODIMM Ba ck

Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l

1

VREF

VSS

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

VSS

101

A9

VSS

A7

151 DQ42

153 DQ43

2

VREF

VSS

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

A8

VSS

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

DQ46

DQ47

VDD

3

DQ19 103

DQ24 105

4

5

DQ0

DQ1

VDD

155

157

159

161

VDD

VSS

6

DQ4

DQ5

VDD

A6

7

VDD

107

A5

8

A4

CK1#

CK1

9

DQ25 109

DQS3 111

A3

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

A2

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

DQS0

DQ2

VSS

A1

VSS

DM0

DQ6

VSS

A0

VSS

113

VDD

A10

BA0

WE#

S0#

NC

163 DQ48

165 DQ49

VDD

BA1

RAS#

CAS#

S1#

DQ52

DQ53

VDD

DQ26 115

DQ27 117

DQ30

DQ31

VDD

NC

DQ3

DQ8

VDD

167

VDD

DQ7

DQ12

VDD

NC

119

121

123

125

169 DQS6

171 DQ50

DM6

DQ54

VSS

DQ9

DQS1

VSS

NC

173

VSS

DQ13

DM1

VSS

NC

VSS

NC

VSS

175 DQ51

VSS

DQ55

DQ60

VDD

127 DQ32 177 DQ56

129 DQ33 179

131 181 DQ57

133 DQS4 183 DQS7

135 DQ34 185

137 187 DQ58

139 DQ35 189 DQ59

NC

DQ36

DQ37

VDD

DM4

DQ38

VSS

DQ10

DQ11

VDD

NC

VDD

DQ14

DQ15

VDD

NC

VDD

NC

VDD

NC

DQ61

DM7

VSS

CK0

NC

VSS

VDD

NC

CK0#

VSS

NF

VSS

DQ62

DQ63

VDD

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

DQ16

DQ17

VDD

NF

141 DQ40 191

143 193

145 DQ41 195

VDD

SDA

SCL

DQ20

DQ21

VDD

CKE0

NC

VDD

CKE1

NC

VDD

SA0

SA1

DQS2

DQ18

147 DQS5 197 VDDSPD

149 VSS 199 NC

DM2

DQ22

SA2

A12

A11

VSS

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Pin Assig n m e n t s a n d De scrip t io n s

Ta b le 6:

Sym b o l

Pin De scrip t io n s

Typ e

De script io n

A0–A12

Input

Ad d re ss in p u t s: Provide the row address for ACTIVE commands, and the column address

and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the

memory array in the respective device bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank

selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-

code during a MODE REGISTER SET command. BA0 and BA1 define which mode register

(mode register or extended mode register) is loaded during the LOAD MODE REGISTER

command.

BA0, BA1

Input

Ba n k a d d re ss: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied.

CK0, CK0#,

CK1, CK1#

Clo ck: CK, CK# are differential clock inputs. All control, command, and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output

data (DQ and DQS) is referenced to the crossings of CK and CK#.

CKE0, CKE1

S0#, S1#

SA0–SA2

SCL

Input

Input/

Clo ck e n a b le : CKE (registered HIGH) activates and CKE (registered LOW) deactivates the

internal clock, input buffers, and output drivers.

Ch ip se le ct s: S# enables (registered LOW) and disables (registered HIGH) the command

decoder.

Pre se n ce -d e t e ct a d d re ss in p u t s: These pins are used to configure the SPD EEPROM address

range on the I²C bus.

Se ria l clo ck fo r p re se n ce -d e t e ct : SCL is used to synchronize the presence-detect data

transfer to and from the module.

SDA

Se ria l p re se n ce -d e t e ct d a t a : SDA is a bidirectional pin used to transfer addresses and data

Output into and out of the presence-detect portion of the module.

WE#, CAS#,

RAS#

Input

Co m m a n d in p u t s: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

DM0–DM7

Input

In p u t d a t a m a sk: DM is an input mask signal for write data. Input data is masked when DM

is sampled HIGH, along with that input data, during a write access. DM is sampled on both

edges of DQS. Although the DM pins are input-only, the DM loading is designed to match

that of DQ and DQS pins.

DQ0–DQ63

DQS0–DQS7

Input/

Output

Da t a in p u t /o u t p u t : Data bus.

Input/

Da t a st ro b e : Output with read data. Edge-aligned with read data. Input with write data.

Output Center-aligned with write data. Used to capture data.

VDD

VDDSPD

VREF

VSS

Supply Po w e r su p p ly: +2.5V ±0.2V.

Supply Se ria l EEPROM p o sit ive p o w e r su p p ly: +2.3V to +3.6V.

Supply SSTL_2 reference voltage (VDD/2).

Supply Ground.

NC

–

No co n n e ct : These pins are not connected on the module.

NF

No fu n ct io n : These pins are connected within the module, but provide no functionality.

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Fu n ct io n a l Blo ck Dia g ra m s

Fig u re 3:

Fu n ct io n a l Blo ck Dia g ra m – 512MB

S1#

S0#

DQS0

DM0

DQS1

DM1

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ

DQ8

DQ9

DQ

DQ U14

DQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U1

DQ

U7

DQ

U16

DQ

DQS3

DQS2

DM3

DM2

DM CS# DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ

U2

U13

DQ

U3

DQ

U12

DQ

DQS5

DQS4

DM5

DM4

DM CS# DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ

U5

DQ

U4

DQ

U11

U10

DQ

DQS7

DQS6

DM6

DM7

DM CS# DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ

U8

U15

U9

DQ

U6

DQ

V

DDSPD

DD

REF

BA0, BA1: DDR SDRAM

A0–A12: DDR SDRAM

RAS#: DDR SDRAM

SPD EEPROM

BA0, BA1

A0–A12

V

DDR SDRAM

U1, U2, U3, U7

CK0

RAS#

CAS#

U12, U13, U14, U16

CK0#

V

CAS#: DDR SDRAM

CKE0

CKE1

WE#

CKE0: DDR SDRAM U1–U8

VSS

U4, U5, U6, U8

CK1

CKE1: DDR SDRAM U9–U16

WE#: DDR SDRAM

U9, U10, U11, U15

CK1#

U17

SPD EEPROM

WP A0 A1 A2

SDA

SCL

CK2

CK2#

V

^SSSA0 SA1 SA2

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Fu n ct io n a l Blo ck Dia g ra m s

Fig u re 4:

Fu n ct io n a l Blo ck Dia g ra m – 1GB

S1#

S0#

DQS0

DM0

DQS1

DM1

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ

DQ8

DQ9

DQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ

U1

U12

U5

U16

DQS3

DM3

DQS2

DM2

DM CS# DQS

DQ

DQ U15

DQ

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ

U6

U11

U2

DQ

DQS5

DM5

DQS4

DM4

DM CS# DQS

DQ

DM CS# DQS

DQ

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ

U7

DQ

U3

U10

U14

DQ

DQS7

DM7

DQS6

DM6

DM CS# DQS

DQ

DM CS# DQS

DQ

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ

U4

U9

U8

U13

BA0, BA1: DDR SDRAM

A0–A12: DDR SDRAM

RAS#: DDR SDRAM

CAS#: DDR SDRAM

BA0, BA1

DDR SDRAM

U1, U2, U3, U7

U12, U13, U14, U16

CK2

CK2#

CK0

CK0#

A0–A12

RAS#

CAS#

CKE0

CKE1

WE#

U17

SPD EEPROM

WP A0 A1 A2

DDR SDRAM

U4, U5, U6, U8

U9, U10, U11, U15

CK1

CK1#

SDA

SCL

CKE0: DDR SDRAM U1–U8

CKE1: DDR SDRAM U9–U16

WE#: DDR SDRAM

V

^SSSA0 SA1 SA2

V

DDSPD

DD

REF

SS

SPD EEPROM

DDR SDRAM

V

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Ge n e ra l De scrip t io n

The MT16VDDF6464H and MT16VDDF12864H are high-speed, CMOS, dynamic

random access 512MB and 1GB memory modules organized in a x64 configuration.

These modules use DDR SDRAM devices with four internal banks.

DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 2n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/ O pins. A single

read or write access for the DDR SDRAM module effectively consists of a single 2n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/ O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in

data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during

READs and by the memory controller during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs.

DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing

of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands are registered at every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of DQS, as well as to both

edges of CK.

Se ria l Pre se n ce -De t e ct Op e ra t io n

DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module

type and various DDR SDRAM organizations and timing parameters. The remaining 128

bytes of storage are available for use by the customer. System READ/ WRITE operations

between the master (system logic) and the slave EEPROM device occur via a standard

2

I C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],

which provide eight unique DIMM/ EEPROM addresses. Write protect (WP) is connected

to VSS, permanently disabling hardware write protect.

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Ele ct rica l Sp e cifica t io n s

Stresses greater than those listed in Table 7 may cause permanent damage to the

module. This is a stress rating only, and functional operation of the module at these or

any other conditions outside those indicated on the device data sheet is not implied.

Exposure to absolute maximum rating conditions for extended periods may adversely

affect reliability.

Ta b le 7:

Sym b o l

Ab so lu t e Ma xim u m Ra t in g s

Pa ra m e t e r

Min

Ma x

Un it s

VDD

VIN, VOUT

II

VDD supply voltage relative to VSS

–1.0

–0.5

–32

+3.6

+3.2

+32

V

Voltage on any pin relative to VSS

Input leakage current; Any input 0V ≤ VIN ≤ VDD;

Address inputs,

µA

VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA

test = 0V)

S#, CKE, CK, CK#

–16

–4

+16

+4

DM

IOZ

T_A

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are

disabled

DRAM ambient operating temperature¹

DQ, DQS

–10

+10

µA

Commercial

Industrial

0

+70

+85

°C

–40

Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available

on Micron’s Web site.

DRAM Op e ra t in g Co n d it io n s

Recommended AC operating conditions are given in the DDR component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades, as shown in Table 8.

Ta b le 8:

Mo d u le a n d Co m p o n e n t Sp e e d Gra d e s

DDR components may exceed the listed module speed grades

Mo d u le Sp e e d Gra d e

Co m p o n e n t Sp e e d Gra d e

-40B

-335

-265

-5B

-6

-75

De sig n Co n sid e ra t io n s

Sim u la t io n s

Micron memory modules are designed to optimize signal integrity through carefully

designed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system’s

memory bus to ensure adequate signal integrity of the entire memory system.

Po w e r

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to

ensure the required supply voltage is maintained.

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DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Ele ct rica l Sp e cifica t io n s

IDD Sp e cifica t io n s

Ta b le 9:

IDD Sp e cifica t io n s a n d Co n d it io n s – 512MB (Die Re viso n K)

Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the

256Mb (32 Meg x 8) component data sheet

Pa ra m e t e r/Co n d it io n

Sym b o l

-40B

-335

Un it s

Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : One device

IDD0¹

832

752

mA

t

bank; Active-precharge; ^tRC = RC (MIN); ^tCK = CK (MIN); DQ, DM,

and DQS inputs changing once per clock cycle; Address and control

inputs changing once every two clock cycles

Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : One device

IDD1¹

992

952

mA

t

bank; Active-read-precharge; BL = 4; ^tRC = RC (MIN);

t

^tCK = CK (MIN); IOUT = 0mA; Address and control inputs changing

once per clock cycle

Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks idle;

IDD2P²

IDD2F²

64

mA

t

Power-down mode; ^tCK = CK (MIN); CKE = (LOW)

Id le st a n d b y cu rre n t : CS# = HIGH; All device banks are idle;

800

t

^tCK = CK (MIN); CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank active;

IDD3P²

IDD3N²

560

960

480

880

mA

t

Power-down mode; ^tCK = CK (MIN); CKE = LOW

Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One device

t

bank active; ^tRC = RAS (MAX); ^tCK = CK (MIN); DQ, DM, and DQS

inputs changing twice per clock cycle; Address and other control

inputs changing once per clock cycle

Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst reads;

IDD4R¹

1,472

1,132

1,312

mA

One device bank active; Address and control inputs changing once

t

per clock cycle; ^tCK = CK (MIN); IOUT = 0mA

Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst writes;

IDD4W¹

One device bank active; Address and control inputs changing once

t

per clock cycle; ^tCK = CK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

t

Au t o re fre sh b u rst cu rre n t

^tREFC = RFC (MIN)

^tREFC = 7.8125µs

Standard

IDD5²

IDD5A²

IDD6^{2, 3}

IDD6A^{2, 3}

IDD7¹

2,560

96

2,560

96

mA

Se lf re fre sh cu rre n t : CKE ≤ 0.2V

64

Low power

32

Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device bank

2,352

2,192

interleaving reads (BL = 4) with auto precharge;

t

^tRC = (MIN) ^tRC allowed; ^tCK = CK (MIN); Address and control

inputs change only during active READ or WRITE commands

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are

in IDD2P (CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

3. The standard module guarantees IDD6 and the low-power module guarantees IDD6A.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Ele ct rica l Sp e cifica t io n s

Ta b le 10:

IDD Sp e cifica t io n s a n d Co n d it io n s – 512MB (All Ot h e r Die Re visio n s)

Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the

256Mb (32 Meg x 8) component data sheet

Pa ra m e t e r/Co n d it io n

Sym b o l

-40B

-335

-265

Un it s

Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : One

IDD0¹

1,112

1,032

992

mA

t

device bank; Active-precharge; ^tRC = RC (MIN); CK = CK

(MIN); DQ, DM, and DQS inputs changing once per clock

cycle; Address and control inputs changing once every two

clock cycles

Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : One

IDD1¹

1,392

1,192

mA

t

device bank; Active-read-precharge; BL = 4; ^tRC = RC (MIN);

t

^tCK = CK (MIN); IOUT = 0mA; Address and control inputs

changing once per clock cycle

Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks

IDD2P²

IDD2F²

64

mA

idle; Power-down mode; ^tCK = tCK (MIN); CKE = (LOW)

Id le st a n d b y cu rre n t : CS# = HIGH; All device banks are idle;

960

800

720

t

^tCK = CK (MIN); CKE = HIGH; Address and other control

inputs changing once per clock cycle. VIN = VREF for DQ, DQS,

and DM

Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank

IDD3P²

IDD3N²

640

480

960

480

800

mA

t

active; Power-down mode; ^tCK = CK (MIN); CKE = LOW

Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One

1,120

t

device bank active; ^tRC = RAS (MAX); ^tCK = CK (MIN); DQ,

DM, and DQS inputs changing twice per clock cycle; Address

and other control inputs changing once per clock cycle

Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst

IDD4R¹

1,632

1,592

1,432

1,232

mA

reads; One device bank active; Address and control inputs

t

changing once per clock cycle; ^tCK = CK (MIN); IOUT = 0mA

Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst

IDD4W¹

writes; One device bank active; Address and control inputs

t

changing once per clock cycle; ^tCK = CK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

t

Au t o re fre sh b u rst cu rre n t

^tREFC = RFC (MIN)

^tREFC = 7.8125µs

Standard

IDD5²

IDD5A²

IDD6^{2, 3}

IDD6A^{2, 3}

IDD7¹

4,160

96

4,080

96

3,920

96

mA

Se lf re fre sh cu rre n t : CKE ≤ 0.2V

64

Low power

32

Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device

3,792

3,312

2,952

bank interleaving READs (BL = 4) with auto precharge;

t

^tRC = (MIN) ^tRC allowed; ^tCK = CK (MIN); Address and

control inputs change only during active READ or WRITE

commands

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are

in IDD2P (CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

3. The standard module guarantees IDD6 and the low power module guarantees IDD6A.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Ele ct rica l Sp e cifica t io n s

Ta b le 11:

IDD Sp e cifica t io n s a n d Co n d it io n s – 1GB

Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the

512Mb (64 Meg x 8) component data sheet

Pa ra m e t e r/Co n d it io n

Sym b o l

-40B

-335

-265

Un it s

Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : One

IDD0¹

1,280

1,080

960

mA

t

device bank; Active-precharge; ^tRC = RC (MIN); ^tCK = CK

(MIN); DQ, DM, and DQS inputs changing once per clock

cycle; Address and control inputs changing once every two

clock cycles

Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t :

IDD1¹

1,520

1,320

1,200

mA

t

One device bank; Active-read-precharge; BL = 4; ^tRC = RC

t

(MIN); ^tCK = CK (MIN); IOUT = 0mA; Address and control

inputs changing once per clock cycle

Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device

IDD2P²

IDD2F²

80

90

mA

t

banks idle; Power-down mode; ^tCK = CK (MIN); CKE = (LOW)

Id le st a n d b y cu rre n t : CS# = HIGH; All device banks are idle;

880

720

640

t

^tCK = CK (MIN); CKE = HIGH; Address and other control

inputs changing once per clock cycle. VIN = VREF for DQ, DQS,

and DM

Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank

IDD3P²

IDD3N²

720

960

560

800

480

720

mA

t

active; Power-down mode; ^tCK = CK (MIN); CKE = LOW

Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One

t

device bank active; ^tRC = RAS (MAX); ^tCK = CK (MIN); DQ,

DM, and DQS inputs changing twice per clock cycle; Address

and other control inputs changing once per clock cycle

Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst

IDD4R¹

1,560

1,600

1,360

1,440

1,200

1,120

mA

reads; One device bank active; Address and control inputs

t

changing once per clock cycle; ^tCK = CK (MIN); IOUT = 0mA

Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst

IDD4W¹

writes; One device bank active; Address and control inputs

t

changing once per clock cycle; ^tCK = CK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

t

Au t o re fre sh b u rst cu rre n t

^tREFC = RFC (MIN)

^tREFC = 7.8125µs

Standard

IDD5²

IDD5A²

IDD6^{2, 3}

IDD6A^{2, 3}

IDD7¹

5,520

176

80

4,640

160

80

4,480

160

80

mA

Se lf re fre sh cu rre n t : CKE ≤ 0.2V

Low power

48

Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device

bank interleaving READs (BL = 4) with auto precharge;

^tRC = (MIN) ^tRC allowed; ^tCK = tCK (MIN); Address and

control inputs change only during active READ or WRITE

commands

3,640

3,280

2,840

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are

in IDD2P (CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

3. The standard module guarantees IDD6 and the low power module guarantees IDD6A.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Se ria l Pre se n ce -De t e ct

Ta b le 12:

Se ria l Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s

Pa ra m e t e r/Co n d it io n

Sym b o l

Min

Ma x

Un it s

Supply voltage

VDDSPD

VIH

VIL

2.3

3.6

V

Input high voltage: Logic 1; All inputs

Input low voltage: Logic 0; All inputs

VDDSPD × 0.7 VDDSPD + 0.5

–1.0

VDDSPD × 0.3

V

Output low voltage: IOUT = 3mA

VOL

ILI

–

0.4

10

V

Input leakage current: VIN = GND to VDD

Output leakage current: VOUT = GND to VDD

Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS

Power supply current: SCL clock frequency = 100 kHz

µA

mA

ILO

10

ISB

30

ICC

2.0

Ta b le 13:

Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s

Pa ra m e t e r/Co n d it io n

Sym b o l

Min

Ma x

Un it s

No t e s

SCL LOW to SDA data-out valid

Time the bus must be free before a new transition can start

Data-out hold time

^tAA

^tBUF

^tDH

^tF

^tR

^tHD:DAT

^tHD:STA

^tHIGH

^tI

^tLOW

^fSCL

^tSU:DAT

^tSU:STA

^tSU:STO

^tWRC

0.2

1.3

200

–

0.9

–

µs

ns

µs

ns

µs

kHz

ns

µs

ms

1

–

Clock/data fall time

300

–

2

Clock/data rise time

–

Data-in hold time

0

Start condition hold time

Clock HIGH period

0.6

–

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

50

–

1.3

–

SCL clock frequency

400

–

Data-in setup time

100

0.6

–

Start condition setup time

Stop condition setup time

WRITE cycle time

–

3

4

–

10

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and

the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (^tWRC) is the time from a valid stop condition of a write

sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE

cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-

tor, and the EEPROM does not respond to its slave address.

Se ria l Pre se n ce -De t e ct Da t a

For the latest serial presence-detect data, refer to Micron’s SPD page:

www.micron.com/ SPD.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Mo d u le Dim e n sio n s

Fig u re 5:

200-Pin SODIMM – 512MB

Front view

3.8 (0.15)

MAX

67.75 (2.667)

67.45 (2.656)

2.0 (0.079) R

(2X)

U1

U2

U3

U4

U5

U6

31.9 (1.256)

31.6 (1.244)

1.8 (0.071)

(2X)

U8

20.0 (0.787)

U7

U17

TYP

6.0 (0.236) TYP

2.44 (0.096) TYP

1.1 (0.043)

0.9 (0.035)

2.0 (0.079) TYP

0.99 (0.039)

TYP

0.46 (0.018)

TYP

0.61 (0.024)

TYP

Pin 199

Pin 1

63.6 (2.504)

TYP

Back view

U9

U10

U11

U12

U13

U14

U15

U16

Pin 200

Pin 2

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-

tional design dimensions.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

512MB, 1GB (x64, DR) 200-Pin DDR SODIMM

Mo d u le Dim e n sio n s

Fig u re 6:

200-Pin SODIMM – 1GB

Front view

67.75 (2.667)

67.45 (2.656)

3.8 (0.15)

MAX

2.0 (0.079) R

(2X)

U17

U1

U5

U2

U3

U7

U4

31.9 (1.256)

31.6 (1.244)

1.8 (0.071)

(2X)

U6

U8

20.0 (0.787)

TYP

6.0 (0.236) TYP

2.44 (0.096) TYP

1.1 (0.043)

0.9 (0.035)

2.0 (0.079) TYP

0.99 (0.039)

TYP

0.46 (0.018)

TYP

0.61 (0.024)

TYP

Pin 199

Pin 1

63.6 (2.504)

TYP

Back view

U9

U10

U14

U11

U12

U16

U13

U15

Pin 200

Pin 2

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-

tional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

PDF: 09005aef80a77a90/Source: 09005aef80a646bc

DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15


型号：	MT16VDDF6464HG-40B
厂家：	MICRON TECHNOLOGY
描述：	DDR SDRAM SODIMM 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件：	总15页 (文件大小：654K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT16VDDF6464HG-40B [MICRON]

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