MT36VDDF12872G-262 [MICRON]
DDR SDRAM RDIMM;
| 型号： | MT36VDDF12872G-262 |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | DDR SDRAM RDIMM 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fe a t u re s
DDR SDRAM RDIMM
MT36VDDF12872 – 1GB
MT36VDDF25672 – 2GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Fig u re 2:
St a n d a rd -He ig h t La yo u t – 1GB
(MO-206-CA R/C D)
Fe a t u re s
• 184-pin, registered dual in-line memory module
(RDIMM)
PCB height: 30.48mm (1.2in)
• Tall- and standard-height PCB options
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
Fig u re 3:
St a n d a rd -He ig h t La yo u t – 2GB
(MO-206-CA R/C D)
• 2.5V I/ O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
PCB height: 30.48mm (1.2in)
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Dual rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
Op t io n s
• Operating temperature
Ma rkin g
1
– Commercial (0°C ≤ T ≤ +70°C)
None
I
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
A
– Industrial (–40°C ≤ T ≤ +85°C)
A
• Package
– 184-pin DIMM (standard)
– 184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
G
Y
2
• Gold edge contacts
– 5.0ns (200 MHz), 400 MT/ s, CL = 3
– 6.0ns (166 MHz), 333 MT/ s, CL = 2.5
– 7.5ns (133 MHz), 266 MT/ s, CL = 2
– 7.5ns (133 MHz), 266 MT/ s, CL = 2
– 7.5ns (133 MHz), 266 MT/ s, CL = 2.5
-40B
-335
-262
-26A
-265
184-Pin RDIMM Fig u re s
Fig u re 1:
Ta ll-He ig h t La yo u t – 1GB, 2GB
(MO-206-EA)
Notes: 1. Contact Micron for industrial temperature
module offerings.
PCB height: 43.18mm (1.7in)
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fe a t u re s
Ta b le 1:
Ke y Tim in g Pa ra m e t e rs
In d u st ry
Da t a Ra t e (MT/s)
Sp e e d
Gra d e
t RCD
(n s)
t RP
(n s)
t RC
(n s)
No m e n cla t u re
CL = 3
CL = 2.5
CL = 2
No t e s
-40B
-335
-262
-26A
-265
PC3200
PC2700
PC2100
PC2100
PC2100
400
–
333
333
266
266
266
t
266
266
266
266
200
15
18
15
20
20
15
18
15
20
20
55
60
60
65
65
1
–
–
–
Notes: 1. The values of tRCD and RP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
Ta b le 2:
Ad d re ssin g
Pa ra m e t e r
1GB
2GB
8K
8K
Refresh count
Row address
8K (A0–A12)
8K (A0–A12)
4 (BA0, BA1)
4 (BA0, BA1)
Device bank address
Device configuration
Column address
256Mb (64 Meg x 4)
2K (A0–A9, A11)
2 (S0#, S1#)
512Mb (128 Meg x 4)
4K (A0–A9, A11, A12)
2 (S0#, S1#)
Module rank address
Ta b le 3:
Pa rt Nu m b e rs a n d Tim in g Pa ra m e t e rs – 1GB Mo d u le s
Base device: MT46V64M4,1 256Mb DDR SDRAM
Mo d u le
De n sit y
Mo d u le
Ba n d w id t h
Me m o ry Clo ck/
Clo ck Cycle s
(CL-t RCD-t RP)
Pa rt Nu m b e r2
Co n fig u ra t io n
Da t a Ra t e
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
MT36VDDF12872G-40B__
MT36VDDF12872Y-40B__
MT36VDDF12872G-335__
MT36VDDF12872Y-335__
MT36VDDF12872G-262__
MT36VDDF12872G-26A__
MT36VDDF12872Y-26A__
MT36VDDF12872G-265__
MT36VDDF12872Y-265__
3-3-3
3-3-3
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT36VDDF12872Y-335G3.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fe a t u re s
Ta b le 4:
Pa rt Nu m b e rs a n d Tim in g Pa ra m e t e rs – 2GB Mo d u le s
Base device: MT46V128M4,1 512Mb DDR SDRAM
Mo d u le
De n sit y
Mo d u le
Ba n d w id t h
Me m o ry Clo ck/
Da t a Ra t e
Clo ck Cycle s
(CL-t RCD-t RP)
Pa rt Nu m b e r2
Co n fig u ra t io n
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
MT36VDDF25672G-40B__
MT36VDDF25672Y-40B__
MT36VDDF25672G-335__
MT36VDDF25672Y-335__
MT36VDDF25672G-262__
MT36VDDF25672G-26A__
MT36VDDF25672G-265__
MT36VDDF25672Y-265__
3-3-3
3-3-3
2-2-2
2-3-3
2.5-3-3
2.5-3-3
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT36VDDF12872Y-335G3.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Pin Assig n m e n t s a n d De scrip t io n s
Pin Assig n m e n t s a n d De scrip t io n s
Ta b le 5:
Pin Assig n m e n t s
184-Pin DDR RDIMM Fro n t
184-Pin DDR RDIMM Ba ck
Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l
Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l
1
2
3
4
5
6
7
8
9
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
24
25
26
27
28
29
30
31
32
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
VSS
CB3
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDD
NC
DQ48
DQ49
VSS
93
94
95
96
97
VSS
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
116
117
118
VSS
139
VSS
162 DQ47
DQ21 140 DQS17 163
A11
NC
141
A10
CB6
VDDQ
CB7
164
VDDQ
119 DQS11 142
165 DQ52
166 DQ53
120
121
122
123
124
125
126
127
128
VDD
143
DQ22 144
A8 145
BA1
NC
NC
98
99
167
168
NC
VDD
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
VSS
VDDQ
DQS6
DQ50
DQ51
VSS
100
101
102
103
104
DQ23 146 DQ36
VSS
A6
DQ28 149 DQS13 172
DQ29
VDDQ
169 DQS15
170 DQ54
171 DQ55
147
148
DQ37
VDD
10 RESET# 33
11
12
13
14
15
16
17
18
19
20
21
22
23
VSS
DQ8
DQ9
DQS1
VDDQ
NC
34
35
36
37
38
39
40
41
42
43
44
45
46
VDDQ
NC
150
151 DQ39
DQ38
173
BA0
NC
105 DQ12
106 DQ13
107 DQS10 130
108
109 DQ14
110 DQ15
111
112
113
114 DQ20
115 A12
174 DQ60
175 DQ61
DQ35
DQ40
VDDQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
129 DQS12 152
VSS
A3
153 DQ44
176
VSS
VDD
131
132
133
134
135
136
137
138
DQ30 154
155
DQ31 156
RAS#
DQ45
VDDQ
S0#
177 DQS16
178 DQ62
179 DQ63
NC
VSS
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
VSS
A1
CB0
CB1
CKE1
VDDQ
NC
CB4
CB5
VDDQ
CK0
157
158
180
181
VDDQ
SA0
S1#
159 DQS14 182
160 183
161 DQ46 184 VDDSPD
SA1
SA2
VSS
VDD
CK0#
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
4
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Pin Assig n m e n t s a n d De scrip t io n s
Ta b le 6:
Pin De scrip t io n s
Sym b o l
Typ e
De scrip t io n
A0–A12
Input
Ad d re ss in p u t s: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
BA0, BA1
Input
Input
Ba n k a d d re ss: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
CK0, CK0#
Clo ck: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
CKE0, CKE1
Input
Input
Input
Clo ck e n a b le : CKE enables (registered HIGH) and CKE disables (registered
LOW) the internal clock, input buffers, and output drivers.
RAS#, CAS#, WE#
RESET#
Co m m a n d in p u t s: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Re se t : Asynchronously forces all registered outputs LOW when RESET# is LOW.
This signal can be used during power-up to ensure that CKE is LOW and DQ are
High-Z.
S0#, S1#
SA0–SA2
SCL
Input
Input
Input
Ch ip se le ct s: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Pre se n ce -d e t e ct a d d re ss in p u t s: These pins are used to configure the SPD
EEPROM address range on the I2C bus.
Se ria l clo ck fo r SPD EEPROM: SCL is used to synchronize the presence-detect
data transfer to and from the module.
CB0–CB7
DQ0–DQ63
DQS0–DQS17
I/O
I/O
I/O
Check bits.
Da t a in p u t /o u t p u t : Data bus.
Da t a st ro b e : Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
SDA
I/O
Se ria l d a t a : SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
VDD/VDDQ
VDDSPD
VREF
Supply
Supply
Supply
Supply
–
Po w e r su p p ly: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
SPD EEPROM p o w e r su p p ly: +2.3V to +3.6V.
SSTL_2 reference voltage (VDD/2).
VSS
Ground.
NC
No co n n e ct : These pins are not connected on the module.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fu n ct io n a l Blo ck Dia g ra m s
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 4:
Fu n ct io n a l Blo ck Dia g ra m – Ta ll-He ig h t La yo u t (1GB, 2GB)
S1#
S0#
DQS0
DQS4
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15
U32
U36
U11
DQS9
DQS13
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
U28
U7
U22
DQS1
DQS5
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U35
U16
U31
U12
DQS10
DQS14
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U21
U27
U2
U8
DQS8
DQS17
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U24
U23
U5
U6
DQS2
DQS6
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
U34
U30
U17
DQS11
DQS15
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U20
U26
U3
U9
DQS3
DQS7
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
U33
U29
U18
DQS12
DQS16
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ U19
DQ
DQS CS#
DQ
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U25
U10
U4
DQ
Rank 0 = U1–U18
Rank 1 = U19–U36
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
U39
SPD EEPROM
U37, U38
RAS#
RAS#: DDR SDRAM
CAS#: DDR SDRAM
SCL
SDA
WP A0 A1 A2
R
e
g
i
s
t
e
r
s
CAS#
CKE0
CKE1
WE#
U40
CKE0: DDR SDRAM, rank 0
CKE1: DDR SDRAM, rank 1
WE#: DDR SDRAM
VSS
SA0 SA1 SA2
CK0
CK0#
PLL
VDD
A0–A12
BA0
A0–A12: DDR SDRAM
BA0: DDR SDRAM
VDDSPD
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM x 4
Register x 2
BA1
BA1: DDR SDRAM
VDD/VDDQ
VREF
S0#
S0#: DDR SDRAM, rank 0
S1#: DDR SDRAM, rank 1
S1#
VSS
RESET#
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
6
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 5:
Fu n ct io n a l Blo ck Dia g ra m – St a n d a rd -He ig h t La yo u t (1GB)
S1#
S0#
DQS0
DQS4
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U25
U8
U1
U33
DQS9
DQS13
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U32
U2
U36
U17
DQS1
DQS5
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
U40
U9
U24
DQS10
DQS14
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U31
U3
U18
U35
DQS8
DQS17
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U7
U26
U28
U6
DQS2
DQS6
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U30
U4
U34
U20
DQS11
DQS15
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
U14
U39
DQ
DQ
DQ
DQ
DQ
DQ
U10
U23
DQS3
DQS7
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
U29
U12
U21
DQS12
DQS16
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15
U38
U11
U22
Rank 0 = U1–U6, U13–U15, U21–U26, U34–U36
Rank 1 = U7–U12, U17, U18, U20, U28–U33, U38–U40
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
U16, U37
RAS#
RAS#: DDR SDRAM
U27
PLL
R
e
g
i
s
t
e
r
s
CAS#
CKE0
CKE1
WE#
CAS#: DDR SDRAM
CK0
CK0#
CKE0: DDR SDRAM, rank 0
CKE1: DDR SDRAM, rank 1
WE#: DDR SDRAM
VDD
A0–A12
BA0
A0–A12: DDR SDRAM
BA0: DDR SDRAM
DDR SDRAM x 4
Register x 2
BA1
BA1: DDR SDRAM
S0#
S0#: DDR SDRAM, rank 0
S1#: DDR SDRAM, rank 1
S1#
VDDSPD
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
RESET#
VDD/VDDQ
VREF
U19
SPD EEPROM
WP A0 A1 A2
SCL
SDA
VSS
VSS SA0 SA1 SA2
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
7
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 6:
Fu n ct io n a l Blo ck Dia g ra m – St a n d a rd -He ig h t La yo u t (2GB)
S1#
S0#
DQS0
DQS4
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U31
U25
U1
U6
DQS9
DQS13
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U40
U11
U24
U7
DQS1
DQS5
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
U30
U34
U17
DQS10
DQS14
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U39
U12
U8
U23
DQS8
DQS17
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U35
U16
U5
U27
DQS2
DQS6
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U29
U3
U9
U22
DQS11
DQS15
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
U38
U18
U33
DQS3
DQS7
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U28
U4
U10
U21
DQS12
DQS16
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQS CS#
DQ
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
U37
DQ
DQ
DQ
U20
U32
Rank 0 = U1–U5, U11–U14, U21–U25, U32–U35
Rank 1 = U6–U10, U16–U20, U27–U31, U37–U40
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
U15, U36
RAS#
CAS#
CKE0
CKE1
WE#
RAS#: DDR SDRAM
U26
R
e
g
i
s
t
e
r
s
CAS#: DDR SDRAM
CK0
CK0#
PLL
CKE0: DDR SDRAM, rank 0
CKE1: DDR SDRAM, rank 1
WE#: DDR SDRAM
VDD
A0–A12
A0–A12: DDR SDRAM
BA0: DDR SDRAM
DDR SDRAM x 4
Register x 2
BA0
BA1
S0#
S1#
BA1: DDR SDRAM
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM
S0#: DDR SDRAM, rank 0
S1#: DDR SDRAM, rank 1
VDDSPD
VDD/VDDQ
VREF
RESET#
SCL
U19
SPD EEPROM
WP A0 A1 A2
SDA
VSS
VSS SA0 SA1 SA2
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
8
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ge n e ra l De scrip t io n
Ge n e ra l De scrip t io n
The MT36VDDF12872 and MT36VDDF25672 are high-speed, CMOS dynamic random
access 1GB and 2GB memory modules organized in a x72 configuration. These modules
use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/ O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/ O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Re g ist e r a n d PLL Op e ra t io n
These DDR SDRAM modules operate in registered mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by
one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differ-
ential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce
control, command, address, and clock signals loading by isolating DRAM from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Se ria l Pre se n ce -De t e ct Op e ra t io n
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various DDR SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/ WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
2
I C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
which provide eight unique DIMM/ EEPROM addresses. Write protect (WP) is connected
to VSS, permanently disabling hardware write protect.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
9
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ele ct rica l Sp e cifica t io n s
Ele ct rica l Sp e cifica t io n s
Stresses greater than those listed in Table 7 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Ta b le 7:
Sym b o l
Ab so lu t e Ma xim u m Ra t in g s
Pa ra m e t e r
Min
Ma x
Un it s
VDD/VDDQ
VIN, VOUT
II
–1.0
–0.5
–5
+3.6
+3.2
+5
V
V
VDD/VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
µA
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
Address inputs,
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA,
test = 0V)
S#, CKE
CK, CK#
DQ, DQS
–10
–10
+10
+10
IOZ
TA
µA
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are
disabled
DRAM ambient operating temperature1
Commercial
Industrial
0
+70
+85
°C
°C
–40
Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
10
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ele ct rica l Sp e cifica t io n s
DRAM Op e ra t in g Co n d it io n s
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in table 8.
Ta b le 8:
Mo d u le a n d Co m p o n e n t Sp e e d Gra d e s
DDR components may exceed the listed module speed grades
Mo d u le Sp e e d Gra d e
Co m p o n e n t Sp e e d Gra d e
-40B
-335
-262
-26A
-265
-5B
-6
-75E
-75Z
-75
De sig n Co n sid e ra t io n s
Sim u la t io n s
Micron memory modules are designed to optimize signal integrity through carefully
designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system’s
memory bus to ensure adequate signal integrity of the entire memory system.
Po w e r
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to
ensure the required supply voltage is maintained.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ele ct rica l Sp e cifica t io n s
IDD Sp e cifica t io n s
Ta b le 9:
IDD Sp e cifica t io n s a n d Co n d it io n s – 1GB (Die Re visio n K)
Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
Pa ra m e t e r/Co n d it io n
Sym b o l -40B
-335
Un it s
IDD01
1,872 1,692
mA
t
t
Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : tRC = RC (MIN); tCK = CK (MIN);
DQ and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
IDD11
IDD2P2
IDD2F2
2,232 2,142
mA
mA
mA
t
Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : BL = 2; tRC = RC (MIN);
tCK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
t
144
144
Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks idle; Power-down mode;
tCK = CK (MIN); CKE = LOW
t
Id le st a n d b y cu rre n t : CS# = HIGH; All device banks idle; tCK = CK (MIN); CKE = HIGH;
t
1,800 1,800
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ and
DQS
IDD3P2
IDD3N2
1,260 1,080
2,160 1,980
mA
mA
Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank active; Power-down mode;
t
tCK = CK (MIN); CKE = LOW
Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One device bank active;
t
t
tRC = RAS (MAX); tCK = CK (MIN); DQ and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
IDD4R1
3,312 2,952
3,312 2,952
5,760 5,760
mA
mA
Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle; tCK = CK (MIN);
t
IOUT = 0mA
IDD4W1
Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle; tCK = CK (MIN); DQ
t
and DQS inputs changing twice per clock cycle
IDD52
IDD5A2
IDD62
mA
mA
mA
mA
Au t o re fre sh cu rre n t
tRFC = tRFC (MIN)
tRFC = 7.8125µs
216
144
216
144
Se lf re fre sh cu rre n t : CKE ≤ 0.2V
IDD71
5,292 4,932
Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device bank interleaving reads
(BL = 4) with auto precharge; tRC = RC (MIN); tCK = CK (MIN); Address and control
t
t
inputs change only during active READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
12
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ele ct rica l Sp e cifica t io n s
Ta b le 10:
IDD Sp e cifica t io n s a n d Co n d it io n s – 1GB (All Ot h e r Die Re visio n s)
Values are for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
-26A/
Pa ra m e t e r/Co n d it io n
Sym b o l -40B -335 -262 -265 Un it s
IDD01
2,502 2,322 2,322 2,232 mA
t
Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : tRC = RC (MIN);
tCK = CK (MIN); DQ and DQS inputs changing once per clock cycle; Address
t
and control inputs changing once every two clock cycles
IDD11
3,132 3,132 2,952 2,682 mA
Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : BL = 2;
t
t
tRC = RC (MIN); tCK = CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD2P2
144
144
144
144
mA
Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks idle; Power-
t
down mode; tCK = CK (MIN); CKE = LOW
IDD2F2 2,160 1,800 1,620 1,620 mA
t
Id le st a n d b y cu rre n t : CS# = HIGH; All device banks idle; tCK = CK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
IN = VREF for DQ and DQS
IDD3P2 1,440 1,080 900
900/
mA
Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank active; Power-
down mode; tCK = CK (MIN); CKE = LOW
t
1,080
IDD3N2 2,520 2,160 1,800 1,800 mA
IDD4R1 3,672 3,222 2,772 2,772 mA
IDD4W1 3,582 3,222 2,772 2,772 mA
Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One device bank active;
t
t
tRC = RAS (MAX); tCK = CK (MIN); DQ and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
tCK = CK (MIN); IOUT = 0mA
Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = CK (MIN); DQ and DQS inputs changing twice per clock cycle
t
IDD52
9,360 9,180 8,460 8,460/ mA
8,820
Au t o re fre sh cu rre n t
tRFC = tRFC (MIN)
IDD5A2
IDD62
216
144
216
144
216
144
216
144
mA
mA
tRFC = 7.8125µs
Se lf re fre sh cu rre n t : CKE ≤ 0.2V
IDD71
8,532 7,452 6,372 6,372/ mA
6,642
Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device bank interleaving
reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during active READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
13
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Ele ct rica l Sp e cifica t io n s
Ta b le 11:
IDD Sp e cifica t io n s a n d Co n d it io n s – 2GB
Values are for the MT46V128M4 DDR SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
-26A/
-265 Un it s
Pa ra m e t e r/Co n d it io n
Sym b o l -40B -335
-262
IDD01
2,880 2,430 2,430 2,160
mA
t
Op e ra t in g o n e b a n k a ct ive -p re ch a rg e cu rre n t : tRC = RC (MIN);
tCK = CK (MIN); DQ and DQS inputs changing once per clock cycle;
t
Address and control inputs changing once every two clock cycles
IDD11
3,420 2,970 2,970 2,700
mA
Op e ra t in g o n e b a n k a ct ive -re a d -p re ch a rg e cu rre n t : BL = 2;
t
t
tRC = RC (MIN); tCK = CK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD2P2
180
180
180
180
mA
mA
Pre ch a rg e p o w e r-d o w n st a n d b y cu rre n t : All device banks idle; Power-
t
down mode; tCK = CK (MIN); CKE = LOW
IDD2F2 1,980 1,620 1,620 1,440
t
Id le st a n d b y cu rre n t : CS# = HIGH; All device banks idle; tCK = CK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock
cycle; VIN = VREF for DQ and DQS
IDD3P2 1,620 1,260 1,260 1,080
IDD3N2 2,160 1,800 1,800 1,620
mA
mA
Act ive p o w e r-d o w n st a n d b y cu rre n t : One device bank active; Power-
t
down mode; tCK = CK (MIN); CKE = LOW
Act ive st a n d b y cu rre n t : CS# = HIGH; CKE = HIGH; One device bank
t
t
active; tRC = RAS (MAX); tCK = CK (MIN); DQ and DQS inputs changing
twice per clock cycle; Address and other control inputs changing once per
clock cycle
IDD4R1 3,510 3,060 3,060 2,700
IDD4W1 3,600 3,240 2,880 2,520
mA
mA
Op e ra t in g b u rst re a d cu rre n t : BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
t
cycle; tCK = CK (MIN); IOUT = 0mA
Op e ra t in g b u rst w rit e cu rre n t : BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = CK (MIN); DQ and DQS inputs changing twice per clock cycle
t
IDD52 12,420 10,440 10,440 10,080 mA
Au t o re fre sh cu rre n t
tRFC = tRFC (MIN)
tRFC = 7.8125µs
IDD5A2
IDD62
396
180
360
180
360
180
360
180
mA
mA
mA
Se lf re fre sh cu rre n t : CKE ≤ 0.2V
IDD71
8,190 7,380 7,290 6,390
Op e ra t in g b a n k in t e rle a ve re a d cu rre n t : Four device bank
t
interleaving reads (BL = 4) with auto precharge; tRC = RC (MIN);
t
tCK = CK (MIN); Address and control inputs change only during active
READ or WRITE commands
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
14
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Re g ist e r a n d PLL Sp e cifica t io n s
Re g ist e r a n d PLL Sp e cifica t io n s
Ta b le 12:
Re g ist e r Sp e cifica t io n s
SSTV16859 devices or equivalent JESD82-4B
Pa ra m e t e r
Sym b o l
Pin s
Co n d it io n
Min
Ma x
Un it s
VIH(DC) Control, command,
address
SSTL_25
VREF(DC) + 150
–
mV
DC high-level
input voltage
VIL(DC) Control, command,
address
SSTL_25
SSTL_25
SSTL_25
–
VREF(DC) - 150
VDD
mV
mV
mV
DC low-level
input voltage
VIH(AC) Control, command,
address
VREF(DC) + 310
–
AC high-level
input voltage
VIL(AC) Control, command,
address
VREF(DC) - 310
AC low-level
input voltage
VOH
VOL
II
Parity output
Parity output
All pins
LVCMOS
LVCMOS
VDD - 0.2
–
V
V
Output high voltage
Output low voltage
Input current
–
–5.0
–
0.2
VI = VDDQ or VSSQ
RESET# = VSSQ (IO = 0)
+5.0
100
µA
µA
mA
IDD
IDD
All pins
Static standby
All pins
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
–
Varies by
manufacturer
Static operating
IDDD
IDDD
n/a
n/a
RESET# = VDD, VI = VIH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50% duty
cycle
–
–
Varies by
manufacturer
µA
µA
Dynamic operating
(clock tree)
RESET# = VDD, VI = VIH(AC)
or VIL(AC), IO = 0; CK and
CK# switching 50% duty
cycle; One data input
Varies by
manufacturer
Dynamic operating
(per each input)
t
switching at CK/2, 50%
duty cycle
CI
CI
All inputs except
RESET#
VI = VREF ±250mV;
VDDQ = 1.8V
2.5
–
3.5
pF
pF
Input capacitance
(per device, per pin)
RESET#
VI = VDDQ or VSSQ
Varies by
Input capacitance
manufacturer
(per device, per pin)
Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-
ation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available in
JEDEC Standard JESD82.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
15
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Re g ist e r a n d PLL Sp e cifica t io n s
Ta b le 13:
Pa ra m e t e r
PLL Sp e cifica t io n s
CVF857 device or equivalent JESD82-1A
Sym b o l
Min
Ma x
Un it s
VIH
VIL
1.7
VDDQ + 0.3
0.7
V
V
DC high-level input voltage
DC low-level input voltage
Input voltage (limits)
–0.3
VIN
–0.3
VDDQ + 0.3
(VDDQ/2) + 0.2
VDDQ + 0.6
VDDQ + 0.6
+10
V
VIX
(VDDQ/2) - 0.2
V
Input differential-pair cross voltage
Input differential voltage
Input differential voltage
Input current
VID(DC)
VID(AC)
II
0.36
0.70
–10
–
V
V
µA
µA
µA
mA
pF
IDDPD
IDDQ
IADD
CIN
200
Dynamic supply current
Dynamic supply current
Dynamic supply current
Input capacitance
–
300
–
12
2.0
3.5
Ta b le 14:
Pa ra m e t e r
PLL Clo ck Drive r Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
Sym b o l
Min
Ma x
Un it s
tL
tslr(i)
–
1.0
30
0
100
4.0
50
µs
V/ns
kHz
%
Stabilization time
Input clock slew rate
–
–
–
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth (–3dB from unity gain)
–0.5
–
2.0
MHz
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82-1A.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
16
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Se ria l Pre se n ce -De t e ct
Se ria l Pre se n ce -De t e ct
Ta b le 15:
Se ria l Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
VDDSPD
VIH
VIL
2.3
3.6
V
V
Supply voltage
VDDSPD × 0.7 VDDSPD + 0.5
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
–1.0
VDDSPD × 0.3
V
VOL
ILI
–
–
–
–
–
0.4
10
V
Output low voltage: IOUT = 3mA
µA
µA
µA
mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 kHz
ILO
10
ISB
30
ICC
2.0
Ta b le 16:
Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
No t e s
tAA
tBUF
tHD:DAT
tF
0.2
1.3
200
–
0.9
–
µs
µs
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
–
ns
300
300
–
ns
2
2
SDA fall time
tR
–
ns
SDA rise time
tHD:DI
tHD:STA
tHIGH
tLOW
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
0
µs
µs
Data-in hold time
0.6
0.6
1.3
–
–
Start condition hold time
Clock HIGH period
–
µs
–
µs
Clock LOW period
400
–
kHz
ns
µs
µs
SCL clock frequency
100
0.6
0.6
–
Data-in setup time
–
3
4
Start condition setup time
Stop condition setup time
WRITE cycle time
–
5
ms
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Se ria l Pre se n ce -De t e ct Da t a
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/ SPD.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
17
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Mo d u le Dim e n sio n s
Mo d u le Dim e n sio n s
Fig u re 7:
184-Pin RDIMM – Ta ll-He ig h t La yo u t (1GB, 2GB)
Front view
133.50 (5.256)
4.0 (0.157)
MAX
133.20 (5.244)
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U18
U39
43.31 (1.705)
43.05 (1.695)
U38
U37
U11
U12
U13
U14
U15
U16
U17
2.0 (0.079) R
(4X)
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
0.9 (0.035) R
1.37 (0.054)
1.17 (0.046)
Pin 1
10.0 (0.394)
2.21 (0.087) TYP
1.27 (0.05)
TYP
1.02 (0.04)
TYP
6.35 (0.25) TYP
TYP
1.0 (0.039) TYP
64.77 (2.55)
TYP
49.53 (1.95)
TYP
Pin 92
120.65 (4.75)
TYP
Back view
U19
U20
U21
U22
U32
U23
U24
U25
U33
U26
U34
U27
U35
U28
U29
U30
U31
U36
U40
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-
tional design dimensions.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
18
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Mo d u le Dim e n sio n s
Fig u re 8:
184-Pin RDIMM – St a n d a rd -He ig h t La yo u t (1GB)
Front view
133.50 (5.256)
133.20 (5.244)
4.0 (0.157)
MAX
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
30.61 (1.205)
30.35 (1.195)
2.0 (0.079) R
(4X)
U16
U13
U14
U15
U17
U18
U20
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
U19
2.31 (0.091) TYP
0.9 (0.035) R
1.37 (0.054)
1.17 (0.046)
Pin 1
2.21 (0.087) TYP
1.0 (0.039) TYP
10.0 (0.394)
TYP
1.27 (0.05)
TYP
1.02 (0.04)
TYP
6.35 (0.25) TYP
64.77 (2.55)
TYP
49.53 (1.95)
TYP
Pin 92
120.65 (4.75)
TYP
Back view
U27
U21
U22
U23
U24
U26
U28
U29
U30
U31
U32
U33
U25
U37
U34
U35
U36
U38
U39
U40
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-
tional design dimensions.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
19
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
Mo d u le Dim e n sio n s
Fig u re 9:
184-Pin RDIMM – St a n d a rd -He ig h t La yo u t (2GB)
Front view
133.50 (5.256)
133.20 (5.244)
4.0 (0.157)
MAX
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
30.61 (1.205)
30.35 (1.195)
2.0 (0.079) R
(4X)
U11
U12
U13
U14
U16
U17
U18
U20
U15
U19
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
1.37 (0.054)
1.17 (0.046)
0.9 (0.035) R
Pin 1
2.21 (0.087) TYP
1.0 (0.039) TYP
10.0 (0.394)
TYP
1.27 (0.05)
TYP
1.02 (0.04)
TYP
6.35 (0.25) TYP
64.77 (2.55)
TYP
49.53 (1.95)
TYP
Pin 92
120.65 (4.75)
TYP
Back view
U21
U22
U23
U24
U25
U27
U28
U29
U30
U31
U26
U32
U33
U34
U35
U37
U38
U39
U40
U36
3.8 (0.15) TYP
Pin 184
Pin 93
73.28 (2.88)
TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-
tional design dimensions.
®
8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900
p ro d m kt g @m icro n .co m w w w .m icro n .co m Cu st o m e r Co m m e n t Lin e : 800-932-4992
Micro n , t h e M lo g o , a n d t h e Micro n lo g o a re t ra d e m a rks o f Micro n Te ch n o lo g y, In c. All o t h e r t ra d e m a rks a re t h e p ro p e rt y o f
t h e ir re sp e ct ive o w n e rs.
Th is d a t a sh e e t co n t a in s m in im u m a n d m a xim u m lim it s sp e cifie d o ve r t h e p o w e r su p p ly a n d t e m p e ra t u re ra n g e se t fo rt h
h e re in . Alt h o u g h co n sid e re d fin a l, t h e se sp e cifica t io n s a re su b je ct t o ch a n g e , a s fu rt h e r p ro d u ct d e ve lo p m e n t a n d d a t a
ch a ra ct e riza t io n so m e t im e s o ccu r.
PDF: 09005aef80772fd2/Source: 09005aef8075ebf6
DDF36C128_256x72.fm - Rev. G 9/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
20
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