MT40A1G8WE-083E [MICRON]
Automotive DDR4 SDRAM;
| 型号： | MT40A1G8WE-083E |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | Automotive DDR4 SDRAM 动态存储器 双倍数据速率 |
| 文件： | 总358页 (文件大小：11412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Automotive DDR4 SDRAM
MT40A1G8
MT40A512M16
Options1
Marking
Features
• VDD = VDDQ = 1.2V ±±60V
• VPP = 2.5V –1250V/+2560V
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• Refresh ti0e of 8192-cycle at TC te0perature range:
– ±40s at –46°C to 85°C
• Configuration
– 1 Gig x 8
– 512 Meg x 1±
1G8
512M1±
• 78-ball FBGA package (Pb-free) – x8
– 800 x 1200 – Rev. B
• 9±-ball FBGA package (Pb-free) – x1±
– 800 x 1400 – Rev. B
• Ti0ing – cycle ti0e
– 6.756ns @ CL = 18 (DDR4-2±±±)
– 6.833ns @ CL = 1± (DDR4-2466)
• Product certification
– Auto0otive
• Operating te0perature
– Industrial (–46° TC 95°C)
– Auto0otive (–46° TC 165°C)
– Ultra-high (–46° TC 125°C)3
– Revision
WE
JY
– 320s at 85°C to 95°C
– 1±0s at 95°C to 165°C
– 80s at 165°C to 125°C
-675E
-683E
• 1± internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x1±): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Progra00able data strobe prea0bles
• Data strobe prea0ble training
• Co00and/Address latency (CAL)
• Multipurpose register read and write capability
• Write and read leveling
A
IT
AT
UT
:B
• Self refresh 0ode
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Notes:
• Low-power auto self refresh (LPASR)
• Te0perature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maxi0u0 power saving
• Output driver calibration
2. The data sheet does not support ×4 mode
even though ×4 mode description exists in
the following sections.
3. The UT option use based on automotive us-
age model. Please contact Micron sales rep-
resentative if you have questions.
• No0inal, park, and dyna0ic on-die ter0ination
(ODT)
• Data bus inversion (DBI) for data bus
• Co00and/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test (x1±)
• JEDEC JESD-79-4 co0pliant
• sPPR and hPPR capability
• AEC-Q166
• PPAP sub0ission
• 8D response ti0e
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
-075E1
Data Rate (MT/s)
Target tRCD-tRP-CL
18-18-18
tRCD (ns)
13.5
tRP (ns)
13.5
CL (ns)
13.5
2666
2400
-083E
16-16-16
13.32
13.32
13.32
1. Backward compatible to 2400, CL = 16.
Note:
Table 2: Addressing
Parameter
1024 Meg x 8
512 Meg x 16
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
4
BG[1:0]
4
2
BG0
4
BA[1:0]
64K (A[15:0])
1K (A[9:0])
1KB
BA[1:0]
64K (A[15:0])
1K (A[9:0])
2KB
Column addressing
Page size1
1. Page size is per bank, calculated as follows:
Note:
Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
Figure 1: Order Part Number Example
Example Part Number: MT40A1G8WE-083EAAT:B
-
:
Configuration
Package
Speed
Revision
MT40A
Revision
:B
Configuration
1 Gig x 8
512 Meg x 16
Mark
1G8
512M16
Case Temperature
Commercial
Mark
Package
Mark
WE
JY
None
IT
78-ball 8.0mm x 12.0mm FBGA
96-ball 8.0mm x 14.0mm FBGA
Industrial temperature
Automotive
AT
Ultra-high
UT
Mark Speed Grade
Product certification
Automotive
Mark
A
t
-083E CK = 0.833ns, CL = 16
t
-075E CK = 0.750ns, CL = 18
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
2
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Contents
General Notes and Description ....................................................................................................................... 18
Description ................................................................................................................................................ 18
Industrial Te0perature ............................................................................................................................... 18
Auto0otive Te0perature ............................................................................................................................ 18
Ultra-high Te0perature .............................................................................................................................. 18
General Notes ............................................................................................................................................ 18
Definitions of the Device-Pin Signal Level ................................................................................................... 19
Definitions of the Bus Signal Level ............................................................................................................... 19
Functional Block Diagra0s ............................................................................................................................. 26
Ball Assign0ents ............................................................................................................................................ 21
Ball Descriptions ............................................................................................................................................ 23
Package Di0ensions ....................................................................................................................................... 2±
State Diagra0 ................................................................................................................................................ 28
Functional Description ................................................................................................................................... 36
RESET and Initialization Procedure ................................................................................................................. 31
Power-Up and Initialization Sequence ......................................................................................................... 31
RESET Initialization with Stable Power Sequence ......................................................................................... 34
Uncontrolled Power-Down Sequence .......................................................................................................... 35
Progra00ing Mode Registers ......................................................................................................................... 3±
Mode Register 6 .............................................................................................................................................. 39
Burst Length, Type, and Order ..................................................................................................................... 41
CAS Latency ............................................................................................................................................... 42
Test Mode .................................................................................................................................................. 42
Write Recovery(WR)/READ-to-PRECHARGE ............................................................................................... 42
DLL RESET ................................................................................................................................................. 42
Mode Register 1 .............................................................................................................................................. 43
DLL Enable/DLL Disable ............................................................................................................................ 44
Output Driver I0pedance Control ............................................................................................................... 45
ODT RTT(NOM) Values .................................................................................................................................. 45
Additive Latency ......................................................................................................................................... 45
Write Leveling ............................................................................................................................................ 45
Output Disable ........................................................................................................................................... 4±
Ter0ination Data Strobe ............................................................................................................................. 4±
Mode Register 2 .............................................................................................................................................. 47
CAS WRITE Latency .................................................................................................................................... 49
Low-Power Auto Self Refresh ....................................................................................................................... 49
Dyna0ic ODT ............................................................................................................................................ 49
Write Cyclic Redundancy Check Data Bus .................................................................................................... 49
Mode Register 3 .............................................................................................................................................. 56
Multipurpose Register ................................................................................................................................ 51
WRITE Co00and Latency When CRC/DM is Enabled ................................................................................. 52
Fine Granularity Refresh Mode .................................................................................................................... 52
Te0perature Sensor Status ......................................................................................................................... 52
Per-DRAM Addressability ........................................................................................................................... 52
Gear-Down Mode ....................................................................................................................................... 52
Mode Register 4 .............................................................................................................................................. 53
Hard Post Package Repair Mode .................................................................................................................. 54
Soft Post Package Repair Mode .................................................................................................................... 55
WRITE Prea0ble ........................................................................................................................................ 55
READ Prea0ble .......................................................................................................................................... 55
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
3
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
READ Prea0ble Training ............................................................................................................................ 55
Te0perature-Controlled Refresh ................................................................................................................. 55
Co00and Address Latency ........................................................................................................................ 55
Internal VREF Monitor ................................................................................................................................. 55
Maxi0u0 Power Savings Mode ................................................................................................................... 5±
Mode Register 5 .............................................................................................................................................. 57
Data Bus Inversion ..................................................................................................................................... 58
Data Mask .................................................................................................................................................. 59
CA Parity Persistent Error Mode .................................................................................................................. 59
ODT Input Buffer for Power-Down .............................................................................................................. 59
CA Parity Error Status ................................................................................................................................. 59
CRC Error Status ......................................................................................................................................... 59
CA Parity Latency Mode .............................................................................................................................. 59
Mode Register ± .............................................................................................................................................. ±6
tCCD_L Progra00ing ................................................................................................................................. ±1
VREFDQ Calibration Enable .......................................................................................................................... ±1
VREFDQ Calibration Range ........................................................................................................................... ±1
VREFDQ Calibration Value ............................................................................................................................ ±1
Truth Tables ................................................................................................................................................... ±2
NOP Co00and .............................................................................................................................................. ±5
DESELECT Co00and .................................................................................................................................... ±5
DLL-Off Mode ................................................................................................................................................ ±5
DLL-On/Off Switching Procedures .................................................................................................................. ±7
DLL Switch Sequence fro0 DLL-On to DLL-Off ........................................................................................... ±7
DLL-Off to DLL-On Procedure .................................................................................................................... ±8
Input Clock Frequency Change ....................................................................................................................... ±9
Write Leveling ................................................................................................................................................ 76
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 72
Procedure Description ................................................................................................................................ 73
Write Leveling Mode Exit ............................................................................................................................ 74
Co00and Address Latency ............................................................................................................................ 75
Low-Power Auto Self Refresh Mode ................................................................................................................. 86
Manual Self Refresh Mode .......................................................................................................................... 86
Multipurpose Register .................................................................................................................................... 82
MPR Reads ................................................................................................................................................. 83
MPR Readout For0at ................................................................................................................................. 85
MPR Readout Serial For0at ........................................................................................................................ 85
MPR Readout Parallel For0at ..................................................................................................................... 8±
MPR Readout Staggered For0at .................................................................................................................. 87
MPR READ Wavefor0s ............................................................................................................................... 88
MPR Writes ................................................................................................................................................ 96
MPR WRITE Wavefor0s .............................................................................................................................. 91
MPR REFRESH Wavefor0s ......................................................................................................................... 92
Gear-Down Mode ........................................................................................................................................... 95
Maxi0u0 Power-Saving Mode ........................................................................................................................ 98
Maxi0u0 Power-Saving Mode Entry ........................................................................................................... 98
Maxi0u0 Power-Saving Mode Entry in PDA ............................................................................................... 99
CKE Transition During Maxi0u0 Power-Saving Mode ................................................................................. 99
Maxi0u0 Power-Saving Mode Exit ............................................................................................................. 99
Co00and/Address Parity .............................................................................................................................. 161
Per-DRAM Addressability .............................................................................................................................. 169
V
REFDQ Calibration ........................................................................................................................................ 112
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
4
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
VREFDQ Range and Levels ........................................................................................................................... 113
VREFDQ Step Size ........................................................................................................................................ 113
VREFDQ Incre0ent and Decre0ent Ti0ing .................................................................................................. 114
V
REFDQ Target Settings ............................................................................................................................... 118
Connectivity Test Mode ................................................................................................................................. 126
Pin Mapping ............................................................................................................................................. 126
Mini0u0 Ter0s Definition for Logic Equations ......................................................................................... 121
Logic Equations for a ×4 Device, When Supported ...................................................................................... 121
Logic Equations for a ×8 Device, When Supported ...................................................................................... 122
Logic Equations for a ×1± Device ................................................................................................................ 122
CT Input Ti0ing Require0ents .................................................................................................................. 122
Excessive Row Activation ............................................................................................................................... 124
Post Package Repair ....................................................................................................................................... 125
Post Package Repair ................................................................................................................................... 125
Hard Post Package Repair .............................................................................................................................. 12±
hPPR Row Repair - Entry ............................................................................................................................ 12±
hPPR Row Repair – WRA Initiated (REF Co00ands Allowed) ...................................................................... 12±
hPPR Row Repair – WR Initiated (REF Co00ands NOT Allowed) ................................................................. 128
sPPR Row Repair ........................................................................................................................................... 136
hPPR/sPPR Support Identifier ........................................................................................................................ 133
ACTIVATE Co00and .................................................................................................................................... 133
PRECHARGE Co00and ................................................................................................................................ 134
REFRESH Co00and ..................................................................................................................................... 135
Te0perature-Controlled Refresh Mode .......................................................................................................... 137
TCR Mode – Nor0al Te0perature Range .................................................................................................... 137
TCR Mode – Extended Te0perature Range ................................................................................................. 137
Fine Granularity Refresh Mode ....................................................................................................................... 139
Mode Register and Co00and Truth Table .................................................................................................. 139
tREFI and tRFC Para0eters ........................................................................................................................ 139
Changing Refresh Rate ............................................................................................................................... 142
Usage with TCR Mode ................................................................................................................................ 142
Self Refresh Entry and Exit ......................................................................................................................... 142
SELF REFRESH Operation .............................................................................................................................. 144
Self Refresh Abort ...................................................................................................................................... 14±
Self Refresh Exit with NOP Co00and ......................................................................................................... 147
Power-Down Mode ........................................................................................................................................ 149
Power-Down Clarifications – Case 1 ........................................................................................................... 154
Power-Down Entry, Exit Ti0ing with CAL ................................................................................................... 155
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 157
CRC Write Data Feature ................................................................................................................................. 159
CRC Write Data ......................................................................................................................................... 159
WRITE CRC DATA Operation ...................................................................................................................... 159
DBI_n and CRC Both Enabled .................................................................................................................... 1±6
DM_n and CRC Both Enabled .................................................................................................................... 1±6
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 1±6
CRC and Write Prea0ble Restrictions ......................................................................................................... 1±6
CRC Si0ultaneous Operation Restrictions .................................................................................................. 1±6
CRC Polyno0ial ........................................................................................................................................ 1±6
CRC Co0binatorial Logic Equations .......................................................................................................... 1±1
Burst Ordering for BL8 ............................................................................................................................... 1±2
CRC Data Bit Mapping ............................................................................................................................... 1±2
CRC Enabled With BC4 .............................................................................................................................. 1±3
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
5
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
CRC with BC4 Data Bit Mapping ................................................................................................................ 1±3
CRC Equations for x8 Device in BC4 Mode with A2 = 6 and A2 = 1 ................................................................ 1±±
CRC Error Handling ................................................................................................................................... 1±8
CRC Write Data Flow Diagra0 ................................................................................................................... 1±9
Data Bus Inversion ........................................................................................................................................ 176
DBI During a WRITE Operation .................................................................................................................. 176
DBI During a READ Operation ................................................................................................................... 171
Data Mask ..................................................................................................................................................... 172
Progra00able Prea0ble Modes and DQS Posta0bles .................................................................................... 174
WRITE Prea0ble Mode .............................................................................................................................. 174
READ Prea0ble Mode ............................................................................................................................... 177
READ Prea0ble Training ........................................................................................................................... 177
WRITE Posta0ble ...................................................................................................................................... 178
READ Posta0ble ....................................................................................................................................... 178
Bank Access Operation .................................................................................................................................. 186
READ Operation ............................................................................................................................................ 184
Read Ti0ing Definitions ............................................................................................................................ 184
Read Ti0ing – Clock-to-Data Strobe Relationship ....................................................................................... 185
Read Ti0ing – Data Strobe-to-Data Relationship ........................................................................................ 187
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 188
tRPRE Calculation ..................................................................................................................................... 189
tRPST Calculation ...................................................................................................................................... 196
READ Burst Operation ............................................................................................................................... 191
READ Operation Followed by Another READ Operation .............................................................................. 193
READ Operation Followed by WRITE Operation .......................................................................................... 198
READ Operation Followed by PRECHARGE Operation ................................................................................ 264
READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 267
READ Operation with Co00and/Address Parity (CA Parity) ........................................................................ 268
READ Followed by WRITE with CRC Enabled .............................................................................................. 216
READ Operation with Co00and/Address Latency (CAL) Enabled ............................................................... 211
WRITE Operation .......................................................................................................................................... 213
Write Ti0ing Definitions ........................................................................................................................... 213
Write Ti0ing – Clock-to-Data Strobe Relationship ...................................................................................... 213
tWPRE Calculation .................................................................................................................................... 215
tWPST Calculation ..................................................................................................................................... 21±
Write Ti0ing – Data Strobe-to-Data Relationship ........................................................................................ 21±
WRITE Burst Operation ............................................................................................................................. 226
WRITE Operation Followed by Another WRITE Operation ........................................................................... 222
WRITE Operation Followed by READ Operation .......................................................................................... 228
WRITE Operation Followed by PRECHARGE Operation ............................................................................... 232
WRITE Operation with WRITE DBI Enabled ................................................................................................ 235
WRITE Operation with CA Parity Enabled ................................................................................................... 237
WRITE Operation with Write CRC Enabled ................................................................................................. 238
Write Ti0ing Violations ................................................................................................................................. 243
Motivation ................................................................................................................................................ 243
Data Setup and Hold Violations ................................................................................................................. 243
Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 243
ZQ CALIBRATION Co00ands ....................................................................................................................... 244
On-Die Ter0ination ...................................................................................................................................... 24±
ODT Mode Register and ODT State Table ........................................................................................................ 24±
ODT Read Disable State Table .................................................................................................................... 247
Synchronous ODT Mode ................................................................................................................................ 248
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
6
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
ODT Latency and Posted ODT .................................................................................................................... 248
Ti0ing Para0eters .................................................................................................................................... 248
ODT During Reads .................................................................................................................................... 256
Dyna0ic ODT ............................................................................................................................................... 251
Functional Description .............................................................................................................................. 251
Asynchronous ODT Mode .............................................................................................................................. 254
Electrical Specifications ................................................................................................................................. 255
Absolute Ratings ........................................................................................................................................ 255
DRAM Co0ponent Operating Te0perature Range ...................................................................................... 255
Electrical Characteristics – AC and DC Operating Conditions .......................................................................... 25±
Supply Operating Conditions ..................................................................................................................... 25±
Leakages ................................................................................................................................................... 257
V
REFCA Supply ............................................................................................................................................ 257
VREFDQ Supply and Calibration Ranges ....................................................................................................... 258
VREFDQ Ranges ........................................................................................................................................... 259
Electrical Characteristics – AC and DC Single-Ended Input Measure0ent Levels .............................................. 2±6
RESET_n Input Levels ................................................................................................................................ 2±6
Co00and/Address Input Levels ................................................................................................................ 2±6
Co00and, Control, and Address Setup, Hold, and Derating ........................................................................ 2±2
Data Receiver Input Require0ents ............................................................................................................. 2±4
Connectivity Test (CT) Mode Input Levels .................................................................................................. 2±8
Electrical Characteristics – AC and DC Differential Input Measure0ent Levels ................................................. 272
Differential Inputs ..................................................................................................................................... 272
Single-Ended Require0ents for CK Differential Signals ............................................................................... 273
Slew Rate Definitions for CK Differential Input Signals ................................................................................ 274
CK Differential Input Cross Point Voltage .................................................................................................... 275
DQS Differential Input Signal Definition and Swing Require0ents .............................................................. 277
DQS Differential Input Cross Point Voltage ................................................................................................. 279
Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 286
Electrical Characteristics – Overshoot and Undershoot Specifications ............................................................. 282
Address, Co00and, and Control Overshoot and Undershoot Specifications ................................................ 282
Clock Overshoot and Undershoot Specifications ......................................................................................... 282
Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 283
Electrical Characteristics – AC and DC Output Measure0ent Levels ................................................................ 284
Single-Ended Outputs ............................................................................................................................... 284
Differential Outputs .................................................................................................................................. 285
Reference Load for AC Ti0ing and Output Slew Rate ................................................................................... 287
Connectivity Test Mode Output Levels ........................................................................................................ 287
Electrical Characteristics – AC and DC Output Driver Characteristics ............................................................... 289
Output Driver Electrical Characteristics ..................................................................................................... 289
Output Driver Te0perature and Voltage Sensitivity ..................................................................................... 292
Alert Driver ............................................................................................................................................... 292
Electrical Characteristics – On-Die Ter0ination Characteristics ...................................................................... 294
ODT Levels and I-V Characteristics ............................................................................................................ 294
ODT Te0perature and Voltage Sensitivity ................................................................................................... 295
ODT Ti0ing Definitions ............................................................................................................................ 29±
DRAM Package Electrical Specifications ......................................................................................................... 299
Ther0al Characteristics ................................................................................................................................. 363
Current Specifications – Measure0ent Conditions .......................................................................................... 364
I
I
DD, IPP, and IDDQ Measure0ent Conditions ................................................................................................ 364
DD Definitions .......................................................................................................................................... 365
Current Specifications – Patterns and Test Conditions ..................................................................................... 369
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
7
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Current Test Definitions and Patterns ......................................................................................................... 369
IDD Specifications ...................................................................................................................................... 318
Current Specifications – Li0its ....................................................................................................................... 319
Speed Bin Tables ........................................................................................................................................... 325
Refresh Para0eters By Device Density ............................................................................................................ 333
Electrical Characteristics and AC Ti0ing Para0eters – DDR4-1±66 through DDR4-2466 ................................... 334
Electrical Characteristics and AC Ti0ing Para0eters – DDR4-2±±± through DDR4-3266 ................................... 34±
Revision History ............................................................................................................................................ 358
Rev. C – 3/17 .............................................................................................................................................. 358
Rev. B – 9/1± .............................................................................................................................................. 358
Rev. A – ±/1± .............................................................................................................................................. 358
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
8
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
List of Figures
Figure 1: Order Part Nu0ber Exa0ple .............................................................................................................. 2
Figure 2: 1 Gig × 8 Functional Block Diagra0 .................................................................................................. 26
Figure 3: 512 Meg × 1± Functional Block Diagra0 ........................................................................................... 26
Figure 4: 78-Ball x4, x8 Ball Assign0ents ........................................................................................................ 21
Figure 5: 9±-Ball x1± Ball Assign0ents ............................................................................................................ 22
Figure ±: 78-Ball FBGA – x4, x8 (WE) ............................................................................................................... 2±
Figure 7: 9±-Ball FBGA – x1± (JY) .................................................................................................................... 27
Figure 8: Si0plified State Diagra0 ................................................................................................................. 28
Figure 9: RESET and Initialization Sequence at Power-On Ra0ping ................................................................. 34
Figure 16: RESET Procedure at Power Stable Condition ................................................................................... 35
Figure 11: tMRD Ti0ing ................................................................................................................................ 37
Figure 12: tMOD Ti0ing ................................................................................................................................ 37
Figure 13: DLL-Off Mode Read Ti0ing Operation ........................................................................................... ±±
Figure 14: DLL Switch Sequence fro0 DLL-On to DLL-Off .............................................................................. ±8
Figure 15: DLL Switch Sequence fro0 DLL-Off to DLL-On .............................................................................. ±9
Figure 1±: Write Leveling Concept, Exa0ple 1 ................................................................................................ 71
Figure 17: Write Leveling Concept, Exa0ple 2 ................................................................................................ 72
Figure 18: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 73
Figure 19: Write Leveling Exit ......................................................................................................................... 74
Figure 26: CAL Ti0ing Definition ................................................................................................................... 75
Figure 21: CAL Ti0ing Exa0ple (Consecutive CS_n = LOW) ............................................................................ 75
Figure 22: CAL Enable Ti0ing – tMOD_CAL ................................................................................................... 7±
Figure 23: tMOD_CAL, MRS to Valid Co00and Ti0ing with CAL Enabled ....................................................... 7±
Figure 24: CAL Enabling MRS to Next MRS Co00and, tMRD_CAL .................................................................. 77
Figure 25: tMRD_CAL, Mode Register Cycle Ti0e With CAL Enabled ............................................................... 77
Figure 2±: Consecutive READ BL8, CAL3, 1tCK Prea0ble, Different Bank Group ............................................... 78
Figure 27: Consecutive READ BL8, CAL4, 1tCK Prea0ble, Different Bank Group ............................................... 78
Figure 28: Auto Self Refresh Ranges ................................................................................................................ 81
Figure 29: MPR Block Diagra0 ....................................................................................................................... 82
Figure 36: MPR READ Ti0ing ........................................................................................................................ 89
Figure 31: MPR Back-to-Back READ Ti0ing ................................................................................................... 89
Figure 32: MPR READ-to-WRITE Ti0ing ........................................................................................................ 96
Figure 33: MPR WRITE and WRITE-to-READ Ti0ing ...................................................................................... 91
Figure 34: MPR Back-to-Back WRITE Ti0ing .................................................................................................. 92
Figure 35: REFRESH Ti0ing ........................................................................................................................... 92
Figure 3±: READ-to-REFRESH Ti0ing ............................................................................................................ 93
Figure 37: WRITE-to-REFRESH Ti0ing .......................................................................................................... 93
Figure 38: Clock Mode Change fro0 1/2 Rate to 1/4 Rate (Initialization) .......................................................... 9±
Figure 39: Clock Mode Change After Exiting Self Refresh ................................................................................. 9±
Figure 46: Co0parison Between Gear-Down Disable and Gear-Down Enable .................................................. 97
Figure 41: Maxi0u0 Power-Saving Mode Entry .............................................................................................. 98
Figure 42: Maxi0u0 Power-Saving Mode Entry with PDA ............................................................................... 99
Figure 43: Maintaining Maxi0u0 Power-Saving Mode with CKE Transition .................................................... 99
Figure 44: Maxi0u0 Power-Saving Mode Exit ............................................................................................... 166
Figure 45: Co00and/Address Parity Operation ............................................................................................. 161
Figure 4±: Co00and/Address Parity During Nor0al Operation ..................................................................... 163
Figure 47: Persistent CA Parity Error Checking Operation ............................................................................... 164
Figure 48: CA Parity Error Checking – SRE Atte0pt ........................................................................................ 164
Figure 49: CA Parity Error Checking – SRX Atte0pt ........................................................................................ 165
Figure 56: CA Parity Error Checking – PDE/PDX ............................................................................................ 165
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
9
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Figure 51: Parity Entry Ti0ing Exa0ple – tMRD_PAR ..................................................................................... 16±
Figure 52: Parity Entry Ti0ing Exa0ple – tMOD_PAR ..................................................................................... 16±
Figure 53: Parity Exit Ti0ing Exa0ple – tMRD_PAR ....................................................................................... 167
Figure 54: Parity Exit Ti0ing Exa0ple – tMOD_PAR ....................................................................................... 167
Figure 55: CA Parity Flow Diagra0 ................................................................................................................ 168
Figure 5±: PDA Operation Enabled, BL8 ........................................................................................................ 116
Figure 57: PDA Operation Enabled, BC4 ........................................................................................................ 116
Figure 58: MRS PDA Exit ............................................................................................................................... 111
Figure 59: VREFDQ Voltage Range ................................................................................................................... 112
Figure ±6: Exa0ple of VREF Set Tolerance and Step Size .................................................................................. 114
Figure ±1: VREFDQ Ti0ing Diagra0 for VREF,ti0e Para0eter .............................................................................. 115
Figure ±2: VREFDQ Training Mode Entry and Exit Ti0ing Diagra0 ................................................................... 11±
Figure ±3: VREF Step: Single Step Size Incre0ent Case .................................................................................... 117
Figure ±4: VREF Step: Single Step Size Decre0ent Case ................................................................................... 117
Figure ±5: VREF Full Step: Fro0 VREF,0in to VREF,0axCase .................................................................................. 118
Figure ±±: VREF Full Step: Fro0 VREF,0ax to VREF,0inCase .................................................................................. 118
Figure ±7: VREFDQ Equivalent Circuit ............................................................................................................. 119
Figure ±8: Connectivity Test Mode Entry ....................................................................................................... 123
Figure ±9: hPPR WRA – Entry ........................................................................................................................ 128
Figure 76: hPPR WRA – Repair and Exit ......................................................................................................... 128
Figure 71: hPPR WR – Entry .......................................................................................................................... 129
Figure 72: hPPR WR – Repair and Exit ............................................................................................................ 136
Figure 73: sPPR – Entry ................................................................................................................................. 132
Figure 74: sPPR – Repair, and Exit ................................................................................................................. 133
Figure 75: tRRD Ti0ing ................................................................................................................................ 134
Figure 7±: tFAW Ti0ing ................................................................................................................................. 134
Figure 77: REFRESH Co00and Ti0ing ......................................................................................................... 13±
Figure 78: Postponing REFRESH Co00ands (Exa0ple) ................................................................................. 13±
Figure 79: Pulling In REFRESH Co00ands (Exa0ple) ................................................................................... 13±
Figure 86: TCR Mode Exa0ple1 ..................................................................................................................... 138
Figure 81: 4Gb with Fine Granularity Refresh Mode Exa0ple ......................................................................... 141
Figure 82: OTF REFRESH Co00and Ti0ing ................................................................................................. 142
Figure 83: Self Refresh Entry/Exit Ti0ing ...................................................................................................... 145
Figure 84: Self Refresh Entry/Exit Ti0ing with CAL Mode ............................................................................... 14±
Figure 85: Self Refresh Abort ......................................................................................................................... 147
Figure 8±: Self Refresh Exit with NOP Co00and ............................................................................................ 148
Figure 87: Active Power-Down Entry and Exit ................................................................................................ 156
Figure 88: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 151
Figure 89: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 151
Figure 96: Power-Down Entry After Write ...................................................................................................... 152
Figure 91: Precharge Power-Down Entry and Exit .......................................................................................... 152
Figure 92: REFRESH Co00and to Power-Down Entry ................................................................................... 153
Figure 93: Active Co00and to Power-Down Entry ......................................................................................... 153
Figure 94: PRECHARGE/PRECHARGE ALL Co00and to Power-Down Entry .................................................. 154
Figure 95: MRS Co00and to Power-Down Entry ........................................................................................... 154
Figure 9±: Power-Down Entry/Exit Clarifications – Case 1 .............................................................................. 155
Figure 97: Active Power-Down Entry and Exit Ti0ing with CAL ...................................................................... 155
Figure 98: REFRESH Co00and to Power-Down Entry with CAL ..................................................................... 15±
Figure 99: ODT Power-Down Entry with ODT Buffer Disable Mode ................................................................ 157
Figure 166: ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................. 158
Figure 161: CRC Write Data Operation .......................................................................................................... 159
Figure 162: CRC Error Reporting ................................................................................................................... 1±8
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
10
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Figure 163: CA Parity Flow Diagra0 .............................................................................................................. 1±9
Figure 164: 1tCK vs. 2tCK WRITE Prea0ble Mode ........................................................................................... 174
t
Figure 165: 1tCK vs. 2tCK WRITE Prea0ble Mode, CCD = 4 ............................................................................ 175
t
Figure 16±: 1tCK vs. 2tCK WRITE Prea0ble Mode, CCD = 5 ............................................................................ 17±
t
Figure 167: 1tCK vs. 2 tCK WRITE Prea0ble Mode, CCD = ± ........................................................................... 17±
Figure 168: 1tCK vs. 2tCK READ Prea0ble Mode ............................................................................................ 177
Figure 169: READ Prea0ble Training ............................................................................................................. 178
Figure 116: WRITE Posta0ble ....................................................................................................................... 178
Figure 111: READ Posta0ble ........................................................................................................................ 179
Figure 112: Bank Group x4/x8 Block Diagra0 ................................................................................................ 186
Figure 113: READ Burst tCCD_S and tCCD_L Exa0ples .................................................................................. 181
t
Figure 114: Write Burst CCD_S and tCCD_L Exa0ples ................................................................................... 181
Figure 115: tRRD Ti0ing ............................................................................................................................... 182
Figure 11±: tWTR_S Ti0ing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 182
Figure 117: tWTR_L Ti0ing (WRITE-to-READ, Sa0e Bank Group, CRC and DM Disabled) .............................. 183
Figure 118: Read Ti0ing Definition ............................................................................................................... 185
Figure 119: Clock-to-Data Strobe Relationship .............................................................................................. 18±
Figure 126: Data Strobe-to-Data Relationship ................................................................................................ 187
Figure 121: tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 188
Figure 122: tRPRE Method for Calculating Transitions and Endpoints ............................................................. 189
Figure 123: tRPST Method for Calculating Transitions and Endpoints ............................................................. 196
Figure 124: READ Burst Operation, RL = 11 (AL = 6, CL = 11, BL8) ................................................................... 191
Figure 125: READ Burst Operation, RL = 21 (AL = 16, CL = 11, BL8) ................................................................. 192
Figure 12±: Consecutive READ (BL8) with 1tCK Prea0ble in Different Bank Group .......................................... 193
Figure 127: Consecutive READ (BL8) with 2tCK Prea0ble in Different Bank Group .......................................... 193
Figure 128: Nonconsecutive READ (BL8) with 1tCK Prea0ble in Sa0e or Different Bank Group ....................... 194
Figure 129: Nonconsecutive READ (BL8) with 2tCK Prea0ble in Sa0e or Different Bank Group ....................... 194
Figure 136: READ (BC4) to READ (BC4) with 1tCK Prea0ble in Different Bank Group ...................................... 195
Figure 131: READ (BC4) to READ (BC4) with 2tCK Prea0ble in Different Bank Group ...................................... 195
Figure 132: READ (BL8) to READ (BC4) OTF with 1tCK Prea0ble in Different Bank Group ............................... 19±
Figure 133: READ (BL8) to READ (BC4) OTF with 2tCK Prea0ble in Different Bank Group ............................... 19±
Figure 134: READ (BC4) to READ (BL8) OTF with 1tCK Prea0ble in Different Bank Group ............................... 197
Figure 135: READ (BC4) to READ (BL8) OTF with 2tCK Prea0ble in Different Bank Group ............................... 197
Figure 13±: READ (BL8) to WRITE (BL8) with 1tCK Prea0ble in Sa0e or Different Bank Group ........................ 198
Figure 137: READ (BL8) to WRITE (BL8) with 2tCK Prea0ble in Sa0e or Different Bank Group ........................ 198
Figure 138: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Prea0ble in Sa0e or Different Bank Group ......... 199
Figure 139: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Prea0ble in Sa0e or Different Bank Group ......... 266
Figure 146: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Prea0ble in Sa0e or Different Bank Group ..... 266
Figure 141: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Prea0ble in Sa0e or Different Bank Group ..... 261
Figure 142: READ (BC4) to WRITE (BL8) OTF with 1tCK Prea0ble in Sa0e or Different Bank Group ................ 262
Figure 143: READ (BC4) to WRITE (BL8) OTF with 2tCK Prea0ble in Sa0e or Different Bank Group ................ 262
Figure 144: READ (BL8) to WRITE (BC4) OTF with 1tCK Prea0ble in Sa0e or Different Bank Group ................ 263
Figure 145: READ (BL8) to WRITE (BC4) OTF with 2tCK Prea0ble in Sa0e or Different Bank Group ................ 263
Figure 14±: READ to PRECHARGE with 1tCK Prea0ble .................................................................................. 264
Figure 147: READ to PRECHARGE with 2tCK Prea0ble .................................................................................. 265
Figure 148: READ to PRECHARGE with Additive Latency and 1tCK Prea0ble .................................................. 265
Figure 149: READ with Auto Precharge and 1tCK Prea0ble ............................................................................ 26±
Figure 156: READ with Auto Precharge, Additive Latency, and 1tCK Prea0ble ................................................. 267
Figure 151: Consecutive READ (BL8) with 1tCK Prea0ble and DBI in Different Bank Group ............................ 267
Figure 152: Consecutive READ (BL8) with 1tCK Prea0ble and CA Parity in Different Bank Group .................... 268
Figure 153: READ (BL8) to WRITE (BL8) with 1tCK Prea0ble and CA Parity in Sa0e or Different Bank Group ... 269
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
11
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Figure 154: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Prea0ble and Write CRC in Sa0e or Different
Bank Group ............................................................................................................................................... 216
Figure 155: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Prea0ble and Write CRC in Sa0e or Different
Bank Group ............................................................................................................................................... 211
Figure 15±: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Prea0ble in Different Bank Group .................. 211
Figure 157: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Prea0ble in Different Bank Group .................. 212
Figure 158: Write Ti0ing Definition .............................................................................................................. 214
Figure 159: tWPRE Method for Calculating Transitions and Endpoints ............................................................ 215
Figure 1±6: tWPST Method for Calculating Transitions and Endpoints ............................................................ 21±
Figure 1±1: Rx Co0pliance Mask .................................................................................................................. 217
Figure 1±2: VCENT_DQ VREFDQ Voltage Variation .............................................................................................. 217
Figure 1±3: Rx Mask DQ-to-DQS Ti0ings ...................................................................................................... 218
Figure 1±4: Rx Mask DQ-to-DQS DRAM-Based Ti0ings ................................................................................. 219
Figure 1±5: Exa0ple of Data Input Require0ents Without Training ................................................................ 226
Figure 1±±: WRITE Burst Operation, WL = 9 (AL = 6, CWL = 9, BL8) ................................................................. 221
Figure 1±7: WRITE Burst Operation, WL = 19 (AL = 16, CWL = 9, BL8) ............................................................. 222
Figure 1±8: Consecutive WRITE (BL8) with 1tCK Prea0ble in Different Bank Group ........................................ 222
Figure 1±9: Consecutive WRITE (BL8) with 2tCK Prea0ble in Different Bank Group ........................................ 223
Figure 176: Nonconsecutive WRITE (BL8) with 1tCK Prea0ble in Sa0e or Different Bank Group ..................... 224
Figure 171: Nonconsecutive WRITE (BL8) with 2tCK Prea0ble in Sa0e or Different Bank Group ..................... 224
Figure 172: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Prea0ble in Different Bank Group .................... 225
Figure 173: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Prea0ble in Different Bank Group .................... 22±
Figure 174: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Prea0ble in Different Bank Group ................. 22±
Figure 175: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Prea0ble in Different Bank Group ............................ 227
Figure 17±: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Prea0ble in Different Bank Group ............................ 228
Figure 177: WRITE (BL8) to READ (BL8) with 1tCK Prea0ble in Different Bank Group ..................................... 228
Figure 178: WRITE (BL8) to READ (BL8) with 1tCK Prea0ble in Sa0e Bank Group .......................................... 229
Figure 179: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Prea0ble in Different Bank Group ...................... 236
Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Prea0ble in Sa0e Bank Group ........................... 236
t
Figure 181: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 CK Prea0ble in Different Bank Group ................. 231
Figure 182: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Prea0ble in Sa0e Bank Group ....................... 231
Figure 183: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Prea0ble ........................................................ 232
Figure 184: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Prea0ble .............................................................. 233
Figure 185: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Prea0ble ................................................ 233
Figure 18±: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Prea0ble ...................................................... 234
Figure 187: WRITE (BL8/BC4-OTF) with 1tCK Prea0ble and DBI ................................................................... 235
Figure 188: WRITE (BC4-Fixed) with 1tCK Prea0ble and DBI ......................................................................... 23±
Figure 189: Consecutive Write (BL8) with 1tCK Prea0ble and CA Parity in Different Bank Group ..................... 237
Figure 196: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Prea0ble and Write CRC in Sa0e or Different Bank
Group ....................................................................................................................................................... 238
Figure 191: Consecutive WRITE (BC4-Fixed) with 1tCK Prea0ble and Write CRC in Sa0e or Different Bank
Group ....................................................................................................................................................... 239
Figure 192: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Prea0ble and Write CRC in Sa0e or Different
Bank Group ............................................................................................................................................... 246
Figure 193: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Prea0ble and Write CRC in Sa0e or Different
Bank Group ............................................................................................................................................... 241
Figure 194: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Prea0ble and Write CRC in Sa0e or Different Bank Group .2..42
Figure 195: ZQ Calibration Ti0ing ................................................................................................................ 245
Figure 19±: Functional Representation of ODT .............................................................................................. 24±
Figure 197: Synchronous ODT Ti0ing with BL8 ............................................................................................. 249
Figure 198: Synchronous ODT with BC4 ........................................................................................................ 249
Figure 199: ODT During Reads ...................................................................................................................... 256
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
12
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Figure 266: Dyna0ic ODT (1t CK Prea0ble; CL = 14, CWL = 11, BL = 8, AL = 6, CRC Disabled) .......................... 252
Figure 261: Dyna0ic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 6, CRC Disabled) .......... 253
Figure 262: Asynchronous ODT Ti0ings with DLL Off ................................................................................... 254
Figure 263: VREFDQ Voltage Range .................................................................................................................. 257
Figure 264: RESET_n Input Slew Rate Definition ............................................................................................ 2±6
Figure 265: Single-Ended Input Slew Rate Definition ..................................................................................... 2±2
Figure 26±: DQ Slew Rate Definitions ............................................................................................................ 2±5
Figure 267: Rx Mask Relative to tDS/tDH ....................................................................................................... 2±7
Figure 268: Rx Mask Without Write Training .................................................................................................. 2±8
Figure 269: TEN Input Slew Rate Definition ................................................................................................... 2±9
Figure 216: CT Type-A Input Slew Rate Definition .......................................................................................... 276
Figure 211: CT Type-B Input Slew Rate Definition .......................................................................................... 276
Figure 212: CT Type-C Input Slew Rate Definition .......................................................................................... 271
Figure 213: CT Type-D Input Slew Rate Definition ......................................................................................... 272
Figure 214: Differential AC Swing and “Ti0e Exceeding AC-Level” tDVAC ....................................................... 272
Figure 215: Single-Ended Require0ents for CK .............................................................................................. 274
Figure 21±: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 275
Figure 217: VIX(CK) Definition ........................................................................................................................ 27±
Figure 218: Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 277
Figure 219: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exe0pt non-Monotonic Signaling ..... 278
Figure 226: VIXDQS Definition ........................................................................................................................ 279
Figure 221: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 286
Figure 222: ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 282
Figure 223: CK Overshoot and Undershoot Definition .................................................................................... 283
Figure 224: Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 284
Figure 225: Single-ended Output Slew Rate Definition ................................................................................... 285
Figure 22±: Differential Output Slew Rate Definition ...................................................................................... 28±
Figure 227: Reference Load For AC Ti0ing and Output Slew Rate ................................................................... 287
Figure 228: Connectivity Test Mode Reference Test Load ................................................................................ 288
Figure 229: Connectivity Test Mode Output Slew Rate Definition .................................................................... 288
Figure 236: Output Driver: Definition of Voltages and Currents ...................................................................... 289
Figure 231: Alert Driver ................................................................................................................................ 293
Figure 232: ODT Definition of Voltages and Currents ..................................................................................... 294
Figure 233: ODT Ti0ing Reference Load ....................................................................................................... 29±
Figure 234: tADC Definition with Direct ODT Control .................................................................................... 297
Figure 235: tADC Definition with Dyna0ic ODT Control ................................................................................ 298
Figure 23±: tAOFAS and tAONAS Definitions .................................................................................................. 298
Figure 237: Ther0al Measure0ent Point ....................................................................................................... 363
Figure 238: Measure0ent Setup and Test Load for IDDx, IDDPx, and IDDQx ........................................................ 365
Figure 239: Correlation: Si0ulated Channel I/O Power to Actual Channel I/O Power ....................................... 365
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
13
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
List of Tables
Table 1: Key Ti0ing Para0eters ....................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: Ball Descriptions .............................................................................................................................. 23
Table 4: State Diagra0 Co00and Definitions ................................................................................................ 29
Table 5: Supply Power-up Slew Rate ............................................................................................................... 31
Table ±: Address Pin Mapping ........................................................................................................................ 39
Table 7: MR6 Register Definition .................................................................................................................... 39
Table 8: Burst Type and Burst Order ............................................................................................................... 41
Table 9: Address Pin Mapping ........................................................................................................................ 43
Table 16: MR1 Register Definition .................................................................................................................. 43
Table 11: Additive Latency (AL) Settings ......................................................................................................... 45
Table 12: TDQS Function Matrix .................................................................................................................... 4±
Table 13: Address Pin Mapping ...................................................................................................................... 47
Table 14: MR2 Register Definition .................................................................................................................. 47
Table 15: Address Pin Mapping ...................................................................................................................... 56
Table 1±: MR3 Register Definition .................................................................................................................. 56
Table 17: Address Pin Mapping ...................................................................................................................... 53
Table 18: MR4 Register Definition .................................................................................................................. 53
Table 19: Address Pin Mapping ...................................................................................................................... 57
Table 26: MR5 Register Definition .................................................................................................................. 57
Table 21: Address Pin Mapping ...................................................................................................................... ±6
Table 22: MR± Register Definition .................................................................................................................. ±6
Table 23: Truth Table – Co00and .................................................................................................................. ±2
Table 24: Truth Table – CKE ........................................................................................................................... ±4
Table 25: MR Settings for Leveling Procedures ................................................................................................ 72
Table 2±: DRAM TERMINATION Function in Leveling Mode ........................................................................... 72
Table 27: Auto Self Refresh Mode ................................................................................................................... 86
Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 82
Table 29: DRAM Address to MPR UI Translation ............................................................................................. 82
Table 36: MPR Page and MPRx Definitions ..................................................................................................... 83
Table 31: MPR Readout Serial For0at ............................................................................................................. 85
Table 32: MPR Readout – Parallel For0at ....................................................................................................... 8±
Table 33: MPR Readout Staggered For0at, x4 ................................................................................................. 87
Table 34: MPR Readout Staggered For0at, x4 – Consecutive READs ................................................................ 88
Table 35: MPR Readout Staggered For0at, x8 and x1± ..................................................................................... 88
Table 3±: Mode Register Setting for CA Parity ................................................................................................. 163
Table 37: VREFDQ Range and Levels ................................................................................................................ 113
Table 38: VREFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 119
Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 121
Table 46: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 124
Table 41: PPR MR6 Guard Key Settings .......................................................................................................... 12±
Table 42: DDR4 hPPR Ti0ing Para0eters DDR4-1±66 through DDR4-3266 ..................................................... 136
Table 43: sPPR Associated Rows .................................................................................................................... 131
Table 44: PPR MR6 Guard Key Settings .......................................................................................................... 131
Table 45: DDR4 sPPR Ti0ing Para0eters DDR4-1±66 through DDR4-3266 ..................................................... 133
Table 4±: DDR4 Repair Mode Support Identifier ............................................................................................ 133
Table 47: Nor0al tREFI Refresh (TCR Disabled) ............................................................................................. 137
Table 48: Nor0al tREFI Refresh (TCR Enabled) .............................................................................................. 138
Table 49: MRS Definition .............................................................................................................................. 139
Table 56: REFRESH Co00and Truth Table .................................................................................................... 139
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
14
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 51: tREFI and tRFC Para0eters ............................................................................................................. 146
Table 52: Power-Down Entry Definitions ....................................................................................................... 149
Table 53: CRC Error Detection Coverage ........................................................................................................ 1±6
Table 54: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 1±2
Table 55: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 1±2
Table 5±: CRC Data Mapping for x1± Devices, BL8 ......................................................................................... 1±3
Table 57: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 1±3
Table 58: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 1±4
Table 59: CRC Data Mapping for x1± Devices, BC4 ......................................................................................... 1±5
Table ±6: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 176
Table ±1: DBI Write, DQ Fra0e For0at (x8) ................................................................................................... 176
Table ±2: DBI Write, DQ Fra0e For0at (x1±) ................................................................................................. 176
Table ±3: DBI Read, DQ Fra0e For0at (x8) .................................................................................................... 171
Table ±4: DBI Read, DQ Fra0e For0at (x1±) .................................................................................................. 171
Table ±5: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 172
Table ±±: Data Mask, DQ Fra0e For0at (x8) .................................................................................................. 172
Table ±7: Data Mask, DQ Fra0e For0at (x1±) ................................................................................................ 172
Table ±8: CWL Selection ............................................................................................................................... 175
Table ±9: DDR4 Bank Group Ti0ing Exa0ples .............................................................................................. 186
Table 76: Read-to-Write and Write-to-Read Co00and Intervals .................................................................... 185
Table 71: Ter0ination State Table ................................................................................................................. 247
Table 72: Read Ter0ination Disable Window ................................................................................................. 247
Table 73: ODT Latency at DDR4-1±66/-18±±/-2133/-2466/-2±±±/-3266 .......................................................... 248
Table 74: Dyna0ic ODT Latencies and Ti0ing (1tCK Prea0ble Mode and CRC Disabled) ................................ 251
Table 75: Dyna0ic ODT Latencies and Ti0ing with Prea0ble Mode and CRC Mode Matrix ............................ 252
Table 7±: Absolute Maxi0u0 Ratings ............................................................................................................ 255
Table 77: Te0perature Range ........................................................................................................................ 255
Table 78: Reco00ended Supply Operating Conditions .................................................................................. 25±
Table 79: VDD Slew Rate ................................................................................................................................ 25±
Table 86: Leakages ....................................................................................................................................... 257
Table 81: VREFDQ Specification ...................................................................................................................... 258
Table 82: VREFDQ Range and Levels ................................................................................................................ 259
Table 83: RESET_n Input Levels (CMOS) ....................................................................................................... 2±6
Table 84: Co00and and Address Input Levels: DDR4-1±66 Through DDR4-2466 ........................................... 2±6
Table 85: Co00and and Address Input Levels: DDR4-2±±± ............................................................................ 2±1
Table 8±: Co00and and Address Input Levels: DDR4-2933 and DDR4-3266 ................................................... 2±1
Table 87: Single-Ended Input Slew Rates ....................................................................................................... 2±2
Table 88: Co00and and Address Setup and Hold Values Referenced – AC/DC-Based ..................................... 2±3
t
Table 89: Derating Values for IS/tIH – AC166DC75-Based .............................................................................. 2±3
t
Table 96: Derating Values for IS/tIH – AC96/DC±5-Based .............................................................................. 2±4
Table 91: DQ Input Receiver Specifications .................................................................................................... 2±5
Table 92: Rx Mask and tDS/tDH without Write Training .................................................................................. 2±8
Table 93: TEN Input Levels (CMOS) .............................................................................................................. 2±8
Table 94: CT Type-A Input Levels .................................................................................................................. 2±9
Table 95: CT Type-B Input Levels .................................................................................................................. 276
Table 9±: CT Type-C Input Levels (CMOS) ..................................................................................................... 276
Table 97: CT Type-D Input Levels .................................................................................................................. 271
Table 98: Differential Input Swing Require0ents for CK_t, CK_c ..................................................................... 273
t
Table 99: Mini0u0 Ti0e AC Ti0e DVAC for CK ........................................................................................... 273
Table 166: Single-Ended Require0ents for CK ............................................................................................... 274
Table 161: CK Differential Input Slew Rate Definition ..................................................................................... 274
Table 162: Cross Point Voltage For CK Differential Input Signals at DDR4-1±66 through DDR4-2466 ................ 27±
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
15
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 163: Cross Point Voltage For CK Differential Input Signals at DDR4-2±±± through DDR4-3266 ................ 27±
Table 164: DDR4-1±66 through DDR4-2466 Differential Input Swing Require0ents for DQS_t, DQS_c ............. 277
Table 165: DDR4-2±33 through DDR4-3266 Differential Input Swing Require0ents for DQS_t, DQS_c ............. 277
Table 16±: Cross Point Voltage For Differential Input Signals DQS ................................................................... 279
Table 167: DQS Differential Input Slew Rate Definition .................................................................................. 286
Table 168: DDR4-1±66 through DDR4-2466 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 286
Table 169: DDR4-2±±± through DDR4-3266 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 281
Table 116: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 282
Table 111: CK Overshoot and Undershoot/ Specifications .............................................................................. 282
Table 112: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 283
Table 113: Single-Ended Output Levels ......................................................................................................... 284
Table 114: Single-Ended Output Slew Rate Definition .................................................................................... 284
Table 115: Single-Ended Output Slew Rate .................................................................................................... 285
Table 11±: Differential Output Levels ............................................................................................................. 285
Table 117: Differential Output Slew Rate Definition ....................................................................................... 28±
Table 118: Differential Output Slew Rate ....................................................................................................... 287
Table 119: Connectivity Test Mode Output Levels .......................................................................................... 287
Table 126: Connectivity Test Mode Output Slew Rate ..................................................................................... 289
Table 121: Strong Mode (34ȍ) Output Driver Electrical Characteristics ........................................................... 296
Table 122: Weak Mode (48ȍ) Output Driver Electrical Characteristics ............................................................. 291
Table 123: Output Driver Sensitivity Definitions ............................................................................................ 292
Table 124: Output Driver Voltage and Te0perature Sensitivity ....................................................................... 292
Table 125: Alert Driver Voltage ...................................................................................................................... 293
Table 12±: ODT DC Characteristics ............................................................................................................... 294
Table 127: ODT Sensitivity Definitions .......................................................................................................... 295
Table 128: ODT Voltage and Te0perature Sensitivity ..................................................................................... 29±
Table 129: ODT Ti0ing Definitions ............................................................................................................... 29±
Table 136: Reference Settings for ODT Ti0ing Measure0ents ........................................................................ 297
Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 299
Table 132: DRAM Package Electrical Specifications for x1± Devices ................................................................ 366
Table 133: Pad Input/Output Capacitance ..................................................................................................... 362
Table 134: Ther0al Characteristics ............................................................................................................... 363
Table 135: Basic IDD, IPP, and IDDQ Measure0ent Conditions .......................................................................... 365
Table 13±: IDD6 and IPP6 Measure0ent-Loop Pattern1 .................................................................................... 369
Table 137: IDD1 Measure0ent – Loop Pattern1 ............................................................................................... 316
Table 138: IDD2N, IDD3N, and IPP3P Measure0ent – Loop Pattern1 .................................................................... 311
Table 139: IDD2NT and IDDQ2NT Measure0ent – Loop Pattern1 ......................................................................... 312
Table 146: IDD4R Measure0ent – Loop Pattern1 .............................................................................................. 313
Table 141: IDD4W Measure0ent – Loop Pattern1 ............................................................................................. 314
Table 142: IDD4Wc Measure0ent – Loop Pattern1 ............................................................................................ 315
Table 143: IDD5R Measure0ent – Loop Pattern1 .............................................................................................. 31±
Table 144: IDD7 Measure0ent – Loop Pattern1 ............................................................................................... 317
Table 145: Ti0ings used for IDD, IPP, and IDDQ Measure0ent – Loop Patterns .................................................. 318
Table 14±: IDD, IPP, and IDDQ Current Li0its; Die Rev. B (–46° TC +95°C) ..................................................... 319
Table 147: IDD, IPP, and IDDQ Current Li0its; Die Rev. B (–46° TC +165°C) .................................................... 321
Table 148: IDD, IPP, and IDDQ Current Li0its; Die Rev. B (–46° TC +125°C) .................................................... 323
Table 149: DDR4-1±66 Speed Bins and Operating Conditions ......................................................................... 325
Table 156: DDR4-18±± Speed Bins and Operating Conditions ......................................................................... 32±
Table 151: DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 327
Table 152: DDR4-2466 Speed Bins and Operating Conditions ......................................................................... 328
Table 153: DDR4-2±±± Speed Bins and Operating Conditions ......................................................................... 329
Table 154: DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 336
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
16
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 155: DDR4-3266 Speed Bins and Operating Conditions ......................................................................... 332
Table 15±: Refresh Para0eters by Device Density ........................................................................................... 333
Table 157: Electrical Characteristics and AC Ti0ing Para0eters ..................................................................... 334
Table 158: Electrical Characteristics and AC Ti0ing Para0eters ..................................................................... 34±
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
17
8Gb: x8, x16 Automotive DDR4 SDRAM
General Notes and Description
General Notes and Description
Description
The DDR4 SDRAM is a high-speed dyna0ic rando0-access 0e0ory internally config-
ured as an eight-bank DRAM for the x1± configuration and as a 1±-bank DRAM for the
x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-
speed operation. The 8n-prefetch architecture is co0bined with an interface designed
to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Industrial Temperature
An industrial te0perature (IT) device option requires that the case te0perature not ex-
ceed below –46°C or above 95°C. JEDEC specifications require the refresh rate to double
when TC exceeds 85°C; this also requires use of the high-te0perature self refresh option.
Additionally, ODT resistance and the input/output i0pedance 0ust be derated when
operating outside of the co00ercial te0perature range (6°C ~ +85°C).
Automotive Temperature
The auto0otive te0perature (AT) device option requires that the case te0perature not
exceed below –46°C or above 165°C. The specifications require the refresh rate to 2X
when TC exceeds 85°C; 4X when TC exceeds 95°C. Additionally, ODT resistance and the
input/output i0pedance 0ust be derated when operating outside of the co00ercial
te0perature range ( 6°C ~ +85°C).
Ultra-high Temperature
The ultra-high te0perature (UT) device option requires that the case te0perature not
exceed below –46°C or above 125°C. The specifications require the refresh rate to 2X
when TC exceeds 85°C; 4X when TC exceeds 95°C, 8X when TC exceeds 165°C. Addition-
ally, ODT resistance and the input/output i0pedance 0ust be derated when operating
outside of the co00ercial te0perature range (6°C ~ +85°C).
General Notes
• The functionality and the ti0ing specifications discussed in this data sheet are for the
DLL enable 0ode of operation (nor0al operation), unless specifically stated other-
wise.
• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ
ter0 is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise.
• The ter0s "_t" and "_c" are used to represent the true and co0ple0ent of a differen-
tial signal pair. These ter0s replace the previously used notation of "#" and/or over-
bar characters. For exa0ple, differential data strobe pair DQS, DQS# is now referred
to as DQS_t, DQS_c.
• The ter0 "_n" is used to represent a signal that is active LOW and replaces the previ-
ously used "#" and/or overbar characters. For exa0ple: CS# is now referred to as
CS_n.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
18
© 2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
General Notes and Description
• The ter0s "DQS" and "CK" found throughout the data sheet are to be interpreted as
DQS_t and DQS_c, and CK_t and CK_c respectively, unless specifically stated other-
wise.
• Co0plete functionality 0ay be described throughout the entire docu0ent; any page
or diagra0 0ay have been si0plified to convey a topic and 0ay not be inclusive of all
require0ents.
• Any specific require0ent takes precedence over a general state0ent.
• Any functionality not specifically stated here within is considered undefined, illegal,
and not supported, and can result in unknown operation.
• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for
row/col address.
• The NOP co00and is not allowed, except when exiting 0axi0u0 power savings
0ode or when entering gear-down 0ode, and only a DES co00and should be used.
• Not all features described within this docu0ent 0ay be available on the rev. A (first)
version.
• Not all specifications listed are finalized industry standards; best conservative esti-
0ates have been provided when an industry standard has not been finalized.
• Although it is i0plied throughout the specification, the DRAM 0ust be used after VDD
has reached the stable power-on level, which is achieved by toggling CKE at least once
every 8192 × tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least
once every 8192 × tREFI is an acceptable alternative. Placing the DRAM into self re-
fresh 0ode also alleviates the need to toggle CKE.
• Not all features designated in the data sheet 0ay be supported by earlier die revisions
due to late definition by JEDEC.
Definitions of the Device-Pin Signal Level
• HIGH: A device pin is driving the logic 1 state.
• LOW: A device pin is driving the logic 6 state.
• High-Z: A device pin is tri-state.
• ODT: A device pin ter0inates with the ODT setting, which could be ter0inating or tri-
state depending on the 0ode register setting.
Definitions of the Bus Signal Level
• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is no0inally VDDQ
.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is no0inally VOL(DC) if ODT was enabled, or
VSSQ if High-Z.
• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as
the bus is floating.
• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-
el on the bus is no0inally VDDQ
.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
19
8Gb: x8, x16 Automotive DDR4 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR4 SDRAM is a high-speed, CMOS dyna0ic rando0 access 0e0ory. It is internally
configured as an 1±-bank (4-banks per Bank Group) DRAM.
Figure 2: 1 Gig × 8 Functional Block Diagram
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CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
20
8Gb: x8, x16 Automotive DDR4 SDRAM
Ball Assignments
Ball Assignments
Figure 4: 78-Ball x4, x8 Ball Assignments
1
2
3
4
5
6
7
8
9
A
B
C
D
E
A
B
C
D
E
NF, NF/
NF, NF/DM_n/
DBI_n/TDQS_t
VDD
VPP
V
V
V
SS
SSQ
SSQ
TDQS_c
VDDQ
DQS_c
DQS_t
DQ1
VDD
VDDQ
ZQ
VDDQ
DQ0
V
VDDQ
SS
VSSQ DQ4/NC DQ2
DQ3 DQ5/NC
DQ7/NC VDDQ
V
SSQ
VSS
VDDQ DQ6/NC
V
SS
F
F
VDD C2/ODT1 ODT
CK_t
CK_c
VDD
G
H
J
G
H
J
VSS
C0/CKE1 CKE
CS_n C1/CS1_n RFU/TEN
CAS_n/
VDD WE_n/A14ACT_n
RAS_n/A16 V
SS
A15
VREFCA
BG0 A10/AP
A12/BC_n BG1
VDD
K
L
K
L
VSS
BA0
A4
A0
A3
A1
A9
BA1
V
SS
RESET_n A6
A5 ALERT_n
M
N
M
N
VDD
VSS
A8
A2
A7
V
PP
A11
PAR
A17/NF A13
VDD
1. See Ball Descriptions.
Notes:
2. A comma “,” separates the configuration; a slash “/” defines a selectable function. For
example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configuration
only. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable be-
tween NF, DM_n, DBI_n, or TDQS_t via MRS.
3. Address bits (including bank groups) are density- and configuration-dependent (see Ad-
dressing).
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
21
© 2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Ball Assignments
Figure 5: 96-Ball x16 Ball Assignments
1
2
3
4
5
6
7
8
9
A
B
C
D
E
A
B
C
D
E
VDDQ
VSSQ
DQ8
VDD
UDQS_c VSSQ
UDQS_t DQ9
DQ11 DQ13
VDDQ
VDD
VSSQ
VDDQ
VSS
VPP
VSS
VDDQ DQ12 DQ10
VDD
VSSQ
DQ14
VSSQ
DQ15
VSSQ
VSSQ
VDDQ
VSS
NF/LDM_n/
LDBI_n
NF/UDM_n/
UDBI_n
VSS
F
F
VSSQ
VDDQ
VSSQ
VDD
VSS
VDDQ LDQS_c
DQ0 LDQS_t
DQ1
VDD
ZQ
G
H
J
G
H
J
VDDQ
VSSQ
VDD
VSS
DQ4
VDDQ
CKE
DQ2
DQ6
ODT
DQ3
DQ7
CK_t
DQ5
VDDQ
CK_c
K
L
K
L
VDD WE_n/A14 ACT_n
CS_n RAS_n/A16 VDD
M
N
P
M
N
P
VREFCA
BG0
BA0
A10/AP
A4
A12/BC_n CAS-n/A15 VSS
VSS
A3
A1
A9
NC
BA1
A5
TEN
ALERT_n
RESET_n A6
A0
R
T
R
T
VDD
A8
A2
A7
VPP
VSS
A11
PAR
A13
VDD
1. See Ball Descriptions.
Notes:
2. A slash “/” defines a selectable function. For example: Ball E7 = NF/LDM_n. If data mask
is enabled via the MRS, ball E7 = LDM_n. If data mask is disabled in the MRS, E7 = NF (no
function).
3. Address bits (including bank groups) are density- and configuration-dependent (see Ad-
dressing).
CCMTD-1406124318-10419
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22
© 2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Ball Descriptions
Ball Descriptions
The pin description table below is a co0prehensive list of all possible pins for DDR4 de-
vices. All pins listed 0ay not be supported on the device defined in this data sheet. See
the Ball Assign0ents section to review all pins used on this device.
Table 3: Ball Descriptions
Symbol
Type
Description
A[17:0]
Input
Address inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have addi-
tional functions, see individual entries in this table.) The address inputs also provide
the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and
16Gb parts, and A17 is only used on some 16Gb parts.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine
whether auto precharge should be performed to the accessed bank after a READ or
WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sam-
pled during a PRECHARGE command to determine whether the PRECHARGE applies
to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,
the bank is selected by the bank group and bank addresses.
A12/BC_n
ACT_n
Input
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if
burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chop-
ped). See the Command Truth Table.
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with
CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as
row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with
CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as nor-
mal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command
Truth Table.
BA[1:0]
BG[1:0]
Input
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command.
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are
used in the x4 and x8 configurations. BG1 is not used in the x16 configuration.
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked; that is,
they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are
not used in the x16 configuration). DDR4 will support a traditional DDP package,
which uses these three signals for control of the second die (CS1_n, CKE1, ODT1).
DDR4 is not expected to support a traditional QDP package. For all other stack con-
figurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of
configuration where C0, C1, and C2 are used as chip ID selects in conjunction with a
single CS_n, CKE, and ODT signal.
CK_t,
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
CKE
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock sig-
nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has
become stable during the power-on and initialization sequence, it must be main-
tained during all operations (including SELF REFRESH). CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RE-
SET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and
RESET_n) are disabled during self refresh.
CS_n
Input
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides
for external rank selection on systems with multiple ranks. CS_n is considered part of
the command code.
DM_n,
UDM_n
LDM_n
Input data mask: DM_n is an input mask signal for write data. Input data is masked
when DM is sampled LOW coincident with that input data during a write access. DM
is sampled on both edges of DQS. DM is not supported on x4 configurations. The
UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with
DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are en-
abled by mode register settings. See the Data Mask section.
ODT
PAR
Input
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t,
DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations
(when the TDQS function is enabled via mode register). For the x16 configuration, RTT
is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal.
The ODT pin will be ignored if the mode registers are programmed to disable RTT.
Parity for command and address: This function can be enabled or disabled via the
mode register. When enabled, the parity signal covers all command and address in-
puts, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n,
BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT cov-
ered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are densi-
ty- and configuration-specific should be treated internally as 0s by the DRAM parity
logic. Command and address inputs will have parity check performed when com-
mands are latched via the rising edge of CK_t and when CS_n is LOW.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input
Input
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and
ACT_n) define the command and/or address being entered. See the ACT_n descrip-
tion in this table.
RESET_n
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inac-
tive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n
is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV
for DC HIGH and 240 mV for DC LOW).
TEN
Input
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC
HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC
LOW).
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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24
© 2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
DQ
I/O
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and
DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled
via mode register, the write CRC code is added at the end of data burst. Any one or
all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal VREF level during
test via mode register setting MR[4] A[4] = HIGH, training times change when ena-
bled. During this mode, the RTT value should be set to High-Z. This measurement is
for verification purposes and is NOT an external voltage supply pin.
DBI_n,
UDBI_n,
LDBI_n
I/O
I/O
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data
bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configu-
ration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The
DBI feature is not supported on the x4 configuration. DBI can be configured for both
READ (output) and WRITE (input) operations depending on the mode register set-
tings. The DM, DBI, and TDQS functions are enabled by mode register settings. See
the Data Bus Inversion section.
DQS_t,
DQS_c,
DQSU_t,
DQSU_c,
DQSL_t,
DQSL_c
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For the x16, DQSL corresponds to the
data on DQ[7:0]; DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 con-
figurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4
SDRAM supports a differential data strobe only and does not support a single-ended
data strobe.
ALERT_n
Output
Output
Alert output: This signal allows the DRAM to indicate to the system's memory con-
troller that a specific alert or event has occurred. Alerts will include the command/
address parity error and the CRC data error when either of these functions is enabled
in the mode register.
TDQS_t,
TDQS_c
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When
enabled via the mode register, the DRAM will enable the same RTT termination resist-
ance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS
function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA
MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be dis-
abled in the mode register for both the x4 and x16 configurations. The DM function
is supported only in x8 and x16 configurations.
VDD
VDDQ
VPP
Supply
Supply
Supply
Supply
Supply
Supply
Power supply: 1.2V 0.060V.
DQ power supply: 1.2V 0.060V.
DRAM activating power supply: 2.5V –0.125V/+0.250V.
Reference voltage for control, command, and address pins.
Ground.
VREFCA
VSS
VSSQ
ZQ
DQ ground.
Reference Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor
(RZQ), which is tied to VSSQ
.
RFU
NC
NF
–
–
–
Reserved for future use.
No connect: No internal electrical connection is present.
No function: May have internal connection present but has no function.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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© 2016 Micron Technology, Inc. All rights reserved.
25
8Gb: x8, x16 Automotive DDR4 SDRAM
Package Dimensions
Package Dimensions
Figure 6: 78-Ball FBGA – x4, x8 (WE)
0.155
Seating plane
0.12 A
A
1.8 CTR
nonconductive
overmold
78X Ø0.47
Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
Ball A1 ID
9
8
7
3 2 1
A
B
C
D
E
12 0.1
F
G
H
J
9.6 CTR
K
L
M
N
0.8 TYP
0.8 TYP
6.4 CTR
1.1 0.1
0.34 0.05
8
0.1
1. All dimensions are in millimeters.
Notes:
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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© 2016 Micron Technology, Inc. All rights reserved.
26
8Gb: x8, x16 Automotive DDR4 SDRAM
Package Dimensions
Figure 7: 96-Ball FBGA – x16 (JY)
0.155
Seating plane
0.12 A
A
1.8 CTR
Nonconductive
overmold
96X Ø0.47
Dimensions apply
to solder balls post-
reflow on Ø0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
Ball A1 ID
9
8
7
3
2 1
A
B
C
D
E
F
G
H
J
14 0.1
12 CTR
K
L
M
N
P
R
T
0.8 TYP
1.1 0.1
0.8 TYP
6.4 CTR
8 0.1
0.34 0.05
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
Notes:
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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© 2016 Micron Technology, Inc. All rights reserved.
27
8Gb: x8, x16 Automotive DDR4 SDRAM
State Diagram
State Diagram
This si0plified state diagra0 provides an overview of the possible state transitions and
the co00ands to control the0. Situations involving 0ore than one bank, the enabling
or disabling of on-die ter0ination, and so0e other events are not captured in full de-
tail.
Figure 8: Simplified State Diagram
IV
,
REFDQ
RTT, and
so on
MPSM
RESET
SRX* = SRX with NOP
From any state
SRX*
CKE_L
MRS
SRX*
Power
applied
MRS, MPR,
write leveling,
Reset
procedure
Self
refresh
PDA
mode
V
training
Power-On
RESET
Initialization
REFDQ
TEN = 1
TEN = 1
MRS
MRS
SRX
ZQCL
SRE
MRS
Connectivity
test
ZQ
calibration
ZQCL,ZQCS
REF
Idle
ACT
Refreshing
TEN = 0
RESET
PDE
CKE_L
CKE_L
PDX
Active
power-
down
Precharge
power-
down
Activating
PDX
PDE
Bank
active
WRITE
READ
READ
WRITE
WRITE A
WRITE
READ A
READ
Reading
READ A
Writing
WRITE A
WRITE A
READ A
PRE, PREA
PRE, PREA
Writing
Reading
PRE, PREA
Precharging
Automatic
sequence
Command
sequence
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8Gb: x8, x16 Automotive DDR4 SDRAM
State Diagram
Table 4: State Diagram Command Definitions
Command
ACT
Description
Active
MPR
Multipurpose register
Mode register set
Enter power-down
Exit power-down
MRS
PDE
PDX
PRE
Precharge
PREA
READ
READ A
REF
Precharge all
RD, RDS4, RDS8
RDA, RDAS4, RDAS8
Refresh, fine granularity refresh
Start reset procedure
Self refresh entry
RESET
SRE
SRX
Self refresh exit
TEN
Boundary scan mode enable
WR, WRS4, WRS8 with/without CRC
WRITE
WRITE A
ZQCL
ZQCS
WRA, WRAS4, WRAS8 with/without CRC
ZQ calibration long
ZQ calibration short
1. See the Command Truth Table for more details.
Note:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Functional Description
Functional Description
The DDR4 SDRAM is a high-speed dyna0ic rando0-access 0e0ory internally config-
ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi-
ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x1±
devices. The device uses double data rate (DDR) architecture to achieve high-speed op-
eration. DDR4 architecture is essentially an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for a device 0odule effectively consists of a single 8n-bit-wide, four-clock-
cycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-
half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected lo-
cation and continue for a burst length of eight or a chopped burst of four in a progra0-
0ed sequence. Operation begins with the registration of an ACTIVE co00and, which is
then followed by a READ or WRITE co00and. The address bits registered coincident
with the ACTIVE co00and are used to select the bank and row to be accessed (BG[1:6]
select the bank group for x4/x8, and BG6 selects the bank group for x1±; BA[1:6] select
the bank, and A[17:6] select the row. See the Addressing section for 0ore details). The
address bits registered coincident with the READ or WRITE co00and are used to select
the starting colu0n location for the burst operation, deter0ine if the auto PRECHARGE
co00and is to be issued (via A16), and select BC4 or BL8 0ode on-the-fly (OTF) (via
A12) if enabled in the 0ode register.
Prior to nor0al operation, the device 0ust be powered up and initialized in a prede-
fined 0anner. The following sections provide detailed infor0ation covering device reset
and initialization, register definition, co00and descriptions, and device operation.
NOTE: The use of the NOP co00and is allowed only when exiting 0axi0u0 power
saving 0ode or when entering gear-down 0ode.
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8Gb: x8, x16 Automotive DDR4 SDRAM
RESET and Initialization Procedure
RESET and Initialization Procedure
To ensure proper device function, the power-up and reset initialization default values
for the following 0ode register (MR) settings are defined as:
• Gear-down 0ode (MR3 A[3]): 6 = 1/2 rate
• Per-DRAM addressability (MR3 A[4]): 6 = disable
• Maxi0u0 power-saving 0ode (MR4 A[1]): 6 = disable
• CS to co00and/address latency (MR4 A[8:±]): 666 = disable
• CA parity latency 0ode (MR5 A[2:6]): 666 = disable
• Hard post package repair 0ode (MR4 A[13]): 6 = disable
• Soft post package repair 0ode (MR4 A[5]): 6 = disable
Power-Up and Initialization Sequence
The following sequence is required for power-up and initialization:
1. Apply power (RESET_n and TEN should be 0aintained below 6.2 × VDD while sup-
plies ra0p up; all other inputs 0ay be undefined). When supplies have ra0ped to
a valid stable level, RESET_n 0ust be 0aintained below 6.2 × VDD for a 0ini0u0
of tPW_RESET_L and TEN 0ust be 0aintained below 6.2 × VDD for a 0ini0u0 of
766μs. CKE is pulled LOW anyti0e before RESET_n is de-asserted (0ini0u0 ti0e
of 16ns). The power voltage ra0p ti0e between 3660V to VDD,0in 0ust be no
greater than 2660s, and during the ra0p, VDD 0ust be greater than or equal to
VDDQ and (VDD - VDDQ) < 6.3V. VPP 0ust ra0p at the sa0e ti0e or before VDD, and
VPP 0ust be equal to or higher than VDD at all ti0es. After VDD has ra0ped and
reached the stable level and after RESET_n goes high, the initialization sequence
0ust be started within 3 seconds. For debug purposes, the 3 second delay li0it
0ay be extended to ±6 0inutes provided the DRAM is operated in this debug
0ode for no 0ore than 3±6 cu0ulative hours.
During power-up, the supply slew rate is governed by the li0its stated in the table
below and either condition A or condition B listed below 0ust be 0et.
Table 5: Supply Power-up Slew Rate
Symbol
Min
Max Unit Comment
VDD_SL, VDDQ_SL,
VPP_SL
0.004
600
200
200
V/ms Measured between 300mV and 80% of
supply minimum
VDD_ona
N/A
N/A
ms VDD maximum ramp time from 300mV to
VDD minimum
VDDQ_ona
ms VDDQ maximum ramp time from 300mV
to VDDQ minimum
1. 20 MHz band-limited measurement.
Note:
• Condition A:
– Apply VPP without any slope reversal before or at the sa0e ti0e as VDD and
VDDQ
.
– VDD and VDDQ are driven fro0 a single-power converter output and apply
VDD/VDDQ without any slope reversal before or at the sa0e ti0e as VTT and
VREFCA
.
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8Gb: x8, x16 Automotive DDR4 SDRAM
RESET and Initialization Procedure
– The voltage levels on all balls other than VDD, VDDQ, VSS, and VSSQ 0ust be less
than or equal to VDDQ and VDD on one side and 0ust be greater than or equal
to VSSQ and VSS on the other side.
– VTT is li0ited to 6.7±V MAX when the power ra0p is co0plete.
– VREFCA tracks VDD/2.
• Condition B:
– Apply VPP without any slope reversal before or at the sa0e ti0e as VDD
– Apply VDD without any slope reversal before or at the sa0e ti0e as VDDQ
– Apply VDDQ without any slope reversal before or at the sa0e ti0e as VTT and
VREFCA
.
.
.
– The voltage levels on all pins other than VPP, VDD, VDDQ, VSS, and VSSQ 0ust be
less than or equal to VDDQ and VDD on one side and 0ust be larger than or
equal to VSSQ and VSS on the other side.
2. After RESET_n is de-asserted, wait for another 566μs but no longer then 3 seconds
until CKE beco0es active. During this ti0e, the device will start internal state ini-
tialization; this will be done independently of external clocks. A reasonable at-
te0pt was 0ade in the design to power up with the following default MR settings:
gear-down 0ode (MR3 A[3]): 6 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 6
= disable; 0axi0u0 power-down (MR4 A[1]): 6 = disable; CS to co00and/
address latency (MR4 A[8:±]): 666 = disable; CA parity latency 0ode (MR5 A[2:6]):
666 = disable. However, it should be assu0ed that at power up the MR settings are
undefined and should be progra00ed as shown below.
3. Clocks (CK_t, CK_c) need to be started and stabilized for at least 16ns or 5 tCK
(whichever is larger) before CKE goes active. Because CKE is a synchronous signal,
the corresponding setup ti0e to clock (tIS) 0ust be 0et. Also, a DESELECT co0-
0and 0ust be registered (with tIS setup ti0e to clock) at clock edge Td. After the
CKE is registered HIGH after RESET, CKE needs to be continuously registered
HIGH until the initialization sequence is finished, including expiration of tDLLK
and tZQinit.
4. The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,
the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is
registered HIGH. The ODT input signal 0ay be in an undefined state until tIS be-
fore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal
0ay be statically held either LOW or HIGH. If RTT(NOM) is to be enabled in MR1,
the ODT input signal 0ust be statically held LOW. In all cases, the ODT input sig-
nal re0ains static until the power-up initialization sequence is finished, including
the expiration of tDLLK and tZQinit.
5. After CKE is registered HIGH, wait a 0ini0u0 of RESET CKE EXIT ti0e, tXPR, be-
fore issuing the first MRS co00and to load 0ode register (tXPR = MAX (tXS, 5 ×
tCK).
±. Issue MRS co00and to load MR3 with all application settings, wait tMRD.
7. Issue MRS co00and to load MR± with all application settings, wait tMRD.
8. Issue MRS co00and to load MR5 with all application settings, wait tMRD.
9. Issue MRS co00and to load MR4 with all application settings, wait tMRD.
16. Issue MRS co00and to load MR2 with all application settings, wait tMRD.
11. Issue MRS co00and to load MR1 with all application settings, wait tMRD.
12. Issue MRS co00and to load MR6 with all application settings, wait tMOD.
13. Issue a ZQCL co00and to start ZQ calibration.
14. Wait for tDLLK and tZQinit to co0plete.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
RESET and Initialization Procedure
15. The device will be ready for nor0al operation. Once the DRAM has been initial-
ized, if the DRAM is in an idle state longer than 9±60s, then either (a) REF co0-
0ands 0ust be issued within tREFI constraints (specification for posting allowed)
or (b) CKE or CS_n 0ust toggle once within every 9±60s interval of idle ti0e. For
debug purposes, the 9±60s delay li0it 0aybe extended to ±6 0inutes provided
the DRAM is operated in this debug 0ode for no 0ore than 3±6 cu0ulative hours.
A stable valid VDD level is a set DC level (6Hz to 256 KHz) and 0ust be no less than
VDD,0in and no greater than VDD,0ax. If the set DC level is altered anyti0e after initializa-
tion, the DLL reset and calibrations 0ust be perfor0ed again after the new set DC level
is stable. AC noise of ±±60V (greater than 256 KHz) is allowed on VDD provided the
noise doesn't alter VDD to less than VDD,0in or greater than VDD,0ax
.
A stable valid VDDQ level is a set DC level (6Hz to 256 KHz) and 0ust be no less than
VDDQ,0in and no greater than VDDQ,0ax. If the set DC level is altered anyti0e after initial-
ization, the DLL reset and calibrations 0ust be perfor0ed again after the new set DC
level is stable. AC noise of ±±60V (greater than 256 KHz) is allowed on VDDQ provided
the noise doesn't alter VDDQ to less than VDDQ,0in or greater than VDDQ,0ax
.
A stable valid VPP level is a set DC level (6Hz to 256 KHz) and 0ust be no less than
VPP,0in and no greater than VPP,0ax. If the set DC level is altered anyti0e after initializa-
tion, the DLL reset and calibrations 0ust be perfor0ed again after the new set DC level
is stable. AC noise of ±1260V (greater than 256KHz) is allowed on VPP provided the
noise doesn't alter VPP to less than VPP,0in or greater than VPP,0ax
.
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RESET and Initialization Procedure
Figure 9: RESET and Initialization Sequence at Power-On Ramping
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD, VDDQ
tPW_RESET_L
T = 500μs
RESET_n
CKE
tIS
T (MIN) = 10ns
Valid
tDLLK
ZQCL
tZQinit
Note 1
tXPR
tMRD
tMOD
tMRD
tMRD
tIS
Note 1
Command
BG, BA
MRS
MRx
MRS
MRx
MRS
MRx
MRS
MRx
Valid
Valid
tIS
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
Valid
ODT
RTT
Time Break
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
Notes:
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for de-
pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
RESET Initialization with Stable Power Sequence
The following sequence is required for RESET at no power interruption initialization:
1. Assert RESET_n below 6.2 × VDD any ti0e reset is needed (all other inputs 0ay be
undefined). RESET 0ust be 0aintained for a 0ini0u0 of 166ns. CKE is pulled
LOW before RESET_n is de-asserted (0ini0u0 ti0e 16ns).
2. Follow Steps 2 to 16 in the Reset and Initialization Sequence at Power-on Ra0ping
procedure.
When the reset sequence is co0plete, all counters except the refresh counters have
been reset and the device is ready for nor0al operation.
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RESET and Initialization Procedure
Figure 10: RESET Procedure at Power Stable Condition
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD, VDDQ
tPW_RESET_S
T = 500μs
RESET_n
CKE
tIS
T (MIN) = 10ns
Valid
tDLLK
ZQCL
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
Note 1
tIS
Note 1
Command
BG, BA
MRS
MRx
MRS
MRx
MRS
MRx
MRS
MRx
Valid
Valid
tIS
tIS
Valid
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
ODT
RTT
Time Break
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
Notes:
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for de-
pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
Uncontrolled Power-Down Sequence
In the event of an uncontrolled ra0ping down of VPP supply, VPP is allowed to be less
than VDD provided the following conditions are 0et:
• Condition A: VPP and VDD/VDDQ are ra0ping down (as part of turning off) fro0 nor-
0al operating levels.
• Condition B: The a0ount that VPP 0ay be less than VDD/VDDQ is less than or equal to
5660V.
• Condition C: The ti0e VPP 0ay be less than VDD is 160s per occurrence with a total
accu0ulated ti0e in this state 1660s.
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Programming Mode Registers
• Condition D: The ti0e VPP 0ay be less than 2.6V and above VSS while turning off is
150s per occurrence with a total accu0ulated ti0e in this state 1560s.
Programming Mode Registers
For application flexibility, various functions, features, and 0odes are progra00able in
seven 0ode registers (MRn) provided by the device as user defined variables that 0ust
be progra00ed via a MODE REGISTER SET (MRS) co00and. Because the default val-
ues of the 0ode registers are not defined, contents of 0ode registers 0ust be fully ini-
tialized and/or re-initialized; that is, they 0ust be written after power-up and/or reset
for proper operation. The contents of the 0ode registers can be altered by re-executing
the MRS co00and during nor0al operation. When progra00ing the 0ode registers,
even if the user chooses to 0odify only a sub-set of the MRS fields, all address fields
within the accessed 0ode register 0ust be redefined when the MRS co00and is is-
sued. MRS and DLL RESET co00ands do not affect array contents, which 0eans these
co00ands can be executed any ti0e after power-up without affecting the array con-
tents.
The MRS co00and cycle ti0e, tMRD, is required to co0plete the WRITE operation to
the 0ode register and is the 0ini0u0 ti0e required between the two MRS co00ands
shown in the tMRD Ti0ing figure.
So0e of the 0ode register settings affect address/co00and/control input functionali-
ty. In these cases, the next MRS co00and can be allowed when the function being up-
dated by the current MRS co00and is co0pleted. These MRS co00ands don’t apply
tMRD ti0ing to the next MRS co00and; however, the input cases have unique MR set-
ting procedures, so refer to individual function descriptions:
• Gear-down 0ode
• Per-DRAM addressability
• Maxi0u0 power saving 0ode
• CS to co00and/address latency
• CA parity latency 0ode
• VREFDQ training value
• VREFDQ training 0ode
• VREFDQ training range
So0e 0ode register settings 0ay not be supported because they are not required by
certain speed bins.
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Programming Mode Registers
Figure 11: tMRD Timing
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
CK_c
CK_t
MRS2
Valid
DES
DES
DES
DES
DES
Valid
Valid
MRS2
Valid
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
CKE
tMRD
Old settings
Updating settings
Settings
Don’t Care
Time Break
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMRD applies to all MRS commands with the following exceptions:
Notes:
Gear-down mode
CA parity mode
CAL mode
Per-DRAM addressability mode
V
REFDQ training value, VREFDQ training mode, and VREFDQ training range
The MRS co00and to nonMRS co00and delay, tMOD, is required for the DRAM to
update features, except for those noted in note 2 in figure below where the individual
function descriptions 0ay specify a different require0ent. tMOD is the 0ini0u0 ti0e
required fro0 an MRS co00and to a nonMRS co00and, excluding DES, as shown in
the tMOD Ti0ing figure.
Figure 12: tMOD Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
CK_c
CK_t
Command
Valid
Valid
Valid
Valid
Valid
Valid
MRS2
Valid
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
CKE
tMOD
Old settings
Updating settings
New settings
Settings
Don’t Care
Time Break
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode
Notes:
V
REFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQ
training range
Maximum power savings mode , Per-DRAM addressability mode, and CA parity mode
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Programming Mode Registers
The 0ode register contents can be changed using the sa0e co00and and ti0ing re-
quire0ents during nor0al operation as long as the device is in idle state; that is, all
banks are in the precharged state with tRP satisfied, all data bursts are co0pleted, and
CKE is HIGH prior to writing into the 0ode register. If the RTT(NOM) feature is enabled in
the 0ode register prior to and/or after an MRS co00and, the ODT signal 0ust contin-
uously be registered LOW, ensuring RTT is in an off state prior to the MRS co00and.
The ODT signal 0ay be registered HIGH after tMOD has expired. If the RTT(NOM) feature
is disabled in the 0ode register prior to and after an MRS co00and, the ODT signal
can be registered either LOW or HIGH before, during, and after the MRS co00and. The
0ode registers are divided into various fields depending on functionality and 0odes.
In so0e 0ode register setting cases, function updating takes longer than tMOD. This
type of MRS does not apply tMOD ti0ing to the next valid co00and, excluding DES.
These MRS co00and input cases have unique MR setting procedures, so refer to indi-
vidual function descriptions.
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Mode Register 0
Mode Register 0
Mode register 6 (MR6) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR6 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR6 Register
Definition table.
Table 6: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 7: MR0 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13,11:9
WR (WRITE recovery)/RTP (READ-to-PRECHARGE)
0000 = 10 / 5 clocks1
0001 = 12 / 6 clocks
0010 = 14 / 7 clocks1
0011 = 16 / 8 / clocks
0100 = 18 / 9 clocks1
0101 = 20 /10 clocks
0110 = 24 / 12 clocks
0111 = 22 / 11 clocks1
1000 = 26 / 13 clocks1
1001 = 28 / 14 clocks2
1010 through 1111 = Reserved
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 0
Table 7: MR0 Register Definition (Continued)
Mode
Register Description
8
DLL reset
0 = No
1 = Yes
7
Test mode (TM) – Manufacturer use only
0 = Normal operating mode, must be programmed to 0
12, 6:4, 2 CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out
00000 = 9 clocks1
00001 = 10 clocks
00010 = 11 clocks1
00011 = 12 clocks
00100 = 13 clocks1
00101 = 14 clocks
00110 = 15 clocks1
00111 = 16 clocks
01000 = 18 clocks
01001 = 20 clocks
01010 = 22 clocks
01011 = 24 clocks
01100 = 23 clocks1
01101 = 17 clocks1
01110 = 19 clocks1
01111 = 21 clocks 1
10000 = 25 clocks (3DS use only)
10001 = 26 clocks
10010 = 27 clocks (3DS use only)
10011 = 28 clocks
10100 = 29 clocks1
10101 = 30 clocks
10110 = 31 clocks1
10111 = 32 clocks
3
Burst type (BT) – Data burst ordering within a READ or WRITE burst access
0 = Nibble sequential
1 = Interleave
1:0
Burst length (BL) – Data burst size associated with each read or write access
00 = BL8 (fixed)
01 = BC4 or BL8 (on-the-fly)
10 = BC4 (fixed)
11 = Reserved
1. Not allowed when 1/4 rate gear-down mode is enabled.
Notes:
2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28
clocks and RTP should be set to 14 clocks.
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Mode Register 0
Burst Length, Type, and Order
Accesses within a given burst 0ay be progra00ed to sequential or interleaved order.
The ordering of accesses within a burst is deter0ined by the burst length, burst type,
and the starting colu0n address as shown in the following table. Burst length options
include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec-
ted coincidentally with the registration of a READ or WRITE co00and via A12/BC_n.
Table 8: Burst Type and Burst Order
Note 1 applies to the entire table
Starting
Column Address Burst Type = Sequential
Burst
READ/
WRITE
Burst Type = Interleaved
(Decimal)
Length
(A[2, 1, 0])
(Decimal)
Notes
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
BC4
READ
0 0 0
0, 1, 2, 3, T, T, T, T
1, 2, 3, 0, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 0, 1, 2, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 6, 7, 4, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 4, 5, 6, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 4, 7, 6, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 6, 5, 4, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
WRITE
READ
0, V, V
1, V, V
0 0 0
BL8
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
WRITE
V, V, V
3
1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
Notes:
2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts
two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and
tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in-
ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during
column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting
point for tWR and tWTR will not be pulled in by two clocks as described in the BC4
(fixed) case.
3. T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X = “Don’t Care.”
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Mode Register 0
CAS Latency
Test Mode
The CAS latency (CL) setting is defined in the MR6 Register Definition table. CAS laten-
cy is the delay, in clock cycles, between the internal READ co00and and the availability
of the first bit of output data. The device does not support half-clock latencies. The
overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL +
CL.
The nor0al operating 0ode is selected by MR6[7] and all other bits set to the desired
values shown in the MR6 Register Definition table. Progra00ing MR6[7] to a value of 1
places the device into a DRAM 0anufacturer-defined test 0ode to be used only by the
0anufacturer, not by the end user. No operations or functionality is specified if MR6[7]
= 1.
Write Recovery(WR)/READ-to-PRECHARGE
The progra00ed write recovery (WR) value is used for the auto precharge feature along
with tRP to deter0ine tDAL. WR for auto precharge (MIN) in clock cycles is calculated
by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR (MIN)
cycles = roundup (tWR[ns]/tCK[ns]). The WR value 0ust be progra00ed to be equal to
or larger than tWR (MIN). When both DM and write CRC are enabled in the 0ode regis-
ter, the device calculates CRC before sending the write data into the array; tWR values
will change when enabled. If there is a CRC error, the device blocks the WRITE opera-
tion and discards the data.
Internal READ-to-PRECHARGE (RTP) co00and delay for auto precharge (MIN) in
clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the
next integer: RTP (MIN) cycles = roundup (tRTP[ns]/tCK[ns]). The RTP value in the
0ode register 0ust be progra00ed to be equal to or larger than RTP (MIN). The pro-
gra00ed RTP value is used with tRP to deter0ine the ACT ti0ing to the sa0e bank.
DLL RESET
The DLL reset bit is self-clearing, 0eaning that it returns to the value of 6 after the DLL
RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET
should be applied. Any ti0e the DLL RESET function is used, tDLLK 0ust be 0et before
functions requiring the DLL can be used, such as READ co00ands or synchronous
ODT operations, for exa0ple,).
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Mode Register 1
Mode Register 1
Mode register 1 (MR1) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR1 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR1 Register
Definition table.
Table 9: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 10: MR1 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
12
11
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
Data output disable (Qoff) – Output buffer disable
0 = Enabled (normal operation)
1 = Disabled (both ODI and RTT)
Termination data strobe (TDQS) – Additional termination pins (x8 configuration only)
0 = TDQS disabled
1 = TDQS enabled
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Mode Register 1
Table 10: MR1 Register Definition (Continued)
Mode
Register Description
10, 9, 8
Nominal ODT (RTT(NOM) – Data bus termination setting
000 = RTT(NOM) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
7
Write leveling (WL) – Write leveling mode
0 = Disabled (normal operation)
1 = Enabled (enter WL mode)
6, 5
4, 3
RFU
0 = Must be programmed to 0
1 = Reserved
Additive latency (AL) – Command additive latency setting
00 = 0 (AL disabled)
01 = CL - 11
10 = CL - 2
11 = Reserved
2, 1
Output driver impedance (ODI) – Output driver impedance setting
00 = RZQ/7 (34 ohm)
01 = RZQ/5 (48 ohm)
10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm)
11 = Reserved
0
DLL enable – DLL enable feature
0 = DLL disabled
1 = DLL enabled (normal operation)
1. Not allowed when 1/4 rate gear-down mode is enabled.
Note:
DLL Enable/DLL Disable
The DLL 0ust be enabled for nor0al operation and is required during power-up initial-
ization and upon returning to nor0al operation after having the DLL disabled. During
nor0al operation (DLL enabled with MR1[6]) the DLL is auto0atically disabled when
entering the SELF REFRESH operation and is auto0atically re-enabled upon exit of the
SELF REFRESH operation. Any ti0e the DLL is enabled and subsequently reset, tDLLK
clock cycles 0ust occur before a READ or SYNCHRONOUS ODT co00and can be is-
sued to allow ti0e for the internal clock to be synchronized with the external clock. Fail-
ing to wait for synchronization to occur 0ay result in a violation of the tDQSCK, tAON,
or tAOF para0eters.
During tDLLK, CKE 0ust continuously be registered HIGH. The device does not require
DLL for any WRITE operation, except when RTT(WR) is enabled and the DLL is required
for proper ODT operation.
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Mode Register 1
The direct ODT feature is not supported during DLL off 0ode. The ODT resistors 0ust
be disabled by continuously registering the ODT pin LOW and/or by progra00ing the
RTT(NOM) bits MR1[9,±,2] = 666 via an MRS co00and during DLL off 0ode.
The dyna0ic ODT feature is not supported in DLL off 0ode; to disable dyna0ic ODT
externally, use the MRS co00and to set RTT(WR), MR2[16:9] = 66.
Output Driver Impedance Control
The output driver i0pedance of the device is selected by MR1[2,1], as shown in the MR1
Register Definition table.
ODT RTT(NOM) Values
The device is capable of providing three different ter0ination values: RTT(Park), RTT(NOM)
and RTT(WR). The no0inal ter0ination value, RTT(NOM), is progra00ed in MR1. A sepa-
rate value, RTT(WR), 0ay be progra00ed in MR2 to enable a unique RTT value when
ODT is enabled during WRITE operations. The RTT(WR) value can be applied during
WRITE co00ands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is pro-
gra0ed in MR5. RTT(Park) provides a ter0ination value when the ODT signal is LOW.
,
Additive Latency
The ADDITIVE LATENCY (AL) operation is supported to 0ake co00and and data
buses efficient for sustainable bandwidths in the device. In this operation, the device al-
lows a READ or WRITE co00and (either with or without auto precharge) to be issued
i00ediately after the ACTIVATE co00and. The co00and is held for the ti0e of AL be-
fore it is issued inside the device. READ latency (RL) is controlled by the su0 of the AL
and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the su0 of
the AL and CAS WRITE latency (CWL) register settings.
Table 11: Additive Latency (AL) Settings
A4
0
A3
0
AL
0 (AL disabled)
CL - 1
0
1
1
0
CL - 2
1
1
Reserved
1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 regis-
ter.
Note:
Write Leveling
For better signal integrity, the device uses fly-by topology for the co00ands, addresses,
control signals, and clocks. Fly-by topology benefits fro0 a reduced nu0ber of stubs
and their lengths, but it causes flight-ti0e skew between clock and strobe at every
DRAM on the DIMM. This 0akes it difficult for the controller to 0aintain tDQSS, tDSS,
and tDSH specifications. Therefore, the device supports a write leveling feature that al-
lows the controller to co0pensate for skew.
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Mode Register 1
Output Disable
The device outputs 0ay be enabled/disabled by MR1[12] as shown in the MR1 Register
Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ
and DQS) are disconnected fro0 the device, which re0oves any loading of the output
drivers. For exa0ple, this feature 0ay be useful when 0easuring 0odule power. For
nor0al operation, set MR1[12] to 6.
Termination Data Strobe
Ter0ination data strobe (TDQS) is a feature of the x8 device and provides additional
ter0ination resistance outputs that 0ay be useful in so0e syste0 configurations. Be-
cause this function is available only in a x8 configuration, it 0ust be disabled for x4 and
x1± configurations.
While TDQS is not supported in x4 or x1± configurations, the sa0e ter0ination resist-
ance function that is applied to the TDQS pins is applied to the DQS pins when enabled
via the 0ode register.
The TDQS, DBI, and DATA MASK (DM) functions share the sa0e pin. When the TDQS
function is enabled via the 0ode register, the DM and DBI functions are not supported.
When the TDQS function is disabled, the DM and DBI functions can be enabled sepa-
rately.
Table 12: TDQS Function Matrix
TDQS
Data Mask (DM)
Enabled
WRITE DBI
Disabled
Enabled
Disabled
Disabled
READ DBI
Disabled
Enabled or disabled
Enabled or disabled
Enabled or disabled
Disabled
Disabled
Disabled
Enabled
Disabled
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 2
Mode Register 2
Mode register 2 (MR2) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR2 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR2 Register
Definition table.
Table 13: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 14: MR2 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
12
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
WRITE data bus CRC
0 = Disabled
1 = Enabled
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 2
Table 14: MR2 Register Definition (Continued)
Mode
Register Description
11:9
Dynamic ODT (RTT(WR)) – Data bus termination setting during WRITEs
000 = RTT(WR) disabled (WRITE does not affect RTT value)
001 = RZQ/2 (120 ohm)
010 = RZQ/1 (240 ohm)
011 = High-Z
100 = RZQ/3 (80 ohm)
101 = Reserved
110 = Reserved
111 = Reserved
7:6
5:3
Low-power auto self refresh (LPASR) – Mode summary
00 = Manual mode - Normal operating temperature range (TC: –40°C–85°C)
01 = Manual mode - Reduced operating temperature range (TC: –40°C–45°C)
10 = Manual mode - Extended operating temperature range (TC: –40°C–125°C)
11 = ASR mode - Automatically switching among all modes
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
1tCK WRITE preamble
000 = 9 (DDR4-1600)1
001 = 10 (DDR4-1866)
010 = 11 (DDR4-2133/1600)1
011 = 12 (DDR4-2400/1866)
100 = 14 (DDR4-2666/2133)
101 = 16 (DDR4-2933,3200/2400)
110 = 18 (DDR4-2666)
111 = 20 (DDR4-2933, 3200)
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
2tCK WRITE preamble
000 = N/A
001 = N/A
010 = N/A
011 = N/A
100 = 14 (DDR4-2400)
101 = 16 (DDR4-2666/2400)
110 = 18 (DDR4-2933, 3200/2666)
111 = 20 (DDR4-2933, 3200)
8, 2
1:0
RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
1. Not allowed when 1/4 rate gear-down mode is enabled.
Note:
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Mode Register 2
CAS WRITE Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Defini-
tion table. CWL is the delay, in clock cycles, between the internal WRITE co00and and
the availability of the first bit of input data. The device does not support any half-clock
latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity la-
tency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.
Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring
SELF REFRESH operation over different te0perature ranges can use this feature to opti-
0ize the IDD± current for a given te0perature range as specified in the MR2 Register
Definition table.
Dynamic ODT
In certain applications and to further enhance signal integrity on the data bus, it is de-
sirable to change the ter0ination strength of the device without issuing an MRS co0-
0and. This 0ay be done by configuring the dyna0ic ODT (RTT(WR)) settings in
MR2[11:9]. In write leveling 0ode, only RTT(NOM) is available.
Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added
to the device. When enabled via the 0ode register, the data transfer size goes fro0 the
nor0al 8-bit (BL8) fra0e to a larger 16-bit UI fra0e, and the extra two UIs are used for
the CRC infor0ation.
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Mode Register 3
Mode Register 3
Mode register 3 (MR3) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR3 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR3 Register
Definition table.
Table 15: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 16: MR3 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
12:11
Multipurpose register (MPR) – Read format
00 = Serial
01 = Parallel
10 = Staggered
11 = Reserved
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 3
Table 16: MR3 Register Definition (Continued)
Mode
Register Description
10:9
WRITE CMD latency when CRC/DM enabled
00 = 4CK (DDR4-1600)
01 = 5CK (DDR4-1866/2133/2400/2666)
10 = 6CK (DDR4-2933/3200)
11 = Reserved
8:6
Fine granularity refresh mode
000 = Normal mode (fixed 1x)
001 = Fixed 2x
010 = Fixed 4x
011 = Reserved
100 = Reserved
101 = On-the-fly 1x/2x
110 = On-the-fly 1x/4x
111 = Reserved
5
4
Temperature sensor status
0 = Disabled
1 = Enabled
Per-DRAM addressability
0 = Normal operation (disabled)
1 = Enable
3
Gear-down mode – Ratio of internal clock to external data rate
0 = [1:1]; (1/2 rate data)
1 = [2:1]; (1/4 rate data)
2
Multipurpose register (MPR) access
0 = Normal operation
1 = Data flow from MPR
1:0
MPR page select
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3 (restricted for DRAM manufacturer use only)
Multipurpose Register
The 0ultipurpose register (MPR) is used for several features:
• Readout of the contents of the MRn registers
• WRITE and READ syste0 patterns used for data bus calibration
• Readout of the error fra0e when the co00and address parity feature is enabled
To enable MPR, issue an MRS co00and to MR3[2] = 1. MR3[12:11] define the for0at of
read data fro0 the MPR. Prior to issuing the MRS co00and, all banks 0ust be in the
idle state (all banks precharged and tRP 0et). After MPR is enabled, any subsequent RD
or RDA co00ands will be redirected to a specific 0ode register.
The 0ode register location is specified with the READ co00and using address bits. The
MR is split into upper and lower halves to align with a burst length li0itation of 8. Pow-
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Mode Register 3
er-down 0ode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA co0-
0ands are not allowed during MPR 0ode. The RESET function is supported during
MPR 0ode, which requires device re-initialization.
WRITE Command Latency When CRC/DM is Enabled
The WRITE co00and latency (WCL) 0ust be set when both write CRC and DM are en-
abled for write CRC persistent 0ode. This provides the extra ti0e required when co0-
pleting a WRITE burst when write CRC and DM are enabled. This 0eans at data rates
less than or equal to 1±66 MT/s then 4nCK is used, 5nCK or ±nCK are not allowed; at
data rates greater than 1±66 MT/s and less than or equal to 2±±± MT/s then 5nCK is
used, 4nCK or ±nCK are not allowed; and at data rates greater than 2±±± MT/s and less
than or equal to 3266 MT/s then ±nCK is used; 4nCK or 5nCK are not allowed.
Fine Granularity Refresh Mode
This 0ode had been added to DDR4 to help co0bat the perfor0ance penalty due to
refresh lockout at high densities. Shortening tRFC and increasing cycle ti0e allows 0ore
accesses to the chip and can produce higher bandwidth.
Temperature Sensor Status
This 0ode directs the DRAM to update the te0perature sensor status at MPR Page 2,
MPR6 [4,3]. The te0perature sensor setting should be updated within 320s; when an
MPR read of the te0perature sensor status bits occurs, the te0perature sensor status
should be no older than 320s.
Per-DRAM Addressability
This 0ode allows co00ands to be 0asked on a per device basis providing any device
in a rank (devices sharing the sa0e co00and and address signals) to be progra00ed
individually. As an exa0ple, this feature can be used to progra0 different ODT or VREF
values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock 0ode and uses a low frequency MRS co0-
0and followed by a sync pulse to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) 0ode. For operation in 1/2 rate 0ode,
no MRS co00and or sync pulse is required.
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Mode Register 4
Mode Register 4
Mode register 4 (MR4) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR4 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR4 Register
Definition table.
Table 17: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.
Note:
Table 18: MR4 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
12
11
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
Hard Post Package Repair (hPPR mode)
0 = Disabled
1 = Enabled
WRITE preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle
READ preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at
least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 4
Table 18: MR4 Register Definition (Continued)
Mode
Register Description
10
READ preamble training
0 = Disabled
1 = Enabled
9
Self refresh abort mode
0 = Disabled
1 = Enabled
8:6
CMD (CAL) address latency
000 = 0 clocks (disabled)
001 =3 clocks1
010 = 4 clocks
011 = 5 clocks1
100 = 6 clocks
101 = 8 clocks
110 = Reserved
111 = Reserved
5
4
3
2
1
0
soft Post Package Repair (sPPR mode)
0 = Disabled
1 = Enabled
Internal VREF monitor
0 = Disabled
1 = Enabled
Temperature controlled refresh mode
0 = Disabled
1 = Enabled
Temperature controlled refresh range
0 = Normal temperature mode
1 = Extended temperature mode
Maximum power savings mode
0 = Normal operation
1 = Enabled
RFU
0 = Must be programmed to 0
1 = Reserved
1. Not allowed when 1/4 rate gear-down mode is enabled.
Note:
Hard Post Package Repair Mode
The hard post package repair (hPPR) 0ode feature is JEDEC optional for 4Gb DDR4
0e0ories. Perfor0ing an MPR read to page 2 MPR6 [7] indicates whether hPPR 0ode is
available (A7 = 1) or not available (A7 = 6). hPPR 0ode provides a si0ple and easy repair
0ethod of the device after placed in the syste0. One row per bank can be repaired. The
repair process is irrevocable so great care should be exercised when using.
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Mode Register 4
Soft Post Package Repair Mode
The soft post package repair (sPPR) 0ode feature is JEDEC optional for 4Gb and 8Gb
DDR4 0e0ories. Perfor0ing an MPR read to page 2 MPR6 [±] indicates whether sPPR
0ode is available (A± = 1) or not available (A± = 6). sPPR 0ode provides a si0ple and
easy repair 0ethod of the device after placed in the syste0. One row per bank can be
repaired. The repair process is revocable by either doing a reset or power-down or by
rewriting a new address in the sa0e bank.
WRITE Preamble
t
Progra00able WRITE prea0ble, WPRE, can be set to 1tCK or 2tCK via the MR4 register.
The 1tCK setting is si0ilar to DDR3. However, when operating in 2tCK WRITE prea0ble
0ode, CWL 0ust be progra00ed to a value at least 1 clock greater than the lowest CWL
setting supported in the applicable tCK range.
When operating in 2tCK WRITE prea0ble 0ode, CWL 0ust be progra00ed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range. So0e even settings will require addition of 2 clocks. If the alternate longer CWL
was used, the additional clocks will not be required.
READ Preamble
Progra00able READ prea0ble tRPRE can be set to 1tCK or 2tCK via the MR4 register.
Both the 1tCK and 2tCK DDR4 prea0ble settings are different fro0 that defined for the
DDR3 SDRAM. Both DDR4 READ prea0ble settings 0ay require the 0e0ory controller
to train (or read level) its data strobe receivers using the READ prea0ble training.
READ Preamble Training
Progra00able READ prea0ble training can be set to 1tCK or 2tCK. This 0ode can be
used by the 0e0ory controller to train or READ level its data strobe receivers.
Temperature-Controlled Refresh
When te0perature-controlled refresh 0ode is enabled, the device 0ay adjust the inter-
nal refresh period to be longer than tREFI of the nor0al te0perature range by skipping
external REFRESH co00ands with the proper gear ratio. For exa0ple, the DRAM te0-
perature sensor detected less than 45°C. Nor0al te0perature 0ode covers the range of
–46°C to 85°C, while the extended te0perature range covers –46°C to 125°C.
Command Address Latency
COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled
or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) be-
tween a CS_n registered LOW and its corresponding registered co00and and address.
The value of CAL (in clocks) 0ust be progra00ed into the 0ode register and is based
on the roundup (in clocks) of [tCK(ns)/tCAL(ns)].
Internal VREF Monitor
The device generates its own internal VREFDQ. This 0ode 0ay be enabled during VREFDQ
training, and when enabled, VREF,ti0e-short and VREF,ti0e-long need to be increased by 16ns
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Mode Register 4
if DQ6, DQ1, DQ2, or DQ3 have 6pF loading. An additional 15ns per pF of loading is also
needed.
Maximum Power Savings Mode
This 0ode provides the lowest power 0ode where data retention is not required. When
the device is in the 0axi0u0 power saving 0ode, it does not need to guarantee data
retention or respond to any external co00and (except the MAXIMUM POWER SAVING
MODE EXIT co00and and during the assertion of RESET_n signal LOW).
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Mode Register 5
Mode Register 5
Mode register 5 (MR5) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR5 is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR5 Register
Definition table.
Table 19: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 20: MR5 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
12
11
10
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
Data bus inversion (DBI) – READ DBI enable
0 = Disabled
1 = Enabled
Data bus inversion (DBI) – WRITE DBI enable
0 = Disabled
1 = Enabled
Data mask (DM)
0 = Disabled
1 = Enabled
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 5
Table 20: MR5 Register Definition (Continued)
Mode
Register Description
9
CA parity persistent error mode
0 = Disabled
1 = Enabled
8:6
Parked ODT value (RTT(Park)
000 = RTT(Park) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
)
5
4
ODT input buffer for power-down
0 = Buffer enabled
1 = Buffer disabled
CA parity error status
0 = Clear
1 = Error
3
CRC error status
0 = Clear
1 = Error
2:0
CA parity latency mode
000 = Disable
001 = 4 clocks (DDR4-1600/1866/2133)
010 = 5 clocks (DDR4-2400/2666)1
011 = 6 clocks (DDR4-2933/3200)
100 = 8 clocks (DDR4-2933/3200)
101 = Reserved
110 = Reserved
111 = Reserved
1. Not allowed when 1/4 rate gear-down mode is enabled.
Note:
Data Bus Inversion
The DATA BUS INVERSION (DBI) function has been added to the device and is suppor-
ted only for x8 and x1± configurations (x4 is not supported). The DBI function shares a
co00on pin with the DM and TDQS functions. The DBI function applies to both READ
and WRITE operations; Write DBI cannot be enabled at the sa0e ti0e the DM function
is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three
functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an
MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12. DBI is not al-
lowed during MPR READ operations.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 5
Data Mask
The DATA MASK (DM) function, also described as a partial write, has been added to the
device and is supported only for x8 and x1± configurations (x4 is not supported). The
DM function shares a co00on pin with the DBI and TDQS functions. The DM function
applies only to WRITE operations and cannot be enabled at the sa0e ti0e the write DBI
function is enabled. Refer to the TDQS Function Matrix table for valid configurations for
all three functions (TDQS/DM/DBI).
CA Parity Persistent Error Mode
Nor0al CA parity 0ode (CA parity persistent 0ode disabled) no longer perfor0s CA
parity checking while the parity error status bit re0ains set at 1. However, with CA pari-
ty persistent 0ode enabled, CA parity checking continues to be perfor0ed when the
parity error status bit is set to a 1.
ODT Input Buffer for Power-Down
This feature deter0ines whether the ODT input buffer is on or off during power-down.
If the input buffer is configured to be on (enabled during power-down), the ODT input
signal 0ust be at a valid logic level. If the input buffer is configured to be off (disabled
during power-down), the ODT input signal 0ay be floating and the device does not pro-
vide RTT(NOM) ter0ination. However, the device 0ay provide RTT(Park) ter0ination de-
pending on the MR settings. This is pri0arily for additional power savings.
CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error
status bit re0ains set at 1 until the device controller clears it explicitly using an MRS
co00and.
CRC Error Status
The device will set the error status bit to 1 upon detecting a CRC error. The CRC error
status bit re0ains set at 1 until the device controller clears it explicitly using an MRS
co00and.
CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on tCK, is progra00ed; this ac-
counts for parity calculation delay internal to the device. The nor0al state of CA parity
is to be disabled. If CA parity is enabled, the device 0ust ensure there are no parity er-
rors before executing the co00and. CA parity signal (PAR) covers ACT_n, RAS_n/A1± ,
CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group
bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 6
Mode Register 6
Mode register ± (MR±) controls various device operating 0odes as shown in the follow-
ing register definition table. Not all settings listed 0ay be available on a die; only set-
tings required for speed bin support are available. MR± is written by issuing the MRS
co00and while controlling the states of the BGx, BAx, and Ax address pins. The 0ap-
ping of address pins during the MRS co00and is shown in the following MR± Register
Definition table.
Table 21: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode
21 20 19 18 17
–
–
–
13 12 11 10
9
8
7
6
5
4
3
2
1
0
register
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Note:
Table 22: MR6 Register Definition
Mode
Register Description
21
RFU
0 = Must be programmed to 0
1 = Reserved
20:18
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
13
NA on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
12:10
tCCD_L
000 = 4 clocks (≤1333 Mb/s)
001 = 5 clocks (>1333 Mb/s and ≤1866 Mb/s)
010 = 6 clocks (>1866 Mb/s and ≤2400 Mb/s)
011 = 7 clocks (>2400 Mb/s and ≤2666 Mb/s)
100 = 8 clocks (>2666 Mb/s and ≤3200 Mb/s)
101 = Reserved
110 = Reserved
111 = Reserved
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8Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 6
Table 22: MR6 Register Definition (Continued)
Mode
Register Description
9, 8
RFU
0 = Must be programmed to 0
1 = Reserved
7
VREF Calibration Enable
0 = Disable
1 = Enable
6
VREF Calibration Range
0 = Range 1
1 = Range 2
5:0
VREF Calibration Value
See the VREFDQ Range and Levels table in the VREFDQ Calibration section
tCCD_L Programming
The device controller 0ust progra0 the correct tCCD_L value. tCCD_L will be progra0-
0ed according to the value defined per operating frequency in the AC para0eter table.
Although JEDEC specifies the larger of 5nCK or Xns, Micron's DRAM supports the larger
of 4nCK or Xns. The -683C, -675C, and -6±8C operate with one additional clock for
tCCD_l.
VREFDQ Calibration Enable
VREFDQ calibration is where the device internally generates its own VREFDQ to be used by
the DQ input receivers. The VREFDQ value will be output on any DQ of DQ[3:6] for evalu-
ation only. The device controller is responsible for setting and calibrating the internal
VREFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assu0ed
that the controller will use a series of writes and reads in conduction with VREFDQ ad-
just0ents to opti0ize and verify the data eye. Enabling VREFDQ calibration 0ust be used
whenever values are being written to the MR±[±:6] register.
VREFDQ Calibration Range
The device defines two VREFDQ calibration ranges: Range 1 and Range 2. Range 1 sup-
ports VREFDQ between ±6% and 92% of VDDQ while Range 2 supports VREFDQ between
45% and 77% of VDDQ, as seen in VREFDQ Specification table. Although not a restriction,
Range 1 was targeted for 0odule-based designs and Range 2 was added to target point-
to-point designs.
VREFDQ Calibration Value
Fifty settings provide approxi0ately 6.±5% of granularity steps sizes for both Range 1
and Range 2 of VREFDQ, as seen in VREFDQ Range and Levels table in the VREFDQ Calibra-
tion section.
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Truth Tables
Table 23: Truth Table – Command
Notes 1–5 apply to the entire table; Note 6 applies to all READ/WRITE commands
Prev. Pres.
Function
CKE CKE
Notes
MODE REGISTER SET
REFRESH
MRS
REF
SRE
SRX
H
H
H
L
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
X
H
H
H
H
L
L
L
L
L
L
H
H
X
H
L
BG
V
BA
V
V
V
V
X
V
V
V
OP code
7
V
V
V
V
X
V
V
V
V
V
X
V
L
V
V
X
V
V
V
Self refresh entry
Self refresh exit
L
L
V
V
8, 9, 10
H
X
H
L
X
H
H
H
H
X
X
X
8, 9, 10,
11
V
V
V
Single-bank PRECHARGE
PRECHARGE all banks
Reserved for future use
Bank ACTIVATE
PRE
PREA
RFU
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BG
V
BA
V
V
L
L
V
H
L
H
RFU
ACT
Row address (RA)
BG
BG
BG
BG
BG
BG
BG
BG
BG
BG
BG
BG
BG
V
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
X
X
X
X
X
Row address (RA)
WRITE
BL8 fixed, BC4 fixed
WR
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
H
H
L
L
L
L
V
L
V
V
V
V
V
V
V
V
V
V
V
V
V
X
X
X
X
X
L
L
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
V
BC4OTF
WRS4
WRS8
WRA
WRAS4
WRAS8
RD
BL8OTF
L
L
H
V
L
L
WRITE
with auto
precharge
BL8 fixed, BC4 fixed
BC4OTF
L
L
H
H
H
L
L
L
BL8OTF
L
L
H
V
L
READ
BL8 fixed, BC4 fixed
BC4OTF
L
H
H
H
H
H
H
H
X
X
X
L
RDS4
RDS8
RDA
L
L
BL8OTF
L
H
V
L
L
READ
with auto
precharge
BL8 fixed, BC4 fixed
BC4OTF
L
H
H
H
V
X
X
X
H
L
RDAS4
RDAS8
NOP
L
BL8OTF
L
H
V
X
X
X
X
X
NO OPERATION
H
X
X
X
H
H
12
Device DESELECTED
Power-down entry
Power-down exit
DES
X
X
X
13
PDE
X
X
X
10, 14
10, 14
PDX
H
H
H
X
X
X
ZQ CALIBRATION LONG
ZQ CALIBRATION SHORT
ZQCL
ZQCS
H
H
X
X
X
L
X
X
X
8Gb: x8, x16 Automotive DDR4 SDRAM
Truth Tables
1. • BG = Bank group address
• BA = Bank address
• RA = Row address
• CA = Column address
• BC_n = Burst chop
• X = “Don’t Care”
• V = Valid
Notes:
2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/
A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA
are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16,
CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respec-
tively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address
pins A16, A15, and A14, respectively.
3. RESET_n is enabled LOW and is used only for asynchronous reset and must be main-
tained HIGH during any function.
4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a
bank group is being operated upon. For MRS commands, the BG and BA selects the spe-
cific mode register location.
5. V means HIGH or LOW (but a defined logic level), and X means either defined or unde-
fined (such as floating) logic level.
6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF)
BL will be defined by MRS.
7. During an MRS command, A17 is RFU and is device density- and configuration-depend-
ent.
8. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh.
9. VPP and VREF (VREFCA) must be maintained during SELF REFRESH operation.
10. Refer to the Truth Table – CKE table for more details about CKE transition.
11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has
the choice of either synchronous or asynchronous.
12. The NO OPERATION (NOP) command may be used only when exiting maximum power
saving mode or when entering gear-down mode.
13. The NOP command may not be used in place of the DESELECT command.
14. The power-down mode does not perform any REFRESH operation.
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Truth Tables
Table 24: Truth Table – CKE
Notes 1–7, 9, and 20 apply to the entire table
CKE
Previous Cycle Present Cycle
Current State
(n - 1)
(n)
Command (n)
Action (n)
Maintain power-down
Power-down exit
Notes
8, 10, 11
Power-down
L
L
L
X
DES
X
H
L
8, 10, 12
Self refresh
L
Maintain self refresh
Self refresh exit
11, 13
L
H
L
DES
DES
DES
DES
DES
DES
DES
REFRESH
8, 13, 14, 15
8, 10, 12, 16
8, 10, 12, 16, 17
8, 10, 12, 16, 17
8, 10, 12, 16, 17
8, 12
Bank(s) active
Reading
H
H
H
H
H
H
H
Active power-down entry
Power-down entry
L
Writing
L
Power-down entry
Precharging
Refreshing
All banks idle
L
Power-down entry
L
Precharge power-down entry
L
Precharge power-down entry 8, 10, 12, 16, 18
Self refresh 16, 18, 19
L
1. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock
edge n.
Notes:
2. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the
previous clock edge.
3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of
COMMAND (n); ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh.
6. During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must be
maintained until 1 nCK prior to tCKE (MIN) being satisfied (at which time CKE may tran-
sition again).
7. DESELECT and NOP are defined in the Truth Table – Command table.
8. For power-down entry and exit parameters, see the Power-Down Modes section.
9. CKE LOW is allowed only if tMRD and tMOD are satisfied.
10. The power-down mode does not perform any REFRESH operations.
11. X = "Don’t Care" (including floating around VREF) in self refresh and power-down. X al-
so applies to address pins.
12. The DESELECT command is the only valid command for power-down entry and exit.
13. VPP and VREFCA must be maintained during SELF REFRESH operation.
14. On self refresh exit, the DESELECT command must be issued on every clock edge occur-
ring during the tXS period. READ or ODT commands may be issued only after tXSDLL is
satisfied.
15. The DESELECT command is the only valid command for self refresh exit.
16. Self refresh cannot be entered during READ or WRITE operations. For a detailed list of
restrictions see the SELF REFRESH Operation and Power-Down Modes sections.
17. If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command,
then precharge power-down is entered; otherwise, active power-down is entered.
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NOP Command
18. Idle state is defined as all banks are closed (tRP, tDAL, and so on, satisfied), no data
bursts are in progress, CKE is HIGH, and all timings from previous operations are satis-
fied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on), as well as all self refresh ex-
it and power-down exit parameters are satisfied (tXS, tXP, tXSDLL, and so on).
19. Self refresh mode can be entered only from the all banks idle state.
20. For more details about all signals, see the Truth Table – Command table; must be a legal
command as defined in the table.
NOP Command
The NO OPERATION (NOP) co00and was originally used to instruct the selected
DDR4 SDRAM to perfor0 a NOP (CS_n = LOW and ACT_n, RAS_n/A1±, CAS_n/A15, and
WE_n/A14 = HIGH). This prevented unwanted co00ands fro0 being registered during
idle or wait states. NOP co00and general support has been re0oved and the co0-
0and should not be used unless specifically allowed, which is when exiting 0axi0u0
power-saving 0ode or when entering gear-down 0ode.
DESELECT Command
The deselect function (CS_n HIGH) prevents new co00ands fro0 being executed;
therefore, with this co00and, the device is effectively deselected. Operations already in
progress are not affected.
DLL-Off Mode
DLL-off 0ode is entered by setting MR1 bit A6 to 6, which will disable the DLL for sub-
sequent operations until the A6 bit is set back to 1. The MR1 A6 bit for DLL control can
be switched either during initialization or during self refresh 0ode. Refer to the Input
Clock Frequency Change section for 0ore details.
The 0axi0u0 clock frequency for DLL-off 0ode is specified by the para0eter
tCKDLL_OFF. There is no 0ini0u0 frequency li0it besides the need to satisfy the re-
fresh interval, tREFI.
Due to latency counter and ti0ing restrictions, only one CL value and CWL value (in
MR6 and MR2 respectively) are supported. The DLL-off 0ode is only required to sup-
port setting both CL = 16 and CWL = 9.
DLL-off 0ode will affect the read data clock-to-data strobe relationship (tDQSCK), but
not the data strobe-to-data relationship (tDQSQ, tQH). Special attention is needed to
line up read data to the controller ti0e do0ain.
Co0pared with DLL-on 0ode, where tDQSCK starts fro0 the rising clock edge (AL +
CL) cycles after the READ co00and, the DLL-off 0ode tDQSCK starts (AL + CL - 1) cy-
cles after the READ co00and. Another difference is that tDQSCK 0ay not be s0all
co0pared to tCK (it 0ight even be larger than tCK), and the difference between tDQSCK
(MIN) and tDQSCK (MAX) is significantly larger than in DLL-on 0ode. The tDQSCK
(DLL-off) values are vendor-specific.
The ti0ing relations on DLL-off 0ode READ operation are shown in the following dia-
gra0, where CL = 16, AL = 6, and BL = 8.
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DLL-Off Mode
Figure 13: DLL-Off Mode Read Timing Operation
T0
T1
T6
T7
T8
T9
T10
T11
T12
T13
T14
( (
) )
( (
) )
( (
) )
CK_c
CK_t
( (
) )
( (
) )
( (
) )
RD
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Command
Address
( (
) )
( (
) )
( (
) )
ARD
RL (DLL-on) = AL + CL = 10
CL = 10, AL = 0
( (
) )
DQS_t, DQS_c
(DLL-on)
t
t
DQSCK (MIN)
DQSCK (MAX)
( (
) )
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
DQS_c
(DLL-on)
RL (DLL-off) = AL + (CL - 1) = 9
CL = 10, AL = 0
t
DQSCK (DLL-off) MIN
( (
) )
DQS_t, DQS_c
(DLL-off)
( (
) )
DQS_c
(DLL-off)
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
t
DQSCK (DLL-off) MAX
( (
) )
DQS_t, DQS_c
(DLL-off)
( (
) )
DQS_c
(DLL-off)
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
DIN
b+7
Transitioning data
Don’t Care
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8Gb: x8, x16 Automotive DDR4 SDRAM
DLL-On/Off Switching Procedures
DLL-On/Off Switching Procedures
The DLL-off 0ode is entered by setting MR1 bit A6 to 6; this will disable the DLL for
subsequent operations until the A6 bit is set back to 1.
DLL Switch Sequence from DLL-On to DLL-Off
To switch fro0 DLL-on to DLL-off requires the frequency to be changed during self re-
fresh, as outlined in the following procedure:
1. Starting fro0 the idle state (all banks pre-charged, all ti0ings fulfilled, and, to dis-
able the DLL, the DRAM on-die ter0ination resistors, RTT(NOM), 0ust be in High-Z
before MRS to MR1.)
2. Set MR1 bit A6 to 1 to disable the DLL.
3. Wait tMOD.
4. Enter self refresh 0ode; wait until tCKSRE/tCKSRE_PAR is satisfied.
5. Change frequency, following the guidelines in the Input Clock Frequency Change
section.
±. Wait until a stable clock is available for at least tCKSRX at device inputs.
7. Starting with the SELF REFRESH EXIT co00and, CKE 0ust continuously be reg-
istered HIGH until all tMOD ti0ings fro0 any MRS co00and are satisfied. In ad-
dition, if any ODT features were enabled in the 0ode registers when self refresh
0ode was entered, the ODT signal 0ust continuously be registered LOW until all
tMOD ti0ings fro0 any MRS co00and are satisfied. If RTT(NOM) was disabled in
the 0ode registers when self refresh 0ode was entered, the ODT signal is "Don't
Care."
8. Wait tXS_FAST, tXS_ABORT, or tXS, and then set 0ode registers with appropriate
values (an update of CL, CWL, and WR 0ay be necessary; a ZQCL co00and can
also be issued after tXS_FAST).
t
• XS_FAST: ZQCL, ZQCS, and MRS co00ands. For MRS co00ands, only CL and
WR/RTP registers in MR6, the CWL register in MR2, and gear-down 0ode in
MR3 0ay be accessed provided the device is not in per-DRAM addressability
0ode. Access to other device 0ode registers 0ust satisfy tXS ti0ing.
t
• XS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh
and does not incre0ent the refresh counter. The controller can issue a valid
co00and after a delay of tXS_ABORT. Upon exiting fro0 self refresh, the device
requires a 0ini0u0 of one extra REFRESH co00and before it is put back into
self refresh 0ode. This require0ent re0ains the sa0e regardless of the MRS bit
setting for self refresh abort.
t
• XS: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8,
RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.
9. Wait tMOD to co0plete.
The device is ready for the next co00and.
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DLL-On/Off Switching Procedures
Figure 14: DLL Switch Sequence from DLL-On to DLL-Off
Ta
Tb0
Tb1
Tc
Td
Te0
Te1
Tf
Tg
Th
CK_c
CK_t
t
t
t
5
CKSRE/ CKSRE_PAR
Note 4
CKSRX
t
IS
t
CPDED
Valid
Valid
Valid
CKE
t
XS_FAST
3
6
9
7
8
2
SRE
DES
SRX
Valid
Valid
Valid
MRS
Command
Address
Valid
Valid
Valid
t
t
RP
XS_ABORT
t
t
IS
t
t
XS
CKESR/ CKESR_PAR
ODT
Valid
Enter self refresh
Exit self refresh
Time Break
Don’t Care
1. Starting in the idle state. RTT in stable state.
2. Disable DLL by setting MR1 bit A0 to 0.
3. Enter SR.
Notes:
4. Change frequency.
5. Clock must be stable tCKSRX.
6. Exit SR.
7. Update mode registers allowed with DLL-off settings met.
DLL-Off to DLL-On Procedure
To switch fro0 DLL-off to DLL-on (with required frequency change) during self refresh:
1. Starting fro0 the idle state (all banks pre-charged, all ti0ings fulfilled, and DRAM
ODT resistors (RTT(NOM)) 0ust be in High-Z before self refresh 0ode is entered.)
2. Enter self refresh 0ode; wait until tCKSRE/tCKSRE_PAR are satisfied.
3. Change frequency (following the guidelines in the Input Clock Frequency Change
section).
4. Wait until a stable clock is available for at least tCKSRX at device inputs.
5. Starting with the SELF REFRESH EXIT co00and, CKE 0ust continuously be reg-
istered HIGH until tDLLK ti0ing fro0 the subsequent DLL RESET co00and is
satisfied. In addition, if any ODT features were enabled in the 0ode registers
when self refresh 0ode was entered, the ODT signal 0ust continuously be regis-
tered LOW or HIGH until tDLLK ti0ing fro0 the subsequent DLL RESET co0-
0and is satisfied. If RTT(NOM) disabled in the 0ode registers when self refresh
0ode was entered, the ODT signal is "Don't Care."
±. Wait tXS or tXS_ABORT, depending on bit 9 in MR4, then set MR1 bit A6 to 6 to
enable the DLL.
7. Wait tMRD, then set MR6 bit A8 to 1 to start DLL reset.
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Input Clock Frequency Change
8. Wait tMRD, then set 0ode registers with appropriate values; an update of CL,
t
CWL, and WR 0ay be necessary. After MOD is satisfied fro0 any proceeding MRS
co00and, a ZQCL co00and can also be issued during or after tDLLK.
9. Wait for tMOD to co0plete. Re0e0ber to wait tDLLK after DLL RESET before ap-
plying any co00and requiring a locked DLL. In addition, wait for tZQoper in case
a ZQCL co00and was issued.
The device is ready for the next co00and.
Figure 15: DLL Switch Sequence from DLL-Off to DLL-On
Ta
Tb0
Tb1
Tc
Td
Te0
Te1
Tf
Tg
Th
CK_c
CK_t
t
t
t
5
Note 1
CKSRE/ CKSRE_PAR
Note 4
CKSRX
t
IS
t
CPDED
Valid
Valid
Valid
CKE
t
XS_ABORT
3
6
7
7
7
2
SRE
DES
SRX
Valid
Valid
Valid
MRS
Command
Address
Valid
Valid
Valid
t
t
t
RP
XS
MRD
t
IS
t
t
CKESR/ CKESR_PAR
ODT
Valid
Enter self refresh
Exit self refresh
Time Break
Don’t Care
1. Starting in the idle state.
2. Enter SR.
Notes:
3. Change frequency.
4. Clock must be stable tCKSRX.
5. Exit SR.
6. Set DLL to on by setting MR1 to A0 = 0.
7. Update mode registers.
8. Issue any valid command.
Input Clock Frequency Change
After the device is initialized, it requires the clock to be stable during al0ost all states of
nor0al operation. This 0eans that after the clock frequency has been set and is in the
stable state, the clock period is not allowed to deviate except for what is allowed by the
clock jitter and spread spectru0 clocking (SSC) specifications. The input clock frequen-
cy can be changed fro0 one stable clock rate to another stable clock rate only when in
self refresh 0ode. Outside of self refresh 0ode, it is illegal to change the clock frequen-
cy.
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Write Leveling
After the device has been successfully placed in self refresh 0ode and tCKSRE/
tCKSRE_PAR have been satisfied, the state of the clock beco0es a "Don’t Care." Follow-
ing a "Don’t Care," changing the clock frequency is per0issible, provided the new clock
frequency is stable prior to tCKSRX. When entering and exiting self refresh 0ode for the
sole purpose of changing the clock frequency, the self refresh entry and exit specifica-
tions 0ust still be 0et as outlined in SELF REFRESH Operation.
For the new clock frequency, additional MRS co00ands to MR6, MR2, MR3, MR4, MR5,
and MR± 0ay need to be issued to progra0 appropriate CL, CWL, gear-down 0ode,
t
READ and WRITE prea0ble, Co00and Address Latency, and CCD_L/tDLLK values.
When the clock rate is being increased (faster), the MR settings that require additional
clocks should be updated prior to the clock rate being increased. In particular, the PL
latency 0ust be disabled when the clock rate changes, for exa0ple, while in self refresh
0ode. For exa0ple, if changing the clock rate fro0 DDR4-2133 to DDR4-2933 with CA
parity 0ode enabled, MR5[2:6] 0ust first change fro0 PL = 4 to PL = disable prior to PL
= ±. The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:6], (2)
enter self refresh 0ode, (3) change clock rate fro0 DDR4-2133 to DDR4-2933, (4) exit
self refresh 0ode, (5) Enable CA parity 0ode setting PL = ± vis MR5 [2:6].
If the MR settings that require different clocks are updated after the clock rate has been
changed, for exa0ple. after exiting self refresh 0ode, the required MR settings 0ust be
updated prior to re0oving the DRAM fro0 the IDLE state, unless the DRAM is RESET. If
the DRAM leaves the IDLE state to enter self refresh 0ode or ZQ calibration, the updat-
ing of the required MR settings 0ay be deferred to the next ti0e the DRAM enters the
IDLE state.
If MR± is issued prior to self refresh entry for new the tDLLK value, DLL will relock auto-
0atically at self refresh exit. However, if MR± is issued after self refresh entry, MR6 0ust
be issued to reset the DLL.
The device input clock frequency can change only within the 0ini0u0 and 0axi0u0
operating frequency specified for the particular speed grade. Any frequency change be-
low the 0ini0u0 operating frequency would require the use of DLL-on 0ode to DLL-
off 0ode transition sequence (see DLL-On/Off Switching Procedures).
Write Leveling
For better signal integrity, DDR4 0e0ory 0odules use fly-by topology for the co0-
0ands, addresses, control signals, and clocks. Fly-by topology has benefits fro0 the re-
duced nu0ber of stubs and their length, but it also causes flight-ti0e skew between
clock and strobe at every DRAM on the DIMM. This 0akes it difficult for the controller
to 0aintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a
write leveling feature to allow the controller to co0pensate for skew. This feature 0ay
not be required under so0e syste0 conditions, provided the host can 0aintain the
tDQSS, tDSS, and tDSH specifications.
The 0e0ory controller can use the write leveling feature and feedback fro0 the device
to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The 0e0ory con-
troller involved in the leveling 0ust have an adjustable delay setting on DQS to align the
rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously
feeds back CK, sa0pled with the rising edge of DQS, through the DQ bus. The controller
repeatedly delays DQS until a transition fro0 6 to 1 is detected. The DQS delay estab-
lished though this exercise would ensure the tDQSS specification. Besides tDQSS, tDSS
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Write Leveling
and tDSH specifications also need to be fulfilled. One way to achieve this is to co0bine
the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS
signals. Depending on the actual tDQSS in the application, the actual values for tDQSL
and tDQSH 0ay have to be better than the absolute li0its provided in the AC Ti0ing
Para0eters section in order to satisfy tDSS and tDSH specifications. A conceptual ti0-
ing of this sche0e is shown below.
Figure 16: Write Leveling Concept, Example 1
T0
T1
T2
T3
T4
T5
T6
T7
CK_c
CK_t
Source
diff_DQS
Tn
T0
T1
T2
T3
T4
T5
T6
CK_c
Destination
CK_t
diff_DQS
DQ
0 or 1
0
0
0
Push DQS to capture
the 0-1 transition
diff_DQS
DQ
0 or 1
1
1
1
DQS driven by the controller during leveling 0ode 0ust be ter0inated by the DRAM
based on the ranks populated. Si0ilarly, the DQ bus driven by the DRAM 0ust also be
ter0inated at the controller.
All data bits carry the leveling feedback to the controller across the DRAM configura-
tions: x4, x8, and x1±. On a x1± device, both byte lanes should be leveled independently.
Therefore, a separate feedback 0echanis0 should be available for each byte lane. The
upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-
clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-
to-clock relationship.
The figure below is another representative way to view the write leveling procedure. Al-
though it shows the clock varying to a static strobe, this is for illustrative purpose only;
the clock does not actually change phase, the strobe is what actually varies. By issuing
0ultiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the ti0e
at which the clock edge arrives at the DRAM clock input buffer.
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Write Leveling
Figure 17: Write Leveling Concept, Example 2
tWLS
CK_c
1 1 1 111 1 1 11 1 1 1 1 1 1 1 1
tWLH
CK_t
CK_c
0 0 0 0 0 0 0 0 0 0 0 0 0
tWLS
CK_t
tWLH
CK_c
CK_t
11 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0
X XX X X X
DQS_t/
DQS_c
tWLO
DQ (CK 0 to 1)
DQ (CK 1 to 0)
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode
The DRAM enters into write leveling 0ode if A7 in MR1 is HIGH. When leveling is fin-
ished, the DRAM exits write leveling 0ode if A7 in MR1 is LOW (see the MR Leveling
Procedures table). Note that in write leveling 0ode, only DQS ter0inations are activa-
ted and deactivated via the ODT pin, unlike nor0al operation (see DRAM DRAM TER-
MINATION Function in Leveling Mode table).
Table 25: MR Settings for Leveling Procedures
Function
MR1
A7
Enable
Disable
Write leveling enable
Output buffer mode (Q off)
1
0
0
1
A12
Table 26: DRAM TERMINATION Function in Leveling Mode
ODT Pin at DRAM
DQS_t/DQS_c Termination
DQ Termination
RTT(NOM) with ODT HIGH
RTT(Park) with ODT LOW
On
On
Off
Off
1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1
and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] =
0), all RTT(NOM) and RTT(Park) settings are supported.
Notes:
2. RTT(WR) is not allowed in write leveling mode and must be set to disable prior to enter-
ing write leveling mode.
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Write Leveling
Procedure Description
The 0e0ory controller initiates the leveling 0ode of all DRAM by setting bit 7 of MR1
to 1. When entering write leveling 0ode, the DQ pins are in undefined driving 0ode.
During write leveling 0ode, only the DESELECT co00and is supported, other than
MRS co00ands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]).
Upon exiting write leveling 0ode, the MRS co00and perfor0ing the exit (MR1[A7] = 6)
0ay also change the other MR1 bits. Because the controller levels one rank at a ti0e,
the output of other ranks 0ust be disabled by setting MR1 bit A12 to 1. The controller
0ay assert ODT after tMOD, at which ti0e the DRAM is ready to accept the ODT signal,
unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is in-
creased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR
co00and), then ODT assertion should be delayed by DODTLon after tMOD is satisfied,
which 0eans the delay is now tMOD + DODTLon.
The controller 0ay drive DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN, at
which ti0e the DRAM has applied ODT to these signals. After tDQSL and tWLMRD, the
controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sa0ple
CK driven fro0 the controller. tWLMRD (MAX) ti0ing is controller dependent.
The DRAM sa0ples CK status with the rising edge of DQS and provides feedback on all
the DQ bits asynchronously after tWLO ti0ing. There is a DQ output uncertainty of
tWLOE defined to allow 0is0atch on DQ bits. The tWLOE period is defined fro0 the
transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller sa0-
ples inco0ing DQ and either incre0ents or decre0ents DQS delay setting and launch-
es the next DQS pulse after so0e ti0e, which is controller dependent. After a 6-to-1
transition is detected, the controller locks the DQS delay setting, and write leveling is
achieved for the device. The following figure shows the ti0ing diagra0 and para0eters
for the overall write leveling procedure.
Figure 18: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)
T1
T2
tWLH
tWLH
tWLS
tWLS
CK_c5
CK_t
DES3
DES
OP
DES
DES
MRS2
DES
DES
DES
DES
DES
Command
DES
DES
tMOD
ODT
tDQSH6
tDQSL6
tDQSL6
tDQSH6
tWLDQSEN
diff_DQS4
tWLMRD
tWLO
tWLO
Late Prime DQ1
Early Prime DQ1
tWLOE
tWLO
tWLO
tWLOE
Time Break
Undefined Driving Mode
Don’t Care
1. The device drives leveling feedback on all DQs.
2. MRS: Load MR1 to enter write leveling mode.
Notes:
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Write Leveling
3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings.
DQS_t is shown with a solid line; DQS_c is shown with a dotted line.
4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line.
5. DQS needs to fulfill minimum pulse width requirements, tDQSH (MIN) and tDQSL (MIN),
as defined for regular WRITEs; the maximum pulse width is system dependent.
6. tWLDQSEN must be satisfied following equation when using ODT:
• DLL = Enable, then tWLDQSEN > tMOD (MIN) + DODTLon + tADC
• DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS
Write Leveling Mode Exit
Write leveling 0ode should be exited as follows:
1. After the last rising strobe edge (see ~T6), stop driving the strobe signals (see
~Tc6). Note that fro0 this point on, DQ pins are in undefined driving 0ode and
will re0ain undefined, until tMOD after the respective MR co00and (Te1).
2. Drive ODT pin LOW (tIS 0ust be satisfied) and continue registering LOW (see
Tb6).
3. After RTT is switched off, disable write leveling 0ode via the MRS co00and (see
Tc2).
4. After tMOD is satisfied (Te1), any valid co00and can be registered. (MR co0-
0ands can be issued after tMRD [Td1]).
Figure 19: Write Leveling Exit
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
CK_c
CK_t
DES
DES
DES
DES
DES
DES
DES
tMRD
Valid
Valid
Valid
Valid
DES
DES
Command
Address
ODT
DES
MR1
tIS
t
MOD
t
ODTL (OFF)
ADC (MIN)
R
TT(DQS_t)
RTT(NON)
RTT(Park)
R
TT(DQS_c)
t
ADC (MAX)
DQS_t,
DQS_c
R
TT(DQ)
t
WLO
1
DQ
result = 1
Time Break
Transitioning
Don’t Care
Undefined Driving Mode
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t
HIGH just after the T0 state.
2. See previous figure for specific tWLO timing.
Notes:
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Command Address Latency
Command Address Latency
DDR4 supports the co00and address latency (CAL) function as a power savings fea-
ture. This feature can be enabled or disabled via the MRS setting. CAL ti0ing is defined
as the delay in clock cycles (tCAL) between a CS_n registered LOW and its correspond-
ing registered co00and and address. The value of CAL in clocks 0ust be progra00ed
into the 0ode register (see MR1 Register Definition table) and is based on the equation
tCK(ns)/tCAL(ns), rounded up in clocks.
Figure 20: CAL Timing Definition
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CS_n
CMD/ADDR
t
CAL
CAL gives the DRAM ti0e to enable the co00and and address receivers before a co0-
0and is issued. After the co00and and the address are latched, the receivers can be
disabled if CS_n returns to HIGH. For consecutive co00ands, the DRAM will keep the
co00and and address input receivers enabled for the duration of the co00and se-
quence.
Figure 21: CAL Timing Example (Consecutive CS_n = LOW)
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CS_n
CMD/ADDR
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8Gb: x8, x16 Automotive DDR4 SDRAM
Command Address Latency
When the CAL 0ode is enabled, additional ti0e is required for the MRS co00and to
co0plete. The earliest the next valid co00and can be issued is tMOD_CAL, which
should be equal to tMOD + tCAL. The two following figures are exa0ples.
Figure 22: CAL Enable Timing – tMOD_CAL
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
CK_c
CK_t
Command
Address
Valid
Valid
MRS
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CS_n
t
CAL
t
MOD_CAL
Settings
Old settings
Updating settings
New settings
Time Break
Don’t Care
1. CAL mode is enabled at T1.
Note:
Figure 23: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled
T0
T1
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
CK_c
CK_t
Command
Valid
Valid
DES
DES
MRS
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
t
t
CAL
CAL
Address
CS_n
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
t
MOD_CAL
Settings
Old settings
Updating settings
New settings
Time Break
Don’t Care
1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL set-
ting if modified.
Note:
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Command Address Latency
When the CAL 0ode is enabled or being enabled, the earliest the next MRS co00and
can be issued is tMRD_CAL is equal to tMOD + tCAL. The two following figures are ex-
a0ples.
Figure 24: CAL Enabling MRS to Next MRS Command, tMRD_CAL
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
CK_c
CK_t
Command
Valid
Valid
MRS
DES
DES
DES
DES
DES
DES
DES
MRS
DES
tCAL
Address
CS_n
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tMRD_CAL
Settings
Old settings
Updating settings
Updating settings
Time Break
Don’t Care
1. Command address latency mode is enabled at T1.
Note:
Figure 25: tMRD_CAL, Mode Register Cycle Time With CAL Enabled
7ꢅ
7ꢇ
7Dꢅ
7Dꢇ
7Dꢈ
7Eꢅ
7Eꢇ
7Eꢈ
7Fꢅ
7Fꢇ
7Fꢈ
CK_c
CK_t
Command
9DOLG
9DOLG
'(6
9DOLG
'(6
9DOLG
056
9DOLG
'(6
9DOLG
'(6
9DOLG
'(6
9DOLG
'(6
9DOLG
'(6
9DOLG
056
9DOLG
'(6
9DOLG
W
W
&$/
&$/
Address
CS_n
W
05'B&$/
Settings
2OGꢀVHWWLQJV
8SGDWLQJꢀVHWWLQJV
1HZꢀVHWWLQJV
7LPHꢀ%UHDN
'RQ¶Wꢀ&DUH
1. MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL set-
ting if modified.
Note:
CAL Exa0ples: Consecutive READ BL8 with two different CALs and 1tCK prea0ble in
different bank group shown in the following figures.
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Figure 26: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group
T0
T1
T2
T3
T4
T5
T6
T7
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CK_c
CK_t
CS_n
tCAL = 3
tCAL = 3
DES
DES
DES
DES
READ
BG b
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Command
READ
BG a
tCCD_S = 4
Bank Group
Address
Bank,
Col n
Bank,
Col b
Address
tRPST
tRPRE (1nCK)
DQS_t, DQS_c
DQ
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
OUT
b + 7
OUT
n
OUT
n + 1
OUT
n + 2
OUT
n + 3
OUT
n + 4
OUT
n + 5
OUT
n + 6
OUT
n + 7
OUT
b
OUT
b + 7
OUT
b + 2
OUT
b + 3
OUT
b + 4
OUT
b + 5
OUT
b + 6
RL = 11
RL = 11
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK.
2. DOUT n = data-out from column n; DOUT b = data-out from column b.
3. DES commands are shown for ease of illustration, other commands may be valid at these times.
Notes:
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and
T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.
6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.
Figure 27: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group
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1. BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1tCK.
2. DOUT n = data-out from column n; DOUT b = data-out from column b.
3. DES commands are shown for ease of illustration, other commands may be valid at these times.
Notes:
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and
T8.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable.
6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the
same timing relationship relative to the command/address bus as when CAL is disabled.
8Gb: x8, x16 Automotive DDR4 SDRAM
Low-Power Auto Self Refresh Mode
Low-Power Auto Self Refresh Mode
An auto self refresh 0ode is provided for application ease. Auto self refresh 0ode is en-
abled by setting MR2[±] = 1 and MR2[7] = 1. The device will 0anage self refresh entry
over the supported te0perature range of the DRAM. In this 0ode, the device will
change its self refresh rate as the DRAM operating te0perature changes, going lower at
low te0peratures and higher at high te0peratures.
Manual Self Refresh Mode
If auto self refresh 0ode is not enabled, the low-power auto self refresh 0ode register
0ust be 0anually progra00ed to one of the three self refresh operating 0odes. This
0ode provides the flexibility to select a fixed self refresh operating 0ode at the entry of
the self refresh, according to the syste0 0e0ory te0perature conditions. The user is
responsible for 0aintaining the required 0e0ory te0perature condition for the 0ode
selected during the SELF REFRESH operation. The user 0ay change the selected 0ode
after exiting self refresh and before entering the next self refresh. If the te0perature
condition is exceeded for the 0ode selected, there is a risk to data retention resulting in
loss of data.
Table 27: Auto Self Refresh Mode
Low-Power
Auto Self Refresh
Mode
Operating Temperature
Range for Self Refresh Mode
MR2[7] MR2[6]
SELF REFRESH Operation
(DRAM TCASE)
0
0
Normal
Fixed normal self refresh rate maintains data
retention at the normal operating tempera-
ture. User is required to ensure that 85°C
DRAM TCASE (MAX) is not exceeded to avoid
any risk of data loss.
–40°C to 85°C
1
0
0
1
Extended
temperature
Fixed high self refresh rate optimizes data re-
tention to support the extended tempera-
ture range.
–40°C to 125°C
–40°C to 45°C
Reduced
temperature
Variable or fixed self refresh rate or any oth-
er DRAM power consumption reduction con-
trol for the reduced temperature range. User
is required to ensure 45°C DRAM TCASE
(MAX) is not exceeded to avoid any risk of
data loss.
1
1
Auto self refresh
Auto self refresh mode enabled. Self refresh
power consumption and data retention are
optimized for any given operating tempera-
ture condition.
All of the above
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Low-Power Auto Self Refresh Mode
Figure 28: Auto Self Refresh Ranges
IDD6
2x refresh rate
1x refresh rate
Extended
temperature
range
1/2x refresh rate
Reduced
temperature
range
Normal
temperature
range
Tc
25°C
45°C
85°C
125°C
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81
8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Multipurpose Register
The MULTIPURPOSE REGISTER (MPR) function, MPR access 0ode, is used to write/
read specialized data to/fro0 the DRAM. The MPR consists of four logical pages, MPR
Page 6 through MPR Page 3, with each page having four 8-bit registers, MPR6 through
MPR3. Page 6 can be read by any of three readout 0odes (serial, parallel, or staggered)
while Pages 1, 2, and 3 can be read by only the serial readout 0ode. Page 3 is for DRAM
vendor use only. MPR 0ode enable and page selection is done with MRS co00ands.
Data bus inversion (DBI) is not allowed during MPR READ operation.
Once the MPR access 0ode is enabled (MR3[2] = 1), only the following co00ands are
allowed: MRS, RD, RDA WR, WRA, DES, REF, and RESET; RDA/WRA have the sa0e func-
tionality as RD/WR which 0eans the auto precharge part of RDA/WRA is ignored. Pow-
er-down 0ode and SELF REFRESH co00and are not allowed during MPR enable
0ode. No other co00and can be issued within tRFC after a REF co00and has been
issued; 1x refresh (only) is to be used during MPR access 0ode. While in MPR access
0ode, MPR read or write sequences 0ust be co0pleted prior to a REFRESH co00and.
Figure 29: MPR Block Diagram
Memory core
(all banks precharged)
Four multipurpose registers (pages),
each with four 8-bit registers:
MR3 [2] = 1
Data patterns (RD/WR)
Error log (RD)
Mode registers (RD)
DRAM manufacture only (RD)
DQ,s DM_n/DBI_n, DQS_t, DQS_c
Table 28: MR3 Setting for the MPR Access Mode
Address
Operation Mode
Description
A[12:11]
MPR data read format
00 = Serial ........... 01 = Parallel
10 = Staggered .... 11 = Reserved
A2
MPR access
0 = Standard operation (MPR not enabled)
1 = MPR data flow enabled
A[1:0]
MPR page selection
00 = Page 0 .... 01 = Page 1
10 = Page 2 .... 11 = Page 3
Table 29: DRAM Address to MPR UI Translation
MPR Location
DRAM address – Ax
MPR UI – UIx
[7]
A7
[6]
A6
[5]
A5
[4]
A4
[3]
A3
[2]
A2
[1]
A1
[0]
A0
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
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82
8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Table 30: MPR Page and MPRx Definitions
Address MPR Location
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Note
MPR Page 0 – Read or Write (Data Patterns)
BA[1:0]
00 = MPR0
01 = MPR1
10 = MPR2
11 = MPR3
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
Read/
Write
(default
value lis-
ted)
MPR Page 1 – Read-only (Error Log)
BA[1:0]
00 = MPR0
01 = MPR1
A7
A6
A5
A4
A3
A2
A1
A9
A0
A8
Read-on-
ly
CAS_n/A WE_n/A1
A13
A12
A11
A10
15
4
10 = MPR2
11 = MPR3
PAR
ACT_n
BG1
BG0
BA1
BA0
C2
A17
C1
RAS_n/A
16
CRC er- CA pari-
ror sta- ty error
tus
CA parity latency: [5] =
MR5[2], [4] = MR5[1], [3] =
MR5[0]
C0
status
MPR Page 2 – Read-only (MRS Readout)
BA[1:0]
00 = MPR0
01 = MPR1
hPPR
sPPR
RTT(WR)
Temperature sen- CRC write
R
TT(WR) MR2[10:9] Read-on-
ly
support support MR2[11]
sor status2
enable
MR2[12]
VREFDQ
traing-
ing
range
MR6[6]
V
REFDQ training value: [6:1] = MR6[5:0]
Gear-
down
enable
MR3[3]
10 = MPR2
11 = MPR3
CAS latency: [7:3] = MR0[6:4,2,12]
CAS write latency [2:0] =
MR2[5:3]
R
TT(NOM): [7:5] = MR1[10:8]
RTT(Park): [4:2] = MR5[8:6]
RON: [1:0] =
MR2[2:1]
MPR Page 3 – Read-only (Restricted, except for MPR3 [3:0])
BA[1:0]
00 = MPR0
01 = MPR1
10 = MPR2
11 = MPR3
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Read-on-
ly
DC
DC
DC
DC
DC
MAC
MAC
MAC
MAC
1. DC = "Don't Care"
Notes:
2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh;
MPR[4:3] 11 = Reserved
MPR Reads
MPR reads are supported using BL8 and BC4 0odes. Burst length on-the-fly is not sup-
ported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ opera-
tion; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR 0ode.
READ co00ands for BC4 are supported with a starting colu0n address of A[2:6] = 666
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
or 166. After power-up, the content of MPR Page 6 has the default values, which are de-
fined in Table 36. MPR page 6 can be rewritten via an MPR WRITE co00and. The de-
vice 0aintains the default values unless it is rewritten by the DRAM controller. If the
DRAM controller does overwrite the default values (Page 6 only), the device will 0ain-
tain the new values unless re-initialized or there is power loss.
Ti0ing in MPR 0ode:
• Reads (back-to-back) fro0 Page 6 0ay use tCCD_S or tCCD_L ti0ing between READ
co00ands
• Reads (back-to-back) fro0 Pages 1, 2, or 3 0ay not use tCCD_S ti0ing between READ
co00ands; tCCD_L 0ust be used for ti0ing between READ co00ands
The following steps are required to use the MPR to read out the contents of a 0ode reg-
ister (MPR Page x, MPRy).
1. The DLL 0ust be locked if enabled.
2. Precharge all; wait until tRP is satisfied.
3. MRS co00and to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read for-
0at, and MR3[1:6] MPR page.
a. MR3[12:11] MPR read for0at:
1. 66 = Serial read for0at
2. 61 = Parallel read for0at
3. 16 = staggered read for0at
4. 11 = RFU
b. MR3[1:6] MPR page:
1. 66 = MPR Page 6
2. 61 = MPR Page 1
3. 16 = MPR Page 2
4. 11 = MPR Page 3
4. tMRD and tMOD 0ust be satisfied.
5. Redirect all subsequent READ co00ands to specific MPRx location.
±. Issue RD or RDA co00and.
a. BA1 and BA6 indicate MPRx location:
1. 66 = MPR6
2. 61 = MPR1
3. 16 = MPR2
4. 11 = MPR3
b. A12/BC = 6 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported.
1. If BL = 8 and MR6 A[1:6] = 61, A12/BC 0ust be set to 1 during MPR
READ co00ands.
c. A2 = burst-type dependant:
1. BL8: A2 = 6 with burst order fixed at 6, 1, 2, 3, 4, 5, ±, 7
2. BL8: A2 = 1 not allowed
3. BC4: A2 = 6 with burst order fixed at 6, 1, 2, 3, T, T, T, T
4. BC4: A2 = 1 with burst order fixed at 4, 5, ±, 7, T, T, T, T
d. A[1:6] = 66, data burst is fixed nibble start at 66.
e. Re0aining address inputs, including A16, and BG1 and BG6 are "Don’t
Care."
CCMTD-1406124318-10419
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84
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
7. After RL = AL + CL, DRAM bursts data fro0 MPRx location; MPR readout for0at
deter0ined by MR3[A12,11,1,6].
8. Steps 5 through 7 0ay be repeated to read additional MPRx locations.
9. After the last MPRx READ burst, tMPRR 0ust be satisfied prior to exiting.
16. Issue MRS co00and to exit MPR 0ode; MR3[2] = 6.
11. After the tMOD sequence is co0pleted, the DRAM is ready for nor0al operation
fro0 the core (such as ACT).
MPR Readout Format
The MPR read data for0at can be set to three different settings: serial, parallel, and
staggered.
MPR Readout Serial Format
The serial for0at is required when enabling the MPR function to read out the contents
of an MRx, te0perature sensor status, and the co00and address parity error fra0e.
However, data bus calibration locations (four 8-bit registers) can be progra00ed to
read out any of the three for0ats. The DRAM is required to drive associated strobes
with the read data si0ilar to nor0al operation (such as using MRS prea0ble settings).
Serial for0at i0plies that the sa0e pattern is returned on all DQ lanes, as shown the
table below, which uses values progra00ed into the MPR via [7:6] as 6111 1111.
Table 31: MPR Readout Serial Format
Serial
x4 Device
DQ0
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DQ1
DQ2
DQ3
x8 Device
DQ0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
x16 Device
DQ0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DQ1
DQ2
DQ3
DQ4
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85
8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Table 31: MPR Readout Serial Format (Continued)
Serial
DQ5
UI0
0
UI1
1
UI2
1
UI3
1
UI4
1
UI5
1
UI6
1
UI7
1
DQ6
0
1
1
1
1
1
1
1
DQ7
0
1
1
1
1
1
1
1
DQ8
0
1
1
1
1
1
1
1
DQ9
0
1
1
1
1
1
1
1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
MPR Readout Parallel Format
Parallel for0at i0plies that the MPR data is returned in the first data UI and then repea-
ted in the re0aining UIs of the burst, as shown in the table below. Data pattern location
6 is the only location used for the parallel for0at. RD/RDA fro0 data pattern locations
1, 2, and 3 are not allowed with parallel data return 0ode. In this exa0ple, the pattern
progra00ed in the data pattern location 6 is 6111 1111. The x4 configuration only out-
puts the first four bits (6111 in this exa0ple). For the x1± configuration, the sa0e pat-
tern is repeated on both the upper and lower bytes.
Table 32: MPR Readout – Parallel Format
Parallel
x4 Device
DQ0
UI0
UI1
UI2
UI3
UI4
UI5
UI6
UI7
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
DQ1
DQ2
DQ3
x8 Device
DQ0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
x16 Device
DQ0
0
0
0
0
0
0
0
0
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86
8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Table 32: MPR Readout – Parallel Format (Continued)
Parallel
DQ1
UI0
1
UI1
1
UI2
1
UI3
1
UI4
1
UI5
1
UI6
1
UI7
1
DQ2
1
1
1
1
1
1
1
1
DQ3
1
1
1
1
1
1
1
1
DQ4
1
1
1
1
1
1
1
1
DQ5
1
1
1
1
1
1
1
1
DQ6
1
1
1
1
1
1
1
1
DQ7
1
1
1
1
1
1
1
1
DQ8
0
0
0
0
0
0
0
0
DQ9
1
1
1
1
1
1
1
1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MPR Readout Staggered Format
Staggered for0at of data return is defined as the staggering of the MPR data across the
lanes. In this 0ode, an RD/RDA co00and is issued to a specific data pattern location
and then the data is returned on the DQ fro0 each of the different data pattern loca-
tions. For the x4 configuration, an RD/RDA to data pattern location 6 will result in data
fro0 location 6 being driven on DQ6, data fro0 location 1 being driven on DQ1, data
fro0 location 2 being driven on DQ2, and so on, as shown below. Si0ilarly, an RD/RDA
co00and to data pattern location 1 will result in data fro0 location 1 being driven on
DQ6, data fro0 location 2 being driven on DQ1, data fro0 location 3 being driven on
DQ2, and so on. Exa0ples of different starting locations are also shown.
Table 33: MPR Readout Staggered Format, x4
x4 READ MPR0 Command x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command
Stagger
DQ0
UI[7:0]
MPR0
MPR1
MPR2
MPR3
Stagger
DQ0
UI[7:0]
MPR1
MPR2
MPR3
MPR0
Stagger
DQ0
UI[7:0]
MPR2
MPR3
MPR0
MPR1
Stagger
DQ0
UI[7:0]
MPR3
MPR0
MPR1
MPR2
DQ1
DQ1
DQ1
DQ1
DQ2
DQ2
DQ2
DQ2
DQ3
DQ3
DQ3
DQ3
It is expected that the DRAM can respond to back-to-back RD/RDA co00ands to the
MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be
created on the data bus with no bubbles or clocks between read data. In this case, the
syste0 0e0ory controller issues a sequence of RD(MPR6), RD(MPR1), RD(MPR2),
RD(MPR3), RD(MPR6), RD(MPR1), RD(MPR2), and RD(MPR3).
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Table 34: MPR Readout Staggered Format, x4 – Consecutive READs
Stagger
DQ0
UI[7:0]
MPR0
MPR1
MPR2
MPR3
UI[15:8]
MPR1
MPR2
MPR3
MPR0
UI[23:16]
MPR2
UI[31:24]
MPR3
UI[39:32]
MPR0
UI[47:40]
MPR1
UI[55:48]
MPR2
UI[63:56]
MPR3
DQ1
MPR3
MPR0
MPR1
MPR2
MPR3
MPR0
DQ2
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
DQ3
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
For the x8 configuration, the sa0e pattern is repeated on the lower nibble as on the up-
per nibble. READs to other MPR data pattern locations follow the sa0e for0at as the x4
case. A read exa0ple to MPR6 for x8 and x1± configurations is shown below.
Table 35: MPR Readout Staggered Format, x8 and x16
x8 READ MPR0 Command
x16 READ MPR0 Command
x16 READ MPR0 Command
Stagger
DQ0
UI[7:0]
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
Stagger
DQ0
UI[7:0]
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
Stagger
DQ8
UI[7:0]
MPR0
MPR1
MPR2
MPR3
MPR0
MPR1
MPR2
MPR3
DQ1
DQ1
DQ9
DQ2
DQ2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ3
DQ3
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
MPR READ Waveforms
The following wavefor0s show MPR read accesses.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Figure 30: MPR READ Timing
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Tc2
Tc3
Td0
Td1
Te0
Tf0
Tf1
CK_c
CK_t
MPE Enable
MPE Disable
1
3
4
Command
Address
CKE
PREA
Valid
MRS
DES
READ
DES
DES
DES
DES
DES
DES
MRS
Valid
DES
t
t
t
t
MPRR
MOD
RP
MOD
Valid
2
Valid
Add
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
5
PL + AL + CL
DQS_t,
DQS_c
DQ
UI0 UI1 UI2 UI5 UI6 UI7
Time Break
Don’t Care
1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting:
Notes:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Multipurpose registers read/write disable (MR3 A2 = 0).
4. Continue with regular DRAM command.
5. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
Figure 31: MPR Back-to-Back READ Timing
T0
T1
T2
T3
T4
T5
T6
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
CK_c
CK_t
Command
DES
READ
DES
DES
DES
READ
Valid
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
1
CCD_S
2
2
Address
CKE
Valid
Add
Valid
Add
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
3
PL + AL + CL
DQS_t,
DQS_c
DQ
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
DQS_t,
DQS_c
DQ
UI0 UI1 UI2 UI3
UI0 UI1 UI2 UI3
Time Break
Don’t Care
1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting:
Notes:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is
fixed at 0, 1, 2, 3, T, T, T, T)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
Figure 32: MPR READ-to-WRITE Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
CK_c
CK_t
Command
Address
CKE
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
WRITE
DES
DES
t
MPRR
1
2
Add
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Add
Valid
Valid
3
PL + AL + CL
DQS_t,
DQS_c
DQ
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
1. Address setting:
Notes:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01
2. Address setting:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
MPR Writes
MPR access 0ode allows 8-bit writes to the MPR Page 6 using the address bus A[7:6].
Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will
0aintain the new written values unless re-initialized or there is power loss.
The following steps are required to use the MPR to write to 0ode register MPR Page 6.
1. The DLL 0ust be locked if enabled.
2. Precharge all; wait until tRP is satisfied.
3. MRS co00and to MR3[2] = 1 (enable MPR data flow) and MR3[1:6] = 66 (MPR
Page 6); writes to 61, 16, and 11 are not allowed.
4. tMRD and tMOD 0ust be satisfied.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
5. Redirect all subsequent WRITE co00ands to specific MPRx location.
±. Issue WR or WRA co00and:
a. BA1 and BA6 indicate MPRx location
1. 66 = MPR6
2. 61 = MPR1
3. 16 = MPR2
4. 11 = MPR3
b. A[7:6] = data for MPR Page 6, 0apped A[7:6] to UI[7:6].
c. Re0aining address inputs, including A16, and BG1 and BG6 are "Don’t
Care."
7. tWR_MPR 0ust be satisfied to co0plete MPR WRITE.
8. Steps 5 through 7 0ay be repeated to write additional MPRx locations.
9. After the last MPRx WRITE, tMPRR 0ust be satisfied prior to exiting.
16. Issue MRS co00and to exit MPR 0ode; MR3[2] = 6.
11. When the tMOD sequence is co0pleted, the DRAM is ready for nor0al operation
fro0 the core (such as ACT).
MPR WRITE Waveforms
The following wavefor0s show MPR write accesses.
Figure 33: MPR WRITE and WRITE-to-READ Timing
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Td2
Td3
DES
Td4
Td5
CK_c
CK_t
MPR Enable
1
Command
Address
CKE
PREA
Valid
MRS
DES
WRITE
DES
t
DES
READ
Add
DES
DES
DES
DES
DES
t
t
RP
MOD
WR_MPR
2
2
Valid
Valid
Add
Valid
Valid
Valid
Valid
Valid
Add
Valid
Valid
3
PL + AL + CL
DQS_t,
DQS_c
DQ
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
1. Multipurpose registers read/write enable (MR3 A2 = 1).
Notes:
2. Address setting:
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Figure 34: MPR Back-to-Back WRITE Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
CK_c
CK_t
Command
Address
CKE
WRITE
Add1
DES
DES
DES
WRITE
Valid
DES
DES
Add
DES
DES
DES
DES
DES
DES
tWR_MPR
Valid
Valid
Add1
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQS_t,
DQS_c
DQ
Time Break
Don’t Care
1. Address setting:
Note:
BA1 and BA0 indicate the MPR location
A[7:0] = data for MPR
A10 and other address pins are "Don’t Care"
MPR REFRESH Waveforms
The following wavefor0s show MPR accesses interaction with refreshes.
Figure 35: REFRESH Timing
T0
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tc0
Tc1
Tc2
Tc3
Tc4
CK_c
CK_t
MPR Enable
1
2
Command
Address
PREA
Valid
MRS
DES
REF
DES
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
t
t
t
RP
MOD
RFC
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Time Break
Don’t Care
1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and
writes to MPR locations.
Notes:
2. 1x refresh is only allowed when MPR mode is enabled.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Figure 36: READ-to-REFRESH Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
CK_c
CK_t
Command
Address
CKE
READ
Add1
DES
DES
DES
DES
DES
DES
DES
DES
DES
REF2
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
PL + AL + CL
(4 + 1) + Clocks
tRFC
BL = 8
DQS_t, DQS_c
DQ
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
BC = 4
DQS_t, DQS_c
DQ
UI0 UI1 UI2 UI3
Time Break
Don’t Care
1. Address setting:
Notes:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10, and must be 1b when MR0 A[1:0] = 01
2. 1x refresh is only allowed when MPR mode is enabled.
Figure 37: WRITE-to-REFRESH Timing
T0
T1
Ta0
Ta1
Ta2
REF
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
Ta10
CK_c
CK_t
2
Command
Address
CKE
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
t
WR_MPR
RFC
1
Add
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQS_t,
DQS_c
DQ
Time Break
Don’t Care
1. Address setting:
BA1 and BA0 indicate the MPR location
Notes:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
A[7:0] = data for MPR
A10 and other address pins are "Don’t Care"
2. 1x refresh is only allowed when MPR mode is enabled.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Gear-Down Mode
Gear-Down Mode
The DDR4 SDRAM defaults in 1/2 rate (1N) clock 0ode and uses a low-frequency MRS
co00and (the MRS co00and has relaxed setup and hold) followed by a sync pulse
(first CS pulse after MRS setting) to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) 0ode. Gear-down 0ode is only sup-
ported at DDR4-2±±± and faster. For operation in 1/2 rate 0ode, neither an MRS co0-
0and or a sync pulse is required. Gear-down 0ode 0ay only be entered during initiali-
zation or self refresh exit and 0ay only be exited during self refresh exit. CAL 0ode and
CA parity 0ode 0ust be disabled prior to gear-down 0ode entry. The two 0odes 0ay
be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The gener-
al sequence for operation in 1/4 rate during initialization is as follows:
1. The device defaults to a 1N 0ode internal clock at power-up/reset.
2. Assertion of reset.
3. Assertion of CKE enables the DRAM.
4. MRS is accessed with a low-frequency N × tCK gear-down MRS co00and. (NtCK
static MRS co00and is qualified by 1N CS_n. )
5. The 0e0ory controller will send a 1N sync pulse with a low-frequency N × tCK
NOP co00and. tSYNC_GEAR is an even nu0ber of clocks. The sync pulse is on
an even edge clock boundary fro0 the MRS co00and.
±. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N
0ode after tCMD_GEAR fro0 1N sync pulse.
The device resets to 1N gear-down 0ode after entering self refresh. The general se-
quence for operation in gear-down after self refresh exit is as follows:
1. MRS is set to 1, via MR3[3], with a low-frequency N × tCK gear-down MRS co0-
0and.
a. The NtCK static MRS co00and is qualified by 1N CS_n, which 0eets tXS or
tXS_ABORT.
b. Only a REFRESH co00and 0ay be issued to the DRAM before the NtCK
static MRS co00and.
2. The DRAM controller sends a 1N sync pulse with a low-frequency N × tCK NOP
co00and.
a. tSYNC_GEAR is an even nu0ber of clocks.
b. The sync pulse is on even edge clock boundary fro0 the MRS co00and.
3. A valid co00and not requiring locked DLL is available in 2N 0ode after
tCMD_GEAR fro0 the 1N sync pulse.
a. A valid co00and requiring locked DLL is available in 2N 0ode after tXSDLL
or tDLLK fro0 the 1N sync pulse.
4. If operation is in 1N 0ode after self refresh exit, N × tCK MRS co00and or sync
pulse is not required during self refresh exit. The 0ini0u0 exit delay to the first
valid co00and is tXS, or tXS_ABORT.
The DRAM 0ay be changed fro0 2N to 1N by entering self refresh 0ode, which will re-
set to 1N 0ode. Changing fro0 2N to by any other 0eans can result in loss of data and
0ake operation of the DRAM uncertain.
When operating in 2N gear-down 0ode, the following MR settings apply:
• CAS latency (MR6[±:4,2]): Even nu0ber of clocks
• Write recovery and read to precharge (MR6[11:9]): Even nu0ber of clocks
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8Gb: x8, x16 Automotive DDR4 SDRAM
Gear-Down Mode
• Additive latency (MR1[4:3]): CL - 2
• CAS WRITE latency (MR2 A[5:3]): Even nu0ber of clocks
• CS to co00and/address latency 0ode (MR4[8:±]): Even nu0ber of clocks
• CA parity latency 0ode (MR5[2:6]): Even nu0ber of clocks
Figure 38: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)
TdkN
TdkN + N
even
CK_c
CK_t
t
DSRX
DRAM
internal CLK
RESET_n
CKE
t
t
t
SYNC_GEAR
CMD_GEAR
XPR_GEAR
1N sync pulse
2N mode
CS_n
t
t
t
t
N CK
N CK
N CK
N CK
hold
setup
MRS
hold
setup
NOP
Valid
Command
Configure DRAM
to 1/4 rate
Time Break
Don’t Care
Figure 39: Clock Mode Change After Exiting Self Refresh
TdkN
TdkN + Neven
CK_c
CK_t
DRAM
internal CLK
CKE
t
t
t
CMD_GEAR
SYNC_GEAR
XPR_GEAR
1N sync pulse
2N mode
CS_n
NtCK
NtCK
NtCK
NtCK
hold
setup
hold
setup
MRS
NOP
Valid
Command
Configure DRAM
to 1/4 rate
Time Break
Don’t Care
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Figure 40: Comparison Between Gear-Down Disable and Gear-Down Enable
T0
T1
T2
T3
T15
T16
T17
T18
T19
T30
T31
T32
DES
T33
DES
T34
DES
T35
DES
T36
DES
T37
DES
T38
DES
CK_c
CK_t
AL = 0 (geardown = disable)
Command
DQ
ACT
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DO
DO
DO
DO
DO
DO
DO
DO
n
n+ 1 n+ 2 n + 3 n+ 4 n+ 5 n+ 6 n+ 7
tRCD = 16
RL =CL= 16 (AL = 0)
AL = CL - 1 (geardown = disable)
READ
DES
Command
ACT
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7
RL = AL + CL = 31 (AL = CL - 1 = 15)
READ
Command
DQ
ACT
READ
DES
DES
DES
DES
DES
DES
DES
DO
DO
DO
DO
DO
DO
DO
DO
n
n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7
AL + CL = RL = 30 (AL = CL - 2 = 14)
Time Break
Transitioning Data
Don’t Care
8Gb: x8, x16 Automotive DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode
Maxi0u0 power-saving 0ode provides the lowest power 0ode where data retention is
not required. When the device is in the 0axi0u0 power-saving 0ode, it does not
0aintain data retention or respond to any external co00and, except the MAXIMUM
POWER SAVING MODE EXIT co00and and during the assertion of RESET_n signal
LOW. This 0ode is 0ore like a “hibernate 0ode” than a typical power-saving 0ode.
The intent is to be able to park the DRAM at a very low-power state; the device can be
switched to an active state via the per-DRAM addressability (PDA) 0ode.
Maximum Power-Saving Mode Entry
Maxi0u0 power-saving 0ode is entered through an MRS co00and. For devices with
shared control/address signals, a single DRAM device can be entered into the 0axi-
0u0 power-saving 0ode using the per-DRAM addressability MRS co00and. Large
CS_n hold ti0e to CKE upon the 0ode exit could cause DRAM 0alfunction; as a result,
CA parity, CAL, and gear-down 0odes 0ust be disabled prior to the 0axi0u0 power-
saving 0ode entry MRS co00and.
The MRS co00and 0ay use both address and DQ infor0ation, as defined in the Per-
DRAM Addressability section. As illustrated in the figure below, after tMPED fro0 the
0ode entry MRS co00and, the DRAM is not responsive to any input signals except
CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals 0ay be-
co0e High-Z). The syste0 will provide a valid clock until tCKMPE expires, at which ti0e
clock inputs (CK) should be disabled (external clock signals 0ay beco0e High-Z).
Figure 41: Maximum Power-Saving Mode Entry
Ta0
Ta1
Ta2
Tb0
Tb1
Tb3
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Tc11
CK_c
CK_t
t
CKMPE
DES
MR4[A1=1]
MPSM Enable)
Command
DES
MRS
DES
DES
t
MPED
Address
CS_n
Valid
CKE
CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode
RESET_n
Time Break
Don’t Care
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8Gb: x8, x16 Automotive DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode Entry in PDA
The sequence and ti0ing required for the 0axi0u0 power-saving 0ode with the per-
DRAM addressability enabled is illustrated in the figure below.
Figure 42: Maximum Power-Saving Mode Entry with PDA
Ta0
Ta1
Ta2
Tb0
DES
Tb1
DES
Tb3
DES
Tb4
DES
Tb5
DES
Tb6
DES
Tb7
Tb8
DES
Tb9
DES
Tc0
Tc1
Tc2
Td0
Td1
Td2
CK_c
CK_t
MR4[A1 = 1]
MPSM Enable)
Command
DES
MRS
DES
DES
DES
DES
t
CKMPE
CS_n
CKE
t
AL + CWL
MPED
DQS_t
DQS_c
t
t
PDA_S
PDA_H
DQ
RESET_n
Time Break
Don’t Care
CKE Transition During Maximum Power-Saving Mode
The following figure shows how to 0aintain 0axi0u0 power-saving 0ode even though
the CKE input 0ay toggle. To prevent the device fro0 exiting the 0ode, CS_n should be
HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold
(tMPX_H) ti0ings.
Figure 43: Maintaining Maximum Power-Saving Mode with CKE Transition
CLK
CMD
CS_n
tMPX_S
tMPX_HH
CKE
RESET_n
Don’t Care
Maximum Power-Saving Mode Exit
To exit the 0axi0u0 power-saving 0ode, CS_n should be LOW at the CKE LOW-to-
HIGH transition, with appropriate setup (tMPX_S) and hold (tMPX_LH) ti0ings, as
shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during
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Maximum Power-Saving Mode
this 0ode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n sig-
nal level is detected LOW, the DRAM clears the 0axi0u0 power-saving 0ode MRS bit
and begins the exit procedure fro0 this 0ode. The external clock 0ust be restarted and
be stable by tCKMPX before the device can exit the 0axi0u0 power-saving 0ode. Dur-
ing the exit ti0e (tXMP), only NOP and DES co00ands are allowed: NOP during
tMPX_LH and DES the re0ainder of tXMP. After tXMP expires, valid co00ands not re-
quiring a locked DLL are allowed; after tXMP_DLL expires, valid co00ands requiring a
locked DLL are allowed.
Figure 44: Maximum Power-Saving Mode Exit
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Tc2
Tc4
Td0
DES
Td1
DES
Td2
DES
Td3
Te0
Te1
CK_c
CK_t
tCKMPX
Command
CS_n
NOP
NOP
NOP
NOP
NOP
DES
Valid
DES
DES
tMPX_LH
tMPX_S
CKE
tXMP
tXMP_DLL
RESET_n
Time Break
Don’t Care
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8Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
Command/Address Parity
Co00and/address (CA) parity takes the CA parity signal (PAR) input carrying the parity
bit for the generated address and co00ands signals and 0atches it to the internally
generated parity fro0 the captured address and co00ands signals. CA parity is suppor-
ted in the DLL enabled state only; if the DLL is disabled, CA parity is not supported.
Figure 45: Command/Address Parity Operation
DRAM Controller
DRAM
CMD/ADDR
CMD/ADDR
Even parity
GEN
Even parity
GEN
CMD/ADDR
Even parity bit
Even parity bit
Compare
parity
bit
CA parity is disabled or enabled via an MRS co00and. If CA parity is enabled by pro-
gra00ing a non-zero value to CA parity latency in the MR, the DRAM will ensure that
there is no parity error before executing co00ands. There is an additional delay re-
quired for executing the co00ands versus when parity is disabled. The delay is pro-
gra00ed in the MR when CA parity is enabled (parity latency) and applied to all co0-
0ands which are registered by CS_n (rising edge of CK_t and falling CS_n). The co0-
0and is held for the ti0e of the parity latency (PL) before it is executed inside the de-
vice. The co00and captured by the input clock has an internal delay before executing
and is deter0ined with PL. When CA parity is enabled, only DES are allowed between
valid co00ands. PAR will go active when the DRAM detects a CA parity error.
CA parity covers ACT_n, RAS_n/A1±, CAS_n/A15, WE_n/A14, the address bus including
bank address and bank group bits, and C[2:6] on 3DS devices; the control signals CKE,
ODT, and CS_n are not covered. For exa0ple, for a 4Gb x4 0onolithic device, parity is
co0puted across BG[1:6], BA[1:6], A1±/RAS_n, A15/CAS_n, A14/ WE_n, A[13:6], and
ACT_n. The DRAM treats any unused address pins internally as zeros; for exa0ple, if a
co00on die has stacked pins but the device is used in a 0onolithic application, then
the address pins used for stacking and not connected are treated internally as zeros.
The convention for parity is even parity; for exa0ple, valid parity is defined as an even
nu0ber of ones across the inputs used for parity co0putation co0bined with the pari-
ty signal. In other words, the parity bit is chosen so that the total nu0ber of ones in the
trans0itted signal, including the parity bit, is even.
If a DRAM device detects a CA parity error in any co00and qualified by CS_n, it will
perfor0 the following steps:
1. Ignore the erroneous co00and. Co00ands in the MAX NnCK window
(tPAR_UNKNOWN) prior to the erroneous co00and are not guaranteed to be
executed. When a READ co00and in this NnCK window is not executed, the de-
vice does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC
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Command/Address Parity
occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit lo-
cated at MR5[3] 0ay or 0ay not get set. When CA Parity and WRITE CRC are both
enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset.
2. Log the error by storing the erroneous co00and and address bits in the MPR er-
ror log.
3. Set the parity error status bit in the 0ode register to 1. The parity error status bit
0ust be set before the ALERT_n signal is released by the DRAM (that is,
tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)).
4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within
tPAR_ALERT_ON ti0e.
5. Wait for all in-progress co00ands to co0plete. These co00ands were received
tPAR_UNKOWN before the erroneous co00and.
±. Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing
any co00ands during the window defined by (tPAR_ALERT_ON +
tPAR_ALERT_PW).
7. After tPAR_ALERT_PW (MIN) has been satisfied, the device 0ay de-assert
ALERT_n.
a. When the device is returned to a known precharged state, ALERT_n is al-
lowed to be de-asserted.
8. After (tPAR_ALERT_PW (MAX)) the DRAM is ready to accept co00ands for nor-
0al operation. Parity latency will be in effect; however, parity checking will not re-
su0e until the 0e0ory controller has cleared the parity error status bit by writing
a zero. The DRAM will execute any erroneous co00ands until the bit is cleared;
unless persistent 0ode is enabled.
• The DRAM should have only DES co00ands issued around ALERT_n going HIGH
such that at least 3 clocks prior and 1 clock plus 3ns after the release of ALERT_n.
• It is possible that the device 0ight have ignored a REFRESH co00and during
tPAR_ALERT_PW or the REFRESH co00and is the first erroneous fra0e, so it is rec-
o00ended that extra REFRESH cycles be issued, as needed.
• The parity error status bit 0ay be read anyti0e after tPAR_ALERT_ON +
tPAR_ALERT_PW to deter0ine which DRAM had the error. The device 0aintains the
error log for the first erroneous co00and until the parity error status bit is reset to a
zero or a second CA parity occurs prior to resetting.
The 0ode register for the CA parity error is defined as follows: CA parity latency bits are
write only, the parity error status bit is read/write, and error logs are read-only bits. The
DRAM controller can only progra0 the parity error status bit to zero. If the DRAM con-
troller illegally atte0pts to write a 1 to the parity error status bit, the DRAM can not be
certain that parity will be checked; the DRAM 0ay opt to block the DRAM controller
fro0 writing a 1 to the parity error status bit.
The device supports persistent parity error 0ode. This 0ode is enabled by setting
MR5[9] = 1; when enabled, CA parity resu0es checking after the ALERT_n is de-asser-
ted, even if the parity error status bit re0ains a 1. If 0ultiple errors occur before the er-
ror status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In
persistent parity error 0ode the ALERT_n pulse will be asserted and de-asserted by the
DRAM as defined with the MIN and MAX value tPAR_ALERT_PW. The DRAM controller
0ust issue DESELECT co00ands once it detects the ALERT_n signal, this response
ti0e is defined as tPAR_ALERT_RSP. The following figures capture the flow of events on
the CA bus and the ALERT_n signal.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
Table 36: Mode Register Setting for CA Parity
CA Parity Latency
Erroneous CA
MR5[2:0]1
000 = Disabled
001 = 4 clocks
010 = 5 clocks
011 = 6 clocks
100 = 8 clocks
101 = Reserved
110 = Reserved
111 = Reserved
Applicable Speed Bin
Parity Error Status Parity Persistent Mode
Frame
N/A
1600, 1866, 2133
2400, 2666
2933, 3200
RFU
C[2:0], ACT_n, BG1,
BG0, BA[1:0], PAR,
A17, A16/RAS_n, A15/
CAS_n, A14/WE_n,
A[13:0]
MR5 [4] 0 = Clear
MR5 [4] 1 = Error
MR5 [9] 0 = DisabledMR5
[9] 1 = Enabled
RFU
RFU
RFU
1. Parity latency is applied to all commands.
Notes:
2. Parity latency can be changed only from a CA parity disabled state; for example, a direct
change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to
PL = 4.
3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL.
READ latency = AL + CL + PL.
Figure 46: Command/Address Parity During Normal Operation
T1
Ta0
Ta1
Ta2
Tb0
Tc0
Tc1
Td0
Te0
Te1
T0
CK_c
CK_t
Command/
Address
Valid2
Valid2
Valid2
Error
DES2
DES2
Valid3
Valid3
Valid
Valid
Valid
t > 2nCK
t > 1nCK + 3ns
t
2
t
t
1
PAR_UNKNOWN
PAR_ALERT_ON
PAR_ALERT_PW
ALERT_n
Valid2
DES2
Valid
Command execution unknown
Command not executed
Error
Don’t Care
Time Break
Valid3
Command executed
1. DRAM is emptying queues. Precharge all and parity checking are off until parity error
status bit is cleared.
Notes:
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE
CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located
at MR5[3] may or may not get set.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit is cleared.
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Command/Address Parity
Figure 47: Persistent CA Parity Error Checking Operation
T1
Ta0
Ta1
Ta2
Tb0
Tc0
Tc1
Td0
Te0
Te1
T0
CK_c
CK_t
Command/
Address
Valid2
Valid2
Valid2
Error
DES
1
DES
DES
Valid3
Valid
Valid
Valid
t
PAR_ALERT_RSP
t
t > 2nCK
t > 1nCK + 3ns
t
2
t
PAR_UNKNOWN
PAR_ALERT_ON
PAR_ALERT_PW
ALERT_n
Valid2
Error
DES
Command execution unknown
Command not executed
Valid
Valid3
Don’t Care
Time Break
Command executed
1. DRAM is emptying queues. Precharge all and parity check re-enable finished by
tPAR_ALERT_PW.
Notes:
2. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE
CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located
at MR5[3] may or may not get set
3. Normal operation with parity latency and parity checking (CA parity persistent error
mode enabled).
Figure 48: CA Parity Error Checking – SRE Attempt
T0
T1
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Td2
Td3
Te0
Te1
CK_c
CK_t
tCPDED + PL
tXP + PL
DES6
Command/
Address
DES1
DES1, 5
Error2
DES6
DES5
Valid3
tIS
tIS
CKE
t > 2nCK
t > 1nCK + 3ns
tIH
Note 4
tPAR_ALERT_ON
tPAR_ALERT_PW1
ALERT_n
DES1, 5
DES6
DES1
DES5
Command execution unknown
Error2
Valid3
Command not executed
Don’t Care
Time Break
Command executed
1. Only DESELECT command is allowed.
Notes:
2. SELF REFRESH command error. The DRAM masks the intended SRE command and enters
precharge power-down.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until the parity error status bit cleared.
4. The controller cannot disable the clock until it has been capable of detecting a possible
CA parity error.
5. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
6. Only a DESELECT command is allowed; CKE may go HIGH prior to Tc2 as long as DES
commands are issued.
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Command/Address Parity
Figure 49: CA Parity Error Checking – SRX Attempt
T0
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Tc2
Td0
Td1
Te0
Tf0
CK_c
CK_t
Command/
Address
2
2
2
Valid
1
2
2, 3
DES
2, 3
DES
2, 4, 5
2, 4, 6
2, 4, 7
Valid
Valid
Valid
SRX
DES
DES
Error
Valid
Valid
t > 2nCK
t > 1nCK + 3ns
tIS
CKE
tPAR_UNKNOWN
tPAR_ALERT_ON
tPAR_ALERT_PW
ALERT_n
tXS_FAST8
tXS
tXSDLL
1
3, 5
Valid
SRX
DES
Command execution unknown
Command not executed
Command executed
Error
Valid
Don’t Care
Time Break
4,5,6,7
Valid
1. Self refresh abort = disable: MR4 [9] = 0.
2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT, and tXS_FAST timing.
Notes:
3. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking off until parity error status bit cleared.
5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS,
or ZQCL command is allowed.
6. Valid commands not requiring a locked DLL.
7. Valid commands requiring a locked DLL.
8. This figure shows the case from which the error occurred after tXS_FAST. An error may
also occur after tXS_ABORT and tXS.
Figure 50: CA Parity Error Checking – PDE/PDX
T0
T1
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Td2
Td3
Te0
Te1
CK_c
CK_t
tCPDED + PL
DES1
tXP + PL
DES5
Command/
Address
DES1
Error2
DES5
DES4
Valid3
tIS
tIS
CKE
t > 2nCK
t > 1nCK + 3ns
tIH
tPAR_ALERT_ON
tPAR_ALERT_PW1
ALERT_n
DES4
Error2
Valid3
DES5
DES1
Command execution unknown
Command not executed
Don’t Care
Time Break
Command executed
1. Only DESELECT command is allowed.
2. Error could be precharge or activate.
Notes:
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit cleared.
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Command/Address Parity
4. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES
commands are issued.
Figure 51: Parity Entry Timing Example – tMRD_PAR
Ta0
Ta1
Ta2
Tb0
DES
Tb1
Tb2
DES
CK_c
CK_t
Command
DES
MRS
DES
MRS
Parity latency
PL = 0
Updating setting
tMRD_PAR
PL = N
Enable
parity
Time Break
Don’t Care
1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.
Note:
Figure 52: Parity Entry Timing Example – tMOD_PAR
Ta0
Ta1
Ta2
Tb0
DES
Tb1
Tb2
DES
CK_c
CK_t
Command
DES
MRS
DES
Valid
Parity latency
PL = 0
Updating setting
tMOD_PAR
PL = N
Enable
parity
Time Break
Don’t Care
1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.
Note:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
Figure 53: Parity Exit Timing Example – tMRD_PAR
Ta0
Ta1
Ta2
Tb0
DES
Tb1
Tb2
DES
CK_c
CK_t
Command
DES
MRS
DES
MRS
Parity latency
PL = N
Updating setting
tMRD_PAR
Disable
parity
Time Break
Don’t Care
1. tMRD_PAR = tMOD + N; where N is the programmed parity latency.
Note:
Figure 54: Parity Exit Timing Example – tMOD_PAR
Ta0
Ta1
Ta2
Tb0
DES
Tb1
Tb2
DES
CK_c
CK_t
Command
DES
MRS
DES
Valid
Parity latency
PL = N
Updating setting
tMOD_PAR
Disable
parity
Time Break
Don’t Care
1. tMOD_PAR = tMOD + N; where N is the programmed parity latency.
Note:
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Figure 55: CA Parity Flow Diagram
CA
MR5[2:0] set parity latency (PL)
MR5[4] set parity error status to 0
process start
MR5[9] enable/disable persistent mode
CA
latched in
Persistent
mode
enabled
Yes
Yes
Yes
Yes
CA parity
enabled
CA parity
error
No
No
No
Command
execution
unknown
Good CA
processed
Ignore
bad CMD
MR5[4] = 0
@ ADDR/CMD
latched
Yes
CA parity
error
No
No
MR5[4] = 0 Yes
@ ADDR/CMD
latched
ALERT_n LOW
44 to 144 CKs
Log error/
set parity status
Command
execution
unknown
Good CA
processed
Ignore
bad CMD
Yes
No
CA error
No
ALERT_n LOW
44 to 144 CKs
Log error/
set parity status
Internal
precharge all
Good CA
processed
Bad CA
processed
Internal
precharge all
ALERT_n HIGH
Normal
operation ready
Operation ready?
Command
execution
unknown
ALERT_n HIGH
Normal operation ready
MR5[4] reset to 0 if desired
Command
execution
unknown
Normal operation ready
MR5[4] reset to 0 if desired
8Gb: x8, x16 Automotive DDR4 SDRAM
Per-DRAM Addressability
Per-DRAM Addressability
DDR4 allows progra00ability of a single, specific DRAM on a rank. As an exa0ple, this
feature can be used to progra0 different ODT or VREF values on each DRAM on a given
rank. Because per-DRAM addressability (PDA) 0ode 0ay be used to progra0 opti0al
VREF for the DRAM, the data set up for first DQ6 transfer or the hold ti0e for the last
DQ6 transfer cannot be guaranteed. The DRAM 0ay sa0ple DQ6 on either the first fall-
ing or second rising DQS transfer edge. This supports a co00on i0ple0entation be-
tween BC4 and BL8 0odes on the DRAM. The DRAM controller is required to drive DQ6
to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8
cases.
1. Before entering PDA 0ode, write leveling is required.
• BL8 or BC4 0ay be used.
2. Before entering PDA 0ode, the following MR settings are possible:
• RTT(Park) MR5 A[8:±] = Enable
• RTT(NOM) MR1 A[16:8] = Enable
3. Enable PDA 0ode using MR3 [4] = 1. (The default progra0ed value of MR3[4] = 6.)
4. In PDA 0ode, all MRS co00ands are qualified with DQ6. The device captures
DQ6 by using DQS signals. If the value on DQ6 is LOW, the DRAM executes the
MRS co00and. If the value on DQ6 is HIGH, the DRAM ignores the MRS co0-
0and. The controller can choose to drive all the DQ bits.
5. Progra0 the desired DRAM and 0ode registers using the MRS co00and and
DQ6.
±. In PDA 0ode, only MRS co00ands are allowed.
7. The MODE REGISTER SET co00and cycle ti0e in PDA 0ode, AL + CWL + BL/2 -
6.5tCK + tMRD_PDA + PL, is required to co0plete the WRITE operation to the
0ode register and is the 0ini0u0 ti0e required between two MRS co00ands.
8. Re0ove the device fro0 PDA 0ode by setting MR3[4] = 6. (This co00and re-
quires DQ6 = 6.)
Note: Re0oving the device fro0 PDA 0ode will require progra00ing the entire MR3
when the MRS co00and is issued. This 0ay i0pact so0e PDA values progra00ed
within a rank as the EXIT co00and is sent to the rank. To avoid such a case, the PDA
enable/disable control bit is located in a 0ode register that does not have any PDA
0ode controls.
In PDA 0ode, the device captures DQ6 using DQS signals the sa0e as in a nor0al
WRITE operation; however, dyna0ic ODT is not supported. Extra care is required for
the ODT setting. If RTT(NOM) MR1 [16:8] = enable, device data ter0ination needs to be
controlled by the ODT pin, and applies the sa0e ti0ing para0eters (defined below).
Symbol
DODTLon
DODTLoff
tADC
Parameter
Direct ODT turnon latency
Direct ODT turn off latency
RTT change timing skew
tAONAS
tAOFAS
Asynchronous RTT(NOM) turn-on delay
Asynchronous RTT(NOM) turn-off delay
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Per-DRAM Addressability
Figure 56: PDA Operation Enabled, BL8
&.BF
&.BW
05ꢋꢀ$ꢃꢀ ꢀꢇ
ꢌ3'$ꢀHQDEOHꢎ
056
056
056
W02'
&:/ꢓ$/ꢓ3/
W05'B3'$
'46BW
'46BF
'4ꢅ
W3'$B6
'2'7/RIIꢀ ꢀ:/ꢏꢋ
W3'$B+
2'7
'2'7/RQꢀ ꢀ:/ꢏꢋ
5
5
5
5
77ꢌ3DUNꢎ
77
77ꢌ3DUNꢎ
77ꢌ120ꢎ
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
Note:
Figure 57: PDA Operation Enabled, BC4
CK_c
CK_t
MR3 A4 = 1
(PDA enable)
MRS
MRS
MRS
tMOD
CWL+AL+PL
tMRD_PDA
DQS_t
DQS_c
DQ0
tPDA_S
DODTLoff = WL-3
tPDA_H
ODT
RTT
DODTLon = WL-3
RTT(Park)
RTT(NOM)
RTT(Park)
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
Note:
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Per-DRAM Addressability
Figure 58: MRS PDA Exit
&.BF
&.BW
05ꢋꢀ$ꢃꢀ ꢀꢅ
ꢌ3'$ꢀGLVDEOHꢎ
056
9DOLG
W02'B3'$
&:/ꢓ$/ꢓ3/
'46BW
'46BF
'4ꢅ
W3'$B6
'2'7/RIIꢀ ꢀ:/ꢀꢏꢀꢋ
W3'$B+
2'7
'2'7/RQꢀ ꢀ:/ꢀꢏꢀꢋ
5
5
5
5
77ꢌ3DUNꢎ
77
77ꢌ3DUNꢎ
77ꢌ120ꢎ
1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On.
Note:
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REFDQ Calibration
V
VREFDQ Calibration
The VREFDQ level, which is used by the DRAM DQ input receivers, is internally gener-
ated. The DRAM VREFDQ does not have a default value upon power-up and 0ust be set
to the desired value, usually via VREFDQ calibration 0ode. If PDA or PPR 0odes (hPPR or
sPPR) are used prior to VREFDQ calibration, VREFDQ should initially be set at the 0idpoint
between the VDD,0ax, and the LOW as deter0ined by the driver and ODT ter0ination
selected with wide voltage swing on the input levels and setup and hold ti0es of ap-
proxi0ately 6.75UI. The 0e0ory controller is responsible for VREFDQ calibration to de-
ter0ine the best internal VREFDQ level. The VREFDQ calibration is enabled/disabled via
MR±[7], MR±[±] selects Range 1 (±6% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of
VDDQ), and an MRS protocol using MR±[5:6] to adjust the VREFDQ level up and down.
MR±[±:6] bits can be altered using the MRS co00and if MR±[7] is disabled. The DRAM
controller will likely use a series of writes and reads in conjunction with VREFDQ adjust-
0ents to obtain the best VREFDQ, which in turn opti0izes the data eye.
The internal VREFDQ specification para0eters are voltage range, step size, VREF step
ti0e, VREF full step ti0e, and VREF valid level. The voltage operating range specifies the
0ini0u0 required VREF setting range for DDR4 SDRAM devices. The 0ini0u0 range is
defined by VREFDQ,0in and VREFDQ,0ax. As noted, a calibration sequence, deter0ined by
the DRAM controller, should be perfor0ed to adjust VREFDQ and opti0ize the ti0ing
and voltage 0argin of the DRAM data input receivers. The internal VREFDQ voltage value
0ay not be exactly within the voltage range setting coupled with the VREF set tolerance;
the device 0ust be calibrated to the correct internal VREFDQ voltage.
Figure 59: VREFDQ Voltage Range
VDDQ
VREF,max
VREF
range
VREF,min
V
V
SWING small
SWING large
System variance
Total range
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V
REFDQ Calibration
VREFDQ Range and Levels
Table 37: VREFDQ Range and Levels
MR6[5:0]
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111
01 1000
01 1001
Range 1 MR6[6] 0
60.00%
60.65%
61.30%
61.95%
62.60%
63.25%
63.90%
64.55%
65.20%
65.85%
66.50%
67.15%
67.80%
68.45%
69.10%
69.75%
70.40%
71.05%
71.70%
72.35%
73.00%
73.65%
74.30%
74.95%
75.60%
76.25%
Range 2 MR6[6] 1
45.00%
45.65%
46.30%
46.95%
47.60%
48.25%
48.90%
49.55%
50.20%
50.85%
51.50%
52.15%
52.80%
53.45%
54.10%
54.75%
55.40%
56.05%
56.70%
57.35%
58.00%
58.65%
59.30%
59.95%
60.60%
61.25%
MR6[5:0]
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111
10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111
11 0000
11 0001
11 0010
Range 1 MR6[6] 0
76.90%
77.55%
78.20%
78.85%
79.50%
80.15%
80.80%
81.45%
82.10%
82.75%
83.40%
84.05%
84.70%
85.35%
86.00%
86.65%
87.30%
87.95%
88.60%
89.25%
89.90%
90.55%
91.20%
91.85%
92.50%
Range 2 MR6[6] 1
61.90%
62.55%
63.20%
63.85%
64.50%
65.15%
65.80%
66.45%
67.10%
67.75%
68.40%
69.05%
69.70%
70.35%
71.00%
71.65%
72.30%
72.95%
73.60%
74.25%
74.90%
75.55%
76.20%
76.85%
77.50%
11 0011 to 11 1111 = Reserved
VREFDQ Step Size
The VREF step size is defined as the step size between adjacent steps. VREF step size rang-
es fro0 6.5% VDDQ to 6.8% VDDQ. However, for a given design, the device has one value
for VREF step size that falls within the range.
The VREF set tolerance is the variation in the VREF voltage fro0 the ideal setting. This ac-
counts for accu0ulated error over 0ultiple steps. There are two ranges for VREF set tol-
erance uncertainty. The range of VREF set tolerance uncertainty is a function of nu0ber
of steps n.
The VREF set tolerance is 0easured with respect to the ideal line, which is based on the
MIN and MAX VREF value endpoints for a specified range. The internal VREFDQ voltage
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REFDQ Calibration
V
value 0ay not be exactly within the voltage range setting coupled with the VREF set tol-
erance; the device 0ust be calibrated to the correct internal VREFDQ voltage.
Figure 60: Example of VREF Set Tolerance and Step Size
Actual VREF
output
Straight line
(endpoint fit)
VREF
V
REF set
tolerance
VREF set
tolerance
VREF
step size
Digital Code
1. Maximum case shown.
Note:
VREFDQ Increment and Decrement Timing
The VREF incre0ent/decre0ent step ti0es are defined by VREF,ti0e. VREF,ti0e is defined
fro0 t6 to t1, where t1 is referenced to the VREF voltage at the final DC level within the
VREF valid tolerance (VREF,val_tol). The VREF valid level is defined by VREF,val tolerance to
qualify the step ti0e t1. This para0eter is used to insure an adequate RC ti0e constant
behavior of the voltage level change after any VREF incre0ent/decre0ent adjust0ent.
Note:
t6 is referenced to the MRS co00and clock
t1 is referenced to VREF,tol
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V
REFDQ Calibration
Figure 61: VREFDQ Timing Diagram for VREF,time Parameter
CK_c
CK_t
MRS
Command
DQ VREF
V
REF setting
adjustment
Old VREF setting
Updating VREF setting
VREF_time
New VREF setting
t0
t1
Don’t Care
VREFDQ calibration 0ode is entered via an MRS co00and, setting MR±[7] to 1 (6 disa-
bles VREFDQ calibration 0ode) and setting MR±[±] to either 6 or 1 to select the desired
range (MR±[5:6] are "Don't Care"). After VREFDQ calibration 0ode has been entered,
VREFDQ calibration 0ode legal co00ands 0ay be issued once tVREFDQE has been sat-
isfied. Legal co00ands for VREFDQ calibration 0ode are ACT, WR, WRA, RD, RDA, PRE,
DES, and MRS to set VREFDQ values, and MRS to exit VREFDQ calibration 0ode. Also, after
VREFDQ calibration 0ode has been entered, “du00y” WRITE co00ands are allowed
prior to adjusting the VREFDQ value the first ti0e VREFDQ calibration is perfor0ed after
initialization.
Setting VREFDQ values requires MR±[7] be set to 1 and MR±[±] be unchanged fro0 the
initial range selection; MR±[5:6] 0ay be set to the desired VREFDQ values. If MR±[7] is set
to 6, MR±[±:6] are not written. VREF,ti0e-short or VREF,ti0e-long 0ust be satisfied after each
MR± co00and to set VREFDQ value before the internal VREFDQ value is valid.
If PDA 0ode is used in conjunction with VREFDQ calibration, the PDA 0ode require-
0ent that only MRS co00ands are allowed while PDA 0ode is enabled is not waived.
That is, the only VREFDQ calibration 0ode legal co00ands noted above that 0ay be
used are the MRS co00ands: MRS to set VREFDQ values and MRS to exit VREFDQ calibra-
tion 0ode.
The last MR±[±:6] setting written to MR± prior to exiting VREFDQ calibration 0ode is the
range and value used for the internal VREFDQ setting. VREFDQ calibration 0ode 0ay be
exited when the DRAM is in idle state. After the MRS co00and to exit VREFDQ calibra-
tion 0ode has been issued, DES 0ust be issued until tVREFDQX has been satisfied
where any legal co00and 0ay then be issued. VREFDQ setting should be updated if the
die te0perature changes too 0uch fro0 the calibration te0perature.
The following are typical script when applying the above rules for VREFDQ calibration
routine when perfor0ing VREFDQ calibration in Range 1:
• MR±[7:±]16 [5:6]XXXXXXX.
– Subsequent legal co00ands while in VREFDQ calibration 0ode: ACT, WR, WRA, RD,
RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration 0ode).
• All subsequent VREFDQ calibration MR setting co00ands are MR±[7:±]16
[5:6]VVVVVV.
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REFDQ Calibration
V
– "VVVVVV" are desired settings for VREFDQ
.
• Issue ACT/WR/RD looking for pass/fail to deter0ine VCENT (0idpoint) as needed.
• To exit VREFDQ calibration, the last two VREFDQ calibration MR co00ands are:
– MR±[7:±]16 [5:6]VVVVVV* where VVVVVV* = desired value for VREFDQ
– MR±[7]6 [±:6]XXXXXXX to exit VREFDQ calibration 0ode.
.
The following are typical script when applying the above rules for VREFDQ calibration
routine when perfor0ing VREFDQ calibration in Range 2:
• MR±[7:±]11 [5:6]XXXXXXX.
– Subsequent legal co00ands while in VREFDQ calibration 0ode: ACT, WR, WRA, RD,
RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration 0ode).
• All subsequent VREFDQ calibration MR setting co00ands are MR±[7:±]11
[5:6]VVVVVV.
– "VVVVVV" are desired settings for VREFDQ
.
• Issue ACT/WR/RD looking for pass/fail to deter0ine VCENT (0idpoint) as needed.
• To exit VREFDQ calibration, the last two VREFDQ calibration MR co00ands are:
– MR±[7:±]11 [5:6]VVVVVV* where VVVVVV* = desired value for VREFDQ
– MR±[7]6 [±:6]XXXXXXX to exit VREFDQ calibration 0ode.
.
Note:
Range 0ay only be set or changed when entering VREFDQ calibration 0ode;
changing range while in or exiting VREFDQ calibration 0ode is illegal.
Figure 62: VREFDQ Training Mode Entry and Exit Timing Diagram
T0
T1
Ta0
Ta1
Tb0
DES
Tb1
Tc0
DES
Tc1
Td0
Td1
WR
Td2
DES
CK_c
CK_t
MRS1,2
DES
Command
DES
MRS
DES
CMD
CMD
tVREFDQE
tVREFDQX
VREFDQ training on
New VREFDQ
value or write
New VREFDQ
value or write
VREFDQ training off
Don’t Care
1. New VREFDQ values are not allowed with an MRS command during calibration mode en-
try.
Notes:
2. Depending on the step size of the latest programmed VREF value, VREF must be satisfied
before disabling VREFDQ training mode.
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REFDQ Calibration
V
Figure 63: VREF Step: Single Step Size Increment Case
VREF
Voltage
VREF
(VDDQ(DC)
)
VREF,val_tol
Step size
t1
Time
Figure 64: VREF Step: Single Step Size Decrement Case
VREF
Voltage
t1
Step size
VREF,val_tol
VREF
(VDDQ(DC)
)
Time
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REFDQ Calibration
V
Figure 65: VREF Full Step: From VREF,min to VREF,maxCase
VREF
Voltage
VREF
(VDDQ(DC))
VREF,max
VREF,val_tol
Full range
step
t1
VREF,min
Time
Figure 66: VREF Full Step: From VREF,max to VREF,minCase
VREF,max
VREF
Voltage
Full range
step
t1
VREF,val_tol
VREF,min
VREF
(VDDQ(DC)
)
Time
VREFDQ Target Settings
The VREFDQ initial settings are largely dependant on the ODT ter0ination settings. The
table below shows all of the possible initial settings available for VREFDQ training; it is
unlikely the lower ODT settings would be used in 0ost cases.
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REFDQ Calibration
V
Table 38: VREFDQ Settings (VDDQ = 1.2V)
RON
ODT
Vx – VIN LOW (mV)
VREFDQ (mv)
900
VREFDQ (%VDDQ
)
34 ohm
40 ohm
48 ohm
60 ohm
80 ohm
120 ohm
240 ohm
34 ohm
40 ohm
48 ohm
60 ohm
80 ohm
120 ohm
240 ohm
600
550
500
435
360
265
150
700
655
600
535
450
345
200
75%
875
73%
850
71%
34 ohm
815
68%
780
65%
732
61%
675
56%
950
79%
925
77%
900
75%
48 ohm
865
72%
825
69%
770
64%
700
58%
Figure 67: VREFDQ Equivalent Circuit
V
V
DDQ
DDQ
ODT
RXer
Vx
V
R
REFDQ
ON
(internal)
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Connectivity Test Mode
Connectivity Test Mode
Connectivity test (CT) 0ode is si0ilar to boundary scan testing but is designed to sig-
nificantly speed up the testing of electrical continuity of pin interconnections between
the device and the 0e0ory controller on the PC boards. Designed to work sea0lessly
with any boundary scan device, CT 0ode is supported in all ×4, ×8, and ×1± devices (JE-
DEC states CT 0ode for ×4 and ×8 is not required on 4Gb and is an optional feature on
8Gb and above).
Contrary to other conventional shift-register-based test 0odes, where test patterns are
shifted in and out of the 0e0ory devices serially during each clock, the CT 0ode allows
test patterns to be entered on the test input pins in parallel and the test results to be
extracted fro0 the test output pins of the device in parallel. These two functions are al-
so perfor0ed at the sa0e ti0e, significantly increasing the speed of the connectivity
check. When placed in CT 0ode, the device appears as an asynchronous device to the
external controlling agent. After the input test pattern is applied, the connectivity test
results are available for extraction in parallel at the test output pins after a fixed propa-
gation delay ti0e.
Note: A reset of the device is required after exiting CT 0ode (see RESET and Initializa-
tion Procedure).
Pin Mapping
Only digital pins can be tested using the CT 0ode. For the purposes of a connectivity
check, all the pins used for digital logic in the device are classified as one of the follow-
ing types:
• Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT 0ode.
In CT 0ode, the nor0al 0e0ory function inside the device is bypassed and the I/O
pins appear as a set of test input and output pins to the external controlling agent.
Additionally, the device will set the internal VREFDQ to VDDQ × 6.5 during CT 0ode
(this is the only ti0e the DRAM takes direct control over setting the internal VREFDQ).
The TEN pin is dedicated to the connectivity check function and will not be used dur-
ing nor0al device operation.
• Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the
device. When de-asserted, these output pins will be High-Z. The CS_n pin in the de-
vice serves as the CS_n pin in CT 0ode.
• Test input: A group of pins used during nor0al device operation designated as test
input pins. These pins are used to enter the test pattern in CT 0ode.
• Test output: A group of pins used during nor0al device operation designated as test
output pins. These pins are used for extraction of the connectivity test results in CT
0ode.
• RESET_n: This pin 0ust be fixed high level during CT 0ode, as in nor0al function.
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Connectivity Test Mode
Table 39: Connectivity Mode Pin Description and Switching Levels
CT Mode
Pins
Pin Name During Normal Memory Operation
Switching Level
CMOS (20%/80% VDD
VREFCA 200mV
Notes
Test enable
Chip select
TEN
)
1, 2
3
CS_n
BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR
VREFCA 200mV
3
A
Test
input
B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n
VREFDQ 200mV
4
2, 5
2
C ALERT_n
CMOS (20%/80% VDD
CMOS (20%/80% VDD
VTT 100mV
)
)
D RESET_n
Test
DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c
6
output
1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW.
TEN must be LOW during normal operation.
Notes:
2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV
for DC HIGH and 240mV for DC LOW.)
3. VREFCA should be VDD/2.
4. VREFDQ should be VDDQ/2.
5. ALERT_n switching level is not a final setting.
6. VTT should be set to VDD/2.
Minimum Terms Definition for Logic Equations
The test input and output pins are related by the following equations, where INV de-
notes a logical inversion operation and XOR a logical exclusive OR operation:
MT6 = XOR (A1, A±, PAR)
MT1 = XOR (A8, ALERT_n, A9)
MT2 = XOR (A2, A5, A13)
MT3 = XOR (A6, A7, A11)
MT4 = XOR (CK_c, ODT, CAS_n/A15)
MT5 = XOR (CKE, RAS_n/A1±, A16/AP)
MT± = XOR (ACT_n, A4, BA1)
MT7 = ×1±: XOR (DMU_n/DBIU_n , DML_n/DBIL_n, CK_t)
= ×8: XOR (BG1, DML_n/DBIL_n, CK_t)
= ×4: XOR (BG1, CK_t)
MT8 = XOR (WE_n/A14, A12 / BC, BA6)
MT9 = XOR (BG6, A3, RESET_n and TEN)
Logic Equations for a ×4 Device, When Supported
DQ6 = XOR (MT6, MT1)
DQ1 = XOR (MT2, MT3)
DQ2 = XOR (MT4, MT5)
DQ3 = XOR (MT±, MT7)
DQS_t = MT8
DQS_c = MT9
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Connectivity Test Mode
Logic Equations for a ×8 Device, When Supported
DQ6 = MT6
DQ1 = MT1
DQ2 = MT2
DQ3 = MT3
DQ4 = MT4
DQ5 = MT5
DQ± = MT±
DQ7 = MT7
DQS_t = MT8
DQS_c = MT9
Logic Equations for a ×16 Device
DQ6 = MT6
DQ1 = MT1
DQ2 = MT2
DQ3 = MT3
DQ4 = MT4
DQ5 = MT5
DQ± = MT±
DQ7 = MT7
DQ16 = INV DQ2
DQ11 = INV DQ3
DQ12 = INV DQ4
DQ13 = INV DQ5
DQ14 = INV DQ±
DQ15 = INV DQ7
LDQS_t = MT8
LDQS_c = MT9
DQ8 = INV DQ6 UDQS_t = INV LDQS_t
DQ9 = INV DQ1 UDQS_c = INV LDQS_c
CT Input Timing Requirements
Prior to the assertion of the TEN pin, all voltage supplies, including VREFCA, 0ust be val-
id and stable and RESET_n registered high prior to entering CT 0ode. Upon the asser-
tion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and
CKE signals beco0e test inputs within tCTECT_Valid. The re0aining CT inputs beco0e
valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sa0pling, pro-
vided inputs were valid for at least tCT_Valid. While in CT 0ode, refresh activities in the
0e0ory arrays are not allowed; they are initiated either externally (auto refresh) or in-
ternally (self refresh).
The TEN pin 0ay be asserted after the DRAM has co0pleted power-on. After the DRAM
is initialized and VREFDQ is calibrated, CT 0ode 0ay no longer be used. The TEN pin
0ay be de-asserted at any ti0e in CT 0ode. Upon exiting CT 0ode, the states and the
integrity of the original content of the 0e0ory array are unknown. A full reset of the
0e0ory device is required.
After CT 0ode has been entered, the output signals will be stable within tCT_Valid after
the test inputs have been applied as long as TEN is 0aintained HIGH and CS_n is 0ain-
tained LOW.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Connectivity Test Mode
Figure 68: Connectivity Test Mode Entry
Ta
Tc
Td
Tb
CK_t
CK_c
Valid input
Valid input
tCKSRX
tIS
tCT_IS
tCT_IS
T = 10ns
CKE
Valid input
Valid input
tCTCKE_Valid
T = 200μs
T = 500μs
RESET_n
TEN
tCT_IS
tCTCKE_Valid>10ns
tCT_IS>0ns
tCT_Enable
CS_n
tCT_IS
CT Inputs
Valid input
tCT_Valid
Valid input
tCT_Valid
tCT_Valid
CT Outputs
Valid
Valid
Don’t Care
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8Gb: x8, x16 Automotive DDR4 SDRAM
Excessive Row Activation
Excessive Row Activation
Rows can be accessed a li0ited nu0ber of ti0es within a certain ti0e period before ad-
jacent rows require refresh. The 0axi0u0 activate count (MAC) is the 0axi0u0 nu0-
ber of activates that a single row can sustain within a ti0e interval of equal to or less
than the 0axi0u0 activate window (tMAW) before the adjacent rows need to be re-
freshed, regardless of how the activates are distributed over tMAW.
Micron's DDR4 devices auto0atically perfor0 a type of TRR 0ode in the background
and provide an MPR Page 3 MPR3[3:6] of 1666, indicating there is no restriction to the
nu0ber of ACTIVATE co00ands to a given row in a refresh period provided DRAM ti0-
ing specifications are not violated.
Table 40: MAC Encoding of MPR Page 3 MPR3
[7] [6] [5] [4] [3] [2] [1] [0]
MAC
Comments
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Untested
The device has not been tested for MAC.
tMAC = 700K
tMAC = 600K
tMAC = 500K
tMAC = 400K
tMAC = 300K
Reserved
tMAC = 200K
Unlimited
There is no restriction to the number of AC-
TIVATE commands to a given row in a re-
fresh period provided DRAM timing specifi-
cations are not violated.
x
x
x
x
x
x
x
x
x
x
x
x
1
:
0
:
0
:
1
:
Reserved
Reserved
Reserved
1
1
1
1
1. MAC encoding in MPR Page 3 MPR3.
Note:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Post Package Repair
Post Package Repair
Post Package Repair
JEDEC defines two 0odes of Post Package Repair (PPR): soft Post Package Repair (sPPR)
and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row 0aybe
altered; that is, sPPR is NOT a per0anent repair and even though it will repair a row, the
repair can be reversed, reassigned via another sPPR, or 0ade per0anent via hPPR.
Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR ad-
dress, further PPR co00ands to a previous hPPR section should not be perfor0ed, that
is, hPPR is a per0anent repair; once repaired, it cannot be reversed. The controller pro-
vides the failing row address in the hPPR/sPPR sequence to the device to perfor0 the
row repair. hPPR Mode and sPPR Mode 0ay not be enabled at the sa0e ti0e.
JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts how-
ever Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The
hPPR support is identified via an MPR read fro0 MPR Page 2, MPR6[7] and sPPR sup-
port is identified via an MPR read fro0 MPR Page 2, MPR6[±].
The JEDEC 0ini0u0 support require0ent for DDR4 PPR (hPPR or sPPR) is to provide
one row of repair per bank group (BG), x4/x8 have 4 BG and x1± has 2 BG; this is a total
of 4 repair rows available on x4/x8 and 2 repair rows available on x1±. Micron PPR sup-
port exceeds the JEDEC 0ini0u0 require0ents; Micron DDR4 DRAMs have at least
one row of repair for each bank which is essentially 4 row repairs per BG for a total of 1±
repair rows for x4 and x8 and 8 repair rows for x1±; a 4x increase in repair rows.
JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to
enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing
sPPR row repair addresses are not required to be cleared prior to entering hPPR 0ode.
Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a
sPPR row repair existing in a different bank.
sPPR followed by sPPR to same bank
When PPR is issued to a bank for the first ti0e and is a sPPR co00and, the repair row
will be a sPPR. When a subsequent sPPR is issued to the sa0e bank, the previous sPPR
repair row will be cleared and used for the subsequent sPPR address as the sPPR opera-
tion is non-persistent.
sPPR followed by hPPR to same bank
When a PPR is issued to a bank for the first ti0e and is a sPPR co00and, the repair row
will be a sPPR. When a subsequent hPPR is issued to the sa0e bank, the initial sPPR
repair row will be cleared and used for the hPPR address. If a further subsequent PPR
(hPPR or sPPR) is issued to the sa0e bank, the further subsequent PPR ( hPPR or sPPR)
repair row will not clear or overwrite the previous hPPR address as the hPPR operation
is persistent.
hPPR followed by hPPR or sPPR to same bank
When a PPR is issued to a bank for the first ti0e and is a hPPR co00and, the repair row
will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the sa0e bank, the
subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR
address as the initial hPPR is persistent.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
Hard Post Package Repair
All banks 0ust be precharged and idle. DBI and CRC 0odes 0ust be disabled. Both
sPPR and hPPR 0ust be disabled. sPPR is disabled with MR4[5] = 6. hPPR is disabled
with MR4[13] = 6, which is the nor0al state, and hPPR is enabled with MR4 [13]= 1,
which is the hPPR enabled state. There are two for0s of hPPR 0ode. Both for0s of
hPPR have the sa0e entry require0ent as defined in the sections below. The first co0-
0and sequence uses a WRA co00and and supports data retention with a REFRESH
operation except for the bank containing the row that is being repaired; JEDEC has re-
laxed this require0ent and allows BA[6] to be a don't care regarding the banks which
are not required to 0aintain data a REFRESH operation during hPPR. The second co0-
0and sequence uses a WR co00and (a REFRESH operation can't be perfor0ed in this
co00and sequence). The second co00and sequence doesn't support data retention
for the target DRAM.
hPPR Row Repair - Entry
As stated above, all banks 0ust be precharged and idle. DBI and CRC 0odes 0ust be
disabled, and all ti0ings 0ust be followed as shown in the ti0ing diagra0 that follows.
All other co00ands except those listed in the following sequences are illegal.
1. Issue MR4[13] 1 to enter hPPR 0ode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key co00ands (shown in the table below) to MR6
with each co00and separated by tMOD. The PPR guard key settings are the sa0e
whether perfor0ing sPPR or hPPR 0ode.
a. Any interruption of the key sequence by other co00ands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR co00ands, hPPR will not be enabled, and the progra00ing cycle
will result in a NOP.
c. When the hPPR entry sequence is interrupted and followed by ACT and WR
co00ands, these co00ands will be conducted as nor0al DRAM co0-
0ands.
d. JEDEC allows A±:6 to be "Don't Care" on 4Gb and 8Gb devices fro0 a sup-
plier perspective and the user should rely on vendor datasheet.
Table 41: PPR MR0 Guard Key Settings
MR0
BG1:0
BA1:0
A17:12
xxxxxx
xxxxxx
xxxxxx
xxxxxx
A11
A10
A9
0
A8
0
A7
1
A6:0
First guard key
Second guard key
Third Guard key
Fourth guard key
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1111111
1111111
1111111
1111111
1
1
1
1
1
1
1
1
1
hPPR Row Repair – WRA Initiated (REF Commands Allowed)
1. Issue an ACT co00and with failing BG and BA with the row address to be re-
paired.
2. Issue a WRA co00and with BG and BA of failing row address.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
a. The address 0ust be at valid levels, but the address is "Don't Care."
3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 6 through bit 7)
after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 6
through bit 7 are LOW. The bank under repair does not get the REFRESH
co00and applied to it.
b. Repair will not be initiated to the target DRAM if any DQ during bit 6
through bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If
HIGH is driven to all DQs of a DRAM consecutively for equal to or lon-
ger than 2tCK, then DRAM does not conduct hPPR and retains data if
REF co00and is properly issued; if all DQs are neither LOW for 4tCK
nor HIGH for equal to or longer than 2tCK, then hPPR 0ode execution
is unknown.
c. DQS should function nor0ally.
4. REF co00and 0ay be issued anyti0e after the WRA co00and followed by WL +
4nCK + tWR + tRP.
a. Multiple REF co00ands are issued at a rate of tREFI or tREFI/2, however
back-to-back REF co00ands 0ust be separated by at least tREFI/4 when
the DRAM is in hPPR 0ode.
b. All banks except the bank under repair will perfor0 refresh.
5. Issue PRE after tPGM ti0e so that the device can repair the target row during
tPGM ti0e.
a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
±. Issue MR4[13] 6 co00and to hPPR 0ode disable.
a. Wait tPGMPST for hPPR 0ode exit to co0plete.
b. After tPGMPST has expired, any valid co00and 0ay be issued.
The entire sequence fro0 hPPR 0ode enable through hPPR 0ode disable 0ay be re-
peated if 0ore than one repair is to be done.
After co0pleting hPPR 0ode, MR6 0ust be re-progra00ed to a prehPPR 0ode state if
the device is to be accessed.
After hPPR 0ode has been exited, the DRAM controller can confir0 if the target row
was repaired correctly by writing data into the target row and reading it back.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
Figure 69: hPPR WRA – Entry
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Figure 70: hPPR WRA – Repair and Exit
Te0
Tf0
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
Tk0
PRE
Tk1
Tm0
Tm1
DES
Tn0
CK_c
CK_t
CMD
ACT
BGf
BAf
WRA
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
REF/DES
N/A
REF/DES
N/A
REF/DES
MRSx
Valid
Valid
Valid
N/A
N/A
Valid
Valid
N/A
N/A
Valid
Valid
BG
BA
BGf
BAf
N/A
N/A
Valid
Valid
N/A
N/A
N/A
N/A
Valid
Valid
N/A
N/A
N/A
N/A
N/A
Valid
ADDR
CKE
(A13 = 0)
t t
WR + RP + 1nCK
WL = CWL+AL+PL
4nCK
DQS_t
DQS_c
1
DQs
bit 6
bit 0
bit 1
bit 7
t
t
t
t
PGMPST
RCD
PGM
PGM_Exit
All Banks
Precharged
and idle state
Normal
mode
hPPR Recognitio
hPPR Exit
hPPR Repair
hPPR Repair
hPPR Repair
Don’t Care
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed)
1. Issue an ACT co00and with failing BG and BA with the row address to be re-
paired.
2. Issue a WR co00and with BG and BA of failing row address.
a. The address 0ust be at valid levels, but the address is "Don't Care."
3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 6 through bit 7)
after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 6
through bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 6
through bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If
HIGH is driven to all DQs of a DRAM consecutively for equal to or lon-
ger than 2tCK, then DRAM does not conduct hPPR and retains data if
REF co00and is properly issued; if all DQs are neither LOW for 4tCK
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Hard Post Package Repair
nor HIGH for equal to or longer than 2tCK, then hPPR 0ode execution
is unknown.
c. DQS should function nor0ally.
4. REF co00ands 0ay NOT be issued at anyti0e while in PPT 0ode.
5. Issue PRE after tPGM ti0e so that the device can repair the target row during
tPGM ti0e.
a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target
row address.
±. Issue MR4[13] 6 co00and to hPPR 0ode disable.
a. Wait tPGMPST for hPPR 0ode exit to co0plete.
b. After tPGMPST has expired, any valid co00and 0ay be issued.
The entire sequence fro0 hPPR 0ode enable through hPPR 0ode disable 0ay be re-
peated if 0ore than one repair is to be done.
After co0pleting hPPR 0ode, MR6 0ust be re-progra00ed to a prehPPR 0ode state if
the device is to be accessed.
After hPPR 0ode has been exited, the DRAM controller can confir0 if the target row
was repaired correctly by writing data into the target row and reading it back.
Figure 71: hPPR WR – Entry
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CCMTD-1406124318-10419
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129
8Gb: x8, x16 Automotive DDR4 SDRAM
sPPR Row Repair
Figure 72: hPPR WR – Repair and Exit
Te0
Tf0
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
Tk0
PRE
Tk1
Tm0
Tm1
DES
Tn0
CK_c
CK_t
CMD
ACT
BGf
BAf
WR
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
MRSx
Valid
Valid
Valid
N/A
N/A
Valid
Valid
N/A
N/A
Valid
Valid
BG
BA
BGf
BAf
Valid
Valid
N/A
N/A
N/A
N/A
Valid
Valid
N/A
N/A
N/A
N/A
N/A
Valid
ADDR
CKE
(A13 = 0)
WL = CWL + AL + PL
4nCK
DQS_t
DQS_c
1
DQs
bit 6
bit 0
bit 1
bit 7
t
t
t
t
PGMPST
RCD
PGM
PGM_Exit
All Banks
Precharged
and idle state
Normal
hPPR Recognition
hPPR Exit
hPPR Repair
hPPR Repair
hPPR Repair
mode
Don’t Care
Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200
Parameter
Symbol
tPGM
Min
1000
2000
15
Max
Unit
hPPR programming time
×4, ×8
×16
–
–
–
–
ms
ms
ns
hPPR precharge exit time
hPPR exit time
tPGM_Exit
tPGMPST
50
μs
sPPR Row Repair
Soft post package repair (sPPR) is a way to quickly, but te0porarily, repair a row ele-
0ent in a bank on a DRAM device, where hPPR takes longer but per0anently repairs a
row ele0ent. sPPR 0ode is entered in a si0ilar fashion as hPPR, sPPR uses MR4[5]
while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 6, which is the nor0al state,
and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state.
sPPR requires the sa0e guard key sequence as hPPR to qualify the MR4 PPR entry. After
sPPR entry, an ACT co00and will capture the target bank and target row, herein seed
row, where the row repair will be 0ade. After tRCD ti0e, a WR co00and is used to se-
lect the individual DRAM, through the DQ bits, to transfer the repair address into an in-
ternal register in the DRAM. After a write recovery ti0e and PRE co00and, the sPPR
0ode can be exited and nor0al operation can resu0e.
The DRAM will retain the soft repair infor0ation as long as VDD re0ains within the op-
erating region unless rewritten by a subsequent sPPR entry to the sa0e bank. If DRAM
power is re0oved or the DRAM is reset, the soft repair will revert to the unrepaired
state. hPPR and sPPR should not be enabled at the sa0e ti0e; Micron sPPR does not
have to be disabled and cleared prior to entering hPPR 0ode.
With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR re-
quest is 0ade to the sa0e bank, the subsequently issued sPPR address will replace the
previous sPPR address. When the hPPR resource for a bank is used up, the bank should
be assu0ed to not have available resources for sPPR. If a repair sequence is issued to a
bank with no repair resource available, the DRAM will ignore the progra00ing se-
quence.
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8Gb: x8, x16 Automotive DDR4 SDRAM
sPPR Row Repair
The bank receiving sPPR change is expected to retain 0e0ory array data in all rows ex-
cept for the seed row and its associated row addresses. If the data in the 0e0ory array
in the bank under sPPR repair is not required to be retained, then the handling of the
seed row’s associated row addresses is not of interest and can be ignored. If the data in
the 0e0ory array is required to be retained in the bank under sPPR 0ode, then prior to
executing the sPPR 0ode, the seed row and its associated row addresses should be
backed up and subsequently restored after sPPR has been co0pleted. sPPR associated
seed row addresses are specified in the Table below; BA6 is not required by Micron
DRAMs however it is JEDEC reserved.
Table 43: sPPR Associated Rows
sPPR Associated Row Address
BA0*
A17
A16
A15
A14
A13
A1
A0
All banks 0ust be precharged and idle. DBI and CRC 0odes 0ust be disabled, and all
sPPR ti0ings 0ust be followed as shown in the ti0ing diagra0 that follows.
All other co00ands except those listed in the following sequences are illegal.
1. Issue MR4[5] 1 to enter sPPR 0ode enable.
a. All DQ are driven HIGH.
2. Issue four consecutive guard key co00ands (shown in the table below) to MR6
with each co00and separated by tMOD. Please note that JEDEC recently added
the four guard key entry used for hPPR to sPPR entry; early DRAMs 0ay not re-
quire four guard key entry code. A prudent controller design should acco00o-
date either option in case an earlier DRAM is used.
a. Any interruption of the key sequence by other co00ands, such as ACT, WR,
RD, PRE, REF, ZQ, and NOP, are not allowed.
b. If the guard key bits are not entered in the required order or interrupted with
other MR co00ands, sPPR will not be enabled, and the progra00ing cycle
will result in a NOP.
c. When the sPPR entry sequence is interrupted and followed by ACT and WR
co00ands, these co00ands will be conducted as nor0al DRAM co0-
0ands.
d. JEDEC allows A±:6 to be "Don't Care" on 4Gb and 8Gb devices fro0 a sup-
plier perspective and the user should rely on vendor datasheet.
Table 44: PPR MR0 Guard Key Settings
MR0
BG1:0
BA1:0
A17:12
xxxxxx
xxxxxx
xxxxxx
xxxxxx
A11
A10
A9
0
A8
0
A7
1
A6:0
First guard key
Second guard key
Third guard key
Fourth guard key
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1111111
1111111
1111111
1111111
1
1
1
1
1
1
1
1
1
3. After tMOD, issue an ACT co00and with failing BG and BA with the row address
to be repaired.
4. After tRCD, issue a WR co00and with BG and BA of failing row address.
a. The address 0ust be at valid levels, but the address is a "Don't Care."
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8Gb: x8, x16 Automotive DDR4 SDRAM
sPPR Row Repair
5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 6 through bit 7)
after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 6
through bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 6
through bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If
HIGH is driven to all DQs of a DRAM consecutively for equal to or lon-
ger than the first 2tCK, then DRAM does not conduct hPPR and retains
data if REF co00and is properly issued; if all DQs are neither LOW for
4tCK nor HIGH for equal to or longer than the first 2tCK, then hPPR
0ode execution is unknown.
c. DQS should function nor0ally.
±. REF co00and 0ay NOT be issued at anyti0e while in sPPR 0ode.
7. Issue PRE after tWR ti0e so that the device can repair the target row during tWR
ti0e.
a. Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired tar-
get row address.
8. Issue MR4[5] 6 co00and to sPPR 0ode disable.
a. Wait tPGMPST_s for sPPR 0ode exit to co0plete.
b. After tPGMPST_s has expired, any valid co00and 0ay be issued.
The entire sequence fro0 sPPR 0ode enable through sPPR 0ode disable 0ay be repea-
ted if 0ore than one repair is to be done.
After sPPR 0ode has been exited, the DRAM controller can confir0 if the target row
was repaired correctly by writing data into the target row and reading it back.
Figure 73: sPPR – Entry
7ꢅ
7ꢇ
7Dꢅ
7Dꢇ
7Eꢅ
7Eꢇ
7Fꢅ
7Fꢇ
7Gꢅ
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7Hꢅ
7Iꢅ
:5
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056ꢃ
9DOLG
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1ꢄ$
056ꢅ
ꢅꢅ
'(6
1ꢄ$
1ꢄ$
056ꢅ
ꢅꢅ
'(6
1ꢄ$
1ꢄ$
056ꢅ
ꢅꢅ
'(6
1ꢄ$
1ꢄ$
056ꢅ
ꢅꢅ
'(6
1ꢄ$
1ꢄ$
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'(6
1ꢄ$
1ꢄ$
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ꢅꢅ
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9DOLGꢀ
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QG
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1ꢄ$
1ꢄ$
1ꢄ$
1ꢄ$
9DOLG
1ꢄ$
ꢇ
ꢀ.H\
ꢈ
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'46BW
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ꢇ
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02'
02'
02'
02'
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8Gb: x8, x16 Automotive DDR4 SDRAM
hPPR/sPPR Support Identifier
Figure 74: sPPR – Repair, and Exit
Te0
Tf0
Tg0
Tg1
Th0
Th1
Tj0
Tj1
Tj2
Tk0
PRE
Tk1
DES
Tm0
Tm1
DES
Tn0
CK_c
CK_t
CMD
ACT
BGf
BAf
WR
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
DES
N/A
N/A
MRS4
Valid
Valid
Valid
N/A
N/A
Valid
Valid
N/A
N/A
Valid
Valid
BG
BA
BGf
BAf
Valid
Valid
N/A
N/A
N/A
N/A
Valid
Valid
N/A
N/A
N/A
N/A
N/A
Valid
ADDR
CKE
(A5=0)
t
WR
WL = CWL + AL + PL
4nCK
DQS_t
DQS_c
1
DQs
bit 0
bit 1
bit 6
bit 7
t
t
PGM_s
t
t
RCD
PGM_Exit_s
PGMPST_s
All Banks
Precharged
and idle state
Normal
Mode
sPPR Recognitio
sPPR Exit
sPPR Repair
sPPR Repair
sPPR Repair
sPPR Repair
Don’t Care
Table 45: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200
Parameter
Symbol
Min
Max
Unit
sPPR programming time
tPGM_s
t RCD(MIN)+ WL + 4nCK
+ tWR(MIN)
–
ns
sPPR precharge exit time
sPPR exit time
tPGM_Exit_s
tPGMPST_s
20
tMOD
–
–
ns
ns
hPPR/sPPR Support Identifier
Table 46: DDR4 Repair Mode Support Identifier
MPR Page 2
A7
UI0
A6
UI1
A5
UI2
A4
A3
A2
A1
UI6
A0
UI7
UI3
UI4
UI5
MPR0
hPPR1
sPPR2
RTT_WR
Temp sensor
CRC
RTT_WR
1. 0 = hPPR mode is not available, 1 = hPPR mode is available.
2. 0 = sPPR mode is not available, 1 = sPPR mode is available.
3. Gray shaded areas are for reference only.
Notes:
ACTIVATE Command
The ACTIVATE co00and is used to open (activate) a row in a particular bank for subse-
quent access. The values on the BG[1:6] inputs select the bank group, the BA[1:6] inputs
select the bank within the bank group, and the address provided on inputs A[17:6] se-
lects the row within the bank. This row re0ains active (open) for accesses until a PRE-
CHARGE co00and is issued to that bank. A PRECHARGE co00and 0ust be issued be-
fore opening a different row in the sa0e bank. Bank-to-bank co00and ti0ing for AC-
TIVATE co00ands uses two different ti0ing para0eters, depending on whether the
banks are in the sa0e or different bank group. tRRD_S (short) is used for ti0ing be-
tween banks located in different bank groups. tRRD_L (long) is used for ti0ing between
banks located in the sa0e bank group. Another ti0ing restriction for consecutive ACTI-
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8Gb: x8, x16 Automotive DDR4 SDRAM
PRECHARGE Command
VATE co00ands [issued at tRRD (MIN)] is tFAW (fifth activate window). Because there
is a 0axi0u0 of four banks in a bank group, the tFAW para0eter applies across differ-
ent bank groups (five ACTIVATE co00ands issued at tRRD_L (MIN) to the sa0e bank
group would be li0ited by tRC).
Figure 75: tRRD Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
ACT
T11
DES
CK_c
CK_t
ACT
DES
DES
DES
DES
DES
DES
DES
DES
ACT
Command
tRRD_S
tRRD_L
Bank
Group
(BG)
BG b
Bank d
Row n
BG a
Bank c
Row n
BG b
Bank c
Row n
Bank
Address
Don’t Care
1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI-
VATE commands to different bank groups (that is, T0 and T4).
Notes:
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI-
VATE commands to the different banks in the same bank group (that is, T4 and T10).
Figure 76: tFAW Timing
T0
Ta0
ACT
Tb0
ACT
Tc0
ACT
Tc1
Tc2
Td0
ACT
Td1
NOP
CK_c
CK_t
ACT
Valid
Valid
Valid
Valid
Valid
Valid
Command
tRRD
tRRD
tRRD
tFAW
Bank
Group
(BG)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Bank
Valid
Valid
Valid
Valid
Valid
Address
Don’t Care
Time Break
1. tFAW; four activate windows.
Note:
PRECHARGE Command
The PRECHARGE co00and is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row activation
for a specified ti0e (tRP) after the PRECHARGE co00and is issued. An exception to
this is the case of concurrent auto precharge, where a READ or WRITE co00and to a
different bank is allowed as long as it does not interrupt the data transfer in the current
bank and does not violate any other ti0ing para0eters.
After a bank is precharged, it is in the idle state and 0ust be activated prior to any READ
or WRITE co00ands being issued to that bank. A PRECHARGE co00and is allowed if
there is no open row in that bank (idle state) or if the previously open row is already in
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8Gb: x8, x16 Automotive DDR4 SDRAM
REFRESH Command
the process of precharging. However, the precharge period will be deter0ined by the
last PRECHARGE co00and issued to the bank.
The auto precharge feature is engaged when a READ or WRITE co00and is issued with
A16 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay
the PRECHARGE operation until the ARRAY RESTORE operation has co0pleted. The
RAS lockout circuit feature allows the PRECHARGE operation to be partially or co0-
pletely hidden during burst READ cycles when the auto precharge feature is engaged.
The PRECHARGE operation will not begin until after the last data of the burst write se-
quence is properly stored in the 0e0ory array.
REFRESH Command
The REFRESH co00and (REF) is used during nor0al operation of the device. This
co00and is nonpersistent, so it 0ust be issued each ti0e a refresh is required. The de-
vice requires REFRESH cycles at an average periodic interval of tREFI. When CS_n,
RAS_n/A1±, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of
the clock, the device enters a REFRESH cycle. All banks of the SDRAM 0ust be pre-
charged and idle for a 0ini0u0 of the precharge ti0e, tRP (MIN), before the REFRESH
co00and can be applied. The refresh addressing is generated by the internal DRAM re-
fresh controller. This 0akes the address bits “Don’t Care” during a REFRESH co00and.
An internal address counter supplies the addresses during the REFRESH cycle. No con-
trol of the external address bus is required once this cycle has started. When the RE-
FRESH cycle has co0pleted, all banks of the SDRAM will be in the precharged (idle)
state. A delay between the REFRESH co00and and the next valid co00and, except
DES, 0ust be greater than or equal to the 0ini0u0 REFRESH cycle ti0e tRFC (MIN),
as shown in Figure 77 (page 13±).
Note: The tRFC ti0ing para0eter depends on 0e0ory density.
In general, a REFRESH co00and needs to be issued to the device regularly every tREFI
interval. To allow for i0proved efficiency in scheduling and switching between tasks,
so0e flexibility in the absolute refresh interval is provided for postponing and pulling-
in the REFRESH co00and. A li0ited nu0ber REFRESH co00ands can be postponed
depending on refresh 0ode: a 0axi0u0 of 8 REFRESH co00ands can be postponed
when the device is in 1X refresh 0ode; a 0axi0u0 of 1± REFRESH co00ands can be
postponed when the device is in 2X refresh 0ode; and a 0axi0u0 of 32 REFRESH
co00ands can be postponed when the device is in 4X refresh 0ode.
When 8 consecutive REFRESH co00ands are postponed, the resulting 0axi0u0 inter-
val between the surrounding REFRESH co00ands is li0ited to 9 × tREFI (see Figure 78
(page 13±)). For both the 2X and 4X refresh 0odes, the 0axi0u0 consecutive RE-
FRESH co00ands allowed is li0ited to 17 × tREFI2 and 3± × tREFI4, respectively.
A li0ited nu0ber REFRESH co00ands can be pulled-in as well. A 0axi0u0 of 8 addi-
tional REFRESH co00ands can be issued in advance or “pulled-in” in 1X refresh 0ode,
a 0axi0u0 of 1± additional REFRESH co00ands can be issued when in advance in 2X
refresh 0ode, and a 0axi0u0 of 32 additional REFRESH co00ands can be issued in
advance when in 4X refresh 0ode. Each of these REFRESH co00ands reduces the
nu0ber of regular REFRESH co00ands required later by one. Note that pulling in
0ore than the 0axi0u0 allowed REFRESH co00ands in advance does not further re-
duce the nu0ber of regular REFRESH co00ands required later, so that the resulting
0axi0u0 interval between two surrounding REFRESH co00ands is li0ited to 9 × tRE-
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8Gb: x8, x16 Automotive DDR4 SDRAM
REFRESH Command
FI (Figure 79 (page 13±)), 18 × tRFEI2, or 3± × tREFI4. At any given ti0e, a 0axi0u0 of
1± REF co00ands can be issued within 2 × tREFI, 32 REF2 co00ands can be issued
within 4 × tREFI2, and ±4 REF4 co00ands can be issued within 8 × tREFI4.
Figure 77: REFRESH Command Timing
T0
T1
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Tc2
Tc3
CK_c
CK_t
REF
DES
REF
DES
Valid
Valid
Valid
Valid
Vaid
REF
Valid
Valid
Valid
Command
DE
DE
tRFC
tRFC (MIN)
tREFI (MAX 9 × tREFI)
DRAM must be idle
DRAM must be idle
Time Break
Don’t Care
1. Only DES commands are allowed after a REFRESH command is registered until tRFC
(MIN) expires.
Notes:
2. Time interval between two REFRESH commands may be extended to a maximum of 9 ×
tREFI.
Figure 78: Postponing REFRESH Commands (Example)
tREFI
9 × tREFI
W
tRFC
8 REF-Commands postponed
Figure 79: Pulling In REFRESH Commands (Example)
tREFI
9 × tREFI
W
tRFC
8 REF-Commands pulled-in
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8Gb: x8, x16 Automotive DDR4 SDRAM
Temperature-Controlled Refresh Mode
Temperature-Controlled Refresh Mode
During nor0al operation, te0perature-controlled refresh (TCR) 0ode disabled, the de-
vice 0ust have a REFRESH co00and issued once every tREFI, except for what is al-
lowed by posting (see REFRESH Co00and section). This 0eans a REFRESH co00and
0ust be issued once every 6.4875μs if TC is greater than or equal to 122°C, once every
6.975μs if TC is greater than or equal to 165°C, once every 1.95μs if TC is greater than or
equal to 95°C, once every 3.9μs if TC is greater than or equal to 85°C, and once every
7.8μs if TC is less than 85°C.
Table 47: Normal tREFI Refresh (TCR Disabled)
Normal Temperature
Extended Temperature
External Refresh
Period
Internal Refresh
Period
External Refresh
Internal Refresh
Period
Temperature
TC < 45°C
Period
3.9μs1
7.8μs
7.8μs
3.9μs1
45°C ≤ TC < 85°C
85°C ≤ TC < 95°C
95°C ≤ TC < 105°C
105°C ≤ TC ≤ 122°C
TC >= 122°C
N/A
N/A
N/A
N/A
3.9μs
1.95μs
3.9μs
N/A
N/A
N/A
0.975μs
0.4875μs
1. If TC is less than 85°C, the external refresh period can be 7.8μs instead of 3.9μs.
Notes:
2. If TC is higher than 85°C, the TCR must disable, the device must have a REFRESH com-
mand issued once every tREFI.
When TCR 0ode is enabled, the device will register the externally supplied REFRESH
co00and and adjust the internal refresh period to be longer than tREFI of the nor0al
te0perature range, when allowed, by skipping REFRESH co00ands with the proper
gear ratio. TCR 0ode has two ranges to select between the nor0al te0perature range
and the extended te0perature range; the correct range 0ust be selected so the internal
control operates correctly. The DRAM 0ust have the correct refresh rate applied exter-
nally; the internal refresh rate is deter0ined by the DRAM based upon the te0perature.
TCR Mode – Normal Temperature Range
REFRESH co00ands should be issued to the device with the refresh period equal to or
shorter than tREFI of nor0al te0perature range (–46°C to 85°C). In this 0ode, the sys-
te0 0ust guarantee that TC does not exceed 85°C. The device 0ay adjust the internal
refresh period to be longer than tREFI of the nor0al te0perature range by skipping ex-
ternal REFRESH co00ands with the proper gear ratio when TC is below 45°C. The in-
ternal refresh period is auto0atically adjusted inside the DRAM, and the DRAM con-
troller does not need to provide any additional control.
TCR Mode – Extended Temperature Range
REFRESH co00ands should be issued to the device with the refresh period equal to or
shorter than tREFI of extended te0perature range (85°C to 125°C). In this 0ode, the sys-
te0 0ust guarantee that the TC does not exceed 125°C. Even though the external re-
fresh supports the extended te0perature range, the device will adjust its internal re-
fresh period to tREFI of the nor0al te0perature range by skipping external REFRESH
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8Gb: x8, x16 Automotive DDR4 SDRAM
Temperature-Controlled Refresh Mode
co00ands with proper gear ratio when operating in the nor0al te0perature range (–
46°C to 85°C). The device 0ay adjust the internal refresh period to be longer than tREFI
of the nor0al te0perature range by skipping external REFRESH co00ands with the
proper gear ratio when TC is below 45°C. The internal refresh period is auto0atically
adjusted inside the DRAM, and the DRAM controller does not need to provide any addi-
tional control.
Table 48: Normal tREFI Refresh (TCR Enabled)
Normal Temperature Range
Extended Temperature Range
External Refresh Internal Refresh
Period Period
External Refresh
Period
Internal Refresh
Period
Temperature
TC < 45°C
7.8μs
7.8μs
>> 7.8μs
>=7.8μs
3.9μs1
>> 3.9μs
>3.9μs
3.9μs
N/A
45°C ≤ TC < 85°C
85°C ≤ TC < 95°C
95°C ≤ TC < 105°C
105°C ≤ TC ≤ 122°C
TC > 122°C
N/A
N/A
N/A
N/A
3.9μs
1.95μs
0.975μs
0.4875μs
N/A
N/A
1. If the external refresh period is 7.8μs, the device will refresh internally at half the listed
refresh rate and will violate refresh specifications.
Note:
Figure 80: TCR Mode Example1
Controller
95°C to 85°C
REFRESH
Below 45°C
REFRESH
85°C to 45°C
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
External
tREFI
<3.9μs
Internal
tREFI
3.9μs
Internal
tREFI
>3.9μs
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
Internal
tREFI
>>3.9μs
REFRESH
REFRESH
REFRESH
REFRESH
REFRESH
External REFRESH
commands are not
ignored
Every other
external REFRESH
ignored
At low temperature,
more REFRESH commands
can be ignored
Controller issues REFRESH
commands at extended
temperature rate
1. TCR enabled with extended temperature range selected.
Note:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Fine Granularity Refresh Mode
Fine Granularity Refresh Mode
Mode Register and Command Truth Table
The REFRESH cycle ti0e (tRFC) and the average refresh interval (tREFI) can be pro-
gra00ed by the MRS co00and. The appropriate setting in the 0ode register will set a
single set of REFRESH cycle ti0es and average refresh interval for the device (fixed
0ode), or allow the dyna0ic selection of one of two sets of REFRESH cycle ti0es and
average refresh interval for the device (on-the-fly 0ode [OTF]). OTF 0ode 0ust be ena-
bled by MRS before any OTF REFRESH co00and can be issued.
Table 49: MRS Definition
MR3[8]
MR3[7]
MR3[6]
Refresh Rate Mode
Normal mode (fixed 1x)
Fixed 2x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fixed 4x
Reserved
Reserved
On-the-fly 1x/2x
On-the-fly 1x/4x
Reserved
There are two types of OTF 0odes (1x/2x and 1x/4x 0odes) that are selectable by pro-
gra00ing the appropriate values into the 0ode register. When either of the two OTF
0odes is selected, the device evaluates the BG6 bit when a REFRESH co00and is is-
sued, and depending on the status of BG6, it dyna0ically switches its internal refresh
configuration between 1x and 2x (or 1x and 4x) 0odes, and then executes the corre-
sponding REFRESH operation.
Table 50: REFRESH Command Truth Table
A[9:0],
RAS_n/A CAS_n/A WE_n/
A10/
AP
A[12:11], MR3[8:6
Refresh
Fixed rate
OTF: 1x
OTF: 2x
OTF: 4x
CS_n
ACT_n
15
14
A13
BG1
V
BG0
V
A[20:16]
]
L
L
L
L
H
H
H
H
L
L
H
V
V
V
V
V
V
V
V
0vv
1vv
101
110
L
L
H
V
L
L
L
H
V
H
L
L
H
V
H
tREFI and tRFC Parameters
The default refresh rate 0ode is fixed 1x 0ode where REFRESH co00ands should be
issued with the nor0al rate; that is, tREFI1 = tREFI(base) (for TC 85°C), and the dura-
tion of each REFRESH co00and is the nor0al REFRESH cycle ti0e (tRFC1). In 2x
0ode (either fixed 2x or OTF 2x 0ode), REFRESH co00ands should be issued to the
device at the double frequency (tREFI2 = tREFI(base)/2) of the nor0al refresh rate. In 4x
0ode, the REFRESH co00and rate should be quadrupled (tREFI4 = tREFI(base)/4). Per
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8Gb: x8, x16 Automotive DDR4 SDRAM
Fine Granularity Refresh Mode
each 0ode and co00and type, the tRFC para0eter has different values as defined in
the following table.
For discussion purposes, the REFRESH co00and that should be issued at the nor0al
refresh rate and has the nor0al REFRESH cycle duration 0ay be referred to as an REF1x
co00and. The REFRESH co00and that should be issued at the double frequency
(tREFI2 = tREFI(base)/2) 0ay be referred to as a REF2x co00and. Finally, the REFRESH
co00and that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) 0ay be
referred to as a REF4x co00and.
In the fixed 1x refresh rate 0ode, only REF1x co00ands are per0itted. In the fixed 2x
refresh rate 0ode, only REF2x co00ands are per0itted. In the fixed 4x refresh rate
0ode, only REF4x co00ands are per0itted. When the on-the-fly 1x/2x refresh rate
0ode is enabled, both REF1x and REF2x co00ands are per0itted. When the OTF
1x/4x refresh rate 0ode is enabled, both REF1x and REF4x co00ands are per0itted.
Table 51: tREFI and tRFC Parameters
Refresh Mode Parameter
2Gb
4Gb
8Gb
Units
μs
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
tREFI (base)
7.8
7.8
7.8
1x mode
2x mode
4x mode
tREFI1
-40°C ≤ TC ≤ 85°C
85°C ≤ TC ≤ 95°C
95°C ≤ TC ≤ 105°C
105°C ≤ TC ≤ 125°C
tREFI(base)
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
160
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
110
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
tREFI(base)/32
90
tREFI(base)
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
260
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
160
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
tREFI(base)/32
110
tREFI(base)
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
350
tREFI(base)/2
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
260
tREFI(base)/4
tREFI(base)/8
tREFI(base)/16
tREFI(base)/32
160
tRFC1
tREFI2
-40°C ≤ TC ≤ 85°C
85°C ≤ TC ≤ 95°C
95°C ≤ TC ≤ 105°C
105°C ≤ TC ≤ 125°C
tRFC2
tREFI4
-40°C ≤ TC ≤ 85°C
85°C ≤ TC ≤ 95°C
95°C ≤ TC ≤ 105°C
105°C ≤ TC ≤ 125°C
tRFC4
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Figure 81: 4Gb with Fine Granularity Refresh Mode Example
Normal Temperature Operation – –40°C to 85°C
Extended Temperature Operation – –40°C to 125°C
1x Mode
2x Mode
4x Mode
1x Mode
2x Mode
4x Mode
(–40°C to 85°C)
(–40°C to 85°C)
(–40°C to 85°C)
(–40°C to 125°C)
(–40°C to 125°C)
(–40°C to 125°C)
REF@260ns
REF@260ns
REF@260ns
REF@160ns
REF@110ns
REF@110ns
REF@110ns
REF@260ns
REF@260ns
REF@260ns
REF@260ns
REF@260ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@160ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@110ns
REF@160ns
REF@110ns
REF@110ns
REF@110ns
REF@160ns
REF@160ns
REF@160ns
REF@110ns
REF@110ns
REF@110ns
8Gb: x8, x16 Automotive DDR4 SDRAM
Fine Granularity Refresh Mode
1. tREFI value is dependent on operating temperature range. See Table 51.
Note:
Changing Refresh Rate
If the refresh rate is changed by either MRS or OTF. New tREFI and tRFC para0eters will
be applied fro0 the 0o0ent of the rate change. When the REF1x co00and is issued to
the DRAM, tREF1 and tRFC1 are applied fro0 the ti0e that the co00and was issued;
when the REF2x co00and is issued, tREF2 and tRFC2 should be satisfied.
Figure 82: OTF REFRESH Command Timing
CK_c
CK_t
Command
DES
REF1
DS
DES
DES
Valid
Vaid
REF2
DES
DS
RFC2 (MIN)
Valid
DS
REF2
DES
t
t
RFC1 (MIN)
t
t
REFI1
REFI2
Don’t Care
The following conditions 0ust be satisfied before the refresh rate can be changed. Oth-
erwise, data retention cannot be guaranteed.
• In the fixed 2x refresh rate 0ode or the OTF 1x/2x refresh 0ode, an even nu0ber of
REF2x co00ands 0ust be issued because the last change of the refresh rate 0ode
with an MRS co00and before the refresh rate can be changed by another MRS co0-
0and.
• In the OTF1x/2x refresh rate 0ode, an even nu0ber of REF2x co00ands 0ust be is-
sued between any two REF1x co00ands.
• In the fixed 4x refresh rate 0ode or the OTF 1x/4x refresh 0ode, a 0ultiple-of-four
nu0ber of REF4x co00ands 0ust be issued because the last change of the refresh
rate with an MRS co00and before the refresh rate can be changed by another MRS
co00and.
• In the OTF1x/4x refresh rate 0ode, a 0ultiple-of-four nu0ber of REF4x co00ands
0ust be issued between any two REF1x co00ands.
There are no special restrictions for the fixed 1x refresh rate 0ode. Switching between
fixed and OTF 0odes keeping the sa0e rate is not regarded as a refresh rate change.
Usage with TCR Mode
If the te0perature controlled refresh 0ode is enabled, only the nor0al 0ode (fixed 1x
0ode, MR3[8:±] = 666) is allowed. If any other refresh 0ode than the nor0al 0ode is
selected, the te0perature controlled refresh 0ode 0ust be disabled.
Self Refresh Entry and Exit
The device can enter self refresh 0ode anyti0e in 1x, 2x, and 4x 0ode without any re-
striction on the nu0ber of REFRESH co00ands that have been issued during the
0ode before the self refresh entry. However, upon self refresh exit, extra REFRESH co0-
0and(s) 0ay be required, depending on the condition of the self refresh entry.
The conditions and require0ents for the extra REFRESH co00and(s) are defined as
follows:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Fine Granularity Refresh Mode
• In the fixed 2x refresh rate 0ode or the enable-OTF 1x/2x refresh rate 0ode, it is rec-
o00ended there be an even nu0ber of REF2x co00ands before entry into self re-
fresh after the last self refresh exit, REF1x co00and, or MRS co00and that set the
refresh 0ode. If this condition is 0et, no additional REFRESH co00ands are re-
quired upon self refresh exit. In the case that this condition is not 0et, either one ex-
tra REF1x co00and or two extra REF2x co00ands 0ust be issued upon self refresh
exit. These extra REFRESH co00ands are not counted toward the co0putation of the
average refresh interval (tREFI).
• In the fixed 4x refresh rate 0ode or the enable-OTF 1x/4x refresh rate 0ode, it is rec-
o00ended there be a 0ultiple-of-four nu0ber of REF4x co00ands before entry in-
to self refresh after the last self refresh exit, REF1x co00and, or MRS co00and that
set the refresh 0ode. If this condition is 0et, no additional refresh co00ands are re-
quired upon self refresh exit. When this condition is not 0et, either one extra REF1x
co00and or four extra REF4x co00ands 0ust be issued upon self refresh exit. These
extra REFRESH co00ands are not counted toward the co0putation of the average
refresh interval (tREFI).
There are no special restrictions on the fixed 1x refresh rate 0ode.
This section does not change the require0ent regarding postponed REFRESH co0-
0ands. The require0ent for the additional REFRESH co00and(s) described above is
independent of the require0ent for the postponed REFRESH co00ands.
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SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH co00and can be used to retain data in the device, even if the rest
of the syste0 is powered down. When in self refresh 0ode, the device retains data with-
out external clocking. The device has a built-in ti0er to acco00odate SELF REFRESH
operation. The SELF REFRESH co00and is defined by having CS_n, RAS_n, CAS_n,
and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock.
Before issuing the SELF REFRESH ENTRY co00and, the device 0ust be idle with all
banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are
closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and
all ti0ings fro0 previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper,
tZQCS, and so on). After the SELF REFRESH ENTRY co00and is registered, CKE 0ust
be held LOW to keep the device in self refresh 0ode. The DRAM auto0atically disables
ODT ter0ination, regardless of the ODT pin, when it enters self refresh 0ode and auto-
0atically enables ODT upon exiting self refresh. During nor0al operation (DLL_on),
the DLL is auto0atically disabled upon entering self refresh and is auto0atically ena-
bled (including a DLL reset) upon exiting self refresh.
When the device has entered self refresh 0ode, all of the external control signals, except
CKE and RESET_n, are “Don’t Care.” For proper SELF REFRESH operation, all power
supply and reference pins (VDD, VDDQ, VSS, VSSQ, VPP, and VREFCA) 0ust be at valid levels.
The DRAM internal VREFDQ generator circuitry 0ay re0ain on or be turned off. If the
internal VREFDQ circuit is on in self refresh, the first WRITE operation or first write-level-
ing activity 0ay occur after tXS ti0e after self refresh exit. If the DRAM internal VREFDQ
circuitry is turned off in self refresh, it ensures that the VREFDQ generator circuitry is
powered up and stable within the tXSDLL period when the DRAM exits the self refresh
state. The first WRITE operation or first write-leveling activity 0ay not occur earlier
than tXSDLL after exiting self refresh. The device initiates a 0ini0u0 of one REFRESH
co00and internally within the tCKE period once it enters self refresh 0ode.
The clock is internally disabled during a SELF REFRESH operation to save power. The
0ini0u0 ti0e that the device 0ust re0ain in self refresh 0ode is tCKESR/
tCKESR_PAR. The user 0ay change the external clock frequency or halt the external
clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock 0ust
be restarted and tCKSRX 0ust be stable before the device can exit SELF REFRESH oper-
ation.
The procedure for exiting self refresh requires a sequence of events. First, the clock 0ust
be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT co00and (SRX,
co0bination of CKE going HIGH and DESELECT on the co00and bus) is registered,
the following ti0ing delay 0ust be satisfied:
Co00ands that do not require locked DLL:
t
• XS = ACT, PRE, PREA, REF, SRE, and PDE.
t
• XS_FAST = ZQCL, ZQCS, and MRS co00ands. For an MRS co00and, only DRAM
CL, WR/RTP register, and DLL reset in MR6; RTT(NOM) register in MR1; the CWL and
RTT(WR) registers in MR2; and gear-down 0ode register in MR3; WRITE and READ pre-
a0ble registers in MR4; RTT(PARK) register in MR5; tCCD_L/tDLLK and VREFDQ calibra-
tion value registers in MR± 0ay be accessed provided the DRAM is not in per-DRAM
0ode. Access to other DRAM 0ode registers 0ust satisfy tXS ti0ing. WRITE co0-
0ands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT
and dyna0ic ODT controlled by the WRITE co00and require a locked DLL.
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8Gb: x8, x16 Automotive DDR4 SDRAM
SELF REFRESH Operation
Co00ands that require locked DLL in the nor0al operating range:
t
• XSDLL – RD, RDS4, RDS8, RDA, RDAS4, and RDAS8 (unlike DDR3, WR, WRS4, WRS8,
WRA, WRAS4, and WRAS8 because synchronous ODT is required).
Depending on the syste0 environ0ent and the a0ount of ti0e spent in self refresh, ZQ
CALIBRATION co00ands 0ay be required to co0pensate for the voltage and te0pera-
ture drift described in the ZQ CALIBRATION Co00ands section. To issue ZQ CALIBRA-
TION co00ands, applicable ti0ing require0ents 0ust be satisfied (see the ZQ Calibra-
tion Ti0ing figure).
CKE 0ust re0ain HIGH for the entire self refresh exit period tXSDLL for proper opera-
tion except for self refresh re-entry. Upon exit fro0 self refresh, the device can be put
back into self refresh 0ode or power-down 0ode after waiting at least tXS period and
issuing one REFRESH co00and (refresh period of tRFC). The DESELECT co00and
0ust be registered on each positive clock edge during the self refresh exit interval tXS.
ODT 0ust be turned off during tXSDLL.
The use of self refresh 0ode introduces the possibility that an internally ti0ed refresh
event can be 0issed when CKE is raised for exit fro0 self refresh 0ode. Upon exit fro0
self refresh, the device requires a 0ini0u0 of one extra REFRESH co00and before it is
put back into self refresh 0ode.
Figure 83: Self Refresh Entry/Exit Timing
T0
T1
Ta0
Tb0
Tc0
Td0
Td1
Te0
Tf0
Tg0
CK_c
CK_t
tCKSRX
tCKSRE/tCKSRE_PAR
tCPDED
tIS
CKE
Valid
Valid
Valid
Valid
t
t
AR
CKESR/ CKESR_P
ODT
tXS_FAST
Valid1
Valid
Valid2
Valid
Command
ADDR
Valid3
Valid
DES
SRE
DES
SRX
tXS
tRP
tXSDLL
Enter Self Refresh
Exit Self Refresh
Don’t Care
Time Break
1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or
ZQCL commands are allowed.
Notes:
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
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8Gb: x8, x16 Automotive DDR4 SDRAM
SELF REFRESH Operation
Figure 84: Self Refresh Entry/Exit Timing with CAL Mode
T0
T1
T3
T4
T7
T8
T11
Ta0
Ta7
Ta8
Ta9
Ta10 Tb0
Tb1 Tb3
CK_c
CK_t
tCKSRX
tCKSRE
CS_n
Note 2
Note 3
Command
w/o CS_n
DES
DES
SRE
DES
DES
SRX
DES
DES
DES
DES
Valid
ADDR
CKE
Valid
Valid
tCAL
tCPDED
tXS_FAST
tCAL
Don’t Care
1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE = 8nCK, tCKSRX = 8nCK, tXS_FAST = tRFC4(min) +
Notes:
10ns
2. CS_n = HIGH, ACT_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 = "Don't Care."
3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or
ZQCL commands are allowed.
Self Refresh Abort
The exit ti0ing fro0 self refresh exit to the first valid co00and not requiring a locked
DLL is tXS. The value of tXS is (tRFC + 16ns). This delay allows any refreshes started by
the device ti0e to co0plete. tRFC continues to grow with higher density devices, so tXS
will grow as well. An MRS bit enables the self refresh abort 0ode. If the bit is disabled,
the controller uses tXS ti0ings (location MR4, bit 9). If the bit is enabled, the device
aborts any ongoing refresh and does not incre0ent the refresh counter. The controller
can issue a valid co00and not requiring a locked DLL after a delay of tXS_ABORT.
Upon exit fro0 self refresh, the device requires a 0ini0u0 of one extra REFRESH co0-
0and before it is put back into self refresh 0ode. This require0ent re0ains the sa0e
irrespective of the setting of the MRS bit for self refresh abort.
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8Gb: x8, x16 Automotive DDR4 SDRAM
SELF REFRESH Operation
Figure 85: Self Refresh Abort
T0
T1
Ta0
Tb0
Tc0
Td0
Td1
Te0
Tf0
Tg0
CK_c
CK_t
tCKSRX
tCKSRE/tCKSRE_PAR
tCPDED
tIS
CKE
Valid
Valid
Valid
Valid
t
t
AR
CKESR/ CKESR_P
ODT
tXS_FAST
Valid1
Valid
Valid2
Valid
Command
ADDR
Valid3
Valid
DES
SRE
DES
SRX
tXS_ABORT
tXSDLL
tRP
Enter Self Refresh
Exit Self Refresh
Don’t Care
Time Break
1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or
ZQCL commands are allowed.
Notes:
2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the
mode register.
3. Valid commands requiring a locked DLL.
Self Refresh Exit with NOP Command
Exiting self refresh 0ode using the NO OPERATION co00and (NOP) is allowed under a
specific syste0 application. This special use of NOP allows for a co00on co00and/
address bus between active DRAM devices and DRAM(s) in 0axi0u0 power saving
0ode. Self refresh 0ode 0ay exit with NOP co00ands provided:
• The device entered self refresh 0ode with CA parity and CAL disabled.
t
• MPX_S and tMPX_LH are satisfied.
• NOP co00ands are only issued during tMPX_LH window.
No other co00and is allowed during the tMPX_LH window after an SELF REFRESH EX-
IT (SRX) co00and is issued.
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8Gb: x8, x16 Automotive DDR4 SDRAM
SELF REFRESH Operation
Figure 86: Self Refresh Exit with NOP Command
Ta0
Ta1
Ta2
Ta3 Tb0
Tb1 Tb2
Tb3 Tc0
Tc1
Tc2
Tc3
Tc4
Td0 Td1 Td2 Td3
Te0
Te1
CK_c
CK_t
tCKSRX
CKE
ODT
Valid
tMPX_S
tMPX_LH
CS_n
Note 1, 2
Note 3
Valid
Command
ADDR
DES
DES
SRX
NOP
NOP
NOP
NOP
DES
DES
DES
Valid
Valid
DES
Valid
Valid
Valid
Valid
Valid
Valid
tXS
tXS + tXSDLL
Don’t Care
1. CS_n = LOW, ACT_n = HIGH, RAS_n/A16 = HIGH, CAS_n/A15 = HIGH, WE_n/A14 = HIGH
at Tb2 (NO OPERATION command).
Notes:
2. SRX at Tb2 is only allowed when DRAM shared command/address bus is under exiting
max power saving mode.
3. Valid commands not requiring a locked DLL.
4. Valid commands requiring locked DLL.
5. tXS_FAST and tXS_ABORT are not allowed this case.
6. Duration of CS_n LOW around CKE rising edge must satisfy tMPX_S and tMPX_LH as de-
fined max power saving mode AC parameters.
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Power-Down Mode
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW (along with a DESE-
LECT co00and). CKE is not allowed to go LOW when the following operations are in
progress: MRS co00and, MPR operations, ZQCAL operations, DLL locking, or READ/
WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW
ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the
power-down IDD specification will not be applied until those operations are co0plete.
The ti0ing diagra0s that follow illustrate power-down entry and exit.
For the fastest power-down exit ti0ing, the DLL should be in a locked state when pow-
er-down is entered. If the DLL is not locked during power-down entry, the DLL 0ust be
reset after exiting power-down 0ode for proper READ operation and synchronous ODT
operation. DRAM design provides all AC and DC ti0ing and voltage specification as
well as proper DLL operation with any CKE intensive operations as long as the control-
ler co0plies with DRAM specifications.
During power-down, if all banks are closed after any in-progress co00ands are co0-
pleted, the device will be in precharge power-down 0ode; if any bank is open after in-
progress co00ands are co0pleted, the device will be in active power-down 0ode.
Entering power-down deactivates the input and output buffers, excluding CK, CKE, and
RESET_n. In power-down 0ode, DRAM ODT input buffer deactivation is based on MRx
bit Y. If it is configured to 6b, the ODT input buffer re0ains on and the ODT input signal
0ust be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated
and the DRAM ODT input signal 0ay be floating and the device does not provide
RTT(NOM) ter0ination. Note that the device continues to provide RTT(Park) ter0ination if
it is enabled in the 0ode register MRa bit B. To protect internal delay on the CKE line to
block the input signals, 0ultiple DES co00ands are needed during the CKE switch off
and on cycle(s); this ti0ing period is defined as tCPDED. CKE LOW will result in deacti-
vation of co00and and address receivers after tCPDED has expired.
Table 52: Power-Down Entry Definitions
Power-
DRAM Status
DLL
Down Exit Relevant Parameters
Active
(a bank or more open)
On
Fast
Fast
tXP to any valid command.
Precharged
On
tXP to any valid command.
(all banks precharged)
The DLL is kept enabled during precharge power-down or active power-down. In pow-
er-down 0ode, CKE is LOW, RESET_n is HIGH, and a stable clock signal 0ust be 0ain-
tained at the inputs of the device. ODT should be in a valid state, but all other input sig-
nals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out
of power-down 0ode and in the reset state.) CKE LOW 0ust be 0aintained until tCKE
has been satisfied. Power-down duration is li0ited by 9 × tREFI.
The power-down state is synchronously exited when CKE is registered HIGH (along
with DES co00and). CKE HIGH 0ust be 0aintained until tCKE has been satisfied. The
ODT input signal 0ust be at a valid level when the device exits fro0 power-down 0ode,
independent of MRx bit Y if RTT(NOM) is enabled in the 0ode register. If RTT(NOM) is disa-
bled, the ODT input signal 0ay re0ain floating. A valid, executable co00and can be
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Power-Down Mode
applied with power-down exit latency, tXP, and/or tXPDLL after CKE goes HIGH. Power-
down exit latency is defined in the AC Specifications table.
Figure 87: Active Power-Down Entry and Exit
T0
T1
T2
Ta0
Ta1
DES
Tb0
DES
Tb1
Tc0
CK_c
CK_t
Command
CKE
Valid
DES
DES
DES
Valid
Valid
tPD
tIS
tIH
Valid
tCKE
tIH
tIS
ODT (ODT buffer enabled - MR5 [5] = 0)2
tIS
ODT (ODT buffer disbled - MR5 [5] = 1)3
Address
Valid
Valid
tCPDED
tXP
Enter
Exit
power-down
mode
power-down
mode
Don’t Care
Time Break
1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-
tion of the PRECHARGE command.
Notes:
2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting).
3. ODT pin driven to a valid state; MR5[5] = 1.
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Power-Down Mode
Figure 88: Power-Down Entry After Read and Read with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
DES
Tb1
CK_c
CK_t
RD or
RDA
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Command
DES
tIS
tCPDED
Valid
Valid
CKE
Valid
Address
tPD
RL = AL + CL
DQS_t, DQS_c
DQ BL8
DI
b
DI
DI
DI
DI
DI
DI
DI
b+1 b+2
b+3
b+4 b+5
b+6 b+7
DI
n
DI
DI
DI
DQ BC4
n+1 n+2
n+3
tRDPDEN
Power-Down
entry
Transitioning Data
Don’t Care
Time Break
1. DI n (or b) = data-in from column n (or b).
Note:
Figure 89: Power-Down Entry After Write and Write with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
DES
Tb2
DES
Tc0
Tc1
CK_c
CK_t
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Command
DES
tIS
tCPDED
Valid
Valid
CKE
Address
A10
Bank,
Col n
tPD
WL = AL + CWL
WR
DQS_t, DQS_c
DQ BL8
DI
b
DI
DI
DI
DI
DI
DI
DI
b + 1
b + 2
b + 3
b + 4
b + 5
b + 6
b + 7
Start internal
precharge
DI
n
DI
DI
DI
DQ BC4
n + 1
n + 2
n + 3
tWRAPDEN
Power-Down
entry
Transitioning Data
7LPHꢀ%UHDN
'RQ¶Wꢀ&DUH
1. DI n (or b) = data-in from column n (or b).
Notes:
2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-
tion of the PRECHARGE command.
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Power-Down Mode
Figure 90: Power-Down Entry After Write
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
DES
Tb1
DES
Tb2
DES
Tc0
Tc1
CK_c
CK_t
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Command
tIS
tCPDED
Valid
Valid
CKE
Address
A10
Bank,
Col n
tPD
WL = AL + CWL
tWR
DQS_t, DQS_c
DQ BL8
DI
b
DI
b + 1
DI
b + 2
DI
b + 3
DI
b + 4
DI
b + 5
DI
b + 6
DI
b + 7
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
DQ BC4
tWRPDEN
Power-Down
entry
Transitioning Data
Time Break
Don’t Care
1. DI n (or b) = data-in from column n (or b).
Note:
Figure 91: Precharge Power-Down Entry and Exit
T0
T1
T2
Ta0
Ta1
DES
Tb0
Tb1
DES
Tc0
CK_c
CK_t
Command
DES
DES
DES
DES
Valid
Valid
t
t
CPDED
CKE
t
t
IS
IH
CKE
Valid
t
t
IS
t
PD
XP
Enter
Exit
power-down
mode
power-down
mode
Don’t Care
Time Break
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Power-Down Mode
Figure 92: REFRESH Command to Power-Down Entry
T0
T1
T2
Ta0
DES
Tb0
DES
Tb1
DES
CK_c
CK_t
Command
Address
REF
DES
Valid
tCPDED
tIS
tPD
tCKE
Valid
CKE
tREFPDEN
Don’t Care
Time Break
Figure 93: Active Command to Power-Down Entry
T0
T1
T2
Ta0
DES
Tb0
Tb1
CK_c
CK_t
Command
Address
ACT
DES
DES
DES
Valid
t
CPDED
t
t
t
IS
PD
CKE
Valid
CKE
t
ACTPDEN
Don’t Care
Time Break
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Power-Down Mode
Figure 94: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry
T0
T1
T2
Ta0
Tb0
Tb1
CK_c
CK_t
PRE or
PREA
Command
Address
DES
DES
DES
Valid
Valid
tCPDED
tIS
tPD
tCKE
CKE
tPREPDEN
Don’t Care
Time Break
Figure 95: MRS Command to Power-Down Entry
T0
T1
Ta0
Ta1
DES
Tb0
Tb1
CK_c
CK_t
Command
Address
MRS
DES
DES
DES
Valid
t
CPDED
t
t
t
IS
PD
CKE
Valid
CKE
t
MRSPDEN
Don’t Care
Time Break
Power-Down Clarifications – Case 1
When CKE is registered LOW for power-down entry, tPD (MIN) 0ust be satisfied before
CKE can be registered HIGH for power-down exit. The 0ini0u0 value of para0eter
tPD (MIN) is equal to the 0ini0u0 value of para0eter tCKE (MIN) as shown in the
Ti0ing Para0eters by Speed Bin table. A detailed exa0ple of Case 1 follows.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Power-Down Mode
Figure 96: Power-Down Entry/Exit Clarifications – Case 1
T0
T1
T2
Ta0
Ta1
DES
Tb0
DES
Tb1
DES
Tb2
DES
CK_c
CK_t
Command
Valid
DES
DES
tPD
tPD
tIH
tIS
tIS
CKE
tIS
tCKE
tIH
Address
Valid
tCPDED
tCPDED
Enter
Exit
Enter
power-down
mode
power-down
mode
power-down
mode
Don’t Care
Time Break
Power-Down Entry, Exit Timing with CAL
Co00and/Address latency is used and additional ti0ing restrictions are required when
entering power-down, as noted in the following figures.
Figure 97: Active Power-Down Entry and Exit Timing with CAL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T14
T15
T16
T17
T18
CK_c
CK_t
CS_n
Command
w/o CS_n
DES
DES
DES
Valid
Valid
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
ADDR
CKE
Valid
tCAL
tCPDED
tPD
tCAL
tXP
Don’t Care
1. tCAL = 3nCK, tCPDED = 4nCK, tPD = 6nCK, tXP = 5nCK
Note:
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Power-Down Mode
Figure 98: REFRESH Command to Power-Down Entry with CAL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T14
T15
T16
T17
T18
CK_c
CK_t
CS_n
Command
w/o CS_n
DES
DES
DES
REF
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
ADDR
CKE
Valid
Valid
tCAL
tREFPDEN
tCPDED
tPD
tCAL
tXP
Don’t Care
1. tCAL = 3nCK, tREFPDEN = 1nCK, tCPDED = 4nCK, tPD = 6nCK, tXP = 5nCK
Note:
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ODT Input Buffer Disable Mode for Power-Down
ODT Input Buffer Disable Mode for Power-Down
ODT input buffer disable 0ode, when enabled via MR5[5], will prevent the device fro0
providing RTT(NOM) ter0ination during power-down for additional power savings.
The internal delay on the CKE path to disable the ODT buffer and block the sa0pled
output 0ust be accounted for; therefore, ODT 0ust be continuously driven to a valid
level, either LOW or HIGH, when entering power-down. However, after tCPDED (MIN)
has been satisfied, the ODT signal 0ay float.
When ODT input buffer disable 0ode is enabled, RTT(NOM) ter0ination corresponding
to sa0pled ODT after CKE is first registered LOW (and tANPD before that) 0ay not be
provided. tANPD is equal to (WL - 1) and is counted backward fro0 PDE, with CKE reg-
istered LOW.
Figure 99: ODT Power-Down Entry with ODT Buffer Disable Mode
diff_CK
CKE
tDODTLoff +1
tCPDED (MIN)
Floating
tADC (MIN)
ODT
DRAM_RTT_sync
(DLL enabled)
CA parity disabled
RTT(NOM)
RTT(Park)
tCPDED (MIN) + tADC (MAX)
DODTLoff
tADC (MIN)
DRAM_RTT_sync
(DLL enabled)
CA parity enabled
RTT(NOM)
RTT(Park)
tCPDED (MIN) + tADC (MAX) + PL
DODTLoff
DRAM_RTT_async
(DLL disabled)
RTT(NOM)
RTT(Park)
tAONAS (MIN)
tCPDED (MIN) + tAOFAS (MAX)
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ODT Input Buffer Disable Mode for Power-Down
Figure 100: ODT Power-Down Exit with ODT Buffer Disable Mode
diff_CK
CKE
ODT_A
(DLL enabled)
Floating
tADC (MAX)
tXP
RTT(Park)
RTT(NOM)
DRAM_RTT_A
DODTLon
tADC (MIN)
ODT_B
(DLL disabled)
Floating
tXP
RTT(Park)
RTT(NOM)
DRAM_RTT_B
tAONAS (MIN)
tAOFAS (MAX)
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CRC Write Data Feature
CRC Write Data Feature
CRC Write Data
The CRC write data feature takes the CRC generated data fro0 the DRAM controller and
co0pares it to the internally CRC generated data and deter0ines whether the two
0atch (no CRC error) or do not 0atch (CRC error).
Figure 101: CRC Write Data Operation
DRAM
Data
DRAM Controller
Data
CRC
engine
CRC
engine
CRC
Code
Data
CRC Code
CRC Code
Compare
CRC
WRITE CRC DATA Operation
A DRAM controller generates a CRC checksu0 using a 72-bit CRC tree and for0s the
write data fra0es, as shown in the following CRC data 0apping tables for the x4, x8, and
x1± configurations. A x4 device has a CRC tree with 32 input data bits used, and the re-
0aining upper 46 bits D[71:32] being 1s. A x8 device has a CRC tree with ±4 input data
bits used, and the re0aining upper 8 bits dependant upon whether DM_n/DBI_n is
used (1s are sent when not used). A x1± device has two identical CRC trees each, one for
the lower byte and one for the upper byte, with ±4 input data bits used by each, and the
re0aining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s
are sent when not used). For a x8 and x1± DRAMs, the DRAM 0e0ory controller 0ust
send 1s in transfer 9 location whether or not DM_n/DBI_n is used.
The DRAM checks for an error in a received code word D[71:6] by co0paring the re-
ceived checksu0 against the co0puted checksu0 and reports errors using the
ALERT_n signal if there is a 0is0atch. The DRAM can write data to the DRAM core
without waiting for the CRC check for full writes when DM is disabled. If bad data is
written to the DRAM core, the DRAM 0e0ory controller will try to overwrite the bad
data with good data; this 0eans the DRAM controller is responsible for data coherency
when DM is disabled. However, in the case where both CRC and DM are enabled via
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CRC Write Data Feature
MRS (that is, persistent 0ode), the DRAM will not write bad data to the core when a
CRC error is detected.
DBI_n and CRC Both Enabled
The DRAM co0putes the CRC for received written data D[71:6]. Data is not inverted
back based on DBI before it is used for co0puting CRC. The data is inverted back based
on DBI before it is written to the DRAM core.
DM_n and CRC Both Enabled
When both DM and write CRC are enabled in the DRAM 0ode register, the DRAM cal-
culates CRC before sending the write data into the array. If there is a CRC error, the
DRAM blocks the WRITE operation and discards the data. The Nonconsecutive WRITE
(BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group and
the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different
BankGroup figures in the WRITE Operation section show ti0ing differences when DM
is enabled.
DM_n and DBI_n Conflict During Writes with CRC Enabled
Both write DBI_n and DM_n can not be enabled at the sa0e ti0e; read DBI_n and
DM_n can be enabled at the sa0e ti0e.
CRC and Write Preamble Restrictions
When write CRC is enabled:
t
• And 1tCK WRITE prea0ble 0ode is enabled, a CCD_S or tCCD_L of 4 clocks is not
allowed.
• And 2tCK WRITE prea0ble 0ode is enabled, a CCD_S or tCCD_L of ± clocks is not
t
allowed.
CRC Simultaneous Operation Restrictions
When write CRC is enabled, neither MPR writes nor per-DRAM 0ode is allowed.
CRC Polynomial
The CRC polyno0ial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1.
A co0binatorial logic block i0ple0entation of this 8-bit CRC for 72 bits of data in-
cludes 272 two-input XOR gates contained in eight ±-XOR-gate-deep trees.
The CRC polyno0ial and co0binatorial logic used by DDR4 is the sa0e as used on
GDDR5.
The error coverage fro0 the DDR4 polyno0ial used is shown in the following table.
Table 53: CRC Error Detection Coverage
Error Type
Detection Capability
Random single-bit errors
Random double-bit errors
100%
100%
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CRC Write Data Feature
Table 53: CRC Error Detection Coverage (Continued)
Error Type
Detection Capability
Random odd count errors
100%
100%
Random multibit UI vertical column error
detection excluding DBI bits
CRC Combinatorial Logic Equations
0odule CRC8_D72;
// polyno0ial: (6 1 2 8)
// data width: 72
// convention: the first serial data bit is D[71]
//initial condition all 6 i0plied
// "^" = XOR
function [7:6]
nextCRC8_D72;
input [71:6] Data;
input [71:6] D;
reg [7:6] CRC;
begin
D = Data;
CRC[0] =
D[±9]^D[±8]^D[±7]^D[±±]^D[±4]^D[±3]^D[±6]^D[5±]^D[54]^D[53]^D[52]^D[56]^D[49
]^D[48]^D[45]^D[43]^D[46]^D[39]^D[35]^D[34]^D[31]^D[36]^D[28]^D[23]^D[21]^D[1
9]^D[18]^D[1±]^D[14]^D[12]^D[8]^D[7]^D[±]^D[6] ;
CRC[1] =
D[76]^D[±±]^D[±5]^D[±3]^D[±1]^D[±6]^D[57]^D[5±]^D[55]^D[52]^D[51]^D[48]^D[4±
]^D[45]^D[44]^D[43]^D[41]^D[39]^D[3±]^D[34]^D[32]^D[36]^D[29]^D[28]^D[24]^D[2
3]^D[22]^D[21]^D[26]^D[18]^D[17]^D[1±]^D[15]^D[14]^D[13]^D[12]^D[9]^D[±]^D[1
]^D[6];
CRC[2] =
D[71]^D[±9]^D[±8]^D[±3]^D[±2]^D[±1]^D[±6]^D[58]^D[57]^D[54]^D[56]^D[48]^D[47
]^D[4±]^D[44]^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[2
2]^D[17]^D[15]^D[13]^D[12]^D[16]^D[8]^D[±]^D[2]^D[1]^D[6];
CRC[3] =
D[76]^D[±9]^D[±4]^D[±3]^D[±2]^D[±1]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47
]^D[45]^D[44]^D[43]^D[46]^D[38]^D[35]^D[34]^D[36]^D[29]^D[2±]^D[25]^D[23]^D[1
8]^D[1±]^D[14]^D[13]^D[11]^D[9]^D[7]^D[3]^D[2]^D[1];
CRC[4] =
D[71]^D[76]^D[±5]^D[±4]^D[±3]^D[±2]^D[±6]^D[59]^D[5±]^D[52]^D[56]^D[49]^D[48
]^D[4±]^D[45]^D[44]^D[41]^D[39]^D[3±]^D[35]^D[31]^D[36]^D[27]^D[2±]^D[24]^D[1
9]^D[17]^D[15]^D[14]^D[12]^D[16]^D[8]^D[4]^D[3]^D[2];
CRC[5] =
D[71]^D[±±]^D[±5]^D[±4]^D[±3]^D[±1]^D[±6]^D[57]^D[53]^D[51]^D[56]^D[49]^D[47
]^D[4±]^D[45]^D[42]^D[46]^D[37]^D[3±]^D[32]^D[31]^D[28]^D[27]^D[25]^D[26]^D[1
8]^D[1±]^D[15]^D[13]^D[11]^D[9]^D[5]^D[4]^D[3];
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8Gb: x8, x16 Automotive DDR4 SDRAM
CRC Write Data Feature
CRC[6] =
D[±7]^D[±±]^D[±5]^D[±4]^D[±2]^D[±1]^D[58]^D[54]^D[52]^D[51]^D[56]^D[48]^D[47
]^D[4±]^D[43]^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[2±]^D[21]^D[19]^D[1
7]^D[1±]^D[14]^D[12]^D[16]^D[±]^D[5]^D[4];
CRC[7] =
D[±8]^D[±7]^D[±±]^D[±5]^D[±3]^D[±2]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48
]^D[47]^D[44]^D[42]^D[39]^D[38]^D[34]^D[33]^D[36]^D[29]^D[27]^D[22]^D[26]^D[1
8]^D[17]^D[15]^D[13]^D[11]^D[7]^D[±]^D[5];
nextCRC8_D72 = CRC;
Burst Ordering for BL8
DDR4 supports fixed WRITE burst ordering [A2:A1:A6 = 6:6:6] when write CRC is ena-
bled in BL8 (fixed).
CRC Data Bit Mapping
Table 54: CRC Data Mapping for x4 Devices, BL8
Transfer
Func-
tion
DQ0
DQ1
DQ2
DQ3
0
1
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
D8
D9
D10
D18
D26
D11
D19
D27
D12
D20
D28
D13
D21
D29
D14
D22
D30
D15
D23
D31
D16
D24
D17
D25
Table 55: CRC Data Mapping for x8 Devices, BL8
Transfer
Func-
tion
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
D8
D9
D10
D18
D26
D34
D42
D50
D58
D66
D11
D19
D27
D35
D43
D51
D59
D67
D12
D20
D28
D36
D44
D52
D60
D68
D13
D21
D29
D37
D45
D53
D61
D69
D14
D22
D30
D38
D46
D54
D62
D70
D15
D23
D31
D39
D47
D55
D63
D71
D16
D24
D32
D40
D48
D56
D64
D17
D25
D33
D41
D49
D57
D65
DM_n/
DBI_n
A x1± device is treated as two x8 devices; a x1± device will have two identical CRC trees
i0ple0ented. CRC[7:6] covers data bits D[71:6], and CRC[15:8] covers data bits
D[143:72].
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CRC Write Data Feature
Table 56: CRC Data Mapping for x16 Devices, BL8
Transfer
Func-
tion
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D1
D2
D3
D4
D5
D6
D7
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
D8
D9
D10
D18
D26
D34
D42
D50
D58
D66
D11
D19
D27
D35
D43
D51
D59
D67
D12
D20
D28
D36
D44
D52
D60
D68
D13
D21
D29
D37
D45
D53
D61
D69
D14
D22
D30
D38
D46
D54
D62
D70
D15
D23
D31
D39
D47
D55
D63
D71
D16
D24
D32
D40
D48
D56
D17
D25
D33
D41
D49
D57
D65
LDM_n/ D64
LDBI_n
DQ8
DQ9
D72
D80
D73
D81
D74
D82
D75
D83
D76
D84
D77
D85
D78
D86
D79
D87
D95
CRC8
CRC9
1
1
1
1
1
1
1
1
1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D88
D89
D90
D91
D92
D93
D94
CRC10
D96
D97
D98
D99
D100
D108
D116
D124
D132
D140
D101
D109
D117
D125
D133
D141
D102
D110
D118
D126
D134
D142
D103 CRC11
D111 CRC12
D119 CRC13
D127 CRC14
D135 CRC15
D104
D112
D120
D128
D105
D113
D121
D129
D137
D106
D114
D122
D130
D138
D107
D115
D123
D131
D139
UDM_n/ D136
UDBI_n
D143
1
CRC Enabled With BC4
If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data
first for BC4 writes.
CRC with BC4 Data Bit Mapping
For a x4 device, the CRC tree inputs are 1± data bits, and the inputs for the re0aining
bits are 1.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:6], D[15:12] are used as inputs to
D[11:8], and so forth, for the CRC tree.
Table 57: CRC Data Mapping for x4 Devices, BC4
Transfer
Function
0
1
2
3
4
5
6
7
8
9
A2 = 0
DQ0
DQ1
DQ2
D0
D8
D1
D9
D2
D3
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC4
CRC5
CRC6
D10
D18
D11
D19
D16
D17
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CRC Write Data Feature
Table 57: CRC Data Mapping for x4 Devices, BC4 (Continued)
Transfer
Function
0
1
2
3
4
5
6
7
8
9
DQ3
D24
D25
D26
D27
1
1
1
1
CRC3
CRC7
A2 = 1
DQ0
DQ1
DQ2
DQ3
D4
D5
D6
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
D12
D20
D28
D13
D21
D29
D14
D22
D30
D15
D23
D31
For a x8 device, the CRC tree inputs are 3± data bits.
When A2 = 6, the input bits D[±7:±4]) are used if DBI_n or DM_n functions are enabled;
if DBI_n and DM_n are disabled, then D[±7:±4]) are 1.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:6], D[15:12] are used as inputs to
D[11:8], and so forth, for the CRC tree. The input bits D[71:±8]) are used if DBI_n or
DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:±8]) are 1.
Table 58: CRC Data Mapping for x8 Devices, BC4
Transfer
Function
0
1
2
3
4
5
6
7
8
9
A2 = 0
DQ0
DQ1
D0
D1
D2
D3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
1
1
1
1
1
1
1
1
1
D8
D9
D10
D18
D26
D34
D42
D50
D58
D66
D11
D19
D27
D35
D43
D51
D59
D67
DQ2
D16
D24
D32
D40
D48
D56
D64
D17
D25
D33
D41
D49
D57
D65
DQ3
DQ4
DQ5
DQ6
DQ7
DM_n/DBI_n
A2 = 1
DQ0
DQ1
D4
D5
D6
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
1
1
1
1
1
1
1
1
1
D12
D20
D28
D36
D44
D52
D60
D68
D13
D21
D29
D37
D45
D53
D61
D69
D14
D22
D30
D38
D46
D54
D62
D70
D15
D23
D31
D39
D47
D55
D63
D71
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM_n/DBI_n
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CRC Write Data Feature
There are two identical CRC trees for x1± devices, each have CRC tree inputs of 3± bits.
When A2 = 6, input bits D[±7:±4] are used if DBI_n or DM_n functions are enabled; if
DBI_n and DM_n are disabled, then D[±7:±4] are 1s. The input bits D[139:13±] are used
if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then
D[139:13±] are 1s.
When A2 = 1, data bits D[7:4] are used as inputs for D[3:6], D[15:12] are used as inputs
for D[11:8], and so forth, for the CRC tree. Input bits D[71:±8] are used if DBI_n or DM_n
functions are enabled; if DBI_n and DM_n are disabled, then D[71:±8] are 1s. The input
bits D[143:146] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n
are disabled, then D[143:146] are 1s.
Table 59: CRC Data Mapping for x16 Devices, BC4
Transfer
Function
0
1
2
3
4
5
6
7
8
9
A2 = 0
DQ0
DQ1
D0
D8
D1
D9
D2
D10
D18
D26
D34
D42
D50
D58
D66
D74
D82
D90
D98
D106
D114
D122
D130
D138
D3
D11
D19
D27
D35
D43
D51
D59
D67
D75
D83
D91
D99
D107
D115
D123
D131
D139
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DQ2
D16
D24
D32
D40
D48
D56
D64
D72
D80
D88
D96
D104
D112
D120
D128
D136
D17
D25
D33
D41
D49
D57
D65
D73
D81
D89
D97
D105
D113
D121
D129
D137
DQ3
DQ4
DQ5
DQ6
DQ7
LDM_n/LDBI_n
DQ8
CRC8
CRC9
CRC10
CRC11
CRC12
CRC13
CRC14
CRC15
1
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDM_n/UDBI_n
A2 = 1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D4
D5
D6
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC0
CRC1
CRC2
CRC3
CRC4
CRC5
CRC6
CRC7
1
1
1
1
1
1
1
1
D12
D20
D28
D36
D44
D52
D60
D13
D21
D29
D37
D45
D53
D61
D14
D22
D30
D38
D46
D54
D62
D15
D23
D31
D39
D47
D55
D63
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CRC Write Data Feature
Table 59: CRC Data Mapping for x16 Devices, BC4 (Continued)
Transfer
Function
LDM_n/LDBI_n
DQ8
0
1
2
3
4
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
1
1
1
8
9
1
1
1
1
1
1
1
1
1
1
D68
D69
D70
D71
1
D76
D77
D78
D79
CRC8
CRC9
CRC10
CRC11
CRC12
CRC13
CRC14
CRC15
1
DQ9
D84
D85
D86
D87
DQ10
D92
D93
D94
D95
DQ11
D100
D108
D116
D124
D132
D140
D101
D109
D117
D125
D133
D141
D102
D110
D118
D126
D134
D142
D103
D111
D119
D127
D135
D143
DQ12
DQ13
DQ14
DQ15
UDM_n/UDBI_n
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1
The following exa0ple is of a CRC tree when x8 is used in BC4 0ode (x4 and x1± CRC
trees have si0ilar differences).
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CRC Write Data Feature
CRC[0], A2=0 =
1^1^D[±7]^D[±±]^D[±4]^1^1^D[5±]^1^1^1^D[56]^D[49]^D[48]^1^D[43]^D[46]^1^D[3
5]^D[34]^1^1^1^1^1^D[19]^D[18]^D[1±]^1^1^D[8] ^1^1^ D[6] ;
CRC[0], A2=1 =
1^1^D[71]^D[76]^D[±8]^1^1^D[±6]^1^1^1^D[54]^D[53]^D[52]^1^D[47]^D[44]^1^D[3
9]^D[38]^1^1^1^1^1^D[23]^D[22]^D[26]^1^1^D[12]^1^1^D[4] ;
CRC[1], A2=0 =
1^D[±±]^D[±5]^1^1^1^D[57]^D[5±]^1^1^D[51]^D[48]^1^1^1^D[43]^D[41]^1^1^D[34
]^D[32]^1^1^1^D[24]^1^1^1^1^D[18]^D[17]^D[1±]^1^1^1^1^D[9] ^1^ D[1]^D[6];
CRC[1], A2=1 =
1^D[76]^D[±9]^1^1^1^D[±1]^D[±6]^1^1^D[55]^D[52]^1^1^1^D[47]^D[45]^1^1^D[38
]^D[3±]^1^1^1^D[28]^1^1^1^1^D[22]^D[21]^D[26]^1^1^1^1^D[13]^1^D[5]^D[4];
CRC[2], A2=0 =
1^1^1^1^1^1^1^D[58]^D[57]^1^D[56]^D[48]^1^1^1^D[43]^D[42]^1^1^D[34]^D[33]^1
^1^D[25]^D[24]^1^D[17]^1^1^1^D[16]^D[8] ^1^D[2]^D[1]^D[6];
CRC[2], A2=1 =
1^1^1^1^1^1^1^D[±2]^D[±1]^1^D[54]^D[52]^1^1^1^D[47]^D[4±]^1^1^D[38]^D[37]^1
^1^D[29]^D[28]^1^D[21]^1^1^1^D[14]^D12]^1^D[±]^D[5]^D[4];
CRC[3], A2=0 =
1^1^D[±4]^1^1^1^D[59]^D[58]^1^D[51]^D[49]^D[48]^1^1^1^D[43]^D[46]^1^D[35]^
D[34]^1^1^D[2±]^D[25]^1^D[18]^D[1±]^1^1^D[11]^D[9] ^1^D[3]^D[2]^D[1];
CRC[3], A2=1 =
1^1^D[±8]^1^1^1^D[±3]^D[±2]^1^D[55]^D[53]^D[52]^1^1^1^D[47]^D[44]^1^D[39]^
D[38]^1^1^D[36]^D[29]^1^D[22]^D[26]^1^1^D[15]^D[13]^1^D[7]^D[±]^D[5];
CRC[4], A2=0 =
1^1^D[±5]^D[±4]^1^1^1^D[59]^D[5±]^1^D[56]^D[49]^D[48]^1^1^1^D[41]^1^1^D[35
]^1^1^D[27]^D[2±]^D[24]^D[19]^D[17]^1^1^1^D[16]^D[8] ^1^D[3]^D[2];
CRC[4], A2=1 =
1^1^D[±9]^D[±8]^1^1^1^D[±3]^D[±6]^1^D[54]^D[53]^D[52]^1^1^1^D[45]^1^1^D[39
]^1^1^D[31]^D[36]^D[28]^D[23]^D[21]^1^1^1^D[14]^D[12]^1^D[7]^D[±];
CRC[5], A2=0 =
1^D[±±]^D[±5]^D[±4]^1^1^1^D[57]^1^D[51]^D[56]^D[49]^1^1^1^D[42]^D[46]^1^1^
D[32]^1^1^D[27]^D[25]^1^D[18]^D[1±]^1^1^D[11]^D[9] ^1^1^D[3];
CRC[5], A2=1 =
1^D[76]^D[±9]^D[±8]^1^1^1^D[±1]^1^D[55]^D[54]^D[53]^1^1^1^D[4±]^D[44]^1^1^
D[3±]^1^1^D[31]^D[29]^1^D[22]^D[26]^1^1^D[15]^D[13]^1^1^D[7];
CRC[6], A2=0 =
D[±7]^D[±±]^D[±5]^D[±4]^1^1^D[58]^1^1^D[51]^D[56]^D[48]^1^1^D[43]^D[41]^1^1
^D[33]^D[32]^1^1^D[2±]^1^D[19]^D[17]^D[1±]^1^1^D[16]^1^1^1;
CRC[6], A2=1 =
D[71]^D[76]^D[±9]^D[±8]^1^1^D[±2]^1^1^D[55]^D[54]^D[52]^1^1^D[47]^D[45]^1^1
^D[37]^D[3±]^1^1^D[36]^1^D[23]^D[21]^D[26]^1^1^D[14]^1^1^1;
CRC[7], A2=0 =
1^D[±7]^D[±±]^D[±5]^1^1^D[59]^1^1^1^D[51]^D[49]^D[48]^1^1^D[42]^1^1^D[34]^
D[33]^1^1^D[27]^1^1^D[18]^D[17]^1^1^D[11]^1^1^1;
CRC[7], A2=1 =
1^D[71]^D[76]^D[±9]^1^1^D[±3]^1^1^1^D[55]^D[53]^D[52]^1^1^D[4±]^1^1^D[38]^
D[37]^1^1^D[31]^1^1^D[22]^D[21]^1^1^D[15]^1^1^1;
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8Gb: x8, x16 Automotive DDR4 SDRAM
CRC Write Data Feature
CRC Error Handling
The CRC error 0echanis0 shares the sa0e ALERT_n signal as CA parity for reporting
write errors to the DRAM. The controller has two ways to distinguish between CRC er-
rors and CA parity errors: 1) Read DRAM 0ode/MPR registers, and 2) Measure ti0e
ALERT_n is LOW. To speed up recovery for CRC errors, CRC errors are only sent back as
a "short" pulse; the 0axi0u0 pulse width is roughly ten clocks (unlike CA parity where
ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the
0axi0u0 li0it at the controller if there are 0ultiple CRC errors as the ALERT_n signals
are connected by a daisy chain bus. The latency to ALERT_n signal is defined as
tCRC_ALERT in the following figure.
The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC
error, which will subsequently set the CRC error status flag in the MPR error log HIGH
(MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) re0ains set
at 1 until the DRAM controller clears the CRC error status bit using an MRS co00and
to set MR5[3] to a 6. The DRAM controller, upon seeing an error as a pulse width, will
retry the write transactions. The controller should consider the worst-case delay for
ALERT_n (during initialization) and backup the transactions accordingly. The DRAM
controller 0ay also be 0ade 0ore intelligent and correlate the write CRC error to a spe-
cific rank or a transaction.
Figure 102: CRC Error Reporting
T0
T1
T2
T3
T4
T5
T6
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
CK_c
CK_t
DQ
IN
Dx
Dx+1 Dx+2 Dx+3 Dx+4 Dx+5 Dx+6 Dx+7 CRCy
1
CRC ALERT_PW (MAX)
CRC ALERT_PW (MIN)
t
CRC_ALERT
ALERT_n
Transition Data
Don’t Care
1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generat-
ing process at T6.
Notes:
2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal
LOW to the point where the DRAM driver releases and the controller starts to pull the
signal up.
3. Timing diagram applies to x4, x8, and x16 devices.
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CRC Write Data Flow Diagram
Figure 103: CA Parity Flow Diagram
DRAM write
process start
MR2 12 enable CRC
MR5 3 set CRC error clear to 0
MR5 10 enable/disable DM
MR3[10:9] WCL if DM enabled
Capture data
DRAM
CRC same as
controller
CRC
Persistent
mode
enabled
Yes
Yes
No
CRC
enabled
Yes
No
No
Transfer data
internally
Transfer data
internally
Transfer Data
Internally
DRAM
CRC same as
controller
CRC
Yes
Yes
Yes
No
MR5[3] = 0
at WRITE
MR5[3] = 0
at WRITE
CA error
No
ALERT_n LOW
6 to 10 CKs
Set error flag
MR5[A3] ꢀ1
ALERT_n LOW
6 to 10 CKs
Set error flag
MR5[A3] ꢀ1
Yes
No
No
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
Set error status
PAGE1 MPR3[7] ꢀ1
Set error status
PAGE1 MPR3[7] ꢀ1
ALERT_n HIGH
ALERT_n HIGH
WRITE burst
completed
WRITE burst
completed
WRITE burst
completed
WRITE burst
completed
WRITE burst
completed
WRITE burst
rejected
Bad data written
MR5 3 reset to 0 if desired
Bad data not written
MR5 3 reset to 0 if desired
8Gb: x8, x16 Automotive DDR4 SDRAM
Data Bus Inversion
Data Bus Inversion
The DATA BUS INVERSION (DBI) function is supported only for x8 and x1± configura-
tions (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in
conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given
DQS strobe edge. The DBI function shares a co00on pin with the DATA MASK (DM)
and TDQS functions. The DBI function applies to either or both READ and WRITE oper-
ations: Write DBI cannot be enabled at the sa0e ti0e the DM function is enabled, and
DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM,
and DBI functions are shown below.
Table 60: DBI vs. DM vs. TDQS Function Matrix
Read DBI
Write DBI
Data Mask (DM)
TDQS (x8 only)
Enabled (or Disabled)
MR5[12]=1 (or
MR5[12] = 0)
Disabled
MR5[11] = 0
Disabled
MR5[10] = 0
Disabled
MR1[11] = 0
Enabled
Disabled
Disabled
MR5[11] = 1
MR5[10] = 0
MR1[11] = 0
Disabled
Enabled
Disabled
MR5[11] = 0
MR5[10] = 1
MR1[11] = 0
Disabled
Disabled
Disabled
Enabled
MR5[12] = 0
MR5[11] = 0
MR5[10] = 0
MR1[11] = 1
DBI During a WRITE Operation
If DBI_n is sa0pled LOW on a given byte lane during a WRITE operation, the DRAM in-
verts write data received on the DQ inputs prior to writing the internal 0e0ory array. If
DBI_n is sa0pled HIGH on a given byte lane, the DRAM leaves the data received on the
DQ inputs noninverted. The write DQ fra0e for0at is shown below for x8 and x1± con-
figurations (the x4 configuration does not support the DBI function).
Table 61: DBI Write, DQ Frame Format (x8)
Transfer
Function
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DM_n or
DBI_n
DM0 or
DBI0
DM1 or
DBI1
DM2 or
DBI2
DM3 or
DBI3
DM4 or
DBI4
DM5 or
DBI5
DM6 or
DBI6
DM7 or
DBI7
Table 62: DBI Write, DQ Frame Format (x16)
Transfer, Lower (L) and Upper(U)
Function
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
LDM_n or
LDBI_n
LDM0 or
LDBI0
LDM1 or
LDBI1
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
LDM6 or
LDBI6
LDM7 or
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
170
UByte 4
UByte 5
UByte 6
UByte 7
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8Gb: x8, x16 Automotive DDR4 SDRAM
Data Bus Inversion
Table 62: DBI Write, DQ Frame Format (x16) (Continued)
Transfer, Lower (L) and Upper(U)
Function
0
1
2
3
4
5
6
7
UDM_n or
UDBI_n
UDM0 or
UDBI0
UDM1 or
UDBI1
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
UDM6 or
UDBI6
UDM7 or
UDBI7
DBI During a READ Operation
If the nu0ber of 6 data bits within a given byte lane is greater than four during a READ
operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin
LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin
HIGH. The read DQ fra0e for0at is shown below for x8 and x1± configurations (the x4
configuration does not support the DBI function).
Table 63: DBI Read, DQ Frame Format (x8)
Transfer Byte
Function
DQ[7:0]
DBI_n
0
1
2
3
4
5
6
7
Byte 0
DBI0
Byte 1
DBI1
Byte 2
DBI2
Byte 3
DBI3
Byte 4
DBI4
Byte 5
DBI5
Byte 6
DBI6
Byte 7
DBI7
Table 64: DBI Read, DQ Frame Format (x16)
Transfer Byte, Lower (L) and Upper(U)
Function
DQ[7:0]
LDBI_n
0
1
2
3
4
5
6
7
LByte 0
LDBI0
LByte 1
LDBI1
LByte 2
LDBI2
LByte 3
LDBI3
LByte 4
LDBI4
LByte 5
LDBI5
LByte 6
LDBI6
LByte 7
LDBI7
DQ[15:8]
UDBI_n
UByte 0
UDBI0
UByte 1
UDBI1
UByte 2
UDBI2
UByte 3
UDBI3
UByte 4
UDBI4
UByte 5
UDBI5
UByte 6
UDBI6
UByte 7
UDBI7
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8Gb: x8, x16 Automotive DDR4 SDRAM
Data Mask
Data Mask
The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only
for x8 and x1± configurations (it is not supported on x4 devices). The DM function
shares a co00on pin with the DBI_n and TDQS functions. The DM function applies
only to WRITE operations and cannot be enabled at the sa0e ti0e the WRITE DBI
function is enabled. The valid configurations for the TDQS, DM, and DBI functions are
shown here.
Table 65: DM vs. TDQS vs. DBI Function Matrix
Data Mask (DM)
TDQS (x8 only)
Write DBI
Read DBI
Enabled
MR5[10] = 1
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Enabled or Disabled
MR5[12] = 1 or
MR5[12] = 0
Disabled
Enabled
Disabled
Disabled
MR5[10] = 0
MR1[11] = 1
MR5[11] = 0
MR5[12] = 0
Disabled
MR1[11] = 0
Enabled
MR5[11] = 1
Enabled or Disabled
MR5[12] = 1 or
MR5[12] = 0
Disabled
MR1[11] = 0
Disabled
MR5[11] = 0
Enabled (or Disabled)
MR5[12] = 1 (or
MR5[12] = 0)
When enabled, the DM function applies during a WRITE operation. If DM_n is sa0pled
LOW on a given byte lane, the DRAM 0asks the write data received on the DQ inputs. If
DM_n is sa0pled HIGH on a given byte lane, the DRAM does not 0ask the data and
writes this data into the DRAM core. The DQ fra0e for0at for x8 and x1± configurations
is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be
checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error
occurs while the DM feature is enabled, CRC write persistent 0ode will be enabled and
data will not be written into the DRAM core. In the case of CRC write enabled and DM
disabled (via MRS), that is, CRC write nonpersistent 0ode, data is written to the DRAM
core even if a CRC error occurs.
Table 66: Data Mask, DQ Frame Format (x8)
Transfer
Function
0
1
2
3
4
5
6
7
DQ[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
DM_n or
DBI_n
DM0 or
DBI0
DM1 or
DBI1
DM2 or
DBI2
DM3 or
DBI3
DM4 or
DBI4
DM5 or
DBI5
DM6 or
DBI6
DM7 or
DBI7
Table 67: Data Mask, DQ Frame Format (x16)
Transfer, Lower (L) and Upper (U)
Function
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
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8Gb: x8, x16 Automotive DDR4 SDRAM
Data Mask
Table 67: Data Mask, DQ Frame Format (x16) (Continued)
Transfer, Lower (L) and Upper (U)
Function
0
1
2
3
4
5
6
7
LDM_n or
LDBI_n
LDM0 or
LDBI0
LDM1 or
LDBI1
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
LDM6 or
LDBI6
LDM7 or
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
UDM_n or
UDBI_n
UDM0 or
UDBI0
UDM1 or
UDBI1
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
UDM6 or
UDBI6
UDM7 or
UDBI7
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Programmable Preamble Modes and DQS Postambles
The device supports progra00able WRITE and READ prea0ble 0odes, either the nor-
0al 1tCK prea0ble 0ode or special 2tCK prea0ble 0ode. The 2tCK prea0ble 0ode
places special ti0ing constraints on 0any operational features as well as being suppor-
ted for data rates of DDR4-2466 and faster. The WRITE prea0ble 1tCK or 2tCK 0ode
can be selected independently fro0 READ prea0ble 1tCK or 2tCK 0ode.
READ prea0ble training is also supported; this 0ode can be used by the DRAM con-
troller to train or "read level" the DQS receivers.
There are tCCD restrictions under so0e circu0stances:
• When 2tCK READ prea0ble 0ode is enabled, a tCCD_S or tCCD_L of 5 clocks is not
allowed.
• When 2tCK WRITE prea0ble 0ode is enabled and write CRC is not enabled, a tCCD_S
or tCCD_L of 5 clocks is not allowed.
• When 2tCK WRITE prea0ble 0ode is enabled and write CRC is enabled, a CCD_S or
t
tCCD_L of ± clocks is not allowed.
WRITE Preamble Mode
MR4[12] = 6 selects 1tCK WRITE prea0ble 0ode while MR4[12] = 1 selects 2tCK WRITE
prea0ble 0ode. Exa0ples are shown in the figures below.
Figure 104: 1tCK vs. 2tCK WRITE Preamble Mode
t
1 CK Mode
WR
WL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
t
2 CK Mode
WR
WL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
CWL has special considerations when in the 2tCK WRITE prea0ble 0ode. The CWL val-
ue selected in MR2[5:3], as seen in table below, requires at least one additional clock
when the pri0ary CWL value and 2tCK WRITE prea0ble 0ode are used; no additional
clocks are required when the alternate CWL value and 2tCK WRITE prea0ble 0ode are
used.
Table 68: CWL Selection
CWL - Primary Choice
1tCK Preamble 2tCK Preamble
CWL - Alternate Choice
Speed Bin
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
1tCK Preamble
2tCK Preamble
9
N/A
N/A
N/A
14
11
12
14
16
18
20
20
N/A
N/A
N/A
16
10
11
12
14
16
16
16
18
18
20
18
20
1. CWL programmable requirement for MR2[5:3].
Note:
t
When operating in 2tCK WRITE prea0ble 0ode, WTR (co00and based) and tWR
(MR6[11:9]) 0ust be progra00ed to a value 1 clock greater than the tWTR and tWR set-
ting nor0ally required for the applicable speed bin to be JEDEC co0pliant; however,
Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The
CAS_n-to-CAS_n co00and delay to either a different bank group (tCCD_S) or the sa0e
bank group (tCCD_L) have 0ini0u0 ti0ing require0ents that 0ust be satisfied be-
tween WRITE co00ands and are stated in the Ti0ing Para0eters by Speed Bin tables.
Figure 105: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4
t
1 CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD = 4
WL
DQS_t,
DQS_c
Preamble
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
DQ
t
2 CK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD = 4
WL
DQS_t,
DQS_c
Preamble
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
DQ
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 106: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5
1tCK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD = 5
WL
DQS_t,
DQS_c
Preamble
Preamble
D0
D0
D1 D2
D3 D4 D5
D6
D7
D1 D2
D3
DQ
2tCK Mode: tCCD = 5 is not allowed in 2tCK mode.
1. tCCD_S and tCCD_L = 5 tCKs is not allowed when in 2tCK WRITE preamble mode.
Note:
Figure 107: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6
1tCK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD = 6
WL
DQS_t,
DQS_c
Preamble
Preamble
D0
D0
D1 D2 D3 D4 D5 D6
D7
D1 D2
D3
DQ
2tCK Mode
CMD
WRITE
WRITE
CK_c
CK_t
tCCD = 6
WL
DQS_t,
DQS_c
Preamble
Preamble
D0
D1 D2 D3 D4 D5 D6
D7
D0
D1 D2
D3
DQ
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
READ Preamble Mode
MR4[11] = 6 selects 1tCK READ prea0ble 0ode and MR4[11] = 1 selects 2tCK READ pre-
a0ble 0ode. Exa0ples are shown in the following figure.
Figure 108: 1tCK vs. 2tCK READ Preamble Mode
t
1 CK Mode
RD
CL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
t
2 CK Mode
RD
CL
CK_c
CK_t
Preamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
READ Preamble Training
DDR4 supports READ prea0ble training via MPR reads; that is, READ prea0ble train-
ing is allowed only when the DRAM is in the MPR access 0ode. The READ prea0ble
training 0ode can be used by the DRAM controller to train or "read level" its DQS re-
ceivers. READ prea0ble training is entered via an MRS co00and (MR4[16] = 1 is ena-
bled and MR4[16] = 6 is disabled). After the MRS co00and is issued to enable READ
prea0ble training, the DRAM DQS signals are driven to a valid level by the ti0e tSDO is
satisfied. During this ti0e, the data bus DQ signals are held quiet, that is, driven HIGH.
The DQS_t signal re0ains driven LOW and the DQS_c signal re0ains driven HIGH until
an MPR Page6 READ co00and is issued (MPR6 through MPR3 deter0ine which pat-
tern is used), and when CAS latency (CL) has expired, the DQS signals will toggle nor-
0ally depending on the burst length setting. To exit READ prea0ble training 0ode, an
MRS co00and 0ust be issued, MR4[16] = 6.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 109: READ Preamble Training
MRS
MPR RD
CL
CMD
t
SDO
DQS_c
DQS_t,
DQs (Quiet/Driven HIGH)
D0
D1
D2
D3
D4
D5
D6
D7
WRITE Postamble
Whether the 1tCK or 2tCK WRITE prea0ble 0ode is selected, the WRITE posta0ble re-
0ains the sa0e at ½tCK.
Figure 110: WRITE Postamble
t
1 CK Mode
WR
WL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
t
2 CK Mode
WR
WL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
READ Postamble
Whether the 1tCK or 2tCK READ prea0ble 0ode is selected, the READ posta0ble re-
0ains the sa0e at ½tCK.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Figure 111: READ Postamble
t
1 CK Mode
RD
CL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
t
2 CK Mode
RD
CL
CK_c
CK_t
Postamble
DQS_t,
DQS_c
D0
D1
D2
D3
D4
D5
D6
D7
DQ
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8Gb: x8, x16 Automotive DDR4 SDRAM
Bank Access Operation
Bank Access Operation
DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:6]), and
each bank group is co0prised of four subbanks (BA[1:6]); x1± DRAMs have two bank
groups (BG[6]), and each bank group is co0prised of four subbanks. Bank accesses to
different banks' groups require less ti0e delay between accesses than bank accesses to
within the sa0e bank's group. Bank accesses to different bank groups require tCCD_S
(or short) delay between co00ands while bank accesses within the sa0e bank group
require tCCD_L (or long) delay between co00ands.
Figure 112: Bank Group x4/x8 Block Diagram
Bank 3
Bank 2
Bank 1
Bank 0
Bank 3
Bank 2
Bank 1
Bank 0
Bank 3
Bank 2
Bank 1
Bank 0
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Memory Array
Memory Array
Memory Array
Bank Group 0
Bank Group 1
Bank Group 2
Bank Group 3
CMD/ADDR
register
CMD/ADDR
Sense amplifiers
Local I/O gating
Sense amplifiers
Local I/O gating
Sense amplifiers
Local I/O gating
Sense amplifiers
Local I/O gating
Global I/O gating
Data I/O
1. Bank accesses to different bank groups require tCCD_S.
2. Bank accesses within the same bank group require tCCD_L.
Notes:
Table 69: DDR4 Bank Group Timing Examples
Parameter
tCCD_S
DDR4-1600
4nCK
DDR4-2133
4nCK
DDR4-2400
4nCK
tCCD_L
4nCK or 6.25ns
4nCK or 5.355ns
4nCK or 5ns
tRRD_S (½K)
tRRD_L (½K)
4nCK or 5ns
4nCK or 6ns
4nCK or 3.7ns
4nCK or 5.3ns
4nCK or 3.3ns
4nCK or 4.9ns
tRRD_S (1K)
tRRD_L (1K)
4nCK or 5ns
4nCK or 6ns
4nCK or 3.7ns
4nCK or 5.3ns
4nCK or 3.3ns
4nCK or 4.9ns
tRRD_S (2K)
tRRD_L (2K)
4nCK or 6ns
4nCK or 5.3ns
4nCK or 6.4ns
4nCK or 5.3ns
4nCK or 6.4ns
4nCK or 7.5ns
tWTR_S
2nCK or 2.5ns
2nCK or 2.5ns
2nCK or 2.5ns
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Bank Access Operation
Table 69: DDR4 Bank Group Timing Examples (Continued)
Parameter
DDR4-1600
DDR4-2133
DDR4-2400
tWTR_L
4nCK or 7.5ns
4nCK or 7.5ns
4nCK or 7.5ns
1. Refer to Timing Tables for actual specification values, these values are shown for refer-
ence only and are not verified for accuracy.
Notes:
2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the
two cases must be satisfied.
Figure 113: READ Burst tCCD_S and tCCD_L Examples
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
DES
CK_c
CK_t
Command
READ
DES
DES
DES
DES
DES
DES
t
DES
DES
READ
READ
t
CCD_S
CCD_L
Bank Group
(BG)
BG a
BG b
BG b
Bank
Bank c
Bank c
Bank c
Address
Col n
Col n
Col n
Don’t Care
1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
Notes:
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
Figure 114: Write Burst tCCD_S and tCCD_L Examples
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
DES
CK_c
CK_t
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
WRITE
Command
WRITE
tCCD_S
tCCD_L
Bank Group
(BG)
BG a
BG b
BG b
Bank c
Bank c
Bank c
Bank
Coln
Coln
Coln
Address
Don’t Care
1. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank
groups (T0 to T4).
Notes:
2. tCCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank
group (T4 to T10).
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Bank Access Operation
Figure 115: tRRD Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
ACT
T11
DES
CK_c
CK_t
DES
DES
DES
DES
DES
DES
DES
DES
ACT
ACT
Command
t
t
RRD_S
RRD_L
Bank
Group
(BG)
BG b
Bank d
Row n
BG a
Bank c
Row n
BG b
Bank c
Row n
Bank
Address
Don’t Care
1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI-
VATE commands to different bank groups (T0 and T4).
Notes:
2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI-
VATE commands to the different banks in the same bank group (T4 and T10).
Figure 116: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
CK_c
CK_t
Command
WRITE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ
Valid
tWTR_S
Bank
BGa
Bank c
Col n
BGb
Bank c
Col n
Group
Bank
Address
tWPRE
tWPST
DQS, DQS_c
DQ
DI
n
DI
DI
DI
DI
DI
DI
DI
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
WL
RL
Time Break
Transitioning Data
Don’t Care
1. tWTR_S: delay from start of internal write transaction to internal READ command to a
different bank group.
Note:
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Bank Access Operation
Figure 117: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
CK_c
CK_t
Command
WRITE
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
READ
Valid
tWTR_L
Bank
BGa
Bank c
Col n
BGa
Bank c
Col n
Group
Bank
Address
tWPRE
tWPST
DQS, DQS_c
DQ
DI
n
DI
DI
DI
DI
DI
DI
DI
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
WL
RL
Time Break
Transitioning Data
Don’t Care
1. tWTR_L: delay from start of internal write transaction to internal READ command to the
same bank group.
Note:
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READ Operation
READ Operation
Read Timing Definitions
The read ti0ings shown below are applicable in nor0al operation 0ode, that is, when
the DLL is enabled and locked.
Note: tDQSQ = both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge para0eters:
t
• DQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-
tive to CK.
t
• DQSCK is the actual position of a rising strobe edge relative to CK.
t
• QSH describes the DQS differential output HIGH ti0e.
t
• DQSQ describes the latest valid transition of the associated DQ pins.
t
• QH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge para0eters:
t
• QSL describes the DQS differential output LOW ti0e.
t
• DQSQ describes the latest valid transition of the associated DQ pins.
t
• QH describes the earliest invalid transition of the associated DQ pins.
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READ Operation
Figure 118: Read Timing Definition
CK_c
CK_t
t
t
t
t
DQSCK (MIN) DQSCK (MAX) DQSCK (MIN) DQSCK (MAX)
t
t
DQSCKi
DQSCKi
Rising strobe
region
Rising strobe
region
t
DQSCK MAX
window
window
t
t
DQSCKi
DQSCKi
Rising strobe
region
Rising strobe
region
t
DQSCK center
window
window
t
t
DQSCKi
DQSCKi
Rising strobe
region
Rising strobe
region
t
DQSCK MIN
window
window
t
t
DQSCK
DQSCK
t
t
QSH/DQS_c
QSH/DQS_t
DQS_c
DQS_t
t
t
QH
QH
t
t
DQSQ
DQSQ
Associated
DQ Pins
Table 70: Read-to-Write and Write-to-Read Command Intervals
Access Type
Bank Group
Same
Timing Parameters
CL - CWL + RBL/2 + 1tCK + tWPRE
CL - CWL + RBL/2 + 1tCK + tWPRE
CWL + WBL/2 + tWTR_L
Note
1, 2
1, 2
1, 3
1, 3
Read-to-Write, mini-
mum
Different
Same
Write-to-Read, mini-
mum
Different
CWL + WBL/2 + tWTR_S
1. These timings require extended calibrations times tZQinit and tZQCS.
Notes:
2. RBL: READ burst length associated with READ command, RBL = 8 for fixed 8 and on-the-
fly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4.
3. WBL: WRITE burst length associated with WRITE command, WBL = 8 for fixed 8 and on-
the-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only.
Read Timing – Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship shown below is applicable in nor0al operation
0ode, that is, when the DLL is enabled and locked.
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READ Operation
Rising data strobe edge para0eters:
t
• DQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela-
tive to CK.
t
• DQSCK is the actual position of a rising strobe edge relative to CK.
t
• QSH describes the data strobe high pulse width.
t
• HZ(DQS) DQS strobe going to high, nondrive level (shown in the posta0ble section
of the figure below).
Falling data strobe edge para0eters:
t
• QSL describes the data strobe low pulse width.
t
• LZ(DQS) DQS strobe going to low, initial drive level (shown in the prea0ble section
of the figure below).
Figure 119: Clock-to-Data Strobe Relationship
RL measured
to this point
CK_t
CK_c
t
t
t
t
DQSCK (MIN)
DQSCK (MIN)
DQSCK (MIN)
DQSCK (MIN)
t
HZ(DQS) MIN
t
t
t
t
t
t
t
QSH
QSL
QSH
QSL
QSH
QSL
LZ(DQS) MIN
DQS_t, DQS_c
Early Strobe
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RPST
t
t
RPRE
t
HZ(DQS) MAX
t
t
t
t
DQSCK (MAX)
DQSCK (MAX)
Bit 2
DQSCK (MAX)
Bit 4
DQSCK (MAX)
t
RPST
Bit 7
t
LZ(DQS) MAX
DQS_t, DQS_c
Late Strobe
Bit 0
Bit 1
Bit 3
Bit 5
Bit 6
t
t
t
t
t
RPRE
QSH
QSL
QSH
QSL
1. Within a burst, the rising strobe edge will vary within tDQSCKj while at the same volt-
age and temperature. However, when the device, voltage, and temperature variations
are incorporated, the rising strobe edge variance window can shift between tDQSCK
(MIN) and tDQSCK (MAX).
Notes:
A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a devi-
ce's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from ris-
ing CK_t, CK_c is limited by tDQSCK (MIN).
2. Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be im-
mediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other
timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH
(MIN) + tQSL (MIN)) - | tDQSCK(n + 1) |.
3. The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t,
DQS_c differential output LOW time is defined by tQSL.
4. tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and
tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case).
5. The minimum pulse width of READ preamble is defined by tRPRE (MIN).
6. The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left
side and tHZDSQ (MAX) on the right side.
7. The minimum pulse width of READ postamble is defined by tRPST (MIN).
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READ Operation
8. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK
(MAX) on the right side.
Read Timing – Data Strobe-to-Data Relationship
The data strobe-to-data relationship is shown below and is applied when the DLL is en-
abled and locked.
Note: tDQSQ: both rising/falling edges of DQS; no tAC defined.
Rising data strobe edge para0eters:
t
• DQSQ describes the latest valid transition of the associated DQ pins.
t
• QH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge para0eters:
t
• DQSQ describes the latest valid transition of the associated DQ pins.
t
• QH describes the earliest invalid transition of the associated DQ pins.
Data valid window para0eters:
t
• DVWd is the Data Valid Window per device per UI and is derived fro0 [tQH - tDQSQ]
of each UI on a given DRAM
t
• DVWp is the Data Valid Window per pin per UI and is derived [tQH - tDQSQ] of each
UI on a pin of a given DRAM
Figure 120: Data Strobe-to-Data Relationship
T0
T1
T2
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
CK_c
CK_t
3
READ
DES
DES
DES
Command
RL = AL + CL
Bank,
Col n
4
Address
t
t
DQSQ (MAX)
DQSQ (MAX)
t
RPST
t
RPRE (1nCK)
DQS_t, DQS_c
t
t
QH
QH
2
DQ
D
D
D
D
n + 3
D
n + 4
D
D
D
OUT
OUT
n + 1
OUT
n + 2
OUT
OUT
OUT
n + 5
OUT
n + 6
OUT
n + 7
n
(Last data )
t
DVWp
2
D
D
n + 1
D
n + 2
D
n + 3
D
n + 4
D
n + 5
D
D
n + 7
OUT
n
OUT
OUT
OUT
OUT
OUT
OUT
n + 6
OUT
DQ
(First data no longer)
t
DVWp
D
D
n + 1
D
n + 2
D
n + 3
D
n + 4
D
n + 5
D
n + 6
D
n + 7
OUT
n
OUT
OUT
OUT
OUT
OUT
OUT
OUT
All DQ collectively
t
t
DVWd
DVWd
Don’t Care
1. BL = 8, RL = 11 (AL = 0, CL = 1) , Premable = 1tCK.
Notes:
2. DOUT n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0.
5. Output timings are referenced to VDDQ, and DLL on for locking.
6. tDQSQ defines the skew between DQS to data and does not define DQS to clock.
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READ Operation
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ
can vary (either early or late) within a burst.
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations
tHZ and tLZ transitions occur in the sa0e ti0e window as valid data transitions. These
para0eters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and
tLZ(DQ). The figure below shows a 0ethod to calculate the point when the device is no
longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by
0easuring the signal at two different voltages. The actual voltage 0easure0ent points
are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS),
and tHZ(DQ) are defined as singled-ended para0eters.
Figure 121: tLZ and tHZ Method for Calculating Transitions and Endpoints
t
t
t
LZ(DQ): CK_t, CK_c rising crossing at RL
HZ(DQ) with BL8: CK_t, CK_c rising crossing at RL + 4CK
HZ(DQ) with BC4: CK_t, CK_c rising crossing at RL + 2CK
CK_t
CK_c
t
t
LZ
HZ
Begin point:
Extrapolated point at V
DDQ
V
DDQ
DQ
V
DQ
DDQ
V
V
SW2
SW2
0.7 × V
DDQ
0.7 × V
DDQ
V
V
SW1
SW1
0.4 × V
DDQ
0.4 × V
DDQ
Begin point: Extrapolated point (low level)
1. Vsw1 = (0.70 - 0.04) × VDDQ for both tLZ and tHZ.
2. Vsw2 = (0.70 + 0.04) × VDDQ for both tLZ and tHZ.
Notes:
3. Extrapolated point (low level) = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
V
TT test load = 50Ω to VDDQ.
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READ Operation
tRPRE Calculation
Figure 122: tRPRE Method for Calculating Transitions and Endpoints
CK_t
VDD/2
CK_c
Single-ended signal provided as background information
DQS_t
VDDQ
0.7 × V
DDQ
0.4 × V
DDQ
DQS_c
VDDQ
0.7 × V
DDQ
0.4 × V
DDQ
VDDQ
DQS_t
DQS_c
DQS_t
0.7 × V
DDQ
0.4 × V
DQS_c
DDQ
Resulting differential signal relevanttRfPoRrE specification
0.6 × V
DDQ
VSW2
VSW1
0.3 × V
DDQ
DQS_t, DQS_c
0V
tRPRE beginst1()
tRPRE endst(2)
1. Vsw1 = (0.3 - 0.04) × VDDQ
.
Notes:
2. Vsw2 = (0.30 + 0.04) × VDDQ
.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
V
TT test load = 50Ω to VDDQ.
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READ Operation
tRPST Calculation
Figure 123: tRPST Method for Calculating Transitions and Endpoints
CK_t
VDD/2
CK_c
Single-ended signal provided as background information
VDDQ
0.7 × V
DDQ
0.4 × V
DQS_t
DQS_c
DDQ
VDDQ
0.7 × V
DDQ
0.4 × V
DDQ
DQS_c
VDDQ
0.7 × V
DDQ
DQS_t
Resulting differential signal relevanttRfPoSrT specification
tRPST beginst(1)
0V
VSW2
VSW1
–0.3 × V
DDQ
–0.6 × V
DQS_t, DQS_c
DDQ
tRPST endst(2)
1. Vsw1 = (–0.3 - 0.04) × VDDQ
.
Notes:
2. Vsw2 = (–0.30 + 0.04) × VDDQ
.
3. DQS_t and DQS_c low level = VDDQ/(50 + 34) × 34 = 0.4 × VDDQ
Driver impedance = RZQ/7 = 34Ω
V
TT test load = 50Ω to VDDQ.
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READ Operation
READ Burst Operation
DDR4 READ co00ands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-
the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 6, BC4 (BC4 = burst chop)
• A12 = 1, BL8
READ co00ands can issue precharge auto0atically with a READ with auto precharge
co00and (RDA), and is enabled by A16 HIGH:
• READ co00and with A16 = 6 (RD) perfor0s standard read, bank re0ains active after
READ burst.
• READ co00and with A16 = 1 (RDA) perfor0s read with auto precharge, bank goes in
to precharge after READ burst.
Figure 124: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group
Address
Bank
col n
Address
tRPRE
tRPST
DQS_t
DQS_c
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
CL = 11
RL = AL + CL
Time Break
Transitioning Data
Don’t Care
1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1tCK.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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READ Operation
Figure 125: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
DES
Tb1
DES
Tb2
DES
Tb3
DES
Tb4
DES
Tb5
DES
Tb6
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
DES
DES
Bank Group
Address
Bank
col n
Address
t
t
RPRE
RPST
DQS_t
DQS_c
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
AL = 10
CL = 11
RL = AL + CL
Time Break
Transitioning Data
Don’t Care
1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1tCK.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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READ Operation
READ Operation Followed by Another READ Operation
Figure 126: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
DES
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 127: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 128: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S/L = 5
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 1tCK, tCCD_S/L = 5.
Notes:
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 129: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T2
T5
T6
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S/L = 6
Bank Group
Address
BGa or
BGb
Bank
Col n
Bank
Col b
Address
tRPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK, tCCD_S/L = 6.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0 and T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
6. 6 tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 130: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
b
b + 1 b + 2 b + 3
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 131: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
b
b + 1 b + 2 b + 3
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 132: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 133: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL =0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4
setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 134: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPST
tRPST
tRPRE
tRPRE
DQS_t,
DQS_c
RL = 11
DO
n
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL =0, CL = 11, Preamble = 1tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 135: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DO
n
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, Preamble = 2tCK.
2. DO n (or b) = data-out from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8
setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
READ Operation Followed by WRITE Operation
Figure 136: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
DES
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
tWTR
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = 9
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 137: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
DES
T20
T21
DES
T22
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
tWTR
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = 10
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9+1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 138: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
tWTR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = 9
Time Break
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 139: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
tWTR
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = 10
Time Break
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 140: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
tWTR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
2 Clocks
Bank Group
Address
BGa or
BGb
BGa
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = 9
Time Break
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
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READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 01.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 141: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
tWTR
2 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = 10
Time Break
Transitioning Data
Don’t Care
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 9 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
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READ Operation
Figure 142: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
tWTR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tRPST
tWPST
tRPRE
tWPRE
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3 n + 4 n + 5 n + 6 n + 7
WL = 9
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 143: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
T19
DES
T20
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
tWTR
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tRPST
tWPST
tRPRE
tWPRE
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3 n + 4 n + 5 n + 6 n + 7
WL = 10
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6.
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READ Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 144: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
T20
DES
T21
DES
T22
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
tWR
tWTR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
WL = 9
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE
preamble = 1tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 145: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
DES
T19
DES
T20
T21
DES
T22
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 3 tCK
tWTR
4 Clocks
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
WL = 10
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2tCK.
Notes:
2. DO n = data-out from column n; DI b = data-in from column b.
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READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
READ Operation Followed by PRECHARGE Operation
The 0ini0u0 external READ co00and to PRECHARGE co00and spacing to the sa0e
bank is equal to AL + tRTP with tRTP being the internal READ co00and to PRECHARGE
co00and delay. Note that the 0ini0u0 ACT to PRE ti0ing, tRAS, 0ust be satisfied as
well. The 0ini0u0 value for the internal READ co00and to PRECHARGE co00and
delay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE co00and
0ay be issued to the sa0e bank if the following two conditions are satisfied si0ultane-
ously:
• The 0ini0u0 RAS precharge ti0e (tRP [MIN]) has been satisfied fro0 the clock at
which the precharge begins.
• The 0ini0u0 RAS cycle ti0e (tRC [MIN]) fro0 the previous bank activation has been
satisfied.
Figure 146: READ to PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T6
T7
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
DES
READ
BGa
DES
DES
DES
PRE
ACT
BGa
Bank Group
Address
BGa
or BGb
Bank a
Col n
Bank a
(or all)
Bank a
Row b
Address
tRTP
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DO
n
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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READ Operation
Figure 147: READ to PRECHARGE with 2tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
DES
READ
BGa
DES
DES
DES
PRE
DES
DES
DES
ACT
BGa
Bank Group
Address
BGa or
BGb
Bank a
Col n
Bank a
(or all)
Bank a
Row b
Address
tRTP
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DO
n
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 148: READ to PRECHARGE with Additive Latency and 1tCK Preamble
T0
T1
T2
T3
T10
DES
T11
DES
T12
DES
T13
DES
T16
PRE
T19
DES
T20
DES
T21
DES
T22
DES
T23
DES
T24
DES
T25
DES
T26
DES
T27
CK_c
CK_t
Command
DES
READ
BGa
DES
DES
ACT
BGa
Bank Group
Address
BGa or
BGb
Bank a
Col n
Bank a
(or all)
Bank a
Row b
Address
t
t
AL = CL - 2 = 9
RTP
RP
CL = 11
BC4 Opertaion
DQS_t,
DQS_c
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DO
n
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.
Notes:
2. DO n = data-out from column n.
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READ Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time
(T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 149: READ with Auto Precharge and 1tCK Preamble
T0
T1
T2
T3
T6
T7
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
T19
DES
T20
DES
T21
DES
CK_c
CK_t
Command
DES
RDA
BGa
DES
DES
DES
PRE
ACT
BGa
Bank Group
Address
BGa or
BGb
Bank a
Col n
Bank a
Col n
Bank a
Row b
Address
tRTP
tRP
RL = AL + CL
BC4 Opertaion
DQS_t,
DQS_c
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DO
n
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. tRTP = 6 setting activated by MR0[A11:9 = 001].
5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T18).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 150: READ with Auto Precharge, Additive Latency, and 1tCK Preamble
T0
T1
T2
T3
T10
T11
T12
T13
T16
T19
T20
T21
T22
T23
T24
DES
T25
DES
T26
DES
T27
CK_c
CK_t
Command
DES
RDA
BGa
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
ACT
BGa
Bank Group
Address
Bank a
Col n
Bank a
Row b
Address
AL = CL - 2 = 9
tRTP
tRP
CL = 11
BC4 Opertaion
DQS_t,
DQS_c
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DO
n
DO
DO
DO
DO
DO
DO
DO
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. RL = 20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11.
Notes:
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. tRTP = 6 setting activated by MR0[11:9] = 001.
5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time
(T27).
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
READ Operation with Read Data Bus Inversion (DBI)
Figure 151: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DES
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
CCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
t
t
RPRE
RPST
DQS_t,
DQS_c
RL = 11 + 2 (Read DBI adder)
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7
RL = 11 + 2 (Read DBI adder)
DBI
n
DBI
DBI
DBI
DBI
DBI
DBI
DBI
DBI
b
DBI
DBI
DBI
DBI
DBI
DBI
DBI
DBI_n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, Preamble = 1tCK, RL = 11 + 2 (Read DBI adder).
Notes:
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READ Operation
2. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from col-
umn n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable.
READ Operation with Command/Address Parity (CA Parity)
Figure 152: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T13
T14
T15
T16
T17
T18
T19
T20
T21
T20
T21
DES
CK_c
CK_t
Command
READ
BGa
DES
DES
DES
READ
BGb
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tCCD_S = 4
Bank Group
Address
Bank
Col n
Bank
Col b
Address
Parity
tRPRE
tRPST
DQS_t,
DQS_c
RL = 15
DO
DO
DO
DO
DO
DO
DO
DO
DO
b
DO
DO
DO
DO
DO
DO
DO
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7
RL = 15
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1tCK.
Notes:
2. DO n (or b) = data-out from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during
READ commands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable.
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8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 153: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank
Group
T0
T1
T7
T8
T9
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
READ to WRITE command delay
= RL +BL/2 - WL + 2 tCK
4 Clocks
tWTR
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
Parity
tWPST
tWPRE
tRPRE
tRPST
DQS_t,
DQS_c
RL = 15
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = 13
Time Break
Transitioning Data
Don’t Care
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1tCK, CWL = 9,
AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK.
Notes:
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE command at T8.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
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READ Operation
READ Followed by WRITE with CRC Enabled
Figure 154: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or
Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
DES
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
t
WR
WTR
READ to WRITE command delay
= RL +BL/2 - WL + 2 CK
4 Clocks
t
Bank Group
Address
BGa or
BGb
BGa
Bank
Col n
Bank
Col b
Address
t
WPST
t
t
t
WPRE
RPRE
RPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x4,
BL = 8
CRC
CRC
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = 9
DO
n
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x8/X16,
BL = 8
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
DQ x4,
READ: BL = 8,
WRITE: BC = 4 (OTF)
DO
n
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
DQ x8/X16,
READ: BL = 8,
DO
n
DO
DO
DO
DO
DO
DO
DO
DI
b
DI
DI
DI
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
WRITE: BC = 4 (OTF)
Time Break
Transitioning Data
Don’t Care
1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL =
9 (CWL = 9, AL = 0), WRITE preamble = 1tCK.
Notes:
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.
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READ Operation
Figure 155: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or
Different Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command
READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
DES
DES
WR
READ to WRITE command delay
= RL +BL/2 - WL + 2 CK
t
t
2 Clocks
WTR
Bank Group
Address
BGa or
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
t
t
WPST
WPRE
RPRE
RPST
DQS_t,
DQS_c
RL = 11
DO
DO
DO
DO
DI
b
DI
DI
DI
DQ x4,
BC = 4 (Fixed)
CRC
CRC
CRC
n
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = 9
DO
n
DO
DO
DO
DI
b
DI
DI
DI
DQ x8/X16,
BC = 4 (Fixed)
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL =
0), WRITE preamble = 1tCK.
Notes:
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Enable.
READ Operation with Command/Address Latency (CAL) Enabled
Figure 156: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T5
T6
T7
T8
T13
T14
T15
T17
T18
T19
T21
T22
T23
DES
CK_c
CK_t
tCAL = 3
DES
tCAL = 3
Command
w/o CS_n
DES
READ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
CS_n
tCCD_S = 4
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DI
n
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 5 n + 6 n + 7
b + 1 b + 2 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.
Notes:
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READ Operation
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T7.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
Figure 157: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T5
T6
T7
T8
T14
T15
T16
T18
T19
T21
T22
T23
T24
DES
CK_c
CK_t
tCAL = 4
DES
tCAL = 4
DES
Command
w/o CS_n
DES
READ
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
CS_n
tCCD_S = 4
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
tRPST
tRPRE
DQS_t,
DQS_c
RL = 11
DI
n
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 5 n + 6 n + 7
b + 1 b + 2 b + 5 b + 6 b + 7
RL = 11
Time Break
Transitioning Data
Don’t Care
1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK.
Notes:
2. DI n (or b) = data-in from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T3 and T8.
5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. Enabling CAL mode does not impact ODT control timings. The same timing relationship
relative to the command/address bus as when CAL is disabled should be maintained.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
WRITE Operation
Write Timing Definitions
The write ti0ings shown in the following figures are applicable in nor0al operation
0ode, that is, when the DLL is enabled and locked.
Write Timing – Clock-to-Data Strobe Relationship
The clock-to-data strobe relationship is shown below and is applicable in nor0al oper-
ation 0ode, that is, when the DLL is enabled and locked.
Rising data strobe edge para0eters:
t
• DQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge
relative to CK.
t
• DQSS is the actual position of a rising strobe edge relative to CK.
t
• DQSH describes the data strobe high pulse width.
t
• WPST strobe going to HIGH, nondrive level (shown in the posta0ble section of the
graphic below).
Falling data strobe edge para0eters:
t
• DQSL describes the data strobe low pulse width.
t
• WPRE strobe going to LOW, initial drive level (shown in the prea0ble section of the
graphic below).
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WRITE Operation
Figure 158: Write Timing Definition
T0
T1
T2
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
CK_c
CK_t
Command3
WRITE
DES
DES
DES
DES
DES
WL = AL + CWL
Bank,
Col n
Address4
t
t
t
t
t
DQSS
DSH
DSH
DSH
DSH
t
t
WPSTaa
tDQSS (MIN)
WPRE(1nCK)
DQS_t, DQS_c
DQ2
t
t
t
t
t
t
t
DQSL DQSH DQSL DQSH DQSL DQSH DQSL tDQSH
t
t
DQSL (MIN)
DQSH (MIN)
t
t
t
t
t
DSS
DSS
DSS
DSS
DSS
DIN
n
DIN
n+ 2
DIN
DIN
n+ 4
DIN
n+ 6
DIN
n+ 7
n+ 3
t
t
t
t
DSH
DSH
DSH
DSH
t
t
t
WPST (MIN)
WPRE(1nCK)
DQSS (nominal)
DQS_t, DQS_c
DQ2
t
t
t
t
t
t
t
t
DQSL DQSH DQSL DQSH DQSL DQSH DQSL DQSH
t
t
DQSL (MIN)
DQSH (MIN)
t
t
t
t
t
DSS
DSS
DSS
DSS
DSS
DIN
n
DIN
n+ 2
DIN
DIN
n+ 4
DIN
DIN
n+ 7
n+ 3
n+ 6
t
DQSS
t
t
t
t
DSH
DSH
DSH
DSH
t
t
WPST (MIN)
WPRE(1nCK)
t
DQSS (MAX)
DQS_t, DQS_c
t
t
t
t
t
t
t
t
DQSL DQSH DQSL DQSH DQSL DQSH DQSL DQSH
t
t
DQSL (MIN)
DQSH (MIN)
t
t
t
t
t
DSS
DSS
DSS
DSS
DSS
DIN
n
DIN
n+ 2
DIN
n+ 3
DIN
n+ 4
DIN
n+ 6
DIN
n+ 7
DQ2
DM_n
Time Break
Transitioning Data
Don’t Care
1. BL8, WL = 9 (AL = 0, CWL = 9).
Notes:
2. DIN n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
tWPRE Calculation
Figure 159: tWPRE Method for Calculating Transitions and Endpoints
&.BW
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1. Vsw1 = (0.1) × VIH,diff,DQS
2. Vsw2 = (0.9) × VIH,diff,DQS
.
.
Notes:
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215
8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
tWPST Calculation
Figure 160: tWPST Method for Calculating Transitions and Endpoints
&.BW
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1. Vsw1 =(0.9) × VIL,diff,DQS
.
Notes:
2. Vsw2 = (0.1) × VIL,diff,DQS
.
Write Timing – Data Strobe-to-Data Relationship
The DQ input receiver uses a co0pliance 0ask (Rx) for voltage and ti0ing as shown in
the figure below. The receiver 0ask (Rx 0ask) defines the area where the input signal
0ust not encroach in order for the DRAM input receiver to be able to successfully cap-
ture a valid input signal. The Rx 0ask is not the valid data-eye. TdiVW and VdiVW define
the absolute 0axi0u0 Rx 0ask.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 161: Rx Compliance Mask
Rx Mask
VCENTDQ,midpoint
TdiVW
VCENTDQ,0idpoint is defined as the 0idpoint between the largest VREFDQ voltage level and
the s0allest VREFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's
VREFDQ is defined by the center (widest opening) of the cu0ulative data input eye as de-
picted in the following figure. This 0eans a DRAM's level variation is accounted for
within the DRAM Rx 0ask. The DRAM VREFDQ level will be set by the syste0 to account
for RON and ODT settings.
Figure 162: VCENT_DQ VREFDQ Voltage Variation
DQx
DQz
DQy
(largest V
V
Level)
(smallest V
Level)
REFDQ
REFDQ
V
CENTDQz
CENTDQx
V
CENTDQ,midpoint
V
CENTDQy
V
variation
REF
(component)
The following figure shows the Rx 0ask require0ents both fro0 a 0idpoint-to-0id-
point reference (left side) and fro0 an edge-to-edge reference. The intent is not to add
any new require0ent or specification between the two but rather how to convert the
relationship between the two 0ethodologies. The 0ini0u0 data-eye shown in the
co0posite view is not actually obtainable due to the 0ini0u0 pulse width require-
0ent.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 163: Rx Mask DQ-to-DQS Timings
DQS, DQs Data-In at DRAM Ball
DQS, DQs Data-In at DRAM Ball
Rx Mask – Alternative View
Rx Mask
DQS_c
DQS_t
DQS_c
DQS_t
0.5 × TdiVW
0.5 × TdiVW
0.5 × TdiVW
0.5 × TdiVW
DRAMa
DQx–z
DRAMa
DQx–z
Rx Mask
Rx Mask
TdiVW
TdiVW
t
DQS2DQ +0.5 × TdiVW
t
DQS2DQ
DRAMb
DQy
DRAMb
DQy
Rx Mask
Rx Mask
T
diVW
t
t
DQ2DQ
DQ2DQ
DRAMb
DQz
DRAMb
DQz
Rx Mask
Rx Mask
T
diVW
t
DQ2DQ
t
DQS2DQ +0.5 × TdiVW
t
DQS2DQ
DRAMc
DQz
DRAMc
DQz
Rx Mask
Rx Mask
T
diVW
t
t
DQ2DQ
DQ2DQ
DRAMc
DQy
DRAMc
DQy
Rx Mask
Rx Mask
T
diVW
t
DQ2DQ
1. DQx represents an optimally centered mask.
DQy represents earliest valid mask.
Notes:
DQz represents latest valid mask.
2. DRAMa represents a DRAM without any DQS/DQ skews.
DRAMb represents a DRAM with early skews (negative tDQS2DQ).
DRAMc represents a DRAM with delayed skews (positive tDQS2DQ).
3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ
for a DRAM. Signals assume data is center-aligned at DRAM latch.
TdiPW is not shown; composite data-eyes shown would violate TdiPW.
V
CENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW.
The previous figure shows the basic Rx 0ask require0ents. Converting the Rx 0ask re-
quire0ents to a classical DQ-to-DQS relationship is shown in the following figure. It
should beco0e apparent that DRAM write training is required to take full advantage of
the Rx 0ask.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 164: Rx Mask DQ-to-DQS DRAM-Based Timings
DQS, DQs Data-In at DRAM Ball
DQS, DQs Data-In at DRAM Ball
Rx Mask vs. Composite Data-Eye
Rx Mask vs. UI Data-Eye
DQS_c
DQS_t
DQS_c
DQS_t
t
t
TdiPW
DSx
DHx
DRAMa
DQx–z
DRAMa
DQx , y, z
Rx Mask
Rx Mask
TdiVW
TdiVW
TdiPW
TdiPW
t
t
DSy
DHy
*Skew
DRAMb
DQy
Rx Mask
t
DQ2DQ
TdiVW
DRAMb
DQz
Rx Mask
t
DQ2DQ
TdiPW
T
diVW
t
t
DSz
DHz
*Skew
DRAMc
DQy
Rx Mask
t
DQ2DQ
TdiVW
DRAMc
DQz
Rx Mask
t
DQ2DQ
TdiVW
TdiPW
1. DQx represents an optimally centered mask.
DQy represents earliest valid mask.
Notes:
DQz represents latest valid mask.
2. *Skew = tDQS2DQ + 0.5 × TdiVW
DRAMa represents a DRAM without any DQS/DQ skews.
DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew).
DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew).
3. tDS/tDH are traditional data-eye setup/hold edges at DC levels.
tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width
and Rx mask limits are not violated.
tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ.
The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx
0ask of TdiVW provided the 0ini0u0 pulse width is satisfied. The DRAM controller
will have to train the data input buffer to utilize the Rx 0ask specifications to this 0axi-
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
0u0 benefit. If the DRAM controller does not train the data input buffers, then the
worst case li0its have to be used for the Rx 0ask (TdiVW + 2 × tDQS2DQ), which will
generally be the classical 0ini0u0 ( tDS and tDH) and is required as well.
Figure 165: Example of Data Input Requirements Without Training
t
TdiVW + 2 × DQS2DQ
V
IH(DC)
0.5 × V
0.5 × V
diVW
Rx Mask
V
CENTDQ,midpoint
diVW
V
IL(DC)
t
t
DS
DH
0.5 × TdiVW + DQS2DQ 0.5 × TdiVW + DQS2DQ
DQS_c
t
t
DQS_t
WRITE Burst Operation
The following write ti0ing diagra0s are intended to help understand each write pa-
ra0eter's 0eaning and are only exa0ples. Each para0eter will be defined in detail sep-
arately. In these write ti0ing diagra0s, CK and DQS are shown aligned, and DQS and
DQ are shown center-aligned for the purpose of illustration.
DDR4 WRITE co00and supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-
the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 6, BC4 (BC4 = burst chop)
• A12 = 1, BL8
WRITE co00ands can issue precharge auto0atically with a WRITE with auto pre-
charge (WRA) co00and, which is enabled by A16 HIGH.
• WRITE co00and with A16 = 6 (WR) perfor0s standard write, bank re0ains active af-
ter WRITE burst
• WRITE co00and with A16 = 1 (WRA) perfor0s write with auto precharge, bank goes
into precharge after WRITE burst
The DATA MASK (DM) function is supported for the x8 and x1± configurations only (the
DM function is not supported on x4 devices). The DM function shares a co00on pin
with the DBI_n and TDQS functions. The DM function only applies to WRITE opera-
tions and cannot be enabled at the sa0e ti0e the DBI function is enabled.
• If DM_n is sa0pled LOW on a given byte lane, the DRAM 0asks the write data re-
ceived on the DQ inputs.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
• If DM_n is sa0pled HIGH on a given byte lane, the DRAM does not 0ask the data and
writes this data into the DRAM core.
• If CRC write is enabled, then DM enabled (via MRS) will be selected between write
CRC nonpersistent 0ode (DM disabled) and write CRC persistent 0ode (DM ena-
bled).
Figure 166: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)
T0
T1
T2
T7
T8
T9
T10
T11
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
DES
Bank Group
Address
Bank
Col n
Address
tWPST
tWPRE
DQS_t,
DQS_c
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK.
Notes:
2. DI n = Data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA atency = Disable, Read DBI = Disable.
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WRITE Operation
Figure 167: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)
T0
T1
T2
T9
T10
T11
T17
T18
T19
DES
T20
DES
T21
DES
T22
DES
T23
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
DES
Bank Group
Address
Bank
Col n
Address
t
t
WPST
WPRE
DQS_t,
DQS_c
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
AL = 10
CWL = 9
WL = AL + CWL = 19
Time Break
Transitioning Data
Don’t Care
1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
WRITE Operation Followed by Another WRITE Operation
Figure 168: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
DES
T18
DES
T19
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
WPST
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
Notes:
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WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
Figure 169: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
T17
DES
T18
DES
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
WPST
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 10
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-
ble mode.
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WRITE Operation
Figure 170: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S/L = 5
WTR
Bank Group
Address
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
Address
t
t
WPST
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
Figure 171: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T2
T6
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
T18
T19
DES
T20
CK_c
CK_t
Command
WRITE
DES
DES
WRITE
DES
DES
DES
DES
DES
tWR
tCCD_S/L = 6
4 Clocks
tWTR
Bank Group
Address
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 10
Time Break
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
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WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T20.
8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-
ble mode.
Figure 172: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
T16
DES
T17
DES
T18
T19
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
t
WPST
t
WPST
WPRE
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 173: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
t
WPST
WPRE
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = AL + CWL = 10
Time Break
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-
ble mode.
Figure 174: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
T15
DES
T16
DES
T17
T18
DES
T19
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
t
WR
t
2 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
t
t
t
WPST
t
WPST
WPRE
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
Notes:
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WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.
Figure 175: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
DES
T12
DES
T13
DES
T14
DES
T15
T16
DES
T17
DES
T18
DES
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
tWR
tWTR
tCCD_S = 4
4 Clocks
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 176: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
DES
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
tCCD_S = 4
4 Clocks
tWTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPST
tWPRE
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 9
Time Break
Transitioning Data
Don’t Care
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
WRITE Operation Followed by READ Operation
Figure 177: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
DES
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
tWTR_S = 2
4 Clocks
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6
Time Break
Transitioning Data
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 178: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
DES
T11
T12
DES
T13
DES
T14
DES
T15
T16
DES
T17
T18
DES
T26
DES
T27
DES
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
READ
BGa
tWTR_L = 4
4 Clocks
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2
Time Break
Transitioning Data
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T17.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
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WRITE Operation
Figure 179: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
DES
T24
DES
T25
DES
T26
DES
T27
DES
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
BGb
tWTR_S = 2
4 Clocks
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tWPST
tRPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 180: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
BGa
DES
DES
DES
tWTR_L = 4
4 Clocks
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
b
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T17.
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WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 181: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
T11
DES
T12
T13
DES
T14
DES
T22
DES
T23
DES
T24
T25
DES
T26
DES
T27
DES
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
READ
BGb
tWTR_S = 2
2 Clocks
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tWPST
tRPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T11.
Figure 182: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
DES
T12
DES
T13
T14
DES
T15
T16
DES
T24
DES
T25
DES
T26
DES
T27
DES
T28
DES
T29
DES
CK_c
CK_t
Command
WRITE
BGa
DES
DES
DES
DES
DES
DES
READ
BGa
tWTR_L = 4
2 Clocks
Bank Group
Address
Bank
Col n
Bank
Col b
Address
tWPST
tRPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DI
DI
DI
DI
b
DI
DI
DI
DQ
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
Notes:
2. DI b = data-in from column b.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T11.
WRITE Operation Followed by PRECHARGE Operation
The 0ini0u0 external WRITE co00and to PRECHARGE co00and spacing is equal to
WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The 0in-
i0u0 ACT to PRE ti0ing, tRAS, 0ust be satisfied as well.
Figure 183: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
T12
DES
T13
DES
T14
DES
T22
DES
T23
T24
DES
T25
PRE
T26
DES
CK_c
CK_t
Command
Address
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
4 Clocks
tWR = 12
tRP
BGa, Bank b
Col n
BGa, Bank b
(or all)
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8
setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command
at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
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WRITE Operation
Figure 184: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T22
DES
T23
PRE
T24
DES
T25
DES
T26
DES
CK_c
CK_t
Command
Address
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
2 Clocks
tWR = 12
tRP
BGa, Bank b
Col n
BGa, Bank b
(or all)
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
Time Break
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 185: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T4
T7
T8
T9
T10
DES
T11
T12
DES
T13
DES
T14
DES
T22
DES
T23
T24
DES
T25
DES
T26
DES
CK_c
CK_t
Command
Address
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
4 Clocks
tWR = 12
tRP
BGa, Bank b
Col n
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Time Break
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-
mand at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 186: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
DES
T12
DES
T13
T14
DES
T22
DES
T23
DES
T24
DES
T25
DES
T26
DES
CK_c
CK_t
Command
Address
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
t
RP
WL = AL + CWL = 9
2 Clocks
WR = 12
BGa, Bank b
Col n
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
Time Break
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
CCMTD-1406124318-10419
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WRITE Operation
WRITE Operation with WRITE DBI Enabled
Figure 187: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
DES
T13
DES
T14
DES
T15
DES
T16
DES
T17
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
4 Clocks
tWR
tWTR
Address
Address
BGa
Bank,
Col n
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
DI
n
DI
DI
DI
DBI_n
n + 1 n + 2 n + 3
BL8 Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
DI
n
DI
DI
DI
DI
DI
DI
DI
DBI_n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-
mand at T0.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
bled.
6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the
last write data shown at T13.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 188: WRITE (BC4-Fixed) with 1tCK Preamble and DBI
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
DES
T12
DES
T13
DES
T14
DES
T15
T16
DES
T17
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
2 Clocks
tWR
tWTR
Address
Address
BGa
Bank,
Col n
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DI
DI
DI
DQ
n + 1 n + 2 n + 3
DI
n
DI
DI
DI
DBI_n
n + 1 n + 2 n + 3
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
bled.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
WRITE Operation with CA Parity Enabled
Figure 189: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group
T0
T1
T2
T3
T4
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
DES
CK_c
CK_t
Command
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
WR
t
4 Clocks
t
CCD_S = 4
WTR
Bank Group
Address
BGa
BGb
Bank
Col n
Bank
Col b
Address
Parity
Valid
Valid
t
t
WPST
WPRE
DQS_t,
DQS_c
WL = PL + AL + CWL = 13
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = PL + AL + CWL = 13
Time Break
Transitioning Data
Don’t Care
1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK.
Notes:
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com-
mands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
ble.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
CCMTD-1406124318-10419
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WRITE Operation
WRITE Operation with Write CRC Enabled
Figure 190: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Differ-
ent Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command
WRITE
DES
DES
t
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
t
WR
WTR
4 Clocks
CCD_S/L = 5
Bank Group
Address
BGa or
BGb
BGa
Bank
Col n
Bank
Col b
Address
t
WPST
t
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x4,
BL = 8
CRC
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x8/X16,
BL = 8
CRC
CRC
CRC
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
DQ x4,
BC = 4 (OTF)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
CRC
CRC
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 5tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T5.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 191: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different
Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR
tCCD_S/L = 5
2 Clocks
tWTR
Bank Group
Address
BGa or
BGb
BGa
Bank
Col n
Bank
Col b
Address
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DQ x4,
BC = 4 (Fixed)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
CRC
CRC
CRC
CRC
CRC
CRC
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
WL = AL + CWL = 9
DQ x8/X16,
BC = 4 (Fixed)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 5tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T16.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 192: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Dif-
ferent Bank Group
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7ꢇꢅ
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7ꢇꢋ
7ꢇꢃ
7ꢇꢐ
7ꢇꢂ
7ꢇꢉ
7ꢇꢁ
7ꢇꢑ
7ꢈꢅ
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&.BW
&RPPDQG
:5,7(
'(6
W
'(6
:5,7(
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
'(6
W
W
:5
:75
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W
W
:367
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',
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1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCDD_S/L = 6tCK.
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T6.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T19.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 193: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Dif-
ferent Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CK_c
CK_t
Command
WRITE
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t
t
WR
WTR
t
4 Clocks
CCD_S/L = 7
Bank Group
Address
BGa or
BGb
BGa
Bank
Col n
Bank
Col b
Address
t
WPST
t
t
WPRE
WPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
WL = AL + CWL = 10
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x4,
BL = 8
CRC
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
DI
n
DI
DI
DI
DI
DI
DI
DI
DI
b
DI
DI
DI
DI
DI
DI
DI
DQ x8/X16,
BL = 8
CRC
CRC
CRC
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
b + 1 b + 2 b + 3 b + 4 b + 5 b + 6 b + 7
DQ x4,
BC = 4 (OTF)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
CRC
CRC
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
DI
DI
DI
b
DI
DI
DI
n + 1 n + 2 n + 3
b + 1 b + 2 b + 3
Time Break
Transitioning Data
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCDD_S/L = 7tCK
(see Note 7).
Notes:
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T7.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T7.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. tCDD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCDD_S/L allowed in
1tCK preamble mode would have been 6 clocks.
8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble
mode.
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8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 194: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank
Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
tWR_CRC_DM
4 Clocks
tWTR_S_CRC_DM/tWTR_L_CRC_DM
Bank Group
Address
BGa
Bank
Col n
Address
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ x4,
BL = 8
CRC
CRC
CRC
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
DI
n
DI
DI
DI
DI
DI
DI
DI
DQ x8/X16,
BL = 8
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
DM
n
DM
DM
DM
DM
DM
DM
DM
DMx4/x8/x16
BL = 8
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
DQ x4,
BC = 4 (OTF/Fixed)
DI
n
DI
DI
DI
CRC
CRC
CRC
n + 1 n + 2 n + 3
DQ x8/X16,
BC = 4 (OTF/Fixed)
DI
n
DI
DI
DI
n + 1 n + 2 n + 3
DM x4/x8/x16
BC = 4 (OTF / Fixed)
DM
n
DM
DM
DM
n + 1 n + 2 n + 3
Time Break
Transitioning Data
Don’t Care
1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
Notes:
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during
WRITE command at T0.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Enable.
7. The write recovery time (tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/
tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write da-
ta shown at T13.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Write Timing Violations
Write Timing Violations
Motivation
Generally, if ti0ing para0eters are violated, a co0plete reset/initialization procedure
has to be initiated to 0ake sure that the device works properly. However, for certain 0i-
nor violations, it is desirable that the device is guaranteed not to "hang up" and that er-
rors are li0ited to that specific operation. A 0inor violation does not include a 0ajor
ti0ing violation (for exa0ple, when a DQS strobe 0isses in the tDQSCK window).
For the following, it will be assu0ed that there are no ti0ing violations with regard to
the WRITE co00and itself (including ODT, and so on) and that it does satisfy all ti0ing
require0ents not 0entioned below.
Data Setup and Hold Violations
If the data-to-strobe ti0ing require0ents (tDS, tDH) are violated, for any of the strobe
edges associated with a WRITE burst, then wrong data 0ight be written to the 0e0ory
location addressed with this WRITE co00and.
In the exa0ple, the relevant strobe edges for WRITE Burst A are associated with the
clock edges: T5, T5.5, T±, T±.5, T7, T7.5, T8, and T8.5.
Subsequent reads fro0 that location 0ight result in unpredictable read data; however,
the device will work properly otherwise.
Strobe-to-Strobe and Strobe-to-Clock Violations
If the strobe ti0ing require0ents (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock
ti0ing require0ents (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges asso-
ciated with a WRITE burst, then wrong data 0ight be written to the 0e0ory location
addressed with the offending WRITE co00and. Subsequent reads fro0 that location
0ight result in unpredictable read data; however, the device will work properly other-
wise with the following constraints:
• Both write CRC and data burst OTF are disabled; ti0ing specifications other than
tDQSH, tDQSL, tWPRE, tWPST, tDSS, tDSH, tDQSS are not violated.
• The offending write strobe (and prea0ble) arrive no earlier or later than six DQS tran-
sition edges fro0 the WRITE latency position.
• A READ co00and following an offending WRITE co00and fro0 any open bank is
allowed.
• One or 0ore subsequent WR or a subsequent WRA (to sa0e bank as offending WR)
0ay be issued tCCD_L later, but incorrect data could be written. Subsequent WR and
WRA can be either offending or non-offending writes. Reads fro0 these writes 0ay
provide incorrect data.
• One or 0ore subsequent WR or a subsequent WRA (to a different bank group) 0ay be
issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA
can be either offending or non-offending writes. Reads fro0 these writes 0ay provide
incorrect data.
• After one or 0ore precharge co00ands (PRE or PREA) are issued to the device after
an offending WRITE co00and and all banks are in precharged state (idle state), a
subsequent, non-offending WR or WRA to any open bank will be able to write correct
data.
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8Gb: x8, x16 Automotive DDR4 SDRAM
ZQ CALIBRATION Commands
ZQ CALIBRATION Commands
A ZQ CALIBRATION co00and is used to calibrate DRAM RON and ODT values. The de-
vice needs a longer ti0e to calibrate the output driver and on-die ter0ination circuits
at initialization and a relatively s0aller ti0e to perfor0 periodic calibrations.
The ZQCL co00and is used to perfor0 the initial calibration during the power-up ini-
tialization sequence. This co00and 0ay be issued at any ti0e by the controller de-
pending on the syste0 environ0ent. The ZQCL co00and triggers the calibration en-
gine inside the DRAM and, after calibration is achieved, the calibrated values are trans-
ferred fro0 the calibration engine to DRAM I/O, which is reflected as an updated out-
put driver and ODT values.
The first ZQCL co00and issued after reset is allowed a ti0ing period of tZQinit to per-
for0 the full calibration and the transfer of values. All other ZQCL co00ands except
the first ZQCL co00and issued after reset are allowed a ti0ing period of tZQoper.
The ZQCS co00and is used to perfor0 periodic calibrations to account for voltage and
te0perature variations. A shorter ti0ing window is provided to perfor0 the calibration
and transfer of values as defined by ti0ing para0eter tZQCS. One ZQCS co00and can
effectively correct a 0ini0u0 of 6.5% (ZQ correction) of RON and RTT i0pedance error
within ±4 nCK for all speed bins assu0ing the 0axi0u0 sensitivities specified in the
Output Driver and ODT Voltage and Te0perature Sensitivity tables. The appropriate in-
terval between ZQCS co00ands can be deter0ined fro0 these tables and other appli-
cation-specific para0eters. One 0ethod for calculating the interval between ZQCS
co00ands, given the te0perature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the
device is subjected to in the application, is illustrated. The interval could be defined by
the following for0ula:
ZQ
correction
(T
x T
) + (V
x T
)
sense drift_rate sense drift_rate
Where Tsense = MAX(dRTTdT, dRONdTM) and Vsense = MAX(dRTTdV, dRONdVM) define
the te0perature and voltage sensitivities.
For exa0ple, if Tsens = 1.5%/°C, Vsens = 6.15%/0V, Tdriftrate = 1 °C/sec and Vdriftrate = 15
0V/sec, then the interval between ZQCS co00ands is calculated as:
0.5
= 0.133 §128ms
(1.5 × 1) + (0.15 × 15)
No other activities should be perfor0ed on the DRAM channel by the controller for the
duration of tZQinit, tZQoper, or tZQCS. The quiet ti0e on the DRAM channel allows ac-
curate calibration of output driver and on-die ter0ination values. After DRAM calibra-
tion is achieved, the device should disable the ZQ current consu0ption path to reduce
power.
All banks 0ust be precharged and tRP 0et before ZQCL or ZQCS co00ands are issued
by the controller.
ZQ CALIBRATION co00ands can also be issued in parallel to DLL lock ti0e when
co0ing out of self refresh. Upon self refresh exit, the device will not perfor0 an I/O cali-
bration without an explicit ZQ CALIBRATION co00and. The earliest possible ti0e for a
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
ZQ CALIBRATION Commands
ZQ CALIBRATION co00and (short or long) after self refresh exit is tXS, tXS_Abort, or
tXS_FAST depending on operation 0ode.
In syste0s that share the ZQ resistor between devices, the controller 0ust not allow any
overlap of tZQoper, tZQinit, or tZQCS between the devices.
Figure 195: ZQ Calibration Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
DES
Tc0
Tc1
Tc2
CK_c
CK_t
Command
Address
A10
ZQCL
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
ZQCS
DES
DES
Valid
Valid
Valid
CKE
Valid
Valid
Valid
Valid
Valid
Valid
Note 1
Note 2
ODT
DQ Bus
High-Z or RTT(Park)
High-Z or RTT(Park)
Activities
Activities
Note 3
t
t
ZQinit_ ZQoper
t
ZQCS
Time Break
Don’t Care
1. CKE must be continuously registered HIGH during the calibration procedure.
Notes:
2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to pro-
vide RTT_PARK.
3. All devices connected to the DQ bus should be High-Z during the calibration procedure.
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On-Die Termination
On-Die Termination
The on-die ter0ination (ODT) feature enables the device to change ter0ination resist-
ance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and
TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control
pin, WRITE co00and, or default parking value with MR setting. For the x1± configura-
tion, ODT is applied to each DQU, DQL, DQSU, DQSL, DMU_n/DBIU_n, and DML_n/
DBIL_n signal. The ODT feature is designed to i0prove the signal integrity of the 0e0-
ory channel by allowing the DRAM controller to independently change ter0ination re-
sistance for any or all DRAM devices. If DBI read 0ode is enabled while the DRAM is in
standby, either DM 0ode or DBI write 0ode 0ust also be enabled if RTT(NOM) or
RTT(Park) is desired. More details about ODT control 0odes and ODT ti0ing 0odes can
be found further along in this docu0ent.
The ODT feature is turned off and not supported in self refresh 0ode.
Figure 196: Functional Representation of ODT
ODT
VDDQ
To other
circuitry
such as
RCV,
RTT
Switch
DQ, DQS, DM, TDQS
. . .
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control infor0ation. The value of RTT is deter0ined by the settings of
0ode register bits (see Mode Register). The ODT pin will be ignored if the 0ode register
MR1 is progra00ed to disable RTT(NOM) [MR1[16,9,8] = 6,6,6] and in self refresh 0ode.
ODT Mode Register and ODT State Table
The ODT 0ode of the DDR4 device has four states: data ter0ination disable, RTT(NOM)
TT(WR), and RTT(Park). The ODT 0ode is enabled if any of MR1[16:8] (RTT(NOM)),
,
R
MR2[11:9] (RTT(WR)), or MR5[8:±] (RTT(Park)) are non-zero. When enabled, the value of
RTT is deter0ined by the settings of these bits.
RTT control of each RTT condition is possible with a WR or RD co00and and ODT pin.
• RTT(WR): The DRAM (rank) that is being written to provide ter0ination regardless of
ODT pin status (either HIGH or LOW).
• RTT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT
is disabled by MR1).
• RTT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned
on.
• The Ter0ination State Table that follows shows various interactions.
The RTT values have the following priority:
• Data ter0ination disable
• RTT(WR)
• RTT(NOM)
• RTT(Park)
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ODT Mode Register and ODT State Table
Table 71: Termination State Table
Case
RTT(Park)
RTT(NOM)
1
RTT(WR)
2
ODT Pin
ODT READS3 ODT Standby ODT WRITES
A4
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Don't Care
Don't Care
Don't Care
Don't Care
Low
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
Off (High-Z)
RTT(Park)
Off (High-Z)
RTT(WR)
B5
C6
Enabled
Disabled
RTT(Park)
RTT(WR)
RTT(Park)
Off (High-Z)
RTT(NOM)
Off (High-Z)
RTT(NOM)
RTT(WR)
High
Enabled
Disabled
Enabled
Low
Off (High-Z)
RTT(NOM)
High
RTT(WR)
D6
Enabled
Enabled
Low
RTT(Park)
RTT(Park)
RTT(NOM)
RTT(WR)
High
RTT(NOM)
Low
RTT(Park)
High
RTT(NOM)
RTT(WR)
1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power.
Notes:
2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period
time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in
the Dynamic ODT section.
3. When a READ command is executed, the DRAM termination state will be High-Z for a
defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is
described in the ODT During Read section.
4. Case A is generally best for single-rank memories.
5. Case B is generally best for dual-rank, single-slotted memories.
6. Case C and Case D are generally best for multi-slotted memories.
ODT Read Disable State Table
Upon receiving a READ co00and, the DRAM driving data disables ODT after RL - (2 or
3) clock cycles, where 2 = 1tCK prea0ble 0ode and 3 = 2tCK prea0ble 0ode. ODT stays
off for a duration of BL/2 + (2 or 3) + (6 or 1) clock cycles, where 2 = 1tCK prea0ble
0ode, 3 = 2tCK prea0ble 0ode, 6 = CRC disabled, and 1 = CRC enabled.
Table 72: Read Termination Disable Window
Start ODT Disable After
Read
Preamble
CRC
Duration of ODT Disable
1tCK
Disabled
Enabled
Disabled
Enabled
RL - 2
RL - 2
RL - 3
RL - 3
BL/2 + 2
BL/2 + 3
BL/2 + 3
BL/2 + 4
2tCK
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Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT 0ode is selected whenever the DLL is turned on and locked. Based
on the power-down definition, these 0odes include the following:
• Any bank active with CKE HIGH
• Refresh with CKE HIGH
• Idle 0ode with CKE HIGH
• Active power-down 0ode (regardless of MR1 bit A16)
• Precharge power-down 0ode
In synchronous ODT 0ode, RTT(NOM) will be turned on DODTLon clock cycles after
ODT is sa0pled HIGH by a rising clock edge and turned off DODTLoff clock cycles after
ODT is registered LOW by a rising clock edge. The ODT latency is deter0ined by the
progra00ed values for: CAS WRITE latency (CWL), additive latency (AL), and parity la-
tency (PL), as well as the progra00ed state of the prea0ble.
ODT Latency and Posted ODT
The ODT latencies for synchronous ODT 0ode are su00arized in the table below. For
details, refer to the latency definitions.
Table 73: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200
Applicable when write CRC is disabled
Symbol
DODTLon
DODTLoff
Parameter
1tCK Preamble
CWL + AL + PL - 2
CWL + AL + PL - 2
CL + AL + PL - 2
2tCK Preamble
CWL + AL + PL - 3
CWL + AL + PL - 3
CL + AL + PL - 3
Unit
tCK
Direct ODT turn-on latency
Direct ODT turn-off latency
RODTLoff READ command to internal ODT turn-off
latency
RODTLon4
READ command to RTT(Park) turn-on la-
tency in BC4-fixed
RODTLoff + 4
RODTLoff + 6
RODTLoff + 5
RODTLoff + 7
RODTLon8
READ command to RTT(Park) turn-on la-
tency in BL8/BC4-OTF
ODTH4
ODTH8
ODT Assertion time, BC4 mode
ODT Assertion time, BL8 mode
4
6
5
7
Timing Parameters
In synchronous ODT 0ode, the following para0eters apply:
• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX).
t
• ADC (MIN) and tADC (MAX) are 0ini0u0 and 0axi0u0 RTT change ti0ing skew
between different ter0ination values. These ti0ing para0eters apply to both the syn-
chronous ODT 0ode and the data ter0ination disable 0ode.
When ODT is asserted, it 0ust re0ain HIGH until 0ini0u0 ODTH4 (BC = 4) or
ODTH8 (BL = 8) is satisfied. If write CRC 0ode or 2tCK prea0ble 0ode is enabled,
ODTH should be adjusted to account for it. ODTHx is 0easured fro0 ODT first regis-
tered HIGH to ODT first registered LOW or fro0 the registration of a WRITE co00and.
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Synchronous ODT Mode
Figure 197: Synchronous ODT Timing with BL8
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ODT
DODTLon = WL - 2
DODTLoff = WL - 2
t
t
ADC (MAX)
ADC (MAX)
t
t
ADC (MIN)
ADC (MIN)
DRAM_R
TT
R
R
R
TT(Park)
TT(NOM)
TT(Park)
Transitioning
1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL +
PL + CWL - 2 = 7.
Notes:
2. ODT must be held HIGH for at least ODTH8 after assertion (T1).
Figure 198: Synchronous ODT with BC4
T0
T1
T2
T3
T4
T5
T18
T19
T20
T21
T22
T23
T36
T37
T38
T39
T40
T41
42
diff_CK
WRS4
Command
ODTH4
ODT
DODTLoff = WL - 2
ODTLcnw= WL - 2
DODTLon = CWL - 2
ODTLcwn4 = ODTLcnw + 4
tADC (MAX)
tADC (MIN)
tADC (MAX)
tADC (MAX)
tADC (MIN)
tADC (MAX)
tADC (MIN)
tADC (MIN)
RTT(Park)
RTT(NOM)
RTT(Park)
RTT(WR)
RTT(Park)
DRAM_RTT
Transitioning
1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw =
AL + PL+ CWL - 2 = 17.
Notes:
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
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Synchronous ODT Mode
ODT During Reads
Because the DRAM cannot ter0inate with RTT and drive with RON at the sa0e ti0e, RTT
0ay no0inally not be enabled until the end of the posta0ble as shown in the exa0ple
below. At cycle T25 the device turns on the ter0ination when it stops driving, which is
deter0ined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC
(MIN) ti0ing 0ay apply. If the DRAM stops driving late (that is, tHZ is late), then the
DRAM co0plies with tADC (MAX) ti0ing.
Using CL = 11 as an exa0ple for the figure below: PL = 6, AL = CL - 1 = 16, RL = PL + AL +
CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK
prea0ble.
Figure 199: ODT During Reads
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Dynamic ODT
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is
desirable that the ter0ination strength of the device can be changed without issuing an
MRS co00and. This require0ent is supported by the dyna0ic ODT feature.
Functional Description
Dyna0ic ODT 0ode is enabled if bit A9 or A16 of MR2 is set to 1.
• Three RTT values are available: RTT(NOM), RTT(WR), and RTT(Park)
.
– The value for RTT(NOM) is preselected via bits MR1[16:8].
– The value for RTT(WR) is preselected via bits MR2[11:9].
– The value for RTT(Park) is preselected via bits MR5[8:±].
• During operation without WRITE co00ands, the ter0ination is controlled as fol-
lows:
– No0inal ter0ination strength RTT(NOM) or RTT(Park) is selected.
– RTT(NOM) on/off ti0ing is controlled via ODT pin and latencies DODTLon and
DODTLoff, and RTT(Park) is on when ODT is LOW.
• When a WRITE co00and (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is regis-
tered, and if dyna0ic ODT is enabled, the ter0ination is controlled as follows:
– Latency ODTLcnw after the WRITE co00and, ter0ination strength RTT(WR) is se-
lected.
– Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for
BC4, fixed by MRS or selected OTF) after the WRITE co00and, ter0ination
strength RTT(WR) is de-selected.
One or two clocks will be added into or subtracted fro0 ODTLcwn8 and ODTLcwn4,
depending on write CRC 0ode and/or 2tCK prea0ble enable0ent.
The following table shows latencies and ti0ing para0eters relevant to the on-die ter0i-
nation control in dyna0ic ODT 0ode. The dyna0ic ODT feature is not supported in
DLL-off 0ode. An MRS co00and 0ust be used to set RTT(WR) to disable dyna0ic ODT
externally (MR2[11:9] = 666).
Table 74: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled)
Definition for All
Name and Description
Abbr.
Defined from
Defined to
DDR4 Speed Bins
Unit
ODT latency for change from
ODTLcnw Registering external Change RTT strength
ODTLcnw = WL - 2
tCK
RTT(Park)/RTT(NOM) to RTT(WR)
WRITE command
from RTT(Park)/RTT(NOM)
to RTT(WR)
ODT latency for change from
TT(WR) to RTT(Park)/RTT(NOM) (BC =
4)
ODTLcwn Registering external Change RTT strength
WRITE command from RTT(WR) to
TT(Park)/RTT(NOM)
ODTLcwn Registering external Change RTT strength
ODTLcwn4 = 4 +
ODTLcnw
tCK
R
4
R
ODT latency for change from
ODTLcwn8 = 6 +
ODTLcnw
tCK
(AVG)
RTT(WR) to RTT(Park)/RTT(NOM) (BL =
8
WRITE command
from RTT(NOM) to
RTT(WR)
8)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC (MIN) = 0.3
tADC (MAX) = 0.7
tCK
(AVG)
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Dynamic ODT
Table 75: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix
1tCK Parameter
CRC Off
2tCK Parameter
CRC Off
Symbol
ODTLcnw1
ODTLcwn4
ODTLcwn8
CRC On
WL - 2
CRC On
WL - 3
Unit
tCK
WL - 2
WL - 3
ODTLcnw + 4
ODTLcnw + 6
ODTLcnw + 7
ODTLcnw + 7
ODTLcnw + 5
ODTLcnw + 7
ODTLcnw + 8
ODTLcnw + 8
1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
Note:
Figure 200: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T8
T9
T10
T11
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
diff_CK
WR
Command
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
t
t
t
t
ADC (MAX)
ADC (MAX)
ADC (MAX)
ADC (MAX)
R
TT
t
t
t
t
ADC (MIN)
ADC (MIN)
ADC (MIN)
ADC (MIN)
ODTLcnw
ODTLcwn
Transitioning
1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
Notes:
2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then
ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.
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Dynamic ODT
Figure 201: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T9
T10
T11
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
diff_CK
WR
Command
ODT
ODTLcnw
ODTLcwn8
t
t
t
ADC (MAX)
ADC (MAX)
ADC (MAX)
R
R
R
R
R
TT_PARK
TT
TT_NOM
TT_WR
TT_NOM
t
t
t
ADC (MIN)
ADC (MIN)
ADC (MIN)
DODTLoff = CWL -2
1. Behavior with WR command issued while ODT is registered HIGH.
Note:
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Asynchronous ODT Mode
Asynchronous ODT Mode
Asynchronous ODT 0ode is selected when the DRAM runs in DLL-off 0ode. In asyn-
chronous ODT ti0ing 0ode, the internal ODT co00and is not delayed by either addi-
tive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)).
In asynchronous ODT 0ode, two ti0ing para0eters apply: tAONAS (MIN/MAX), and
tAOFAS (MIN/MAX).
R
TT(NOM) Turn-on Time
• Mini0u0 RTT(NOM) turn-on ti0e (tAONAS [MIN]) is when the device ter0ination cir-
cuit leaves RTT(Park) and ODT resistance begins to turn on.
• Maxi0u0 RTT(NOM) turn-on ti0e (tAONAS [MAX]) is when the ODT resistance has
reached RTT(NOM)
.
• AONAS (MIN) and tAONAS (MAX) are 0easured fro0 ODT being sa0pled HIGH.
t
RTT(NOM) Turn-off Time
• Mini0u0 RTT(NOM) turn-off ti0e (tAOFAS [MIN]) is when the device's ter0ination
circuit starts to leave RTT(NOM)
.
• Maxi0u0 RTT(NOM) turn-off ti0e (tAOFAS [MAX]) is when the on-die ter0ination has
reached RTT(Park)
.
• AOFAS (MIN) and tAOFAS (MAX) are 0easured fro0 ODT being sa0pled LOW.
t
Figure 202: Asynchronous ODT Timings with DLL Off
T0
T1
T2
T3
T4
T5
T6
Ti
Ti + 1
Ti + 2
Ti + 3
Ti + 4
Ti + 5
Ti + 6
Ta
Tb
diff_CK
CKE
tIH
tIS
tIH
tIS
ODT
tAONAS (MAX)
tAONAS (MIN)
tAONAS (MIN)
tAONAS (MAX)
RTT
RTT(Park)
RTT(NOM)
Transitioning
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Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed 0ay cause per0anent da0age to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not i0-
plied. Exposure to absolute 0axi0u0 rating conditions for extended periods 0ay ad-
versely affect reliability. Although "unli0ited" row accesses to the sa0e row is allowed
within the refresh period; excessive row accesses to the sa0e row over a long ter0 can
result in degraded operation.
Table 76: Absolute Maximum Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to VSS
Min
–0.4
–0.4
–0.4
–0.4
–55
Max
1.5
Unit
V
Notes
1
1
3
VDDQ
VPP
Voltage on VDDQ pin relative to VSS
Voltage on VPP pin relative to VSS
1.5
V
3.0
V
VIN, VOUT Voltage on any pin relative to VSS
TSTG Storage temperature
1.5
V
150
°C
2
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
Notes:
greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV.
2. Storage temperature is the case surface temperature on the center/top side of the
DRAM. For the measurement conditions, please refer to the JESD51-2 standard.
3. VPP must be equal to or greater than VDD/VDDQ at all times when powered.
DRAM Component Operating Temperature Range
Operating te0perature, TOPER, is the case surface te0perature on the center/top side of
the DRAM. For 0easure0ent conditions, refer to the JEDEC docu0ent JESD51-2.
Table 77: Temperature Range
Symbol
Parameter
Min
–40
Max
85
Unit
°C
Notes
TOPER
Normal operating temperature range
Extended temperature range (optional)
1
2
>85
125
°C
1. The normal temperature range specifies the temperatures at which all DRAM specifica-
tions will be supported. During operation, the DRAM case temperature must be main-
tained between –40°C to 85°C under all operating conditions for the commercial offer-
ing.
Notes:
2. Some applications require operation of the commercial and industrial temperature
DRAMs in the extended temperature range (between 85°C and 125°C case tempera-
ture). Full specifications are supported in this range, but the following additional condi-
tions apply:
• REFRESH commands must be doubled in frequency, reducing the refresh interval tREFI
to 3.9μs. It is also possible to specify a component with 1X refresh (tREFI to 7.8μs) in
the extended temperature range.
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Electrical Characteristics – AC and DC Operating Conditions
• REFRESH command must be issued once every 0.975μs if TC is greater than 105°C, once
every 1.95μs if TC is greater than or equal to 95°C, once every 3.9μs if TC is greater
than 85°C, and once every 7.8μs if TC is less than 85°C.
Electrical Characteristics – AC and DC Operating Conditions
Supply Operating Conditions
Table 78: Recommended Supply Operating Conditions
Rating
Symbol Parameter
Min
1.14
Typ
1.2
1.2
2.5
Max
1.26
Unit
V
Notes
1, 2, 3, 4, 5
1, 2, 6
VDD
VDDQ
VPP
Supply voltage
Supply voltage for output
Wordline supply voltage
1.14
1.26
V
2.375
2.750
V
7
1. Under all conditions VDDQ must be less than or equal to VDD
.
Notes:
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600
V/ms, 20 MHz band-limited measurement.
4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms.
5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than
VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa-
tion, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of 60mV (greater than 250 KHz) is allowed on VDD provided the noise
doesn't alter VDD to less than VDD,min or greater than VDD,max
6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than
DDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial-
.
V
ization, the DLL reset and calibrations must be performed again after the new set DC
level is final. AC noise of 60mV (greater than 250 KHz) is allowed on VDDQ provided the
noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max
7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than
PP,min and no greater than VPP,max. If the set DC level is altered anytime after initializa-
.
V
tion, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of 120mV (greater than 250 KHz) is allowed on VPP provided the noise
doesn't alter VPP to less than VPP,min or greater than VPP,max
.
Table 79: VDD Slew Rate
Symbol
VDD_sl
Min
0.004
–
Max
600
Unit
V/ms
ms
Notes
1, 2
3
VDD_on
200
1. Measurement made between 300mV and 80% VDD (minimum level).
2. The DC bandwidth is limited to 20 MHz.
Notes:
3. Maximum time to ramp VDD from 300 mV to VDD minimum.
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Electrical Characteristics – AC and DC Operating Conditions
Leakages
Table 80: Leakages
Condition
Symbol
IIN
Min
–2
Max
Unit
μA
μA
μA
μA
μA
μA
Notes
Input leakage (excluding ZQ and TEN)
ZQ leakage
2
3
1
1
IZQ
–3
TEN leakage
ITEN
–6
10
2
1, 2
3
VREFCA leakage
IVREFCA
IOZpd
IOZpu
–2
Output leakage: VOUT = VDDQ
Output leakage: VOUT = VSSQ
–
5
4
–50
–
4, 5
1. Input under test 0V < VIN < 1.1V.
Notes:
2. Additional leakage due to weak pull-down.
3. VREFCA = VDD/2, VDD at valid level after initialization.
4. DQs are disabled.
5. ODT is disabled with the ODT input HIGH.
VREFCA Supply
VREFCA is to be supplied to the DRAM and equal to VDD/2. The VREFCA is a reference sup-
ply input and therefore does not draw biasing current.
The DC-tolerance li0its and AC-noise li0its for the reference voltages VREFCA are illus-
trated in the figure below. The figure shows a valid reference voltage VREF(t) as a function
of ti0e (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long
period of ti0e (1 second). This average has to 0eet the MIN/MAX require0ents. Fur-
ther0ore, VREF(t) 0ay te0porarily deviate fro0 VREF(DC) by no 0ore than ±1% VDD for
the AC-noise li0it.
Figure 203: VREFDQ Voltage Range
Voltage
V
DD
V
REF(t)
V
AC-noise
REF
V
V
MAX
MIN
REF(DC)
V
REF(DC)
/2
DD
V
REF(DC)
V
SS
Time
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Electrical Characteristics – AC and DC Operating Conditions
The voltage levels for setup and hold ti0e 0easure0ents are dependent on VREF. VREF is
understood as VREF(DC), as defined in the above figure. This clarifies that DC-variations
of VREF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW
level, and therefore, the ti0e to which setup and hold is 0easured. Syste0 ti0ing and
voltage budgets need to account for VREF(DC) deviations fro0 the opti0u0 position
within the data-eye of the input signals. This also clarifies that the DRAM setup/hold
specification and derating values need to include ti0e and voltage associated with VREF
AC-noise. Ti0ing and voltage effects due to AC-noise on VREF up to the specified li0it
(±1% of VDD) are included in DRAM ti0ings and their associated deratings.
VREFDQ Supply and Calibration Ranges
The device internally generates its own VREFDQ. DRAM internal VREFDQ specification pa-
ra0eters: voltage range, step size, VREF step ti0e, VREF full step ti0e, and VREF valid level
are used to help provide esti0ated values for the internal VREFDQ and are not pass/fail
li0its. The voltage operating range specifies the 0ini0u0 required range for DDR4
SDRAM devices. The 0ini0u0 range is defined by VREFDQ,0in and VREFDQ,0ax. A cali-
bration sequence should be perfor0ed by the DRAM controller to adjust VREFDQ and
opti0ize the ti0ing and voltage 0argin of the DRAM data input receivers.
Table 81: VREFDQ Specification
Parameter
Symbol
VREFDQ R1
VREFDQ R2
VREF,step
Min
60%
Typ
–
Max
92%
Unit
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
ns
Notes
1, 2
Range 1 VREFDQ operating points
Range 2 VREFDQ operating points
VREF step size
45%
–
77%
1, 2
0.5%
–1.625%
–0.15%
–
0.65%
0%
0%
–
0.8%
1.625%
0.15%
150
3
VREF set tolerance
VREF,set_tol
4, 5, 6
4, 7, 8
9, 10, 11
12
VREF step time
VREF,time
VREF valid tolerance
VREF_val_tol
–0.15%
0%
0.15%
VDDQ
1. VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V.
2. DRAM range 1 or range 2 is set by the MRS6[6]6.
Notes:
3. VREF step size increment/decrement range. VREF at DC level.
4. VREF,new = VREF,old n × VREF,step; n = number of steps. If increment, use “+,” if decrement,
use “-.”
5. For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ
.
6. Measured by recording the MIN and MAX values of the VREF output over the range,
drawing a straight line between those points, and comparing all other VREF output set-
tings to that line.
7. For n ≤4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ
.
8. Measured by recording the MIN and MAX values of the VREF output across four consecu-
tive steps (n = 4), drawing a straight line between those points, and comparing all VREF
output settings to that line.
9. Time from MRS command to increment or decrement one step size for VREF
10. Time from MRS command to increment or decrement more than one step size up to the
full range of VREF
.
.
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Electrical Characteristics – AC and DC Operating Conditions
11. If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and
an additional +15 ns/pF of DQ bus loading.
12. Only applicable for DRAM component-level test/characterization purposes. Not applica-
ble for normal mode of operation. VREF valid qualifies the step times, which will be char-
acterized at the component level.
VREFDQ Ranges
MR±[±] selects range 1 (±6% to 92.5% of VDDQ) or range 2 (45% to 77.5% of VDDQ), and
MR±[5:6] sets the VREFDQ level, as listed in the following table. The values in MR±[±:6]
will update the VDDQ range and level independent of MR±[7] setting. It is reco00ended
MR±[7] be enabled when changing the settings in MR±[±:6], and it is highly reco00en-
ded MR±[7] be enabled when changing the settings in MR±[±:6] 0ultiple ti0es during a
calibration routine.
Table 82: VREFDQ Range and Levels
MR6[6] 0 =
MR6[6] 1 =
Range 2
MR6[6] 0 =
Range 1
MR6[6] 1 =
Range 2
MR6[5:0]
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111
01 1000
01 1001
Range 1
60.00%
60.65%
61.30%
61.95%
62.60%
63.25%
63.90%
64.55%
65.20%
65.85%
66.50%
67.15%
67.80%
68.45%
69.10%
69.75%
70.40%
71.05%
71.70%
72.35%
73.00%
73.65%
74.30%
74.95%
75.60%
76.25%
MR6[5:0]
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111
10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111
11 0000
11 0001
11 0010
45.00%
45.65%
46.30%
46.95%
47.60%
48.25%
48.90%
49.55%
50.20%
50.85%
51.50%
52.15%
52.80%
53.45%
54.10%
54.75%
55.40%
56.05%
56.70%
57.35%
58.00%
58.65%
59.30%
59.95%
60.60%
61.25%
76.90%
77.55%
78.20%
78.85%
79.50%
80.15%
80.80%
81.45%
82.10%
82.75%
83.40%
84.05%
84.70%
85.35%
86.00%
86.65%
87.30%
87.95%
88.60%
89.25%
89.90%
90.55%
91.20%
91.85%
92.50%
61.90%
62.55%
63.20%
63.85%
64.50%
65.15%
65.80%
66.45%
67.10%
67.75%
68.40%
69.05%
69.70%
70.35%
71.00%
71.65%
72.30%
72.95%
73.60%
74.25%
74.90%
75.55%
76.20%
76.85%
77.50%
11 0011 to 11 1111 are reserved
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Electrical Characteristics – AC and DC Single-Ended Input Measurement
Levels
RESET_n Input Levels
Table 83: RESET_n Input Levels (CMOS)
Parameter
Symbol
VIH(AC)_RESET
VIH(DC)_RESET
VIL(DC)_RESET
VIL(AC)_RESET
tR_RESET
Min
Max
Unit
V
Note
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Rising time
0.8 × VDD
VDD
1
2
0.7 × VDD
VDD
V
VSS
VSS
–
0.3 × VDD
V
3
0.2 × VDD
V
4
1
–
–
μs
μs
μs
5
RESET pulse width after power-up
RESET pulse width during power-up
tPW_RESET_S
tPW_RESET_L
1
6, 7
6
200
1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
Notes:
VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RE-
SET during tPW_RESET, otherwise the DRAM may not be reset.
4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-
gated as much as possible.
6. RESET is destructive to data contents.
7. See RESET Procedure at Power Stable Condition figure.
Figure 204: RESET_n Input Slew Rate Definition
tPW_RESET
VIH(AC)_RESET,min
VIH(DC)_RESET,min
VIL(DC)_RESET,max
VIL(AC)_RESET,max
tR_RESET
Command/Address Input Levels
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400
Parameter
Symbol
Min
Max
VDD
Unit
Note
AC input high voltage
VIH(AC)
VREF + 100
5
mV
1, 2, 3
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)
Parameter
Symbol
VIH(DC)
Min
VREF + 75
VSS
Max
VDD
Unit
mV
mV
mV
V
Note
1, 2
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
VIL(DC)
VREF - 75
VREF - 100
0.51 × VDD
1, 2
VIL(AC)
VSS5
1, 2, 3
4
VREFFCA(DC)
0.49 × VDD
1. For input except RESET_n. VREF = VREFCA(DC)
2. VREF = VREFCA(DC)
.
Notes:
.
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
1% VDD (for reference: approximately 12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 85: Command and Address Input Levels: DDR4-2666
Parameter
Symbol
VIH(AC)
Min
VREF + 90
VREF + 65
VSS
Max
VDD
Unit
mV
mV
mV
mV
V
Note
1, 2, 3
1, 2
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
5
VIH(DC)
VDD
VIL(DC)
VREF - 65
VREF - 90
0.51 × VDD
1, 2
VIL(AC)
VSS5
1, 2, 3
4
VREFFCA(DC)
0.49 × VDD
1. For input except RESET_n. VREF = VREFCA(DC)
2. VREF = VREFCA(DC)
.
Notes:
.
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
1% VDD (for reference: approximately 12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200
Parameter
Symbol
VIH(AC)
Min
VREF + 90
VREF + 65
VSS
Max
VDD
Unit
mV
mV
mV
mV
V
Note
1, 2, 3
1, 2
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
5
VIH(DC)
VDD
VIL(DC)
VREF - 65
VREF - 90
0.51 × VDD
1, 2
VIL(AC)
VSS5
1, 2, 3
4
VREFFCA(DC)
0.49 × VDD
1. For input except RESET_n. VREF = VREFCA(DC)
2. VREF = VREFCA(DC)
.
Notes:
.
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
1% VDD (for reference: approximately 12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 87: Single-Ended Input Slew Rates
Parameter
Symbol
Min
Max
Unit
Note
Single-ended input slew rate – CA
SRCA
1.0
7.0
V/ns
1, 2, 3, 4
1. For input except RESET_n.
2. VREF = VREFCA(DC)
3. tIS/tIH timings assume SRCA = 1V/ns.
Notes:
.
4. Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC)
for rising edges
Figure 205: Single-Ended Input Slew Rate Definition
TR
TFse
se
V
IH(AC)
V
IH(DC)
V
REFCA
V
IL(DC)
V
IL(AC)
Command, Control, and Address Setup, Hold, and Derating
The total tIS (setup ti0e) and tIH (hold ti0e) required is calculated to account for slew
rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and
tIH (base) values, the VIL(DC)/VIH(DC) points; to the ǻtIS and ǻtIH derating values, respec-
tively. The base values are derived with single-end signals at 1V/ns and differential clock
t
at 2 V/ns. Exa0ple: IS (total setup ti0e) = tIS (base) + ǻtIS. For a valid transition, the
input signal has to re0ain above/below VIH(AC)/VIL(AC) for the ti0e defined by tVAC.
Although the total setup ti0e for slow slew rates 0ight be negative (for exa0ple, a valid
input signal will not have reached VIH(AC)/VIL(AC) at the ti0e of the rising clock transi-
tion), a valid input signal is still required to co0plete the transition and to reach
VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the
derating values 0ay be obtained by linear interpolation.
Setup (tIS) no0inal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)0ax and the first crossing of VIH(AC)0in that does not ring back be-
low VIH(DC)0in . Setup (tIS) no0inal slew rate for a falling signal is defined as the slew
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
rate between the last crossing of VIH(DC)0in and the first crossing of VIL(AC)0ax that does
not ring back above VIL(DC)0ax
.
Hold (tIH) no0inal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)0ax and the first crossing of VIH(AC)0in that does not ring back be-
low VIH(DC)0in. Hold (tIH) no0inal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIH(DC)0in and the first crossing of VIL(AC)0inthat does not
ring back above VIL(DC)0ax
.
Table 88: Command and Address Setup and Hold Values Referenced – AC/DC-Based
Symbol
1600
115
140
–
1866
100
125
–
2133
80
2400
62
2666
–
2933
–
3200
–
Unit
ps
Reference
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
VIH(DC)/VIL(DC)
tIS(base, AC100)
tIH(base, DC75)
tIS(base, AC90)
tIH(base, DC65)
tIS/tIH(Vref)
105
–
87
–
–
–
ps
–
55
80
145
48
73
138
40
65
130
ps
–
–
–
–
ps
215
200
180
162
ps
Table 89: Derating Values for tIS/tIH – AC100DC75-Based
ΔtIS with AC100 Threshold, ΔtIH with DC75 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
10.0 V/ns
8.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
7.0
6.0
5.0
4.0
3.0
2.0
1.5
1.0
76
73
70
65
57
40
23
–10
54
53
50
46
40
28
15
–10
76
74
71
66
57
41
24
–9
55
53
51
47
41
28
16
–9
77
75
72
67
58
42
25
–8
56
54
52
48
42
29
17
–8
79
77
74
69
60
44
27
–6
58
56
54
50
44
31
19
–6
82
79
76
71
63
46
29
–4
60
58
56
52
46
33
21
–4
86
83
80
75
67
50
33
64
63
60
56
50
38
25
94
92
88
83
75
58
42
8
73
71
68
65
58
46
33
8
111
108
105
100
92
89
88
85
81
75
63
50
25
75
58
25
0
0
0.9
0.8
0.7
0.6
0.5
0.4
–17
–26
–37
–52
–73
–14
–19
–26
–35
–48
–16
–25
–36
–51
–72
–14
–19
–25
–34
–47
–15
–24
–35
–50
–71
–13
–18
–24
–33
–46
–13
–22
–33
–48
–69
–10
–16
–22
–31
–44
–11
–20
–31
–46
–67
–98
–8
1
4
18
9
21
16
9
–7
–4
–9
–14
–20
–29
–42
–60
–16
–27
–42
–63
–94
–7
–1
–16
–25
–38
–56
–18
–33
–54
–85
–8
–2
–17
–29
–48
–17
–38
–69
0
–13
–31
–104 –66 –103 –66 –102 –65 –100 –63
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 90: Derating Values for tIS/tIH – AC90/DC65-Based
ΔtIS with AC90 Threshold, ΔtIH with DC65 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
10.0 V/ns
8.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
7.0
6.0
5.0
4.0
3.0
2.0
1.5
1.0
68
66
63
59
51
36
21
–9
47
45
43
40
34
24
13
–9
69
67
64
59
52
37
22
–8
47
46
44
40
35
24
13
–8
70
68
65
60
53
38
23
–8
48
47
45
41
36
25
14
–8
72
69
66
62
54
39
24
–6
50
49
46
43
38
27
16
–6
73
71
68
64
56
41
26
–4
52
50
48
45
40
29
18
–4
77
75
72
68
60
45
30
56
54
52
49
43
33
22
85
83
80
75
68
53
38
8
63
62
60
56
51
40
29
8
100
98
95
90
83
68
53
23
78
77
75
71
66
55
44
23
0
0
0.9
0.8
0.7
0.6
0.5
0.4
–15
–23
–34
–47
–67
–95
–13
–17
–23
–31
–42
–58
–15
–23
–33
–47
–66
–95
–12
–17
–22
–30
–41
–57
–14
–22
–32
–46
–65
–94
–11
–16
–21
–29
–40
–56
–12
–20
–30
–44
–63
–92
–9
–10
–18
–28
–42
–61
–90
–7
1
4
16
8
19
14
9
–6
–4
–8
–14
–20
–27
–38
–54
–12
–18
–25
–36
–53
–14
–25
–38
–58
–86
–7
–1
–14
–22
–33
–49
–17
–31
–50
–79
–6
–2
–14
–25
–41
–16
–35
–64
1
–10
–26
Data Receiver Input Requirements
The following para0eters apply to the data receiver Rx MASK operation detailed in the
Write Ti0ing section, Data Strobe-to-Data Relationship.
The rising edge slew rates are defined by srr1 and srr2. The slew rate 0easure0ent
points for a rising edge are shown in the figure below. A LOW-to-HIGH transition ti0e,
tr1, is 0easured fro0 6.5 × VdiVW,0ax below VCENTDQ,0idpoint to the last transition
through 6.5 × VdiVW,0ax above VCENTDQ,0idpoint; tr2 is 0easured fro0 the last transition
through 6.5 × VdiVW,0ax above VCENTDQ,0idpoint to the first transition through the 6.5 ×
VIHL(AC)0in above VCENTDQ,0idpoint
.
The falling edge slew rates are defined by srf1 and srf2. The slew rate 0easure0ent
points for a falling edge are shown in the figure below. A HIGH-to-LOW transition ti0e,
tf1, is 0easured fro0 6.5 × VdiVW,0ax above VCENTDQ,0idpoint to the last transition
through 6.5 × VdiVW,0ax below VCENTDQ,0idpoint; tf2 is 0easured fro0 the last transition
through 6.5 × VdiVW,0ax below VCENTDQ,0idpoint to the first transition through the 6.5 ×
VIHL(AC)0in below VCENTDQ,0idpoint
.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 206: DQ Slew Rate Definitions
t
r2
0.5 × V
V
diVW,max
Rx Mask
Rx Mask
CENTDQ,midpoint
0.5 × V
diVW,max
t
r1
t
f1
0.5 × V
V
diVW,max
CENTDQ,midpoint
0.5 × V
diVW,max
t
f2
1. Rising edge slew rate equation srr1 = VdiVW,max/(tr1).
Notes:
2. Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 × tr2).
3. Falling edge slew rate equation srf1 = VdiVW,max/(tf1).
4. Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 × tf2).
Table 91: DQ Input Receiver Specifications
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Not
Max Unit es
Parameter
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
VIN Rx mask input
peak-to-peak
VdiVW
TdiVW
VIHL(AC)
–
136
–
130
–
120
–
115
–
110
0.23
–
mV 2, 3
UI 2, 3
mV 4, 5
DQ Rx input tim-
ing window
–
0.2
–
–
0.2
–
–
0.22
–
–
0.23
–
–
DQ AC input
swing peak-to-
peak
186
160
150
145
140
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 91: DQ Input Receiver Specifications (Continued)
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Not
Max Unit es
Parameter
Symbol Min
TdiPW 0.58
Max
Min
Max
Min
Max
Min
Max
Min
DQ input pulse
width
–
0.58
–
0.58
–
0.58
–
0.58
–
0.22
0.125
9
UI
6
7
8
9
DQS-to-DQ Rx
mask offset
DQ-to-DQ Rx mask tDQ2DQ
offset
tDQS2D –0.17
Q
0.17
0.1
9
–0.17
0.17
0.1
9
–0.19
0.19
0.105
9
–0.22
0.22
0.115
9
–0.22
UI
–
–
–
–
–
UI
Input slew rate
over VdiVW if tCK ≥
0.925ns
srr1, srf1
1
1
1
1
1
V/ns
Input slew rate
over VdiVW if
0.935ns > tCK ≥
0.625ns
srr1, srf1
–
–
1.25
9
1.25
9
1.25
9
1.25
9
V/ns
9
Rising input slew
rate over 1/2
VIHL(AC)
srr2
srf2
0.2 ×
srr1
9
9
0.2 ×
srr1
9
9
0.2 ×
srr1
9
9
0.2 ×
srr1
9
9
0.2 ×
srr1
9
9
V/ns 10
V/ns 10
Falling input slew
rate over 1/2
VIHL(AC)
0.2 ×
srf1
0.2 ×
srf1
0.2 ×
srf1
0.2 ×
srf1
0.2 ×
srf1
1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum in-
put pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew
rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased
to the point where the minimum input pulse width would no longer be violated.
Notes:
2. Data Rx mask voltage and timing total input valid window where VdiVW is centered
around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied
per bit and should include voltage and temperature drift terms. The input buffer design
specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.
3. Defined over the DQ internal VREF range 1.
4. Overshoot and undershoot specifications apply.
5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min
is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a
valid TdiPW).
6. DQ minimum input pulse width defined at the VCENTDQ,midpoint
.
7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word
(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM
balls over process, voltage, and temperature.
8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at
the SDRAM balls for a given component over process, voltage, and temperature.
9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to
fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.
10. Input slew rate between VdiVW mask edge and VIHL(AC)min points.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
The following figure shows the Rx 0ask relationship to the input ti0ing specifications
relative to syste0 tDS and tDH. The classical definition for tDS/tDH required a DQ rising
and falling edges to not violate tDS and tDH relative to the DQS strobe at any ti0e; how-
ever, with the Rx 0ask tDS and tDH can shift relative to the DQS strobe provided the
input pulse width specification is satisfied and the Rx 0ask is not violated.
Figure 207: Rx Mask Relative to tDS/tDH
TdiPW
VIH(DC)
0.5 × VdiVW
VCENTDQ,pin mean
Rx
Mask
0.5 × VdiVW
VIL(DC)
tf1
TdiVW
tr1
tDS = Greater of 0.5 × TdiVW
or
tDH = Greater of 0.5 × TdiVW
or
0.5 × (TdiPW + VdiVW/tf1)
0.5 × (TdiPW + VdiVW/tr1)
DQS_c
DQS_t
The following figure and table show an exa0ple of the worst case Rx 0ask required if
the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The
figure and table show that without DRAM write DQ training, the Rx 0ask would in-
crease fro0 6.2UI to essentially 6.54UI. This would also be the 0ini0u0 tDS and tDH
required as well.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 208: Rx Mask Without Write Training
TdiVW + 2 × tDQS2DQ
Rx Mask
VIH(DC)
0.5 × VdiVW
VCENTDQ,midpoint
0.5 × VdiVW
VIL(DC)
tDS
0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ
DQS_c
tDH
DQS_t
Table 92: Rx Mask and tDS/tDH without Write Training
Rx Mask
with Write
Train
VIHL(AC)
(mV)
TdiPW
(UI)
VdiVW
(mV)
TdiVW
(UI)
tDQS2DQ
(UI)
tDQ2DQ
(UI)
tDS + tDH
(ps)
DDR4
(ps)
1600
1866
2133
2400
2666
2933
3200
186
186
186
160
150
145
140
0.58
0.58
0.58
0.58
0.58
0.58
0.58
136
136
136
130
120
115
110
0.2
0.2
0.17
0.17
0.17
0.17
0.19
0.22
0.22
0.1
0.1
125
107.1
94
338
289
253
225
225
228
209
0.2
0.1
0.2
0.1
83.3
82.5
78.4
71.8
0.22
0.23
0.23
0.105
0.115
0.125
1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint
.
Note:
Connectivity Test (CT) Mode Input Levels
Table 93: TEN Input Levels (CMOS)
Parameter
Symbol
VIH(AC)_TEN
VIH(DC)_TEN
VIL(DC)_TEN
VIL(AC)_TEN
Min
0.8 × VDD
0.7 × VDD
VSS
Max
VDD
VDD
Unit
V
Note
TEN AC input high voltage
TEN DC input high voltage
TEN DC input low voltage
TEN AC input low voltage
1
V
0.3 × VDD
0.2 × VDD
V
VSS
V
2
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 93: TEN Input Levels (CMOS) (Continued)
Parameter
Symbol
tF_TEN
tR_TEN
Min
Max
1 0
Unit
ns
Note
TEN falling time
TEN rising time
–
–
1 0
ns
1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
Notes:
Figure 209: TEN Input Slew Rate Definition
V
IH(AC)_TENmin
V
IH(DC)_TENmin
V
IL(DC)_TENmin
V
IL(AC)_TENmin
t
t
F_TEN
R_TEN
Table 94: CT Type-A Input Levels
Parameter
Symbol
VIH(AC)
Min
VREF + 200
VREF + 150
VSS
Max
Unit
V
Note
2, 3
2, 3
2, 3
2, 3
2
1
CTipA AC input high voltage
CTipA DC input high voltage
CTipA DC input low voltage
CTipA AC input low voltage
CTipA falling time
VDD1
VIH(DC)
VDD
V
VIL(DC)
VREF - 150
V
1
VIL(AC)
VSS1
VREF - 200
V
tF_CTipA
tR_CTipA
–
–
5
5
ns
ns
CTipA rising time
2
1. Refer to Overshoot and Undershoot Specifications.
Notes:
2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
CAS_n/A15, RAS_n/A16, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR.
3. VREFCA = 0.5 × VDD
.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 210: CT Type-A Input Slew Rate Definition
VIH(AC)_CTipAmin
VIH(DC)_CTipAmin
VREFCA
VIL(DC)_CTipAmax
VIL(AC)_CTipAmax
tF_CTipA
tR_CTipA
Table 95: CT Type-B Input Levels
Parameter
Symbol
VIH(AC)
VIH(DC)
Min
VREF + 300
VREF + 200
VSS
Max
Unit
Note
2, 3
2, 3
2, 3
2, 3
2
1
CTipB AC input high voltage
CTipB DC input high voltage
CTipB DC input low voltage
CTipB AC input low voltage
CTipB falling time
VDD1
V
V
VDD
VIL(DC)
VREF - 200
V
1
VIL(AC)
VSS1
VREF - 300
V
tF_CTipB
tR_CTipB
–
–
5
5
ns
ns
CTipB rising time
2
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n.
3. VREFDQ should be 0.5 × VDD
Notes:
Figure 211: CT Type-B Input Slew Rate Definition
V
IH(AC)_CTipBmin
V
IH(DC)_CTipBmin
V
REFDQ
V
IL(DC)_CTipBmax
V
IL(AC)_CTipBmax
tF_CTipB
tR_CTipB
Table 96: CT Type-C Input Levels (CMOS)
Parameter
Symbol
Min
0.8 × VDD
0.7 × VDD
VSS
Max
Unit
Note
1
CTipC AC input high voltage
CTipC DC input high voltage
CTipC DC input low voltage
VIH(AC)_CTipC
VIH(DC)_CTipC
VIL(DC)_CTipC
VDD
V
V
V
2
2
2
VDD
0.3 × VDD
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 96: CT Type-C Input Levels (CMOS) (Continued)
Parameter
Symbol
VIL(AC)_CTipC
tF_CTipC
Min
Max
0.2 × VDD
1 0
Unit
V
Note
1
CTipC AC input low voltage
CTipC falling time
CTipC rising time
VSS
2
2
2
–
–
ns
tR_CTipC
1 0
ns
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-C inputs: Alert_n.
Notes:
Figure 212: CT Type-C Input Slew Rate Definition
V
IH(AC)_TENmin
V
IH(DC)_TENmin
V
IL(DC)_TENmin
V
IL(AC)_TENmin
t
t
F_TEN
R_TEN
Table 97: CT Type-D Input Levels
Parameter
Symbol
VIH(AC)_CTipD
VIH(DC)_CTipD
VIL(DC)_CTipD
VIL(AC)_CTipD
tR_RESET
Min
Max
Unit
V
Note
CTipD AC input high voltage
CTipD DC input high voltage
CTipD DC input low voltage
CTipD AC input low voltage
Rising time
0.8 × VDD
VDD
4
2
1
5
3
0.7 × VDD
VDD
V
VSS
VSS
–
0.3 × VDD
V
0.2 × VDD
V
1
–
–
μs
μs
μs
RESET pulse width - after power-up
RESET pulse width - during power-up
tPW_RESET_S
tPW_RESET_L
1
200
1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RE-
SET during tPW_RESET, otherwise, the DRAM may not be reset.
Notes:
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-
gated as much as possible.
4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
6. CT Type-D inputs: RESET_n; same requirements as in normal mode.
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Figure 213: CT Type-D Input Slew Rate Definition
t
PW_RESET
V
V
IH(AC)_RESETmin
IH(DC)_RESETmin
V
V
IL(DC)_RESETmax
IL(AC)_RESETmax
t
R_RESET
Electrical Characteristics – AC and DC Differential Input Measurement
Levels
Differential Inputs
Figure 214: Differential AC Swing and “Time Exceeding AC-Level” tDVAC
t
DVAC
V
IH,diff(AC)min
V
IH,diff,min
CK_t, CK_c
0.0
V
IL,diff,max
V
IL,diff(AC)max
t
Half cycle
DVAC
1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope.
2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.
Notes:
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Table 98: Differential Input Swing Requirements for CK_t, CK_c
DDR4-1600 / 1866 /
2133 / 2400
DDR4-2666 / 2933 /
3200
Parameter
Symbol
VIHdiff
Min
Max
Min
0.120
Max
Note 3
-0.120
Note 3
Unit
V
Notes
Differential input high
Differential input low
Differential input high (AC)
0.150
Note 3
–0.150
Note 3
1
1
2
VILdiff
Note 3
Note 3
V
VIHdiff(AC) 2 × (VIH(AC)
- VREF
Note 3
2 × (VIH(AC)
V
)
- VREF
)
Differential input low (AC)
Notes:
VILdiff(AC)
2 × (VIL(AC)
-
Note 3
2 × (VIL(AC)
-
V
2
VREF
)
VREF)
1. Used to define a differential signal slew-rate.
2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA
.
3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Table 99: Minimum Time AC Time tDVAC for CK
tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)
|
Slew Rate (V/ns)
200mV
120
115
110
105
100
95
>4.0
4.0
3.0
2.0
1.9
1.6
1.4
1.2
1.0
<1.0
90
85
80
80
1. Below VIL(AC)
.
Note:
Single-Ended Requirements for CK Differential Signals
Each individual co0ponent of a differential signal (CK_t, CK_c) has to co0ply with cer-
tain require0ents for single-ended signals. CK_t and CK_c have to reach approxi0ately
V
SEH0in/VSEL,0ax, which are approxi0ately equal to the AC levels VIH(AC) and VIL(AC) for
ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD 0ight
differ per speed-bin, and so on. For exa0ple, if a value other than 1660V is used for
ADD/CMD VIH(AC) and VIL(AC) signals, then these AC levels also apply for the single-
ended signals CK_t and CK_c.
While ADD/CMD signal require0ents are with respect to VREFCA, the single-ended co0-
ponents of differential signals have a require0ent with respect to VDD/2; this is no0i-
nally the sa0e. The transition of single-ended signals through the AC levels is used to
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
0easure setup ti0e. For single-ended co0ponents of differential signals the require-
0ent to reach VSEL,0ax/VSEH,0in has no bearing on ti0ing, but adds a restriction on the
co00on 0ode characteristics of these signals.
Figure 215: Single-Ended Requirements for CK
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK
VSEL,max
VSEL
VSS or VSSQ
Table 100: Single-Ended Requirements for CK
DDR4-1600 / 1866 /
2133 / 2400
DDR4-2666 / 2933 /
3200
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Single-ended high level for CK_t,
CK_c
VSEH
VDD/2 +
0.100
Note 3
VDD/2 +
0.90
Note 3
V
1, 2
Single-ended low level for CK_t, CK_c
VSEL
Note 3
VDD/2 -
0.100
Note 3
VDD/2 - 0.90
V
1, 2
1. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA
2. ADDR/CMD VIH(AC) and VIL(AC) based on VREFCA
.
Notes:
.
3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Slew Rate Definitions for CK Differential Input Signals
Table 101: CK Differential Input Slew Rate Definition
Measured
Description
From
To
Defined by
Differential input slew rate for rising edge
VIL,diff,max
VIH,diff,min
|VIH,diff,min - VIL,diff,maxΔTRdiff
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Table 101: CK Differential Input Slew Rate Definition (Continued)
Measured
From
VIH,diff,min
Description
To
Defined by
Differential input slew rate for falling edge
VIL,diff,max
|VIH,diff,min - VIL,diff,maxΔTFdiff
1. The differential signal CK_t, CK_c must be monotonic between these thresholds.
Note:
Figure 216: Differential Input Slew Rate Definition for CK_t, CK_c
TRdiff
VIH,diff,min
0
VIL,diff,max
TFdiff
CK Differential Input Cross Point Voltage
To guarantee tight setup and hold ti0es as well as output skew para0eters with respect
to clock and strobe, each cross point voltage of differential input signal CK_t, CK_c 0ust
0eet the require0ents shown below. The differential input cross point voltage VIX(CK) is
0easured fro0 the actual cross point of true and co0ple0ent signals to the 0idlevel
between VDD and VSS
.
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Figure 217: VIX(CK) Definition
VDD
CK_c
VIX(CK)
VDD/2
VIX(CK)
VIX(CK)
CK_t
VSS
VSEH
VSEL
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400
DDR4-1600, 1866, 2133
DDR4-2400
Parameter
Sym
Input Level
Min
N/A
N/A
Max
Min
N/A
N/A
Max
Differential VIX(CK)
input cross
point volt-
VSEH > VDD/2 + 145mV
120mV
120mV
VDD/2 + 100mV ≤ VSEH ≤ VDD/2
(VSEH - VDD/2) -
25mV
(VSEH - VDD/2) -
25mV
+ 145mV
age relative
to VDD/2 for
CK_t, CK_c
V
DD/2 - 145mV ≤ VSEL ≤ VDD/2 - –(VDD/2-VSEL
)
N/A
–(VDD/2-VSEL) +
25mV
N/A
100mV
+25mV
VSEL ≤ VDD/2 - 145mV
–120mV
N/A
–120mV
N/A
Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200
DDR4-2666
DDR4-2933, 3200
Parameter
Sym
Input Level
Min
N/A
N/A
Max
Min
Max
Differential VIX(CK)
input cross
point volt-
VSEH > VDD/2 + 135mV
110mV
N/A
N/A
110mV
VDD/2 + 90mV ≤ VSEH ≤ VDD/2 +
(VSEH - VDD/2) -
30mV
(VSEH - VDD/2) -
30mV
135mV
age relative
to VDD/2 for
CK_t, CK_c
V
DD/2 - 135mV ≤ VSEL ≤ VDD/2 - –(VDD/2-VSEL) +
N/A
–(VDD/2-VSEL) +
30mV
N/A
90mV
30mV
VSEL ≤ VDD/2 - 135mV
–110mV
N/A
–110mV
N/A
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
DQS Differential Input Signal Definition and Swing Requirements
Figure 218: Differential Input Signal Definition for DQS_t, DQS_c
VIH,diff,peak
Half cycle
0.0V
Half cycle
VIL,diff,peak
Table 104: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c
DDR4-1600, 1866,
2133
DDR4-2400
Parameter
Symbol
VIH,diff,peak
VIL,diff,peak
Min
186
Max
VDDQ
–186
Min
Max
VDDQ
–160
Unit
mV
Notes
1 , 2
Peak differential input high voltage
Peak differential input low voltage
160
VSSQ
VSSQ
mV
1 , 2
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
Notes:
2. Minimum value point is used to determine differential signal slew-rate.
Table 105: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Peak differential input high volt-
age
VIH,diff,peak
150
VDDQ
145
VDDQ
140
VDDQ
mV
1 , 2
Peak differential input low volt-
age
VIL,diff,peak
VSSQ
–150
VSSQ
–145
VSSQ
–140
mV
1 , 2
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
Notes:
2. Minimum value point is used to determine differential signal slew-rate.
The peak voltage of the DQS signals are calculated using the following equations:
V
IH,dif,Peak voltage = MAX(ft)
VIL,dif,Peak voltage = MIN(ft)
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
(ft) = DQS_t, DQS_c.
The MAX(f(t)) or MIN(f(t)) used to deter0ine the 0idpoint fro0 which to reference the
±35% window of the exe0pt non-0onotonic signaling shall be the s0allest peak volt-
age observed in all UIs.
Figure 219: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Sig-
naling
DQS_t
+50%
+35%
MIN(f )
t
MAX(f )
t
–35%
–50%
DQS_c
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
DQS Differential Input Cross Point Voltage
To achieve tight RxMask input require0ents as well as output skew para0eters with re-
spect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) 0ust
0eet VIX_DQS,ratio in the table below. The differential input cross point voltage VIX_DQS
(VIX_DQS_FR and VIX_DQS_RF) is 0easured fro0 the actual cross point of DQS_t, DQS_c
relative to the VDQS,0id of the DQS_t and DQS_c signals.
VDQS,0id is the 0idpoint of the 0ini0u0 levels achieved by the transitioning DQS_t
and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the low-
est horizontal tangent above VDQS,0id of the transitioning DQS signals and the highest
horizontal tangent below VDQS,0id of the transitioning DQS signals. A non-0onotonic
transitioning signal’s ledge is exe0pt or not used in deter0ination of a horizontal tan-
gent provided the said ledge occurs within ±35% of the 0idpoint of either VIH.DIFF.Peak
voltage (DQS_t rising) or VIL.DIFF.Peak voltage (DQS_c rising), as shown in the figure be-
low.
A secondary horizontal tangent resulting fro0 a ring-back transition is also exe0pt in
deter0ination of a horizontal tangent. That is, a falling transition’s horizontal tangent is
derived fro0 its negative slope to zero slope transition (point A in the figure below), and
a ring-back’s horizontal tangent is derived fro0 its positive slope to zero slope transi-
tion (point B in the figure below) and is not a valid horizontal tangent; a rising transi-
tion’s horizontal tangent is derived fro0 its positive slope to zero slope transition (point
C in the figure below), and a ring-back’s horizontal tangent derived fro0 its negative
slope to zero slope transition (point D in the figure below) and is not a valid horizontal
tangent.
Figure 220: VIXDQS Definition
Lowest horizontal tanget above V
of the transitioning signals
DQS,mid
C
DQS_t
D
V
V
IX_DQS,RF
IX_DQS,FR
V
DQS,mid
V
V
IX_DQS,FR
IX_DQS,RF
B
DQS_c
A
Highest horizontal tanget below V
of the transitioning signals
DQS,mid
V
SSQ
Table 106: Cross Point Voltage For Differential Input Signals DQS
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
Symbol
Min
Max
Unit
Notes
DQS_t and DQS_c crossing relative to the
midpoint of the DQS_t and DQS_c signal
swings
VIX_DQS,ratio
–
25
%
1, 2
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Table 106: Cross Point Voltage For Differential Input Signals DQS (Continued)
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
Symbol
Min
Max
Unit
Notes
VDQS,mid to Vcent(midpoint) offset
VDQS,mid_to_Vcent
–
Note 3
mV
2
1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is
the difference between the lowest horizontal tangent above VDQS,midd of the transition-
ing DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning
DQS signals.
Notes:
2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) ob-
tained during VREF Training if the DQS and DQs drivers and paths are matched.
3. The maximum limit shall not exceed the smaller of VIH,diff,DQS minimum limit or 50mV.
Slew Rate Definitions for DQS Differential Input Signals
Table 107: DQS Differential Input Slew Rate Definition
Measured
Description
From
To
Defined by
Differential input slew rate for rising edge
Differential input slew rate for falling edge
V IL,diff,DQS
V IH,diff,DQS
V IH,diff,DQS
V IL,diff,DQS
|VIH,diff,DQS - VIL,diff,DQSΔTRdiff
|VIHdiffDQS - VIL,diff,DQSΔTFdiff
1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds.
Note:
Figure 221: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c
VIH,diff,peak
VIH,diff,DQS
0.0V
VIL,diff,DQS
TR
TF
diff
diff
VIL,diff,peak
Table 108: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-1600, 1866, 2133
DDR4-2400
Min Max
Parameter
Symbol
VIH,diff,peak
VIH,diff,DQS
VIL,diff,DQS
Min
186
136
–
Max
VDDQ
–
Unit
mV
mV
mV
Notes
1
Peak differential input high voltage
Differential input high voltage
Differential input low voltage
160
130
–
VDDQ
–
2, 3
2, 3
–136
–130
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Electrical Characteristics – AC and DC Differential Input Meas-
urement Levels
Table 108: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c (Continued)
DDR4-1600, 1866, 2133
DDR4-2400
Parameter
Symbol
VIL,diff,peak
SRIdiff
Min
VSSQ
3.0
Max
–186
18
Min
Max
–160
18
Unit
mV
Notes
1
Peak differential input low voltage
DQS differential input slew rate
VSSQ
3.0
V/ns
4, 5
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
Notes:
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
V
IL,diff,min - VIH,diff,maxΔTRdiff
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
IL,diff,min - VIH,diff,maxΔTFdiff
.
V
.
Table 109: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
Peak differential input
high voltage
VIH,diff,peak
150
120
–
VDDQ
145
115
–
VDDQ
140
110
–
VDDQ
mV
mV
mV
mV
V/ns
1
Differential input high
voltage
VIH,diff,DQS
VIL,diff,DQS
VIL,diff,peak
SRIdiff
–
–
–
2, 3
2, 3
1
Differential input low
voltage
–120
–150
18
–115
–145
18
–110
–140
18
Peak differential input
low voltage
VSSQ
3.0
VSSQ
3.0
VSSQ
3.0
DQS differential input
slew rate
4, 5
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
Notes:
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
V
IL,diff,min - VIH,diff,maxΔTRdiff
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
IL,diff,min - VIH,diff,maxΔTFdiff
.
V
.
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Electrical Characteristics – Overshoot and Undershoot Specifi-
cations
Electrical Characteristics – Overshoot and Undershoot Specifications
Address, Command, and Control Overshoot and Undershoot Specifications
Table 110: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications
DDR4- DDR4-
1600 1866
DDR4-
2133
DDR4- DDR4- DDR4- DDR4-
2400 2666 2933 3200
Description
Unit
Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0)
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
V
V
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
Area C: Maximum peak amplitude allowed for
undershoot below VSS
Area A maximum overshoot area per 1tCK
Area B maximum overshoot area per 1tCK
Area C maximum undershoot area per 1tCK
0.0083 0.0071
0.2550 0.2185
0.2644 0.2265
0.0062
0.1914
0.1984
0.0055 0.0055 0.0055 0.0055 V/ns
0.1699 0.1699 0.1699 0.1699 V/ns
0.1762 0.1762 0.1762 0.1762 V/ns
Figure 222: ADDR, CMD, CNTL Overshoot and Undershoot Definition
Absolute MAX overshoot
Overshoot area above V absolute MAX
DD
A
V
absolute MAX
DD
Overshoot area below V absolute MAX
DD
B
and above V MAX
DD
V
DD
t
1 CK
V
SS
Undershoot area below V
SS
C
Clock Overshoot and Undershoot Specifications
Table 111: CK Overshoot and Undershoot/ Specifications
DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-
Description
1600
1866
2133
2400
2666
2933 3200
Unit
CLK_t, CLK_n
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
0.06
0.24
0.30
V
V
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
Area C: Maximum peak amplitude allowed for
undershoot below VSS
Area A maximum overshoot area per 1UI
Area B maximum overshoot area per 1UI
0.0038 0.0032 0.0028 0.0025 0.0025 0.0025 0.0025 V/ns
0.1125 0.0964 0.0844 0.0750 0.0750 0.0750 0.0750 V/ns
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Electrical Characteristics – Overshoot and Undershoot Specifi-
cations
Table 111: CK Overshoot and Undershoot/ Specifications (Continued)
DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-
1600 1866 2133 2400 2666 2933 3200
0.1144 0.0980 0.0858 0.0762 0.0762 0.0762 0.0762 V/ns
Description
Unit
Area C maximum undershoot area per 1UI
Figure 223: CK Overshoot and Undershoot Definition
Absolute MAX overshoot
VDD absolute MAX
Overshoot area above VDD absolute MAX
A
B
Overshoot area below VDD absolute MAX
and above VDD MAX
VDD
VSS
1UI
Undershoot area below VSS
C
Data, Strobe, and Mask Overshoot and Undershoot Specifications
Table 112: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications
DDR4- DDR4- DDR4- DDR4- DDR4- DDR4- DDR4-
1600 1866 2133 2400 2666 2933 3200
DQS_t, DQS_n, DQSL_t, DQSL_n, DQSU_t, DQSU_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI,
Description
Unit
Area A: Maximum peak amplitude above VDDQ
absolute MAX
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
0.16
0.24
0.30
0.10
V
V
V
V
Area B: Amplitude allowed between VDDQ and
VDDQ absolute MAX
Area C: Maximum peak amplitude allowed for
undershoot below VSSQ
Area D: Maximum peak amplitude below VSSQ
absolute MIN
Area A maximum overshoot area per 1UI
Area B maximum overshoot area per 1UI
Area C maximum undershoot area per 1UI
Area D maximum undershoot area per 1UI
0.0150 0.0129 0.0113 0.0100 0.0129 0.0113 0.0100 V/ns
0.1050 0.0900 0.0788 0.0700 0.0900 0.0788 0.0700 V/ns
0.1050 0.0900 0.0788 0.0700 0.0900 0.0788 0.0700 V/ns
0.0150 0.0129 0.0113 0.0100 0.0129 0.0113 0.0100 V/ns
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 224: Data, Strobe, and Mask Overshoot and Undershoot Definition
Absolute MAX overshoot
VDDQ absolute MAX
Overshoot area above VDDQ absolute MAX
A
B
Overshoot area below VDDQ absolute MAX
and above VDDQ MAX
VDDQ
VSSQ
1UI
Undershoot area below VSSQ MIN and
above VSSQ absolute MIN
C
VSSQ absolute MIN
D
Undershoot area below VSSQ absolute MIN
Absolute MAX undershoot
Electrical Characteristics – AC and DC Output Measurement Levels
Single-Ended Outputs
Table 113: Single-Ended Output Levels
Parameter
Symbol
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
DDR4-1600 to DDR4-3200
1.1 × VDDQ
Unit
V
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output slew rate)
AC output low measurement level (for output slew rate)
0.8 × VDDQ
V
0.5 × VDDQ
V
(0.7 + 0.15) × VDDQ
(0.7 - 0.15) × VDDQ
V
V
1. The swing of 0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
Note:
of 50Ω to VTT = VDDQ
.
Using the sa0e reference load used for ti0ing 0easure0ents, output slew rate for fall-
ing and rising edges is defined and 0easured between VOL(AC) and VOH(AC) for single-
ended signals.
Table 114: Single-Ended Output Slew Rate Definition
Measured
Description
From
VOL(AC)
VOH(AC)
To
Defined by
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)ΔTRse
[VOH(AC) - VOL(AC)ΔTFse
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 225: Single-ended Output Slew Rate Definition
TR
se
V
OH(AC)
V
OL(AC)
TF
se
Table 115: Single-Ended Output Slew Rate
For RON = RZQ/7
DDR4-1600/ 1866 / 2133 /
2400
DDR4-2666
Min Max
DDR4-2933 / 3200
Parameter
Symbol
Min
Max
Min
Max
Unit
Single-ended output
slew rate
SRQse
4
9
4
9
4
9
V/ns
1. SR = slew rate; Q = query output; se = single-ended signals
Notes:
2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte
lane:
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer-
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-
nals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer-
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-
nals in the same byte lane are switching into the opposite direction (from LOW-to-
HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the
opposite direction, the standard maximum limit of 9 V/ns applies.
Differential Outputs
Table 116: Differential Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
AC differential output high measurement level (for output slew
rate)
VOH,diff(AC)
0.3 × VDDQ
V
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 116: Differential Output Levels (Continued)
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
AC differential output low measurement level (for output slew
rate)
VOL,diff(AC)
–0.3 × VDDQ
V
1. The swing of 0.3 × VDDQ is based on approximately 50% of the static single-ended out-
put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50Ω to VTT = VDDQ at each differential output.
Note:
Using the sa0e reference load used for ti0ing 0easure0ents, output slew rate for fall-
ing and rising edges is defined and 0easured between VOL,diff(AC) and VOH,diff(AC) for dif-
ferential signals.
Table 117: Differential Output Slew Rate Definition
Measured
Description
From
VOL,diff(AC)
VOH,diff(AC)
To
Defined by
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTRdiff
[VOH,diff(AC) - VOL,diff(AC)ΔTFdiff
Figure 226: Differential Output Slew Rate Definition
TR
diff
V
OH,diff(AC)
V
OL,diff(AC)
TF
diff
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 118: Differential Output Slew Rate
For RON = RZQ/7
DDR4-1600 / 1866 /
2133 / 2400
DDR4-2666
Min Max
18
DDR4-2933 / 3200
Parameter
Symbol
Min
Max
Min
Max
Unit
Differential output slew
rate
SRQdiff
8
18
8
8
18
V/ns
1. SR = slew rate; Q = query output; diff = differential signals.
Note:
Reference Load for AC Timing and Output Slew Rate
The effective reference load of 56ȍ to VTT = VDDQ and driver i0pedance of RZQ/7 for
each output was used in defining the relevant AC ti0ing para0eters of the device as
well as output slew rate 0easure0ents.
Ron no0inal of DQ, DQS_t and DQS_c drivers uses 34 oh0s to specify the relevant AC
ti0ing paraeter values of the device. The 0axi0u0 DC High level of Output signal = 1.6
* VDDQ, the 0ini0u0 DC Low level of Output signal = { 34 /( 34 + 56 ) } *VDDQ = 6.4*
VDDQ
The no0inal reference level of an Output signal can be approxi0ated by the following:
The center of 0axi0u0 DC High and 0ini0u0 DC Low = { ( 1 + 6.4 ) / 2 } * VDDQ = 6.7
* VDDQ. The actual reference level of Output signal 0ight vary with driver Ron and ref-
erence load tolerances. Thus, the actual reference level or 0idpoint of an output signal
is at the widest part of the output signal’s eye.
Figure 227: Reference Load For AC Timing and Output Slew Rate
VDDQ
VTT = VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
VSSQ
RTT = 50ȍ
Timing reference point
Connectivity Test Mode Output Levels
Table 119: Connectivity Test Mode Output Levels
Parameter
Symbol
VOH(DC)
VOM(DC)
VOL(DC)
DDR4-1600 to DDR4-3200
1.1 × VDDQ
Unit
V
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
0.8 × VDDQ
V
0.5 × VDDQ
V
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 119: Connectivity Test Mode Output Levels (Continued)
Parameter
Symbol
VOB(DC)
VOH(AC)
VOL(AC)
DDR4-1600 to DDR4-3200
Unit
V
DC output below measurement level (for IV curve linearity)
AC output high measurement level (for output slew rate)
AC output low measurement level (for output slew rate)
0.2 × VDDQ
VTT + (0.1 × VDDQ
)
V
VTT - (0.1 × VDDQ
)
V
1. Driver impedance of RZQ/7 and an effective test load of 50Ω to VTT = VDDQ
.
Note:
Figure 228: Connectivity Test Mode Reference Test Load
VDDQ
DQ, DQS_t, DQS_c,
DQSL_t, DQSL_c, DQSU_t, DQSU_c,
DM, DML, DMH, TDQS_t, TDQS_c
0.5 × VDDQ
CT_Inputs
DUT
VSSQ
RTT = 50ȍ
Timing reference point
Figure 229: Connectivity Test Mode Output Slew Rate Definition
V
OH(AC)
V
TT
0.5 x VDD
V
OL(AC)
TF
TR
output_CT
output_CT
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Electrical Characteristics – AC and DC Output Driver Charac-
teristics
Table 120: Connectivity Test Mode Output Slew Rate
DDR4-1600 / 1866 /
2133 / 2400
DDR4-2933 /
3200
DDR4-2666
Parameter
Symbol
Min
Max
10
Min
Max
Min
Max
10
Unit
ns/V
ns/V
Output signal falling time
Output signal rising time
TF_output_CT
TR_output_CT
–
–
–
–
10
10
–
–
10
10
Electrical Characteristics – AC and DC Output Driver Characteristics
Output Driver Electrical Characteristics
The DDR4 driver supports two RON values. These RON values are referred to as strong
0ode (low RON: 34ȍ) and weak 0ode (high RON: 48ȍ). A functional representation of
the output buffer is shown in the figure below.
Figure 230: Output Driver: Definition of Voltages and Currents
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
like
RCV,
...
RONPU
DQ
VOUT
VSSQ
IOUT
RONPD
IPD
The output driver i0pedance, RON, is deter0ined by the value of the external reference
resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a no0i-
nal 34.3ȍ ±16% or 48ȍ ±16% with no0inal RZQ = 246ȍ.
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as fol-
lows:
RONPu when RONPd is off:
V
- V
OUT
DDQ
R
=
ONPU
I
OUT
RONPD when RONPU is off:
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Electrical Characteristics – AC and DC Output Driver Charac-
teristics
VOUT
RONPD
=
IOUT
Table 121: Strong Mode (34Ω) Output Driver Electrical Characteristics
Assumes RZQ Ω; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
0.8
0.9
0.9
0.9
0.9
0.8
–10
Nom
1.0
1.0
1.0
1.0
1.0
1.0
–
Max
1.1
Unit
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
%
Notes
1, 2, 3
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOM(DC) = 0.8 × VDDQ
RON34PD
1.1
1, 2, 3
1.25
1.25
1.1
1, 2, 3
Ω
1, 2, 3
RON34PU
1, 2, 3
1.1
1, 2, 3
Mismatch between DQ to DQ
within byte variation pull-up,
MMPUdd
10
1, 2, 3, 4, 5
Mismatch between DQ to DQ
within byte variation pull-down,
MMPDdd
VOM(DC) = 0.8 × VDDQ
–
–
–
–
10
10
%
%
1, 2, 3, 4,
6, 7
Mismatch between pull-up and
pull-down, MMPUPD
VOM(DC) = 0.8 × VDDQ
1, 2, 3, 4,
6, 7
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity.
Notes:
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ
VSS.
=
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ
.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD
:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val-
ue:
R
- R
ONPD
ONPU
R
MM
=
× 100
PUPD
ON,nom
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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Electrical Characteristics – AC and DC Output Driver Charac-
teristics
R
R
- R
ONPU,min
ONPU,max
MM
=
=
× 100
× 100
PUDD
R
ON,nom
- R
ONPD,max
ONPD,min
MM
PDDD
R
ON,nom
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op-
erates between –40°C and 0°C (TC).
Table 122: Weak Mode (48Ω) Output Driver Electrical Characteristics
Assumes RZQ Ω; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
0.8
0.9
0.9
0.9
0.9
0.8
-10
Nom
1.0
1.0
1.0
1.0
1.0
1.0
–
Max
1.1
Unit
RZQ/5
RZQ/5
RZQ/5
RZQ/5
RZQ/5
RZQ/5
%
Notes
1, 2, 3
Ω
RON34PD
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOM(DC) = 0.8 × VDDQ
1.1
1, 2, 3
1.25
1.25
1.1
1, 2, 3
RON34PU
1, 2, 3
1, 2, 3
1.1
1, 2, 3
Mismatch between DQ to DQ
within byte variation pull-up,
MMPUdd
10
1, 2, 3, 4, 5
Mismatch between DQ to DQ
within byte variation pull-down,
MMPDdd
VOM(DC) = 0.8 × VDDQ
–
–
–
–
10
10
%
%
1, 2, 3, 4,
6, 7
Mismatch between pull-up and
pull-down, MMPUPD
VOM(DC) = 0.8 × VDDQ
1, 2, 3, 4,
6, 7
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity.
Notes:
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ
VSS.
=
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ
.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD
:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val-
ue:
RONPU - RONPD
MMPUPD
=
× 100
RON,nom
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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Electrical Characteristics – AC and DC Output Driver Charac-
teristics
R
R
- R
ONPU,min
ONPU,max
MM
=
=
× 100
× 100
PUDD
R
ON,nom
- R
ONPD,max
ONPD,min
MM
PDDD
R
ON,nom
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op-
erates between –40°C and 0°C (TC).
Output Driver Temperature and Voltage Sensitivity
If te0perature and/or voltage change after calibration, the tolerance li0its widen ac-
cording to the equations and tables below.
ǻT = T - T(@calibration); ǻV = VDDQ - VDDQ(@ calibration); VDD = VDDQ
Table 123: Output Driver Sensitivity Definitions
Symbol
Min
Max
Unit
RZQ/6
RZQ/6
RZQ/6
RONPU@ VOH(DC)
RON@ VOM(DC)
RONPD@ VOL(DC)
0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.1 _ dRONdTH × |ΔT| + dRONdVH × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
Table 124: Output Driver Voltage and Temperature Sensitivity
Voltage and Temperature Range
Symbol
dRONdTM
dRONdVM
dRONdTL
dRONdVL
dRONdTH
dRONdVM
Min
Max
1.5
Unit
%/°C
0
0
0
0
0
0
0.15
1.5
%/mV
%/°C
0.15
1.5
%/mV
%/°C
0.15
%/mV
Alert Driver
A functional representation of the alert output buffer is shown in the figure below. Out-
put driver i0pedance, RON, is defined as follows.
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Electrical Characteristics – AC and DC Output Driver Charac-
teristics
Figure 231: Alert Driver
Alert driver
'5$0
Alert
I
OUT
R
V
OUT
ONPD
I
PD
V
SSQ
RONPD when RONPU is off:
VOUT
RONPD
=
IOUT
Table 125: Alert Driver Voltage
RON,nom
Register
VOUT
Min
Nom
N/A
Max
1.2
Unit
RZQ/7
RZQ/7
RZQ/7
N/A
RONPD
VOL(DC) = 0.1 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
0.3
0.4
0.4
N/A
1.12
1.4
N/A
1. VDDQ voltage is at VDDQ(DC)
.
Note:
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Electrical Characteristics – On-Die Termination Characteristics
Electrical Characteristics – On-Die Termination Characteristics
ODT Levels and I-V Characteristics
On-die ter0ination (ODT) effective resistance settings are defined and can be selected
by any or all of the following options:
• MR1[16:8] (RTT(NOM)): Disable, 246 oh0s, 126 oh0s, 86 oh0s, ±6 oh0s, 48 oh0s, 46
oh0s, and 34 oh0s.
• MR2[11:9] (RTT(WR)): Disable, 246 oh0s,126 oh0s, and 86 oh0s.
• MR5[8:±] (RTT(Park)): Disable, 246 oh0s, 126 oh0s, 86 oh0s, ±6 oh0s, 48 oh0s, 46
oh0s, and 34 oh0s.
ODT is applied to the following inputs:
• x4: DQ, DM_n, DQS_t, and DQS_c inputs.
• x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs.
• x1±: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs.
A functional representation of ODT is shown in the figure below.
Figure 232: ODT Definition of Voltages and Currents
Chip in termination mode
ODT
VDDQ
RTT
To other
circuitry
like RCV,
DQ
...
IOUT
VOUT
VSSQ
Table 126: ODT DC Characteristics
RTT
VOUT
Min
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
Nom
Max
1.25
1.1
Unit
RZQ
Notes
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
240 ohm
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
1
1
1
1
1
1
1
1
1
RZQ
1.1
RZQ
120 ohm
80 ohm
1.25
1.1
RZQ/2
RZQ/2
RZQ/2
RZQ/3
RZQ/3
RZQ/3
1.1
1.25
1.1
1.1
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Electrical Characteristics – On-Die Termination Characteristics
Table 126: ODT DC Characteristics (Continued)
RTT
VOUT
Min
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0.9
0.9
0.8
0
Nom
Max
1.25
1.1
Unit
RZQ/4
RZQ/4
RZQ/4
RZQ/5
RZQ/5
RZQ/5
RZQ/6
RZQ/6
RZQ/6
RZQ/7
RZQ/7
RZQ/7
%
Notes
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4, 5, 6
60 ohm
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOL(DC) = 0.5 × VDDQ
VOM(DC) = 0.8 × VDDQ
VOH(DC) = 1.1 × VDDQ
VOM(DC) = 0.8 × VDDQ
1
1
1
1
1
1
1
1
1
1
1
1
–
1.1
48 ohm
40 ohm
34 ohm
1.25
1.1
1.1
1.25
1.1
1.1
1.25
1.1
1.1
DQ-to-DQ mismatch
within byte
10
1. The tolerance limits are specified after calibration to 240 ohm 1% resistor with stable
voltage and temperature. For the behavior of the tolerance limits if temperature or
voltage changes after calibration, see ODT Temperature and Voltage Sensitivity.
Notes:
2. Micron recommends calibrating pull-up ODT resistors at 0.8 × VDDQ. Other calibration
schemes may be used to achieve the linearity specification shown here.
3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS.
4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t
and DQS_c.
5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t
and DQS_c.
R
- R
TT(MIN)
TT(MAX)
× 100
DQ-to-DQ mismatch =
R
TT(NOM)
6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes.
7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op-
erates between –40°C and 0°C (TC).
ODT Temperature and Voltage Sensitivity
If te0perature and/or voltage change after calibration, the tolerance li0its widen ac-
cording to the following equations and tables.
ǻT = T - T(@ calibration); ǻV = VDDQ - VDDQ(@ calibration); VDD = VDDQ
Table 127: ODT Sensitivity Definitions
Parameter
Min
Max
Unit
RTT@
0.9 - dRTTdT × |ΔT| - dRTTdV × |ΔV|
1.6 + dRTTdTH × |ΔT| + dRTTdVH × |ΔV|
RZQ/n
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Electrical Characteristics – On-Die Termination Characteristics
Table 128: ODT Voltage and Temperature Sensitivity
Parameter
dRTTdT
Min
Max
1.5
Unit
%/°C
0
0
dRTTdV
0.15
%/mV
ODT Timing Definitions
The reference load for ODT ti0ings is different than the reference load used for ti0ing
0easure0ents.
Figure 233: ODT Timing Reference Load
VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
VSSQ
RTT = 50ȍ
VTT
=
VSSQ
Timing reference point
ODT Timing Definitions and Waveforms
Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 129 (page 29±) and
shown in Figure 234 (page 297) and Figure 23± (page 298). Measure0ent reference set-
tings are provided in the subsequent Table 136 (page 297).
The tADC for the dyna0ic ODT case and read disable ODT cases are represented by
tADC of Direct ODT Control case.
Table 129: ODT Timing Definitions
Parameter
Begin Point Definition
End Point Definition
Figure
tADC
Rising edge of CK_t, CK_c defined by the end point of
DODTLoff
Extrapolated point at VRTT,nom
Figure 234
(page 297)
Rising edge of CK_t, CK_c defined by the end point of
DODTLon
Extrapolated point at VSSQ
Extrapolated point at VRTT,nom
Extrapolated point at VSSQ
Extrapolated point at VSSQ
Extrapolated point at VRTT,nom
Figure 234
(page 297)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcnw
Figure 235
(page 298)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcwn4 or ODTLcwn8
Figure 235
(page 298)
tAONAS
tAOFAS
Rising edge of CK_t, CK_c with ODT being first registered
HIGH
Figure 236
(page 298)
Rising edge of CK_t, CK_c with ODT being first registered
LOW
Figure 236
(page 298)
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Electrical Characteristics – On-Die Termination Characteristics
Table 130: Reference Settings for ODT Timing Measurements
Measure
Parameter
tADC
RTT(Park)
Disable
–
RTT(NOM)
RZQΩ
RZQΩ
RZQΩ
RZQΩ
RTT(WR)
VSW1
0.20V
0.20V
0.20V
0.20V
VSW2
0.40V
0.40V
0.40V
0.40V
Note
1, 2, 4
1, 3, 5
1, 2, 6
1, 2, 6
–
High-Z
tAONAS
tAOFAS
Disable
Disable
–
–
1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has
A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for
Notes:
R
TT(WR) setting.
2. ODT state change is controlled by ODT pin.
3. ODT state change is controlled by a WRITE command.
4. Refer to Figure 234 (page 297).
5. Refer to Figure 235 (page 298).
6. Refer to Figure 236 (page 298).
Figure 234: tADC Definition with Direct ODT Control
DODTLoff
DODTLon
Begin point: Rising edge
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
DODTLon
of CK_t, CK_c defined
by the end point of
DODTLoff
CK_c
CK_t
t
t
ADC
ADC
End point: Extrapolated
VRTT,nom
VRTT,nom
point at V
RTT,nom
Vsw2
Vsw1
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
End point: Extrapolated
VSSQ
VSSQ
point at V
SSQ
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Electrical Characteristics – On-Die Termination Characteristics
Figure 235: tADC Definition with Dynamic ODT Control
ODTLcnw
ODTLcnw4/8
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw4 or ODTLcnw8
CK_c
CK_t
t
t
ADC
ADC
End point: Extrapolated
point at V
VRTT,nom
VRTT,nom
RTT,nom
Vsw2
Vsw1
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
End point: Extrapolated
VSSQ
VSSQ
point at V
SSQ
Figure 236: tAOFAS and tAONAS Definitions
Rising edge of CK_t, CK_c
with ODT being first
registered LOW
Rising edge of CK_t, CK_c
with ODT being first
registered HIGH
CK_c
CK_t
tAOFAS
tAONAS
End point: Extrapolated
point at VRTT_NOM
V
V
RTT,nom
RTT,nom
Vsw2
Vsw1
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
End point: Extrapolated
point at VSSQ
V
V
SSQ
SSQ
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DRAM Package Electrical Specifications
DRAM Package Electrical Specifications
Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices
1600/1866/2133/
2400/2666
2933
3200
Parameter
Symbol
ZIO
Min
Max
85
Min
48
14
–
Max
85
Min
48
14
–
Max
85
Unit Notes
Input/
output
Zpkg
45
14
–
ohm 1, 2, 4
Package delay
Lpkg
TdIO
42
40
40
ps
nH
pF
1, 3, 4
LIO
3.3
0.78
85
3.3
0.78
85
3.3
0.78
85
Cpkg
CIO
–
–
–
DQS_t,
DQS_c
Zpkg
ZIO DQS
TdIO DQS
DZIO DQS
DTdIO DQS
LIO DQS
CIO DQS
ZI CTRL
45
14
–
48
14
–
48
14
–
ohm
ps
1, 2
1, 3
Package delay
Delta Zpkg
Delta delay
Lpkg
42
40
40
10
10
10
ohm 1, 2, 6
–
5
–
5
–
5
ps
nH
pF
1, 3, 6
–
3.3
0.78
90
–
3.3
0.78
90
–
3.3
0.78
90
Cpkg
–
–
–
Input CTRL Zpkg
pins
50
14
–
50
14
–
50
14
–
ohm 1, 2, 8
Package delay
TdI CTRL
LI CTRL
42
40
40
ps
nH
pF
1, 3, 8
Lpkg
Cpkg
3.4
0.7
90
3.4
0.7
90
3.4
0.7
90
CI CTRL
–
–
–
Input CMD Zpkg
ADD pins
ZI ADD CMD
TdI ADD CMD
LI ADD CMD
CI ADD CMD
ZCK
50
14
–
50
14
–
50
14
–
ohm 1, 2, 7
Package delay
45
40
40
ps
nH
pF
1, 3, 7
Lpkg
Cpkg
3.6
0.74
90
3.6
0.74
90
3.6
0.74
90
–
–
–
CK_t, CK_c Zpkg
50
14
–
50
14
–
50
14
–
ohm
ps
1, 2
1, 3
Package delay
TdCK
42
42
42
Delta Zpkg
Delta delay
Lpkg
DZDCK
10
10
10
ohm 1, 2, 5
DTdDCK
LI CLK
–
5
–
5
–
5
ps
nH
pF
1, 3, 5
–
3.4
0.7
100
55
–
3.4
0.7
100
55
–
3.4
0.7
100
55
Cpkg
CI CLK
–
–
–
ZQ Zpkg
ZO ZQ
–
–
–
ohm
ps
1, 2
1, 3
1, 2
1, 3
ZQ delay
TdO ZQ
ZO ALERT
TdO ALERT
20
40
20
20
40
20
20
40
20
ALERT Zpkg
ALERT delay
100
55
100
55
100
55
ohm
ps
1. The package parasitic (L and C) are validated using package only samples. The capaci-
tance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins float-
ing. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other sig-
nal pins shorted at the die, not pin, side.
Notes:
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
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DRAM Package Electrical Specifications
4. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi-
mum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
Table 132: DRAM Package Electrical Specifications for x16 Devices
1600/1866/2133/
2400/2666
2933
3200
Parameter
Symbol
ZIO
Min
45
14
–
Max
85
Min
45
14
–
Max
85
Min
45
14
–
Max
85
Unit Notes
Input/
output
Zpkg
ohm 1, 2, 4
Package delay
Lpkg
TdIO
45
45
45
ps
nH
pF
1, 3, 4
LIO
3.4
0.82
85
3.4
0.82
85
3.4
0.82
85
Cpkg
CIO
–
–
–
DQSL_t/
DQSL_c/
DQSU_t/
DQSU_c
Zpkg
ZIO DQS
TdIO DQS
LIO DQS
CIO DQS
DZIO DQS
DTdIO DQS
45
14
–
45
14
–
45
14
–
ohm
ps
1, 2
1, 3
Package delay
Lpkg
45
45
45
3.4
0.82
10
3.4
0.82
10
3.4
0.82
10
nH
pF
Cpkg
–
–
–
DQSL_t/
DQSL_c,
DQSU_t/
DQSU_c,
Delta Zpkg
Delta delay
–
–
–
ohm 1, 2, 6
ps 1, 3, 6
–
5
–
5
–
5
Input CTRL Zpkg
pins
ZI CTRL
TdI CTRL
LI CTRL
50
14
–
90
42
50
14
–
90
42
50
14
–
90
42
ohm 1, 2, 8
Package delay
ps
nH
pF
1, 3, 8
Lpkg
Cpkg
3.4
0.7
90
3.4
0.7
90
3.4
0.7
90
CI CTRL
–
–
–
Input CMD Zpkg
ADD pins
ZI ADD CMD
TdI ADD CMD
LI ADD CMD
CI ADD CMD
ZCK
50
14
–
50
14
–
50
14
–
ohm 1, 2, 7
Package delay
52
52
52
ps
nH
pF
1, 3, 7
Lpkg
Cpkg
3.9
0.86
90
3.9
0.86
90
3.9
0.86
90
–
–
–
CK_t, CK_c Zpkg
50
14
–
50
14
–
50
14
–
ohm
ps
1, 2
1, 3
Package delay
TdCK
42
42
42
Delta Zpkg
Delta delay
Lpkg
DZDCK
10
10
10
ohm 1, 2, 5
DTdDCK
LI CLK
–
5
–
5
–
5
ps
nH
1, 3, 5
Input CLK
ZQ Zpkg
–
3.4
0.7
100
–
3.4
0.7
100
–
3.4
0.7
100
Cpkg
CI CLK
–
–
–
pF
ZO ZQ
–
–
–
ohm
1, 2
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DRAM Package Electrical Specifications
Table 132: DRAM Package Electrical Specifications for x16 Devices (Continued)
1600/1866/2133/
2400/2666
2933
3200
Parameter
ZQ delay
Symbol
TdO ZQ
Min
20
Max
90
Min
20
Max
90
Min
20
Max
90
Unit Notes
ps
ohm
ps
1, 3
1, 2
1, 3
ALERT Zpkg
ALERT delay
ZO ALERT
TdO ALERT
40
100
55
40
100
55
40
100
55
20
20
20
1. The package parasitic (L and C) are validated using package only samples. The capaci-
tance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins float-
ing. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other sig-
nal pins shorted at the die, not pin, side.
Notes:
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi-
mum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
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DRAM Package Electrical Specifications
Table 133: Pad Input/Output Capacitance
DDR4-1600,
1866, 2133
DDR4-2400,
2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max Unit Notes
Input/output capacitance:
DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
CIO
0.55
1.4
0.55
1.15
0.55
1.00
0.55
1.00
pF
1, 2, 3
Input capacitance: CK_t and
CK_c
CCK
CDCK
CDDQS
CI
0.2
0
0.8
0.05
0.05
0.8
0.2
0
0.7
0.05
0.05
0.7
0.2
0
0.7
0.05
0.05
0.6
0.2
0
0.7
0.05
0.05
0.55
0.1
pF 1, 2, 3,
4
Input capacitance delta: CK_t
and CK_c
pF 1, 2, 3,
5
Input/output capacitance del-
ta: DQS_t and DQS_c
0
0
0
0
pF
1, 2, 3
Input capacitance: CTRL,
ADD, CMD input-only pins
0.2
–0.1
0.2
–0.1
–0.1
–0.1
0.2
–0.1
–0.1
–0.1
0.2
–0.1
–0.1
–0.1
pF 1, 2, 3,
6
Input capacitance delta: All
CTRL input-only pins
CDI_CTRL
0.1
0.1
0.1
pF 1, 2, 3,
7
Input capacitance delta: All
ADD/CMD input-only pins
CDI_ADD_CM –0.1
0.1
0.1
0.1
0.1
pF 1, 2, 3,
8, 9
D
Input/output capacitance del-
ta: DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
CDIO
–0.1
0.1
0.1
0.1
0.1
pF 1, 2, 10,
11
Input/output capacitance:
ALERT pin
CALERT
CZQ
0.5
–
1.5
2.3
2.3
0.5
–
1.5
2.3
2.3
0.5
–
1.5
2.3
2.3
0.5
–
1.5
2.3
2.3
pF 1, 2, 2,
3
Input/output capacitance: ZQ
pin
pF 1, 2, 3,
12
Input/output capacitance:
TEN pin
CTEN
0.2
0.2
0.2
0.2
pF 1, 2, 3,
13
1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading
matches DQ and DQS.
Notes:
2. This parameter is not subject to a production test; it is verified by design and characteri-
zation. The capacitance is measured according to the JEP147 specification, “Procedure
for Measuring Input Capacitance Using a Vector Network Analyzer (VNA),” with VDD
,
VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET_n and ODT, as necessary). VDD = VDDQ = 1.5V, VBIAS = VDD/2 and on-die termination
off. Measured data is rounded using industry standard half-rounded up methodology to
the nearest hundredth of the MSB.
3. This parameter applies to monolithic die, obtained by de-embedding the package L and
C parasitics.
4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)).
5. Absolute value of CIO (DQS_t), CIO (DQS_c)
6. Absolute value of CCK_t, CCK_c
7. CI applies to ODT, CS_n, CKE, A[15:0], BA[1:0], RAS_n, CAS_n, and WE_n.
8. CDI_CTRL applies to ODT, CS_n, and CKE.
9. CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
10. CDI_ADD_CMD applies to A[15:0], BA1:0], RAS_n, CAS_n and WE_n.
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Thermal Characteristics
11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
12. Maximum external load capacitance on ZQ pin: 5pF.
13. Only applicable if TEN pin does not have an internal pull-up.
Thermal Characteristics
Table 134: Thermal Characteristics
Parameter/Condition
Value
0 to +85
0 to +95
–40 to +95
Units
°C
Symbol
Notes
1, 2, 3
Operating case temperature:
Commercial
TC
TC
TC
°C
1, 2, 3, 4
1, 2, 3, 4
Operating case temperature:
Industrial
°C
Operating case temperature:
Automotive
–40 to +105
–40 to +125
°C
°C
TC
TC
1, 2, 3, 4
1, 2, 3, 4
Operating case temperature:
Ultra-high
78-ball “WE”
96-ball “JY”
4.2
4.1
Junction-to-case (TOP) Rev B
°C/W
ΘJC
5
1. MAX operating case temperature. TC is measured in the center of the package.
Notes:
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs
interval refresh rate.
5. The thermal resistance data is based off of a number of samples from multiple lots and
should be viewed as a typical number.
Figure 237: Thermal Measurement Point
TC test point
(L/2)
L
(W/2)
W
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Current Specifications – Measurement Conditions
Current Specifications – Measurement Conditions
IDD, IPP, and IDDQ Measurement Conditions
IDD, IPP, and IDDQ 0easure0ent conditions, such as test load and patterns, are defined
in this section.
• IDD currents (IDD6, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R
,
IDD±N, IDD±E, IDD±R, IDD7, and IDD8) are 0easured as ti0e-averaged currents with all
VDD balls of the device under test grouped together. IPP and IDDQ currents are not in-
cluded in IDD currents.
• IPP currents are IPPSB for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8);
IPP6 for active cases (IDD6,IDD1, IDD4R, IDD4W); IPP5R and IPP±N for self refresh cases
(IDD±N, IDD±E, IDD±R), and IPP7. These have the sa0e definitions as the IDD currents ref-
erenced but are 0easured on the VPP supply.
• IDDQ currents (IDDQ2NT) are 0easured as ti0e-averaged currents with VDDQ balls of
the device under test grouped together. IDD current is not included in IDDQ currents.
Note: IDDQ values cannot be directly used to calculate the I/O power of the de-
vice. They can be used to support correlation of si0ulated I/O power to actual
I/O power. In DRAM 0odule application, IDDQ cannot be 0easured separately
because VDD and VDDQ are using a 0erged-power layer in the 0odule PCB.
The following definitions apply for IDD, IDDP and IDDQ 0easure0ents.
• “6” and “LOW” are defined as VIN VIL(AC)0ax
• “1” and “HIGH” are defined as VIN VIH(AC)0in
• “Midlevel” is defined as inputs VREF = VDD/2
• Ti0ings used for IDD, IDDP and IDDQ 0easure0ent-loop patterns are provided in the
Current Test Definition and Patterns section.
• Basic IDD, IPP, and IDDQ 0easure0ent conditions are described in the Current Test
Definition and Patterns section.
• Detailed IDD, IPP, and IDDQ 0easure0ent-loop patterns are described in the Current
Test Definition and Patterns section.
• Current 0easure0ents are done after properly initializing the device. This includes,
but is not li0ited to, setting:
RON = RZQ/7 (34 oh0 in MR1);
Qoff = 6B (output buffer enabled in MR1);
R
TT(NOM) = RZQ/± (46 oh0 in MR1);
RTT(WR) = RZQ/2 (126 oh0 in MR2);
RTT(Park) = disabled;
TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in
MR3; Gear-down 0ode disabled in MR3; Read/Write DBI disabled in MR5; DM disa-
bled in MR5
• Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA
changes when directed.
• Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply in-
vert of BG/BA changes when directed above.
Note: The 0easure0ent-loop patterns 0ust be executed at least once before ac-
tual current 0easure0ents can be taken.
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Current Specifications – Measurement Conditions
Figure 238: Measurement Setup and Test Load for IDDx, IDDPx, and IDDQx
I
I
I
DDQ
DD
PP
V
V
V
DDQ
DD
PP
RESET_n
CK_t/CK_c
DDR4
DQS_t, DQS_c
DQ
CKE
CS_n
C
SDRAM
DM_n
ACT_n, RAS_n, CAS_n, WE_n
A, BG, BA
ODT
ZQ
V
V
SS
SSQ
Figure 239: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power
Application-specific
memory channel
environment
IDD Q
test load
Channel I/O
power simulation
IDD Q
simulation
IDD Q
measurement
Correlation
Correction
Channel I/O
power number
1. Supported by IDDQ measurement.
Note:
IDD Definitions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions
Symbol Description
IDD0
Operating One Bank Active-Precharge Current (AL = 0)
CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between
ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the
next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2,
2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT
signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table
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Current Specifications – Measurement Conditions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol Description
IPP0
Operating One Bank Active-Precharge IPP Current (AL = 0)
Same conditions as IDD0 above
IDD1
Operating One Bank Active-Read-Precharge Current (AL = 0)
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH
between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially
toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with
one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode
registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
IDD2N
Precharge Standby Current (AL = 0)
CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measure-
ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and
RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-
Loop Pattern table
IDD2NT
Precharge Standby ODT Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank gropup address, bank address inputs: partially toggling according to the IDD2NT and IDDQ2NT Meas-
urement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer
and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT and IDDQ2NT Measurement-
Loop Pattern table; Pattern details: see the IDD2NT and IDDQ2NT Measurement-Loop Pattern table
IDDQ2NT
IDD2P
Precharge Standby ODT IDDQ Current
Has the same definition as IDD2NT above, with the exception of measuring IDDQ current instead of IDD current
Precharge Power-Down Current
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD2Q
Precharge Quiet Standby Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD3N
Active Standby Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measure-
ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and
RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-
Loop Pattern table
IPPSB
Active Standby IPPSB Current (AL = 0)
Same conditions as IDD3N above
IDD3P
Active Power-Down Current (AL = 0)
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
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Current Specifications – Measurement Conditions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol Description
IDD4R
IDD4W
IDD5R
Operating Burst Read Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 5 AL: 0; CS_n: HIGH between RD; Com-
mand, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measure-
ment-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the
next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks
open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table);
Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Meas-
urement-Loop Pattern table
Operating Burst Write Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Com-
mand, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measure-
ment-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the
next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks
open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table);
Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see
the IDD4W Measurement-Loop Pattern table
Burst Refresh Current (1X REF)
CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF;
Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Meas-
urement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see
the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal:
stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table
IPP5R
Burst Refresh Current (1X REF)
Same conditions as IDD5R above
IDD6N
Self Refresh Current: Normal Temperature Range
TC: 0–85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; Exter-
nal clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group
address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer
and RTT: enabled in mode registers;2 ODT signal: midlevel
IPP6N
IDD6E
Self Refresh IPP Current: Normal Temperature Range
Same conditions as IDD6N above
Self Refresh Current: Extended Temperature Range 4
TC: 0–95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; Ex-
ternal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group
bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
IDD6R
Self Refresh Current: Reduced Temperature Range
TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; Exter-
nal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank
group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
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Current Specifications – Measurement Conditions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol Description
IDD7
Operating Bank Interleave Read Current
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;1 5 AL: CL -
1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially
toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data
between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;
Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7
Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0;
Pattern details: see the IDD7 Measurement-Loop Pattern table
IPP7
Operating Bank Interleave Read IPP Current
Same conditions as IDD7 above
IDD8
Maximum Power Down Current
Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n:
stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n:
stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: sta-
ble at 0
1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.
Notes:
2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON
=
RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001
(RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).
3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.
4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended
temperature range.
5. READ burst type: Nibble sequential, set MR0[3] 0.
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Current Specifications – Patterns and Test Conditions
Current Specifications – Patterns and Test Conditions
Current Test Definitions and Patterns
Table 136: IDD0 and IPP0 Measurement-Loop Pattern1
Data3
0
0
ACT
D, D
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
3
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
–
–
–
1, 2
3, 4
D_n,
D_n
...
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
nRAS
PRE
0
1
0
1
0
0
0
0
0
0
0
0
0
0
–
...
Repeat pattern 1...4 until nRC - 1; truncate if necessary
1
2
3
4
5
6
7
8
9
1 × nRC
2 × nRC
3 × nRC
4 × nRC
5 × nRC
6 × nRC
7 × nRC
8 × nRC
9 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
10 10 × nRC
11 11 × nRC
12 12 × nRC
13 13 × nRC
14 14 × nRC
15 15 × nRC
1. DQS_t, DQS_c are VDDQ
.
Notes:
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ
4. For x4 and x8 only.
.
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Current Specifications – Patterns and Test Conditions
Table 137: IDD1 Measurement – Loop Pattern1
Data3
0
0
1, 2
ACT
D, D
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
3
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
–
–
–
3, 4
D_n, D_n
...
Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary
nRCD - AL
...
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
nRAS
...
PRE
0
1
0
1
0
0
0
0
0
0
0
0
0
0
Repeat pattern 1...4 until nRC - 1; truncate if necessary
D5 = 00, D7 = FF
1
1 × nRC + 0
ACT
D, D
0
1
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
1 × nRC + 1,
2
1 × nRC + 3, D_n, D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
4
...
Repeat pattern nRC + 1...4 until 1 × nRC + nRAS - 1; truncate if necessary
1 × nRC
+nRCD - AL
RD
0
1
1
0
1
0
1
1
0
0
0
0
0
0
D0 = FF, D1 =
00,
D2 = 00, D3 =
FF,
D4 = 00, D5 =
FF,
...
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
1 × nRC +
nRAS
PRE
0
1
0
1
0
0
1
1
0
0
0
0
0
0
...
Repeat pattern nRC + 1...4 until 2 × nRC - 1; truncate if necessary
D5 = FF, D7 = 00
2
3
2 × nRC
3 × nRC
4 × nRC
5 × nRC
6 × nRC
7 × nRC
9 × nRC
10 × nRC
11 × nRC
12 × nRC
13 × nRC
14 × nRC
15 × nRC
16 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
4
5
6
7
8
9
10
11
12
13
14
15
1. DQS_t, DQS_c are VDDQ when not toggling.
Notes:
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Current Specifications – Patterns and Test Conditions
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ com-
mand.
4. For x4 and x8 only.
Table 138: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1
Data3
0
0
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
3
3
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
F
F
0
0
0
0
–
–
–
–
1
D
2
D_n
D_n
3
1
2
4–7
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
8–11
12–15
16–19
20–23
24–27
28–31
32–35
36–39
40–43
44–47
48–51
52–55
56–59
60–63
3
4
5
6
7
8
9
10
11
12
13
14
15
1. DQS_t, DQS_c are VDDQ
.
Notes:
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ
4. For x4 and x8 only.
.
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Current Specifications – Patterns and Test Conditions
Table 139: IDD2NT and IDDQ2NT Measurement – Loop Pattern1
Data3
0
0
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
3
3
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
F
F
0
0
0
0
–
–
–
–
1
D
2
D_n
D_n
3
1
2
4–7
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
8–11
12–15
16–19
20–23
24–27
28–31
32–35
36–39
40–43
44–47
48–51
52–55
56–59
60–63
3
4
5
6
7
8
9
10
11
12
13
14
15
1. DQS_t, DQS_c are VSSQ
.
Notes:
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VSSQ
4. For x4 and x8 only.
.
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Current Specifications – Patterns and Test Conditions
Table 140: IDD4R Measurement – Loop Pattern1
Data3
0
0
1
RD
D
0
1
1
1
0
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
3
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
2, 3
D_n,
D_n
D5 = 00, D7 =
FF
1
4
5
RD
D
0
1
1
1
0
1
1
0
1
0
0
1
1
0
1
0
0
0
1
0
3
1
0
3
0
0
0
0
0
0
0
0
0
7
0
7
F
0
F
0
0
0
D0 = FF, D1 = 00
D2 = 00, D3 =
FF
D4 = 00, D5 =
FF
6, 7
D_n,
D_n
D5 = FF, D7 = 00
2
3
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
12–15
16–19
20–23
24–27
28–31
32–35
36–39
40–43
44–47
48–51
52–55
56–59
60–63
4
5
6
7
8
9
10
11
12
13
14
15
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
Notes:
3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation,
DQ signals are VDDQ
.
4. For x4 and x8 only.
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Current Specifications – Patterns and Test Conditions
Table 141: IDD4W Measurement – Loop Pattern1
Data3
0
1
0
1
WR
D
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
0
3
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D5 = 00, D7 = FF
2, 3
D_n,
D_n
4
5
WR
D
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
1
1
1
0
3
1
0
3
0
0
0
0
0
0
0
0
0
7
0
7
F
0
F
0
0
0
D0 = FF, D1 = 00
D2 = 00, D3 = FF
D4 = 00, D5 = FF
D5 = FF, D7 = 00
6, 7
D_n,
D_n
2
3
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
12–15
16–19
20–23
24–27
28–31
32–35
36–39
40–43
44–47
48–51
52–55
56–59
60–63
4
5
6
7
8
9
10
11
12
13
14
15
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
Notes:
3. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ
.
4. For x4 and x8 only.
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Current Specifications – Patterns and Test Conditions
Table 142: IDD4Wc Measurement – Loop Pattern1
Data4
0
1
0
WR
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
0
3
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D8 = CRC
1, 2
3, 4
D, D
D_n,
D_n
5
WR
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
1
1
1
0
3
1
0
3
0
0
0
0
0
0
0
0
0
7
0
7
F
0
F
0
0
0
D0 = FF, D1 = 00,
D2 = 00, D3 = FF,
D4 = 00, D5 = FF,
D5 = FF, D7 = 00
D8 = CRC
6, 7
8, 9
D, D
D_n,
D_n
2
3
10–14
15–19
20–24
25–29
30–34
35–39
40–44
45–49
50–54
55–59
60–64
65–69
70–74
75–79
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
4
5
6
7
8
9
10
11
12
13
14
15
1. Pattern provided for reference only.
2. DQS_t, DQS_c are VDDQ when not toggling.
3. BG1 is a "Don't Care" for x16 devices.
Notes:
4. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ
.
5. For x4 and x8 only.
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Current Specifications – Patterns and Test Conditions
Table 143: IDD5R Measurement – Loop Pattern1
Data3
0
1
0
REF
D
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
3
3
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
0
F
F
0
0
0
0
0
–
–
–
–
–
1
2
D
3
D_n
D_n
4
5–8
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead 4
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead 4
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead 4
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead 4
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead 4
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead 4
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead 4
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead 4
Repeat sub-loop 1; truncate if necessary
9–12
13–16
17–20
21–24
25–28
29–32
33–36
37–40
41–44
45–48
49–52
53–56
57–60
61–64
2
65...nREFI -
1
1. DQS_t, DQS_c are VDDQ
.
Notes:
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ
4. For x4 and x8 only.
.
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Current Specifications – Patterns and Test Conditions
Table 144: IDD7 Measurement – Loop Pattern1
Data3
0
1
0
ACT
RDA
D
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
3
0
0
0
3
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
7
0
0
0
F
0
0
0
0
–
1
2
–
–
3
D_n
...
Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
nRRD
ACT
RDA
0
0
0
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
–
nRRD+1
...
Repeat pattern 2...3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessary
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
2
3
2 × nRRD
3 × nRRD
4 × nRRD
nFAW
4
Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
Repeat sub-loop 4
5
6
nFAW + nRRD
nFAW + 2 × nRRD
nFAW + 3 × nRRD
nFAW + 4 × nRRD
2 × nFAW
7
8
9
10
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead
11 2 × nFAW + nRRD
12
13
14
15
2 × nFAW + 2 ×
nRRD
2 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead
Repeat sub-loop 4
2 × nFAW + 4 ×
nRRD
3 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead
16 3 × nFAW + nRRD
17
18
19
20
3 × nFAW + 2 ×
nRRD
3 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead
Repeat sub-loop 4
3 × nFAW + 4 ×
nRRD
4 × nFAW
Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary
1. DQS_t, DQS_c are VDDQ
.
Notes:
2. BG1 is a "Don't Care" for x16 devices.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ com-
mand.
4. For x4 and x8 only.
IDD Specifications
Table 145: Timings used for IDD, IPP, and IDDQ Measurement – Loop Patterns
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
DDR4-2933
DDR4-3200
Uni
t
Symbol
tCK
1.25
1.071
0.937
0.833
0.75
0.682
0.625
ns
CL
10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 20 21 22 20 22 24 CK
11 11 10 12 12 11 14 14 12 16 16 14 18 18 14 18 18 16 20 20 CK
CWL
9
nRCD
nRC
10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 19 20 21 20 22 24 CK
38 39 40 44 45 46 50 51 52 54 55 57 60 61 62 66 67 68 72 74 76 CK
10 11 12 12 13 14 14 15 16 15 16 17 17 18 19 19 20 21 20 22 24 CK
nRP
nRAS
nFA x41
28
16
20
28
32
16
22
28
36
16
23
32
39
16
26
36
43
16
28
40
47
16
31
44
52
16
34
48
CK
CK
CK
CK
W
x8
x1
6
nRRD x4
4
4
5
4
4
5
4
4
6
4
4
7
4
4
7
4
4
8
4
4
9
CK
CK
CK
_S
x8
x1
6
nRRD x4
5
5
6
5
5
6
6
6
7
6
6
8
7
7
9
8
8
8
8
CK
CK
CK
_L
x8
x1
6
10
11
nCCD_S
nCCD_L
nWTR_S
nWTR_L
nREFI
4
5
4
5
4
6
4
6
4
7
4
8
4
8
CK
CK
CK
CK
CK
CK
CK
CK
CK
2
3
3
3
4
4
4
6
7
8
9
10
11
12
6,240
128
208
280
440
7,283
150
243
327
514
8,324
171
278
374
587
9,364
193
313
421
660
10,400
214
347
467
734
11,437
235
382
514
807
12,480
256
416
560
880
nRFC 2Gb
nRFC 4Gb
nRFC 8Gb
nRFC
16Gb
1. 1KB based x4 use same numbers of clocks for nFAW as the x8.
Note:
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8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Limits
Current Specifications – Limits
Table 146: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +95°C)
DDR4-2666
DDR4-2400
(-083E)
Symbol
Width
×8
(-075E)
51
85
3
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
DD0: One bank ACTIVATE-to-PRECHARGE current
48
80
3
×16
×8
PP0: One bank ACTIVATE-to-PRECHARGE IPP current
DD1: One bank ACTIVATE-to-READ-to- PRECHARGE
×16
×8
4
4
63
105
35
35
50
75
25
25
30
30
46
50
3
60
100
34
34
50
75
25
25
30
30
43
47
3
current
×16
×8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DD2N: Precharge standby current
DD2NT: Precharge standby ODT current
DD2P: Precharge power-down current
DD2Q: Precharge quiet standby current
DD3N: Active standby current
×16
×8
×16
×8
×16
×8
×16
×8
×16
×8
PP3N: Active standby IPP current
DD3P: Active power-down current
DD4R: Burst read current
×16
×8
3
3
39
43
149
275
135
264
255
290
28
28
30
30
35
35
35
35
20
20
37
41
138
255
126
248
255
290
28
28
30
30
35
35
35
35
20
20
×16
×8
×16
×8
DD4W: Burst write current
×16
×8
DD5B: Burst refresh current (1X REF)
PP5B: Burst refresh IPP current (1X REF)
DD6N: Self refresh current1
×16
×8
×16
×8
×16
×8
DD6AT: Auto self refresh current 4
DD6ET: Self refresh current2
×16
×8
×16
×8
DD6RT: Self refresh current3, 4
×16
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Current Specifications – Limits
Table 146: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +95°C) (Continued)
DDR4-2666
(-075E)
DDR4-2400
(-083E)
Symbol
Width
×8
Unit
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
I
PP6: Auto self refresh IPP current23
5
5
5
5
×16
×8
DD7: Bank interleave read current
PP7: Bank interleave read IPP current
DD8: Maximum power-down current
182
262
15
20
25
25
177
252
15
20
25
25
×16
×8
×16
×8
×16
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (–40°C–+85°C).
Notes:
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (–40°C–+95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (–40°C–+45°C).
4. IDD6RT and IDD6AT values are typical.
5. When additive latency is enabled for IDD0, current changes by approximately 0%.
6. When additive latency is enabled for IDD1, current changes by approximately +5% (×4/
×8), +4% (×16).
7. When additive latency is enabled for IDD2N, current changes by approximately +0%.
8. When DLL is disabled for IDD2N, current changes by approximately –23%.
9. When CAL is enabled for IDD2N, current changes by approximately –25%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +7%.
12. When additive latency is enabled for IDD3N, current changes by approximately +0.6%.
13. When additive latency is enabled for IDD4R, current changes by approximately +5%.
14. When read DBI is enabled for IDD4R, current changes by approximately 0%.
15. When additive latency is enabled for IDD4W, current changes by approximately +3% (×4/
×8), +4% (×16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%.
17. When write CRC is enabled for IDD4W, current changes by approximately +10% (×4/×8),
+10% (×16).
18. When CA parity is enabled for IDD4W, current changes by approximately +12% (×8),
+12% (×16).
19. When 2X REF is enabled for IDD5B, current changes by approximately –14%.
20. When 4X REF is enabled for IDD5B, current changes by approximately –33%.
21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests.
23. IPP6x is applicable to IDD6N, IDD6E, IDD6R, and IDD6A conditions.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Limits
Table 147: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +105°C)
DDR4-2666
(-075E)
DDR4-2400
(-083E)
Symbol
Width
×8
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
DD0: One bank ACTIVATE-to-PRECHARGE current
53
88
3
53
88
3
×16
×8
PP0: One bank ACTIVATE-to-PRECHARGE IPP current
DD1: One bank ACTIVATE-to-READ-to- PRECHARGE
×16
×8
4
4
65
108
37
38
52
78
27
28
32
33
48
53
3
65
108
37
38
52
78
27
28
32
33
48
53
3
current
×16
×8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DD2N: Precharge standby current
DD2NT: Precharge standby ODT current
DD2P: Precharge power-down current
DD2Q: Precharge quiet standby current
DD3N: Active standby current
×16
×8
×16
×8
×16
×8
×16
×8
×16
×8
PP3N: Active standby IPP current
DD3P: Active power-down current
DD4R: Burst read current
×16
×8
3
3
41
46
151
279
138
269
260
295
28
28
32
33
37
38
37
38
22
23
41
46
151
279
138
269
260
295
28
28
32
33
37
38
37
38
22
23
×16
×8
×16
×8
DD4W: Burst write current
×16
×8
DD5B: Burst refresh current (1X REF)
PP5B: Burst refresh IPP current (1X REF)
DD6N: Self refresh current1
×16
×8
×16
×8
×16
×8
DD6AT: Auto self refresh current 4
DD6ET: Self refresh current2
×16
×8
×16
×8
DD6RT: Self refresh current3, 4
×16
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Current Specifications – Limits
Table 147: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +105°C) (Continued)
DDR4-2666
(-075E)
DDR4-2400
(-083E)
Symbol
Width
×8
Unit
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
I
PP6: Auto self refresh IPP current23
5
5
5
5
×16
×8
DD7: Bank interleave read current
PP7: Bank interleave read IPP current
DD8: Maximum power-down current
184
264
15
20
27
28
184
264
15
20
27
28
×16
×8
×16
×8
×16
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (–40°C–+85°C).
Notes:
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (–40°C–+105°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (–40°C–+45°C).
4. IDD6RT and IDD6AT values are typical.
5. When additive latency is enabled for IDD0, current changes by approximately 0%.
6. When additive latency is enabled for IDD1, current changes by approximately +5% (×4/
×8), +4% (×16).
7. When additive latency is enabled for IDD2N, current changes by approximately +0%.
8. When DLL is disabled for IDD2N, current changes by approximately –23%.
9. When CAL is enabled for IDD2N, current changes by approximately –25%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +7%.
12. When additive latency is enabled for IDD3N, current changes by approximately +0.6%.
13. When additive latency is enabled for IDD4R, current changes by approximately +5%.
14. When read DBI is enabled for IDD4R, current changes by approximately 0%.
15. When additive latency is enabled for IDD4W, current changes by approximately +3%(×4/
×8), +4%(×16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%.
17. When write CRC is enabled for IDD4W, current changes by approximately +10%(×4/×8),
+10%(×16).
18. When CA parity is enabled for IDD4W, current changes by approximately +12% (×8),
+12% (×16).
19. When 2X REF is enabled for IDD5B, current changes by approximately –14%.
20. When 4X REF is enabled for IDD5B, current changes by approximately –33%.
21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests.
23. IPP6x is applicable to IDD6N, IDD6E, IDD6R, and IDD6A conditions.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Limits
Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +125°C)
DDR4-2666
(-075E)
DDR4-2400
(-083E)
Symbol
Width
×8
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
DD0: One bank ACTIVATE-to-PRECHARGE current
68
95
3
68
95
3
×16
×8
PP0: One bank ACTIVATE-to-PRECHARGE IPP current
DD1: One bank ACTIVATE-to-READ-to- PRECHARGE
×16
×8
4
4
80
115
53
55
77
85
45
45
49
49
76
76
3
80
115
53
55
77
85
45
45
49
49
76
76
3
current
×16
×8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DD2N: Precharge standby current
DD2NT: Precharge standby ODT current
DD2P: Precharge power-down current
DD2Q: Precharge quiet standby current
DD3N: Active standby current
×16
×8
×16
×8
×16
×8
×16
×8
×16
×8
PP3N: Active standby IPP current
DD3P: Active power-down current
DD4R: Burst read current
×16
×8
3
3
69
69
170
290
161
284
275
312
28
28
51
51
59
59
59
59
47
47
69
69
170
290
161
284
275
312
28
28
51
51
59
59
59
59
47
47
×16
×8
×16
×8
DD4W: Burst write current
×16
×8
DD5B: Burst refresh current (1X REF)
PP5B: Burst refresh IPP current (1X REF)
DD6N: Self refresh current1
×16
×8
×16
×8
×16
×8
DD6AT: Auto self refresh current 4
DD6ET: Self refresh current2
×16
×8
×16
×8
DD6RT: Self refresh current3. 4
×16
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Current Specifications – Limits
Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. B (–40° ≤ TC ≤ +125°C) (Continued)
DDR4-2666
(-075E)
DDR4-2400
(-083E)
Symbol
Width
×8
Unit
mA
mA
mA
mA
mA
mA
mA
mA
I
I
I
I
PP6: Auto self refresh IPP current23
5
5
5
5
×16
×8
DD7: Bank interleave read current
PP7: Bank interleave read IPP current
DD8: Maximum power-down current
192
273
15
20
42
42
192
273
15
20
42
42
×16
×8
×16
×8
×16
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (–40°C–+85°C).
Notes:
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera-
ture range of operation (–40°C–+125°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (–40°C–+45°C).
4. IDD6RT and IDD6AT values are typical.
5. When additive latency is enabled for IDD0, current changes by approximately 0%.
6. When additive latency is enabled for IDD1, current changes by approximately +5% (×4/
×8), +4% (×16).
7. When additive latency is enabled for IDD2N, current changes by approximately +0%.
8. When DLL is disabled for IDD2N, current changes by approximately –23%.
9. When CAL is enabled for IDD2N, current changes by approximately –25%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +7%.
12. When additive latency is enabled for IDD3N, current changes by approximately +0.6%.
13. When additive latency is enabled for IDD4R, current changes by approximately +5%.
14. When read DBI is enabled for IDD4R, current changes by approximately 0%.
15. When additive latency is enabled for IDD4W, current changes by approximately +3% (×4/
×8), +4% (×16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%.
17. When write CRC is enabled for IDD4W, current changes by approximately +10%(×4/×8),
+10%(×16).
18. When CA parity is enabled for IDD4W, current changes by approximately +12% (×8),
+12% (×16).
19. When 2X REF is enabled for IDD5B, current changes by approximately –14%.
20. When 4X REF is enabled for IDD5B, current changes by approximately –33%.
21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x, and IDD8 conditions; that is, test-
ing IPP3N should satisfy the IPPs for the noted IDD tests.
23. IPP6x is applicable to IDD6N, IDD6E, IDD6R, and IDD6A conditions.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Speed Bin Tables
DDR4 DRAM ti0ing is pri0arily covered by two types of tables: the speed bin tables in
this section and those tables found in the Electrical Characteristics and AC Ti0ing Pa-
ra0eters section. The ti0ing para0eter tables define the applicable ti0ing specifica-
tions based on the speed rating. The speed bin tables below list the tAA, tRCD, tRP, tRAS
and tRC li0its of a given speed 0ark and are applicable to the CL settings in the lower
half of the table provided they are applied in the correct clock range, which is noted.
Table 149: DDR4-1600 Speed Bins and Operating Conditions
DDR4-1600 Speed Bin
CL-nRCD-nRP
-125F
-125E
-125
10-10-10
11-11-11
12-12-12
Parameter
Symbol
tAA
tAA_DBI
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
12.50
tAA
13.755
tAA
15.00
tAA
Internal READ command to first data
with read DBI enabled
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
2nCK
2nCK
2nCK
2nCK
2nCK
2nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.50
–
13.755
–
15.00
–
ns
PRECHARGE command period
tRP
tRAS
12.50
35
–
13.755
35
–
15.00
35
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ: non-
DBI
READ: DBI WRITE
Symbol
tCK4
tCK4
tCK4
tCK4
Min
1.5
Max
1.9
Min
1.5
Max
1.9
Min
Max
Unit
ns
CL = 9
CL = 10
CL = 10
CL = 11
CL = 12
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CWL = 9
Reserved
CWL = 9
1.5
1.9
1.5
1.9
1.5
1.9
ns
CWL = 9, 11
CWL = 9, 11
CWL = 9, 11
1.25
1.25
1.25
<1.5
<1.5
<1.5
Reserved
Reserved
Reserved
1.25 <1.5
ns
1.25
1.25
<1.5
<1.5
ns
tCK4
ns
Supported CL settings
9–12
9, 10, 11, 12
10, 12
12, 14
9, 11
nCK
nCK
nCK
Supported CL settings with read DBI
Supported CWL settings
11–14
9, 11
11, 12, 13, 14
9, 11
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation at defined clock rates.
6. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 150: DDR4-1866 Speed Bins and Operating Conditions
DDR4-1866 Speed Bin
CL-nRCD-nRP
-107F
-107E
-107
12-12-12
13-13-13
14-14-14
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
12.85
tAA
13.927
tAA
15.00
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
2nCK
2nCK
2nCK
2nCK
2nCK
2nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.85
–
13.92 7
–
15.00
–
ns
PRECHARGE command period
tRP
tRAS
12.85
34
–
13.92 7
34
–
15.00
34
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC8
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
nonDBI READ: DBI WRITE
Symbol
tCK6
tCK6
tCK6
tCK6
tCK6
tCK6
tCK6
tCK6
Min
1.5
Max
1.9
Min
1.5
Max
1.9
Min
Max
Unit
ns
CL = 9
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CWL = 9
Reserved
CL = 10
CL = 10
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CWL = 9
1.5
1.9
1.5
1.9
1.5
1.9
ns
CWL = 11
Reserved
Reserved
Reserved
Reserved
Reserved
1.25 <1.5
ns
CWL = 9, 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 10, 12
1.25
1.25
<1.5
<1.5
ns
1.25
<1.5
<1.25
<1.25
<1.25
ns
1.071
1.071
1.071
Reserved
Reserved
Reserved
ns
1.071
1.071
<1.25
<1.25
ns
1.071
<1.25
ns
Supported CL settings
9, 10, 12–14
9, 10–14
10, 12, 14
12, 14, 16
9–12
nCK
nCK
nCK
Supported CL settings with read DBI
Supported CWL settings
11,12,14-16
9–12
11–16
9–12
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. 12.85ns is the minimum value of tAA and tRP when operating at DDR4-1866 at tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 12.5ns supports.
5. 13.92ns is the minimum value of tAA and tRP when operating at DDR4-1866 at tCK
(AVG) MIN = 1.071ns and is only a reference that does not consider the down binning
strategy that 13.75ns supports.
6. tCK (AVG) MIN.
7. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation at de-
fined clock rates.
8. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
CCMTD-1406124318-10419
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8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 151: DDR4-2133 Speed Bins and Operating Conditions
DDR4-2133 Speed Bin
CL-nRCD-nRP
-093F
-093E
-093
14-14-14
15-15-15
16-16-16
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
13.13
tAA
14.065
tAA
15.00
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
2nCK
2nCK
2nCK
2nCK
2nCK
2nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.13
–
14.065
–
15.00
–
ns
PRECHARGE command period
tRP
tRAS
13.13
33
–
14.065
33
–
15.00
33
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC7
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
nonDBI READ: DBI WRITE
Symbol
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
Min
1.5
Max
1.9
Min
1.5
Max
1.9
Min
Max
Unit
CL = 9
CL = 11
CL = 12
CL = 13
CL = 14
CL = 15
CL = 16
CL = 17
CL = 18
CL = 19
CWL = 9
Reserved
ns
CL = 10
CL = 11
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CWL = 9
1.5
1.9
1.5
1.9
1.5
1.9
CWL = 9 , 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 11, 14
CWL = 11, 14
CWL = 11, 14
Reserved
1.25
1.25
1.071
1.071
<1.5
<1.5
<1.25
<1.25
Reserved
ns
ns
1.25
<1.5
1.25
<1.5
Reserved
Reserved
ns
1.071
0.9376
0.937
0.937
<1.25
<1.071
<1.071
<1.071
1.071
<1.25
ns
Reserved
Reserved
Reserved
0.937 <1.071
ns
0.937
0.937
<1.071
<1.071
ns
ns
Supported CL settings
9, 10, 12, 14–16
11, 12, 14, 16–19
9, 10, 11, 12, 14
9–16
10, 12, 14, 16
12, 14, 16, 19
9, 10, 11, 12, 14
nCK
nCK
nCK
Supported CL settings with read DBI
Supported CWL settings
11–16,18,19
9, 10, 11, 12, 14
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation and 13.75ns with CL11 operation 13.92ns
with CL13 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/0.938ns),
but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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327
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8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 152: DDR4-2400 Speed Bins and Operating Conditions
DDR4-2400 Speed Bin
CL-nRCD-nRP
-083F
-083E
-083
15-15-15
16-16-16
17-17-17
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
12.5
tAA
13.32
tAA
14.16
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
3nCK
3nCK
3nCK
3nCK
3nCK
3nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.5
–
13.32
–
14.16
–
ns
PRECHARGE command period
tRP
tRAS
12.5
32
–
13.32
32
–
14.16
32
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
READ: DBI WRITE
Symbol
Min
Max
Min
Max
Min
Max
Unit
nonDBI
CL = 9
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL =17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
CWL = 9
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
1.5
1.5
1.9
1.9
1.5
1.5
1.9
1.9
Reserved
ns
ns
CL = 10
CL = 10
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CWL = 9
1.5
1.9
CWL = 9, 11
CWL = 9, 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 10, 12
CWL = 11, 14
CWL = 11, 14
CWL = 11, 14
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
Reserved
Reserved
1.25 <1.5
Reserved
Reserved
ns
1.25
1.25
<1.5
<1.5
1.25
1.25
<1.5
<1.5
ns
ns
Reserved
Reserved
Reserved
Reserved
ns
1.071
1.071
<1.25
<1.25
1.071
1.071
<1.25
<1.25
ns
1.071
<1.25
ns
Reserved
Reserved
Reserved
0.9375
Reserved
ns
<1.071
<1.071
0.937
0.937
<1.071
<1.071
ns
0.937
<1.071
<0.937
<0.937
<0.937
<0.937
0.937
ns
0.833
0.833
0.833
0.833
Reserved
Reserved
Reserved
ns
0.833
0.833
0.833
<0.937
<0.937
<0.937
ns
0.833
0.833
10–18
<0.937
ns
<0.937
ns
Supported CL settings
9, 10, 12, 14–18
11, 12, 14, 16, 18-21
9-12, 14, 16
9–18
nCK
nCK
nCK
Supported CL settings with read DBI
Supported CWL settings
11–16, 18–21
9-12, 14, 16
12–16, 18–21
9-12, 14, 16
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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328
© 2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
5. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/0.938ns),
but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
6. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
Table 153: DDR4-2666 Speed Bins and Operating Conditions
DDR4-2666 Speed Bin
CL-nRCD-nRP
-075F
-075E
-075
17-17-17
18-18-18
19-19-19
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
12.75
tAA
13.5
tAA
14.255
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
3nCK
3nCK
3nCK
3nCK
3nCK
3nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.75
–
13.5
–
14.255
–
ns
PRECHARGE command period
tRP
tRAS
12.75
32
–
13.5
32
–
14.255
32
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC7
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
READ: DBI WRITE
Symbol
Min
Max
Min
Max
Min
Max
Unit
nonDBI
CL = 9
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL =17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
CL = 20
CL = 21
CL = 22
CWL = 9
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
1.5
1.5
1.9
1.9
1.5
1.5
1.9
1.9
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 10
CL = 10
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CL = 17
CL = 18
CL = 19
CWL = 9
1.5
1.9
CWL = 9, 11
CWL = 9, 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 10, 12
CWL = 11, 14
CWL = 11, 14
CWL = 11, 14
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 14, 18
CWL = 14, 18
CWL = 14, 18
Reserved
Reserved
Reserved
1.25
1.25
<1.5
<1.5
1.25
1.25
<1.5
<1.5
1.25
1.25
<1.5
<1.5
Reserved
Reserved
Reserved
1.071
1.071
<1.25
<1.25
1.071
1.071
<1.25
<1.25
1.071
1.071
<1.25
<1.25
Reserved
0.9376
Reserved
Reserved
<1.071
<1.071
0.937
0.937
<1.071
<1.071
0.937
0.937
<1.071
<1.071
0.937
Reserved
Reserved
Reserved
Reserved
Reserved
0.833
0.833
0.833
0.750
0.750
0.750
<0.937
<0.937
<0.937
<0.833
<0.833
<0.833
0.833
<0.937
<0.937
0.833
0.833
<0.937
<0.937
0.833
Reserved
Reserved
Reserved
0.750 <0.833
0.750
0.750
<0.833
<0.833
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
329
8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 153: DDR4-2666 Speed Bins and Operating Conditions (Continued)
DDR4-2666 Speed Bin
CL-nRCD-nRP
-075F
-075E
-075
17-17-17
18-18-18
19-19-19
Parameter
Symbol
tCK4
Min
0.750
Max
Min
0.750
Max
Min
0.750
Max
Unit
ns
CL = 20
CL = 23
CWL = 14, 18
<0.833
<0.833
<0.833
Supported CL settings
9–20
9–20
10-–20
nCK
nCK
nCK
Supported CL settings with read DBI
Supported CWL settings
11–16, 18–23
11–16, 18–23
12–16, 18–23
9-12, 14, 16, 18
9-12, 14, 16, 18
9-12, 14, 16, 18
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.92ns with CL13 operation, 14.07ns with CL15 operation, and
14.16ns with CL17 operation at defined clock rates.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/0.938ns),
but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
Table 154: DDR4-2933 Speed Bins and Operating Conditions
DDR4-2933 Speed Bin
CL-nRCD-nRP
-068E
-068
-068D
20-20-20
21-21-21
22-22-22
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
13.645
tAA
14.32
tAA
15
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
4nCK
4nCK
4nCK
4nCK
4nCK
4nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
13.64
–
14.32
–
15
–
ns
PRECHARGE command period
tRP
tRAS
13.64
32
–
14.32
32
–
15
32
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
READ: DBI WRITE
Symbol
Min
Max
Min
Max
Min
Max
Unit
nonDBI
CL = 9
CL = 11
CL = 12
CL = 12
CWL = 9
tCK4
tCK4
tCK4
1.5
1.5
1.9
1.9
Reserved
Reserved
ns
ns
ns
CL = 10
CL = 10
CWL = 9
1.5
1.9
1.5
1.9
CWL = 9, 11
Reserved
Reserved
Reserved
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
330
8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 154: DDR4-2933 Speed Bins and Operating Conditions (Continued)
DDR4-2933 Speed Bin
CL-nRCD-nRP
-068E
-068
-068D
20-20-20
21-21-21
22-22-22
Parameter
Symbol
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
Min
Max
<1.5
<1.5
Min
Max
<1.5
<1.5
Min
Reserved
1.25 <1.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CL = 17
CL = 18
CL = 19
CL = 20
CL = 19
CL = 20
CL = 21
CL = 22
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL =17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
CL = 20
CL = 21
CL = 22
CL = 23
CL = 23
CL = 24
CL = 26
CL = 26
CWL = 9, 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 10, 12
CWL = 11, 14
CWL = 11, 14
CWL = 11, 14
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 14, 18
CWL = 14, 18
CWL = 14, 18
CWL = 14, 18
CWL = 16, 20
CWL = 16, 20
CWL = 16, 20
CWL = 16, 20
1.25
1.25
1.25
1.25
Reserved
Reserved
Reserved
Reserved
1.071
1.071
<1.25
<1.25
1.071
1.071
<1.25
<1.25
1.071
<1.25
Reserved
0.9376
Reserved
Reserved
Reserved
<1.071
<1.071
0.937
0.937
<1.071
<1.071
0.937
0.937
<1.071
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.833
0.833
<0.937
<0.937
0.833
0.833
<0.937
<0.937
0.833
<0.937
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.750
<0.833
<0.833
0.750
0.750
<0.833
<0.833
0.750
0.750
<0.833
<0.833
0.750
Reserved
Reserved
Reserved
Reserved
0.682
0.682
0.682
<0.750
<0.750
<0.750
Reserved
Reserved
0.682
0.682
<0.750
<0.750
0.682
<0.750
Supported CL settings
9-22
10-22
10, 12, 14, 16, 18,
19, 20, 22
Supported CL settings with read DBI
Supported CWL settings
11-16, 18-24, 26
12-16,18-24, 26
12, 14, 16, 19, 21,
22, 23, 26
nCK
9-12, 14, 16, 18, 20
9-12, 14, 16, 18, 20
9-12, 14, 16, 18, 20 nCK
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/0.938ns),
but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in a combination that
would violate tRAS.
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8Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
Table 155: DDR4-3200 Speed Bins and Operating Conditions
DDR4-3200 Speed Bin
CL-nRCD-nRP
-062F
-062E
-062
20-20-20
22-22-22
24-24-24
Parameter
Symbol
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Min
Max
19.00
tAA
Unit
ns
Internal READ command to first data
Internal READ command to first data tAA_DBI
with read DBI enabled
12.5
tAA
13.755
tAA
15
tAA
ns
(MIN) + (MAX) + (MIN) + (MAX) + (MIN) + (MAX) +
4nCK
4nCK
4nCK
4nCK
4nCK
4nCK
ACTIVATE to internal READ or WRITE
delay time
tRCD
12.5
–
13.755
–
15
–
ns
PRECHARGE command period
tRP
tRAS
12.5
32
–
13.755
32
–
15
32
–
ns
ns
ACTIVATE-to-PRECHARGE command
period
9 × tREFI
9 × tREFI
9 × tREFI
ACTIVATE-to-ACTIVATE or REFRESH
command period
tRC6
tRAS +
tRP
–
tRAS +
tRP
–
tRAS +
tRP
–
ns
READ:
READ: DBI WRITE
Symbol
Min
Max
Min
Max
Min
Max
Unit
nonDBI
CL = 9
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL =17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
CL = 20
CL = 21
CL = 22
CL = 23
CL = 24
CL = 26
CL = 28
CWL = 9
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
tCK4
1.5
1.5
1.9
1.9
Reserved
Reserved
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
CL = 10
CL = 10
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CL = 17
CL = 18
CL = 19
CL = 20
CL = 20
CL = 22
CL = 24
CWL = 9
1.5
1.9
1.5
1.9
CWL = 9, 11
CWL = 9, 11
CWL = 9, 11
CWL = 10, 12
CWL = 10, 12
CWL = 10, 12
CWL = 11, 14
CWL = 11, 14
CWL = 11, 14
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 12, 16
CWL = 14, 18
CWL = 14, 18
CWL = 14, 18
CWL = 14, 18
CWL = 16, 20
CWL = 16, 20
CWL = 16, 20
Reserved
Reserved
Reserved
Reserved
1.25 <1.5
1.25
1.25
<1.5
<1.5
1.25
1.25
<1.5
<1.5
Reserved
Reserved
Reserved
Reserved
1.071
1.071
<1.25
<1.25
1.071
1.071
<1.25
<1.25
1.071
<1.25
Reserved
0.9376
Reserved
Reserved
Reserved
<1.071
<1.071
0.937
0.937
<1.071
<1.071
0.937
0.937
<1.071
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.833
0.833
0.833
<0.937
<0.937
<0.937
0.833
0.833
<0.937
<0.937
0.833
<0.937
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.750
0.750
0.750
0.625
0.625
0.625
<0.833
<0.833
<0.833
<0.750
<0.750
<0.750
0.750
<0.833
<0.833
0.750
0.750
<0.833
Reserved
Reserved
Reserved
0.625
0.625
<0.750
<0.750
0.625
<0.750
Supported CL settings
9–20, 22, 24
10–20, 22, 24
10, 12, 14, 16, 18.
20, 24
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332
8Gb: x8, x16 Automotive DDR4 SDRAM
Refresh Parameters By Device Density
Table 155: DDR4-3200 Speed Bins and Operating Conditions (Continued)
DDR4-3200 Speed Bin
CL-nRCD-nRP
-062F
-062E
-062
20-20-20
22-22-22
24-24-24
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Supported CL settings with read DBI
11–16, 18-24, 26, 28 12–16, 18–22, 26, 28 12, 14, 16, 19, 21,
23, 28
nCK
Supported CWL settings
9-12, 14, 16, 18, 20
9-12, 14, 16, 18, 20
9-12, 14, 16, 18, 20 nCK
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
Notes:
2. When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. tCK (AVG) MIN.
5. The DRAM requires 13.5ns for CL9 operation; JEDEC doesn't require CL9 support for a
CL22 device.
6. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
tCK (MIN) = 0.938ns and tRP = 14.06ns, then tRP would require 15nCKs (14.06ns/0.938ns),
but if tCK (MIN) = 0.937ns and tRP = 14.06ns, then tRP would still require 15nCKs
(14.06ns/0.938ns) and not 16nCKs (14.06ns/0.937ns).
7. When calculating tRC and tRP in clocks, values may not be used in such a combination
that would violate tRAS.
Refresh Parameters By Device Density
Table 156: Refresh Parameters by Device Density
Parameter
Symbol
2Gb
4Gb
8Gb
16Gb
Unit Notes
REF command to ACT or REF
command time
tRFC (All bank groups)
160
260
350
550
ns
Average periodic refresh inter-
val
tREFI
-40°C ≤ TC ≤ 85°C
85°C < TC ≤ 95°C
95°C < TC ≤ 105°C
7.8
3.9
7.8
3.9
7.8
3.9
3.9
1.95
μs
μs
μs
μs
1
1
1.95
0.975
1.95
0.975
1.95
0.975
0.975
0.4875
105°C < TC ≤
125°C
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine
if the devices support these options or requirements.
Note:
CCMTD-1406124318-10419
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333
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Electrical Characteristics and AC Timing Parameters – DDR4-1600 through DDR4-2400
Table 157: Electrical Characteristics and AC Timing Parameters
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Clock Timing
Clock period average (DLL off mode)
Clock period average
tCK (DLL_OFF)
tCK (AVG,
DLL_ON)
8
20
8
20
8
20
8
20
ns
ns
1.25
1.9
1.071
1.9
0.937
1.9
0.833
1.9
14
High pulse width average
Low pulse width average
tCH (AVG)
tCL (AVG)
tJITper_tot
tJITper_tot
tJITper,lck
tCK (ABS)
0.48
0.48
–63
–31
–50
0.52
0.52
63
0.48
0.48
–54
–27
–43
0.52
0.52
54
0.48
0.48
–47
–23
–38
0.52
0.52
47
0.48
0.48
–42
–21
-33
0.52
0.52
42
CK
CK
ps
ps
ps
ps
Clock period jitter
Total
Deterministic
DLL locking
31
27
23
21
50
43
38
33
Clock absolute period
MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX +
tJITper_tot MAX
Clock absolute high pulse width
(includes duty cycle jitter)
tCH (ABS)
tCL (ABS)
0.45
–
0.45
–
0.45
–
0.45
–
tCK
(AVG)
tCK
(AVG)
Clock absolute low pulse width
(includes duty cycle jitter)
0.45
–
0.45
–
0.45
–
0.45
–
Cycle-to-cycle jitter
Total
tJITcc _tot
tJITcc,lck
-
125
100
92
-
107
86
-
94
75
-
83
67
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DLL locking
-
-
-
-
Cumulative error across 2 cycles
tERR2per
tERR3per
tERR4per
tERR5per
tERR6per
tERR7per
tERR8per
tERR9per
tERR10per
tERR11per
tERR12per
tERRnper
–92
–79
79
–69
69
–61
–73
–81
–87
–92
–97
–101
–104
–107
–110
–112
61
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
–109
–121
–131
–139
–145
–151
–156
–160
–164
–168
109
121
131
139
145
151
156
160
164
168
–94
94
–82
82
73
–104
–112
–119
–124
–129
–134
–137
–141
–144
104
112
119
124
129
134
137
141
144
–91
91
81
–98
98
87
–104
–109
–113
–117
–120
–123
–126
104
109
113
117
120
123
126
92
97
101
104
107
110
112
n = 13, 14 . . . 49,
50 cycles
tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN
tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
Min Max
DQ Input Timing
DDR4-1866
DDR4-2133
Min Max
DDR4-2400
Parameter
Symbol
Min Max
Min
Max
Unit
Notes
Data setup time to
DQS_t, DQS_c
Base (calibrated
VREF
tDS
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
)
Noncalibrated
VREF
tPDA_S
tDH
minimum of 0.5UI
UI
–
Data hold time from
DQS_t, DQS_c
Base (calibrated
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
VREF
)
Noncalibrated
VREF
tPDA_H
tDIPW
minimum of 0.5UI
UI
UI
DQ and DM minimum data pulse width
for each input
0.58
–
0.58
–
0.58
–
–
0.58
–
–
DQ Output Timing (DLL enabled)
DQS_t, DQS_c to DQ skew, per group, per
access
tDQSQ
–
0.16
–
–
0.16
–
0.16
–
0.17
–
UI
DQ output hold time from DQS_t, DQS_c
Data Valid Window per device: tQH -
tDQSQ each device’s output per UI
tQH
tDVWd
0.76
0.63
0.76
0.63
0.76
0.64
0.74
0.64
UI
UI
Data Valid Window per device, per pin:
tQH - tDQSQ each device’s output per UI
tDVWp
0.66
-
0.66
-
0.69
-
0.72
-
UI
DQ Low-Z time from CK_t, CK_c
DQ High-Z time from CK_t, CK_c
tLZDQ
tHZDQ
–450
–
225
225
–390
–
195
195
–360
–
180
180
–330
–
175
175
ps
ps
DQ Strobe Input Timing
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 1tCK preamble
tDQSS1ck
tDQSS2ck
tDQSL
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
CK
CK
CK
CK
CK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 2tCK preamble
DQS_t, DQS_c differential input low pulse
width
DQS_t, DQS_c differential input high
pulse width
tDQSH
tDSS
0.46
0.46
0.46
0.46
DQS_t, DQS_c falling edge setup to CK_t,
CK_c rising edge
0.18
0.18
0.18
0.18
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
DQS_t, DQS_c falling edge hold from
CK_t, CK_c rising edge
tDSH
0.18
–
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c differential WRITE pream-
ble for 1tCK preamble
tWPRE1ck
tWPRE2ck
tWPST
0.9
1.8
–
–
–
0.9
1.8
–
–
–
0.9
1.8
–
–
–
0.9
1.8
–
–
–
CK
CK
CK
DQS_t, DQS_c differential WRITE pream-
ble for 2tCK preamble
DQS_t, DQS_c differential WRITE postam-
ble
0.33
0.33
0.33
0.33
DQS Strobe Output Timing (DLL enabled)
DQS_t, DQS_c rising edge output access
time from rising CK_t, CK_c
tDQSCK
tDQSCKi
tQSH
–225
225
370
–
–195
195
330
–
–180
-
180
310
–
–175
-
175
290
–
ps
ps
DQS_t, DQS_c rising edge output var-
iance window per DRAM
-
-
DQS_t, DQS_c differential output high
time
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
CK
CK
DQS_t, DQS_c differential output low
time
tQSL
–
–
–
–
DQS_t, DQS_c Low-Z time (RL - 1)
tLZDQS
tHZDQS
tRPRE1ck
–450
–
225
225
–
–390
–
195
195
–
–360
–
180
180
–
–330
–
175
175
–
ps
ps
DQS_t, DQS_c High-Z time (RL + BL/2)
DQS_t, DQS_c differential READ pream-
ble for 1tCK preamble
0.9
0.9
0.9
0.9
CK
DQS_t, DQS_c differential READ pream-
ble for 2tCK preamble
tRPRE2ck
tRPST
1.8
–
–
1.8
–
–
1.8
–
–
1.8
–
–
CK
CK
DQS_t, DQS_c differential READ postam-
ble
0.33
0.33
0.33
0.33
Command and Address Timing
DLL locking time
tDLLK
tIS
tISVREF
597
115
215
–
–
–
597
100
200
–
–
–
768
80
–
–
–
768
62
–
–
–
CK
ps
ps
2, 4
CMD, ADDR setup time Base
to CK_t, CK_c Base ref-
erenced to VIH(AC) and
VIL(AC) levels
VREFCA
180
162
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
tIH
tIHVREF
Min
140
215
Max
Min
125
200
Max
Min
105
180
Max
Min
87
Max
Unit
ps
Notes
CMD, ADDR hold time Base
–
–
–
–
–
–
–
–
to CK_t, CK_c Base ref-
erenced to VIH(DC) and
VIL(DC) levels
VREFCA
162
ps
CTRL, ADDR pulse width for each input
tIPW
tRCD
600
–
525
–
460
–
410
–
ps
ns
ACTIVATE to internal READ or WRITE de-
lay
See Speed Bin Tables for tRCD
PRECHARGE command period
tRP
tRAS
See Speed Bin Tables for tRP
See Speed Bin Tables for tRAS
ns
ns
ACTIVATE-to-PRECHARGE command peri-
od
13
13
1
ACTIVATE-to-ACTIVATE or REF command
period
tRC
See Speed Bin Tables for tRC
ns
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1/2KB page
size
tRRD_S
(1/2KB)
MIN = greater
of 4CK or 5ns
MIN = greater
MIN = greater
MIN = greater
CK
of 4CK or 4.2ns of 4CK or 3.7ns of 4CK or 3.3ns
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1KB page
size
tRRD_S
(1KB)
MIN = greater
of 4CK or 5ns
MIN = greater
of 4CK or 4.2ns of 4CK or 3.7ns of 4CK or 3.3ns
MIN = greater
MIN = greater
CK
CK
1
1
ACTIVATE-to-ACTIVATE command period
to different bank groups for 2KB page
size
tRRD_S
(2KB)
MIN = greater
of 4CK or 6ns
MIN = greater
of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 5.3ns
MIN = greater
MIN = greater
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1/2KB page size
tRRD_L
(1/2KB)
tRRD_L
(1KB)
tRRD_L
(2KB)
tFAW
(1/2KB)
tFAW
(1KB)
tFAW
(2KB)
MIN = greater
of 4CK or 6ns
MIN = greater
of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 4.9ns
MIN = greater MIN = greater MIN = greater
of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 4.9ns
MIN = greater MIN = greater MIN = greater
MIN = greater
MIN = greater
CK
CK
CK
ns
1
1
1
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1KB page size
MIN = greater
of 4CK or 6ns
ACTIVATE-to-ACTIVATE command period
to same bank groups for 2KB page size
MIN = greater
of 4CK or 7.5ns of 4CK or 6.4ns of 4CK or 6.4ns of 4CK or 6.4ns
MIN = greater MIN = greater MIN = greater MIN = greater
of 16CK or 20ns of 16CK or 17ns of 16CK or 15ns of 16CK or 13ns
MIN = greater MIN = greater MIN = greater MIN = greater
of 20CK or 25ns of 20CK or 23ns of 20CK or 21ns of 20CK or 21ns
MIN = greater MIN = greater MIN = greater MIN = greater
of 28CK or 35ns of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns
Four ACTIVATE windows for 1/2KB page
size
Four ACTIVATE windows for 1KB page
size
ns
Four ACTIVATE windows for 2KB page
size
ns
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
Min Max
DDR4-1866
Min Max
DDR4-2133
Min Max
DDR4-2400
Min Max
Parameter
Symbol
tWR
tWR2
Unit
ns
Notes
6, 10, 1
6, 11, 1
7, 10, 1
WRITE recovery time
MIN = 15ns
MIN = 1CK + tWR
MIN = tWR_L + greater of (5CK or 3.75ns)
CK
WRITE recovery time when CRC and DM
are both enabled
tWR_CRC_DM MIN = tWR_L +
greater of (4CK
CK
or 3.75ns)
tWR_CRC_DM2
tWTR_L
MIN = 1CK + tWR_CRC_DM
MIN = greater of 4CK or 7.5ns
MIN = 1CK + tWTR_L
CK
CK
CK
7, 11, 1
6, 10, 1
6, 11, 1
Delay from start of internal WRITE trans-
action to internal READ command – Same
bank group
tWTR_L2
Delay from start of internal WRITE trans- tWTR_L_CRC_D MIN = tWTR_L +
MIN = tWTR_L + greater of (5CK or 3.75ns)
CK
7, 10, 1
action to internal READ command – Same
bank group when CRC and DM are both
enabled
M
greater of (4CK
or 3.75ns)
tWTR_L_CRC_D
M2
MIN = 1CK + tWTR_L_CRC_DM
MIN = greater of (2CK or 2.5ns)
MIN = 1CK + tWTR_S
CK
CK
CK
CK
7, 11, 1
Delay from start of internal WRITE trans-
action to internal READ command – Dif-
ferent bank group
tWTR_S
6, 8, 9,
10, 1
tWTR_S2
6, 8, 9,
11, 1
Delay from start of internal WRITE trans- tWTR_S_CRC_D MIN = tWTR_S +
MIN = tWTR_S + greater of (5CK or 3.75ns)
7, 8, 9,
10, 1
action to internal READ command – Dif-
ferent bank group when CRC and DM are
both enabled
M
greater of (4CK
or 3.75ns)
tWTR_S_CRC_D
M2
MIN = 1CK + tWTR_S_CRC_DM
MIN = greater of 4CK or 7.5ns
CK
7, 8, 9,
11, 1
READ-to-PRECHARGE time
tRTP
tCCD_S
CK
CK
1
CAS_n-to-CAS_n command delay to dif-
ferent bank group
4
–
–
4
–
4
–
4
–
–
CAS_n-to-CAS_n command delay to same
bank group
tCCD_L
MIN =
greater
of 4CK
or
MIN =
greater
of 4CK
or
–
MIN =
greater
of 4CK
or
–
MIN =
greater
of 4CK
or 5ns
CK
15
6.25ns
5.355ns
5.355ns
Auto precharge write recovery + pre-
charge time
tDAL (MIN)
MIN = WR + ROUNDUPtRP/tCK (AVG); MAX = N/A
CK
MRS Command Timing
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
tMRD
Min
Max
Min
Max
Min
Max
Min
Max
Unit
CK
Notes
MRS command cycle time
8
–
8
–
8
–
8
–
MRS command cycle time in PDA mode
MRS command cycle time in CAL mode
tMRD_PDA
tMRD_CAL
tMOD
MIN = greater of (16nCK, 10ns)
MIN = tMOD + tCAL
CK
1
1
CK
MRS command update delay in PDA
mode
MIN = greater of (24nCK, 15ns)
CK
MRS command update delay
tMOD_PDA
tMOD_CAL
MIN = tMOD
MIN = tMOD + tCAL
CK
CK
MRS command update delay in CAL
mode
MRS command to DQS drive in preamble
training
tSDO
MIN = tMOD + 9ns
MPR Command Timing
Multipurpose register recovery time
tMPR
tWR_MPR
MIN = 1CK
MIN = tMOD + AL + PL
CRC Error Reporting Timing
CK
Multipurpose register write recovery time
CRC error to ALERT_n latency
CRC ALERT_n pulse width
tCRC_ALERT
tCRC_ALERT_P
W
3
6
13
10
3
6
13
10
3
6
13
10
3
6
13
10
ns
CK
CA Parity Timing
Parity latency
PL
4
-
–
4
-
–
4
-
–
5
-
–
CK
CK
Commands uncertain to be executed dur-
ing this time
tPAR_UN-
KNOWN
PL
PL
PL
PL
Delay from errant command to ALERT_n tPAR_ALERT_O
–
48
–
PL +
6ns
–
56
–
P L +
6ns
–
64
–
PL +
6ns
–
72
–
PL +
6ns
CK
CK
CK
assertion
N
Pulse width of ALERT_n signal when as-
serted
tPAR_ALERT_P
W
96
112
128
144
Time from alert asserted until DES com-
mands required in persistent CA parity
mode
tPAR_ALERT_RS
P
43
50
57
64
CAL Timing
CS_n to command address latency
tCAL
tCALg
3
–
4
–
–
4
–
–
5
–
–
CK
CK
CS_n to command address latency in
gear-down mode
N/A
–
N/A
N/A
N/A
MPSM Timing
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
Min Max
DDR4-2133
Min Max
DDR4-2400
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Command path disable delay upopn
MPSM entry
tMPED
MIN = tMOD (MIN) + tCPDED (MIN)
MIN = tMOD (MIN) + tCPDED (MIN)
MIN = tCK - tCKSRX (MIN)
tXS (MIN)
CK
1
Valid clock requirement after MPSM
entry
tCKMPE
tCKMPX
tXMP
CK
CK
CK
CK
1
1
Valid clock requirement before MPSM
exit
Exit MPSM to commands not requiring a
locked DLL
Exit MPSM to commands requiring a
locked DLL
tXMPDLL
MIN = tXMP (MIN) + tXSDLL (MIN)
1
CS setup time to CKE
tMPX_S
tMPX_HH
tMPX_LH
MIN = tIS (MIN) + tIH (MIN)
MIN = tXP
ns
ns
ns
CS_n HIGH hold time to CKE rising edge
CS_n LOW hold time to CKE rising edge
12
tXMP-1
0ns
12
tXMP-1
0ns
12
tXMP-1
0ns
12
tXMP-1
0ns
Connectivity Test Timing
TEN pin HIGH to CS_n LOW – Enter CT
mode
tCT_Enable
200
–
200
–
200
–
200
–
ns
CS_n LOW and valid input to valid output
tCT_Valid
tCTCKE_Valid
–
200
–
–
200
–
–
200
–
–
200
–
ns
ns
CK_t, CK_c valid and CKE HIGH after TEN
goes HIGH
10
10
10
10
Calibration and VREFDQ Train Timing
ZQCL command: Long POWER-UP and
tZQinit
1024
–
–
–
1024
–
–
–
1024
512
–
–
–
1024
512
–
–
–
CK
CK
CK
calibration time
RESET operation
Normal opera-
tion
tZQoper
512
512
ZQCS command: Short calibration time
The VREF increment/decrement step time
tZQCS
128
128
128
128
VREF_time
tVREFDQE
MIN = 150ns
MIN = 150ns
Enter VREFDQ training mode to the first
write or VREFDQ MRS command delay
ns
ns
1
1
Exit VREFDQ training mode to the first
WRITE command delay
tVREFDQX
MIN = 150ns
Initialization and Reset Timing
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
Min Max
MIN = greater of 5CK or tRFC (MIN) + 10ns
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min Max
Min
Max
Unit
Notes
Exit reset from CKE HIGH to a valid com-
mand
tXPR
CK
1
RESET_L pulse low after power stable
RESET_L pulse low at power-up
tPW_REST_S
tPW_REST_L
tVDDPR
0.1
–
–
0.1
–
–
0.1
–
–
0.1
–
–
μs
μs
200
200
200
200
Begin power supply ramp to power sup-
plies stable
MIN = N/A; MAX = 200
ms
RESET_n LOW to power supplies stable
RESET_n LOW to I/O and RTT High-Z
tRPS
tIOZ
MIN = 0; MAX = 0
ns
ns
MIN = N/A; MAX = undefined
Refresh Timing
REFRESH-to-ACTIVATE
tRFC1
tRFC2
tRFC4
tRFC1
tRFC2
tRFC4
tRFC1
tRFC2
tRFC4
tREFI
MIN = 260
MIN = 160
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
12
or REFRESH command
period (all bank
groups)
4Gb
8Gb
MIN = 110
MIN = 350
MIN = 260
MIN = 160
MIN = 550
16Gb
MIN = 350
MIN = 260
Average periodic re-
fresh interval
-40°C ≤ TC ≤ 85°C
85°C < TC ≤ 95°C
MIN = N/A; MAX = 7.8
MIN = N/A; MAX = 3.9
MIN = N/A; MAX = 1.95
tREFI
tREFI
12
95°C < TC ≤
12
105°C
105°C < TC ≤
125°C
tREFI
MIN = N/A; MAX = 0.975
μs
12
1
Self Refresh Timing
Exit self refresh to commands not requir-
ing a locked DLL SRX to commands not
requiring a locked DLL in self refresh
abort
tXS
tXS_ABORT
MIN = tRFC + 10ns
MIN = tRFC4 + 10ns
ns
ns
1
1
Exit self refresh to ZQCL, ZQCS and MRS
(CL, CWL, WR, RTP and gear-down)
tXS_FAST
tXSDLL
MIN = tRFC4 + 10ns
MIN = tDLLK (MIN)
ns
Exit self refresh to commands requiring a
locked DLL
CK
1
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
Min Max
DDR4-1866
Min Max
DDR4-2133
Min Max
DDR4-2400
Parameter
Symbol
Min
Max
Unit
Notes
Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + 1nCK
CK
1
Minimum CKE low pulse width for self re- tCKESR_PAR
fresh entry to self refresh exit timing
when CA parity is enabled
MIN = tCKE (MIN) + 1nCK + PL
CK
1
Valid clocks after self refresh entry (SRE)
or power-down entry (PDE)
tCKSRE
MIN = greater of (5CK, 10ns)
CK
CK
1
1
Valid clock requirement after self refresh
entry or power-down when CA parity is
enabled
tCKSRE_PAR
MIN = greater of (5CK, 10ns) + PL
Valid clocks before self refresh exit (SRX)
or power-down exit (PDX), or reset exit
tCKSRX
MIN = greater of (5CK, 10ns)
CK
1
Power-Down Timing
MIN = greater of 4CK or 6ns
Exit power-down with DLL on to any val-
id command
tXP
CK
CK
1
1
1
Exit power-down with DLL on to any val-
id command when CA Parity is enabled.
tXP _PAR
MIN = (greater of 4CK or 6ns) + PL
CKE MIN pulse width
tCKE (MIN)
tCPDED
tPD
MIN = greater of 3CK or 5ns
CK
CK
CK
Command pass disable delay
4
–
4
–
4
–
4
–
Power-down entry to power-down exit
timing
MIN = tCKE (MIN); MAX = 9 × tREFI
Begin power-down period prior to CKE
registered HIGH
tANPD
PDE
WL - 1CK
CK
CK
CK
Power-down entry period: ODT either
synchronous or asynchronous
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
tANPD + tXSDLL
Power-down exit period: ODT either syn-
chronous or asynchronous
PDX
Power-Down Entry Minimum Timing
ACTIVATE command to power-down en-
try
tACTPDEN
1
1
1
–
–
–
1
1
1
–
–
–
2
2
2
–
–
–
2
2
2
–
–
–
CK
CK
PRECHARGE/PRECHARGE ALL command
to power-down entry
tPRPDEN
REFRESH command to power-down entry
MRS command to power-down entry
tREFPDEN
tMRSPDEN
CK
CK
MIN = tMOD (MIN)
1
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
Min Max
MIN = RL + 4 + 1
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min Max
Min
Max
Unit
Notes
READ/READ with auto precharge com-
mand to power-down entry
tRDPDEN
CK
1
WRITE command to power-down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPBC4DEN
tWRAPDEN
MIN = WL + 4 + tWR/tCK(AVG)
MIN = WL + 2 + tWR/tCK(AVG)
MIN = WL + 4 + WR + 1
CK
CK
CK
1
1
1
WRITE command to power-down entry
(BC4MRS)
WRITE with auto precharge command to
power-down entry (BL8OTF,
BL8MRS,BC4OTF)
WRITE with auto precharge command to tWRAPBC4DEN
power-down entry (BC4MRS)
MIN = WL + 2 + WR + 1
CK
1
ODT Timing
Direct ODT turn-on latency
Direct ODT turn-off latency
DODTLon
DODTLoff
tADC
WL - 2 = CWL + AL + PL - 2
WL - 2 = CWL + AL + PL - 2
CK
CK
CK
ns
RTT dynamic change skew
0.3
1
0.7
9
0.3
0.7
9
0.3
1
0.7
9
0.3
1
0.7
9
Asynchronous RTT(NOM) turn-on delay
(DLL off)
tAONAS
1
Asynchronous RTT(NOM) turn-off delay
(DLL off)
tAOFAS
1
9
1
9
1
9
1
9
ns
ODT HIGH time with WRITE command
and BL8
ODTH8 1tCK
ODTH8 2tCK
ODTH4 1tCK
ODTH4 2tCK
6
7
4
5
–
–
–
–
6
7
4
5
–
–
–
–
6
7
4
5
–
–
–
–
6
7
4
5
–
–
–
–
CK
ODT HIGH time without WRITE command
or with WRITE command and BC4
CK
Write Leveling Timing
First DQS_t, DQS_c rising edge after write
leveling mode is programmed
tWLMRD
tWLDQSEN
tWLS
40
–
–
–
40
–
–
–
40
25
–
–
–
40
25
–
–
–
CK
CK
DQS_t, DQS_c delay after write leveling
mode is programmed
25
25
Write leveling setup from rising CK_t,
CK_c crossing to rising DQS_t, DQS_c
crossing
0.13
0.13
0.13
0.13
CK(AV
G)
Table 157: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write leveling hold from rising DQS_t,
DQS_c crossing to rising CK_t, CK_c cross-
ing
tWLH
0.13
–
0.13
–
0.13
–
0.13
–
CK(AV
G)
Write leveling output delay
Write leveling output error
tWLO
tWLOE
0
0
9.5
2
0
0
9.5
2
0
0
9.5
2
0
0
9.5
2
ns
ns
Gear-Down Timing (Not Supported Below DDR4-2666)
Exit reset from CKE HIGH to a valid MRS
gear-down
tXPR_GEAR
N/A
N/A
N/A
N/A
N/A
CK
CK
CKE HIGH assert to gear-down enable
time)
tXS_GEAR
N/A
N/A
N/A
MRS command to sync pulse time
Sync pulse to first valid command
Gear-down setup time
tSYNC_GEAR
tCMD_GEAR
tGEAR_setup
tGEAR_hold
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
CK
CK
CK
CK
N/A
N/A
–
–
N/A
N/A
–
–
N/A
N/A
–
–
N/A
N/A
–
–
Gear-down hold time
1. Maximum limit not applicable.
Notes:
2. tCCD_L and tDLLK should be programmed according to the value defined per operating frequency.
3. Although unlimited row accesses to the same row is allowed within the refresh period, excessive row accesses to
the same row over a long term can result in degraded operation.
4. Data rate is greater than or equal to 1066 Mb/s.
5. RFUcorr
6. WRITE-to-READ when CRC and DM are both not enabled.
7. WRITE-to-READ delay when CRC and DM are both enabled.
8. The start of internal write transactions is defined as follows:
• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL
9. For these parameters, the device supports tnPARAM [nCK] = RU{tPARAM [ns]/tCK(AVG) [ns]}, in clock cycles, assum-
ing all input clock jitter specifications are satisfied.
10. When operating in 1tCK WRITE preamble mode.
11. When operating in 2tCK WRITE preamble mode.
12. When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL"
added to tRFC refresh time.
13. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
dress may result in reduction of the product lifetime and/or reduction in data retention ability.
14. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
15. JEDEC specifies a minimum of five clocks.
16. The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZ(DQS) MAX on
the right side.
17. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which
should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with
a driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ.
18. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total
limit.
19. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate
spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term
jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN.
20. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at
targeted speed bin.
21. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side.
See figure in the Clock to Data Strobe Relationship section. Boundary of DQS Low-Z occur one cycle earlier in 2tCK
toggle mode, which is illustrated in the READ Preamble section.
22. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of DQS differential signal
cross-point.
Electrical Characteristics and AC Timing Parameters – DDR4-2666 through DDR4-3200
Table 158: Electrical Characteristics and AC Timing Parameters
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Clock Timing
Clock period average (DLL off mode)
Clock period average
tCK (DLL_OFF)
tCK (AVG,
DLL_ON)
8
20
8
20
8
20
ns
ns
0.75
1.9
0.682
1.9
0.625
1.9
14
High pulse width average
Low pulse width average
tCH (AVG)
tCL (AVG)
tJITper_tot
tJITper_dj
tJITper,lck
tCK (ABS)
0.48
0.48
–38
–19
–30
0.52
0.52
38
0.48
0.48
-34
0.52
0.52
34
0.48
0.48
–32
–16
–25
0.52
0.52
32
CK
CK
ps
ps
ps
ps
Clock period jitter
Total
Deterministic
DLL locking
19
-17
17
16
30
-27
27
25
Clock absolute period
MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX +
tJITper_tot MAX
Clock absolute high pulse width
(includes duty cycle jitter)
tCH (ABS)
tCL (ABS)
0.45
–
0.45
–
0.45
–
tCK
(AVG)
tCK
(AVG)
Clock absolute low pulse width
(includes duty cycle jitter)
0.45
–
0.45
–
0.45
–
Cycle-to-cycle jitter
Total
tJITcc _tot
tJITcc,lck
75
60
68
55
62
50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DLL locking
Cumulative error across 2 cycles
tERR2per
tERR3per
tERR4per
tERR5per
tERR6per
tERR7per
tERR8per
tERR9per
tERR10per
tERR11per
tERR12per
tERRnper
–55
–66
–73
–78
–83
–87
–91
–94
–96
–99
–101
55
66
73
78
83
87
91
94
96
99
101
-50
-60
-66
-71
-75
-79
-83
-85
-88
-90
-92
50
60
66
71
75
79
83
85
88
90
92
–46
–55
–61
–65
–69
–73
–76
–78
–80
–83
–84
46
55
61
65
69
73
76
78
80
83
84
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 13, 14 . . . 49,
50 cycles
tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN
tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
Min Max
DQ Input Timing
DDR4-2933
DDR4-3200
Min Max
Reserved
Min Max
Parameter
Symbol
Min Max
Unit
Notes
Data setup time to
DQS_t, DQS_c
Base (calibrated
VREF
tDS
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
–
)
Non-calibrated
VREF
tPDA_S
tDH
minimum of 0.5ui
UI
–
Data hold time from
DQS_t, DQS_c
Base (calibrated
Refer to DQ Input Receiver Specification section
(approximately 0.15tCK to 0.28tCK )
VREF
)
Non-calibrated
VREF
tPDA_H
tDIPW
minimum of 0.5UI
UI
UI
DQ and DM minimum data pulse width
for each input
0.58
–
0.58
–
0.58
–
–
DQ Output Timing (DLL enabled)
DQS_t, DQS_c to DQ skew, per group, per
access
tDQSQ
–
0.18
–
0.19
0.22
UI
DQ output hold time from DQS_t, DQS_c
Data Valid Window per device: tQH -
tDQSQ each device’s output per IU
tQH
tDVWd
0.74
0.64
–
–
0.74
0.64
–
–
0.74
0.64
–
–
UI
UI
Data Valid Window per device, per pin:
tQH - tDQSQ each device’s output per IU
tDVWp
0.72
–
0.72
–
0.72
–
UI
DQ Low-Z time from CK_t, CK_c
DQ High-Z time from CK_t, CK_c
tLZDQ
tHZDQ
–310
–
170
170
–280
–
165
165
–250
–
160
160
ps
ps
DQ Strobe Input Timing
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 1tCKpreamble
tDQSS1ck
tDQSS2ck
tDQSL
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
–0.27
–0.50
0.46
0.27
0.50
0.54
0.54
–
CK
CK
CK
CK
CK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge for 2tCKpreamble
DQS_t, DQS_c differential input low pulse
width
DQS_t, DQS_c differential input high
pulse width
tDQSH
tDSS
0.46
0.46
0.46
DQS_t, DQS_c falling edge setup to CK_t,
CK_c rising edge
0.18
0.18
0.18
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
DQS_t, DQS_c falling edge hold from
CK_t, CK_c rising edge
tDSH
0.18
–
0.18
–
0.18
–
CK
DQS_t, DQS_c differential WRITE pream-
ble for 1tCKpreamble
tWPRE1ck
tWPRE2ck
tWPST
0.9
1.8
–
–
–
0.9
1.8
–
–
–
0.9
1.8
–
–
–
CK
CK
CK
DQS_t, DQS_c differential WRITE pream-
ble for 2tCKpreamble
DQS_t, DQS_c differential WRITE postam-
ble
0.33
0.33
0.33
DQS Strobe Output Timing (DLL enabled)
DQS_t, DQS_c rising edge output access
time from rising CK_t, CK_c
tDQSCK
tDQSCKi
tQSH
–170
170
270
–
–165
165
265
–
–160
–
160
260
–
ps
ps
DQS_t, DQS_c rising edge output var-
iance window per DRAM
–
–
DQS_t, DQS_c differential output high
time
0.40
0.40
0.40
0.40
0.40
0.40
CK
CK
DQS_t, DQS_c differential output low
time
tQSL
–
–
–
DQS_t, DQS_c Low-Z time (RL - 1)
tLZDQS
tHZDQS
tRPRE1ck
–310
–
170
170
–
–280
–
165
165
–
–250
–
160
160
–
ps
ps
DQS_t, DQS_c High-Z time (RL + BL/2)
DQS_t, DQS_c differential READ pream-
ble for 1tCKpreamble
0.9
0.9
0.9
CK
DQS_t, DQS_c differential READ pream-
ble for 2tCKpreamble
tRPRE2ck
tRPST
1.8
–
–
1.8
–
–
1.8
–
–
CK
CK
DQS_t, DQS_c differential READ postam-
ble
0.33
0.33
0.33
Command and Address Timing
DLL locking time
tDLLK
tIS
tISVREF
854
55
–
–
–
940
48
–
–
–
1024
40
–
–
–
CK
ps
ps
2, 3
CMD, ADDR setup time Base
to CK_t, CK_c refer-
enced to VIH(AC) and
VIL(AC) levels
VREFCA
145
138
130
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max
Parameter
Symbol
tIH
Min
80
Max
Min
73
Max
Min
65
Max
Unit
ps
Notes
CMD, ADDR hold time Base
–
–
–
–
–
–
tIHVREF
ps
to CK_t, CK_c refer-
enced to VIH(DC) and
VIL(DC) levels
VREFCA
145
138
130
CTRL, ADDR pulse width for each input
tIPW
tRCD
385
–
365
–
350
–
ps
ns
ACTIVATE to internal READ or WRITE de-
lay
See Speed Bin Tables for tRCD
PRECHARGE command period
tRP
tRAS
See Speed Bin Tables for tRP
See Speed Bin Tables for tRAS
ns
ns
ACTIVATE-to-PRECHARGE command peri-
od
13
13
1
ACTIVATE-to-ACTIVATE or REF command
period
tRC
See Speed Bin Tables for tRC
ns
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1/2KB page
size
tRRD_S
(1/2KB)
MIN = greater
MIN = greater
MIN = greater
CK
of 4CK or 3.0ns of 4CK or 2.7ns of 4CK or 2.5ns
ACTIVATE-to-ACTIVATE command period
to different bank groups for 1KB page
size
tRRD_S
(1KB)
MIN = greater
of 4CK or 3.0ns of 4CK or 2.7ns of 4CK or 2.5ns
MIN = greater
MIN = greater
CK
CK
1
1
ACTIVATE-to-ACTIVATE command period
to different bank groups for 2KB page
size
tRRD_S
(2KB)
MIN = greater
of 4CK or 5.3ns of 4CK or 5.3ns of 4CK or 5.3ns
MIN = greater
MIN = greater
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1/2KB page size
tRRD_L
(1/2KB)
tRRD_L
(1KB)
tRRD_L
(2KB)
tFAW
MIN = greater
of 4CK or 4.9ns of 4CK or 4.9ns of 4CK or 4.9ns
MIN = greater MIN = greater MIN = greater
of 4CK or 4.9ns of 4CK or 4.9ns of 4CK or 4.9ns
MIN = greater MIN = greater MIN = greater
of 4CK or 6.4ns of 4CK or 6.4ns of 4CK or 6.4ns
MIN = greater
MIN = greater
CK
CK
CK
ns
1
1
1
ACTIVATE-to-ACTIVATE command period
to same bank groups for 1KB page size
ACTIVATE-to-ACTIVATE command period
to same bank groups for 2KB page size
Four ACTIVATE windows for 1/2KB page
size
MIN = greater
MIN = greater
of 16CK or
10.9ns
MIN = greater
(1/2KB)
of 16CK or 12ns
of 16CK or 10ns
Four ACTIVATE windows for 1KB page
size
tFAW
(1KB)
tFAW
(2KB)
MIN = greater
MIN = greater
MIN = greater
ns
ns
of 20CK or 21ns of 20CK or 21ns of 20CK or 21ns
MIN = greater MIN = greater MIN = greater
of 28CK or 30ns of 28CK or 30ns of 28CK or 30ns
Four ACTIVATE windows for 2KB page
size
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
Min Max
DDR4-3200
Min Max
Reserved
Min Max
Parameter
Symbol
tWR
tWR2
Min
Max
Unit
ns
Notes
5, 10, 1
5, 11, 1
6, 10, 1
WRITE recovery time
MIN = 15ns
MIN = 1CK + tWR
MIN = tWR + greater of (5CK or 3.75ns)
CK
WRITE recovery time when CRC and DM
are both enabled
tWR_CRC_DM
CK
WRITE recovery time when CRC and DM
are both enabled
tWR_CRC_DM2
MIN = 1CK + tWR_CRC_DM
CK
6, 11, 1
Delay from start of internal WRITE trans-
action to internal READ command – Same
bank group
tWTR_L
tWTR_L2
MIN = greater of 4CK or 7.5ns
MIN = 1CK + tWTR_L
CK
CK
5, 10, 1
5, 11, 1
Delay from start of internal WRITE trans- tWTR_L_CRC_D
MIN = tWTR_L + greater of (5CK or 3.75ns)
MIN = 1CK + tWTR_L_CRC_DM
MIN = greater of (2CK or 2.5ns)
MIN = 1CK + tWTR_S
CK
CK
CK
CK
CK
CK
6, 10, 1
6, 11, 1
action to internal READ command – Same
bank group when CRC and DM are both
enabled
M
tWTR_L_CRC_D
M2
Delay from start of internal WRITE trans-
action to internal READ command – Dif-
ferent bank group
tWTR_S
5, 7, 8,
10, 1
tWTR_S2
5, 7, 8,
11, 1
Delay from start of internal WRITE trans- tWTR_S_CRC_D
MIN = tWTR_S + greater of (5CK or 3.75ns)
MIN = 1CK + tWTR_S_CRC_DM
MIN = greater of 4CK or 7.5ns
6, 7, 8,
10, 1
action to internal READ command – Dif-
ferent bank group when CRC and DM are
both enabled
M
tWTR_S_CRC_D
M2
6, 7, 8,
11, 1
READ-to-PRECHARGE time
tRTP
CK
CK
1
CAS_n-to-CAS_n command delay to dif-
ferent bank group
tCCD_S
4
–
–
4
–
4
–
CAS_n-to-CAS_n command delay to same
bank group
tCCD_L
MIN =
greater
of 4CK
or 5ns
MIN =
greater
of 4CK
or 5ns
–
MIN =
greater
of 4CK
or 5ns
–
CK
15
Auto precharge write recovery + pre-
charge time
tDAL (MIN)
MIN = WR + ROUNDUPtRP/tCK (AVG); MAX = N/A
CK
MRS Command Timing
10
MRS command cycle time
tMRD
tMRD_PDA
tMRD_CAL
9
–
–
10
–
CK
CK
MRS command cycle time in PDA mode
MRS command cycle time in CAL mode
MIN = greater of (16nCK, 10ns)
MIN = tMOD + tCAL
1
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
Min Max
DDR4-2933
Min Max
DDR4-3200
Min Max
Reserved
Min Max
Parameter
Symbol
Unit
Notes
MRS command update delay in PDA
mode
tMOD
MIN = greater of (24nCK, 15ns)
CK
1
MRS command update delay
tMOD_PDA
tMOD_CAL
MIN = tMOD
MIN = tMOD + tCAL
CK
CK
MRS command update delay in CAL
mode
MRS commandto DQS drive in preamble
training
tSDO
MIN = tMOD + 9ns
MPR Command Timing
Multipurpose register recovery time
tMPR
tWR_MPR
MIN = 1nCK
MIN = tMOD + AL + PL
CRC Error Reporting Timing
CK
Multipurpose register write recovery time
CRC error to ALERT_n latency
CRC ALERT_n pulse width
tCRC_ALERT
tCRC_ALERT_P
W
3
6
13
10
3
6
13
10
3
6
13
10
ns
CK
CA Parity Timing
Parity latency
PL
5
–
–
6
–
–
6
–
–
CK
CK
Commands uncertain to be executed dur-
ing this time
tPAR_UN-
KNOWN
PL
PL
PL
Delay from errant command to ALERT_n tPAR_ALERT_O
–
80
–
PL +
6ns
–
88
–
PL +
6ns
–
96
–
PL +
6ns
CK
CK
CK
assertion
N
Pulse width of ALERT_n signal when as-
serted
tPAR_ALERT_P
W
160
176
192
Time from alert asserted until DES com-
mands required in persistent CA parity
mode
tPAR_ALERT_RS
P
71
78
85
CAL Timing
CS_n to command address latency
tCAL
tCALg
5
6
–
–
6
8
–
–
6
8
–
–
CK
CK
CS_n to command address latency in
gear-down mode
MPSM Timing
MIN = tMOD (MIN) + tCPDED (MIN)
Command path disable delay upopn
MPSM entry
tMPED
CK
1
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
Min Max
DDR4-3200
Min Max
Reserved
Min Max
Parameter
Symbol
Min
Max
Unit
Notes
Valid clock requirement after MPSM
entry
tCKMPE
MIN = tMOD (MIN) + tCPDED (MIN)
MIN = tCK - tCKSRX (MIN)
tXS (MIN)
CK
1
Valid clock requirement before MPSM
exit
tCKMPX
tXMP
CK
CK
CK
1
1
Exit MPSM to commands not requiring a
locked DLL
Exit MPSM to commands requiring a
locked DLL
tXMPDLL
MIN = tXMP (MIN) + tXSDLL (MIN)
CS setup time to CKE
tMPX_S
tMPX_HH
tMPX_LH
MIN = tIS (MIN) + tIH (MIN)
MIN = tXP
ns
ns
ns
CS_n HIGH hold time to CKE rising edge
CS_n LOW hold time to CKE rising edge
12
tXMP-1
0ns
12
tXMP-1
0ns
12
tXMP-1
0ns
Connectivity Test Timing
TEN pin HIGH to CS_n LOW – Enter CT
mode
tCT_Enable
200
–
200
–
200
–
ns
CS_n LOW and valid input to valid output
tCT_Valid
tCTCKE_Valid
–
200
–
–
200
–
–
200
–
ns
ns
CK_t, CK_c valid and CKE HIGH after TEN
goes HIGH
10
10
10
Calibration and VREFDQ Train Timing
ZQCL command: Long POWER-UP and
tZQinit
1024
–
–
–
1024
–
–
–
1024
512
–
–
–
CK
CK
CK
calibration time
RESET operation
Normal opera-
tion
tZQoper
512
512
ZQCS command: Short calibration time
The VREF increment/decrement step time
tZQCS
128
128
128
VREF_time
tVREFDQE
MIN = 150ns
MIN = 150ns
Enter VREFDQ training mode to the first
write or VREFDQ MRS command delay
ns
ns
1
1
Exit VREFDQ training mode to the first
WRITE command delay
tVREFDQX
MIN = 150ns
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid com-
mand
tXPR
MIN = greater of 5CK or tRFC (MIN) + 10ns
CK
μs
1
RESET_L pulse low after power stable
tPW_REST_S
0.1
–
0.1 0.1
–
–
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max
Parameter
Symbol
tPW_REST_L
tVDDPR
Min
Max
Min
Max
Min
Max
Unit
μs
Notes
RESET_L pulse low at power-up
200
–
200
–
200
–
Begin power supply ramp to power sup-
plies stable
MIN = N/A; MAX = 200
ms
RESET_n LOW to power supplies stable
RESET_n LOW to I/O and RTT High-Z
tRPS
tIOZ
MIN = 0; MAX = 0
ns
ns
MIN = N/A; MAX = undefined
Refresh Timing
REFRESH-to-ACTIVATE
tRFC1
tRFC2
tRFC4
tRFC1
tRFC2
tRFC4
tRFC1
tRFC2
tRFC4
tREFI
MIN = 260
MIN = 160
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
1, 12
12
or REFRESH command
period (all bank
groups)
4Gb
8Gb
MIN = 110
MIN = 350
MIN = 260
MIN = 160
MIN = 550
16Gb
MIN = 350
MIN = 260
Average periodic re-
fresh interval
-40°C ≤ TC ≤ 85°C
85°C < TC ≤ 95°C
MIN = N/A; MAX = 7.8
MIN = N/A; MAX = 3.9
MIN = N/A; MAX = 1.95
tREFI
tREFI
12
95°C < TC ≤
12
105°C
105°C < TC ≤
125°C
tREFI
MIN = N/A; MAX = 0.975
μs
12
1
Self Refresh Timing
Exit self refresh to commands not requir-
ing a locked DLL SRX to commands not
requiring a locked DLL in self refresh
abort
tXS
tXS_ABORT
MIN = tRFC + 10ns
MIN = tRFC4 + 10ns
ns
ns
1
1
Exit self refresh to ZQCL, ZQCS and MRS
(CL, CWL, WR, RTP and gear-down)
tXS_FAST
tXSDLL
MIN = tRFC4 + 10ns
MIN = tDLLK (MIN)
ns
Exit self refresh to commands requiring a
locked DLL
CK
1
1
Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + 1nCK
CK
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
Min Max
DDR4-2933
Min Max
DDR4-3200
Min Max
Reserved
Min Max
Parameter
Symbol
Unit
Notes
Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing
when CA parity is enabled
tCKESR_par
MIN = tCKE (MIN) + 1nCK + PL
CK
1
Valid clocks after self refresh entry (SRE)
or power-down entry (PDE)
tCKSRE
MIN = greater of (5CK, 10ns)
CK
CK
1
1
Valid clock requirement after self refresh
entry or power-down when CA parity is
enabled
tCKSRE_par
MIN = greater of (5CK, 10ns) + PL
Valid clocks before self refresh exit (SRX)
or power-down exit (PDX), or reset exit
tCKSRX
MIN = greater of (5CK, 10ns)
CK
1
Power-Down Timing
MIN = greater of 4CK or 6ns
Exit power-down with DLL on to any val-
id command
tXP
CK
CK
1
1
Exit precharge power-down with DLL fro-
zen to commands not requiring a locked
DLL when CA Parity is enabled.
tXP _PAR
MIN = (greater of 4CK or 6ns) + PL
CKE MIN pulse width
tCKE (MIN)
tCPDED
tPD
MIN = greater of 3CK or 5ns
CK
CK
CK
1
Command pass disable delay
4
–
4
–
4
–
Power-down entry to power-down exit
timing
MIN = tCKE (MIN); MAX = 9 × tREFI
Begin power-down period prior to CKE
registered HIGH
tANPD
PDE
WL - 1CK
CK
CK
CK
Power-down entry period: ODT either
synchronous or asynchronous
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
tANPD + tXSDLL
Power-down exit period: ODT either syn-
chronous or asynchronous
PDX
Power-Down Entry Minimum Timing
ACTIVATE command to power-down en-
try
tACTPDEN
2
2
2
–
–
–
2
2
2
–
–
–
2
2
2
–
–
–
CK
CK
PRECHARGE/PRECHARGE ALL command
to power-down entry
tPRPDEN
REFRESH command to power-down entry
MRS command to power-down entry
tREFPDEN
tMRSPDEN
CK
CK
MIN = tMOD (MIN)
1
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
Min Max
MIN = RL + 4 + 1
DDR4-3200
Reserved
Min Max
Parameter
Symbol
Min
Max
Min Max
Unit
Notes
READ/READ with auto precharge com-
mand to power-down entry
tRDPDEN
CK
1
WRITE command to power-down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPBC4DEN
tWRAPDEN
MIN = WL + 4 + tWR/tCK(AVG)
MIN = WL + 2 + tWR/tCK(AVG)
MIN = WL + 4 + WR + 1
CK
CK
CK
1
1
1
WRITE command to power-down entry
(BC4MRS)
WRITE with auto precharge command to
power-down entry (BL8OTF,
BL8MRS,BC4OTF)
WRITE with auto precharge command to tWRAPBC4DEN
power-down entry (BC4MRS)
MIN = WL + 2 + WR + 1
CK
1
ODT Timing
Direct ODT turn-on latency
Direct ODT turn-off latency
DODTLon
DODTLoff
tADC
WL - 2 = CWL + AL + PL - 2
WL - 2 = CWL + AL + PL - 2
CK
CK
CK
ns
RTT dynamic change skew
0.3
1
0.7
9
0.3
0.7
9
0.3
1
0.7
9
Asynchronous RTT(NOM) turn-on delay
(DLL off)
tAONAS
1
Asynchronous RTT(NOM) turn-off delay
(DLL off)
tAOFAS
1
9
1
9
1
9
ns
ODT HIGH time with WRITE command
and BL8
ODTH8 1tCK
ODTH8 2tCK
ODTH4 1tCK
ODTH4 2tCK
6
7
4
5
–
–
–
–
6
7
4
5
–
–
–
–
6
7
4
5
–
–
–
–
CK
ODT HIGH time without WRITE command
or with WRITE command and BC4
CK
Write Leveling Timing
First DQS_t, DQS_c rising edge after write
leveling mode is programmed
tWLMRD
tWLDQSEN
tWLS
40
–
–
–
40
–
–
–
40
25
–
–
–
CK
CK
CK
DQS_t, DQS_c delay after write leveling
mode is programmed
25
25
Write leveling setup from rising CK_t,
CK_c crossing to rising DQS_t, DQS_c
crossing
0.13
0.13
0.13
Table 158: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
DDR4-2933
DDR4-3200
Reserved
Min Max
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write leveling hold from rising DQS_t,
DQS_c crossing to rising CK_t, CK_c cross-
ing
tWLH
0.13
–
0.13
–
0.13
–
CK
Write leveling output delay
Write leveling output error
tWLO
tWLOE
0
0
9.5
2
0
0
9.5
2
0
0
9.5
2
ns
ns
Gear-Down Timing
Exit reset from CKE HIGH to a valid MRS
gear-down
tXPR_GEAR
tXS_GEAR
tXPR
tXPR
tXPR
tXS
CK
CK
CKE HIGH assert to gear-down enable
time)
tXS
tXS
MRS command to sync pulse time
Sync pulse to first valid command
Gear-down setup time
tSYNC_GEAR
tCMD_GEAR
tGEAR_setup
tGEAR_hold
tMOD + 4CK
tMOD
tMOD + 4CK
tMOD
tMOD + 4CK
tMOD
CK
CK
CK
CK
2CK
2CK
–
–
2CK
2CK
–
–
2CK
2CK
–
–
Gear-down hold time
1. Maximum limit not applicable.
Notes:
2. tCCD_L and tDLLK should be programmed according to the value defined per operating frequency.
3. Data rate is greater than or equal to 1066 Mb/s.
4. RFU
5. WRITE-to-READ when CRC and DM are both not enabled.
6. WRITE-to-READ delay when CRC and DM are both enabled.
7. The start of internal write transactions is defined as follows:
• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL
8. For these parameters, the device supports tnPARAM [nCK] = RU{tPARAM [ns]/tCK(AVG) [ns]}, in clock cycles, assum-
ing all input clock jitter specifications are satisfied.
9. Although unlimited row accesses to the same row is allowed within the refresh period, excessive row accesses to
the same row over a long term can result in degraded operation.
10. When operating in 1tCK WRITE preamble mode.
11. When operating in 2tCK WRITE preamble mode.
12. When CA parity mode is selected and the DLLoff mode is used, each REF command requires an additional "PL"
added to tRFC refresh time.
13. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
dress may result in reduction of the product lifetime and/or reduction in data retention ability.
14. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables.
15. JEDEC specifies a minimum of five clocks.
16. The maximum read postamble is bound by tDQSCK(MIN) plus tQSH(MIN) on the left side and tHZ(DQS)MAX on the
right side.
17. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which
should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with a
driver impedance of 34 ohms and an effective test load of 50 ohms to VTT = VDDQ
.
18. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should focus on meeting the total
limit.
19. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate
spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term
jitter component; however, clock rate below tCK (AVG) MIN.
20. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the applicable clocks required at
targeted speed bin.
21. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side.
See figure in Clock to Data Strobe Relationship. Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle
mode which is illustrated in READ Preamble.
22. DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS differential signal
cross-point.
8Gb: x8, x16 Automotive DDR4 SDRAM
Revision History
Revision History
Rev. C – 3/17
• Added Functional Block Diagra0 for 512 Meg x 8 and for 25± Meg x 1±
• Updated Power-Up and Initialization Sequence in RESET and Initialization Procedure
section
• Updated WR (WRITE recovery)/RTP (READ-to-PRECHARGE) in MR6 Register Defini-
tion table: Added 1661 = 28/14 clocks; Changed to 1616 through 1111 = Reserved
• Updated note 2 for MR6 Register Definition table
• Updated Input Clock Frequency Change section
• Updated TCR Mode – Nor0al Te0perature Range section and TCR Mode – Extended
Te0perature Range section in Te0perature-Controlled Refresh Mode
• Updated Current Specification _ Li0its tables
• Added Connectivity Test Mode Output Driver Electrical Characteristics section
• Added note 18 to note 22 to Electrical Characteristics and AC Ti0ing Para0eters table
in Electrical Characteristics and AC Ti0ing Para0eters
Rev. B – 9/16
Rev. A – 6/16
• Updated legal status to Production
• Initial release
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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
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