MT46V32M8FJ-6 [MICRON]
DOUBLE DATA RATE DDR SDRAM; 双倍数据速率DDR SDRAM
| 型号： | MT46V32M8FJ-6 |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | DOUBLE DATA RATE DDR SDRAM |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY‡
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
MT46V64M4 –16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
DOUBLE DATA RATE
(DDR) SDRAM
For the latest data sheet revisions, please refer to the Micron
Website:www.micron.com/dramds
FEATURES
DDR333COMPATIBILITY
• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±±.2V, VDDQ = +2.5V ±±.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
t
support concurrent auto-precharge and RAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (tREFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
Architecture
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
RefreshCount
8K
8K
8K
RowAddressing
BankAddressing
ColumnAddressing
8K (A0–A12)
4(BA0,BA1)
2K (A0–A9, A11)
8K (A0–A12)
4(BA0,BA1)
1K (A0–A9)
8K (A0–A12)
4(BA0,BA1)
512(A0– A8)
• 2.5V I/O (SSTL_2 compatible)
t
• RAS lockout (tRAP = tRCD)
• Backwards compatible with DDR2±± and DDR266
OPTIONS
• Configuration
PART NUMBER
KEYTIMINGPARAMETERS3
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package
64M4
32M8
16M16
SPEED
GRADE CL = 21
CLOCKRATE
DATA-OUT ACCESS DQS-DQ
CL = 2.51 WINDOW2 WINDOW SKEW
-6
-6T
-75Z
133MHz 167MHz
133MHz 167MHz
133MHz 133MHz
2.15ns
2.0ns
2.5ns
0.70ns +0.35ns
0.75ns +0.45ns
0.75ns +0.50ns
66-Pin TSOP (OCPL)
6±-Ball FBGA (16x9mm)
• Timing - Cycle Time
TG
FJ
NOTE: 1. CL = CAS (Read) Latency
6ns @ CL = 2.5 (DDR333B–FBGA)1
6ns @ CL = 2.5 (DDR333B–TSOP)1
7.5ns @ CL = 2 (DDR266A)2
• Self Refresh
-6
-6T
-75Z
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
Standard
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
1
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRONWITHOUTNOTICE.PRODUCTSAREONLYWARRANTEDBYMICRONTOMEETMICRON’SPRODUCTIONANDDATASHEETSPECIFICATIONS.
PRELIMINARY
256Mb : x4, x8, x16
DDR333 SDRAM Ad d e n d u m
FBGA 60-BALL PACKAGE DIMENSION
FBGA PACKAGE PINOUT
0.850 ±0.075
x4 (Top View)
SEATING PLANE
1
2
3
4
5
6
7
8
9
C
A
B
C
D
E
A
B
C
D
E
V
SS
Q
NC
V
DD
DQ0
NC
NC
VSS
DQ3
NC
DQ2
DQS
DM
CK#
CKE
A9
VDDQ
0.10
C
NC
NC
NC
NC
V
V
V
V
DD
SS
DD
SS
SS
Q
Q
Q
Q
V
V
V
V
SS
DD
SS
DD
DD
Q
Q
Q
Q
NC
NC
NC
NC
A13
6.40
1.80
CTR
DQ1
NC
NC
WE#
RAS#
BA1
A0
61X 0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.40
BALL A9
0.80 TYP
PIN A1 ID
1.20 MAX
V
V
V
REF
F
F
CK
A12
A11
A8
CAS#
CS#
BA0
A10
A1
G
H
G
H
BALL A1
J
J
8.00 ±0.05
K
K
A7
A5
A6
L
L
A2
M
A4
VSS
M
A3
VDD
C
11.00
L
16.00 ±0.10
1.00
TYP
5.50 ±0.05
x8 (Top View)
1
SS
2
3
4
5
6
7
8
9
Bottom View
C
L
A
B
C
D
E
A
B
C
D
E
V
Q
DQ7
V
DD
DQ1
DQ2
DQ3
NC
DQ0
VSSQ
VSS
DQ6
DQ5
DQ4
DQS
DM
CK#
CKE
A9
V
DD
NC
NC
NC
NC
A13
Q
NC
NC
NC
NC
V
V
V
V
DD
SS
DD
SS
SS
Q
Q
Q
Q
3.20 ±0.05
V
V
V
DD
Q
Q
Q
4.50 ±0.05
9 .00 ±0.10
SS
SUBSTRATE: PLASTIC LAMINATE
DD
V
NC
VDD
F
VREF
F
MOLD COMPOUND: EPOXY NOVOLAC
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
CK
A12
A11
A8
A6
A4
CAS#
CS#
BA0
A10
A1
WE#
RAS#
BA1
A0
G
H
G
H
J
J
FBGA PACKAGE MARKING
K
K
A7
A5
VSS
L
L
A2
Due to th e ph ysical size of th e FBGA package, th e full
orderin g part n um ber is n ot prin ted on th e package.
In stead th e followin g package code is utilized.
M
M
A3
VDD
Top m ark con tain s five fields
12345
x16 (Top View)
1
SS
2
3
4
5
6
7
8
9
• Field 1 (Product Fam ily)
DRAM
A
B
C
D
E
A
B
C
D
E
V
Q
DQ15
DD
V
DD
DQ2
DQ4
DQ6
LDQS
LDM
WE#
RAS#
BA1
A0
DQ0
VSSQ
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CK#
CKE
A9
V
DDQ
D
Z
DQ14
DQ12
DQ10
DQ8
V
V
V
V
Q
Q
Q
Q
DQ1
DQ3
DQ5
DQ7
A13
DRAM - ES
SS
V
V
V
DD
Q
Q
Q
DD
SS
• Field 2 (Product Type)
SS
DD
2.5 Volt, DDR SDRAM, 60-ball
L
VSS
VDD
F
VREF
F
CK
A12
A11
A8
A6
A4
CAS#
CS#
BA0
A10
A1
G
H
G
H
• Field 3 (Width )
x4 devices
B
C
D
J
J
x8 devices
x16 devices
K
K
A7
A5
VSS
L
L
A2
M
M
A3
VDD
• Field 4 (Den sity / Size)
256Mb
H
• Filed 5 (Speed Grade)
-6
J
-75Z
-75
-8
P
F
C
Exa m p le t o p m a rk fo r a MT46V32M4FJ-6: DLBFJ
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
2
PRELIMINARY
256Mb : x4, x8, x16
DDR333 SDRAM Ad d e n d u m
66-PIN TSOP PACKAGE DIMENSION
66-PIN TSOP PACKAGE PIN ASSIGMENT
SEE DETAIL A
22.22 ± 0.08
(TOP VIEW)
0.71
0.65 TYP
0.10 (2X)
0.32 ± .075 TYP
x8
x4
x4
x8
x16
x16
V
NC
DD
V
DQ7
VSS
NC
DQ6
VDD
NC
DQ5
VSS
NC
DQ4
VDD
NC
NC
VSS
DQS
DNU
SS
V
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
SS
V
DQ0
DD
V
DQ0
DD
1
2
3
4
5
6
7
8
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
V
DD
Q
Q
V
DD
Q
V
DD
Q
NC
DQ0
VSS
NC
NC
NC
DQ1
VSS
NC
DQ2
DQ1
DQ2
VssQ
DQ3
DQ4
11.76 ±0.10
Q
Q
Q
10.16 ±0.08
V
DD
Q
Q
V
DD
Q
V
DD
Q
9
NC
DQ1
VSS
NC
NC
NC
DQ3
VSS
NC
NC
DQ5
DQ6
VssQ
DQ7
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Q
Q
Q
+0.03
-0.02
PIN #1 ID
0.15
V
DD
Q
NC
NC
Q
V
DD
Q
V
DD
Q
NC LDQS
NC NC
VDD
VDD
VREF
VREF
V
DD
DNU
LDM
WE#
CAS#
RAS#
CS#
VREF
DNU
NC
WE#
CAS#
RAS#
CS#
VSS
VSS
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
VSS
0.10
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
1.20 MAX
GAGE PLANE
NC
NC
BA0
BA1
0.25
BA0
BA1
A10/AP
A0
A10/AP A10/AP
A0
A1
A2
A3
A0
A1
A2
A3
A1
A2
A3
+0.10
-0.05
0.10
A4
VSS
A4
VSS
A4
VSS
0.80 TYP
VDD
VDD
VDD
0.50 ±0.10
DETAIL A
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
3
PRELIMINARY
256Mb : x4, x8, x16
DDR333 SDRAM Ad d e n d u m
PIN DESCRIPTIONS
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL TYPE
DESCRIPTION
G2, G3
45, 46
CK, CK#
Input Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
H3
44
CKE
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.
H8
24
CS#
Input Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
H7, G8, G7 23, 22, 21 RAS#,CAS#, Input
WE#
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
3F
F7, 3F
47
20, 47
DM
LDM, UDM
Input Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8
J8,J7
26, 27
29-32
BA0, BA1
Input Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
K7, L8, L7
M8, M2, L3 32, 35, 36
L2, K3, K2 36, 38, 39
J3, K8, J2
H2
A0, A1, A2
A3, A4, A5
A6, A7, A8
Input
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.
40, 29, 41 A9, A10, A11
42 A12
(continued on next page)
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
4
©2001, Micron Technology, Inc.
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PIN DESCRIPTIONS (continued)
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE DESCRIPTION
A8, B9, B7
C9, C7, D9
D7, E9, E1
D3, D1, C3
2, 4, 5,
7, 8, 10
11, 13, 54
56, 57, 59
DQ0-2
DQ3-5
DQ6-8
DQ9-11
I/O
Data Input/Output: Data bus for x16
C1, B3, B1, 60, 62, 63, DQ12-14
A2
65
DQ15
A8, B7, C7,
D7, D3, C3, 11, 56, 59
B3, A2
2, 5, 8,
DQ0-2
DQ3-5
DQ6-7
I/O
Data Input/Output: Data bus for x8
62, 65
B7, D7, D3,
B3
5, 11, 56
62
DQ0-2
DQ2
I/O
I/O
Data Input/Output: Data bus for x4
E3
E7, E3
51
16, 51
DQS
LDQS, UDQS
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.
14, 17, 25,
43, 53
NC
-
No Connect: These pins should be left unconnected.
19, 50
DNU
VDDQ
–
Do Not Use: Must float to minimize noise on Vref
B2, D2, C8, 3, 9, 15, 55,
E8, A9 61
A1, C2, E2, 6, 12, 52,
Supply DQ Power Supply: +2.5V 0.2V. Isolated on the die for improved
noise immunity.
VSSQ
Supply DQ Ground. Isolated on the die for improved noise immunity.
B8, D8
58, 64
F8, M7, A7
1, 18, 33
VDD
Supply Power Supply: +2.5V 0.2V.
Supply Ground.
A1, A3, F2, 34, 48, 66
M3
VSS
F1
F9
49
17
VREF
Supply SSTL_2 reference voltage.
A13
I
Address input A13 for 1Gb devices.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
5
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
GENERALDESCRIPTION
The DDR333 SDRAM is a high-speed CMOS, dy-
namic random-access memory that operates at a fre-
quency of 167 MHz (tCK=6ns) with a peak data trans-
fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.
ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.
In addition to the standard 66-pin TSOP package,
a 6±-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para-
sitic parameters and a smaller footprint.
The standard DDR2±±/DDR266 data sheets also
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-
CAPACITANCE(FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS NOTES
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
DCIO
DCIO
DCIO
DCI1
DCI2
CIO
–
–
0.50
0.50
0.50
0.50
0.25
4.00
2.50
2.50
2.50
pF
pF
pF
pF
pF
pF
pF
pF
pF
13, 24
13, 24
13, 29
13, 29
13, 29
13
–
–
–
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
3.50
1.50
1.50
1.50
CI1
13
CI2
13
Input Capacitance: CKE
CI3
13
CAPACITANCE(TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS NOTES
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
DCIO
DCIO
DCIO
DCI1
DCI2
CIO
–
–
0.50
0.50
0.50
0.50
0.25
5.0
pF
pF
pF
pF
pF
pF
pF
pF
pF
13, 24
13, 24
13, 24
13, 29
13, 29
13
–
–
–
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
4.0
2.0
2.0
2.0
CI1
3.0
13
CI2
3.0
13
Input Capacitance: CKE
CI3
3.0
13
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
6
PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
ACCHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CKhigh-levelwidth
CKlow-levelwidth
-6 (FBGA)
-6T (TSOP)
-75Z
MAX UNITS NOTES
+0.75 ns
SYMBOL
MIN
-0.7
0.45
0.45
6
MAX
MIN
MAX
+0.7
0.55
0.55
13
MIN
-0.75
0.45
0.45
7.5
t
AC
+0.7
0.55
0.55
13
-0.7
0.45
0.45
6
t
t
CH
CL
0.55
0.55
13
CK
30
30
t
t
CK
ns
ns
ns
ns
ns
ns
t
Clock cycle time
CL = 2.5
CL = 2
CK (2.5)
CK (2)
45,52
45,52
26,31
26,31
31
t
7.5
13
7.5
13
7.5
13
t
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQSinputhighpulsewidth
DH
DS
0.45
0.45
1.75
-0.60 +0.60
0.35
0.45
0.45
1.75
0.50
0.50
1.75
t
t
DIPW
t
DQSCK
-0.60 +0.60 -0.75
0.35
0.35
+0.75
t
t
DQSH
DQSL
0.35
0.35
CK
t
t
DQS input low pulse width
0.35
CK
ns
t
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-outhigh-impedancewindowfromCK/CK#
Data-outlow-impedancewindowfromCK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Addressandcontrolinputpulsewidth
DQSQ
0.35
0.45
1.25
0.50
1.25
25, 26
t
t
DQSS
0.75
0.2
1.25
0.75
0.2
0.75
0.2
0.2
t
CK
t
t
DSS
CK
t
t
DSH
0.2
0.2
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
HP
CH, CL
CH, CL
CH, CL
34
18,42
18,43
14
14
14
t
HZ
+0.70
+0.70
+0.75
t
LZ
-0.70
0.75
0.75
0.80
0.80
2.2
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
t
IHF
ISF
IHS
ISS
t
t
t
1
2.2
15
14
t
IPW
t
LOADMODEREGISTERcommandcycletime
DQ-DQS hold, DQS to first DQ to go non-valid, per access
MRD
12
12
t
t
t
t
QH
HP
HP
HP
25, 26
t
t
t
QHS
QHS
QHS
-
-
-
t
QHS
RAP
0.50
0.60
0.75
ns
ns
Data Hold Skew Factor
t
ACTIVEtoAUTOPRECHARGEcommand
ACTIVEtoPRECHARGEcommand
ACTIVEtoACTIVE/AUTOREFRESHcommandperiod
AUTOREFRESHcommandperiod
ACTIVE to READ or WRITE delay
PRECHARGEcommandperiod
DQSreadpreamble
DQSreadpostamble
ACTIVEbankatoACTIVEbankbcommand
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
InternalWRITEtoREADcommanddelay
Datavalidoutputwindow
REFRESHtoREFRESHcommandinterval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
18
42
18
42
20
40
65
75
20
46
35
t
RAS
70,000
70,000
120,000 ns
t
RC
60
72
18
18
60
72
18
18
ns
ns
ns
t
RFC
50
42
t
RCD
t
RP
20
ns
t
t
RPRE
0.9
0.4
12
1.1
0.6
0.9
0.4
12
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
CK
t
t
RPST
CK
t
RRD
ns
t
t
WPRE
0.25
0
0.25
0
CK
ns
t
WPRES
20, 21
19
t
t
WPST
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
CK
ns
t
WR
t
t
WTR
1
1
1
CK
ns
µs
µs
ns
ns
t
t
t
t
t
t
na
REFC
REFI
VTD
XSNR
XSRD
QH - DQSQ
QH - DQSQ
QH - DQSQ
25
23
23
t
70.3
7.8
70.3
7.8
70.3
7.8
t
t
0
75
200
0
75
200
0
75
200
t
t
t
CK
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
7
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Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2001, Micron Technology, Inc.
8
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