MT48H16M16LFB5-75G_技术文档

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

Mobile SDRAM

MT48H16M16LF – 4 Meg x 16 x 4 banks

MT48H8M32LF – 2 Meg x 32 x 4 banks

Table 1:

Addressing

16 Meg x 16

Features

• Fully synchronous; all signals registered on positive

edge of system clock

8 Meg x 32

2 Meg x 32 x 4

banks

4 Meg x 16 x 4

banks

Configuration

• VDD/VDDQ = 1.70–1.95V

• Internal, pipelined operation; column address can

be changed every clock cycle

8K

Refresh count

8K (A0–A12)

4 (BA0, BA1)

512 (A0–A8)

4K (A0–A11)

4 (BA0, BA1)

512 (A0–A8)

Row addressing

Bank addressing

Column addressing

• Four internal banks for concurrent operation

• Programmable burst lengths: 1, 2, 4, 8, or continuous

1

page

• Auto precharge, includes concurrent auto precharge

• Auto refresh and self refresh modes

• LVTTL-compatible inputs and outputs

• On-chip temperature sensor to control refresh rate

• Partial-array self refresh (PASR)

Table 2:

Key Timing Parameters

CL = CAS (READ) latency

Clock Rate

(MHz)

Data Data

Setup Hold

Access Time

• Deep power-down (DPD)

• Selectable output drive (DS)

Speed

Grade CL = 2 CL = 3 CL = 2 CL = 3 Time Time

• 64ms refresh period (8,192 rows)

-75

-8

104

100

133

125

8ns

9ns

6ns

7ns

1.5ns

2.5ns

1ns

Marking

Options

• VDD/VDDQ

H

– 1.8V/1.8V

• Configuration

16M16

8M32

– 16 Meg x 16 (4 Meg x 16 x 4 banks)

– 8 Meg x 32 (2 Meg x 32 x 4 banks)

• Plastic “green” package

– 54-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• Timing – cycle time

– 7.5ns at CL = 3

BF

B5

-75

-8

– 8ns at CL = 3

• Power

– Standard IDD2P/IDD7

– Low IDD2P/IDD7

None

L

• Operating temperature range

– Commercial (0° to +70°C)

– Industrial (–40°C to +85°C)

• Design revision

None

IT

:G

Notes: 1. For continuous page burst, contact factory

for availability.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF__1.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Length (BL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Temperature-Compensated Self Refresh (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Driver Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LFTOC.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

List of Figures

Figure 1:

Figure 2:

Figure 3:

Figure 4:

Figure 5:

Figure 6:

Figure 7:

Figure 8:

256Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

16 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

54-Ball FBGA (Top View) – 8mm x 9mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

90-Ball VFBGA (Top View) – 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

EMR Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Typical Self Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

READ – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

READ – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Single READ – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Single READ – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

WRITE – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

WRITE – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Single WRITE – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Single WRITE – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

54-Ball VFBGA (8mm x 9mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 9:

Figure 10:

Figure 11:

Figure 12:

Figure 13:

Figure 14:

Figure 15:

Figure 16:

Figure 17:

Figure 18:

Figure 19:

Figure 20:

Figure 21:

Figure 22:

Figure 23:

Figure 24:

Figure 25:

Figure 26:

Figure 27:

Figure 28:

Figure 29:

Figure 30:

Figure 31:

Figure 32:

Figure 33:

Figure 34:

Figure 35:

Figure 36:

Figure 37:

Figure 38:

Figure 39:

Figure 40:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

Figure 45:

Figure 46:

Figure 47:

Figure 48:

Figure 49:

Figure 50:

Figure 51:

Figure 52:

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

List of Tables

Table 1:

Table 2:

Table 3:

Table 4:

Table 5:

Table 6:

Table 7:

Table 8:

Table 9:

Table 10:

Table 11:

Table 12:

Table 13:

Table 14:

Table 15:

Table 16:

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Truth Table – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Truth Table – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Truth Table – Current State Bank n, Command to Bank m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .46

AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

IDD Specifications and Conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

IDD7 – Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

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4

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

General Description

Figure 1:

256Mb Mobile SDRAM Part Numbering

Power

Example Part Number: MT48H8M32LFB5-75LIT

Mobile

V

DD

/

MT48

Package

Speed

Temp. Revision

–

Configuration

VDD

Q

Revision

:G Design Revision

V

DD/VDD

Q

H

1.8V/1.8V

Operating Temp.

Commercial

IT Industrial

Configuration

16 Meg x 16 16M16LF

Power

8 Meg x 32

8M32LF

Standard IDD2P/IDD

7

L

Low IDD2P/IDD7

Speed Grade

^tCK = 7.5ns

^tCK = 8.0ns

Package

BF

B5

8 x 9 VFBGA (lead-free)

8 x 13 VFBGA (lead-free)

-75

-8

General Description

®

The Micron 256Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access

memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM

with a synchronous interface (all signals are registered on the positive edge of the clock

signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512

columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4,096 rows by

512 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed. The address bits

registered coincident with the READ or WRITE command are used to select the starting

column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BLs) of 1, 2, 4, or 8

page locations with a read burst terminate option. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

sequence.

The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. It also allows the column address to be changed on every clock cycle to achieve a

high-speed, fully random access. Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide seamless high-speed, random-

access operation.

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5

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Functional Block Diagrams

The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto

refresh mode is provided, along with a power-saving deep power-down mode. All inputs

and outputs are LVTTL-compatible.

SDRAM offers substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks in order to hide precharge

time, and the capability to randomly change column addresses on each clock cycle

during a burst access.

Functional Block Diagrams

Figure 2:

16 Meg x 16 SDRAM

BA1

0

1

BA0

0

1

0

1

Bank

0

1

2

3

CKE

CLK

CONTROL

LOGIC

CS#

WE#

Bank3

CAS#

RAS#

Bank2

Bank1

EXT MODE

REGISTER

REFRESH

13

COUNTER

MODE REGISTER

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

13

BANK0

MEMORY

ARRAY

2

15

8,192

UDQM,

LDQM

13

(8,192 x 512 x 16)

DECODER

DATA

OUTPUT

REGISTER

Sense amplifiers

8,192

16

DQ0–

DQ15

I/O GATING

2

16

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A0–A12,

BA0, BA1

ADDRESS

REGISTER

15

DATA

INPUT

REGISTER

2

16

256

(x16)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

9

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6

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Functional Block Diagrams

Figure 3:

8 Meg x 32 SDRAM

BA1

0

1

BA0

0

1

0

1

Bank

0

1

2

3

CKE

CLK

CONTROL

LOGIC

CS#

WE#

BANK3

CAS#

RAS#

BANK2

BANK1

EXT MODE

REGISTER

REFRESH

COUNTER

13

MODE REGISTER

14

BANK0

ROW-

ADDRESS

LATCH

&

ROW-

ADDRESS

MUX

12

BANK0

MEMORY

ARRAY

4

4,096

DQM0-

DQM3

12

(4,096 x 512 x 32)

DECODER

DATA

OUTPUT

REGISTER

SENSE AMPLIFIERS

4,096

32

DQ0–

DQ31

I/O GATING

2

32

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

BANK

CONTROL

LOGIC

A0–A11,

BA0, BA1

ADDRESS

REGISTER

14

DATA

INPUT

REGISTER

2

32

512

(x32)

COLUMN

DECODER

COLUMN-

ADDRESS

COUNTER/

LATCH

9

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7

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Assignments

Figure 4:

54-Ball FBGA (Top View) – 8mm x 9mm

9

1

2

3

4

5

6

7

8

A

B

C

D

E

VSS DQ15 VSSQ

DQ14 DQ13 VDDQ

DQ12 DQ11 VSSQ

DQ10 DQ9 VDDQ

VDDQ DQ0

VDD

VSSQ DQ2 DQ1

VDDQ DQ4 DQ3

VSSQ DQ6 DQ5

VDD LDQM DQ7

CAS# RAS# WE#

DQ8 DNU

UDQM CLK

VSS

CKE

A9

F

G

H

J

A12

A8

A11

A7

BA0 BA1

CS#

A10

VDD

A6

A0

A3

A1

A2

VSS

A5

A4

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8

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Assignments

Figure 5:

90-Ball VFBGA (Top View) – 8mm x 13mm

1

2

3

4

5

6

7

8

9

A

B

C

D

E

DQ26 DQ24

VSS

VDD

VDDQ

DQ22

DQ17

NC

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

A0

DQ21

DQ19

VDDQ

VSSQ

VDD

DQ28

VSSQ

VDDQ

VSS

VDDQ

VSSQ

DQ27 DQ25

DQ29 DQ30

DQ31

DQM3

A5

NC

A3

F

A2

G

H

J

A4

A6

A10

A1

A7

A8

NC

A9

NC

BA1

A11

CLK

CKE

BA0

CAS#

VDD

CS#

RAS#

DQM0

VSSQ

VDDQ

DQ4

K

L

DQM1

VDDQ

VSSQ

DQ11

NC

VSS

DQ9

WE#

DQ7

DQ5

DQ3

VSSQ

DQ0

DNU

DQ8

DQ10

M

N

P

DQ6

DQ1

VDDQ

VDD

DQ12 DQ14

VDDQ

VSSQ

VSS

R

DQ13 DQ15

DQ2

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9

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Descriptions

Table 3:

VFBGA Ball Descriptions

54-Ball VFBGA 90-Ball VFBGA Symbol

Type

Description

F2

F3

J1

J2

CLK

CKE

Input

Clock: CLK is driven by the system clock. All SDRAM input signals

are sampled on the positive edge of CLK. CLK also increments

the internal burst counter and controls the output registers.

Input

Clock enable: CKE activates (HIGH) and deactivates (LOW) the

CLK signal. Deactivating the clock provides precharge power-

down and SELF REFRESH operation (all banks idle), ACTIVE

power-down (row active in any bank), Deep power-down (all

banks idle), or CLOCK SUSPEND operation (burst/access in

progress). CKE is synchronous except after the device enters

power-down and self refresh modes, where CKE becomes

asynchronous until after exiting the same mode. The input

buffers, including CLK, are disabled during power-down and self

refresh modes, providing low standby power.

G9

J8

CS#

Input

Chip select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when CS# is registered HIGH. CS# provides for external

bank selection on systems with multiple banks. CS# is considered

part of the command code.

F7, F8, F9

F1, E8

K7, J9, K8

CAS#,

RAS#, WE#

Input

Command inputs: RAS#, CAS#, and WE# (along with CS#) define

the command being entered.

K9, K1, F8, F2

UDQM

LDQM,

DQM0–

DQM3

Input/output mask: DQM is sampled HIGH and is an input mask

signal for write accesses and an output enable signal for read

accesses. Input data is masked during a WRITE cycle. The output

buffers are placed in a High-Z state (two-clock latency) during a

READ cycle. For the x16, LDQM corresponds to DQ0–DQ7 and

UDQM corresponds to DQ8–DQ16. For the x32, DQM0

corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15,

DQM2 corresponds to DQ16–DQ23, and DQM3 corresponds to

DQ24–DQ31. DQM0–DQM3 (or LDQM and UDQM if x16) are

considered same state when referenced as DQM. DQM loading is

designed to match that of DQ balls.

G7, G8

J7, H8

BA0, BA1

A0–A12

Input

Bank address input(s): BA0 and BA1 define to which bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied. These balls also provide the op-code during a LOAD

MODE REGISTER (LMR) command. BA0 and BA1 become “Don’t

Care” when registering an ALL BANK PRECHARGE (A10 HIGH).

H7, H8, J8, J7, G8, G9, F7, F3,

J3, J2, H3, H2, G1, G2, G3, H1,

H1, G3, H9, G2, H2, J3, G7, H9

G1

Address inputs: A0–A12 are sampled during the ACTIVE

command (row-address A0–A12) and READ/WRITE command

(column-address A0–A8 [x32]; column-address A0–A8 [x16]; with

A10 defining auto precharge) to select one location out of the

memory array in the respective bank. A10 is sampled during a

PRECHARGE command to determine if all banks are to be

precharged (A10 HIGH) or bank selected by BA0, BA1. The

address inputs also provide the op-code during a LMR command.

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10

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Descriptions

Table 3:

VFBGA Ball Descriptions (Continued)

54-Ball VFBGA 90-Ball VFBGA Symbol

Type

Description

Data input/output: Data bus.

A8, B9, B8, C9, R8, N7, R9, N8, DQ0–DQ31

C8, D9, D8, E9, P9, M8, M7, L8,

E1, D2, D1, C2, L2, M3, M2, P1,

C1, B2, B1, A2 N2, R1, N3, R2,

E8, D7, D8, B9,

I/O

C8, A9, C7, A8,

A2, C3, A1, C2,

B1, D2, D3, E2

A7, B3, C7, D3 B2, B7, C9, D9,

E1, L1, M9, N9,

VDDQ

VSSQ

Supply

DQ power: Provide isolated power to DQ for improved noise

immunity.

P2, P7

A3, B7, C3, D7 B8, B3, C1, D1,

E9, L9, M1, N1,

DQ ground: Provide isolated ground to DQ for improved noise

immunity.

P3, P8

A9, E7, J9

A1, E3, J1

–

A7, F9, L7, R7

A3, F1, L3, R3

VDD

VSS

NC

Supply

–

Core power supply.

Ground.

E3, E7, H3, H7,

K3

Internally not connected: These could be left unconnected, but

it is recommended they be connected to Vss.

E2

K2

DNU

Input

E2 is a TEST pin that must be tied to VSS or VssQ in normal

operation.

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11

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Functional Description

In general, a 256Mb SDRAM is quad-bank DRAM that operates at 1.8V and includes a

synchronous interface (all signals are registered on the positive edge of the clock signal,

CLK).

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A12 select the row for x16, and A0–A11 select the row for x32). The

address bits (A0–A8 for x16 and A0–A8 for x32) registered coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections

provide detailed information covering device initialization, register definition,

command descriptions, and device operation.

Initialization

SDRAM must be powered up and initialized in a predefined manner. Operational proce-

dures other than those specified may result in undefined operation. The initialization for

mobile SDRAM is as follows.

1. Simultaneously apply power to VDD and VDDQ.

2. After power supplies have settled, apply a stable clock signal. Stable clock is defined as

a signal cycling within timing constraints specified for the clock pin.

3. Wait at least 100µs. During this period NOP or COMMAND INHIBIT commands

should be applied. No other command other than NOP or COMMAND INHIBIT is

allowed during this period.

4. Preform a PRECHARGE ALL command to place the SDRAM into an all banks idle

state.

t

5. Wait at least RP time. During this time NOP or COMMAND INHIBIT commands must

be applied.

6. Issue an AUTO REFRESH command.

t

7. Wait at least RFC time, during which only NOP or COMMAND INHIBIT commands

are allowed.

8. Issue an Auto Refresh command.

t

9. Wait at least RFC time, during which only NOP or COMMAND INHIBIT commands

are allowed.

10. Issue a LOAD MODE REGISTER command with BA1=0, andBA0=0, to program the

mode register with desired values.

t

11. Wait MRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-

ing this time.

12. Issue a LOAD MODE REGISTER command with BA1=1, and BA0=0, to program the

extended mode register with desired values.

t

13. Wait MRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-

ing this time.

The Mobile SDRAM is now initialized and can accept any valid command.

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12

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Register Definition

Mode Register

There are two MRs in the component: mode register and extended mode register (EMR).

The mode register is illustrated in Figure 6 on page 14. The mode register is used to

define the specific mode of operation of the SDRAM. This definition includes the selec-

tion of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a

write burst mode, as shown in Figure 6 on page 14. The mode register is programmed via

the LMR command and will retain the stored information until it is programmed again

or the device loses power.

M0–M2 mode register bits specify the BL, M3 specifies the type of burst, M4–M6 specify

the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and

M10 and M11 should be set to zero.

The mode register must be loaded when all banks are idle, and the controller must wait

t

MRD before initiating the subsequent operation. Violating either of these requirements

will result in unspecified operation.

Burst Length (BL)

Read and write accesses to the SDRAM are burst oriented, with the BL being program-

mable, as shown in Figure 6 on page 14. The BL determines the maximum number of

column locations that can be accessed for a given READ or WRITE command. BL = 1, 2,

4, 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the BL is effec-

tively selected. All accesses for that burst take place within this block, meaning that the

burst will wrap within the block if a boundary is reached. The block is uniquely selected

by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least

significant) address bit(s) is (are) used to select the starting location within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the BL, the burst type, and the

starting column address, as shown in Table 4 on page 15.

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Register Definition

Figure 6:

Mode Register Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

0

14 13 12 11 10

9

8

7

6

5

4

3

2

1

Mode

Register (Mx)

0

Burst Length

Reserved

CAS Latency

WB OP Mode

BT

Program

M12, M11, M10 = “0, 0, 0”

to ensure compatibility

with future devices.

Burst Length

M2 M1M0

M3 = 0

M3 = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

Mode Register Definintion

Base mode register

Reserved

M13

M14

4

8

4

8

0

1

0

1

0

1

Reserved

Extended mode register

Reserved

Reserved Reserved

M9

0

Write Burst Mode

Reserved

Programmed burst length

1

Single location access

Burst Type

M3

0

M8 M7

Operating Mode

Normal operation

M6–M0

Valid

–

Sequential

Interleaved

0

–

0

–

1

All other states reserved

CAS Latency

Reserved

2

M6 M5 M4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

Reserved

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Register Definition

Table 4:

Burst Definition Table

Order of Accesses Within a Burst

Burst Length Starting Column Address

Type = Sequential

Type = Interleaved

2

A0

0

0-1

1-0

0-1

1-0

1

4

A1

0

A0

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0

1

0

1

8

A2

0

A1

0

A0

0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0

1

0

1

0

1

0

1

0

1

0

1

CAS Latency (CL)

The CL is the delay, in clock cycles, between the registration of a READ command and

the availability of the first piece of output data. The latency can be set to two or three

clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQs will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times are met, if a READ command is registered at T0

and the latency is programmed to two clocks, the DQs will start driving after T1 and the

data will be valid by T2, as shown in Figure 7 on page 16.

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.

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Register Definition

Figure 7:

CAS Latency

T0

T1

T2

T3

CLK

COMMAND

DQ

READ

NOP

t

NOP

t

LZ

OH

D

OUT

t

AC

CL = 2

T1

T0

T2

T3

T4

CLK

COMMAND

READ

NOP

t

LZ

OH

D

OUT

DQ

t

AC

CL = 3

DON’T CARE

UNDEFINED

Operating Mode

Write Burst Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use.

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.

When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;

when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-

location accesses.

Extended Mode Register (EMR)

The low-power EMR controls the functions beyond those controlled by the MR. These

additional functions are special features of the mobile device. They include tempera-

ture-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and

output drive strength.

The low-power EMR is programmed via the MODE REGISTER SET command and

retains the stored information until it is programmed again or the device loses power.

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Register Definition

Figure 8:

EMR Definition

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0

0

14 13 12 11 10

9

8

7

6

5

4

3

2

1

Extended Mode

Register

1

0

set to “0”

DS

TCSR¹

PASR

Mode Register Definintion

Standard mode register

Reserved

Driver Strength

Full strength driver

Half strength driver

E13

0

1

E14

0

E6 E5

0

1

0

1

Extended mode register

Reserved

Quarter strength driver

Eighth strength driver

1

0

1

E12 E11 E10 E9 E8 E7

E6–E0

Valid

–

E2 E1 E0 Partial Array Self Refresh Coverage

Normal operation

All other states reserved

0

–

0

–

0

–

0

–

0

–

0

–

0

1

0

1

0

Full array

Half array

Quarter array

0

1

0

1

0

1

Reserved

One-eighth array

1

0

1

One-sixteenth array

Reserved

Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.

The EMR must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiating any subsequent operation.

Violating either of these requirements results in unspecified operation. Once the values

are entered, the EMR settings will be retained even after exiting deep power-down mode.

Temperature-Compensated Self Refresh (TCSR)

On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for

automatic control of the self refresh oscillator on the device. Therefore, it is recom-

mended not to program or use the temperature-compensated self refresh control bits in

the extended mode register.

Programming of the TCSR bits has no effect on the device. The self refresh oscillator will

continue refresh at the factory programmed optimal rate for the device temperature.

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Register Definition

Partial-Array Self Refresh (PASR)

For further power savings during self refresh, the partial-array self refresh (PASR) feature

allows the controller to select the amount of memory that will be refreshed during self

refresh. The following refresh options are available.

1. All banks (banks 0, 1, 2, and 3).

2. Two banks (banks 0 and 1; BA1=0).

3. One bank (bank 0; BA1 = BA0 = 0).

4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0).

5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB -1 = 0).

WRITE and READ commands occur to any bank selected during standard operation, but

only the selected banks in PASR will be refreshed during self refresh. It is important to

note that data in banks 2 and 3 will be lost when the two-bank option is used.

Driver Strength

Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs.

This value should be set according to the application’s requirements.

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Commands

Table 5 provides a quick reference of available commands. This is followed by a written

description of each command. Three additional Truth Tables appear following “Opera-

tions” on page 23. These tables provide current state/next state information.

Table 5:

Truth Table – Commands and DQM Operation

Notes 1 and 2 apply to all commands

Name (Function)

CS# RAS# CAS# WE# DQM

ADDR

DQs Notes

H

L

X

H

L

X

H

L

X

H

L

X

4

COMMAND INHIBIT (NOP)

X

4

NO OPERATION (NOP)

X

Bank/Row

Bank/Col

5

ACTIVE (Select bank and activate row)

READ (Select bank and column, and start READ burst)

WRITE (Select bank and column, and start WRITE burst)

H

L/H

X

6

L

Bank/Col Valid

H

L

X

3, 7, 8

BURST TERMINATE or deep power-down

(Enter deep power-down mode)

L

H

L

X

Code

X

9

PRECHARGE (Deactivate row in bank or banks)

H

10, 11

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

L

X

L

X

L

X

L

X

L

Op-Code

X

12

LOAD MODE REGISTER

X

Active

High-Z

Write enable/output enable

Write inhibit/output High-Z

H

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.

2. All states and sequences not shown are reserved and/or illegal.

3. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command

could coincide with data on the bus. However, the DQs column reads a don’t care state to

illustrate that the BURST TERMINATE command can occur when there is no data present.

4. DESELECT and NOP are functionally interchangeable.

5. BA0–BA1 provide bank address and A0–A12 provide row address.

6. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto

precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

7. Applies only to read bursts with auto precharge disabled; this command is undefined (and

should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW.

9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-

charged and BA0–BA1 are “Don’t Care.”

10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

12. BA0–BA1 select either the standard mode register or the extended mode register (BA0 = 0,

BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register;

other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to

the selected mode register.

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the

SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

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Commands

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is

selected (CS# is LOW). This prevents unwanted commands from being registered during

idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The MR is loaded via inputs A0–A12, BA0, and BA1. (See “Mode Register” on page 13.)

The LMR and LOAD EXTENDED MODE REGISTER (LEMR) commands can only be

issued when all banks are idle, and a subsequent executable command cannot be issued

t

until MRD is met.

ACTIVE

READ

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address

provided selects the row. This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A PRECHARGE command must be issued

before opening a different row in the same bank.

The READ command is used to initiate a burst read access to an active row. The value on

the BA0, BA1 inputs selects the bank, and the address provided selects the starting

column location. The value on input A10 determines whether or not auto precharge is

used. If auto precharge is selected, the row being accessed will be precharged at the end

of the read burst; if auto precharge is not selected, the row will remain open for subse-

quent accesses. Read data appears on the DQs subject to the logic level on the DQM

inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding

DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will

provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0, BA1 inputs selects the bank, and the address provides the starting column

location. The value on input A10 determines whether or not auto precharge is used. If

auto precharge is selected, the row being accessed will be precharged at the end of the

write burst; if auto precharge is not selected, the row will remain open for subsequent

accesses. Input data appearing on the DQs is written to the memory array subject to the

DQM input logic level appearing coincident with the data. If a given DQM signal is regis-

tered LOW, the corresponding data will be written to memory; if the DQM signal is regis-

tered HIGH, the corresponding data inputs will be ignored, and a write will not be

executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

t

specified time ( RP) after the precharge command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the case where only one bank is to

be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as

“Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

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Commands

BURST TERMINATE

AUTO REFRESH

The BURST TERMINATE command is used to truncate fixed-length bursts. The most

recently registered READ or WRITE command prior to the BURST TERMINATE

command will be truncated, as shown in “Operations” on page 23.

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAM. This command is non persis-

tent, so it must be issued each time a refresh is required. All active banks must be

PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH

t

command should not be issued until the minimum RP has been met after the

PRECHARGE command, as shown in “Operations” on page 23.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires

t

8,192 AUTO REFRESH cycles every 64ms ( REF). Providing a distributed AUTO REFRESH

command every 7.8125µs will meet the refresh requirement and ensure that each row is

refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the

t

minimum cycle rate ( RFC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self refresh mode, the SDRAM retains data

without external clocking. The SELF REFRESH command is initiated like an AUTO

REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh

t

mode for a minimum period equal to RAS and may remain in self refresh mode for an

indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must

t

have NOP commands issued (a minimum of two clocks) for XSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every

7.8125µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

Auto Precharge

Auto precharge is a feature which performs the same individual-bank precharge func-

tion described above, without requiring an explicit command. This is accomplished by

using A10 to enable auto precharge in conjunction with a specific READ or WRITE

command. A precharge of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst.

Auto precharge is non persistent in that it is either enabled or disabled for each indi-

vidual READ or WRITE command.

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Commands

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

t

time ( RP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in “Operations” on

page 23.

Deep Power-Down

Deep power-down is an operating mode used to achieve maximum power reduction by

eliminating the power to the memory array. Data will not be retained once the device

enters deep power-down mode.

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Operations

Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see Figure 9).

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be

t

issued to that row, subject to the RCD specification. RCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

t

entered. For example, a RCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 24, which covers

t

any case where 2 < RCD (MIN)/ CK ≤ 3. (The same procedure is used to convert other

specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

t

interval between successive ACTIVE commands to the same bank is defined by RC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

t

RRD.

Figure 9:

Activating a Specific Row in a Specific Bank

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

ROW

ADDRESS

A0–A11

BANK

ADDRESS

BA0, BA1

DON´T CARE

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Operations

t

Figure 10: Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK < 3

T0

T1

T2

T3

CLK

t

CK

READ or

WRITE

COMMAND

ACTIVE

NOP

t

RCD (MIN)

DON’T CARE

READs

READ bursts are initiated with a READ command, as shown in Figure 11.

The starting column and bank addresses are provided with the READ command, and

auto precharge is either enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-out

element will be valid by the next positive clock edge. Figure 7 on page 16 shows general

timing for each possible CL setting.

Figure 11: READ Command

CLK

CKE

CS#

HIGH

RAS#

CAS#

WE#

COLUMN

ADDRESS

A0–A8

A9, A11

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A10

BANK

ADDRESS

BA0, BA1

DON’T CARE

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go High-Z.

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Operations

Data from any READ burst may be truncated with a subsequent READ command, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst follows either the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ

command should be issued x cycles before the clock edge at which the last desired data

element is valid, where x = CL - 1.

Figure 7 on page 16 shows for CL of two and three; data element n + 3 is either the last of

a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined

architecture. A READ command can be initiated on any clock cycle following a previous

READ command. Full-speed random read accesses can be performed to the same bank,

as shown in Figure 12 on page 25, or each subsequent READ may be performed to a

different bank.

Figure 12: Consecutive READ Bursts

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

READ

NOP

COMMAND

X = 1 cycle

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

D

OUT

D

n + 1

OUT

DOUT

D

OUT

n

n + 2

n + 3

b

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ

NOP

READ

NOP

COMMAND

X = 2 cycles

BANK,

COL n

BANK,

COL b

ADDRESS

DQ

D

OUT

D

OUT

D

OUT

D

OUT

DOUT

n

n + 1

n + 2

n + 3

b

CL = 3

DON’T CARE

Note:

Each READ command may be to either bank. DQM is LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 13: Random READ Accesses

T0

T1

T2

T3

T4

T5

CLK

COMMAND

ADDRESS

DQ

READ

NOP

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

D

OUT

D

OUT

D

OUT

D

OUT

n

a

x

m

CL = 2

T0

T1

T2

T3

T4

T5

T6

CLK

READ

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

D

OUT

D

OUT

D

OUT

D

OUT

n

a

x

m

CL = 3

DON’T CARE

Note:

Each READ command may be to either bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burst may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). The WRITE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, there may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figure 14 on page 27 and

Figure 15 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior

to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-

out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or

remain High-Z), regardless of the state of the DQM signal, provided the DQM was active

on the clock just prior to the WRITE command that truncated the READ command. If

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during

T4 (as in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the

WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 on

page 25 shows the case where the clock frequency allows for bus contention to be

avoided without adding a NOP cycle, and Figure 13 on page 26 shows the case where the

additional NOP is needed.

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated). The

PRECHARGE command should be issued x cycles before the clock edge at which the last

desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for

each possible CL; data element n + 3 is either the last of a burst of four or the last desired

of a longer burst. Following the PRECHARGE command, a subsequent command to the

t

same bank cannot be issued until RP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate fixed-length page bursts.

Figure 14: READ-to-WRITE

T0

T1

T2

T3

T4

CLK

DQM

READ

NOP

WRITE

COMMAND

ADDRESS

BANK,

COL n

BANK,

COL b

t

CK

t

HZ

DOUT

n

DIN b

DQ

t

DS

DON’T CARE

Note:

CL = 3. The READ command may be to any bank, and the WRITE command may be to any

bank. If a burst of one is used, then DQM is not required.

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Operations

Figure 15: READ-to-WRITE with Extra Clock Cycle

T0

T1

T2

T3

T4

T5

CLK

DQM

READ

NOP

WRITE

COMMAND

ADDRESS

BANK,

COL b

BANK,

COL n

t

HZ

D

OUT

n

D

IN

b

DQ

t

DS

DON’T CARE

Note:

CL = 3. The READ command may be to any bank, and the WRITE command may be to any

bank.

Figure 16: READ-to-PRECHARGE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

t

RP

READ

NOP

PRECHARGE

NOP

ACTIVE

X = 1 cycle

BANK a,

BANK

(a or all)

BANK a,

ROW

COL

n

D

OUT

D

n + 1

OUT

DOUT

n + 3

n

n + 2

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

t

RP

READ

NOP

PRECHARGE

NOP

ACTIVE

X = 2 cycles

BANK a,

BANK

(a or all)

BANK a,

ROW

COL

n

D

OUT

DOUT

D

OUT

DOUT

n + 3

n

n + 1

n + 2

CL = 3

DON’T CARE

Note:

DQM is LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure 17 for each possible CL; data element n +

3 is the last desired data element of a longer burst.

Figure 17: Terminating a READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

BURST

TERMINATE

READ

NOP

COMMAND

ADDRESS

DQ

X = 1 cycle

BANK,

COL n

D

OUT

D

n + 1

OUT

D

OUT

DOUT

n + 3

n

n + 2

CL = 2

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

ADDRESS

DQ

BURST

TERMINATE

READ

NOP

X = 2 cycles

BANK,

COL n

D

OUT

D

OUT

D

n + 2

OUT

DOUT

n + 3

n

n + 1

CL = 3

DON’T CARE

Note:

DQM is LOW.

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29

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30.

The starting column and bank addresses are provided with the WRITE command, and

auto precharge is either enabled or disabled for that access. If auto precharge is enabled,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length burst, assuming no other

commands have been initiated, the DQs will remain High-Z and any additional input

data will be ignored (see Figure 19).

Figure 18: WRITE Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

COLUMN

ADDRESS

A0–A8

A9, A11, A12

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A10

BANK

ADDRESS

BA0, BA1

VALID ADDRESS

DON’T CARE

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRITE burst may be immediately followed by data for a WRITE

command. The new WRITE command can be issued on any clock following the previous

WRITE command, and the data provided coincident with the new command applies to

the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe-

lined architecture. A WRITE command can be initiated on any clock cycle following a

previous WRITE command. Full-speed random write accesses within a page can be

performed to the same bank, as shown in Figure 19 on page 31, or each subsequent

WRITE may be performed to a different bank.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 19: WRITE Burst

T0

T1

T2

T3

CLK

WRITE

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

DIN

n + 1

n

DON’T CARE

Note:

BL = 2. DQM is LOW.

Figure 20: WRITE-to-WRITE

T0

T1

T2

CLK

WRITE

NOP

WRITE

COMMAND

ADDRESS

DQ

BANK,

COL n

BANK,

COL b

D

IN

D

IN

DIN

b

n

n + 1

DON’T CARE

Note:

BL = 2. DQM is LOW. Each WRITE command may be to any bank.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed-length WRITE burst may be immediately followed by a READ command.

Once the READ command is registered, the data inputs will be ignored, and WRITEs will

not be executed. An example is shown in Figure 21 on page 32. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto precharge was not acti-

t

vated). The PRECHARGE command should be issued WR after the clock edge at which

the last desired input data element is registered. The auto precharge mode requires a

t

WR of at least one clock plus time (see note 24 on page 52), regardless of frequency.

In addition, when truncating a WRITE burst, the DQM signal must be used to mask

input data for the clock edge prior to, and the clock edge coincident with, the

PRECHARGE command. An example is shown in Figure 21 on page 32. Data n + 1 is

either the last of a burst of two or the last desired of a longer burst. Following the

PRECHARGE command, a subsequent command to the same bank cannot be issued

t

until RP is met.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate fixed-length bursts.

Figure 21: Random WRITE Cycles

T0

T1

T2

T3

CLK

WRITE

COMMAND

BANK,

COL n

BANK,

COL a

BANK,

COL x

BANK,

COL m

ADDRESS

DQ

D

IN

D

IN

D

IN

DIN

x

m

n

a

DON’T CARE

Note:

Each WRITE command may be to any bank. DQM is LOW.

Figure 22: WRITE-to-READ

T0

T1

T2

T3

T4

T5

CLK

WRITE

NOP

READ

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

BANK,

COL b

DIN

D

IN

D

OUT

DOUT

b + 1

n

n + 1

b

DON’T CARE

Note:

BL = 2. The WRITE command may be to any bank, and the READ command may be to any

bank. DQM is LOW. CL = 2 for illustration.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 23: WRITE-to-PRECHARGE

T0

T1

T2

T3

T4

T5

T6

CLK

t

WR@ CK ≥ 15ns

DQM

t

RP

NOP

WRITE

NOP

PRECHARGE

ACTIVE

COMMAND

ADDRESS

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

t

WR

D

n

IN

DIN

n + 1

DQ

t

WR@ CK < 15ns

DQM

t

RP

NOP

WRITE

NOP

PRECHARGE

ACTIVE

COMMAND

ADDRESS

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

t

WR

D

n

IN

DIN

n + 1

DQ

DON’T CARE

Note:

DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Figure 24: Terminating a WRITE Burst

T0

T1

T2

CLK

BURST

TERMINATE

WRITE

COMMAND

BANK,

COL n

(Address)

(Data)

ADDRESS

DIN

DQ

n

DON’T CARE

Note:

DQMs are LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Fixed-length or WRITE bursts can be truncated with the BURST TERMINATE command.

When truncating a WRITE burst, the input data applied coincident with the BURST

TERMINATE command will be ignored. The last data written (provided that DQM is

LOW at that time) will be the input data applied one clock previous to the BURST

TERMINATE command. This is shown in Figure 22 on page 32, where data n is the last

desired data element of a longer burst.

PRECHARGE

The PRECHARGE command (see Figure 25) is used to deactivate the open row in a

particular bank or the open row in all banks. The bank(s) will be available for a subse-

t

quent row access some specified time ( RP) after the precharge command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all

banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has

been precharged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

Figure 25: PRECHARGE Command

CLK

CKE

HIGH

CS#

RAS#

CAS#

WE#

A0–A9, A11, A12

A10

All Banks

Bank Selected

BANK

ADDRESS

BA0, BA1

VALID ADDRESS

DON’T CARE

Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress. If power-down occurs when all banks are

idle, this mode is referred to as precharge power-down; if power-down occurs when

there is a row active in any bank, this mode is referred to as active power-down. Entering

power-down deactivates the input and output buffers, excluding CKE, for maximum

power savings while in standby. The device may not remain in the power-down state

longer than the refresh period (64ms) since no REFRESH operations are performed in

this mode.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

t

HIGH at the desired clock edge (meeting CKS). See Figure 24.

Figure 26: Power-Down

( (

) )

( (

) )

CLK

> t

CKS

t

CKS

CKE

( (

) )

( (

) )

( (

) )

COMMAND

NOP

ACTIVE

t

All banks idle

RCD

Input buffers gated off

t

RAS

t

RC

Enter power-down mode

Exit power-down mode

DON’T CARE

Deep Power-Down

Deep power-down mode is a maximum power savings feature achieved by shutting off

the power to the entire memory array of the device. Data in the memory array will not be

retained once deep power-down mode is executed. Deep power-down mode is entered

by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the

rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-

down.

To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of Deep Power-

Down mode, at least 200µs of valid clocks with either NOP or COMMAND INHIBIT

commands are applied to the command bus, followed by a full Mobile SDRAM initializa-

tion sequence, is required.

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data present on the input balls at the time of

a suspended internal clock edge is ignored; any data present on the DQ balls remains

driven; and burst counters are not incremented, as long as the clock is suspended. (See

examples in Figure 27 and Figure 28 on page 37.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the MR to a logic 1. In this mode, all WRITE commands result in the access of a

single column location (burst of one), regardless of the programmed BL. READ

commands access columns according to the programmed BL and sequence, just as in

the normal mode of operation (M9 = 0).

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35

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Concurrent Auto Precharge

An access command (READ or WRITE) to a second bank while an access command with

auto precharge enabled on a first bank is executing is not allowed by SDRAM, unless the

SDRAM supports concurrent auto precharge. Micron SDRAM support concurrent auto

precharge. Four cases where concurrent auto precharge occurs are defined in the “READ

with Auto Precharge” and “WRITE with Auto Precharge” sections.

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ

to bank m is registered (see Figure 29 on page 37).

2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when registered. DQM should be used two clocks prior to

the WRITE command to prevent bus contention. The precharge to bank n will begin

when the WRITE to bank m is registered (see Figure 30 on page 38).

Figure 27: Clock Suspend During WRITE Burst

T0

T1

T2

T3

T4

T5

CLK

CKE

INTERNAL

CLOCK

NOP

WRITE

NOP

COMMAND

ADDRESS

BANK,

COL n

D

n

IN

D

n + 1

IN

DIN

n + 2

DIN

DON’T CARE

Note:

For this example, BL = 4 or greater, and DM is LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 28: Clock Suspend During READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

CKE

INTERNAL

CLOCK

READ

NOP

COMMAND

ADDRESS

DQ

BANK,

COL n

D

OUT

D

OUT

D

n + 2

OUT

DOUT

n + 3

n

n + 1

DON’T CARE

Note:

For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

Figure 29: READ with Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

BANK n

READ - AP

BANK m

NOP

COMMAND

Page Active

READ with Burst of 4

Interrupt Burst, Precharge

t

Idle

BANK n

t

RP - BANK n

RP - BANK m

Internal

States

Precharge

Page Active

READ with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

D

OUT

DOUT

a

a + 1

d

d + 1

CL = 3 (bank n)

CL = 3 (bank m)

DON’T CARE

Note:

DQM is LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 30: READ with Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

READ - AP

BANK n

WRITE - AP

BANK m

NOP

COMMAND

Page

Active

READ with Burst of 4

Page Active

Interrupt Burst, Precharge

t

Idle

WR - BANK m

BANK n

t

RP - BANK

n

Internal

States

Write-Back

WRITE with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

1

DQM

D

OUT

DIN

d

D

d + 1

IN

D

d + 2

IN

DIN

d + 3

DQ

a

CL = 3 (bank n)

DON’T CARE

Note:

DQM is HIGH at T2 to prevent DOUT a +1 from contending with DIN d at T4.

WRITE with Auto Precharge

1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

t

precharge to bank n will begin after WR is met, where WR begins when the READ to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (see Figure 31 on page 39).

2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

t

after WR is met, where WR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (see Figure 32 on page 39).

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Operations

Figure 31: WRITE with Auto Precharge Interrupted by a READ

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

BANK n

READ - AP

BANK m

NOP

COMMAND

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

BANK n

t

RP - BANK n

t

WR - BANK n

Internal

States

t

RP - BANK m

Page Active

READ with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

DIN

D

a + 1

IN

DOUT

a

d

d + 1

CL = 3 (bank m)

DON’T CARE

Note:

DQM is LOW.

Figure 32: WRITE with Auto Precharge Interrupted by a WRITE

T0

T1

T2

T3

T4

T5

T6

T7

CLK

WRITE - AP

BANK n

WRITE - AP

BANK m

NOP

COMMAND

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

BANK n

t

RP - BANK n

t

WR - BANK n

Internal

States

t

WR - BANK m

Write-Back

Page Active

WRITE with Burst of 4

BANK m

BANK n,

COL a

BANK m,

COL d

ADDRESS

DQ

DIN

D

a + 1

IN

D

a + 2

IN

DIN

D

IN

a

d

d + 1

d + 2

d + 3

DON’T CARE

Note:

DQM is LOW.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

Table 6:

Truth Table – CKE

Notes: 1–4

CKE_n-1

CKE_n

Current State

Command_n

Action_n

Notes

L

H

L

Power-down

Self refresh

X

Maintain power-down

Maintain self refresh

Maintain clock suspend

Maintain deep power-down

Exit power-down

X

Clock suspend

Deep power-down

Power-down

X

8

5

8

6

7

L

COMMAND INHIBIT or NOP

X

Deep power-down

Self refresh

Exit deep power-down

Exit self refresh

COMMAND INHIBIT or NOP

X

Clock suspend

All banks idle

Reading or writing

Exit clock suspend

H

COMMAND INHIBIT or NOP

BURST TERMINATE

AUTO REFRESH

VALID

Power-down entry

Deep power-down entry

Self refresh entry

8

Clock suspend entry

H

See Table 8 on page 43

Notes: 1. CKE_nis the logic state of CKE at clock edge n; CKE_n-1was the state of CKE at the previous

clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND_nis the command registered at clock edge n, and ACTION_nis a result of COM-

MAND_n.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that ^tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once ^tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the ^tXSR period. A minimum of two NOP commands must be provided during ^tXSR

period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize

the next command at clock edge n + 1.

8. Deep power-down is power savings feature of this Mobile SDRAM device. This command is

BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

Table 7:

Truth Table – Current State Bank n, Command to Bank n

Notes: 1–6; notes appear below table

Current State

CS# RAS# CAS# WE# Command (Action)

Notes

Any

H

X

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

ACTIVE (Select and activate row)

L

H

Idle

L

H

L

H

L

7

AUTO REFRESH

L

LMR

L

H

L

11

10

8

PRECHARGE

Row active

H

L

H

L

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Truncate READ burst, start PRECHARGE)

BURST TERMINATE

L

H

L

Read

(auto precharge

disabled)

H

L

H

L

10

8

L

H

L

H

L

9

Write

(auto precharge

disabled)

H

L

10

8

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE (Truncate WRITE burst, start PRECHARGE)

BURST TERMINATE

L

H

L

H

L

9

Notes: 1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (see Table 6 on page 40) and

after ^tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank

and the commands shown are those allowed to be issued to that bank when in that state.

Exceptions are covered in the notes below.

3. Current state definitions:

Idle:

Row active:

The bank has been precharged, and ^tRP has been met.

A row in the bank has been activated, and ^tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

A READ burst has been initiated, with auto precharge disabled, and has

not yet terminated or been terminated.

Read:

Write:

A WRITE burst has been initiated, with auto precharge disabled, and has

not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands, or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determined by its current state and Table 7, and according to Table 8 on page 43.

Precharging:

Starts with registration of a PRECHARGE command and ends when

^tRP is met. Once ^tRP is met, the bank will be in the idle state.

Starts with registration of an ACTIVE command and ends when ^tRCD

is met. Once ^tRCD is met, the bank will be in the row active state.

Starts with registration of a READ command with auto precharge

enabled and ends when ^tRP has been met. Once ^tRP is met, the bank

will be in the idle state.

Row activating:

Read w/auto-

precharge enabled:

Write w/auto-

precharge enabled:

Starts with registration of a WRITE command with auto precharge

enabled and ends when^tRP has been met. Once ^tRP is met, the bank

will be in the idle state.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

5. The following states must not be interrupted by any executable command; DESELECT or

NOP commands must be applied on each positive clock edge during these states.

Refreshing:

Starts with registration of an AUTO REFRESH command and ends

when ^tRFC is met. Once ^tRFC is met, the Mobile SDRAM will be in the

all banks idle state.

Accessing MR:

Precharging all:

Starts with registration of an LMR command and ends when ^tMRD

has been met. Once ^tMRD is met, the Mobile SDRAM will be in the

all banks idle state.

Starts with registration of a PRECHARGE ALL command and ends

when ^tRP is met. Once ^tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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Truth Tables

Table 8:

Truth Table – Current State Bank n, Command to Bank m

Notes: 1–6; notes appear below and on next page

Current State

CS# RAS# CAS# WE# Command (Action)

Notes

Any

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Any command otherwise allowed to bank m

ACTIVE (Select and activate row)

Idle

Row activating,

active, or

precharging

H

L

7

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

L

H

L

Read

(auto precharge

disabled)

L

H

L

ACTIVE (Select and activate row)

H

L

7, 8

7, 9

10

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

L

H

L

Write

(auto precharge

disabled)

L

H

L

ACTIVE (Select and activate row)

H

L

7, 11

7, 12

10

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE

L

H

L

Read

(with auto

precharge)

L

H

L

ACTIVE (Select and activate row)

H

L

7, 13, 14

7, 13, 15

10

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

L

H

L

Write

(with auto

precharge)

L

H

L

ACTIVE (Select and activate row)

H

L

7, 13, 16

7, 13, 17

10

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE

L

H

L

Notes: 1. This table applies when CKE_n-1was HIGH and CKE_nis HIGH (see Table 6 on page 40) and

after ^tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is

for bank n and the commands shown are those allowed to be issued to bank m (assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, and ^tRP has been met.

A row in the bank has been activated, and ^tRCD has been met. No

data bursts/accesses and no register accesses are in progress.

A READ burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Row active:

Read:

Write:

A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read w/auto-

precharge enabled:

Starts with registration of a READ command with auto precharge

enabled and ends when ^tRP has been met. Once ^tRP is met, the bank

will be in the idle state.

Write w/auto-

precharge enabled:

Starts with registration of a WRITE command with auto precharge

enabled and ends when ^tRP has been met. Once ^tRP is met, the bank

will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LMR commands may only be issued when all banks are

idle.

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 11 on

page 24).

9. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered (see

Figure 12 on page 25 and Figure 13 on page 26). DQM should be used one clock prior to the

WRITE command to prevent bus contention.

10. Burst in bank n continues as initiated.

11. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (see

Figure 20 on page 31), with the data-out appearing CL later. The last valid WRITE to bank n

will be data-in registered one clock prior to the READ to bank m.

12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see

Figure 18 on page 30). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its

burst has been interrupted by bank m burst.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n

will begin when the READ to bank m is registered.

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE

to bank n will begin when the WRITE to bank m is registered.

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The PRECHARGE to bank n will begin after ^tWR is met, where ^tWR

begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in

registered one clock prior to the READ to bank m.

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),

the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to

bank n will begin after ^tWR is met, where ^tWR begins when the WRITE to bank m is regis-

tered. The last valid WRITE to bank n will be data registered one clock to the WRITE to

bank m.

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44

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Absolute Maximum Ratings

Stresses greater than those listed in Table 9 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

Table 9:

Absolute Maximum Ratings

Voltage/Temperature

Min

Max

Units

–0.3

–55

+2.7

+150

V

Voltage on VDD/VDDQ supply relative to VSS (1.8V)

Voltage on inputs, NC or I/O balls relative to VSS (1.8V)

Storage temperature plastic

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V

Parameter/Condition

Symbol

Min

Max

Units

Notes

VDD

VDDQ

VIH

1.7

1.95

V

Supply voltage

I/O supply voltage

0.8 × VDDQ VDDQ + 0.3

V

22

Input high voltage: Logic 1; All inputs

Input low voltage: Logic 0; All inputs

Output high voltage: All inputs: Iout = –4mA

Output low voltage: All inputs: Iout = 4mA

VIL

–0.3

0.9 × VDDQ

–

+0.3

–

V

VOH

VOL

II

V

0.2

1.0

V

–1.0

µA

Input leakage current:

Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)

Operating temperature

+70

+85

°C

T_A(commercial)

T_A(industrial)

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Table 11: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 51 and 52

AC Characteristics

-75

-8

Parameter

Symbol

Min

Max

Min

Max

Units

Notes

CL = 3

CL = 2

^tAC (3)

^tAC (2)

^tAH

6

8

7

9

ns

ms

ns

^tCK

ns

Access time from CLK (pos. edge)

9

1

1.5

3

1

2.5

3

Address hold time

Address setup time

CLK high-level width

CLK low-level width

Clock cycle time

^tAS

^tCH

^tCL

3

CL = 3

CL = 2

^tCK (3)

^tCK (2)

^tCKH

^tCKS

^tCMH

^tCMS

^tDH

7.5

9.6

1

8

23

10

1

CKE hold time

2.5

1

2.5

1

CKE setup time

CS#, RAS#, CAS#, WE#, DQM hold time

CS#, RAS#, CAS#, WE#, DQM setup time

Data-in hold time

1.5

1

2.5

1

^tDS

1.5

2.5

Data-in setup time

CL = 3

CL = 2

^tHZ (3)

^tHZ (2)

^tLZ

6

9

7

9

10

Data-out High-Z time

1

2.5

1.8

44

1

Data-out Low-Z time

^tOH

2.5

1.8

48

72

20

Data-out hold time (load)

^tOHN

^tRAS

^tRC

^tRCD

^tREF

^tRFC

^tRP

^tRRD

^tT

^tWR

^tXSR

25

Data-out hold time (no load)

ACTIVE-to-PRECHARGE command

ACTIVE-to-ACTIVE command period

ACTIVE-to-READ or WRITE delay

Refresh period (8,192 rows)

AUTO REFRESH period

120,000

64

120,000

64

67.5

19

80

19

2

80

19

2

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

Transition time

0.3

15

80

1.2

0.5

15

80

1.2

7

31

20

WRITE recovery time

Exit SELF REFRESH to ACTIVE command

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46

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Table 12: AC Functional Characteristics

Notes: 5, 6, 8, 9,11 notes appear on page 51 and 52

Parameter

Symbol

-75

-8

Units

Notes

^tCCD

^tCKED

^tPED

^tDQD

^tDQM

^tDQZ

1

0

2

0

5

2

1

2

3

2

1

0

2

0

5

2

1

2

3

2

^tCK

17

14

READ/WRITE command to READ/WRITE command

CKE to clock disable or power-down entry mode

CKE to clock enable or power-down exit setup mode

DQM to input data delay

14

17

DQM to data mask during WRITEs

17

DQM to data High-Z during READs

^tDWD

^tDAL

17

WRITE command to input data delay

Data-in to ACTIVE command

15, 21

16, 21

17

^tDPL

Data-in to PRECHARGE command

^tBDL

Last data-in to burst STOP command

Last data-in to new READ/WRITE command

Last data-in to PRECHARGE command

LMR command to ACTIVE or REFRESH command

Data-out High-Z from PRECHARGE command

^tCDL

17

^tRDL

16, 21

25

^tMRD

^tROH(3)

^tROH(2)

CL = 3

CL = 2

17

Table 13:

IDD Specifications and Conditions (x16)

Notes: 1, 5, 6, 11, 13; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V

Max

Parameter/Condition

Symbol

-75

-8

Units

Notes

IDD1

65

60

mA

1, 18,

19

Operating current:

Active mode; BL = 1; READ or WRITE; ^tRC = ^tRC (MIN)

IDD2P

IDD2N

IDD3P

300

20

5

300

20

5

µA

mA

30

Standby current:

Power-down mode; All banks idle; CKE = LOW

Standby current:

Non-power-down mode; All banks idle; CKE = HIGH

1, 12,

19

Standby current:

Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in

progress

IDD3N

IDD4

25

90

25

85

mA

1, 12,

19

Standby current:

Active mode; CKE = HIGH; CS# = HIGH; All banks active after ^tRCD met;

No accesses in progress

1, 18,

19

Operating current:

Burst mode; READ or WRITE; All banks active, half DQs toggling every

cycle

Auto refresh current:

CKE = HIGH; CS# = HIGH

^tRFC = ^tRFC (MIN)

^tRFC = 7.8125µs

IDD5

IDD6

100

5

95

5

mA

1, 12,

18 19,

26

IZZ

10

µA

29, 30

Deep power-down

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Table 14:

IDD Specifications and Conditions (x32)

Notes: 1, 5, 6, 11, 13; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V

Max

Parameter/Condition

Symbol

-75

-8

Units

Notes

IDD1

95

90

mA

1, 18,

19

Operating current:

Active mode; BL = 1; READ or WRITE; ^tRC = ^tRC (MIN)

IDD2P

IDD2N

IDD3P

300

20

5

300

20

5

µA

mA

30

Standby current:

Power-down mode; All banks idle; CKE = LOW

Standby current:

Non-power-down mode; All banks idle; CKE = HIGH

1, 12,

19

Standby current:

Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in

progress

IDD3N

IDD4

25

115

95

mA

1, 12,

19

Standby current:

Active mode; CKE = HIGH; CS# = HIGH; All banks active after ^tRCD met;

No accesses in progress

120

100

1, 18,

19

Operating current:

Burst mode; READ or WRITE; All banks active, half DQs toggling every

cycle

Auto refresh current:

^tRFC = ^tRFC (MIN)

IDD5

1, 12,

18, 26

CKE = HIGH; CS# = HIGH

^tRFC = 7.8125µs

IDD6

IZZ

5

mA

µA

19, 27

29, 30

10

Deep power-down

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Table 15:

IDD7 – Self Refresh Current Options

Notes: 2, 28, 30; notes appear on page 51 and page 52

Temperature-Compensated Self Refresh

Parameter/Condition

Maximum

Temperature

Low IDD7

Option “L”

Standard IDD7

Units

85ºC

70ºC

45ºC

15ºC

85ºC

70ºC

45ºC

15ºC

85ºC

70ºC

45ºC

15ºC

85ºC

70ºC

45ºC

15ºC

85ºC

70ºC

45ºC

15ºC

220

175

140

125

200

150

130

115

185

140

120

115

175

125

115

110

170

120

110

105

300

210

190

180

275

180

160

150

265

160

140

255

150

130

125

250

140

120

115

µA

Self refresh current:

CKE = LOW – 4-bank refresh

Self refresh current:

CKE = LOW – 2-bank refresh

Self refresh current:

CKE = LOW – 1-bank refresh

Self refresh current:

CKE = LOW – Half-bank refresh

Self refresh current:

CKE = LOW – Quarter-bank refresh

Figure 33: Typical Self Refresh Current vs. Temperature

150

Full Array

1/2 Array

125

1/4 Array

Temperature (°C)

1/8 Array

100

75

50

25

0

1/16 Array

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

Table 16: Capacitance

Note: 2; notes appear on page 51 and 52

Parameter

Symbol

Min

Max

Units

CI1

CI2

CIO

1.5

2.0

4.5

6.0

pF

Input capacitance: CLK

Input capacitance: All other input-only balls

Input/output capacitance: DQs

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256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Notes

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +1.8V; T = 25°C; ball under test biased at

A

0.9V; f = 1 MHz.

3. IDD is dependent on output loading and cycle rates. Specified values are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range (–40°C ≤ T ≤ +85°C for T on IT parts) is

A

ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO

t

REFRESH command wake-ups should be repeated any time the REF refresh require-

ment is exceeded.

7. AC characteristics assume T = 1ns.

t

8. In addition to meeting the transition rate specification, the clock and CKE must tran-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured for 1.8V at 0.9V with equivalent load:

Q

20pF

Test loads with full DQ driver strength. Performance will vary with actual system DQ

bus capacitive loading, termination, and programmed drive strength.

t

10. HZ defines the time at which the output achieves the open circuit condition; it is not

t

a reference to VOH or VOL. The last valid data element will meet OH before going

High-Z.

11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover

t

point. If the input transition time is longer than T (MAX), then the timing is refer-

enced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.

12. Other input signals are allowed to transition no more than once every two clocks and

are otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly initialized.

t

14. Timing actually specified by CKS; clock(s) specified as a reference only at minimum

cycle rate.

t

15. Timing actually specified by WR plus RP; clock(s) specified as a reference only at

minimum cycle rate.

16. Timing actually specified by WR.

t

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The IDD current will increase or decrease proportionally according to the amount of

frequency alteration for the test condition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

t

21. Based on CK = 7.5ns for -75, CK = 8ns for -8, at CL = 3.

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51

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Notes

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for

a pulse width ≤ 3ns.

23. The clock frequency can only be changed during clock stop, power-down, or while in

a self-refresh mode.

t

24. Auto precharge mode only. The precharge timing budget ( RP) begins at 7ns for -8

after the first clock delay, after the last WRITE is executed. May not exceed limit set for

precharge mode.The clock frequency can only be changed during

25. Parameter guaranteed by design.

26. CKE is HIGH during refresh command period RFC (MIN) else CKE is LOW.

t

27. The IDD6 limit is actually a nominal value and does not result in a fail value.

28. Values for IDD7 for 70°C, 45°C, 15°C, and IDD7 1/2-bank and 1/4-bank are sampled

only. Values for IDD7 4-bank, 2-bank, and 1-bank for 85°C are 100 percent tested.

29. Deep power-down current is a nominal value at 25°C. This parameter is not tested.

30. Test conditions include 500ms delay prior to measurement.

t

31. Auto precharge mode only. The precharge timing budget ( RP) begins at 7.5ns for -75

and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto pre-

t

charge mode, at least one clock cycle is required during WR.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

52

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 34: Initialize and Load Mode Register

Tn + 1

T0

T1

To + 1

Tp + 1

Tq + 1

Tr + 1

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

CLK

CKE

t

CK

t

CKS

CKH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

t

CMS CMH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

1

COMMAND

NOP

PRE

AR

LMR

VALID

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

DQM

ADDR

A10

t

AS AH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

VALID

CODE

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

VALID

CODE

t

AS AH

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

BA0 = L,

BA1 = L

BBAA00==LL,,

BA0, BA1

DQ

BA1 = H

BA1 = L

High-Z

( (

((

))

((

))

((

))

((

))

((

))

((

))

)

T = 100µs

t

3

t

3

t

2

t

2

t

MRD

RFC

RP

Power-up:

V^DDand

CLK stable

Load Extended

Mode Register

Precharge

all banks

Load Mode

Register

DON’T CARE

Notes: 1. PRE = PRECHARGE command; AR = AUTO REFRESH command; LMR = LOAD MODE REGISTER

command.

2. Only NOPs or COMMAND INHIBITs may be issued during ^tRFC time.

3. At least one NOP or COMMAND INHIBIT is required during ^tMRD time.

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53

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 35: Power-Down Mode

T0

T1

T2

Tn + 1

Tn + 2

( (

) )

( (

) )

t

CK

t

CL

CLK

CKE

t

CH

t

CKS

( (

) )

t

CKS

CKH

t

CMS CMH

PRECHARGE

( (

) )

( (

) )

COMMAND

DQM

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

( (

) )

ADDR

A10

ROW

ALL BANKS

( (

) )

( (

) )

SINGLE BANK

t

AS

t

AH

( (

) )

( (

) )

BA0, BA1

DQ

BANK

BANK(S)

High-Z

( (

) )

Two clock cycles

Input buffers gated off while in

power-down mode

Precharge all

active banks

All banks idle

All banks idle, enter

power-down mode

Exit power-down mode

DON’T CARE

Notes: 1. Violating refresh requirements during power-down may result in a loss of data.

See Table 11 on page 46.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

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54

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 36: Clock Suspend Mode

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CK

t

CL

CLK

CKE

t

CH

t

CKS CKH

t

CKS

CKH

t

CMS

CMH

COMMAND

DQM

READ

NOP

WRITE

NOP

t

CMS

CMH

t

AS

t

AH

2

ADDR

COLUMN m

COLUMN e

t

AS

t

AH

A10

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

AC

t

OH

t

HZ

t

DS

t

DH

D

OUT

m

D

OUT m + 1

D

OUT

e

DOUT e + 1

DQ

t

LZ

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

55

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 37: Auto Refresh Mode

T0

T1

T2

Tn + 1

CL

To + 1

( (

) )

( (

) )

t

CLK

CKE

t

( (

CK

CH

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

COMMAND

DQM

PRECHARGE

NOP

ACTIVE

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

ADDR

A10

ROW

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

SINGLE BANK

t

AH

AS

( (

) )

( (

) )

BANK(S)

BA0, BA1

DQ

BANK

( (

) )

High-Z

( (

) )

( (

) )

t

RFC

RP

RFC

Precharge all

active banks

DON’T CARE

UNDEFINED

Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not

required.

See Table 11 on page 46.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

56

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 38: Self Refresh Mode

T0

T1

T2

Tn + 1

To + 1

To + 2

( (

) )

( (

) )

t

CL

CLK

CKE

t

( (

) )

( (

) )

t

CK

CH

t

> t

RAS

CKS

( (

) )

( (

) )

( (

) )

t

CKS

CKH

t

CMS

CMH

( (

) )

( (

) )

( (

) )

( (

) )

AUTO

REFRESH

AUTO

REFRESH

COMMAND

DQM

PRECHARGE

NOP

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

( (

) )

ADDR

A10

ALL BANKS

( (

) )

( (

) )

( (

) )

( (

) )

SINGLE BANK

t

AH

AS

( (

) )

( (

) )

( (

) )

( (

) )

BA0, BA1

DQ

BANK(S)

High-Z

( (

) )

( (

) )

t

XSR

RP

Precharge all

active banks

Enter self refresh mode

Exit self refresh mode

(Restart refresh time base)

CLK stable prior to exiting

self refresh mode

DON’T CARE

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

57

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 39: READ – without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CK

t

CL

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

COMMAND

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

t

CMH

CMS

DQM

t

AS

t

AH

ROW

COLUMN

m

ADDR

t

AS

t

AH

ALL BANKS

ROW

A10

SINGLE BANK

DISABLE AUTO PRECHARGE

BANK

t

AH

AS

BA0, BA1

BANK

BANK(S)

t

BANK

t

AC

t

OH

AC

OH

DOUT

m

DOUT

m

+ 1

DOUT

m

+ 2

DOUT m + 3

DQ

t

LZ

t

HZ

t

RCD

CL

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

58

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 40: READ – with Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMH

CMS

DQM

t

AS

AH

ROW

COLUMN m

ADDR

t

AS

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

AH

BA0, BA1

BANK

t

AC

OH

t

OH

AC

OH

DOUT

m

DOUT m + 1

DOUT m + 2

DOUT m + 3

DQ

t

LZ

t

HZ

t

RCD

CL

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4, CL = 2.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

59

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 41: Single READ – without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

2

COMMAND

ACTIVE

NOP

READ

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMH

CMS

DQM

t

AS

AH

ROW

COLUMN m

ADDR

t

AS

AH

ALL BANKS

SINGLE BANK

BANK(S)

ROW

A10

DISABLE AUTO PRECHARGE

BANK

t

AS

AH

BA0, BA1

BANK

t

OH

AC

DOUT m

DQ

t

LZ

t

HZ

t

RCD

CL

RP

t

RAS

t

RC

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.

2. PRECHARGE command not allowed or ^tRAS would be violated.

See Table 11 on page 46.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

60

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 42: Single READ – with Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

2

COMMAND

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

t

CMH

CMS

DQM

t

AS

AH

ROW

COLUMN m

ADDR

t

AS

AH

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BA0, BA1

BANK

t

AC

t

OH

DOUT m

DQ

t

CL

HZ

RCD

t

RP

RAS

t

RC

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.

2. PRECHARGE command not allowed or ^tRAS would be violated.

See Table 11 on page 46.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

61

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 43: Alternating Bank Read Accesses

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

DQM

ACTIVE

NOP

READ

t

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

2

COLUMN b

ROW

COLUMN

m

ADDR

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

A10

t

AS

t

AH

BANK 0

BANK 3

BA0, BA1

BANK 0

t

AC

t

AC

t

AC

t

AC

t

AC

t

AC

t

OH

t

OH

t

OH

t

OH

t

OH

D

OUT

m

D

OUT

m

+ 1

DOUT

m

+ 2

DOUT

m

+ 3

DOUT b

DQ

t

LZ

t

RCD - bank 0

t

RCD - bank 0

CL - bank 0

RP - bank 0

t

RAS - bank 0

t

RC - bank 0

t

RCD - bank 4

CL - bank 4

RRD

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4, CL = 2.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

62

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 44: READ – DQM Operation

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

COMMAND

ACTIVE

NOP

READ

NOP

t

CMH

CMS

DQM

t

AS

AH

ROW

COLUMN m

ADDR

t

AS

AH

ENABLE AUTO PRECHARGE

ROW

A10

DISABLE AUTO PRECHARGE

BANK

t

AS

AH

BA0, BA1

BANK

t

AC

t

OH

AC

OH

AC

OH

DQ

DOUT

m

D

OUT m + 2

DOUT m + 3

t

LZ

t

HZ

t

RCD

CL

DON’T CARE

UNDEFINED

Notes: 1. For this example, CL = 2.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

63

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 45: WRITE – without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

t

CMS

CMH

DQM

t

AH

AS

ADDR

ROW

t

ROW

BANK

COLUMN

m

AS

AH

ALL BANKS

ROW

t

A10

DISABLE AUTO PRECHARGE

BANK

SINGLE BANK

BANK

AS

AH

BANK

BA0, BA1

t

DS

DH

DS

DH

DS

DH

DS

DH

DIN

m

DIN

m

+ 1

DIN

m

+ 2

DIN m

+ 3

DQ

t

RP

t

2

RCD

WR

t

RAS

t

RC

DON’T CARE

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a manual PRECHARGE.

2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of fre-

quency.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

64

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 46: WRITE – with Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

DQM

t

AH

AS

ADDR

ROW

t

ROW

BANK

COLUMN m

AS

AH

ENABLE AUTO PRECHARGE

ROW

t

A10

AS

AH

BANK

BA0, BA1

t

DH

DS

DH

DS

DH

DS

DH

DS

DIN m

DIN m + 1

DIN m + 2

DIN m + 3

DQ

t

RP

t

2

RCD

WR

t

RAS

t

RC

DON’T CARE

UNDEFINED

Notes: 1. For this example, BL = 4.

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MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

65

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 47: Single WRITE – without Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

3

COMMAND

ACTIVE

NOP

WRITE

NOP

PRECHARGE

NOP

ACTIVE

NOP

t

CMH

CMS

DQM

t

AS

AH

ROW

COLUMN m

ADDR

t

AS

AH

ALL BANKS

ROW

A10

SINGLE BANK

BANK

DISABLE AUTO PRECHARGE

BANK

t

AS

AH

BA0, BA1

BANK

t

DH

DS

DIN m

DQ

t

2

WR

t

RCD

RP

t

RAS

t

RC

DON’T CARE

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. PRECHARGE command not allowed or ^tRAS would be violated.

See Table 11 on page 46.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

66

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 48: Single WRITE – with Auto Precharge

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

t

CH

t

CKS

CKH

CKE

t

CMS

CMH

3

NOP

COMMAND

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

t

CMH

CMS

DQM

t

AH

AS

ROW

COLUMN

m

ADDR

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

A10

t

AH

AS

BA0, BA1

BANK

t

DH

DS

DQ

DIN m

t

RCD

RP

WR

t

RAS

t

RC

DON’T CARE

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. WRITE command not allowed or ^tRAS would be violated.

See Table 11 on page 46.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

67

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 49: Alternating Bank Write Accesses

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

DQM

ACTIVE

NOP

WRITE

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

t

CMS

CMH

t

AH

AS

2

ROW

COLUMN m

COLUMN b

ADDR

t

AH

AS

ENABLE AUTO PRECHARGE

ROW

A10

t

AH

AS

BANK 0

BANK 1

t

BANK 1

BA0, BA1

BANK 0

t

DS DH

DIN m

DIN m + 1

DIN m + 2

DIN m + 3

DIN b

DIN b + 1

DIN b + 2

DIN m + 3

DQ

t

RCD - bank 0

WR - bank 0

RP - bank 0

RCD - bank 0

t

RAS - bank 0

t

RC - bank 0

WR - bank 1

t

RCD - bank 1

RRD

DON’T CARE

Notes: 1. For this example, BL = 4.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

68

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Timing Diagrams

Figure 50: WRITE – DQM Operation

T0

T1

T2

T3

T4

T5

T6

T7

t

CL

CK

CLK

CKE

t

CH

t

CKS

CKH

t

CMS

CMH

COMMAND

DQM

ACTIVE

NOP

WRITE

t

NOP

t

CMS CMH

t

AH

AS

ADDR

ROW

t

COLUMN m

AS

AH

ENABLE AUTO PRECHARGE

ROW

t

A10

DISABLE AUTO PRECHARGE

BANK

AS

AH

BA0, BA1

BANK

t

DS

DH

DS

DH

DS

DH

DIN m

DIN m + 2

DIN m + 3

DQ

t

RCD

DON’T CARE

Notes: 1. For this example, BL = 4.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

69

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Package Dimensions

Figure 51: 54-Ball VFBGA (8mm x 9mm)

0.65 0.05

SEATING

PLANE

A

0.10 A

SOLDER BALL MATERIAL:

96.5% Sn, 3% Ag, 0.5% Cu

SUBSTRATE MATERIAL: PLASTIC LAMINATE

MOLD COMPOUND: EPOXY NOVOLAC

54X Ø0.45

SOLDER BALL

DIAMETER REFERS

TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER

IS 0.42 ON A 0.40

6.40

0.80

MICRON LOGO

TO BE LASED

BALL A1 ID

TYP

BALL A1

SMD BALL PAD.

4.50 0.05

BALL A9

6.40

C

9.00 0.10

L

3.20

0.80 TYP

C

L

3.20

4.00 0.05

8.00 0.10

1.00 MAX

Notes: 1. All dimensions are in millimeters.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

70

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Package Dimensions

Figure 52: 90-Ball VFBGA (8mm x 13mm)

0.65 0.05

SEATING PLANE

SOLDER BALL MATERIAL:

96.5% Sn, 3%Ag, 0.5% Cu

A

0.10 A

SUBSTRATE MATERIAL:

PLASTIC LAMINATE

MOLD COMPOUND:

EPOXY NOVOLAC

90X Ø0.45

DIMENSIONS APPLY

TO SOLDER BALLS POST

REFLOW. THE PRE-

REFLOW DIAMETER IS

0.42 ON A 0.40 SMD

BALL PAD

6.40

0.80 TYP

BALL A1 ID

BALL A1

BALL A9

11.20 0.10

C

L

13.00 0.10

5.60 0.05

6.50 0.05

C

L

1.00 MAX

3.20

4.00 0.05

8.00 0.10

Notes: 1. All dimensions are in millimeters.

®

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

MT48H16M16LF_2.fm - Rev F 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

71


型号：	MT48H16M16LFB5-75G
厂家：	MICRON TECHNOLOGY
描述：	256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM 256MB ： 16梅格×16 ， 8梅格×32移动SDRAM 动态存储器
文件：	总71页 (文件大小：1814K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT48H16M16LFB5-75G [MICRON]

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