MT48LC16M8A2FB-7EL [MICRON]
SYNCHRONOUS DRAM; 同步DRAM
| 型号： | MT48LC16M8A2FB-7EL |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | SYNCHRONOUS DRAM |
| 文件： | 总59页 (文件大小：1835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128Mb: x4, x8, x16
SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
SYNCHRONOUS
DRAM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
x16 x8 x4
-
-
-
-
V
DQ0
DD
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7 NC
NC DQ0
DQ15
VssQ
DQ14
DQ13
-
NC
DQ6 DQ3
-
NC
DQ5 NC
-
NC
DQ4 DQ2
-
NC
-
NC
-
NC
DQ0 DQ1
-
NC
NC DQ2
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
-
NC
-
NC
VDDQ
DQ12
DQ11
VssQ
DQ10
DQ9
VDDQ
DQ8
Vss
-
NC
-
NC
-
V
DD
Q
9
• LVTTL-compatible inputs and outputs
• Single +3.3V 0.3V power supply
NC DQ5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ1 DQ3 DQ6
-
-
NC
-
-
NC
-
-
VssQ
NC
-
NC DQ7
OPTIONS
• Configurations
MARKING
-
VDD
-
-
NC
-
NC DQML
NC
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DQMH DQM DQM
-
-
-
-
-
-
-
-
-
-
-
-
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
32M4
16M8
8M16
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
• WRITE Recovery (tWR)
-
tWR = “2 CLK”1
A2
-
-
• Package/Pinout
-
-
Plastic Package – OCPL2
54-pin TSOP II (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
DD
-
TG
FB 3,6
FC 3,6
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4 16 Meg x 8 8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
-8E 3,4,5
-75
-7E
Configuration
Refresh Count
Row Addressing
Bank Addressing
4K
4K
4K
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
• Self Refresh
Standard
Column Addressing 2K (A0–A9, A11)
None
L
Low power
KEY TIMING PARAMETERS
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
None
IT 3
SPEED
CLOCK
ACCESS TIME SETUP HOLD
GRADE FREQUENCY CL = 2* CL = 3* TIME
TIME
Part Number Example:
-7E
-7E
-75
-8E3,4,5
-75
-8E3 ,4,5
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
–
5.4ns
–
–
6ns
6ns
5.4ns
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
MT48LC16M8A2TG-7E
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
–
5.4ns
6ns
–
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatability.
–
6. See page 59 for FBGA Device Marking Table.
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128Mb: x4, x8, x16
SDRAM
FBGA BALL ASSIGNMENT
(Top View)
32 Meg x 4
16 Meg x 8
8 x 16mm and 11 x 13mm
8 x 16mm and 11 x 13mm
2
4
6
8
2
4
6
8
1
3
5
7
1
3
5
7
V
DD
DQ7
NC
VDD
A
B
C
D
E
A
B
C
D
E
Vss
VssQ
DQ3
NC
NC
NC
Vss
VssQ
DQ6
NC
DQ0
NC
NC
NC
VDD
Q
VDDQ
VssQ
NC
VssQ
DQ2
NC
VDDQ
DQ0
NC
V
DD
DQ5
NC
Q
DQ1
NC
NC
NC
VssQ
NC
VssQ
DQ4
NC
VDD
Q
VDDQ
DQ1
DQ3
F
VssQ
NC
F
VssQ
NC
VDDQ
DQ2
NC
VDDQ
G
H
J
G
H
J
NC
NC
NC
NC
NC
Vss
DQM
CK
NC
Vss
NC
NC
NC
VDD
WE#
VDD
WE#
RAS#
NC
CAS#
NC
DQM
CK
CAS#
NC
NC
NC
NC
K
L
K
L
NC
NC
RAS#
NC
CKE
A9
CS#
BA0
CKE
CS#
BA0
M
N
P
M
N
P
BA1
A0
BA1
A0
A9
A7
A11
A8
A11
A8
A7
A10
A1
A10
A1
A6
A2
A6
A2
A5
A5
R
R
VDD
VDD
A3
A3
A4
A4
Vss
Vss
Depopulated Balls
Depopulated Balls
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
2
128Mb: x4, x8, x16
SDRAM
128Mb SDRAM PART NUMBERS
PART NUMBER
ARCHITECTURE
32 Meg x 4
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
16 Meg x 8
8 Meg x 16
A0-A11 select the row). The address bits registered
coincident with the READ or WRITE command are used
to select the starting column location for the burst
access.
The SDRAM provides for programmable READ
or WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
MT48LC32M4A2TG
MT48LC32M4A2FC*
MT48LC32M4A2FB*
MT48LC16M8A2TG
MT48LC16M8A2FC*
MT48LC16M8A2FB*
MT48LC8M16A2TG
*See page 59 for FBGA Device Marking Table.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while access-
ing one of the other three banks will hide the precharge
cycles and provide seamless high-speed, random-access
operation.
The 128Mb SDRAM is designed to operate in 3.3V
memorysystems.Anautorefreshmodeisprovided,along
with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
GENERAL DESCRIPTION
The Micron® 128Mb SDRAM is a high-speed CMOS,
dynamicrandom-accessmemorycontaining134,217,728
bits. It is internally configured as a quad-bank DRAM
withasynchronousinterface(allsignalsareregisteredon
thepositiveedgeoftheclocksignal, CLK). Eachofthex4’s
33,554,432-bit banks is organized as 4,096 rows by 2,048
columns by 4 bits. Each of the x8’s 33,554,432-bit banks is
organized as 4,096 rows by 1,024 columns by 8 bits. Each
of the x16’s 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks in order to hide precharge time and the
capabilitytorandomlychangecolumnaddressesoneach
clock cycle during a burst access.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coinci-
dent with the ACTIVE command are used to select the
bank and row to be accessed (BA0, BA1 select the bank;
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
3
128Mb: x4, x8, x16
SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 32 Meg x 4 ................
Functional Block Diagram – 16 Meg x 8 ................
Functional Block Diagram – 8 Meg x 16 ................
Pin Descriptions .....................................................
5
6
7
8
Concurrent Auto Precharge .............................. 26
Truth Table 2 (CKE) ................................................ 28
Truth Table 3 (Current State, Same Bank) ..................... 29
Truth Table 4 (Current State, Different Bank)................. 31
Absolute Maximum Ratings ................................... 33
DC Electrical Characteristics
and Operating Conditions ................................... 33
IDD Specifications and Conditions ......................... 33
Capacitance ............................................................ 34
Functional Description.........................................
Initialization ......................................................
Register Definition ............................................
mode register ................................................
Burst Length............................................
9
9
9
9
9
Burst Type ............................................... 10
CAS Latency ............................................ 11
AC Electrical Characteristics and Recommended
Operating Conditions (Timing Table) ............. 34
Operating Mode ...................................... 11
Write Burst Mode .................................... 11
Timing Waveforms
Initialize and Load mode register...................... 37
Power-Down Mode ............................................ 38
Clock Suspend Mode ......................................... 39
Auto Refresh Mode ............................................ 40
Self Refresh Mode .............................................. 41
Reads
Read – Without Auto Precharge ................... 42
Read – With Auto Precharge ........................ 43
Single Read – Without Auto Precharge ........ 44
Single Read – With Auto Precharge ............. 45
Alternating Bank Read Accesses ................... 46
Read – Full-Page Burst .................................. 47
Read – DQM Operation ................................ 48
Writes
Commands ............................................................. 12
Truth Table 1 (Commands and DQM Operation) ............ 12
Command Inhibit ............................................. 13
No Operation (NOP).......................................... 13
Load mode register ............................................ 13
Active ................................................................ 13
Read ................................................................ 13
Write ................................................................ 13
Precharge ........................................................... 13
Auto Precharge .................................................. 13
Burst Terminate ................................................. 13
Auto Refresh ...................................................... 14
Self Refresh ........................................................ 14
Operation................................................................ 15
Bank/Row Activation ........................................ 15
Reads ................................................................ 16
Writes ................................................................ 22
Precharge ........................................................... 24
Power-Down ...................................................... 24
Clock Suspend ................................................... 25
Burst Read/Single Write .................................... 25
Write – Without Auto Precharge ................. 49
Write – With Auto Precharge ....................... 50
Single Write – Without Auto Precharge....... 51
Single Write – With Auto Precharge ............ 52
Alternating Bank Write Accesses ................. 53
Write – Full-Page Burst ................................. 54
Write – DQM Operation .............................. 55
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
4
128Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 4 SDRAM
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
BANK2
CAS#
RAS#
BANK1
REFRESH
COUNTER
12
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
12
BANK0
MEMORY
ARRAY
1
1
4096
DQM
12
(4,096 x 2,048 x 4)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
4096
4
DQ0-
DQ3
I/O GATING
2
4
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A11,
BA0, BA1
ADDRESS
REGISTER
14
DATA
INPUT
REGISTER
2
4
2048
(x4)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
11
11
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
5
128Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 8 SDRAM
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
BANK2
CAS#
RAS#
BANK1
REFRESH
COUNTER
12
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
12
BANK0
MEMORY
ARRAY
1
1
4096
DQM
12
(4,096 x 1,024 x 8)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
4096
8
DQ0-
DQ7
I/O GATING
2
8
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A11,
BA0, BA1
ADDRESS
REGISTER
14
DATA
INPUT
REGISTER
2
8
1024
(x8)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
10
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
6
128Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 16 SDRAM
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
BANK2
CAS#
RAS#
BANK1
REFRESH
COUNTER
12
MODE REGISTER
12
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
12
BANK0
MEMORY
ARRAY
2
2
4096
DQML,
DQMH
12
(4,096 x 512 x 16)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
4096
16
DQ0-
DQ15
I/O GATING
2
16
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A11,
BA0, BA1
ADDRESS
REGISTER
14
DATA
INPUT
REGISTER
2
16
512
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
7
128Mb: x4, x8, x16
SDRAM
PIN DESCRIPTIONS
TSOP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
38
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37
CKE
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row
active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
CS#
Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is regis-
tered HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
16, 17, 18
WE#, CAS#,
RAS#
Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
39
x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
15, 39
x16: DQML,
DQMH
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled HIGH
during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and
DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH
corresponds to DQ8-DQ15. DQML and DQMH are considered same state
when referenced as DQM.
20, 21
BA0, BA1
A0-A11
Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
23-26, 29-34, 22, 35
Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-
address A0-A11) and READ/WRITE command (column-address A0-A9,
A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10
is sampled during a PRECHARGE command to determine if all banks are
to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (A10
[LOW]). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
44, 45, 47, 48, 50, 51, 53
2, 5, 8, 11, 44, 47, 50, 53
5, 11, 44, 50
40
NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4).
x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
x4: I/O Data Input/Output: Data bus for x4.
DQ0-DQ7
DQ0-DQ3
NC
–
–
No Connect: These pins should be left unconnected.
Address input (A12) for the 256Mb and 512Mb devices
36
NC
3, 9, 43, 49
V
DDQ
Supply DQ Power: Isolated DQ power on the die for improved noise immunity.
6, 12, 46, 52
V
SSQ
Supply DQ Ground: Isolated DQ ground on the die for improved noise
immunity.
1, 14, 27
V
DD
SS
Supply Power Supply: +3.3V 0.3V.
Supply Ground.
28, 41, 54
V
128Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
©2001, Micron Technology, Inc.
8
128Mb: x4, x8, x16
SDRAM
FUNCTIONAL DESCRIPTION
Register Definition
In general, the 128Mb SDRAMs (8 Meg x 4 x 4 banks,
4 Meg x 8 x 4 banks and 2 Meg x 16 x 4 banks) are quad-
bank DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edgeoftheclocksignal, CLK). Eachofthex4’s33,554,432-
bit banks is organized as 4,096 rows by 2,048 columns by
4 bits. Each of the x8’s 33,554,432-bit banks is organized
as 4,096 rows by 1,024 columns by 8 bits. Each of the x16’s
33,554,432-bit banks is organized as 4,096 rows by 512
columns by 16 bits.
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in
Figure 1. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode, and
M10 and M11 are reserved for future use.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITEcommand. Theaddressbitsregisteredcoincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-
A11 select the row). The address bits (x4: A0-A9, A11; x8:
A0-A9; x16: A0-A8) registered coincident with the READ
or WRITE command are used to select the starting col-
umn location for the burst access.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating ei-
ther of these requirements will result in unspecified op-
eration.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the maxi-
mum number of column locations that can be accessed
for a given READ or WRITE command. Burst lengths of 1,
2, 4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
Priortonormaloperation, theSDRAMmustbeinitial-
ized. The following sections provide detailed informa-
tion covering device initialization, register definition,
command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Once
power is applied to VDD and VDDQ (simultaneously) and
the clock is stable (stable clock is defined as a signal
cycling within timing constraints specified for the clock
pin), the SDRAM requires a 100µs delay prior to issuing
anycommandotherthanaCOMMANDINHIBITorNOP.
Starting at some point during this 100µs period and con-
tinuing at least through the end of this period, COM-
MAND INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must then be precharged, thereby placing the
device in the all banks idle state.
Reserved states should not be used, as unknown op-
eration or incompatibility with future versions may re-
sult.
WhenaREADorWRITEcommandisissued, ablockof
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A9, A11 (x4), A1-A9 (x8), or A1-A8 (x16) when the burst
length is set to two; by A2-A9, A11 (x4), A2-A9 (x8), or A2-
A8(x16)whentheburstlengthissettofour;andbyA3-A9,
A11 (x4), A3-A9 (x8), or A3-A8 (x16) when the burst length
is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the
boundary is reached.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register pro-
gramming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying any
operational command.
128Mb: x4, x8, x16 SDRAM
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128Mb: x4, x8, x16
SDRAM
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
Starting Column Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
A11
A8
A6 A5 A4
A1
Address Bus
A10
A7
A3 A2
A0
A9
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
11
9
8
6
5
4
1
10
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
A2 A1 A0
*Should program
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
8
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
n = A0-A11/9/8
(location 0-y)
Not Supported
Cn…
Burst Type
M3
0
Sequential
Interleaved
NOTE: 1. For full-page accesses: y = 2,048 (x4), y = 1,024
(x8), y = 512 (x16).
1
2. For a burst length of two, A1-A9, A11 (x4), A1-A9
(x8) or A1-A8 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9
(x8) or A2-A8 (x16) select the block-of-four burst;
A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-
A9 (x8) or A3-A8 (x16) select the block-of-eight
burst; A0-A2 select the starting column within the
block.
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
5. For a full-page burst, the full row is selected and
A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select
the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9
(x8) or A0-A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Figure 1
Mode Register Definition
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128Mb: x4, x8, x16
SDRAM
CAS Latency
Operating Mode
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with fu-
ture versions may result.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in
Figure 2. Table 2 below indicates the operating frequen-
cies at which each CAS latency setting can be used.
Reserved states should not be used as unknown op-
eration or incompatibility with future versions
may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
Table 2
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
T0
T1
T2
T3
CLK
CAS
LATENCY = 2
CAS
LATENCY = 3
SPEED
COMMAND
READ
NOP
t
NOP
t
-7E
-75
-8E
≤ 133
≤ 100
≤ 100
≤ 143
≤ 133
≤ 125
LZ
OH
D
OUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
D
OUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
Figure 2
CAS Latency
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128Mb: x4, x8, x16
SDRAM
Commands
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
X
DQs NOTES
COMMAND INHIBIT (NOP)
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
NO OPERATION (NOP)
X
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
X
Bank/Row
Bank/Col
X
X
3
4
4
8
8
H
H
H
L
L/H
L/H
X
L
Bank/Col Valid
H
H
L
L
X
Code
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
X
X
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
H
X
6, 7
LOAD MODE REGISTER
L
–
L
–
–
L
–
–
L
–
–
X
L
Op-Code
X
2
8
8
Write Enable/Output Enable
Write Inhibit/Output High-Z
–
–
Active
High-Z
–
H
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read
from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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128Mb: x4, x8, x16
SDRAM
COMMAND INHIBIT
whether or not auto precharge is used. If auto precharge
is selected, the row being accessed will be precharged at
the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subsequent ac-
cesses. Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level ap-
pearing coincident with the data. If a given DQM signal is
registeredLOW, thecorrespondingdatawillbewrittento
memory; if the DQM signal is registered HIGH, the corre-
sponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
TheCOMMANDINHIBITfunctionpreventsnewcom-
mands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effec-
tively deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to per-
form a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being regis-
tered during idle or wait states. Operations already in
progress are not affected.
PRECHARGE
The PRECHARGE command is used to deactivate the
openrowinaparticularbankortheopenrowinallbanks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks
aretobeprecharged, andinthecasewhereonlyonebank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands
being issued to that bank.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11. See
mode register heading in the Register Definition section.
The LOAD MODE REGISTER command can only be is-
sued when all banks are idle, and a subsequent execut-
able command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row. This
row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a
different row in the same bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accom-
plished by using A10 to enable auto precharge in con-
junction with a specific READ or WRITE command. A
PRECHARGE of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where auto precharge does not
apply. Auto precharge is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (tRP) is completed. This is determined as
if an explicit PRECHARGE command was issued at the
earliest possible time, as described for each burst type in
the Operation section of this data sheet.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) selects the starting
column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge
is selected, the row being accessed will be precharged at
the end of the READ burst; if auto precharge is not se-
lected, therowwillremainopenforsubsequentaccesses.
Read data appears on the DQs subject to the logic level on
the DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQM signal was registered
LOW, the DQs will provide valid data.
BURST TERMINATE
WRITE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) selects the starting
column location. The value on input A10 determines
128Mb: x4, x8, x16 SDRAM
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128Mb: x4, x8, x16
SDRAM
retains data without external clocking. The SELF RE-
FRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of CKE,
which must remain LOW.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH
command. The AUTO REFRESH command should not
be issued until the minimum tRP has been met after the
PRECHARGE command as shown in the operation sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
duringanAUTOREFRESHcommand.The128MbSDRAM
requires 4,096 AUTO REFRESH cycles every 64ms (tREF),
regardless of width option. Providing a distributed AUTO
REFRESH command every 15.625µs will meet the refresh
requirementandensurethateachrowisrefreshed. Alter-
natively, 4,096AUTOREFRESHcommandscanbeissued
in a burst at the minimum cycle rate (tRFC), once every
64ms.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
t
self refresh mode for a minimum period equal to RAS
and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
tXSR because time is required for the completion of any
internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row re-
fresh counter.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powereddown.Whenintheselfrefreshmode,theSDRAM
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128Mb: x4, x8, x16
SDRAM
CLK
CKE
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated (see Figure 3).
HIGH
CS#
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a tRCD specification
of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
BANK
ADDRESS
BA0, BA1
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimumtimeintervalbetweensuccessiveACTIVEcom-
mands to different banks is defined by tRRD.
Figure 3
Activating a Specific Row in a
Specific Bank
T0
T1
T2
T3
T4
CLK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD
DON’T CARE
Figure 4
t
t
t
<
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3
128Mb: x4, x8, x16 SDRAM
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128Mb: x4, x8, x16
SDRAM
READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequentREADcommand,anddatafromafixed-length
READ burst may be immediately followed by data from a
READcommand. Ineithercase, acontinuousflowofdata
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one.
The starting column and bank addresses are provided
with the READ command, and auto precharge is either
enabledordisabledforthatburstaccess.Ifautoprecharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mandsusedinthefollowingillustrations, autoprecharge
is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.
T0
T1
T2
T3
CLK
CLK
CKE
CS#
HIGH
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 2
RAS#
CAS#
WE#
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
A0-A9, A11: x4
A0-A9: x8
COLUMN
ADDRESS
DOUT
DQ
A0-A8: x16
t
AC
A11: x8
CAS Latency = 3
A9, A11: x16
DON’T CARE
UNDEFINED
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
Figure 6
CAS Latency
BANK
ADDRESS
BA0,1
Figure 5
READ Command
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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16
128Mb: x4, x8, x16
SDRAM
This is shown in Figure 7 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of four
or the last desired of a longer burst. The 128Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architec-
ture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed
random read accesses can be performed to the same
bank, as shown in Figure 8, or each subsequent READ
may be performed to a different bank.
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
CAS Latency = 3
DON’T CARE
NOTE:
Each READ command may be to any bank. DQM is LOW.
Figure 7
Consecutive READ Bursts
128Mb: x4, x8, x16 SDRAM
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128Mb: x4, x8, x16
SDRAM
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
D
OUT
D
OUT
DOUT
n
a
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 3
NOTE:
Each READ command may be to any bank. DQM is LOW.
DON’T CARE
Figure 8
Random READ Accesses
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
18
128Mb: x4, x8, x16
SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by data
from a WRITE command (subject to bus turnaround
limitations). The WRITE burst may be initiated on the
clock edge immediately following the last (or last de-
sired)dataelementfromtheREADburst, providedthatI/
O contention can be avoided. In a given system design,
there may be a possibility that the device driving the
input data will go Low-Z before the SDRAM DQs go High-
Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or re-
main High-Z), regardless of the state of the DQM signal,
provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 in Figure 10,
then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle, and Figure 10 shows the case where the additional
NOP is needed.
T0
T1
T2
T3
T4
T5
T0
T1
T2
T3
T4
CLK
CLK
DQM
DQM
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
READ
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COL b
BANK,
COL n
BANK,
COL n
BANK,
COL b
t
HZ
t
CK
D
OUT
n
DIN
b
DQ
t
HZ
t
DS
D
OUT
n
DIN b
DQ
t
DS
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
DON’T CARE
Figure 10
READ to WRITE With
Extra Clock Cycle
Figure 9
READ to WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
19
128Mb: x4, x8, x16
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannotbeissueduntil tRPismet. Notethatpartoftherow
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
D
OUT
D
n + 1
OUT
DOUT
DOUT
n + 3
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
CAS Latency = 3
DON’T CARE
NOTE: DQM is LOW.
Figure 11
READ to PRECHARGE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
20
128Mb: x4, x8, x16
SDRAM
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
burstsmaybetruncatedwithaBURSTTERMINATEcom-
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element n + 3 is the last desired data ele-
ment of a longer burst.
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COL n
D
OUT
D
n + 1
OUT
DOUT
DOUT
n + 3
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COL n
D
OUT
DOUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
CAS Latency = 3
NOTE:
DQM is LOW.
DON’T CARE
Figure 12
Terminating a READ Burst
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
21
128Mb: x4, x8, x16
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
command applies to the new command. An example is
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
thesamebank, asshowninFigure16, oreachsubsequent
WRITE may be performed to a different bank.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequentWRITEcommand, anddataforafixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
T0
T1
T2
T3
CLK
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
D
IN
DIN
n + 1
n
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
CLK
CKE
CS#
HIGH
T0
T1
T2
CLK
RAS#
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
CAS#
WE#
BANK,
COL n
BANK,
COL b
A0-A9, A11: x4
A0-A9: x8
COLUMN
ADDRESS
A0-A8: x16
DIN
DIN
DIN
b
n
n + 1
A11: x8
A9, A11: x16
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
NOTE:
DQM is LOW. Each WRITE
command may be to any bank.
DON’T CARE
BANK
ADDRESS
BA0,1
Figure 15
WRITE to WRITE
Figure 13
WRITE Command
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
22
128Mb: x4, x8, x16
SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be
executed. An example is shown in Figure 17. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst.
least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the DQM
signal must be used to mask input data for the clock edge
prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure
18. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
t
PRECHARGE command should be issued WR after the
clock edge at which the last desired input data element is
registered. The auto precharge mode requires a tWR of at
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
WRITE
WRITE
WRITE
WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
t
t
WR@ CK 15ns
DQM
D
IN
D
IN
D
IN
DIN
x
t
RP
DQ
m
n
a
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
NOTE:
Each WRITE command may be to any bank.
DQM is LOW.
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
DQ
Figure 16
Random WRITE Cycles
t
t
WR@ CK < 15ns
DQM
T0
T1
T2
T3
T4
T5
t
RP
CLK
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
t
WR
D
n
IN
DIN
n + 1
DQ
BANK,
COL n
BANK,
COL b
NOTE:
DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.
DIN
n
DIN
n + 1
DOUT
b
DOUT
b + 1
DQ
DON’T CARE
NOTE:
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 18
WRITE to PRECHARGE
Figure 17
WRITE to READ
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
23
128Mb: x4, x8, x16
SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coinci-
dent with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock
previous to the BURST TERMINATE command. This is
shown in Figure 19, where data n is the last desired data
element of a longer burst.
PRECHARGE
The PRECHARGE command (see Figure 20) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the
PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE com-
mands being issued to that bank.
T0
T1
T2
CLK
POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
(ADDRESS)
(DATA)
DIN
n
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). See Figure 21.
Figure 19
Terminating a WRITE Burst
CLK
( (
) )
CLK
( (
) )
CKE
CS#
HIGH
> t
CKS
t
CKS
CKE
( (
) )
( (
) )
( (
) )
COMMAND
NOP
NOP
ACTIVE
RAS#
t
All banks idle
RCD
Input buffers gated off
t
RAS
t
RC
CAS#
WE#
Enter power-down mode.
Exit power-down mode.
DON’T CARE
Figure 21
Power-Down
A0-A9
A10
All Banks
Bank Selected
BANK
ADDRESS
BA0,1
Figure 20
PRECHARGE Command
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
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©2001, Micron Technology, Inc.
24
128Mb: x4, x8, x16
SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended. (See examples in Figures 22 and 23.)
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commandsaccesscolumnsaccordingtotheprogrammed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).
T0
T1
T2
T3
T4
T5
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
CLK
CKE
INTERNAL
CLOCK
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL n
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
D
n
IN
D
n + 1
IN
DIN
n + 2
DIN
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
NOTE: For this example, burst length = 4 or greater, and DM
DON’T CARE
is LOW.
Figure 22
Clock Suspend During WRITE Burst
Figure 23
Clock Suspend During READ Burst
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
25
128Mb: x4, x8, x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
theSDRAMsupportsCONCURRENTAUTOPRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The PRECHARGE to
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
BANK n
t
RP - BANK n
RP - BANK m
Internal
States
Precharge
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
a
OUT
D
a + 1
OUT
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page
Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR - BANK m
BANK n
t
RP - BANK
n
Internal
States
Write-Back
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
26
128Mb: x4, x8, x16
SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appear-
ing CAS latency later. The PRECHARGE to bank n will
4. Interrupted by a WRITE (with or without auto
precharge):AWRITEto bankm willinterruptaWRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
t
t
begin after WR is met, where WR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
the WRITE to bank
m
is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
RP - BANK m
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
IN
D
a + 1
IN
D
OUT
DOUT
d + 1
a
d
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
WR - BANK m
Write-Back
Page Active
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
a + 2
IN
DIN
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
a
d
NOTE: 1. DQM is LOW.
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
27
128Mb: x4, x8, x16
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
L
L
H
L
Power-Down
Self Refresh
X
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
X
Clock Suspend
Power-Down
Self Refresh
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
5
6
7
Exit Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
H
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
Clock Suspend Entry
H
H
See Truth Table 3
NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at
clock edge n + 1.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
28
128Mb: x4, x8, x16
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)
NOTES
Any
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
L
AUTO REFRESH
7
7
L
L
LOAD MODE REGISTER
L
H
L
L
PRECHARGE
11
10
10
8
H
H
L
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
Row Active
L
H
L
L
Read
(Auto
H
H
L
H
L
10
10
8
L
Precharge
Disabled)
Write
H
H
L
L
H
H
H
L
L
9
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
10
10
8
(Auto
L
Precharge
Disabled)
H
H
L
H
L
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
29
128Mb: x4, x8, x16
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
30
128Mb: x4, x8, x16
SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)
NOTES
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
Idle
Row
Activating,
Active, or
Precharging
Read
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7
7
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 10
7, 11
9
Precharge
Disabled)
Write
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 12
7, 13
9
Precharge
Disabled)
Read
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 8, 14
7, 8, 15
9
L
H
H
L
L
Write
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 8, 16
7, 8, 17
9
L
H
L
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
31
128Mb: x4, x8, x16
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been
interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
32
128Mb: x4, x8, x16
SDRAM
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD/VDDQ Supply
Relative to VSS ........................................ -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ........................................ -1V to +4.6V
Operating Temperature,
TA (commercial) ........................................ 0°C to +70°C
Operating Temperature,
TA (extended; IT parts) ......................... -40°C to +85°C
Storage Temperature (plastic) ................ -55°C to +150°C
Power Dissipation .......................................................... 1W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes appear on page 36; VDD/VDDQ = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
VDD/VDDQ
VIH
MIN
3
MAX UNITS NOTES
Supply Voltage
3.6
VDD + 0.3
0.8
V
V
V
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
2
22
22
VIL
-0.3
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
II
-5
5
µA
Output Leakage Current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
V
Output Levels:
VOH
2.4
–
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOL
–
0.4
V
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1, 5, 6, 11, 13; notes appear on page 36; VDD/VDDQ = +3.3V 0.3V)
MAX
-75 -8E UNITS NOTES
PARAMETER/CONDITION
SYMBOL -7E
Operating Current: Active Mode;
IDD1
IDD2
IDD3
160 150 140
mA
mA
mA
3, 18,
19, 32
Burst = 2; READ or WRITE; tRC = tRC (MIN)
Standby Current: Power-Down Mode;
All banks idle; CKE = LOW
2
2
2
32
Standby Current: Active Mode;
50
50
40
3, 12,
19, 32
CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active
IDD4
165 150 140
330 310 270
mA
3, 18,
19, 32
Auto Refresh Current
tRFC = tRFC (MIN)
tRFC = 15.625µs
IDD5
IDD6
mA
mA
3, 12,
18, 19,
32, 33
CKE = HIGH; CS# = HIGH
3
3
3
Self Refresh Current:
Standard
IDD7
IDD7
2
1
2
1
2
1
mA
mA
4
CKE ≤ 0.2V
Low power (L)
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
33
128Mb: x4, x8, x16
SDRAM
CAPACITANCE
(Note: 2; notes appear on page 36)
PARAMETER - TSOP “TG” Package
Input Capacitance: CLK
SYMBOL
CI1
MIN
2.5
MAX UNITS NOTES
3.5
3.8
6.0
pF
pF
pF
29
30
31
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
CI2
2.5
CIO
4.0
PARAMETER - FBGA “FB” Package
Input Capacitance: CLK
SYMBOL
CI1
MIN
1.5
MAX UNITS NOTES
3.5
3.8
6.0
pF
pF
pF
34
35
36
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
CI2
1.5
CIO
3.0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 36)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
-7E
-75
MAX
-8E
MIN
SYMBOL MIN
MAX
5.4
MIN
MAX
6
6
UNITS NOTES
t
CL = 3
CL = 2
AC(3)
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
–
27
t
AC(2)
5.4
t
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
t
AS
CH
t
3
t
CL
3
t
t
CL = 3
CL = 2
CK(3)
CK(2)
8
23
23
7.5
0.8
1.5
0.8
1.5
0.8
1.5
10
1
t
CKE hold time
CKH
0.8
1.5
0.8
1.5
0.8
1.5
t
CKE setup time
CKS
2
t
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
CMH
1
t
CMS
2
t
DH
1
t
Data-in setup time
DS
2
t
t
Data-out high-impedance time
CL = 3
CL = 2
HZ(3)
HZ(2)
5.4
5.4
5.4
6
6
6
10
10
t
Data-out low-impedance time
Data-out hold time (load)
LZ
1
3
1
3
1
3
t
OH
t
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
OH
1.8
37
60
15
1.8
44
66
20
1.8
50
70
20
28
N
t
RAS
120,000
64
120,000
64
120,000
64
t
RC
t
RCD
t
REF
t
RFC
66
15
14
0.3
66
20
15
0.3
70
20
20
0.3
t
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
RP
t
RRD
t
T
1.2
1.2
1.2
7
t
WRITE recovery time
WR 1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
24
14
15
75
15
80
ns
ns
25
20
t
Exit SELF REFRESH to ACTIVE command
XSR
67
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
34
128Mb: x4, x8, x16
SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 36)
PARAMETER
SYMBOL
-7E -75 -8E UNITS NOTES
t
t
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
CCD
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
CK
CK
CK
CK
CK
CK
CK
17
14
14
17
17
17
17
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CKED
t
PED
t
DQD
DQM
DQZ
t
t
t
DWD
t
DAL
CK 15, 21
CK 16, 21
CK
CK
t
t
DPL
BDL
CDL
RDL
17
17
t
t
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
CK 16, 21
t
MRD
CK
CK
CK
26
17
17
t
t
CL = 3
CL = 2
ROH(3)
ROH(2)
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
35
128Mb: x4, x8, x16
SDRAM
NOTES
t
t
1. All voltages referenced to VSS.
15. Timing actually specified by WR plus RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ TA ≤ +70°C and -
40°C ≤ TA ≤ +85°C for IT parts) is ensured.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
6. An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ
mustbeatsamepotential.)ThetwoAUTOREFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
21. Based on tCK = 10ns for -8E and tCK = 7.5ns for -75 and
-7E .
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width
≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifica-
tion, theclockandCKEmusttransitbetweenVIH and
VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
t
or precharge states (READ, WRITE, including WR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
Q
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7ns for -7E, 7.5ns for -75, and 7ns
for -8E after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge
mode.
50pF
t
10. HZ defines the time at which the output achieves the
25. Precharge mode only.
open circuit condition; it is not a reference to VOH or
VOL. The last valid data element will meet tOH before
going High-Z.
26. JEDEC and PC100 specify three clocks.
27. AC for -75/-7E at CL = 3 with no load is 4.6ns and is
t
guaranteed by design.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with
timing referenced to 1.5V crossover point. If the in-
put transition time is longer than 1 ns, then the
timing is referenced at VIL (MAX) and VIH (MIN) and
no longer at the 1.5V crossover point. Refer to Micron
Technical Note TN-48-09 for more details.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
VIH or VIL levels.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
t
32. For -8E, CL = 2 and CK = 10ns; for -75, CL = 3 and
tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
ally a nominal value and does not result in a fail
value.
13. IDD specifications are tested after the device is prop-
erly initialized.
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
14. Timing actually specified by tCKS; clock(s) specified
as a reference only at minimum cycle rate.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
36
128Mb: x4, x8, x16
SDRAM
1
INITIALIZE AND LOAD MODE REGISTER
T0
T1
Tn + 1
To + 1
CL
Tp + 1
Tp + 2
Tp + 3
( (
) )
( (
) )
( (
) )
t
t
CK
CLK
CKE
((
))
t
( (
) )
( (
) )
( (
) )
CH
t
t
CKH
CKS
((
))
((
))
( (
) )
( (
) )
( (
) )
( (
) )
t
t
t
t
t
t
CMS CMH
CMS CMH
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11
A10
CODE
ROW
ROW
BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
SINGLE BANK
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL
BANKS
BA0, BA1
DQ
High-Z
((
))
((
))
T = 100µs
MIN
t
t
t
t
MRD
RP
RFC
RFC
Power-up:
Program Mode Register 2, 3, 4
AUTO REFRESH
VDD and
AUTO REFRESH
Precharge
all banks
CLK stable
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
MRD
RFC
RP
1.5
0.8
1.5
2
1.5
0.8
1.5
2
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
1
CH
3
2
3
t
CL
3
2
CK
CK (3)
CK (2)
CKH
8
66
15
66
20
70
20
ns
ns
7.5
0.8
10
1
0.8
*CAS latency indicated in parentheses.
NOTE: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care.”
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
37
128Mb: x4, x8, x16
SDRAM
1
POWER-DOWN MODE
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
t
CK
CL
CLK
CKE
( (
t
CH
) )
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
( (
) )
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
( (
) )
( (
) )
A0-A9, A11
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
DQ
BANK
BANK(S)
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
MIN
SYMBOL* MIN
MAX
MIN
MAX
MIN
10
1
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
3
3
8
ns
ns
ns
ns
ns
CK (2)
CKH
CKS
7.5
0.8
1.5
0.8
1.5
10
0.8
1.5
0.8
1.5
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
AS
CH
2
CL
CMH
CMS
1
CK (3)
2
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
38
128Mb: x4, x8, x16
SDRAM
1
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CK
CL
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
COLUMN m
COLUMN e
t
t
AH
AS
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
t
AC
t
t
t
t
t
DH
AC
OH
HZ
DS
D
OUT
m
D
OUT m + 1
D
OUT
e
DOUT e + 1
DQ
t
LZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
1.5
0.8
1.5
0.8
1.5
MAX
MIN
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
DH
1.5
0.8
1.5
0.8
1.5
2
1
2
1
2
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
AC (2)
5.4
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
t
t
t
t
t
t
AS
CH
3
DS
CL
3
HZ(3)
HZ(2)
LZ
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
CK (3)
CK (2)
CKH
8
7.5
0.8
10
1
1
3
1
3
1
3
0.8
OH
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
39
128Mb: x4, x8, x16
SDRAM
AUTO REFRESH MODE
T0
T1
T2
Tn + 1
CL
To + 1
( (
) )
( (
) )
t
CLK
CKE
t
t
( (
) )
( (
) )
CK
CH
( (
) )
( (
) )
t
t
t
CKS
CMS
CKH
t
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
( (
) )
( (
) )
A0-A9, A11
A10
ROW
ROW
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BANK(S)
BA0, BA1
DQ
BANK
High-Z
( (
) )
( (
) )
t
t
t
RFC
1
1
RP
RFC
Precharge all
active banks
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
0.8
1.5
0.8
1.5
66
MIN
1
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
RFC
RP
0.8
1.5
0.8
1.5
66
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
AS
2
2
CH
3
1
CL
3
2
CK (3)
CK (2)
8
70
20
7.5
10
15
20
*CAS latency indicated in parentheses.
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
40
128Mb: x4, x8, x16
SDRAM
SELF REFRESH MODE
T0
T1
T2
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
CLK
CKE
( (
t
( (
) )
t
CH
CK
) )
t
CKS
RAS min1
t
≥
( (
) )
( (
) )
( (
) )
t
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
or COMMAND
INHIBIT
COMMAND
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMH
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11
A10
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
( (
) )
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-7E
-75
MAX
-8E
MAX UNITS
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
SYMBOL* MIN
MIN
1.5
0.8
1.5
44
MAX
MIN
2
MAX UNITS
t
t
t
t
t
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
RAS
RP
1.5
0.8
1.5
37
ns
ns
ns
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
120,000
120,000
50
20
80
120,000
ns
ns
ns
CK (3)
CK (2)
CKH
8
15
20
7.5
0.8
10
1
XSR
75
75
0.8
*CAS latency indicated in parentheses.
NOTES:1. No maximum time limit for Self Refresh. tRAS max applies to non-Self Refresh mode.
t
2. XSR requires minimum of two clocks regardless of frequency or timing.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
41
128Mb: x4, x8, x16
SDRAM
1
READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
ROW
t
t
CMS CMH
DQM /
DQML, DQMH
t
t
AS
AH
COLUMN m2
A0-A9, A11
ROW
t
t
AS
AH
ALL BANKS
ROW
ROW
A10
SINGLE BANKS
BANK(S)
DISABLE AUTO PRECHARGE
BANK
t
t
AS
AH
BA0, BA1
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
D
OUT m+1
D
OUT m+2
DOUT m+3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC(3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
1.5
0.8
1.5
1
2
ns
ns
t
t
t
t
t
t
t
t
t
t
AC(2)
5.4
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
AS
CH
3
1
1
1
CL
3
OH
3
3
3
CK(3)
CK(2)
CKH
CKS
8
RAS
RC
37
60
15
15
120,000
44
66
20
20
120,000
50
70
20
20
120,000
7.5
0.8
1.5
10
1
0.8
1.5
RCD
RP
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
42
128Mb: x4, x8, x16
SDRAM
1
READ – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
A0-A9, A11
ROW
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
AC
OH
OH
OH
OH
DOUT
m
D
OUT
m
+ 1
D
OUT
m
+ 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
0.8
MAX
MIN
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
1.5
1
2
ns
ns
t
t
t
t
t
t
t
t
t
t
AC (2)
5.4
1.5
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
AS
CH
3
1
1
1
CL
3
OH
3
3
3
CK (3)
CK (2)
CKH
CKS
8
RAS
RC
37
60
15
15
120,000
44
66
20
20
120,000
50
70
20
20
120,000
7.5
0.8
1.5
10
1
0.8
1.5
RCD
RP
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
43
128Mb: x4, x8, x16
SDRAM
1
SINGLE READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS CMH
3
3
COMMAND
PRECHARGE
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
ROW
NOP
t
t
CMS CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
A0-A9, A11
ROW
COLUMN m
t
AS
t
AH
ALL BANKS
ROW
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANKS
BANK(S)
t
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
OH
DOUT m
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MIN
0.8
MAX
MIN
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
1.5
1
2
ns
ns
t
t
t
t
t
t
t
t
t
t
AC (2)
5.4
1.5
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
AS
CH
3
1
1
1
CL
3
OH
3
3
3
CK (3)
CK (2)
CKH
CKS
8
RAS
RC
37
60
15
15
120,000
44
66
20
20
120,000
50
70
20
20
120,000
7.5
0.8
1.5
10
1
0.8
1.5
RCD
RP
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. PRECHARGE command not allowed or tRAS would be violated.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
44
128Mb: x4, x8, x16
SDRAM
1
SINGLE READ – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
3
3
COMMAND
ACTIVE
NOP
NOP
NOP
READ
t
NOP
ACTIVE
NOP
NOP
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
A0-A9, A11
ROW
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK
BANK
BANK
t
AC
t
OH
D
OUT
m
DQ
t
CAS Latency
t
RCD
HZ
t
t
RP
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
1.5
0.8
1.5
1
2
ns
ns
t
t
t
t
t
t
t
t
t
t
AC (2)
5.4
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
AS
CH
3
1
1
1
CL
3
OH
3
3
3
CK (3)
CK (2)
CKH
CKS
8
RAS
RC
37
60
15
15
120,000
44
66
20
20
120,000
50
70
20
20
120,000
7.5
0.8
1.5
10
1
0.8
1.5
RCD
RP
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. READ command not allowed else tRAS would be violated.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
45
128Mb: x4, x8, x16
SDRAM
1
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 3
t
BANK 3
BANK 0
t
t
t
t
AC
AC
AC
AC
AC
t
t
t
t
t
t
AC
OH
OH
OH
OH
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
D
OUT m + 3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RCD - BANK 0
CAS Latency - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 3
CAS Latency - BANK 3
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
0.8
1.5
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
LZ
0.8
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
AC (2)
5.4
2
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1
t
t
t
t
t
t
t
AS
OH
3
3
3
CH
3
RAS
RC
44
60
15
15
14
120,000
44
66
20
20
15
120,000
50
70
20
20
20
120,000
ns
ns
ns
ns
ns
CL
3
CK (3)
CK (2)
CKH
CKS
8
RCD
RP
7.5
0.8
1.5
10
1
0.8
1.5
RRD
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
46
128Mb: x4, x8, x16
SDRAM
1
READ – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
( (
) )
DQM /
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
2
A0-A9, A11
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC
AC
( (
) )
t
t
t
t
t
t
t
OH
AC
OH
OH
OH
OH
OH
( (
) )
( (
) )
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
D
OUT
m
DOUT m+1
DQ
t
LZ
t
HZ
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
t
RCD
CAS Latency
Full page completed
DON’T CARE
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
3
UNDEFINED
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
-8E
SYMBOL* MNI
MAX
5.4
MIN
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
MAX
MIN
MAX UNITS
t
t
AC (3)
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
2
1
2
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
5.4
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1.5
t
t
t
t
t
t
AS
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
CH
3
CL
3
1
3
1
3
1
3
CK (3)
CK (2)
CKH
8
OH
7.5
0.8
10
1
RCD
15
20
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. Page left open; no tRP.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
47
128Mb: x4, x8, x16
SDRAM
1
READ – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM /
DQML, DQMH
t
AS
t
AH
2
A0-A9, A11
A10
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
BANK
t
AS
t
AH
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m + 2
DOUT m + 3
DQ
t
LZ
t
t
t
HZ
LZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
1.5
MIN
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
0.8
1.5
2
1
2
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
5.4
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1.5
t
t
t
t
t
t
AS
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
CH
3
CL
3
1
3
1
3
1
3
CK (3)
CK (2)
CKH
8
OH
7.5
0.8
10
1
RCD
15
20
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
48
128Mb: x4, x8, x16
SDRAM
1
WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9, A11
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MIN
1.5
0.8
1.5
44
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
1.5
37
60
15
15
14
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
1
CH
3
2
CL
3
RAS
RC
120,000
120,000
50
70
20
20
15
120,000
ns
ns
ns
ns
ns
CK (3)
CK (2)
CKH
CKS
CMH
8
66
7.5
0.8
1.5
0.8
10
1
RCD
RP
20
0.8
1.5
0.8
20
2
WR
15
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
49
128Mb: x4, x8, x16
SDRAM
1
WRITE – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AS
AH
2
A0-A9, A11
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
MIN
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
2
1
ns
ns
ns
ns
ns
ns
ns
–
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
2
0.8
CH
3
1.5
1.5
2
CL
3
RAS
RC
37
120,000
44
120,000
50
120,000
CK (3)
CK (2)
CKH
CKS
CMH
8
60
66
70
7.5
0.8
1.5
0.8
10
1
RCD
RP
15
20
20
0.8
1.5
0.8
15
20
20
2
WR
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
50
128Mb: x4, x8, x16
SDRAM
1
SINGLE WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
4
4
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9, A11
ROW
t
COLUMN m
AS
AH
ALL BANKS
ROW
t
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
D
IN
m
DQ
t
t
RP
2
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MIN
1.5
0.8
1.5
44
MAX
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
1.5
37
60
15
15
14
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
RAS
RC
120,000
120,000
50
70
20
20
15
120,000
ns
ns
ns
ns
ns
CK (3)
CK (2)
CKH
CKS
CMH
8
66
7.5
0.8
1.5
0.8
10
1
RCD
RP
20
0.8
1.5
0.8
20
2
WR
15
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
51
128Mb: x4, x8, x16
SDRAM
1
SINGLE WRITE – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
3
3
3
NOP
COMMAND
ACTIVE
NOP
ACTIVE
NOP
NOP
WRITE
t
NOP
NOP
NOP
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AS
AH
2
A0-A9, A11
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
DIN m
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MIN
1.5
MIN
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
2
1
ns
ns
ns
ns
ns
ns
ns
–
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
0.8
CH
3
1.5
1.5
2
CL
3
RAS
RC
37
120,000
44
120,000
50
120,000
CK (3)
CK (2)
CKH
CKS
CMH
8
60
66
70
7.5
0.8
1.5
0.8
10
1
RCD
RP
15
20
20
0.8
1.5
0.8
15
20
20
2
WR
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. WRITE command not allowed else tRAS would be violated.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
52
128Mb: x4, x8, x16
SDRAM
1
ALTERNATING BANK WRITE ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN
b
DIN b + 1
DIN b + 2
DIN b + 3
DQ
t
t
t
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MIN
0.8
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DH
DS
0.8
1.5
ns
ns
t
t
t
t
t
t
t
t
t
AS
1.5
2
CH
3
RAS
RC
37
120,000
44
120,000
50
70
20
20
20
120,000
ns
ns
ns
ns
ns
–
CL
3
60
66
CK (3)
CK (2)
CKH
CKS
CMH
CMS
8
RCD
RP
15
20
7.5
0.8
1.5
0.8
1.5
10
1
15
20
0.8
1.5
0.8
1.5
RRD
WR
14
15
2
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
1
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
53
128Mb: x4, x8, x16
SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
( (
) )
DQM /
DQML, DQMH
( (
) )
t
t
AH
AS
( (
) )
( (
) )
1
A0-A9, A11
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
( (
) )
D
IN
m
D
IN m + 1
D
IN m + 2
D
IN m + 3
DIN m - 1
DQ
( (
) )
t
RCD
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
command to stop.2, 3
Full page completed
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
0.8
1.5
0.8
1.5
20
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
DH
1.5
0.8
1.5
0.8
1.5
15
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
1
CK (3)
CK (2)
CKH
8
DS
2
7.5
0.8
10
1
RCD
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
t
2. WR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
54
128Mb: x4, x8, x16
SDRAM
1
WRITE – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
2
A0-A9, A11
ROW
t
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
D
IN
m
D
IN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
MIN
1
MAX UNITS
SYMBOL* MIN
MIN
1.5
0.8
1.5
0.8
1.5
20
MAX
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
DH
1.5
0.8
1.5
0.8
1.5
15
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
1
CK (3)
CK (2)
CKH
8
DS
2
7.5
0.8
10
1
RCD
20
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
55
128Mb: x4, x8, x16
SDRAM
54-PIN PLASTIC TSOP (400 mil)
22.30
22.14
SEE DETAIL A
.71
.80 TYP
.10 (2X)
.45
.30
2.80
11.86
11.66
PIN #1 ID
10.24
10.08
.75 (2X)
.18
.13
1.00 (2X)
.25
.20
.05
.60
.40
.10
1.2 MAX
.80
TYP
DETAIL A
MAX
MIN
NOTE: 1. All dimensions in millimeters
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
56
128Mb: x4, x8, x16
SDRAM
FBGA “FB” PACKAGE
60-BALL, 8mm x 16mm
0.850 0.075
0.205 MAX.
0.325 0.025
SEATING PLANE
0.10
5.60
2.40 0.05
CTR
∅0.45 0.05 (TYP)
0.80 (TYP)
PIN #1 ID
8.00 0.05
16.00 0.10
11.20
0.80
(TYP)
5.60 0.05
1.20 MAX.
2.80 0.05
4.00 0.05
8.00 0.10
(Bottom View)
NOTE: 1. All dimensions in millimeters.
2. Recommended Pad size for PCB is 0.33mm 0.025mm.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
57
128Mb: x4, x8, x16
SDRAM
FBGA “FC” PACKAGE
60-BALL, 11mm x 13mm
0.850 0.075
0.325 0.025
0.205 MAX.
SEATING PLANE
0.10
5.60
2.40 0.05
CTR
∅ 0.45 0.05 (TYP)
0.80 (TYP)
PIN #1 ID
6.50 0.05
13.00 0.10
11.20
5.60 0.05
0.80
(TYP)
2.80 0.05
1.20 MAX
5.50 0.05
11.00 0.10
(Bottom View)
NOTE: 1. All dimensions in millimeters.
2. Recommended Pad size for PCB is 0.33mm 0.025mm.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
58
128Mb: x4, x8, x16
SDRAM
FBGA DEVICE MARKING
DBFCF
Due to the size of the package, Micron’s standard part
number is not printed on the top of each device. Instead,
an abbreviated device mark comprised of a five-digit
alphanumericcodeisused. Theabbreviateddevicemarks
are cross referenced to Micron part numbers in Table 1.
Speed Grade
D = -8E
= -75
F
N = -7E
Width ( I/Os)
B = x4
C = x8
D = x16
Device Density
F = 128Mb
Product Type
B = 3.3V SDR SDRAM (60-ball, "FB", 8mm x 16mm)
C = 3.3V SDR SDRAM (60-ball, "FC", 11mm x 13mm)
Product Group
D = DRAM
Z = DRAM ENGINEERING SAMPLE
CROSS REFERENCE FOR FBGA DEVICE MARKING
ENGINEERING
PRODUCTION
MARKING
DCFBF
PART NUMBER
ARCHITECTURE
32 Meg x 4
32 Meg x 4
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
FBGA
SAMPLE
ZCFBF
ZCFBN
ZBFBF
ZBFBN
ZCFCF
ZCFCN
ZBFCF
ZBFCN
MT48LC32M4A2FC-75
MT48LC32M4A2FC-7E
MT48LC32M4A2FB-75
MT48LC32M4A2FB-7E
MT48LC16M8A2FC-75
MT48LC16M8A2FC-7E
MT48LC16M8A2FB-75
MT48LC16M8A2FB-7E
60-ball, 11x13
60-ball, 11x13
60-ball, 8x16
60-ball, 8x16
60-ball, 11x13
60-ball, 11x13
60-ball, 8x16
60-ball, 8x16
DCFBN
DBFBF
DBFBN
DCFCF
DCFCN
DBFCF
DBFCN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
59
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