MT4C4M4E8 [MICRON]
4 MEG x 4 EDO DRAM; 梅格4 ×4 EDO DRAM
| 型号： | MT4C4M4E8 |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | 4 MEG x 4 EDO DRAM |
| 文件： | 总23页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
24/26-Pin TSOP
(DA-2)
(DB-2)
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/ Os on 3.3V devices
V
DQ1
DQ2
WE#
RAS#
CC
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
V
DQ1
DQ2
WE#
RAS#
CC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ4
DQ3
CAS#
OE#
A9
DQ4
DQ3
CAS#
OE#
A9
*NC/A11
*NC/A11
A10
A0
A1
A2
A3
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
V
CC
VSS
V
CC
VSS
OPTIONS
MARKING
* NC on 2K refresh and A11 on 4K refresh options.
• Voltages
3.3V
Note: The “#” symbol indicates signal is active LOW.
LC
C
5V
4 MEG x 4 EDO DRAM PART NUMBERS
• Refresh Addressing
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
E8
E9
PART NUMBER
Vcc
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
REFRESH PACKAGE REFRESH
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
SOJ
SOJ
Standard
Self
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
TSOP
TSOP
SOJ
Standard
Self
• Timing
Standard
Self
50ns access
60ns access
-5
-6
SOJ
TSOP
TSOP
SOJ
Standard
Self
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S
Standard
Self
5V
SOJ
5V
TSOP
TSOP
SOJ
Standard
Self
• Part Number Example: MT4LC4M4E8DJ-6
5V
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
5V
Standard
Self
5V
SOJ
5V
TSOP
TSOP
Standard
Self
5V
KEY TIMING PARAMETERS
GENERAL DESCRIPTION
t
t
t
t
t
t
SPEED
-5
RC
RAC
PC
AA
CAC
CAS
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS#is used to latch the column address
84ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
-6
104ns
10ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
1
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address
pins A10 and A11 are “don’t care”). READ and WRITE
cycles are selected with the WE# input.
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS#LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
A logicHIGH on WE#dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS#returnsHIGH.EDO allowsCAS#precharge
time (tCP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
The four data inputs and the four data outputs are routed
through four pins using common I/ O, and pin direction is
controlled by WE# and OE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row address-
defined page boundary.The PAGEcycle is always initiated
V
IH
RAS#
CAS#
V
IL
V
V
IH
IL
V
V
IH
IL
ADDR
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (A)
VALID DATA (C)
VALID DATA (D)
VALID DATA (B)
t
t
OD
t
OD
OD
t
OES
t
OEHC
V
V
IH
IL
OE#
t
OE
t
OEP
The DQs go back to
Low-Z if OES is met.
The DQs remain High-Z
until the next CAS# cycle
if OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if OEP is met.
t
t
t
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
2
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
fresh cycle and holding RAS# LOW for the specified tRASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation,aswellasduringastandbyor BATTERYBACKUP
mode.
The Self Refresh mode is terminated by driving RAS#
HIGH for a minimum time oftRPS.This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh se-
quence, a burst refresh is not required upon exiting
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
Self Refresh. However, if the DRAM controller utilizes
a
RAS#-ONLY or burst refresh sequence, all rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
t
4K) are executed within REF (MAX), regardless of se-
quence. The CBR and Self Refresh cycles will invoke the
internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
V
IH
RAS#
CAS#
ADDR
V
IL
V
V
IH
IL
V
V
IH
IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (B)
INPUT DATA (C)
t
t
WHZ
WHZ
t
V
IH
WE#
OE#
WPZ
V
IL
V
V
IH
IL
t
The DQs go to High-Z if WE# falls and, if WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
WE# CONTROL OF DQs
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
3
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE#
CAS#
4
4
DATA-IN
BUFFER
DQ1
DQ2
DQ3
DQ4
DATA-OUT
BUFFER
NO. 2 CLOCK
GENERATOR
4
OE#
COLUMN
ADDRESS
BUFFER(11)
COLUMN
DECODER
10
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
4
1024
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
1024
REFRESH
COUNTER
2048
11
4096 x 1024 x 4
MEMORY
2048
2048
ROW
ADDRESS
BUFFERS (11)
ARRAY
11
11
2048
2048
NO. 1 CLOCK
GENERATOR
V
DD
SS
RAS#
V
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
WE#
CAS#
4
4
DATA-IN
BUFFER
DQ1
DQ2
DQ3
DQ4
DATA-OUT
BUFFER
NO. 2 CLOCK
GENERATOR
4
OE#
COLUMN
ADDRESS
BUFFER(10)
COLUMN
DECODER
10
A0
A1
10
4
1024
A2
REFRESH
CONTROLLER
A3
SENSE AMPLIFIERS
I/O GATING
A4
A5
1024
A6
REFRESH
COUNTER
A7
A8
12
A9
4096 x 1024 x 4
MEMORY
4096
4096
A10
A11
ROW
ADDRESS
BUFFERS (12)
ARRAY
12
12
4096
NO. 1 CLOCK
GENERATOR
V
DD
SS
RAS#
V
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
4
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES
DATA-IN/OUT
DQ1-DQ4
FUNCTION
RAS#
CAS#
H→X
L
WE#
X
OE#
tR
tC
Standby
H
X
X
X
High-Z
READ
L
H
L
ROW
ROW
ROW
ROW
n/a
COL
COL
COL
COL
COL
COL
COL
n/a
Data-Out
Data-In
EARLY WRITE
READ WRITE
EDO-PAGE-MODE
READ
L
L
L
X
L
L
H→L
H
L→H
Data-Out, Data-In
Data-Out
Data-Out
Data-In
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Any Cycle
1st Cycle
2nd Cycle
READ
L
H→L
H→L
H→L
H→L
L→H
H→L
H→L
L
L
L
L
H
EDO-PAGE-MODE
EARLY WRITE
L
L
X
ROW
n/a
L
L
X
Data-In
L
L
H
L
n/a
Data-Out
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
EDO-PAGE-MODE
READ-WRITE
H→L
H→L
H
L→H
L→H
L
ROW
n/a
COL
COL
COL
COL
n/a
L
HIDDEN
L→H→L
L→H→L
L
ROW
ROW
ROW
X
REFRESH
WRITE
L
L
X
RAS#-ONLY REFRESH
CBR REFRESH
SELF REFRESH
H
X
X
High-Z
H→L
H→L
L
H
X
X
High-Z
L
H
X
X
X
High-Z
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
5
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/ O Pins Relative to VSS:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic).................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V
5V
PARAMETER/CONDITION
SYMBOL MIN
MAX
MIN
MAX UNITS NOTES
Supply Voltage
VCC
VIH
VIL
II
3.0
2.0
-1.0
-2
3.6
4.5
5.5
V
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC
5.5
0.8
2
2.4
-0.5
-2
VCC +1
0.8
V
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NC
V
Input Leakage Current:
Any input at VIN (0V ≤ VIN ≤ VIH [MAX]);
all other pins not under test = 0V
2
µA
4
Output High Voltage:
IOUT = -2mA (3.3V), -5mA (5V)
VOH
VOL
IOZ
2.4
-
-
0.4
5
2.4
-
-
0.4
5
V
V
Output Low Voltage:
IOUT = 2mA (3.3V), 4.2mA (5V)
Output Leakage Current:
Any output at VOUT (0V ≤ VOUT ≤ 5.5V);
DQ is disabled and in High-Z state
-5
-5
µA
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
6
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3)
3.3V
5V
2K
4K
2K
4K
PARAMETER/CONDITION
SYM SPEED Refresh Refresh Refresh Refresh UNITS NOTES
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
ICC1
ICC2
ICC2
ALL
ALL
ALL
1
1
1
1
mA
µA
STANDBY CURRENT: CMOS (non-S version only)
(RAS# = CAS# = other inputs = VCC -0.2V)
500
150
500
150
500
150
500
150
STANDBY CURRENT: CMOS (S version only)
(RAS# = CAS# = other inputs = VCC -0.2V)
µA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
-5
-6
110
100
90
80
140
130
120
110
mA
5, 6
5, 6
5, 6
5, 7
ICC3
ICC4
ICC5
ICC6
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE
Average power supply current (RAS# = VIL,
CAS#, address cycling: tPC = tPC [MIN])
-5
-6
110
100
100
90
110
100
100
90
mA
mA
mA
REFRESH CURRENT: RAS#-ONLY
Average power supply current
-5
-6
110
100
90
80
140
130
120
110
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
-5
-6
110
100
90
80
140
130
120
110
REFRESH CURRENT: Extended (S version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# = tRAS (MIN); WE# =
VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or
0.2V (DIN may be left open)
ALL
tRC
300
300
300
300
µA
µs
5, 7
25
ICC7
ICC8
62.5
31.25
62.5
31.25
REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with
RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# =
VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V
or 0.2V (DIN may be left open)
ALL
300
300
300
300
µA
5, 7
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
7
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
CAPACITANCE
PARAMETER
SYMBOL
CI1
MAX
UNITS
pF
NOTES
Input Capacitance: Address pins
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
5
7
7
8
8
8
CI2
pF
CIO
pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
t
Access time from column address
Column address setup to CAS# precharge
Column address hold time (referenced to RAS#)
Column address setup time
Row address setup time
AA
25
30
t
ACH
12
38
0
15
45
0
t
AR
t
ASC
t
ASR
0
0
t
Column address to WE# delay time
Access time from CAS#
AWD
42
49
13
14
t
CAC
13
15
t
Column address hold time
CAS# pulse width
CAH
8
8
10
10
15
10
0
t
CAS
10,000
10,000
t
CAS# LOW to “don’t care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CHD
15
8
t
CHR
7
t
CLZ
0
t
Data output hold after next CAS# LOW
CAS# precharge time
COH
3
3
t
CP
8
10
15
t
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CPA
28
35
t
CRP
5
38
5
5
45
5
t
CSH
t
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
CSR
t
CWD
28
8
35
10
10
0
13
t
Write command to CAS# lead time
Data-in hold time
CWL
t
DH
8
16
16
t
Data-in setup time
DS
0
t
Output disable
OD
0
12
12
0
15
15
t
Output Enable
OE
17
18
t
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OEH
8
10
t
OE# HIGH hold from CAS# HIGH
OE# HIGH pulse width
OEHC
5
5
4
0
10
5
ns
ns
ns
ns
18
20
t
OEP
t
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OES
5
t
OFF
12
0
15
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
8
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
t
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
ORD
0
0
ns
t
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
PC
20
47
25
56
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PRWC
t
RAC
50
60
19
21
t
RAS# to column address delay time
Row address hold time
RAD
9
9
12
10
60
60
100
104
14
0
t
RAH
t
RAS# pulse width
RAS
50
50
100
84
11
0
10,000
10,000
t
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
RASP
125,000
125,000
t
RASS
t
RC
t
RCD
22
23
t
Read command hold time (referenced to CAS#)
Read command setup time
RCH
t
RCS
0
0
t
Refresh period (2,048 cycles)
Refresh period (4,096 cycles)
Refresh period S version
REF
32
64
32
64
t
REF
t
REF
t
128
128
RAS# precharge time
RP
30
5
40
5
t
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
Read command hold time (referenced to RAS#)
RAS# hold time
RPC
t
RPS
90
0
105
0
t
RRH
23
13
t
RSH
13
116
67
13
2
15
140
79
15
2
t
READ WRITE cycle time
RWC
t
RAS# to WE# delay time
RWD
t
Write command to RAS# lead time
Transition time (rise or fall)
RWL
t
T
50
12
50
15
t
Write command hold time
WCH
8
10
45
0
t
Write command hold time (referenced to RAS#)
WE# command setup time
WCR
38
0
t
WCS
13
t
Output disable delay from WE#
Write command pulse width
WHZ
0
0
t
WP
5
5
t
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
WPZ
10
8
10
10
10
t
WRH
t
WRP
8
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
9
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
NOTES
1. All voltages referenced to VSS.
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for CP.
t
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is ensured.
3. An initial pause of 100µs is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
16. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
17. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE#
must be pulsed during CAS# HIGH time in order to
place I/ O buffers in High-Z.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = VCCMIN; f = 1 MHz.
9. AC characteristics assume tT = 2.5ns.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
18. LATE WRITE and READ-MODIFY-WRITE cycles
t
t
must have both OD and OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
t
after OEH is met. If CAS# goes HIGH prior to OE#
going back LOW, the DQs will remain open.
t
t
19. Requires that AA and CAC are not violated.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates
and 100pF; and VOL = 0.8V and VOH = 2V.
t
tRAD was greater than the specified RAD (MAX)
limit, then access time was controlled exclusively by
t
tAA (tRAC and CAC no longer applied). With or
t
t
13. tWCS, tRWD, tAWD and CWD are not restrictive
without the tRAD (MAX) limit, tAA, tRAC and CAC
operating parameters. tWCS applies to EARLY
must always be met.
t
WRITE cycles. tRWD, tAWD and CWD apply to
22. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
t
tRCD was greater than the specified RCD (MAX)
limit, then access time was controlled exclusively by
t
t
the entire cycle. If tWCS < WCS (MIN) and RWD ≥
tCAC (tRAC [MIN] no longer applied). With or
tRWD (MIN), tAWD ≥ tAWD (MIN) and CWD ≥
without the tRCD limit, tAA and CAC must always
t
t
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
be met.
t
t
23. Either RCH or RRH must be satisfied for a READ
cycle.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
t
a LATE WRITE (OE#-controlled) cycle. WCS, tRWD,
t
tCWD and AWD are not applicable in a LATE
25. The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
WRITE cycle.
t
t
14. Requires that tAA and RAC are not violated.
refreshes). For 4K refresh, RC = 31.25µs (128ms/
4,096 rows = 31.25µs) and for 2K refresh, tRC = 62.5µs
(128ms/ 2,048 rows = 62.5µs).
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
10
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
RRH
RSH
t
t
t
RCD
CAS
CRP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
ASR
ASC
CAH
t
ACH
V
V
IH
IL
ROW
ROW
COLUMN
ADDR
WE#
t
t
RCH
RCS
V
V
IH
IL
t
t
t
t
AA
RAC
CAC
CLZ
NOTE 1
OFF
t
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OFF
0
0
t
t
ACH
12
38
0
15
45
0
ns
RAC
50
60
ns
t
t
AR
ns
RAD
9
9
12
10
60
104
14
0
ns
t
t
ASC
ns
RAH
ns
t
t
ASR
0
0
ns
RAS
50
84
11
0
10,000
10,000
ns
t
t
CAC
13
15
ns
RC
ns
t
t
CAH
8
8
10
10
0
ns
RCD
ns
t
t
CAS
10,000
10,000
ns
RCH
ns
t
t
CLZ
0
ns
RCS
0
0
ns
t
t
CRP
5
5
ns
RP
30
0
40
0
ns
t
t
CSH
38
0
45
0
ns
RRH
ns
t
t
OD
12
12
15
15
ns
RSH
13
15
ns
t
OE
ns
t
NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
11
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
CSH
t
RSH
t
t
t
CRP
RCD
CAS
V
V
IH
IL
t
AR
t
t
t
ASC
t
RAD
RAH
CAH
t
t
ACH
ASR
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
WE#
V
V
IH
IL
t
t
DS
DH
V
V
IOH
IOL
DQ
VALID DATA
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
12
38
0
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
9
MAX
MIN
10
60
104
14
40
15
15
10
45
0
MAX
UNITS
ns
t
t
ACH
15
45
0
RAH
t
t
AR
ns
RAS
50
84
11
30
13
13
8
10,000
10,000
ns
t
t
ASC
ns
RC
ns
t
t
ASR
0
0
ns
RCD
ns
t
t
CAH
8
10
10
5
ns
RP
ns
t
t
CAS
8
10,000
10,000
ns
RSH
ns
t
t
CRP
5
ns
RWL
ns
t
t
CSH
38
8
45
10
10
0
ns
WCH
ns
t
t
CWL
ns
WCR
38
0
ns
t
t
DH
8
ns
WCS
ns
t
t
DS
0
ns
WP
5
5
ns
t
RAD
9
12
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
12
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
ADDR
t
CSH
t
RSH
t
t
t
CAS
CRP
RCD
V
V
IH
IL
t
AR
t
t
t
t
CAH
RAD
ASC
RCS
t
t
t
ACH
ASR
RAH
V
V
IH
IL
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
AWD
V
V
IH
IL
WE#
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
V
IOH
IOL
VALID D
VALID D
DQ
OPEN
OPEN
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
25
30
OD
0
0
t
ACH
12
38
0
15
45
0
OE
12
15
t
AR
OEH
RAC
RAD
RAH
RAS
RCD
RCS
RP
8
10
t
ASC
50
60
t
AWD
42
0
49
0
9
9
12
10
60
14
0
t
ASR
t
CAC
13
15
50
11
0
10,000
10,000
t
CAH
8
8
10
10
0
t
CAS
10,000
10,000
t
CLZ
0
30
13
116
67
13
5
40
15
140
79
15
5
t
CRP
5
5
RSH
RWC
RWD
RWL
WP
t
CSH
38
28
8
45
35
10
10
0
t
CWD
t
CWL
t
DH
8
t
DS
0
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
13
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS#
CAS#
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CP
V
V
IH
IL
t
AR
t
t
t
t
t
ACH
ACH
RAD
RAH
ACH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
WE#
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RCS
t
RCH
V
V
IH
IL
t
t
t
t
RRH
AA
t
t
t
t
AA
AA
CPA
CAC
t
RAC
CPA
CAC
t
t
CAC
CLZ
t
OEHC
t
OFF
t
COH
t
CLZ
V
V
OH
OL
VALID
DATA
VALID
DATA
VALID
OPEN
DQ
OPEN
DATA
t
t
t
OE
OE
t
OD
OD
t
OES
t
V
V
OES
IH
IL
OE#
t
OEP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
5
MAX
MIN
10
5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
25
30
OEHC
t
t
ACH
12
38
0
15
45
0
OEP
5
t
t
AR
OES
4
5
t
t
ASC
OFF
0
12
50
0
15
60
t
t
ASR
0
0
PC
20
25
t
t
CAC
13
15
RAC
t
t
CAH
8
8
0
3
8
10
10
0
RAD
9
9
12
10
60
14
0
t
t
CAS
10,000
10,000
35
RAH
t
t
CLZ
RASP
50
11
0
125,000
125,000
t
t
COH
3
RCD
t
t
CP
10
RCH
t
t
CPA
28
RCS
0
0
t
t
CRP
5
38
0
5
45
0
RP
30
0
40
0
t
t
CSH
RRH
t
t
OD
12
12
15
15
RSH
13
15
t
OE
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
14
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE EARLY WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CP
V
V
IH
IL
t
AR
t
t
t
t
ACH
RAD
ACH
ACH
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
V
V
IH
IL
WE#
t
t
t
WCR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
V
IOH
IOL
DQ
VALID DATA
VALID DATA
VALID DATA
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
12
38
0
MAX
MIN
15
45
0
MAX
UNITS
ns
SYMBOL
MIN
20
9
MAX
MIN
25
12
10
60
14
40
15
15
10
45
0
MAX
UNITS
ns
t
t
ACH
PC
t
t
AR
ns
RAD
ns
t
t
ASC
ns
RAH
9
ns
t
t
ASR
0
0
ns
RASP
50
11
30
13
13
8
125,000
125,000
ns
t
t
CAH
8
10
10
10
5
ns
RCD
ns
t
t
CAS
8
10,000
10,000
ns
RP
ns
t
t
CP
8
ns
RSH
ns
t
t
CRP
5
ns
RWL
ns
t
t
CSH
38
8
45
10
10
0
ns
WCH
ns
t
t
CWL
ns
WCR
38
0
ns
t
t
DH
8
ns
WCS
ns
t
t
DS
0
ns
WP
5
5
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
15
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
t
RASP
RP
V
V
IH
IL
RAS#
CAS#
t
t
t
t
t
NOTE 1
CSH
PC
PRWC
RSH
CAS
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
RCS
t
t
t
CWL
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
t
AWD
AWD
AWD
CWD
t
CWD
CWD
V
V
IH
IL
WE#
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
DQ
OPEN
OPEN
D
D
D
D
D
D
t
t
t
OD
OD
OD
t
t
t
t
OE
OE
OE
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OD
0
0
t
t
AR
38
0
45
0
OE
12
15
t
t
ASC
OEH
8
10
25
56
t
t
ASR
0
0
PC
20
47
t
t
AWD
42
49
PRWC
t
t
CAC
13
15
RAC
50
60
t
t
CAH
8
8
0
8
10
10
0
RAD
9
12
10
60
14
0
t
t
CAS
10,000
10,000
RAH
9
t
t
CLZ
RASP
50
11
0
125,000
125,000
t
t
CP
10
RCD
t
t
CPA
28
35
RCS
t
t
CRP
5
38
28
8
5
RP
30
13
67
13
5
40
15
79
15
5
t
t
CSH
45
35
10
10
0
RSH
t
t
CWD
RWD
t
t
CWL
RWL
t
t
DH
8
WP
t
DS
0
t
NOTE: 1. PC is for LATE WRITE cycles only.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
16
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS#
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CP
V
V
IH
IL
CAS#
t
t
AR
t
t
t
RAD
ACH
CAH
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE#
ROW
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
RCH
t
t
t
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
t
AA
t
CPA
RAC
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
COH
V
V
IOH
IOL
VALID
DATA (B)
DQ
VALID DATA
IN
OPEN
VALID DATA (A)
t
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AA
25
30
OE
12
15
t
t
ACH
12
38
0
15
45
0
PC
20
25
t
t
AR
RAC
50
60
t
t
ASC
RAD
9
9
12
10
60
14
0
t
t
ASR
0
0
RAH
t
t
CAC
13
15
RASP
50
11
0
125,000
125,000
t
t
CAH
8
8
3
8
10
10
3
RCD
t
t
CAS
10,000
28
10,000
35
RCH
t
t
COH
RCS
0
0
t
t
CP
10
RP
30
13
8
40
15
10
0
t
t
CPA
RSH
t
t
CRP
5
38
8
5
45
10
0
WCH
t
t
CSH
WCS
0
t
t
DH
WHZ
0
12
0
15
t
DS
0
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
17
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
(With WE#-controlled disable)
V
V
IH
RAS#
CAS#
IL
t
CSH
t
t
t
t
t
CP
RCD
CAS
CAH
CRP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
ASC
ASR
ASC
V
V
IH
IL
ROW
COLUMN
COLUMN
ADDR
WE#
t
RCS
t
t
t
RCH
WPZ
RCS
V
V
IH
IL
t
t
t
t
AA
RAC
CAC
CLZ
t
t
WHZ
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
OD
0
0
AA
25
30
t
t
OE
12
15
ns
AR
38
0
45
0
ns
t
t
RAC
50
60
ns
ASC
ns
t
t
RAD
9
9
12
10
14
0
ns
ASR
0
0
ns
t
t
RAH
ns
CAC
13
15
ns
t
t
RCD
11
0
ns
CAH
8
8
10
10
0
ns
t
t
RCH
ns
CAS
10,000
10,000
ns
t
t
RCS
0
0
ns
CLZ
0
ns
t
t
WHZ
0
12
0
15
ns
CP
8
10
5
ns
t
t
WPZ
10
10
ns
CRP
5
ns
t
CSH
38
45
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
18
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON’T CARE)
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
t
CRP
RPC
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
DQ
ROW
ROW
V
OH
OL
OPEN
V
CBR REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS#
t
RPC
CP
t
t
t
t
t
t
CHR
RPC
CSR
CHR
CSR
V
V
IH
IL
CAS#
DQ
V
OH
OL
OPEN
V
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
0
MAX
MIN
0
MAX
UNITS
ns
SYMBOL
MIN
50
84
30
5
MAX
MIN
60
104
40
5
MAX
UNITS
ns
t
t
ASR
RAS
10,000
10,000
t
t
CHR
8
10
10
5
ns
RC
ns
t
t
CP
8
ns
RP
ns
t
t
CRP
5
ns
RPC
ns
t
t
CSR
5
5
ns
WRH
8
10
10
ns
t
t
RAH
9
10
ns
WRP
8
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
19
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
HIDDEN REFRESH CYCLE 24
(WE# = HIGH; OE# = LOW)
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS#
CAS#
t
t
t
RSH
CRP
RCD
t
CHR
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
RAC
t
t
OFF
CAC
t
CLZ
V
V
OH
OL
DQ
OPEN
VALID DATA
OPEN
t
t
OD
OE
t
ORD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
MIN
MAX
15
UNITS
ns
t
t
t
t
t
t
t
t
t
t
t
AA
25
30
OE
12
12
t
AR
38
0
45
0
ns
OFF
ORD
RAC
RAD
RAH
RAS
RCD
RP
0
0
0
0
15
ns
t
ASC
ns
ns
t
ASR
0
0
ns
50
60
ns
t
CAC
13
15
15
ns
9
12
10
60
14
40
15
ns
t
CAH
8
8
0
5
0
10
10
0
ns
9
ns
t
CHR
ns
50
11
30
13
10,000
10,000
ns
t
CLZ
ns
ns
t
CRP
5
ns
ns
t
OD
12
0
ns
RSH
ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
20
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
NOTE 1
t
t
t
t
RP
RASS
RPS
( (
) )
NOTE 2
V
V
IH
IL
RAS#
t
t
( (
) )
( (
) )
RPC
RPC
t
t
t
CP
CP
CSR
CHD
( (
) )
V
V
IH
IL
CAS#
DQ
( (
) )
V
V
( (
) )
OH
OL
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
( (
) )
V
V
IH
IL
WE#
( (
) )
DON'T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
15
8
MAX
MIN
15
MAX
UNITS
SYMBOL
MIN
5
MAX
MIN
5
MAX
UNITS
ns
t
t
CHD
ns
ns
ns
µs
ns
RPC
t
t
CP
10
RPS
90
8
105
10
ns
t
t
CSR
5
5
WRH
ns
t
t
RASS
100
30
100
40
WRP
8
10
ns
t
RP
t
NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode.
t
2. Once RPS is satisfied, a complete burst of all rows should be executed.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
21
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC SOJ (300 mil)
DA-2
.679 (17.25)
.673 (17.09)
.305 (7.75)
.299 (7.59)
.340 (8.64)
.330 (8.38)
PIN #1 INDEX
.050 (1.27) TYP
.600 (15.24) TYP
.037 (0.94) MAX
DAMBAR PROTRUSION
.032 (0.81)
.026 (0.66)
.142 (3.61)
.132 (3.35)
SEATING PLANE
.109 (2.77)
.094 (2.39)
.020 (0.51)
.015 (0.38)
.275 (6.99)
.260 (6.60)
.025 (0.64)
MIN
.040 (1.02)
R
.030 (0.76)
MAX
NOTE: 1. All dimensions in inches (millimeters)
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
22
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC TSOP (300 mil)
DB-2
.678 (17.23)
.672 (17.07)
SEE DETAIL A
.037 (0.95)
.367 (9.32)
.359 (9.12)
.302 (7.67)
.298 (7.57)
.007 (0.18)
.005 (0.13)
PIN #1 INDEX
.050 (1.27)
TYP
.020 (0.50)
.012 (0.30)
.010 (0.25) GAGE PLANE
SEATING PLANE
.004 (0.10)
.047 (1.20)
MAX
.006 (0.15)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.032 (0.80)
TYP
MAX
NOTE: 1. All dimensions in inches (millimeters)
or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
23
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