MT4LC16M4G3DJ-5_技术文档

16 MEG x 4

EDO DRAM

MT4LC16M4G3, MT4LC16M4H9

DRAM

For the latest data sheet, please refer to the Micron Web

site: www.micronsemi.com/mti/msp/html/datasheet.html

FEATURES

• Sin gle +3.3V ±0.3V power supply

• In dustry-stan dard x4 pin out, tim in g, fun ction s,

an d packages

• 12 row, 12 colum n addresses (H9) or

13 row, 11 colum n addresses (G3)

• High -perform an ce CMOS silicon -gate process

• All in puts, outputs an d clocks are LVTTL-com pat-

ible

• Exten ded Data-Out (EDO) PAGE MODE access

• Option al self refresh (S) for low-power data

reten tion

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64m s

PIN ASSIGNMENT (To p Vie w )

32-Pin SOJ

32-Pin TSOP

V

CC

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Vss

V

CC

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Vss

DQ0

DQ1

NC

DQ3

DQ2

NC

CAS#

OE#

NC/A12**

A11

A10

A9

DQ0

DQ1

NC

DQ3

DQ2

NC

CAS#

OE#

NC/A12**

A11

A10

A9

NC

WE#

RAS#

A0

A1

A2

A3

A4

A5

NC

9

WE#

RAS#

A0

A1

A2

A3

A4

A5

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

A8

A7

A6

Vss

A8

A7

A6

Vss

OPTIONS

MARKING

VCC

• Refresh Addressin g

4,096 (4K) rows

8,192 (8K) rows

VCC

H9

G3

**NC on H9 version, A12 on G3 version

• Plastic Packages

32-pin SOJ (400 m il)

32-pin TSOP (400 m il)

DJ

TG

16 MEG x 4 EDO DRAM PART NUMBERS

• Tim in g

REFRESH

PART NUMBER

ADDRESSING

PACKAGE

REFRESH

50n s access

60n s access

-5

-6

MT4LC16M4H9DJ-x

MT4LC16M4H9DJ-x S

MT4LC16M4H9TG-x

MT4LC16M4H9TG-x S

MT4LC16M4G3DJ-x

MT4LC16M4G3DJ-x S

MT4LC16M4G3TG-x

MT4LC16M4G3TG-x S

4K

8K

SOJ

Standard

Self

• Refresh Rates

TSOP

SOJ

Standard

Self

Stan dard Refresh

Self Refresh (128m s period)

Non e

S*

Standard

Self

NOTE: 1. Th e 16 Meg x 4 EDO DRAM base n um ber

differen tiates th e offerin gs in on e place—

MT4LC16M4H9. Th e fifth field distin guish es th e

address offerin gs: H9 design ates 4K addresses an d

G3 design ates 8K addresses.

SOJ

TSOP

Standard

Self

x = speed

2. Th e “#” sym bol in dicates sign al is active LOW.

*Con tact factory for availability

GENERAL DESCRIPTION

Th e 16 Meg x 4 DRAM is a h igh -speed CMOS,

dyn am ic ran dom -access m em ory device con tain in g

67,108,864 bits an d design ed to operate from 3V to

3.6V. Th e MT4LC16M4H9 an d MT4LC16M4G3 are

fun ction ally organ ized as 16,777,216 location s con -

tain in g 4 bits each . Th e 16,777,216 m em ory location s

are arran ged in 4,096 rows by 4,096 colum n s on th e H9

version an d 8,192 rows by 2,048 colum n s on th e G3

version . Durin g READ or WRITE cycles, each location is

Part Number Example:

MT4LC16M4H9DJ-6

KEY TIMING PARAMETERS

t

SPEED

RC

RAC

PC

AA

CAC

CAS

-5

-6

84ns

50ns

60ns

20ns

25ns

30ns

13ns

15ns

8ns

104ns

10ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1

16 MEG x 4

EDO DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4G3 (13 row addresses)

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

CONTROL

LOGIC

DQ3

4

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(11)

COLUMN

DECODER

11

A0

A1

11

4

2,048

A2

A3

REFRESH

CONTROLLER

SENSE AMPLIFIERS

I/O GATING

A4

A5

A6

2,048

REFRESH

A7

COUNTER

A8

A9

13

8,192 x 2,048 x 4

MEMORY

A10

A11

A12

ROW-

ADDRESS

BUFFERS (13)

ARRAY

8,192

13

8,192

NO. 1 CLOCK

GENERATOR

V

DD

RAS#

VSS

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4H9 (12 row addresses)

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

DQ3

CONTROL

LOGIC

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(12)

COLUMN

DECODER

12

A0

A1

12

4

4,096

A2

A3

REFRESH

CONTROLLER

SENSE AMPLIFIERS

I/O GATING

A4

A5

A6

4,096

REFRESH

A7

COUNTER

A8

A9

12

4,096 x 4,096 x 4

MEMORY

A10

A11

ROW-

ADDRESS

BUFFERS (12)

ARRAY

4,096

12

4,096

NO. 1 CLOCK

GENERATOR

V

DD

RAS#

VSS

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

16 MEG x 4

EDO DRAM

GENERAL DESCRIPTION (Co n t in u e d )

un iquely addressed via th e address bits. First, th e row

address is latch ed by th e RAS# sign al, th en th e colum n

address is latch ed by CAS#. Th e device provides EDO-

PAGE-MODE operation , allowin g for fast successive

data operation s (READ, WRITE, or READ-MODIFY-

WRITE) with in a given row.

tran sition s HIGH an d th en brin g OE# HIGH for a

m in im um of OEP an ytim e durin g th e CAS# HIGH

t

period. Th is will disable th e DQs, an d th ey will rem ain

disabled (regardless of th e state of OE# after th at poin t)

un til CAS# falls again . (Please refer to Figure 1.) Durin g

t

oth er cycles, th e outputs are disabled at OFF tim e after

t

Th e 16 Meg x 4 DRAM m ust be refresh ed periodically

in order to retain stored data.

RAS# an d CAS# are HIGH or at WHZ after WE# tran si-

tion s LOW. Th e ^tOFF tim e is referen ced from th e risin g

edge of RAS# or CAS#, wh ich ever occurs last. WE# can

also perform th e fun ction of disablin g th e output

drivers un der certain con dition s, as sh own in Figure 2.

EDO-PAGE-MODE operation s are always in itiated

with a row address strobed in by th e RAS# sign al,

followed by a colum n address strobed in by CAS#, just

like for sin gle location accesses. However, subsequen t

colum n location s with in th e row m ay th en be accessed

at th e page m ode cycle tim e. Th is is accom plish ed by

cyclin g CAS# wh ile h oldin g RAS# LOW an d en terin g

n ew colum n addresses with each CAS# cycle. Return in g

RAS# HIGH term in ates th e EDO-PAGE-MODE opera-

tion .

DRAM ACCESS

Each location in th e DRAM is un iquely addressable,

as m en tion ed in th e Gen eral Description . Th e data for

each location is accessed via th e four I/O pin s (DQ0-

DQ3). A logic HIGH on WE# dictates read m ode, wh ile

a logic LOW on WE# dictates write m ode. Durin g a

WRITE cycle, data-in (D) is latch ed by th e fallin g edge

of WE# or CAS#, wh ich ever occurs last. An EARLY

WRITE occurs wh en WE# is taken LOW prior to CAS#

fallin g. A LATE WRITE or READ-MODIFY-WRITE occurs

wh en WE# falls after CAS# is taken LOW. Durin g

EARLY WRITE cycles, th e data outputs (Q) will rem ain

High -Z, regardless of th e state of OE#. Durin g LATE

WRITE or READ-MODIFY-WRITE cycles, OE# m ust be

taken HIGH to disable th e data outputs prior to apply-

in g in put data. If a LATE WRITE or READ-MODIFY-

WRITEis attem pted wh ile keepin g OE# LOW, n o WRITE

will occur, an d th e data outputs will drive read data

from th e accessed location .

DRAM REFRESH

Th e supply voltage m ust be m ain tain ed at th e speci-

fied levels, an d th e refresh requirem en ts m ust be m et in

order to retain stored data in th e DRAM. Th e refresh

requirem en ts are m et by refresh in g all 8,192 rows (G3)

or all 4,096 rows (H9) in th e DRAM array at least on ce

every 64m s. Th e recom m en ded procedure is to execute

4,096 CBR REFRESH cycles, eith er un iform ly spaced or

grouped in bursts, every 64m s. Th e MT4LC16M4G3

in tern ally refresh es two rows for every CBR cycle,

wh ereas th e MT4LC16M4H9 refresh es on e row for

every CBR cycle. So with eith er device, executin g 4,096

CBR cycles covers all rows. Th e CBR refresh will in voke

th e in tern al refresh coun ter for autom atic RAS# ad-

dressin g. Altern atively, RAS#-ONLY REFRESH capabil-

ity is in h eren tly provided. However, with th is m eth od,

som e com patibility issues m ay becom e apparen t. For

exam ple, both G3 an d H9 version s require 4,096 CBR

REFRESH cycles, yet each requires a differen t n um ber of

RAS#-ONLY REFRESH cycles (G3 = 8,192 an d H9 =

4,096). JEDEC stron gly recom m en ds th e use of CBR

REFRESH for th is device.

EDO PAGE MODE

DRAM READ cycles h ave tradition ally turn ed th e

output buffers off (High -Z) with th e risin g edge of

CAS#. If CAS# wen t HIGH an d OE# was LOW (active),

th e output buffers would be disabled. Th e 16 Meg x 4

DRAM offers an accelerated page m ode cycle by elim i-

n atin g output disable from CAS# HIGH. Th is option is

called EDO an d it allows CAS# prech arge tim e (^tCP) to

occur with out th e output data goin g in valid (see READ

an d EDO-PAGE-MODE READ waveform s).

EDO operates like an y DRAM READ or FAST-PAGE-

MODE READ, except data is h eld valid after CAS# goes

HIGH, as lon g as RAS# an d OE# are h eld LOW an d WE#

is h eld HIGH. OE# can be brough t LOW or HIGH wh ile

CAS# an d RAS# are LOW, an d th e DQs will tran sition

between valid data an d High -Z. Usin g OE#, th ere are

two m eth ods to disable th e outputs an d keep th em

disabled durin g th e CAS# HIGH tim e. Th e first m eth od

is to h ave OE# HIGH wh en CAS# tran sition s HIGH an d

keep OE# HIGH for ^tOEHC th ereafter. Th is will disable

th e DQs, an d th ey will rem ain disabled (regardless of

th e state of OE# after th at poin t) un til CAS# falls again .

Th e secon d m eth od is to h ave OE# LOW wh en CAS#

An option al self refresh m ode is also available on th e

“S” version . Th e self refresh feature is in itiated by

perform in g a CBR REFRESH cycle an d h oldin g RAS#

t

LOW for th e specified RASS. Th e “S” option allows for

an exten ded refresh period of 128m s, or 31.25µs per

row for a 4K refresh an d 15.625µs per row for an 8K

refresh , wh en usin g a distributed CBR REFRESH. Th is

refresh rate can be applied durin g n orm al operation , as

well as durin g a stan dby or battery backup m ode.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

16 MEG x 4

EDO DRAM

DRAM REFRESH (Co n t in u e d )

Th e self refresh m ode is term in ated by drivin g RAS#

HIGH for a m in im um tim e of ^tRPS. Th is delay allows for

th e com pletion of an y in tern al refresh cycles th at m ay

be in process at th e tim e of th e RAS# LOW-to-HIGH

tran sition . If th e DRAM con troller uses a distributed

CBR refresh sequen ce, a burst refresh is n ot required

upon exitin g self refresh . However, if th e DRAM con -

troller uses RAS#-ONLY or burst CBR refresh , all rows

m ust be refresh ed with a refresh rate of ^tRC m in im um

prior to resum in g n orm al operation .

STANDBY

Return in g RAS# an d CAS# HIGH term in ates a

m em ory cycle an d decreases ch ip curren t to a reduced

stan dby level. Th e ch ip is precon dition ed for th e n ext

cycle durin g th e RAS# HIGH tim e.

V

IH

IL

RAS#

V

IH

IL

CAS#

V

IH

IL

ADDR

ROW

COLUMN (A)

COLUMN (B)

COLUMN (C)

COLUMN (D)

V

IOH

IOL

DQ

OPEN

VALID DATA (A)

VALID DATA (C)

VALID DATA (D)

VALID DATA (B)

t

OD

t

OD

t

OES

t

OEHC

V

IH

IL

OE#

t

OE

t

OEP

The DQs go back to

Low-Z if OES is met.

The DQs remain High-Z

until the next CAS# cycle

if OEHC is met.

The DQs remain High-Z

until the next CAS# cycle

if OEP is met.

t

Fig u re 1

OE# Co n t ro l o f DQs

V

IH

IL

RAS#

CAS#

V

IH

IL

V

IH

IL

ADDR

ROW

COLUMN (A)

COLUMN (B)

COLUMN (C)

COLUMN (D)

V

IOH

IOL

DQ

OPEN

VALID DATA (A)

VALID DATA (B)

INPUT DATA (C)

t

WHZ

t

V

IH

WE#

OE#

WPZ

V

IL

V

IH

IL

t

The DQs go to High-Z if WE# falls and, if WPZ is met,

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

DON’T CARE

UNDEFINED

Fig u re 2

WE# Co n t ro l o f DQs

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

16 MEG x 4

EDO DRAM

*Stresses greater th an th ose listed un der “Absolute

Maxim um Ratin gs” m ay cause perm an en t dam age to

th e device. Th is is a stress ratin g on ly, an d fun ction al

operation of th e device at th ese or an y oth er con dition s

above th ose in dicated in th e operation al section s of

th is specification is n ot im plied. Exposure to absolute

m axim um ratin g con dition s for exten ded periods m ay

affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................ -1V to +4.6V

Voltage on NC, In puts or I/O Pin s

Relative to V^SS....................................... -1V to +4.6V

Operatin g Tem perature, T_A(am bien t) ... 0°C to +70°C

Storage Tem perature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Note: 1) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL MIN

MAX UNITS NOTES

SUPPLY VOLTAGE

VCC

VIH

VIL

II

3

3.6

VCC + 0.3

0.8

V

INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC

2

V

26

27

INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC

-0.3

-2

V

INPUT LEAKAGE CURRENT:

Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V);

All other pins not under test = 0V

2

µA

OUTPUT HIGH VOLTAGE:

IOUT = -2mA

VOH

VOL

IOZ

2.4

–

0.4

5

V

OUTPUT LOW VOLTAGE:

IOUT = 2mA

OUTPUT LEAKAGE CURRENT:

Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V);

DQ is disabled and in High-Z state

-5

µA

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

16 MEG x 4

EDO DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

4K

8K

PARAMETER/CONDITION

SYMBOL SPEED REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL

I

CC

1

ALL

1

mA

(RAS# = CAS# = VIH

)

STANDBY CURRENT: CMOS

(RAS# = CAS# VCC - 0.2V; DQs may be left open;

Other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V)

ICC

2

500

µA

OPERATING CURRENT: Random READ/WRITE

Average power supply current

I

CC

3

-5

-6

170

160

130

120

mA

25

t

(RAS#, CAS#, address cycling: ^tRC = RC [MIN])

OPERATING CURRENT: EDO PAGE MODE

Average power supply current

ICC

4

-5

-6

150

120

150

120

mA

t

(RAS# = VIL, CAS#, address cycling: ^tPC = PC [MIN])

REFRESH CURRENT: RAS#-ONLY

Average power supply current

ICC

5

-5

-6

170

160

130

120

22

t

(RAS# cycling, CAS# = VIH: ^tRC = RC [MIN])

REFRESH CURRENT: CBR

ICC

6

-5

-6

160

150

160

150

4, 7

Average power supply current

t

(RAS#, CAS#, address cycling: ^tRC = RC [MIN])

REFRESH CURRENT: Extended (“S” version only)

Average power supply current: CAS# = 0.2V or CBR cycling;

I

CC

7

ALL

400

µA

4, 7

RAS# = ^tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and

DIN = VCC - 0.2V or 0.2V (DIN may be left open)

REFRESH CURRENT: Self (“S” version only)

Average power supply current: CBR with

RAS# ^tRASS (MIN) and CAS# held LOW;

WE# = V^CC- 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V

(DIN may be left open)

ICC

8

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

16 MEG x 4

EDO DRAM

CAPACITANCE

(Note: 2)

PARAMETER

SYMBOL MAX

UNITS

pF

Input Capacitance: Address pins

Input Capacitance: RAS#, CAS#, WE#, OE#

Input/Output Capacitance: DQ

CI1

CI2

CIO

5

7

pF

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

NOTES

t

Access time from column address

Column-address setup to CAS# precharge

Column-address hold time (referenced to RAS#)

Column-address setup time

Row-address setup time

AA

25

30

t

ACH

12

38

0

15

45

0

t

AR

t

ASC

ASR

t

0

t

Column address to WE# delay time

Access time from CAS#

AWD

42

49

18

t

CAC

CAH

13

15

t

Column-address hold time

CAS# pulse width

8

10

15

10

0

t

CAS

CHD

CHR

10,000

t

CAS# LOW to “Don’t Care” during Self Refresh

CAS# hold time (CBR Refresh)

CAS# to output in Low-Z

Data output hold after CAS# LOW

CAS# precharge time

15

8

t

4

t

CLZ

0

t

COH

3

t

CP

8

10

13

t

Access time from CAS# precharge

CAS# to RAS# precharge time

CAS# hold time

CPA

CRP

CSH

CSR

28

35

t

5

38

5

45

5

t

CAS# setup time (CBR Refresh)

CAS# to WE# delay time

4

t

CWD

28

8

35

10

0

18

t

WRITE command to CAS# lead time

Data-in hold time

CWL

t

DH

8

19

t

Data-in setup time

DS

0

t

Output disable

OD

0

12

0

15

23, 24

20

t

Output enable time

OE

t

OE# hold time from WE# during

READ-MODIFY-WRITE cycle

OEH

8

10

24

t

OE# HIGH hold time from CAS# HIGH

OE# HIGH pulse width

OEHC

5

4

0

10

5

ns

t

OEP

t

OE# LOW to CAS# HIGH setup time

Output buffer turn-off delay

OES

5

t

OFF

12

0

15

17, 23

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

16 MEG x 4

EDO DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

t

OE# setup prior to RAS# during

HIDDEN REFRESH cycle

ORD

0

ns

t

EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time

Access time from RAS#

PC

20

47

25

56

ns

µs

ns

ms

ns

t

PRWC

t

RAC

50

60

23

15

t

RAS# to column-address delay time

Row-address hold time

RAD

9

12

10

60

100

104

14

0

t

RAH

t

RAS# pulse width

RAS

50

100

84

11

0

10,000

t

RAS# pulse width (EDO PAGE MODE)

RAS# pulse width during Self Refresh

Random READ or WRITE cycle time

RAS# to CAS# delay time

RASP

RASS

125,000

t

RC

t

RCD

RCH

RCS

14

16

t

READ command hold time (referenced to CAS#)

READ command setup time

t

0

t

Refresh period

REF

64

22

4

Refresh period (4,096 cycles) “S” version

RAS# precharge time

128

t

RP

30

5

40

5

t

RAS# to CAS# precharge time

RAS# precharge time exiting Self Refresh

READ command hold time (referenced to RAS#)

RAS# hold time

RPC

RPS

t

90

0

105

0

t

RRH

RSH

16

18

t

13

116

67

13

2

15

140

79

15

2

t

READ-WRITE cycle time

RWC

t

RAS# to WE# delay time

RWD

t

WRITE command to RAS# lead time

Transition time (rise or fall)

RWL

t

T

50

12

50

15

WRITE command hold time

WCH

WCR

8

10

45

0

t

WRITE command hold time (referenced to RAS#)

WE# command setup time

38

0

t

WCS

WHZ

18

t

WE# to outputs in High-Z

0

t

WRITE command pulse width

WE# pulse width to disable outputs

WE# hold time (CBR Refresh)

WE# setup time (CBR Refresh)

WP

5

t

WPZ

WRH

WRP

10

8

10

t

4, 23

t

8

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

16 MEG x 4

EDO DRAM

NOTES

t

1. All voltages referen ced to VSS.

17. OFF (MAX) defin es th e tim e at wh ich th e output

ach ieves th e open circuit con dition an d is n ot

referen ced to V^OHor VOL.

2. Th is param eter is sam pled. V^CC= +3.3V; f = 1

MHz; T_A= 25°C.

t

3. ICC is depen den t on output loadin g an d cycle

rates. Specified values are obtain ed with m in i-

m um cycle tim e an d th e outputs open .

4. En ables on -ch ip refresh an d address coun ters.

5. Th e m in im um specification s are used on ly to

in dicate cycle tim e at wh ich proper operation

over th e full tem perature ran ge is en sured.

6. An in itial pause of 100µs is required after power-

up, followed by eigh t RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is en sured. Th e eigh t RAS# cycle

18. WCS, ^tRWD, ^tAWD, an d CWD are n ot restrictive

operatin g param eters. ^tWCS applies to EARLY

t

WRITE cycles. If WCS > WCS (MIN), th e cycle is

an EARLY WRITE cycle an d th e data output will

rem ain an open circuit th rough out th e en tire

cycle. RWD, AWD, an d CWD defin e READ-

MODIFY-WRITE cycles. Meetin g th ese lim its

allows for readin g an d disablin g output data an d

th en applyin g in put data. OE# h eld HIGH an d

WE# taken LOW after CAS# goes LOW results in a

t

LATE WRITE (OE#-con trolled) cycle. WCS,

^tRWD, CWD, an d AWD are n ot applicable in a

t

wake-ups sh ould be repeated an y tim e th e REF

refresh requirem en t is exceeded.

7. AC ch aracteristics assum e T = 2.5n s.

LATE WRITE cycle.

t

19. Th ese param eters are referen ced to CAS# leadin g

edge in EARLY WRITE cycles an d WE# leadin g

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied perm an en tly LOW, LATE WRITE or

READ-MODIFY-WRITE operation s are n ot

possible.

21. A HIDDEN REFRESH m ay also be perform ed after

a WRITE cycle. In th is case, WE# is LOW an d

OE# is HIGH.

22. RAS#-ONLY REFRESH requires th at all rows be

refresh ed at least on ce every 64m s (4,096 rows

for th e H9 version an d 8,192 rows for th e G3

version ). CBR REFRESH requires th at at least

4,096 cycles be com pleted every 64m s.

8. VIH (MIN) an d VIL (MAX) are referen ce levels for

m easurin g tim in g of in put sign als. Tran sition

tim es are m easured between V^IHan d VIL (or

between VIL an d VIH).

9. In addition to m eetin g th e tran sition rate

specification , all in put sign als m ust tran sit

between V^IHan d VIL (or between VIL an d VIH) in a

m on oton ic m an n er.

10. If CAS# an d RAS# = V^IH, data output is High -Z.

11. If CAS# = VIL, data output m ay con tain data from

th e last valid READ cycle.

12. Measured with a load equivalen t to two TTL

gates an d 100pF; an d V^OL= 0.8V an d VOH = 2V.

13. If CAS# is LOW at th e fallin g edge of RAS#,

output data will be m ain tain ed from th e previous

cycle. To in itiate a n ew cycle an d clear th e data-

t

23. Th e DQs open durin g READ cycles on ce OD or

^tOFF occur. If CAS# stays LOW wh ile OE# is

brough t HIGH, th e DQs will open . If OE# is

brough t back LOW (CAS# still LOW), th e DQs

will provide th e previously read data.

t

out buffer, CAS# m ust be pulsed HIGH for CP.

t

14. Th e RAD (MAX) lim it is n o lon ger specified.

^tRAD (MAX) was specified as a referen ce poin t

t

on ly. If RAD was greater th an th e specified RAD

(MAX) lim it, th en access tim e was con trolled

24. LATE WRITE an d READ-MODIFY-WRITE cycles

t

m ust h ave both OD an d OEH m et (OE# HIGH

durin g WRITE cycle) in order to en sure th at th e

output buffers will be open durin g th e WRITE

cycle. If OE# is taken back LOW wh ile CAS#

rem ain s LOW, th e DQs will rem ain open .

25. Colum n address ch an ged on ce each cycle.

26. VIH oversh oot: VIH (MAX) = VCC + 2V for a pulse

width ≤ 10n s, an d th e pulse width can n ot be

greater th an on e th ird of th e cycle rate. VIL

un dersh oot: VIL (MIN) = -2V for a pulse width ≤

10n s, an d th e pulse width can n ot be greater th an

on e th ird of th e cycle rate.

t

exclusively by AA (^tRAC an d CAC n o lon ger

t

applied). With or with out th e RAD (MAX) lim it,

^tAA, RAC, an d CAC m ust always be m et.

t

15. Th e RCD (MAX) lim it is n o lon ger specified.

^tRCD (MAX) was specified as a referen ce poin t

t

on ly. If RCD was greater th an th e specified RCD

(MAX) lim it, th en access tim e was con trolled

t

exclusively by CAC (^tRAC [MIN] n o lon ger

t

applied). With or with out th e RCD lim it, AA

an d CAC m ust always be m et.

t

16. Eith er RCH or RRH m ust be satisfied for a READ

cycle.

27. NC pin s are assum ed to be left floatin g an d are

n ot tested for leakage.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

16 MEG x 4

EDO DRAM

READ CYCLE

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CSH

t

RRH

RSH

t

RCD

CAS

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASR

ASC

CAH

t

ACH

V

IH

IL

ROW

COLUMN

ADDR

WE#

t

RCH

RCS

V

IH

IL

t

AA

RAC

CAC

CLZ

NOTE 1

t

OFF

V

OH

OL

DQ

OPEN

VALID DATA

t

OD

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OFF

0

t

ACH

12

38

0

15

45

0

ns

RAC

50

60

ns

t

AR

ns

RAD

9

12

10

60

104

14

0

ns

t

ASC

ns

RAH

ns

t

ASR

0

ns

RAS

50

84

11

0

10,000

ns

t

CAC

13

15

ns

RC

ns

t

CAH

8

10

0

ns

RCD

ns

t

CAS

10,000

ns

RCH

ns

t

CLZ

0

ns

RCS

0

ns

t

CRP

5

ns

RP

30

0

40

0

ns

t

CSH

38

0

45

0

ns

RRH

ns

t

OD

12

15

ns

RSH

13

15

ns

t

OE

ns

t

NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

16 MEG x 4

EDO DRAM

EARLY WRITE CYCLE

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CRP

RCD

CAS

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

t

ASR

CAH

t

ACH

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

t

RWL

WCR

WCH

WP

t

WCS

WE#

V

IH

IL

t

DS

DH

V

IOH

IOL

DQ

VALID DATA

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

12

38

0

MAX

MIN

15

45

0

MAX

UNITS

ns

SYMBOL

MIN

9

MAX

MIN

10

60

104

14

40

15

10

45

0

MAX

UNITS

ns

t

ACH

RAH

t

AR

ns

RAS

50

84

11

30

13

8

10,000

ns

t

ASC

ns

RC

ns

t

ASR

0

ns

RCD

ns

t

CAH

8

10

5

ns

RP

ns

t

CAS

8

10,000

ns

RSH

ns

t

CRP

5

ns

RWL

ns

t

CSH

38

8

45

15

10

0

ns

WCH

ns

t

CWL

ns

WCR

38

0

ns

t

DH

8

ns

WCS

ns

t

DS

0

ns

WP

5

ns

t

RAD

9

12

ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

16 MEG x 4

EDO DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CAS

CRP

ASR

RCD

V

IH

IL

t

AR

t

RAD

t

CAH

t

ASC

RCS

RAH

t

ACH

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

CWL

RWL

WP

t

CWD

t

AWD

V

IH

IL

WE#

t

AA

t

RAC

t

CAC

t

DS

DH

t

CLZ

V

IOH

IOL

VALID D

DQ

OPEN

OUT

IN

t

OE

OD

OEH

V

IH

IL

OE#

DON’ T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OD

0

t

ACH

12

38

0

15

45

0

ns

OE

12

15

ns

t

AR

ns

OEH

RAC

RAD

RAH

RAS

RCD

RCS

RP

8

10

ns

t

ASC

ns

50

60

ns

t

ASR

0

ns

9

12

10

60

14

0

ns

t

AWD

42

49

ns

t

CAC

13

15

ns

50

11

0

10,000

ns

t

CAH

8

10

0

ns

t

CAS

10,000

ns

t

CLZ

0

ns

30

13

116

67

13

5

40

15

140

79

15

5

ns

t

CRP

5

ns

RSH

RWC

ns

t

CSH

38

28

8

45

35

10

0

ns

t

CWD

ns

RWD

RWL

WP

ns

t

CWL

ns

t

DH

8

ns

t

DS

0

ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ CYCLE

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

RSH

CSH

PC

t

CRP

RCD

CAS

CP

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

ACH

RAD

RAH

ACH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

WE#

ROW

COLUMN

ROW

t

RCS

t

RCH

V

IH

IL

t

RRH

AA

t

AA

CPA

CAC

t

RAC

CPA

CAC

t

CAC

CLZ

t

OEHC

t

OFF

t

COH

t

CLZ

V

OH

OL

VALID

DATA

VALID

DATA

VALID

OPEN

DQ

OPEN

DATA

t

OE

t

OD

t

OES

t

V

OES

IH

IL

OE#

t

OEP

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

10

5

MAX

UNITS

ns

t

AA

25

30

OEHC

5

t

ACH

12

38

0

15

45

0

ns

OEP

ns

t

AR

ns

OES

4

5

ns

t

ASC

ns

OFF

0

12

50

0

15

60

ns

t

ASR

0

ns

PC

20

25

ns

t

CAC

13

15

ns

RAC

ns

t

CAH

8

0

3

8

10

0

ns

RAD

9

12

10

60

0

ns

t

CAS

10,000

ns

RAH

ns

t

CLZ

ns

RASP

50

0

125,000

ns

t

COH

3

ns

RCH

ns

t

CP

10

ns

RCD

11

0

14

0

ns

t

CPA

28

35

ns

RCS

ns

t

CRP

5

38

0

5

45

0

ns

RP

30

0

40

0

ns

t

CSH

ns

RRH

ns

t

OD

12

15

ns

RSH

13

15

ns

t

OE

ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE EARLY WRITE CYCLE

t

RP

RASP

V

IH

IL

RAS#

CAS#

t

CSH

PC

RSH

CAS

t

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

ACH

CAH

ACH

CAH

t

ASC

ASR

RAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

WCH

WP

CWL

WCH

WP

t

WCS

WCH

WP

WCS

V

IH

IL

WE#

DQ

t

WCR

DH

RWL

t

DS

DH

DS

DH

V

IOH

IOL

VALID DATA

V

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

12

38

0

MAX

MIN

15

45

0

MAX

UNITS

ns

SYMBOL

MIN

20

9

MAX

MIN

25

12

10

60

14

40

15

10

45

0

MAX

UNITS

ns

t

ACH

PC

t

AR

ns

RAD

ns

t

ASC

ns

RAH

9

ns

t

ASR

0

ns

RASP

50

11

30

13

8

125,000

ns

t

CAH

8

10

5

ns

RCD

ns

t

CAS

8

10,000

ns

RP

ns

t

CP

8

ns

RSH

ns

t

CRP

5

ns

RWL

ns

t

CSH

38

8

45

10

0

ns

WCH

ns

t

CWL

ns

WCR

38

0

ns

t

DH

8

ns

WCS

ns

t

DS

0

ns

WP

5

ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CAS

CRP

ASR

RCD

V

IH

IL

t

AR

t

CAH

RAD

ASC

RCS

t

ACH

RAH

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

CWL

RWL

WP

t

CWD

t

AWD

V

IH

IL

WE#

t

AA

t

RAC

t

CAC

t

DS

DH

t

CLZ

V

IOH

IOL

VALID D

DQ

OPEN

OUT

IN

t

OE

OD

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OD

OE

0

t

AR

38

0

45

0

ns

12

15

ns

t

ASC

ns

OEH

PC

8

10

25

56

ns

t

ASR

0

ns

20

47

ns

t

AWD

42

49

ns

PRWC

RAC

RAD

RAH

RASP

RCD

RCS

ns

t

CAC

13

15

ns

50

60

ns

t

CAH

8

0

8

10

0

ns

9

12

10

60

14

0

ns

t

CAS

10,000

28

10,000

ns

9

ns

t

CLZ

ns

50

11

0

125,000

ns

t

CP

10

ns

t

CPA

35

ns

t

CRP

5

38

28

8

5

ns

RP

30

13

67

13

5

40

15

79

15

5

ns

t

CSH

45

35

10

0

ns

RSH

ns

t

CWD

ns

RWD

RWL

WP

ns

t

CWL

ns

t

DH

8

ns

t

DS

0

ns

t

NOTE: 1. PC is for LATE WRITE cycles only.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RP

RASP

V

IH

IL

RAS#

CAS#

t

CSH

t

PC

RSH

PC

t

CP

CRP

RCD

CAS

CP

CAS

CP

CAS

V

IH

IL

t

AR

t

RAD

ACH

CAH

t

ASR

t

ASC

RAH

ASC

CAH

ASC

CAH

V

IH

IL

ADDR

WE#

ROW

COLUMN (A)

COLUMN (B)

ROW

COLUMN (N)

t

RCH

t

RCS

WCS

WCH

V

IH

IL

t

AA

t

AA

t

CPA

RAC

t

DH

t

CAC

DS

CAC

t

WHZ

COH

V

IOH

IOL

VALID

DATA (B)

DQ

VALID DATA

IN

OPEN

VALID DATA (A)

t

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

t

AA

25

30

OE

12

15

t

ACH

12

38

0

15

45

0

ns

PC

20

25

ns

t

AR

ns

RAC

50

60

ns

t

ASC

ns

RAD

9

12

10

60

14

0

ns

t

ASR

0

ns

RAH

ns

t

CAC

13

15

ns

RASP

50

11

0

125,000

ns

t

CAH

8

3

8

10

3

ns

RCD

ns

t

CAS

10,000

ns

RCH

ns

t

COH

ns

RCS

0

ns

t

CP

10

ns

RP

30

13

8

40

15

10

0

ns

t

CPA

28

35

ns

RSH

ns

t

CRP

5

38

8

5

45

10

0

ns

WCH

ns

t

CSH

ns

WCS

0

ns

t

DH

ns

WHZ

0

12

0

15

ns

t

DS

0

ns

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

16 MEG x 4

EDO DRAM

READ CYCLE

(With WE#-controlled disable)

V

IH

IL

RAS#

CAS#

t

CSH

t

CP

RCD

CAS

CAH

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

ASR

ASC

V

IH

IL

ROW

COLUMN

ADDR

WE#

t

RCS

t

RCH

WPZ

RCS

V

IH

IL

t

AA

RAC

CAC

CLZ

t

WHZ

CLZ

V

OH

OL

DQ

OPEN

VALID DATA

t

OD

OE

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

ns

OD

0

t

AR

38

0

45

0

OE

12

15

ns

t

ASC

RAC

50

60

ns

t

ASR

0

RAD

9

12

10

14

0

ns

t

CAC

13

15

RAH

ns

t

CAH

8

10

0

RCD

11

0

ns

t

CAS

10,000

RCH

ns

t

CLZ

0

RCS

0

ns

t

CP

8

10

5

WHZ

0

12

0

15

ns

t

CRP

5

WPZ

10

ns

t

CSH

38

45

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

16 MEG x 4

EDO DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CRP

RPC

V

IH

IL

t

RAH

ASR

V

IH

IL

ADDR

DQ

ROW

V

OH

OL

OPEN

V

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RAS

RP

RAS

NOTE 1

RP

V

IH

IL

RAS#

t

RPC

CP

t

RPC

t

CHR

CSR

CHR

CSR

V

IH

IL

CAS#

DQ

V

OH

OL

OPEN

V

t

WRH

WRP

WRH

WRP

V

IH

IL

WE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

0

MAX

UNITS

ns

SYMBOL

MIN

50

84

30

5

MAX

MIN

MAX

UNITS

ns

t

ASR

0

8

5

9

RAS

10,000

60

104

40

5

10,000

t

CHR

10

5

ns

RC

ns

t

CP

ns

RP

ns

t

CRP

ns

RPC

ns

t

CSR

5

ns

WRH

8

10

ns

t

RAH

10

ns

WRP

8

ns

NOTE: 1. End of first CBR REFRESH cycle.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

16 MEG x 4

EDO DRAM

1

HIDDEN REFRESH CYCLE

(WE# = HIGH; OE# = LOW)

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

RSH

CRP

RCD

t

CHR

V

IH

IL

t

AR

t

RAD

t

CAH

ASR

RAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

AA

t

RAC

t

OFF

CAC

t

CLZ

V

OH

OL

DQ

OPEN

VALID DATA

OPEN

t

OE

OD

t

ORD

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

MAX

15

UNITS

ns

t

AA

25

30

OE

12

t

AR

38

0

45

0

ns

OFF

ORD

RAC

RAD

RAH

RAS

RCD

RP

0

15

ns

t

ASC

ns

t

ASR

0

ns

50

60

ns

t

CAC

13

12

15

ns

9

12

10

60

14

40

15

ns

t

CAH

8

0

5

0

10

0

ns

9

ns

t

CHR

ns

50

11

30

13

10,000

ns

t

CLZ

ns

t

CRP

5

ns

t

OD

0

ns

RSH

ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

16 MEG x 4

EDO DRAM

SELF REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

NOTE 1

t

RP

RASS

RPS

( (

) )

NOTE 2

V

IH

IL

RAS#

CAS#

t

( (

) )

( (

) )

RPC

CP

RPC

t

CP

CSR

CHD

( (

) )

V

IH

IL

( (

) )

V

( (

) )

OH

OL

OPEN

DQ

t

WRH

WRP

WRH

WRP

( (

) )

V

IH

IL

WE#

( (

) )

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

15

8

MAX

MIN

15

MAX

UNITS

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

t

CHD

ns

µs

ns

RPC

5

90

8

5

t

CP

10

RPS

105

10

ns

t

CSR

5

WRH

ns

t

RASS

100

30

100

40

WRP

8

10

ns

t

RP

t

NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

t

2. Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only por Burst CBR refresh is being used.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

16 MEG x 4

EDO DRAM

32-PIN PLASTIC SOJ (400 m il)

.829 (21.05)

.823 (20.90)

.445 (11.31)

.435 (11.05)

.405 (10.29)

.399 (10.13)

PIN #1 ID

.050 (1.27) TYP

.750 (19.05) TYP

.037 (0.95) MAX DAMBAR PROTRUSION

.024 (0.61)

.032 (0.82)

.026 (0.67)

.030 (0.76)

MIN

.145 (3.68)

.132 (3.35)

.095 (2.42)

.080 (2.03)

SEATING PLANE

.020 (0.51)

.015 (0.38)

.380 (9.65)

.360 (9.14)

.040 (1.02)

R

.030 (0.77)

MAX

MIN

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

16 MEG x 4

EDO DRAM

32-PIN PLASTIC TSOP (400 m il)

.827 (21.01)

.823 (20.91)

SEE DETAIL A

.050 (1.27)

TYP

.0375 (0.95)

32

.467 (11.86)

.459 (11.66)

.402 (10.21)

.398 (10.11)

16

1

.020 (0.50)

.012 (0.30)

.007 (0.18)

.005 (0.13)

.010 (0.25)

.004 (0.10)

.047(1.19)

MAX

GAGE PLANE

.008 (0.20)

.002 (0.05)

.0315 (0.80)

.024 (0.60)

.016 (0.40)

DETAIL A

MAX

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900

E-m a il: p ro d m kt g @m icro n .co m , In t e rn e t : h t t p ://w w w .m icro n .co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

16 Meg x 4 EDO DRAM

D22_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22


型号：	MT4LC16M4G3DJ-5
厂家：	MICRON TECHNOLOGY
描述：	DRAM DRAM 内存集成电路光电二极管动态存储器
文件：	总22页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT4LC16M4G3DJ-5 [MICRON]

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