MT4LC4M4B1TG-6S_技术文档

4 MEG x 4

FPM DRAM

MT4LC4M4B1, MT4C4M4B1

MT4LC4M4A1, MT4C4M4A1

For the latest data sheet, please refer to the Micron Web

site: www.micronsemi.com/mti/msp/html/datasheet.html

DRAM

FEATURES

• In dustry-stan dard x4 pin out, tim in g, fun ction s,

an d packages

PIN ASSIGNMENT (To p Vie w )

• High -perform an ce, low-power CMOS silicon -gate

process

• Sin gle power supply (+3.3V ±0.3V or +5V ±0.5V)

• All in puts, outputs an d clocks are TTL-com patible

• Refresh m odes: RAS#-ONLY, HIDDEN an d CAS#-

BEFORE-RAS# (CBR)

• Option al self refresh (S) for low-power data

reten tion

• 11 row, 11 colum n addresses (2K refresh ) or

12 row, 10 colum n addresses (4K refresh )

• FAST-PAGE-MODE (FPM) access

• 5V toleran t in puts an d I/Os on 3.3V devices

24/26-Pin SOJ

24/26-Pin TSOP

V

DQ0

DQ1

WE#

RAS#

CC

1

2

3

4

5

6

26

25

24

23

22

21

VSS

V

DQ0

DQ1

WE#

RAS#

CC

1

2

3

4

5

6

26

25

24

23

22

21

VSS

DQ3

DQ2

CAS#

OE#

A9

DQ3

DQ2

CAS#

OE#

A9

**NC/A11

A10

A0

A1

A2

A3

8

9

10

11

12

13

19

18

17

16

15

14

A8

A7

A6

A5

A4

A10

A0

A1

A2

A3

8

9

10

11

12

13

19

18

17

16

15

14

A8

A7

A6

A5

A4

V

CC

VSS

V

CC

VSS

OPTIONS

• Voltage

MARKING

3.3V

5V

LC

C

**NC on 2K refresh and A11 on 4K refresh options.

• Refresh Addressin g

2,048 (2K) rows

4,096 (4K) rows

• Packages

B1

A1

4 MEG x 4 FPM DRAM PART NUMBERS

Plastic SOJ (300 m il)

Plastic TSOP (300 m il)

• Tim in g

50n s access

60n s access

• Refresh Rates

Stan dard Refresh

Self Refresh (128m s period)

D J

TG

REFRESH

PARTNUMBER

V^CCADDRESSING PACKAGE REFRESH

MT4LC4M4B1DJ-6

3.3V

2K

4K

2K

4K

SOJ

Standard

Self

-5

-6

MT4LC4M4B1DJ-6 S 3.3V

MT4LC4M4B1TG-6 3.3V

MT4LC4M4B1TG-6 S 3.3V

MT4LC4M4A1DJ-6 3.3V

MT4LC4M4A1DJ-6 S 3.3V

MT4LC4M4A1TG-6 3.3V

MT4C4M4A1TG-6S 3.3V

TSOP

SOJ

Standard

Self

Non e

S*

Standard

Self

SOJ

NOTE: 1. Th e 4 Meg x 4 FPM DRAM base n um ber differen ti-

ates th e offerin gs in on e place—MT4LC4M4B1. Th e

fifth field distin guish es various option s: B1

design ates a 2K refresh an d A1 design ates a 4K

refresh for FPM DRAMs.

TSOP

SOJ

Standard

Self

MT4C4M4B1DJ-6

MT4C4M4B1DJ-6 S

MT4C4M4B1TG-6

5V

Standard

Self

SOJ

2. Th e # sym bol in dicates sign al is active LOW.

TSOP

SOJ

Standard

Self

*Con tact factory for availability

MT4C4M4B1TG-6S 5V

MT4C4M4A1DJ-6 5V

MT4C4M4A1DJ-6 S 5V

MT4C4M4A1TG-6 5V

MT4C4M4A1TG-6S 5V

Standard

Self

Part Number Example:

SOJ

MT4LC4M4B1DJ

TSOP

Standard

Self

KEY TIMING PARAMETERS

t

SPEED

-5

RC

RAC

PC

AA

CAC

RP

84ns

50ns

60ns

20ns

35ns

25ns

30ns

13ns

15ns

30ns

40ns

-6

110ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

1

4 MEG x 4

FPM DRAM

GENERALDESCRIPTION

Th e 4 Meg x 4 DRAM is a ran dom ly accessed, solid-

state m em ory con tain in g 16,777,216 bits organ ized in

a x4 con figuration . RAS# is used to latch th e row

address (first 11 bits for 2K an d first 12 bits for 4K). On ce

th e page h as been open ed by RAS#, CAS# is used to latch

th e colum n address (th e latter 11 bits for 2K an d th e

latter 10 bits for 4K; address pin s A10 an d A11 are “Don ’t

Care”).

Addition al colum n s m ay be accessed by providin g valid

colum n addresses, strobin g CAS# an d h oldin g RAS#

LOW, th us executin g faster m em ory cycles. Return in g

RAS# HIGH term in ates th e page m ode of operation ,

i.e., closes th e page.

DRAM REFRESH

Preserve correct m em ory cell data by m ain tain in g

power an d executin g an y RAS# cycle (READ, WRITE)

or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HID-

DEN) so th at all com bin ation s of RAS# addresses (2,048

for 2K an d 4,096 for 4K) are executed with in ^tREF

(MAX), regardless of sequen ce. Th e CBR an d SELF

REFRESH cycles will in voke th e in tern al refresh coun ter

for autom atic RAS# addressin g.

READ an d WRITE cycles are selected with th e WE#

in put. A logic HIGH on WE# dictates read m ode, wh ile

a logic LOW on WE# dictates write m ode. Durin g a

WRITE cycle, data-in (D) is latch ed by th e fallin g edge

of WE# or CAS#, wh ich ever occurs last. If WE# goes

LOW prior to CAS# goin g LOW, th e output pin s

rem ain open (High - Z) un til th e n ext CAS# cycle,

regardless of OE#.

A logic HIGH on WE# dictates read m ode, wh ile a

logic LOW on WE# dictates write m ode. Durin g a

WRITE cycle, data-in (D) is latch ed by th e fallin g edge

of WE# or CAS#, wh ich ever occurs last. An EARLY

WRITE occurs wh en WE# is taken LOW prior to CAS#

fallin g. A LATE WRITE or READ-MODIFY-WRITE

occurs wh en WE# falls after CAS# is taken LOW. Durin g

EARLY WRITE cycles, th e data outputs (Q) will rem ain

High -Z regardless of th e state of OE#. Durin g LATE

WRITE or READ-MODIFY-WRITE cycles, OE# m ust be

taken HIGH to disable th e data outputs prior to

applyin g in put data. If a LATE WRITE or READ-

MODIFY-WRITE is attem pted wh ile keepin g OE# LOW,

n o WRITE will occur, an d th e data outputs will drive

read data from th e accessed location .

An option al self refresh m ode is also available th e

“S” version . Th e self refresh feature is in itiated by

perform in g a CBR REFRESH cycle an d h oldin g RAS#

t

LOW for th e specified RASS. Th e “S” option allows th e

user th e ch oice of a fully static, low-power data reten -

tion m ode or a dyn am ic refresh m ode at th e exten ded

refresh period of 128m s, or 31.25µs per row for a 4K

refresh an d 62.5µs per row for a 2K refresh , wh en usin g

a distributed CBR REFRESH. Th is refresh rate can be

applied durin g n orm al operation , as well as durin g a

stan dby or battery backup m ode.

Th e self refresh m ode is term in ated by drivin g RAS#

HIGH for a m in im um tim e of ^tRPS. Th is delay allows for

th e com pletion of an y in tern al refresh cycles th at m ay

be in process at th e tim e of th e RAS# LOW-to-HIGH

tran sition . If th e DRAM con troller uses a distributed

CBR refresh sequen ce, a burst refresh is n ot required

upon exitin g self refresh . However, if th e DRAM con -

troller utilizes RAS#-ONLY or burst CBR refresh se-

quen ce, all rows m ust be refresh ed with a refresh rate of

^tRC m in im um prior to resum in g n orm al operation .

Th e four data in puts an d th e four data outputs are

routed th rough four pin s usin g com m on I/O, an d pin

direction is con trolled by WE# an d OE#.

Th e MT4LC4M4B1 an d MT4LC4M4A1 m ust be

refresh ed periodically in order to retain stored data.

FAST PAGE MODE ACCESS

STANDBY

Page operation s allow faster data operation s (READ,

W RITE or READ-MODIFY-W RITE) with in a row-

address-defin ed page boun dary. Th e page cycle is al-

ways in itiated with a row address strobed in by RAS#,

followed by a colum n address strobed in by CAS#.

Return in g RAS# an d CAS# HIGH term in ates a

m em ory cycle an d decreases ch ip curren t to a reduced

stan dby level. Th e ch ip is precon dition ed for th e n ext

cycle durin g th e RAS# HIGH tim e.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

2

4 MEG x 4

FPM DRAM

FUNCTIONAL BLOCK DIAGRAM – 2K REFRESH

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

DQ3

4

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(11)

COLUMN

DECODER

10

1

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

11

4

1,024

REFRESH

CONTROLLER

SENSE AMPLIFIERS

I/O GATING

1,024

REFRESH

COUNTER

2,048

11

4,096 x 1,024 x 4

MEMORY

ROW-

ADDRESS

BUFFERS (11)

ARRAY

11

2,048

NO. 1 CLOCK

GENERATOR

V

DD

SS

RAS#

FUNCTIONAL BLOCK DIAGRAM – 4K REFRESH

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

DQ3

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(10)

COLUMN

DECODER

10

A0

A1

10

4

1,024

A2

REFRESH

CONTROLLER

A3

SENSE AMPLIFIERS

I/O GATING

A4

A5

1,024

A6

REFRESH

COUNTER

A7

A8

12

A9

4,096 x 1,024 x 4

MEMORY

4,096

A10

A11

ROW-

ADDRESS

BUFFERS (12)

ARRAY

12

4,096

NO. 1 CLOCK

GENERATOR

V

DD

RAS#

Vss

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

3

4 MEG x 4

FPM DRAM

*Stresses greater th an th ose listed un der “Absolute Maxi-

m um Ratin gs” m ay cause perm an en t dam age to th e

device. Th is is a stress ratin g on ly, an d fun ction al opera-

tion of th e device at th ese or an y oth er con dition s above

th ose in dicated in th e operation al section s of th is speci-

fication is n ot im plied. Exposure to absolute m axim um

ratin g con dition s for exten ded periods m ay affect

reliability.

ABSOLUTEMAXIMUM RATINGS*

Voltage on VCC Pin Relative to VSS

3.3V............................................. ......... -1V to +4.6V

5V................................................ ............ -1V ^TO+7V

Voltage on NC, In puts or I/O Pin s Relative to VSS

3.3V............................................. ......... -1V to +5.5V

5V................................................ ............ -1V ^TO+7V

Operatin g Tem perature, T_A(am bien t) .... 0°C to +70°C

Storage Tem perature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 5, 6) (VCC (MIN) £ VCC£ VCC (MAX))

3.3V

5 V

PARAMETER/CONDITION

SYMBOL M IN M AX M IN M AX UNITS NOTES

SUPPLY VOLTAGE

VCC

VIH

VIL

II

3

3.6

5.5

0.8

2

4.5

2.4

-0.5

-2

5.5

Vcc+1

0.8

V

INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC

2

V

24

INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC

-1.0

-2

V

INPUT LEAKAGE CURRENT:

Any input at VIN [0V £ VIN £ VCC (MAX)];

All other pins not under test = 0V

2

µA

OUTPUT HIGH VOLTAGE:

IOUT = -2mA

VOH

VOL

IOZ

2.4

–

0.4

5

2.4

–

0.4

5

V

OUTPUT LOW VOLTAGE:

IOUT = 2mA

OUTPUT LEAKAGE CURRENT:

Any output at VOUT [0V £ VOUT £ VCC (MAX)];

DQ is disabled and in High-Z state

-5

µA

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

4

4 MEG x 4

FPM DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) [Vcc (MIN) £ Vcc £ Vcc (MAX)]

3.3V

5V

2K

4K

2K

4K

PARAM ETER/CONDITION

SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES

STANDBYCURRENT:TTL

I

CC

1

ALL

1

mA

µA

(RAS# = CAS# = VIH

)

STANDBYCURRENT:CMOS(non-“S” version only)

(RAS# = CAS# = other inputs = VCC - 0.2V)

ICC

2

500

150

500

150

500

150

500

150

STANDBYCURRENT:CMOS(“S” version only)

(RAS# = CAS# = other inputs = VCC - 0.2V)

ICC2

OPERATINGCURRENT:Random READ/WRITE

Average power supplycurrent

-5

-6

110

100

90

80

140

130

120

110

I

CC

3

mA

23

(RAS#, CAS#, addresscycling:^tRC= ^tRC[MIN])

OPERATINGCURRENT:FASTPAGEMODE

Average power supplycurrent

-5

-6

110

100

90

110

100

90

ICC

4

(RAS# = VIL, CAS#, address cycling: ^tPC = ^tPC [MIN])

REFRESHCURRENT:RAS#-ONLY

-5

-6

110

100

90

80

140

130

120

110

Average power supplycurrent

ICC

5

(RAS# cycling, CAS# = VIH: ^tRC = ^tRC [MIN])

REFRESHCURRENT:CBR

-5

-6

110

100

90

80

140

130

120

110

Average power supplycurrent

I

CC

6

mA

µA

4, 7

(RAS#, CAS#, addresscycling:^tRC= ^tRC[MIN])

REFRESHCURRENT:Extended (“S” version only)

Average power supplycurrent:CAS# = 0.2Vor

CBR cycling; RAS# = ^tRAS (MIN); WE# = VCC - 0.2V;

A0-A11, OE# and D^IN= VCC - 0.2V or 0.2V

(DIN may be left open)

ALL

^tRC

300

I

CC

7

62.5

31.25

62.5

31.25

µs

23

REFRESHCURRENT:Self (“S” version only)

Average power supplycurrent:CBRwith

RAS# ^tRASS(MIN)and CAS# held LOW;

WE# = VCC - 0.2V; A0-A11, OE# and

I

CC

8

ALL

300

µA

4, 7

D

IN = VCC - 0.2V or 0.2V (DIN may be left open)

CAPACITANCE

(Note: 6)

PARAMETER

SYMBOL M AX

UNITS

p F

Input Capacitance: Address pins

Input Capacitance: RAS#, CAS#, WE#, OE#

Input/Output Capacitance: DQ

CI1

CI2

CIO

5

7

p F

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

5

4 MEG x 4

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) £ Vcc £ Vcc (MAX)]

ACCHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

NOTES

t

Access time from column address

Column-addresshold time (referenced to RAS#)

Column-addresssetup time

Row-addresssetup time

AA

25

30

t

AR

38

0

45

0

t

ASC

t

ASR

0

t

Column address to WE# delay time

Access time from CAS#

AWD

42

49

18

t

CAC

13

15

t

Column-addresshold time

CAS# pulse width

CAH

8

10

15

10

0

t

CAS

10,000

t

CAS# LOW to “Don’t Care” during Self Refresh

CAS# hold time (CBR Refresh)

CAS# to output in Low-Z

CAS# precharge time

CHD

15

8

t

CHR

4

t

CLZ

0

22

13

t

CP

8

10

t

Access time from CAS# precharge

CAS# to RAS# precharge time

CAS# hold time

CPA

28

35

t

CRP

5

38

5

45

5

t

CSH

t

CAS# setup time (CBR Refresh)

CAS# to WE# delay time

WRITE command to CAS# lead time

Data-in hold time

CSR

4

t

CWD

28

8

35

10

0

18

t

CWL

t

DH

8

19

22

20

t

Data-in setup time

DS

0

t

Output disable

OD

0

12

0

15

t

Output enable

OE

t

OE# hold time from WE# during

READ-MODIFY-WRITEcycle

OEH

8

10

t

Output buffer turn-off delay

OFF

0

12

50

0

15

60

ns

µs

ns

ms

17, 22

t

OE# setup prior to RAS# during HIDDEN REFRESH cycle

FAST-PAGE-MODE READ or WRITE cycle time

FAST-PAGE-MODEREAD-WRITEcycle time

Access time from RAS#

ORD

t

PC

20

47

25

56

t

PRWC

t

RAC

t

RAS# to column-address delay time

Row-addresshold time

RAD

9

12

10

60

100

104

14

0

15

t

RAH

t

RAS# pulse width

RAS

50

100

84

11

0

10,000

t

RAS# pulse width (FASTPAGEMODE)

RAS# pulse width during Self Refresh

Random READ or WRITE cycle time

RAS# to CAS# delay time

RASP

125,000

t

RASS

t

RC

t

RCD

14

16

t

READcommand hold time (referenced to CAS#)

READcommand setup time

RCH

t

RCS

0

t

Refresh period (2,048 cycles)

REF

32

64

32

64

t

Refresh period (4,096 cycles)

REF

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

6

4 MEG x 4

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) £ Vcc £ Vcc (MAX)]

ACCHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ms

ns

NOTES

t

Refresh period “S” version

RAS# precharge time

REF

128

140

t

RP

30

5

40

5

t

RAS# to CAS# precharge time

RAS# precharge time exiting Self Refresh

READcommand hold time (referenced to RAS#)

RAS# hold time

RPC

ns

t

RPS

90

0

105

0

ns

t

RRH

ns

16

19

t

RSH

13

116

67

13

2

15

140

79

15

2

ns

t

READ-WRITE cycle time

RWC

ns

t

RAS# to WE# delay time

RWD

ns

t

WRITE command to RAS# lead time

Transition time (rise or fall)

WRITEcommand hold time

WRITE command hold time (referenced to RAS#)

WE# command setup time

RWL

ns

t

T

50

ns

t

WCH

8

10

45

0

ns

t

WCR

38

0

ns

t

WCS

ns

18

t

WRITEcommand pulse width

WE# hold time (CBR Refresh)

WE# setup time (CBR Refresh)

WP

5

ns

t

WRH

8

10

ns

4, 23

t

WRP

8

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

7

4 MEG x 4

FPM DRAM

NOTES

1. All voltages referen ced to VSS.

t

trolled exclusively by AA (^tRAC an d CAC n o

2. Th is param eter is sam pled. VCC = +3.3V or 5.0V;

f = 1 MHz.

t

lon ger applied). With or with out th e RAD

(MAX) lim it, AA, RAC, an d CAC m ust always

be m et.

t

3. I^CCis depen den t on output loadin g an d cycle

rates. Specified values are obtain ed with

m in im um cycle tim e an d th e outputs open .

4. En ables on -ch ip refresh an d address coun ters.

5. Th e m in im um specification s are used on ly to

in dicate cycle tim e at wh ich proper operation

over th e full tem perature ran ge is en sured.

6. An in itial pause of 100µs is required after power-

up, followed by eigh t RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is en sured. Th e eigh t RAS# cycle

t

16. Eith er RCH or RRH m ust be satisfied for a READ

cycle.

17. OFF (MAX) defin es th e tim e at wh ich th e

output ach ieves th e open circuit con dition an d

is n ot referen ced to VOH or VOL.

18. WCS, RWD, AWD, an d CWD are n ot

t

restrictive operatin g param eters. WCS applies to

t

EARLY WRITE cycles. RWD, AWD, an d CWD

t

apply to READ-MODIFY-WRITE cycles. If WCS

^tWCS (MIN), th e cycle is an EARLY WRITE

t

wake-ups sh ould be repeated an y tim e th e REF

refresh requirem en t is exceeded.

7. AC ch aracteristics assum e T = 5n s.

cycle an d th e data output will rem ain an open

t

circuit th rough out th e en tire cycle. If RWD ³

t

^tRWD (MIN), AWD ³ ^tAWD (MIN), an d ^tCWD

t

8. VIH (MIN) an d VIL (MAX) are referen ce levels for

m easurin g tim in g of in put sign als. Tran sition

tim es are m easured between V^IHan d VIL (or

between VIL an d VIH).

9. In addition to m eetin g th e tran sition rate

specification , all in put sign als m ust tran sit

between V^IHan d VIL (or between VIL an d VIH) in

a m on oton ic m an n er.

10. If CAS# = V^IH, data output is High -Z.

11. If CAS# = VIL, data output m ay con tain data

from th e last valid READ cycle.

12. Measured with a load equivalen t to two TTL

gates, 100pF an d V^OL= 0.8V an d VOH = 2V.

13. If CAS# is LOW at th e fallin g edge of RAS#, Q

will be m ain tain ed from th e previous cycle. To

in itiate a n ew cycle an d clear th e data-out

³ ^tCWD (MIN), th e cycle is a READ-MODIFY-

WRITE an d th e data output will con tain data

read from th e selected cell. If n eith er of th e

above con dition s is m et, th e state of data-out is

in determ in ate. OE# h eld HIGH an d WE# taken

LOW after CAS# goes LOW result in a LATE

t

WRITE (OE#-con trolled) cycle. WCS, RWD,

^tCWD, an d AWD are n ot applicable in a LATE

t

WRITE cycle.

19. Th ese param eters are referen ced to CAS# leadin g

edge in EARLY WRITE cycles an d WE# leadin g

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied perm an en tly LOW, LATE WRITE,

or READ-MODIFY-WRITE operation s are n ot

perm issible an d sh ould n ot be attem pted.

21. A HIDDEN REFRESH m ay also be perform ed

after a WRITE cycle. In th is case, WE# = LOW

an d OE# = HIGH.

t

buffer, CAS# m ust be pulsed HIGH for CP.

t

14. Th e RCD (MAX) lim it is n o lon ger specified.

^tRCD (MAX) was specified as a referen ce poin t

t

on ly. If RCD was greater th an th e specified

22. Th e 3n s m in im um is a param eter guaran teed by

design .

^tRCD (MAX) lim it, th en access tim e was con -

trolled exclusively by CAC (^tRAC [MIN] n o

t

23. Colum n address ch an ged on ce each cycle.

24. V^IHoversh oot: VIH (MAX) = VCC + 2V for a pulse

width £ 10n s, an d th e pulse width can n ot be

greater th an on e th ird of th e cycle rate. VIL

un dersh oot: VIL (MIN) = -2V for a pulse width £

10n s, an d th e pu lse width can n ot be greater

th an on e th ird of th e cycle rate.

t

lon ger applied). With or with out th e RCD lim it,

^tAA an d CAC m ust always be m et.

t

15. Th e RAD (MAX) lim it is n o lon ger specified.

^tRAD (MAX) was specified as a referen ce poin t

t

on ly. If RAD was greater th an th e specified

^tRAD (MAX) lim it, th en access tim e was con -

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

8

4 MEG x 4

FPM DRAM

READ CYCLE

t

RC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

RRH

t

RCD

CAS

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

t

ASR

CAH

V

IH

IL

ROW

COLUMN

ROW

ADDR

WE#

t

RCS

RCH

V

IH

IL

t

AA

RAC

CAC

CLZ

t

OFF

V

IOH

IOL

DQ

OPEN

VALID DATA

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OFF

0

t

AR

38

0

45

0

ns

RAC

50

60

ns

t

ASC

ns

RAD

9

12

10

60

104

14

0

ns

t

ASR

0

ns

RAH

ns

t

CAC

13

15

ns

RAS

50

84

11

0

10,000

ns

t

CAH

8

10

0

ns

RC

ns

t

CAS

10,000

ns

RCD

ns

t

CLZ

0

ns

RCH

ns

t

CRP

5

ns

RCS

0

ns

t

CSH

38

0

45

0

ns

RP

30

0

40

0

ns

t

OD

12

15

ns

RRH

ns

t

OE

ns

RSH

13

15

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

9

4 MEG x 4

FPM DRAM

EARLY WRITE CYCLE

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CRP

RCD

CAS

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

t

ASR

CAH

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

t

RWL

WCR

WCH

WP

t

WCS

V

IH

IL

WE#

DQ

t

DS

DH

V

IOH

IOL

VALID DATA

V

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

38

0

MAX

MIN

45

0

MAX

UNITS

ns

SYMBOL

MIN

9

MAX

MIN

10

60

104

14

40

15

10

45

0

MAX

UNITS

ns

t

AR

RAH

t

ASC

ns

RAS

50

84

11

30

13

8

10,000

ns

t

ASR

0

ns

RC

ns

t

CAH

8

10

5

ns

RCD

ns

t

CAS

8

10,000

ns

RP

ns

t

CRP

5

ns

RSH

ns

t

CSH

38

8

45

10

0

ns

RWL

ns

t

CWL

ns

WCH

ns

t

DH

8

ns

WCR

38

0

ns

t

DS

0

ns

WCS

ns

t

RAD

9

12

ns

WP

5

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

10

4 MEG x 4

FPM DRAM

READ-WRITECYCLE

(LATEWRITEand READ-MODIFY-WRITEcycles)

t

RWC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CAS

CRP

ASR

RCD

V

IH

IL

t

AR

t

RAD

t

CAH

RAH

ASC

RCS

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

CWL

RWL

WP

t

CWD

t

AWD

V

IH

IL

WE#

t

AA

t

RAC

t

CAC

t

DS

DH

t

CLZ

V

IOH

IOL

VALID D

DQ

OPEN

OUT

IN

t

OE

OD

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OD

0

t

AR

38

0

45

0

ns

OE

12

15

ns

t

ASC

ns

OEH

RAC

RAD

RAH

RAS

RCD

RCS

RP

8

10

ns

t

ASR

0

ns

50

60

ns

t

AWD

42

49

ns

9

12

10

60

14

0

ns

t

CAC

13

15

ns

t

CAH

8

10

0

ns

50

11

0

10,000

ns

t

CAS

10,000

ns

t

CLZ

0

ns

t

CRP

5

ns

30

13

116

67

13

5

40

15

140

79

15

5

ns

t

CSH

38

28

8

45

35

10

0

ns

RSH

RWC

RWD

RWL

WP

ns

t

CWD

ns

t

CWL

ns

t

DH

8

ns

t

DS

0

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

11

4 MEG x 4

FPM DRAM

FAST-PAGE-MODE READ CYCLE

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

RSH

CAS

CSH

PC

t

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

WE#

ROW

COLUMN

t

COLUMN

t

ROW

t

RCS

t

RCS

RRH

t

RCS

RCH

t

RCH

V

IH

IL

t

AA

RAC

CAC

CPA

CAC

CPA

CAC

t

OFF

t

OFF

t

CLZ

V

IOH

IOL

VALID

DATA

VALID

DATA

VALID

DATA

DQ

OPEN

t

OE

OD

OE

OD

OE

OD

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

12

MIN

MAX

UNITS

ns

t

AA

25

30

ns

OE

15

t

AR

38

0

45

0

OFF

0

12

0

ns

t

ASC

PC

20

25

ns

t

ASR

0

RAC

50

60

ns

t

CAC

13

15

RAD

9

12

10

60

14

0

ns

t

CAH

8

0

8

10

0

RAH

ns

t

CAS

10,000

RASP

50

11

0

125,000

ns

t

CLZ

RCD

ns

t

CP

10

RCH

ns

t

CPA

28

12

35

15

RCS

0

ns

t

CRP

5

38

0

5

45

0

RP

30

0

40

0

ns

t

CSH

RRH

ns

t

OD

RSH

13

15

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

12

4 MEG x 4

FPM DRAM

FAST-PAGE-MODE EARLY WRITE CYCLE

t

RP

RASP

V

IH

IL

RAS#

CAS#

t

CSH

PC

RSH

CAS

t

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

t

CAH

ASR

RAH

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

WCH

WP

t

WCS

WCH

WP

WCS

WCH

WP

V

IH

IL

WE#

t

WCR

DH

RWL

t

DS

DH

DS

DH

V

IOH

IOL

DQ

VALID DATA

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

38

0

MAX

MIN

45

0

MAX

UNITS

ns

SYMBOL

MIN

9

MAX

MIN

12

10

60

14

40

15

10

45

0

MAX

UNITS

ns

t

AR

RAD

t

ASC

ns

RAH

9

ns

t

ASR

0

ns

RASP

50

11

30

13

8

125,000

ns

t

CAH

8

10

5

ns

RCD

ns

t

CAS

8

10,000

ns

RP

ns

t

CP

8

ns

RSH

ns

t

CRP

5

ns

RWL

ns

t

CSH

38

8

45

10

0

ns

WCH

ns

t

CWL

ns

WCR

38

0

ns

t

DH

8

ns

WCS

ns

t

DS

0

ns

WP

5

ns

t

PC

20

25

ns

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

13

4 MEG x 4

FPM DRAM

FAST-PAGE-MODEREAD-WRITECYCLE

(LATEWRITEand READ-MODIFY-WRITEcycles)

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

CSH

NOTE 1

CP

PC

t

PRWC

RSH

CAS

t

CRP

RCD

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

t

RWL

t

RCS

t

CWL

t

WP

t

AWD

CWD

t

CWD

V

IH

IL

WE#

t

AA

t

RAC

t

DH

t

CPA

t

DS

t

CAC

CLZ

CAC

CLZ

CAC

CLZ

V

IOH

IOL

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

DQ

OPEN

D

t

OD

t

OE

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

ns

OD

0

t

AR

38

0

45

0

OE

12

15

ns

t

ASC

OEH

8

10

25

56

ns

t

ASR

0

PC

20

47

ns

t

AWD

42

49

PRWC

ns

t

CAC

13

15

RAC

50

60

ns

t

CAH

8

0

8

10

0

RAD

9

12

10

60

14

0

ns

t

CAS

10,000

35

RAH

ns

t

CLZ

RASP

50

11

0

125,000

ns

t

CP

10

RCD

ns

t

CPA

28

RCS

ns

t

CRP

5

38

28

8

5

RP

30

13

67

13

5

40

15

79

15

5

ns

t

CSH

45

35

10

0

RSH

ns

t

CWD

RWD

ns

t

CWL

RWL

ns

t

DH

8

WP

ns

t

DS

0

t

NOTE: 1. PC is for LATE WRITE only.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

14

4 MEG x 4

FPM DRAM

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

RSH

t

CSH

AR

PC

t

CP

CRP

RCD

CAS

CP

CAS

V

IH

IL

t

RAD

RAH

t

CAH

t

CAH

ASC

ASR

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

ROW

CWL

t

RCS

RWL

t

WP

t

WCS

WCH

V

IH

IL

WE#

DQ

t

CAC

NOTE 1

t

DH

CLZ

OFF

DS

V

VALID

DATA

OH

OL

VALID DATA

OPEN

V

t

AA

t

RAC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

0

MAX

MIN

0

MAX

UNITS

ns

t

AA

25

30

OFF

PC

12

15

t

AR

38

0

45

0

ns

20

25

ns

t

ASC

ns

RAC

RAD

RAH

50

60

ns

t

ASR

0

ns

9

12

10

60

14

0

ns

t

CAC

13

15

ns

t

CAH

8

10

0

ns

RASP

RCD

RCS

RP

50

11

0

125,000

ns

t

CAS

10,000

ns

t

CLZ

0

ns

t

CP

8

10

5

ns

30

13

8

40

15

10

0

ns

t

CRP

5

ns

RSH

RWL

WCH

WCS

WP

ns

t

CSH

38

8

45

10

0

ns

t

CWL

ns

t

DH

8

ns

0

ns

t

DS

0

ns

5

ns

NOTE: 1. Do not drive data prior to tristate.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

15

4 MEG x 4

FPM DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CRP

RPC

V

IH

IL

t

RAH

ASR

V

IH

IL

ADDR

DQ

ROW

V

OH

OL

OPEN

V

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RAS

RP

RAS

NOTE 1

RP

V

IH

IL

RAS#

t

RPC

CP

t

RPC

t

CHR

CSR

CHR

CSR

V

IH

IL

CAS#

DQ

V

OH

OL

OPEN

V

t

WRH

WRP

WRH

WRP

V

IH

IL

WE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

0

MAX

UNITS

SYMBOL

MIN

50

84

30

5

MAX

MIN

60

MAX

UNITS

ns

t

ASR

0

8

5

9

ns

RAS

10,000

t

CHR

10

5

RC

104

40

ns

t

CP

RP

ns

t

CRP

RPC

5

ns

t

CSR

5

WRH

8

10

ns

t

RAH

10

WRP

8

10

ns

NOTE: 1. End of CBR REFRESH cycle.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

16

4 MEG x 4

FPM DRAM

1

HIDDEN REFRESH CYCLE

(WE# = HIGH; OE# = LOW)

t

RAS

RP

V

IH

IL

RAS#

t

CRP

RCD

RSH

CHR

V

IH

IL

CASL#/CASH#

t

AR

RAD

t

CAH

ASR

RAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

AA

t

RAC

CAC

CLZ

t

OFF

V

IOH

IOL

DQx

OE#

OPEN

VALID DATA

OPEN

t

OE

t

OD

t

ORD

V

IH

V

IL

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

12

MIN

MAX

15

UNITS

ns

t

AA

25

30

OE

t

AR

38

0

45

0

ns

OFF

0

12

0

15

ns

t

ASC

ns

ORD

ns

t

ASR

0

ns

RAC

50

60

ns

t

CAC

13

15

ns

RAD

9

12

10

60

14

40

15

ns

t

CAH

8

0

5

0

10

0

ns

RAH

9

ns

t

CHR

ns

RAS

50

11

30

13

10,000

ns

t

CLZ

ns

RCD

ns

t

CRP

5

ns

RP

ns

t

OD

12

0

15

ns

RSH

ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

17

4 MEG x 4

FPM DRAM

SELF REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RAS

RP

RAS

RP

V

IH

IL

RAS#

t

RPC

t

CHR

RPC

CP

CSR

CHR

CSR

V

IH

IL

CAS#

Q

OPEN

t

WRH

WRP

WRH

WRP

V

IH

IL

WE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

15

MAX

MIN

15

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

5

MAX

UNITS

ns

t

CHD

RPC

5

90

8

t

CP

8

10

ns

RPS

105

10

ns

t

CSR

5

ns

WRH

ns

t

RASS

100

30

100

40

µs

WRP

8

10

ns

t

RP

ns

t

NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

t

2. Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

18

4 MEG x 4

FPM DRAM

24/26-PIN PLASTIC SOJ (300 m il)

.679 (17.25)

.673 (17.09)

.305 (7.75)

.299 (7.59)

.340 (8.64)

.330 (8.38)

PIN #1 INDEX

.050 (1.27) TYP

.600 (15.24) TYP

.112 (2.84)

.102 (2.59)

.037 (0.94) MAX

DAMBAR PROTRUSION

.032 (0.81)

.026 (0.66)

.105 (2.67)

.090 (2.29)

.142 (3.61)

.132 (3.35)

SEATING PLANE

.020 (0.51)

.015 (0.38)

.275 (6.99)

.260 (6.61)

.040 (1.02)

R

.030 (0.76)

MAX

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per

side.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

19

4 MEG x 4

FPM DRAM

24/26-PIN PLASTIC TSOP (300 m il)

.678 (17.23)

.672 (17.07)

SEE DETAIL A

26

.367 (9.32)

.359 (9.12)

.302 (7.67)

.298 (7.57)

1

13

.007 (0.18)

.005 (0.13)

PIN #1 INDEX

.050 (1.27)

TYP

.020 (0.50)

.012 (0.30)

.010 (0.25) GAGE PLANE

SEATING PLANE

.004 (0.10)

.047 (1.20)

MAX

.008 (0.20)

.002 (0.05)

.024 (0.60)

.016 (0.40)

DETAIL A

.0315 (0.80)

TYP

MAX

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per

side.

8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900

E-m a il: p ro d m kt g @m icro n .co m , In t e rn e t : h t t p ://w w w .m icro n .co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

4 Meg x 4 FPM DRAM

D49_5V.p65 – Rev. 5/00

Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.

20


型号：	MT4LC4M4B1TG-6S
厂家：	MICRON TECHNOLOGY
描述：	DRAM DRAM 内存集成电路光电二极管动态存储器
文件：	总20页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT4LC4M4B1TG-6S [MICRON]

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