MT8KTF12864HZ [MICRON]
1.35V DDR3L SDRAM SODIMM;
| 型号： | MT8KTF12864HZ |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | 1.35V DDR3L SDRAM SODIMM 动态存储器 双倍数据速率 |
| 文件： | 总18页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Features
1.35V DDR3L SDRAM SODIMM
MT8KTF12864HZ – 1GB
MT8KTF25664HZ – 2GB
MT8KTF51264HZ – 4GB
Figure 1: 204-Pin SODIMM (MO-268 R/C B2, B4)
Features
Module height: 30mm (1.181in)
• DDR3L functionality and operations supported as
defined in the component data sheet
• 204-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-14900, PC3-12800, or
PC3-10600
• 1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512
Meg x 64)
• VDD = 1.35V (1.283–1.45V)
• VDD = 1.5V (1.425–1.575V)
• Backward compatible with standard 1.5V (±0.075V)
DDR3 systems
Options
Marking
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
• Package
None
Z
• VDDSPD = 3.0–3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
– 204-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
• Single rank
-1G9
-1G6
-1G4
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• On-board I2C serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade Nomenclature
Industry
CL =
13
CL =
11
CL =
10
tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 9 CL = 8 CL = 7 CL = 6 CL = 5
-1G9
-1G6
-1G4
-1G1
-1G0
-80B
PC3-14900
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
1866
1600
1333
1333
1333
–
1333
1333
1333
–
1066
1066
1066
1066
1066
–
1066
1066
1066
1066
–
800
800
800
800
800
800
667
667
667
667
667
667
13.125 13.125 47.125
13.125 13.125 48.125
13.125 13.125 49.125
13.125 13.125 50.625
–
–
–
–
–
1600
–
–
–
–
–
–
15
15
15
15
52.5
52.5
–
–
–
PDF: 09005aef84577368
ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Features
Table 2: Addressing
Parameter
1GB
8K
2GB
8K
4GB
8K
Refresh count
Row address
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
32K A[14:0]
8 BA[2:0]
2Gb (256 Meg x 8)
1K A[9:0]
1 S0#
64K A[15:0]
8 BA[2:0]
4Gb (512 Meg x 8)
1K A[9:0]
1 S0#
Device bank address
Device configuration
Column address
Module rank address
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41K128M8,1 1Gb 1.35V DDR3L SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
128 Meg x 64
128 Meg x 64
MT8KTF12864HZ-1G6__
MT8KTF12864HZ-1G4__
1GB
1GB
12.8 GB/s
10.6 GB/s
1.25ns/1600 MT/s
1.5ns/1333 MT/s
11-11-11
9-9-9
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41K256M8,1 2Gb 1.35V DDR3L SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
256 Meg x 64
256 Meg x 64
MT8KTF25664HZ-1G6__
MT8KTF25664HZ-1G4__
2GB
2GB
12.8 GB/s
10.6 GB/s
1.25ns/1600 MT/s
1.5ns/1333 MT/s
11-11-11
9-9-9
Table 5: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41K512M8,1 4Gb 1.35V DDR3L SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
512 Meg x 64
512 Meg x 64
512 Meg x 64
MT8KTF51264HZ-1G9__
MT8KTF51264HZ-1G6__
MT8KTF51264HZ-1G4__
4GB
4GB
4GB
14.9 GB/s
12.8 GB/s
10.6 GB/s
1.07ns/1866 MT/s
1.25ns/1600 MT/s
1.5ns/1333 MT/s
13-13-13
11-11-11
9-9-9
1. The data sheet for the base device can be found on Micron’s web site.
Notes:
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8KSF51264HZ-1G9P1.
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ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
204-Pin DDR3 SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
204-Pin DDR3 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
VREFDQ
VSS
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
DQ19
VSS
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
VDD
A10
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
–
DQ42
DQ43
VSS
2
VSS
DQ4
DQ5
VSS
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
VSS
DQ28
DQ29
VSS
106
108
110
112
114
116
118
120
122
124
126
128
VDD
BA1
RAS#
VDD
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
–
DQ46
DQ47
VSS
3
4
5
DQ0
DQ1
VSS
DQ24
DQ25
VSS
BA0
VDD
6
7
DQ48
DQ49
VSS
8
DQ52
DQ53
VSS
9
WE#
CAS#
VDD
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
DQS0#
DQS0
VSS
DQ3#
DQ3
VSS
S0#
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
DM0
VSS
DM3
VSS
ODT0
VDD
DQS6#
DQS6
VSS
DM6
VSS
DQ2
DQ3
VSS
DQ26
DQ27
VSS
A13
DQ6
DQ7
VSS
DQ30
DQ31
VSS
NC
NC
NC
DQ54
DQ55
VSS
VDD
DQ50
DQ51
VSS
VDD
DQ8
DQ9
VSS
CKE0
VDD
NC
NC
DQ12
DQ13
VSS
NC
VREFCA
VSS
VSS
VDD
DQ60
DQ61
VSS
DQ32
DQ33
VSS
DQ56
DQ57
VSS
NF/A151 130
NF/A142 132
DQ36
DQ37
VSS
DQS1#
DQS1
VSS
BA2
VDD
A12
A9
DM1
RESET#
VSS
VDD
A11
A7
134
136
138
140
142
144
146
148
150
152
154
156
DQS7#
DQS7
VSS
DQS4#
DQS4
VSS
DM7
VSS
DM4
VSS
DQ10
DQ11
VSS
DQ14
DQ15
VSS
VDD
A8
DQ58
DQ59
VSS
VDD
A6
DQ38
DQ39
VSS
DQ62
DQ63
VSS
DQ34
DQ35
VSS
DQ16
DQ17
VSS
A5
DQ20
DQ21
VSS
A4
VDD
A3
SA0
VDD
A2
DQ44
DQ45
VSS
NF
DQ40
DQ41
VSS
VDDSPD
SA1
SDA
SCL
DQS2#
DQS2
VSS
A1
DM2
VSS
A0
VDD
CK0
CK0#
VTT
VDD
CK1
CK1#
DQS5#
DQS5
VSS
VTT
DM5
VSS
–
DQ22
DQ23
–
DQ18
–
–
–
–
1. Pin 78 is NF for 1GB and 2GB; A15 for 4GB.
2. Pin 80 is NF for 1GB; A14 for 2GB and 4GB.
Notes:
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ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments table for density-specific ad-
dressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Input
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
DMx
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Sx#
SAx
SCL
Input
Input
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
I/O
I/O
Check bits: Used for system error detection and correction.
Data input/output: Bidirectional data bus.
DQx
DQSx,
Data strobe: Differential data strobes. Output with read data; edge-aligned with
DQSx#
read data; input with write data; center-aligned with write data.
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ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
Description
SDA
I/O
Serial data: Used to transfer addresses and data into and out of the temperature sen-
sor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
EVENT#
VDD
Output
(open drain)
Parity error output: Parity error found on the command and address bus.
Output
Temperature event: The EVENT# pin is asserted by the temperature sensor when crit-
(open drain) ical temperature thresholds have been exceeded.
Supply
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD
.
VDDSPD
VREFCA
VREFDQ
VSS
Supply
Supply
Supply
Supply
Supply
–
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
Reference voltage: Control, command, and address VDD/2.
Reference voltage: DQ, DM VDD/2.
Ground.
VTT
Termination voltage: Used for control, command, and address VDD/2.
No connect: These pins are not connected on the module.
NC
NF
–
No function: These pins are connected within the module, but provide no functional-
ity.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
DQ Maps
DQ Maps
Table 8: Component-to-Module DQ Map, R/C B2 (PCB 1092)
Component
Reference
Number
Component
Reference
Number
Component
DQ
Module Pin
Number
Component
DQ
Module Pin
Number
Module DQ
Module DQ
U1
U3
U6
U8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2
15
7
U2
U4
U7
U9
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
22
17
18
21
23
16
19
20
50
53
54
49
55
48
51
52
45
42
44
46
40
47
41
43
9
50
41
1
6
16
51
5
6
42
7
18
52
0
5
39
3
17
53
4
4
40
34
36
38
33
35
32
39
37
61
62
57
58
60
59
56
63
29
26
25
31
24
30
28
27
141
130
140
131
143
129
142
132
182
192
183
191
180
193
181
194
58
175
166
174
165
176
163
177
164
148
157
146
158
147
160
149
159
23
67
10
13
11
12
15
8
33
59
24
70
35
57
22
68
36
56
21
69
14
34
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
DQ Maps
Table 9: Component-to-Module DQ Map, R/C B4 (PCB 1348)
Component
Reference
Number
Component
Reference
Number
Component
DQ
Module Pin
Number
Component
DQ
Module Pin
Number
Module DQ
Module DQ
U1
U3
U6
U8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2
13
7
U2
U4
U7
U9
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
22
17
18
21
23
16
19
20
50
53
54
49
55
48
51
52
45
42
44
46
40
47
41
43
9
48
39
1
6
16
49
5
6
42
7
18
50
0
5
37
3
15
51
4
4
40
34
36
38
33
35
32
39
37
61
62
57
58
60
59
56
63
29
26
25
31
24
30
28
27
145
134
142
135
147
133
144
136
182
192
185
191
180
193
183
194
56
177
168
174
167
176
165
179
166
150
159
148
160
151
162
153
161
21
63
10
13
11
12
15
8
31
57
24
68
33
55
22
66
36
54
19
65
14
34
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ktf8c128_256_512x64hz.pdf - Rev. K 7/15 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2011 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
U5
S0#
SPD EEPROM
WP A0 A1 A2
SDA
SCL
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
V
SS
SA0 SA1 V
SS
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
BA[2:0]
A[15/14/13:0]
BA[2:0]: DDR3 SDRAM
A[15/14/13:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
U1
U3
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
V
V
SS
SS
DQS5#
DQS5
DM5
DQS1#
DQS1
DM1
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CK0
CK0#
DDR3 SDRAM x 8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U9
U7
CK1
CK1#
V
SS
V
SS
DQS6#
DQS6
DM6
DQS2#
DQS2
DM2
Clock, control, command, and address line terminations:
DDR3
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SDRAM
CKE0, A[15/14/13:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
V
TT
U2
U4
DDR3
SDRAM
CK
CK#
V
DD
V
V
SS
SS
DQS7#
DQS7
DM7
DQS3#
DQS3
DM3
VDDSPD
VDD
SPD EEPROM
DDR3 SDRAM
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
Control, command,
and address termination
VTT
VREFCA
VREFDQ
U8
U6
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
V
SS
V
V
SS
SS
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
Note:
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-
tially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-
ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR3.
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules." These bytes identify module-specific timing parameters, configuration infor-
mation, and physical attributes. The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic)
and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL
(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, per-
manently disabling hardware write protection. For further information refer to Micron
technical note TN-04-42, "Memory Module Serial Presence-Detect."
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 10: Absolute Maximum Ratings
Symbol
VDD
Parameter
Min
–0.4
–0.4
Max
1.975
1.975
Units
VDD supply voltage relative to VSS
Voltage on any pin relative to VSS
V
V
VIN, VOUT
Table 11: Operating Conditions
Symbol Parameter
Min
1.283
Nom
1.35
Max
Units Notes
VDD
VDD supply voltage
1.45
1.575
V
1.425
1.5
V
V
1
VREFCA(DC) Input reference voltage command/address bus
VREFDQ(DC) I/O reference voltage DQ bus
0.49 × VDD
0.49 × VDD
–600
0.5 × VDD
0.5 × VDD
–
0.51 × VDD
0.51 × VDD
600
V
IVTT
VTT
Termination reference current from VTT
mA
V
Termination reference voltage (DC) – command/
address bus
0.49 × VDD
20mV
-
0.5 × VDD 0.51 × VDD
20mV
+
2
II
Input leakage current; Any input Address inputs,
0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN RAS#, CAS#,
≤ 0.95V (All other pins not under WE#, S#, CKE,
–16
0
16
µA
test = 0V)
ODT, BA, CK,
CK#
DM
–2
–5
0
0
2
5
IOZ
Output leakage current; 0V ≤
VOUT ≤ VDD; DQ and ODT are disa-
bled; ODT is HIGH
DQ, DQS, DQS#
µA
µA
IVREF
VREF supply leakage current; VREFDQ = VDD/2 or
VREFCA = VDD/2 (All other pins not under test = 0V)
–8
0
8
TA
TC
Module ambient operating temperature
0
0
–
–
70
95
°C
°C
3, 4
DDR3 SDRAM component case operating tempera-
ture
3, 4, 5
1. Module is backward-compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
Notes:
2. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. TA and TC are simultaneous requirements.
4. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s web site.
5. The refresh rate is required to double when 85°C < TC ≤ 95°C.
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 12: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G1
-1G9
-1G6
-1G4
-1G1
-1G0
-80C
-80B
-093
-107
-125
-15E
-187E
-187
-25E
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
IDD Specifications
IDD Specifications
Table 13: DDR3 IDD Specifications and Conditions – 1GB (Die Revision J)
Values are for the MT41K128M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 1Gb
(128Meg x 8) component data sheet
Parameter
Symbol
IDD0
1600
272
360
96
1333
264
344
96
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Precharge power-down current: Slow exit
Precharge power-down current: Fast exit
Precharge quiet standby current
Precharge standby current
IDD1
IDD2P0
IDD2P1
IDD2Q
IDD2N
IDD2NT
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
96
96
120
136
200
112
192
664
704
1280
96
120
136
192
112
184
576
616
1240
96
Precharge standby ODT current
Active power-down current
Active standby current
Burst read operating current
Burst write operating current
Refresh current
Self refresh temperature current: MAX TC = 85°C
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
Reset current
IDD6
IDD6ET
IDD7
112
1192
112
112
1152
112
IDD8
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
IDD Specifications
Table 14: DDR3 IDD Specifications and Conditions – 2GB (Die Revision K)
Values are for the MT41K256M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 2Gb
(256 Meg x 8) component data sheet
Parameter
Symbol
IDD0
1600
312
416
96
1333
304
400
96
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Precharge power-down current: Slow exit
Precharge power-down current: Fast exit
Precharge quiet standby current
Precharge standby current
IDD1
IDD2P0
IDD2P1
IDD2Q
IDD2N
IDD2NT
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
112
160
168
248
168
256
752
776
1440
96
112
160
168
232
168
240
656
680
1432
96
Precharge standby ODT current
Active power-down current
Active standby current
Burst read operating current
Burst write operating current
Refresh current
Self refresh temperature current: MAX TC = 85°C
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
Reset current
IDD6
IDD6ET
IDD7
120
1248
112
120
1200
112
IDD8
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
IDD Specifications
Table 15: DDR3 IDD Specifications and Conditions – 4GB (Die Revision E)
Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb
(512 Meg x 8) component data sheet
Parameter
Symbol
IDD0
1866
496
1600
440
1333
376
469
144
224
224
232
280
280
280
1120
880
1824
160
200
1520
160
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Precharge power-down current: Slow exit
Precharge power-down current: Fast exit
Precharge quiet standby current
Precharge standby current
IDD1
560
528
IDD2P0
IDD2P1
IDD2Q
IDD2N
IDD2NT
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
144
144
296
256
280
256
280
256
Precharge standby ODT current
336
312
Active power-down current
328
304
Active standby current
328
304
Burst read operating current
1392
1128
1936
160
1256
1000
1880
160
Burst write operating current
Refresh current
Self refresh temperature current: MAX TC = 85°C
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
Reset current
IDD6
IDD6ET
IDD7
200
200
2008
160
1760
160
IDD8
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
IDD Specifications
Table 16: DDR3 IDD Specifications and Conditions – 4GB (Die Revision N)
Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb
(512 Meg x 8) component data sheet
Parameter
Symbol
IDD0
1866
392
512
64
1600
376
488
64
1333
360
464
64
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Precharge power-down current: Slow exit
Precharge power-down current: Fast exit
Precharge quiet standby current
Precharge standby current
IDD1
IDD2P0
IDD2P1
IDD2Q
IDD2N
IDD2NT
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
128
208
208
240
224
256
840
840
1440
96
112
192
192
224
208
240
760
760
1400
96
96
176
176
208
192
224
680
680
1360
96
Precharge standby ODT current
Active power-down current
Active standby current
Burst read operating current
Burst write operating current
Refresh current
Self refresh temperature current: MAX TC = 85°C
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
Reset current
IDD6
IDD6ET
IDD7
128
1120
80
128
1040
80
128
960
80
IDD8
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
IDD Specifications
Table 17: DDR3 IDD Specifications and Conditions – 4GB (Die Revision P)
Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb
(512 Meg x 8) component data sheet
Parameter
Symbol
IDD0
1866
232
352
88
1600
224
344
80
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Precharge power-down current: Slow exit
Precharge power-down current: Fast exit
Precharge quiet standby current
Precharge standby current
IDD1
IDD2P0
IDD2P1
IDD2Q
IDD2N
IDD2NT
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
88
88
120
136
176
120
168
816
904
1216
120
184
1168
104
120
128
160
120
160
720
808
1216
120
184
1040
104
Precharge standby ODT current
Active power-down current
Active standby current
Burst read operating current
Burst write operating current
Refresh current
Self refresh temperature current: MAX TC = 85°C
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
Reset current
IDD6
IDD6ET
IDD7
IDD8
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Serial Presence-Detect EEPROM
Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: micron.com/spd.
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VDDSPD
Parameter/Condition
Symbol
VDDSPD
VIL
Min
Max
3.6
Units
V
Supply voltage
3.0
–0.45
VDDSPD x 0.7
–
Input low voltage: Logic 0; All inputs
Input high voltage: Logic 1; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
VDDSPD x 0.3
VDDSPD + 1.0
0.4
V
VIH
V
VOL
V
ILI
0.1
2.0
µA
µA
ILO
0.05
2.0
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
Clock frequency
Symbol
tSCL
tHIGH
tLOW
Min
10
Max
400
–
Units
kHz
µs
Notes
Clock pulse width HIGH time
Clock pulse width LOW time
SDA rise time
0.6
1.3
–
–
µs
tR
tF
300
300
–
µs
1
1
SDA fall time
20
ns
Data-in setup time
tSU:DAT
tHD:DI
tHD:DAT
tAA:DAT
tSU:STA
tHD:STA
tSU:STO
tBUF
100
0
ns
Data-in hold time
–
µs
Data-out hold time
200
0.2
0.6
0.6
0.6
1.3
900
0.9
–
ns
Data out access time from SCL LOW
Start condition setup time
Start condition hold time
Stop condition setup time
µs
2
3
µs
–
µs
–
µs
Time the bus must be free before a new transition can
start
–
µs
WRITE time
tW
–
10
ms
1. Guaranteed by design and characterization, not necessarily tested.
Notes:
2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-
ing edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
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1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM
Module Dimensions
Module Dimensions
Figure 3: 204-Pin DDR3 SODIMM
Front view
3.8 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
2.0 (0.079) R
(2X)
U1
U2
U3
U4
30.15 (1.187)
29.85 (1.175)
1.8 (0.071)
(2X)
U5
20.0 (0.787)
TYP
6.0 (0.236)
TYP
1.10 (0.043)
0.90 (0.035)
1.0 (0.039)
TYP
0.45 (0.018)
TYP
0.6 (0.024)
TYP
2.0 (0.079)
TYP
Pin 1
Pin 203
63.6 (2.504)
TYP
45° 4X
Back view
U6
U7
U8
U9
4.0 (0.157)
TYP
2.55 (0.10)
TYP
3.0 (0.12)
Pin 204
Pin 2
TYP
39.0 (1.535)
TYP
21.0 (0.827)
TYP
24.8 (0.976)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
Notes:
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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