N25Q256A_技术文档

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB Sector Erase

N25Q256A

• Write protection

– Software write protection applicable to every

64KB sector via volatile lock bit

– Hardware write protection: protected area size

defined by five nonvolatile bits (BP0, BP1, BP2,

BP3, and TB)

– Additional smart protections, available upon re-

quest

Features

• SPI-compatible serial bus interface

• Double transfer rate (DTR) mode

• 2.7–3.6V single supply voltage

• 108 MHz (MAX) clock frequency supported for all

protocols in single transfer rate (STR) mode

• 54 MHz (MAX) clock frequency supported for all

protocols in DTR mode

• Dual/quad I/O instruction provides increased

throughput up to 54 MB/s

• Supported protocols

– Extended SPI, dual I/O, and quad I/O

– DTR mode supported on all

• Execute-in-place (XIP) mode for all three protocols

– Configurable via volatile or nonvolatile registers

– Enables memory to work in XIP mode directly af-

ter power-on

• Electronic signature

– JEDEC-standard 2-byte signature (BA19h)

– Unique ID of 17 read-only bytes including: addi-

tional extended device ID (EDID) to identify de-

vice factory options; customized factory data

• Minimum 100,000 ERASE cycles per sector

• More than 20 years data retention

• Packages JEDEC standard, all RoHS compliant

– V-PDFN-8/8mm x 6mm (also known as SON,

DFPN, MLP, MLF)

• PROGRAM/ERASE SUSPEND operations

• Continuous read of entire memory via a single com-

mand

– Fast read

– Quad or dual output fast read

– Quad or dual I/O fast read

– SOP2-16/300mils (also known as SO16W, SO16-

Wide, SOIC-16)

– T-PBGA-24b05/6mm x 8mm (also known as

TBGA24)

• Flexible to fit application

– Configurable number of dummy cycles

– Output buffer configurable

• Software reset

• 3-byte and 4-byte addressability mode supported

• 64-byte, user-lockable, one-time programmable

(OTP) dedicated area

• An additional reset pin is available on the following

devices

– N25Q256A83ESF40x, N25Q256A83E1240x

• Erase capability

– Subsector erase 4KB uniform granularity blocks

– Sector erase 64KB uniform granularity blocks

– Full-chip erase

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Products and specifications discussed herein are subject to change by Micron without notice.

3V, 256Mb: Multiple I/O Serial Flash Memory

Features

Contents

Device Description ........................................................................................................................................... 6

Features ....................................................................................................................................................... 6

3-Byte Address and 4-Byte Address Modes ..................................................................................................... 6

Operating Protocols ...................................................................................................................................... 6

XIP Mode ..................................................................................................................................................... 6

Device Configurability .................................................................................................................................. 7

Signal Assignments ........................................................................................................................................... 8

Signal Descriptions ......................................................................................................................................... 10

Memory Organization .................................................................................................................................... 12

Memory Configuration and Block Diagram .................................................................................................. 12

Memory Map – 256Mb Density ....................................................................................................................... 13

Device Protection ........................................................................................................................................... 14

Serial Peripheral Interface Modes .................................................................................................................... 17

SPI Protocols .................................................................................................................................................. 19

Nonvolatile and Volatile Registers ................................................................................................................... 20

Status Register ............................................................................................................................................ 21

Nonvolatile and Volatile Configuration Registers .......................................................................................... 22

Extended Address Register .......................................................................................................................... 25

Enhanced Volatile Configuration Register .................................................................................................... 26

Flag Status Register ..................................................................................................................................... 26

Command Definitions .................................................................................................................................... 28

READ REGISTER and WRITE REGISTER Operations ........................................................................................ 32

READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 32

READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 32

READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 33

READ EXTENDED ADDRESS REGISTER Command ..................................................................................... 33

WRITE STATUS REGISTER Command ......................................................................................................... 33

WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 34

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 34

WRITE EXTENDED ADDRESS REGISTER Command ................................................................................... 35

READ LOCK REGISTER Command .............................................................................................................. 35

WRITE LOCK REGISTER Command ............................................................................................................ 36

CLEAR FLAG STATUS REGISTER Command ................................................................................................ 37

READ IDENTIFICATION Operations ............................................................................................................... 38

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 38

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 39

READ MEMORY Operations ............................................................................................................................ 43

3-Byte Address ........................................................................................................................................... 43

4-Byte Address ........................................................................................................................................... 45

READ MEMORY Operations Timing – Single Transfer Rate ........................................................................... 46

READ MEMORY Operations Timing – Double Transfer Rate ......................................................................... 49

PROGRAM Operations .................................................................................................................................... 52

WRITE Operations .......................................................................................................................................... 57

WRITE ENABLE Command ......................................................................................................................... 57

WRITE DISABLE Command ........................................................................................................................ 57

ERASE Operations .......................................................................................................................................... 59

SUBSECTOR ERASE Command ................................................................................................................... 59

SECTOR ERASE Command ......................................................................................................................... 59

BULK ERASE Command ............................................................................................................................. 60

PROGRAM/ERASE SUSPEND Command ..................................................................................................... 61

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3V, 256Mb: Multiple I/O Serial Flash Memory

Features

PROGRAM/ERASE RESUME Command ...................................................................................................... 63

RESET Operations .......................................................................................................................................... 64

RESET ENABLE and RESET MEMORY Command ........................................................................................ 64

ONE TIME PROGRAMMABLE Operations ....................................................................................................... 65

READ OTP ARRAY Command ...................................................................................................................... 65

PROGRAM OTP ARRAY Command .............................................................................................................. 65

ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ................................................................. 68

ENTER or EXIT 4-BYTE ADDRESS MODE Command ................................................................................... 68

ENTER or EXIT QUAD Command ................................................................................................................ 68

XIP Mode ....................................................................................................................................................... 69

Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 69

Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 69

Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 70

Terminating XIP After a Controller and Memory Reset ................................................................................. 71

Power Up and Power Down ............................................................................................................................. 72

Power Up and Power Down Requirements ................................................................................................... 72

Power Loss Recovery Sequence ................................................................................................................... 73

AC Reset Specifications ................................................................................................................................... 74

Absolute Ratings and Operating Conditions ..................................................................................................... 79

DC Characteristics and Operating Conditions .................................................................................................. 81

AC Characteristics and Operating Conditions .................................................................................................. 82

Package Dimensions ....................................................................................................................................... 84

Part Number Ordering Information ................................................................................................................. 87

Revision History ............................................................................................................................................. 89

Rev. P – 01/2013 .......................................................................................................................................... 89

Rev. O – 12/2012 ......................................................................................................................................... 89

Rev. N – 11/2012 ......................................................................................................................................... 89

Rev. M – 09/12 ............................................................................................................................................ 89

Rev. L – 08/12 ............................................................................................................................................. 89

Rev. K – 07/12 ............................................................................................................................................. 89

Rev. J – 06/12 .............................................................................................................................................. 89

Rev. I – 01/12 .............................................................................................................................................. 89

Rev. H, Preliminary – 11/11 ......................................................................................................................... 89

Rev. G, Preliminary – 07/11 ......................................................................................................................... 90

Rev. F, Preliminary – 07/11 ........................................................................................................................... 90

Rev. E, Preliminary – 05/11 .......................................................................................................................... 90

Rev. D, Preliminary – 05/11 ......................................................................................................................... 90

Rev. C – 11/10 ............................................................................................................................................. 90

Rev. B – 08/10 ............................................................................................................................................. 90

Rev. A – 06/10 ............................................................................................................................................. 90

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3V, 256Mb: Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 7

Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) .................................................................................................. 8

Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) ............................................................................... 8

Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9

Figure 5: Block Diagram ................................................................................................................................ 12

Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18

Figure 7: SPI Modes ....................................................................................................................................... 18

Figure 8: Internal Configuration Register ........................................................................................................ 20

Figure 9: Upper and Lower 128Mb Memory Array Segments ........................................................................... 25

Figure 10: READ REGISTER Command .......................................................................................................... 32

Figure 11: WRITE REGISTER Command ......................................................................................................... 34

Figure 12: READ LOCK REGISTER Command ................................................................................................. 36

Figure 13: WRITE LOCK REGISTER Command ............................................................................................... 37

Figure 14: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39

Figure 15: READ Command ........................................................................................................................... 46

Figure 16: FAST READ Command ................................................................................................................... 46

Figure 17: DUAL OUTPUT FAST READ Command – STR ................................................................................. 47

Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR ..................................................................... 47

Figure 19: QUAD OUTPUT FAST READ Command – STR ................................................................................ 48

Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR .................................................................... 48

Figure 21: FAST READ Command – DTR ......................................................................................................... 49

Figure 22: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 50

Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 50

Figure 24: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 51

Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 51

Figure 26: PAGE PROGRAM Command .......................................................................................................... 53

Figure 27: DUAL INPUT FAST PROGRAM Command ...................................................................................... 54

Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 54

Figure 29: QUAD INPUT FAST PROGRAM Command ..................................................................................... 55

Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 56

Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 58

Figure 32: SUBSECTOR and SECTOR ERASE Command .................................................................................. 60

Figure 33: BULK ERASE Command ................................................................................................................ 61

Figure 34: RESET ENABLE and RESET MEMORY Command ........................................................................... 64

Figure 35: READ OTP Command .................................................................................................................... 65

Figure 36: PROGRAM OTP Command ............................................................................................................ 67

Figure 37: XIP Mode Directly After Power-On .................................................................................................. 70

Figure 38: Power-Up Timing .......................................................................................................................... 72

Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 75

Figure 40: Reset Enable ................................................................................................................................. 75

Figure 41: Serial Input Timing ........................................................................................................................ 75

Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 76

Figure 43: Hold Timing .................................................................................................................................. 77

Figure 44: Output Timing .............................................................................................................................. 78

Figure 45: V_PPHTiming .................................................................................................................................. 78

Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 80

Figure 47: V-PDFN-8/8mm x 6mm ................................................................................................................. 84

Figure 48: SOP2-16/300 mils .......................................................................................................................... 85

Figure 49: T-PBGA-24b05/6mm x 8mm .......................................................................................................... 86

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3V, 256Mb: Multiple I/O Serial Flash Memory

Features

List of Tables

Table 1: Signal Descriptions ........................................................................................................................... 10

Table 2: Sectors[511:0] ................................................................................................................................... 13

Table 3: Data Protection using Device Protocols ............................................................................................. 14

Table 4: Memory Sector Protection Truth Table .............................................................................................. 14

Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14

Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 15

Table 7: SPI Modes ........................................................................................................................................ 17

Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 19

Table 9: Status Register Bit Definitions ........................................................................................................... 21

Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 22

Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 23

Table 12: Sequence of Bytes During Wrap ....................................................................................................... 24

Table 13: Supported Clock Frequencies – STR ................................................................................................. 24

Table 14: Supported Clock Frequencies – DTR ................................................................................................ 24

Table 15: Extended Address Register Bit Definitions ........................................................................................ 25

Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 26

Table 17: Flag Status Register Bit Definitions .................................................................................................. 26

Table 18: Command Set ................................................................................................................................. 28

Table 19: Lock Register .................................................................................................................................. 35

Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 38

Table 21: Read ID Data Out ............................................................................................................................ 38

Table 22: Extended Device ID, First Byte ......................................................................................................... 38

Table 23: Serial Flash Discovery Parameter Data Structure .............................................................................. 40

Table 24: Parameter ID .................................................................................................................................. 41

Table 25: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 43

Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. 45

Table 27: Data/Address Lines for PROGRAM Commands ................................................................................ 52

Table 28: Suspend Parameters ....................................................................................................................... 62

Table 29: Operations Allowed/Disallowed During Device States ...................................................................... 63

Table 30: OTP Control Byte (Byte 64) .............................................................................................................. 66

Table 31: XIP Confirmation Bit ....................................................................................................................... 70

Table 32: Effects of Running XIP in Different Protocols .................................................................................... 70

Table 33: Power-Up Timing and V_WIThreshold ............................................................................................... 73

Table 34: AC RESET Conditions ...................................................................................................................... 74

Table 35: Absolute Ratings ............................................................................................................................. 79

Table 36: Operating Conditions ...................................................................................................................... 79

Table 37: Input/Output Capacitance .............................................................................................................. 79

Table 38: AC Timing Input/Output Conditions ............................................................................................... 80

Table 39: DC Current Characteristics and Operating Conditions ...................................................................... 81

Table 40: DC Voltage Characteristics and Operating Conditions ...................................................................... 81

Table 41: AC Characteristics and Operating Conditions ................................................................................... 82

Table 42: Part Number Information ................................................................................................................ 87

Table 43: Package Details ............................................................................................................................... 88

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3V, 256Mb: Multiple I/O Serial Flash Memory

Device Description

The N25Q is the first high-performance multiple input/output serial Flash memory de-

vice manufactured on 65nm NOR technology. It features execute-in-place (XIP) func-

tionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus

interface. The innovative, high-performance, dual and quad input/output instructions

enable double or quadruple the transfer bandwidth for READ and PROGRAM opera-

tions.

Features

The memory is organized as 512 (64KB) main sectors that are further divided into 16

subsectors each (8192 subsectors in total). The memory can be erased one 4KB subsec-

tor at a time, 64KB sectors at a time, or as a whole.

The memory can be write protected by software through volatile and nonvolatile pro-

tection features, depending on the application needs. The protection granularity is of

64KB (sector granularity) for volatile protections

The device has 64 one-time programmable (OTP) bytes that can be read and program-

med with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be

permanently locked with a PROGRAM OTP command.

The device also has the ability to pause and resume PROGRAM and ERASE cycles by us-

ing dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.

3-Byte Address and 4-Byte Address Modes

The device features 3-byte or 4-byte address modes to access memory beyond 128Mb.

When 4-byte address mode is enabled, all commands requiring an address must be en-

tered and exited with a 4-byte address mode command: ENTER 4-BYTE ADDRESS

MODE command and EXIT 4-BYTE ADDRESS MODE command. The 4-byte address

mode can also be enabled through the nonvolatile configuration register. See Registers

for more information.

Operating Protocols

The memory can be operated with three different protocols:

• Extended SPI (standard SPI protocol upgraded with dual and quad operations)

• Dual I/O SPI

• Quad I/O SPI

The standard SPI protocol is extended and enhanced by dual and quad operations. In

addition, the dual SPI and quad SPI protocols improve the data access time and

throughput of a single I/O device by transmitting commands, addresses, and data

across two or four data lines.

Each protocol contains unique commands to perform READ operations in DTR mode.

This enables high data throughput while running at lower clock frequencies.

XIP Mode

XIP mode requires only an address (no instruction) to output data, improving random

access time and eliminating the need to shadow code onto RAM for fast execution.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Device Description

All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods

are available. For applications that must enter XIP mode immediately after powering

up, XIP mode can be set as the default mode through the nonvolatile configuration reg-

ister bits.

Device Configurability

The N25Q family offers additional features that are configured through the nonvolatile

configuration register for default and/or nonvolatile settings. Volatile settings can be

configured through the volatile and volatile-enhanced configuration registers. These

configurable features include the following:

• Number of dummy cycles for the fast READ commands

• Output buffer impedance

• SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI)

• Required XIP mode

• Enabling/disabling HOLD (RESET function)

• Enabling/disabling wrap mode

Figure 1: Logic Diagram

V_CC

DQ0

DQ1

C

S#

RESET²

V

_PP/W#/DQ2

HOLD#/DQ3

V_SS

1. Reset functionality is available in devices with a dedicated part number. See Part Num-

ber Ordering Information for more details.

Notes:

2. RESET is valid only for the N25Q256A83ESF40x and N25Q256A83E1240x devices. On

these devices, the additional RESET pin must be connected to an external pull-up.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Signal Assignments

Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View)

S#

DQ1

1

2

3

4

8

7

6

5

V_CC

HOLD#/DQ3

W#/V_PP/DQ2

V_SS

C

DQ0

1. On the underside of the MLP8 package, there is an exposed central pad that is pulled

Notes:

internally to V_SSand must not be connected to any other voltage or signal line on the

PCB.

2. Reset functionality is available in devices with a dedicated part number. See Part Num-

ber Ordering Information for complete package names and details.

Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View)

HOLD#/DQ3

V_CC

RESET/DNU²

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C

DQ0

DNU

V_SS

DNU

S#

DQ1

W#/V_PP/DQ2

1. Reset functionality is available in devices with a dedicated part number. See Part Num-

ber Ordering Information for complete package names and details.

Notes:

2. Pin 3 is DNU, except for the N25Q256A83ESF40x device, where it is used as RESET.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Signal Assignments

Figure 4: 24-Ball TBGA (Balls Down)

1

2

3

4

5

A

B

NC

C

NC RESET/NC NC

NC

V_SS

V_CC

NC

C

S#

NC W#/V_PP/DQ2 NC

DQ0 HOLD#/DQ3 NC

D

E

DQ1

NC

1. See Part Number Ordering Information for complete package names and details.

2. Ball A4 is NC, except for the N25Q256A83E1240x device, where it is used as RESET.

Notes:

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3V, 256Mb: Multiple I/O Serial Flash Memory

Signal Descriptions

The signal description table below is a comprehensive list of signals for the N25 family

devices. All signals listed may not be supported on this device. See Signal Assignments

for information specific to this device.

Table 1: Signal Descriptions

Symbol

Type

Description

C

Input

Clock: Provides the timing of the serial interface. Commands, addresses, or data present at se-

rial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling

edge of the clock.

S#

Input

Chip select: When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in exten-

ded SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM,

ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode

(not deep power-down mode). Driving S# LOW enables the device, placing it in the active pow-

er mode. After power-up, a falling edge on S# is required prior to the start of any command.

DQ0

Input

and I/O

Serial data: Transfers data serially into the device. It receives command codes, addresses, and

the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for

input/output during the following operations: DUAL OUTPUT FAST READ, QUAD OUTPUT FAST

READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for

output, data is shifted out on the falling edge of the clock.

In DIO-SPI, DQ0 always acts as an input/output.

In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE

cycle performed with V_PP. The device temporarily enters the extended SPI protocol and then re-

turns to QIO-SPI as soon as V_PPgoes LOW.

DQ1

Output

and I/O

Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of

the clock. DQ1 is used for input/output during the following operations: DUAL INPUT FAST

PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD

INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of

the clock.

In DIO-SPI, DQ1 always acts as an input/output.

In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE

cycle performed with the enhanced program supply voltage (V_PP). In this case the device tem-

porarily enters the extended SPI protocol and then returns to QIO-SPI as soon as V_PPgoes LOW.

DQ2

Input

and I/O

DQ2: When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the

signal functions as DQ2, providing input/output.

All data input drivers are always enabled except when used as an output. Micron recommends

customers drive the data signals normally (to avoid unnecessary switching current) and float

the signals before the memory device drives data on them.

DQ3

Input

and I/O

DQ3: When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the

signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if

the device is selected.

RESET#

Control

Input

RESET: This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the

normal operating mode. When RESET# is driven LOW, the memory enters reset mode and out-

put is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation

is in progress, data may be lost.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Signal Descriptions

Table 1: Signal Descriptions (Continued)

Symbol

Type

Description

HOLD#

Control

Input

HOLD: Pauses any serial communications with the device without deselecting the device. DQ1

(output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device

must be selected with S# driven LOW.

HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ,

QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED

FAST PROGRAM.

In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled

when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET#

functionality, it is possible to reset the device unless this functionality is not disabled by means

of dedicated registers bits.

The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR.

On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a

DTR operation is recognized.

W#

Control

Input

Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in

extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the

voltage range applied to the signal. If voltage range is low (0V to V_CC), the signal acts as a

write protection control input. The memory size protected against PROGRAM or ERASE opera-

tions is locked as specified in the status register block protect bits 3:0.

W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD

INPUT/OUTPUT FAST READ operations and in QIO-SPI.

V_PP

Power

Supply voltage: If V_PPis in the voltage range of V_PPH, the signal acts as an additional power

supply, as defined in the AC Measurement Conditions table.

During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the addition-

al V_PPpower supply to speed up internal operations. However, to enable this functionality, it is

necessary to set bit 3 of the VECR to 0.

In this case, V_PPis used as an I/O until the end of the operation. After the last input data is shif-

ted in, the application should apply V_PPvoltage to V_PPwithin 200ms to speed up the internal

operations. If the V_PPvoltage is not applied within 200ms, the PROGRAM/ERASE operations

start at standard speed.

The default value of VECR bit 3 is 1, and the V_PPfunctionality for quad I/O modify operations is

disabled.

V_CC

V_SS

Power

Device core power supply: Source voltage.

Ground: Reference for the V_CCsupply voltage.

Do not use.

Ground

DNU

NC

–

No connect.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Memory Organization

Memory Configuration and Block Diagram

Each page of memory can be individually programmed. Bits are programmed from one

through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable.

Bits are erased from zero through one. The memory is configured as 33,554,432 bytes (8

bits each); 512 sectors (64KB each); 8192 subsectors (4KB each); and 131,072 pages (256

bytes each); and 64 OTP bytes are located outside the main memory array.

Figure 5: Block Diagram

HOLD#

High voltage

Control logic

generator

W#/V

PP

64 OTP bytes

S#

C

DQ0

DQ1

DQ2

DQ3

I/O shift register

Address register

and counter

256 byte

data buffer

Status

register

01FFFFFFh

0000000h

00000FFh

256 bytes (page size)

X decoder

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3V, 256Mb: Multiple I/O Serial Flash Memory

Memory Map – 256Mb Density

Table 2: Sectors[511:0]

Address Range

Sector

Subsector

Start

End

511

8191

01FF F000h

01FF FFFFh

⋮

8176

01FF 0000h

01FF 0FFFh

⋮

255

4095

00FF F000h

00FF FFFFh

⋮

4080

00FF 0000h

00FF 0FFFh

⋮

127

2047

007F F000h

007F FFFFh

⋮

2032

007F 0000h

007F 0FFFh

⋮

63

1023

003F F000h

003F FFFFh

⋮

1008

003F 0000h

003F 0FFFh

⋮

15

⋮

0

0000 F000h

⋮

0000 FFFFh

⋮

0

0000 0000h

0000 0FFFh

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13

3V, 256Mb: Multiple I/O Serial Flash Memory

Device Protection

Table 3: Data Protection using Device Protocols

Note 1 applies to the entire table

Protection by:

Description

Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is out-

side the operating specification.

Command execution check

Ensures that the number of clock pulses is a multiple of one byte before executing a

PROGRAM or ERASE command, or any command that writes to the device registers.

WRITE ENABLE operation

Ensures that commands modifying device data must be preceded by a WRITE ENABLE

command, which sets the write enable latch bit in the status register.

1. Extended, dual, and quad SPI protocol functionality ensures that device data is protec-

ted from excessive noise.

Note:

Table 4: Memory Sector Protection Truth Table

Note 1 applies to the entire table

Sector Lock Register

Sector Lock

Down Bit

Sector Write Lock

Bit

Memory Sector Protection Status

0

1

0

1

0

1

Sector unprotected from PROGRAM and ERASE operations. Protection status re-

versible.

Sector protected from PROGRAM and ERASE operations. Protection status rever-

sible.

Sector unprotected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

Sector protected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

1. Sector lock register bits are written to when the WRITE LOCK REGISTER command is exe-

cuted. The command will not execute unless the sector lock down bit is cleared (see the

WRITE LOCK REGISTER command). The sector lock register is programmed to have all

protection registers activated at power-up.

Note:

Table 5: Protected Area Sizes – Upper Area

Note 1 applies to the entire table

Status Register Content

Memory Content

Top/

Bottom

Bit

BP3

0

BP2

0

BP1

0

BP0

0

Protected Area

Unprotected Area

All sectors

0

None

0

1

Sector 512

Sectors (0 to 511)

Sectors (0 to 510)

Sectors (0 to 508)

Sectors (0 to 504)

0

1

0

Sectors (511 to 512)

Sectors (509 to 512)

Sectors (505 to 512)

0

1

0

1

0

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3V, 256Mb: Multiple I/O Serial Flash Memory

Device Protection

Table 5: Protected Area Sizes – Upper Area (Continued)

Note 1 applies to the entire table

Status Register Content

Memory Content

Top/

Bottom

Bit

BP3

0

BP2

1

BP1

0

BP0

1

Protected Area

Unprotected Area

Sectors (0 to 496)

Sectors (0 to 480)

Sectors (0 to 448)

Sectors (0 to 384)

Sectors (0 to 256)

None

0

Sectors (497 to 512)

Sectors (481 to 512)

Sectors (449 to 512)

Sectors (385 to 512)

Sectors (257 to 512)

All sectors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

All sectors

None

1

0

All sectors

None

1

0

1

All sectors

None

1

0

All sectors

None

1

All sectors

None

1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits.

Note:

Table 6: Protected Area Sizes – Lower Area

Note 1 applies to the entire table

Status Register Content

Memory Content

Top/

Bottom

Bit

1

BP3

0

BP2

0

BP1

0

BP0

0

Protected Area

Unprotected Area

All sectors

None

0

1

Sector 0

Sectors (1 to 511)

Sectors (2 to 511)

Sectors (4 to 511)

Sectors (8 to 511)

Sectors (16 to 511)

Sectors (32 to 511)

Sectors (64 to 511)

Sectors (128 to 511)

Sectors (256 to 511)

None

0

1

0

Sectors (0 to 1)

Sectors (0 to 3)

Sectors (0 to 7)

Sectors (0 to 15)

Sectors (0 to 31)

Sectors (0 to 63)

Sectors (0 to 127)

Sectors (0 to 255)

All sectors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

All sectors

None

1

0

All sectors

None

1

0

1

All sectors

None

1

0

All sectors

None

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3V, 256Mb: Multiple I/O Serial Flash Memory

Device Protection

Table 6: Protected Area Sizes – Lower Area (Continued)

Note 1 applies to the entire table

Status Register Content

Memory Content

Top/

Bottom

Bit

BP3

BP2

BP1

BP0

Protected Area

All sectors

Unprotected Area

1

None

1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits.

Note:

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16

3V, 256Mb: Multiple I/O Serial Flash Memory

Serial Peripheral Interface Modes

The device can be driven by a microcontroller while its serial peripheral interface is in

either of the two modes shown here. The difference between the two modes is the clock

polarity when the bus master is in standby mode and not transferring data. Input data is

latched in on the rising edge of the clock, and output data is available from the falling

edge of the clock.

Table 7: SPI Modes

Note 1 applies to the entire table

SPI Modes

Clock Polarity

CPOL = 0, CPHA = 0

CPOL = 1, CPHA = 1

C remains at 0 for (CPOL = 0, CPHA = 0)

C remains at 1 for (CPOL = 1, CPHA = 1)

1. The listed SPI modes are supported in extended, dual, and quad SPI protocols.

Note:

Shown below is an example of three memory devices in extended SPI protocol in a sim-

ple connection to an MCU on an SPI bus. Because only one device is selected at a time,

that one device drives DQ1, while the other devices are High-Z.

Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus

master might enter a state in which all input/output is High-Z simultaneously, such as

when the bus master is reset. Therefore, the serial clock must be connected to an exter-

nal pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW.

This ensures that S# and the serial clock are not HIGH simultaneously and that ^tSHCH

is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp =

parasitic capacitance of the bus line), is shorter than the time the bus master leaves the

SPI bus in High-Z.

Example: Cp = 50pF, that is R × Cp = 5μs. The application must ensure that the bus mas-

ter never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and HOLD#

should be driven either HIGH or LOW, as appropriate.

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17

3V, 256Mb: Multiple I/O Serial Flash Memory

Serial Peripheral Interface Modes

Figure 6: Bus Master and Memory Devices on the SPI Bus

V_SS

V_CC

R

SDO

SDI

SPI interface:

(CPOL, CPHA) =

(0, 0) or (1, 1)

SCK

C

V_CC

C

V_SS

SPI bus master

DQ1 DQ0

SPI memory

device

SPI memory

device

SPI memory

device

R

CS3

CS2 CS1

S#

W# HOLD#

Figure 7: SPI Modes

CPOL CPHA

0

1

0

1

C

MSB

DQ0

MSB

DQ1

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18

3V, 256Mb: Multiple I/O Serial Flash Memory

SPI Protocols

Table 8: Extended, Dual, and Quad SPI Protocols

Com-

Protocol

Name

mand

Input

Address

Input

Data

Input/Output Description

Multiple DQn Device default protocol from the factory. Additional com-

Extended

Dual

DQ0

Multiple DQn

lines, depending lines, depending mands extend the standard SPI protocol and enable address

on the command on the command or data transmission on multiple DQn lines.

DQ[1:0]

Volatile selectable: When the enhanced volatile configu-

ration register bit 6 is set to 0 and bit 7 is set to 1, the de-

vice enters the dual SPI protocol immediately after the

WRITE ENHANCED VOLATILE CONFIGURATION REGISTER

command. The device returns to the default protocol after

the next power-on. In addition, the device can return to de-

fault protocol using the rescue sequence or through new

WRITE ENHANCED VOLATILE CONFIGURATION REGISTER

command, without power-off or power-on.

Nonvolatile selectable: When nonvolatile configuration

register bit 2 is set, the device enters the dual SPI protocol

after the next power-on. Once this register bit is set, the de-

vice defaults to the dual SPI protocol after all subsequent

power-on sequences until the nonvolatile configuration

register bit is reset to 1.

Quad¹

DQ[3:0]

Volatile selectable: When the enhanced volatile configu-

ration register bit 7 is set to 0, the device enters the quad

SPI protocol immediately after the WRITE ENHANCED VOL-

ATILE CONFIGURATION REGISTER command. The device re-

turns to the default protocol after the next power-on. In ad-

dition, the device can return to default protocol using the

rescue sequence or through new WRITE ENHANCED VOLA-

TILE CONFIGURATION REGISTER command, without power-

off or power-on.

Nonvolatile selectable: When nonvolatile configuration

register bit 3 is set to 0, the device enters the quad SPI pro-

tocol after the next power-on. Once this register bit is set,

the device defaults to the quad SPI protocol after all subse-

quent power-on sequences until the nonvolatile configura-

tion register bit is reset to 1.

1. In quad SPI protocol, all command/address input and data I/O are transmitted on four

lines except during a PROGRAM and ERASE cycle performed with V_PP. In this case, the

device enters the extended SPI protocol to temporarily allow the application to perform

a PROGRAM/ERASE SUSPEND operation or to check the write-in-progress bit in the sta-

tus register or the program/erase controller bit in the flag status register. Then, when

V_PPgoes LOW, the device returns to the quad SPI protocol.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

The device features the following volatile and nonvolatile registers that users can access

to store device parameters and operating configurations:

• Status register

• Nonvolatile and volatile configuration registers

• Extended address register

• Enhanced volatile configuration register

• Flag status register

• Lock register

Note: The lock register is defined in READ LOCK REGISTER Command.

The working condition of memory is set by an internal configuration register that is not

directly accessible to users. As shown below, parameters in the internal configuration

register are loaded from the nonvolatile configuration register during each device boot

phase or power-on reset. In this sense, then, the nonvolatile configuration register con-

tains the default settings of memory.

Also, during the life of an application, each time a WRITE VOLATILE or ENHANCED

VOLATILE CONFIGURATION REGISTER command executes to set configuration pa-

rameters in these respective registers, these new settings are copied to the internal con-

figuration register. Therefore, memory settings can be changed in real time. However, at

the next power-on reset, the memory boots according to the memory settings defined

in the nonvolatile configuration register parameters.

Figure 8: Internal Configuration Register

Volatile configuration register

and volatile enhanced

configuration register

Nonvolatile configuration register

Register download is executed after a

WRITE VOLATILE or ENHANCED

VOLATILE CONFIGURATION REGISTER

command, overwriting configuration

register settings on the internal

configuration register.

Register download is executed only

during the power-on phase or after

a reset, overwriting configuration

register settings on the internal

configuration register.

Internal configuration

register

Device behavior

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3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Status Register

Table 9: Status Register Bit Definitions

Note 1 applies to entire table

Bit

Name

Settings

Description

Notes

7

Status register

0 = Enabled

Nonvolatile bit: Used with the W/V_PPsignal to enable or

3

write enable/disable 1 = Disabled

disable writing to the status register.

5

Top/bottom

0 = Top

1 = Bottom

Nonvolatile bit: Determines whether the protected mem-

ory area defined by the block protect bits starts from the

top or bottom of the memory array.

4

6, 4:2 Block protect 3–0

See Protected Area Nonvolatile bit: Defines memory to be software protec-

Sizes – Upper Area ted against PROGRAM or ERASE operations. When one or

and Lower Area ta- more block protect bits is set to 1, a designated memory

bles in Device Pro-

tection

area is protected from PROGRAM and ERASE operations.

1

0

Write enable latch

Write in progress

0 = Cleared (Default) Volatile bit: The device always powers up with this bit

2

1 = Set

cleared to prevent inadvertent WRITE STATUS REGISTER,

PROGRAM, or ERASE operations. To enable these opera-

tions, the WRITE ENABLE operation must be executed first

to set this bit.

0 = Ready

1 = Busy

Volatile bit: Indicates if one of the following command cy-

cles is in progress:

WRITE STATUS REGISTER

WRITE NONVOLATILE CONFIGURATION REGISTER

PROGRAM

ERASE

1. Bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REG-

ISTER commands, respectively.

Notes:

2. Volatile bits are cleared to 0 by a power cycle or reset.

3. The status register write enable/disable bit, combined with the W#/V_PPsignal as descri-

bed in the Signal Descriptions, provides hardware data protection for the device as fol-

lows: When the enable/disable bit is set to 1, and the W#/V_PPsignal is driven LOW, the

status register nonvolatile bits become read-only and the WRITE STATUS REGISTER oper-

ation will not execute. The only way to exit this hardware-protected mode is to drive

W#/V_PPHIGH.

4. See Protected Area Sizes tables. The BULK ERASE command is executed only if all bits

are 0.

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21

3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Nonvolatile and Volatile Configuration Registers

Table 10: Nonvolatile Configuration Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

Description

Notes

15:12 Number of

0000 (identical to 1111)

Sets the number of dummy clock cycles subse-

quent to all FAST READ commands.

The default setting targets the maximum al-

lowed frequency and guarantees backward com-

patibility.

2, 3

dummy clock 0001

cycles

0010

.

1101

1110

1111

11:9 XIP mode at 000 = XIP: Fast Read

Enables the device to operate in the selected XIP

mode immediately after power-on reset.

power-on re- 001 = XIP: Dual Output Fast Read

set

010 = XIP: Dual I/O Fast Read

011 = XIP: Quad Output Fast Read

100 = XIP: Quad I/O Fast Read

101 = Reserved

110 = Reserved

111 = Disabled (Default)

8:6 Output driver 000 = Reserved

Optimizes impedance at V_CC/2 output voltage.

strength

001 = 90 Ohms

010 = 60 Ohms

011 = 45 Ohms

100 = Reserved

101 = 20 Ohms

110 = 15 Ohms

111 = 30 (Default)

5

4

Reserved

X

"Don't Care."

Reset/hold

0 = Disabled

Enables or disables hold or reset.

1 = Enabled (Default)

(Available on dedicated part numbers.)

3

2

1

0

Quad I/O pro- 0 = Enabled

tocol 1 = Disabled (Default, Extended SPI prot-

cocol)

Dual I/O pro- 0 = Enabled

Enables or disables quad I/O protocol.

4

Enables or disables dual I/O protocol.

tocol

1 = Disabled (Default, Extended SPI pro-

tocol)

128Mb seg-

ment select

0 = Upper 128Mb segment

1 = Lower 128Mb segment (Default)

Selects a 128Mb segment as default for 3B ad-

dress operations. See also the extended address

register.

Address bytes 0 = Enable 4B address

1 = Enable 3B address (Default)

Defines the number of address bytes for a com-

mand.

1. Settings determine device memory configuration after power-on. The device ships from

the factory with all bits erased to 1 (FFFFh). The register is read from or written to by

READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURA-

TION REGISTER commands, respectively.

Notes:

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3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

2. The 0000 and 1111 settings are identical in that they both define the default state,

which is the maximum frequency of ^fc = 108 MHz. This ensures backward compatibility.

3. If the number of dummy clock cycles is insufficient for the operating frequency, the

memory reads wrong data. The number of cycles must be set according to and sufficient

for the clock frequency, which varies by the type of FAST READ command, as shown in

the Supported Clock Frequencies table.

4. If bits 2 and 3 are both set to 0, the device operates in quad I/O. When bits 2 or 3 are

reset to 0, the device operates in quad I/O or dual I/O respectively, after the next power-

on.

Table 11: Volatile Configuration Register Bit Definitions

Note 1 applies to entire table

Bit

Name

Settings

Description

Notes

7:4

Number of dum- 0000 (identical to 1111)

Sets the number of dummy clock cycles subsequent to

all FAST READ commands.

The default setting targets maximum allowed frequen-

cy and guarantees backward compatibility.

2, 3

my clock cycles

0001

0010

.

1101

1110

1111

3

XIP

0

1

Enables or disables XIP. For device part numbers with

feature digit equal to 2 or 4, this bit is always "Don’t

Care," so the device operates in XIP mode without set-

ting this bit.

2

Reserved

Wrap

x = Default

0b = Fixed value.

1:0

00 = 16-byte boundary

aligned

16-byte wrap: Output data wraps within an aligned 16-

byte boundary starting from the 3-byte address issued

after the command code.

4

01 = 32-byte boundary

aligned

32-byte wrap: Output data wraps within an aligned 32-

byte boundary starting from the 3-byte address issued

after the command code.

10 = 64-byte boundary

aligned

64-byte wrap: Output data wraps within an aligned 64-

byte boundary starting from the 3-byte address issued

after the command code.

11 = sequential (default)

Continuous reading (default): All bytes are read se-

quentially.

1. Settings determine the device memory configuration upon a change of those settings by

the WRITE VOLATILE CONFIGURATION REGISTER command. The register is read from or

written to by READ VOLATILE CONFIGURATION REGISTER or WRITE VOLATILE CONFIGU-

RATION REGISTER commands respectively.

Notes:

2. The 0000 and 1111 settings are identical in that they both define the default state,

which is the maximum frequency of ^fc = 108 MHz. This ensures backward compatibility.

3. If the number of dummy clock cycles is insufficient for the operating frequency, the

memory reads wrong data. The number of cycles must be set according to and be suffi-

cient for the clock frequency, which varies by the type of FAST READ command, as

shown in the Supported Clock Frequencies table.

4. See the Sequence of Bytes During Wrap table.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Table 12: Sequence of Bytes During Wrap

Starting Address

16-Byte Wrap

32-Byte Wrap

64-Byte Wrap

0

0-1-2- . . . -15-0-1- . .

0-1-2- . . . -31-0-1- . .

0-1-2- . . . -63-0-1- . .

1-2- . . . -63-0-1-2- . .

15-16-17- . . . -63-0-1- . .

31-32-33- . . . -63-0-1- . .

63-0-1- . . . -63-0-1- . .

1

1-2- . . . -15-0-1-2- . .

1-2- . . . -31-0-1-2- . .

15

31

63

15-0-1-2-3- . . . -15-0-1- . .

31-16-17- . . . -31-16-17- . .

63-48-49- . . . -63-48-49- . .

15-16-17- . . . -31-0-1- . .

31-0-1-2-3- . . . -31-0-1- . .

63-32-33- . . . -63-32-33- . .

Table 13: Supported Clock Frequencies – STR

Note 1 applies to entire table

Number of Dummy

Clock Cycles

DUAL OUTPUT

FAST READ

DUAL I/O FAST

READ

QUAD OUTPUT QUAD I/O FAST

FAST READ

90

FAST READ

READ

1

2

80

50

70

43

60

30

100

90

40

3

108

100

80

75

50

4

108

105

90

60

5

108

100

105

108

100

105

108

70

6

108

80

7

108

86

8

108

95

9

108

105

108

10

108

1. Values are guaranteed by characterization and not 100% tested in production.

Note:

Table 14: Supported Clock Frequencies – DTR

Number of Dummy

Clock Cycles

DUAL OUTPUT

FAST READ

DUAL I/O FAST

READ

QUAD OUTPUT QUAD I/O FAST

FAST READ

READ

1

2

45

50

54

40

45

50

53

54

25

35

40

45

50

53

54

30

38

45

47

50

53

54

15

20

3

25

4

30

5

35

6

40

7

43

8

48

9

53

10

54

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24

3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Extended Address Register

For devices whose A[MAX:MIN] equals A[23:0], the N25 family includes an extended ad-

dress register that provides a fourth address byte A[31:24], enabling access to memory

beyond 128Mb. Extended address register bit 0 is used to select the upper 128Mb seg-

ment or the lower 128Mb segment of the memory array.

Figure 9: Upper and Lower 128Mb Memory Array Segments

Upper 128Mb

Bottom 128Mb

EAR<0> = A<24> = 1

01FFFFFFh

00FFFFFFh

01000000h

00000000h

EAR<0> = A<24> = 0

The PROGRAM and ERASE operations act upon the 128Mb segment selected in the ex-

tended address register.

The BULK ERASE operation erases the entire device.

The READ operation begins reading in the selected 128Mb segment, but is not bound

by it. In a continuous READ, when the last byte of the segment is read, the next byte out-

put is the first byte of the other segment as the operation wraps to 0000000h; Therefore,

a download of the whole array is possible with one READ operation. The value of the

extended address register does not change when a READ operation crosses the selected

128Mb boundary.

Table 15: Extended Address Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

Description

7

6

5

4

3

2

1

0

A[31:25]

0 = Reserved

–

A[24]

0 = Lower 128Mb segment Enables 128Mb segmentation selection.

(default)

The default setting for this bit is determined by the non-

1 = Upper 128Mb segment volatile configuration register bit 1. However, this set-

ting can be changed with the WRITE EXTENDED AD-

DRESS REGISTER command.

1. The extended address register is for an application that supports only 3-byte addressing.

It extends the device's first three address bytes A[23:0] to a fourth address byte A[31:24]

Note:

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25

3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

to enable memory access beyond 128Mb. The extended address register bit 0 enables

128Mb segmentation selection. If 4-byte addressing is enabled, extended address regis-

ter settings are ignored.

Enhanced Volatile Configuration Register

Table 16: Enhanced Volatile Configuration Register Bit Definitions

Note 1 applies to entire table

Bit

Name

Settings

Description

Notes

7

Quad I/O protocol

0 = Enabled

Enables or disables quad I/O protocol.

2

1 = Disabled (Default,

extended SPI protocol)

6

Dual I/O protocol

0 = Enabled

1 = Disabled (Default,

extended SPI protocol)

Enables or disables dual I/O protocol.

0b = Fixed value.

2

5

4

Reserved

x = Default

Reset/hold

0 = Disabled

Enables or disables hold or reset.

1 = Enabled (Default)

(Available on dedicated part numbers.)

3

V_PPaccelerator

0 = Enabled

Enables or disables V_PPacceleration for QUAD

1 = Disabled (Default) INPUT FAST PROGRAM and QUAD INPUT EX-

TENDED FAST PROGRAM OPERATIONS.

2:0

Output driver strength 000 = Reserved

001 = 90 Ohms

Optimizes impedance at V_CC/2 output voltage.

010 = 60 Ohms

011 = 45 Ohms

100 = Reserved

101 = 20 Ohms

110 = 15 Ohms

111 = 30 (Default)

1. Settings determine the device memory configuration upon a change of those settings by

the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The register is

read from or written to in all protocols by READ ENHANCED VOLATILE CONFIGURATION

REGISTER or WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands, respec-

tively.

Notes:

2. If bits 6 and 7 are both set to 0, the device operates in quad I/O. When either bit 6 or 7 is

reset to 0, the device operates in quad I/O or dual I/O respectively following the next

WRITE ENHANCED VOLATILE CONFIGURATION command.

Flag Status Register

Table 17: Flag Status Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

Description

Notes

7

Program or

erase

controller

0 = Busy

1 = Ready

Status bit: Indicates whether a PROGRAM, ERASE,

WRITE STATUS REGISTER, or WRITE NONVOLATILE CON-

FIGURATION command cycle is in progress.

2, 3

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3V, 256Mb: Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Table 17: Flag Status Register Bit Definitions (Continued)

Note 1 applies to entire table

Bit Name Settings

Erase suspend 0 = Not in effect

Description

Notes

6

5

4

3

2

1

Status bit: Indicates whether an ERASE operation has

been or is going to be suspended.

3

1 = In effect

Erase

Program

V_PP

0 = Clear

Error bit: Indicates whether an ERASE operation has

4, 5

3

1 = Failure or protection error succeeded or failed.

0 = Clear

Error bit: An attempt to program a 0 to a 1 when V_PP=

1 = Failure or protection error V_PPHand the data pattern is a multiple of 64 bits.

0 = Enabled

Error bit: Indicates an invalid voltage on V_PPduring a

PROGRAM or ERASE operation.

1 = Disabled (Default)

Program sus-

pend

0 = Not in effect

1 = In effect

Status bit: Indicates whether a PROGRAM operation

has been or is going to be suspended.

Protection

0 = Clear

Error bit: Indicates whether a PROGRAM operation has

4, 5

1 = Failure or protection error attempted to modify the protected array sector or ac-

cess the locked OTP space.

0

Addressing

0 = 3 bytes addressing

1 = 4 bytes addressing

Status bit: Indicates whether 3-byte or 4-byte address

mode is enabled.

3

1. Register bits are read by READ STATUS REGISTER command. All bits are volatile.

Notes:

2. These program/erase controller settings apply only to PROGRAM or ERASE command cy-

cles in progress; they do not apply to a WRITE command cycle in progress.

3. Status bits are reset automatically.

4. Error bits must be reset by CLEAR FLAG STATUS REGISTER command.

5. Typical errors include operation failures and protection errors caused by issuing a com-

mand before the error bit has been reset to 0.

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27

3V, 256Mb: Multiple I/O Serial Flash Memory

Command Definitions

Table 18: Command Set

Note 1 applies to entire table

Dual

I/O

Quad

I/O

Data

Bytes

Command

Code

Extended

Notes

RESET Operations

RESET ENABLE

66h

99h

Yes

0

2

RESET MEMORY

IDENTIFICATION Operations

READ ID

9E/9Fh

AFh

Yes

No

Yes

No

Yes

1 to 20

1 to 3

1 to ∞

2

3

MULTIPLE I/O READ ID

READ SERIAL FLASH

5Ah

Yes

DISCOVERY PARAMETER

READ Operations

READ

03h

0Bh

3Bh

Yes

No

Yes

No

Yes

No

1 to ∞

4

5

FAST READ

DUAL OUTPUT FAST READ

DUAL INPUT/OUTPUT FAST READ

5

0Bh

3Bh

BBh

5, 11

QUAD OUTPUT FAST READ

6Bh

Yes

No

Yes

1 to ∞

5

QUAD INPUT/OUTPUT FAST READ

0Bh

6Bh

EBh

5, 12

FAST READ – DTR

0Dh

3Dh

Yes

No

1 to ∞

6

DUAL OUTPUT FAST READ – DTR

DUAL INPUT/OUTPUT FAST READ – DTR

0Dh

3Dh

BDh

QUAD OUTPUT FAST READ – DTR

6Dh

Yes

No

Yes

1 to ∞

6

7

QUAD INPUT/OUTPUT FAST READ – DTR

0Dh

3Dh

EDh

4-BYTE READ

13h

0Ch

3Ch

BCh

Yes

1 to ∞

8

9

4-BYTE FAST READ

4-BYTE DUAL OUTPUT FAST READ

Yes

No

9

4-BYTE DUAL INPUT/OUTPUT FAST

READ

9, 11

4-BYTE QUAD OUTPUT FAST READ

6Ch

ECh

Yes

No

Yes

1 to ∞

9

4-BYTE QUAD INPUT/OUTPUT FAST

READ

10, 12

WRITE Operations

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3V, 256Mb: Multiple I/O Serial Flash Memory

Command Definitions

Table 18: Command Set (Continued)

Note 1 applies to entire table

Dual

I/O

Quad

I/O

Data

Bytes

Command

Code

06h

Extended

Notes

WRITE ENABLE

Yes

0

2

WRITE DISABLE

04h

REGISTER Operations

READ STATUS REGISTER

WRITE STATUS REGISTER

READ LOCK REGISTER

WRITE LOCK REGISTER

READ FLAG STATUS REGISTER

CLEAR FLAG STATUS REGISTER

05h

01h

E8h

E5h

70h

50h

B5h

Yes

1 to ∞

2

2, 13

4

1

1 to ∞

1

1 to ∞

0

4, 13

2

READ NONVOLATILE

2

CONFIGURATION REGISTER

WRITE NONVOLATILE

CONFIGURATION REGISTER

B1h

85h

81h

65h

61h

2, 13

2

READ VOLATILE

CONFIGURATION REGISTER

Yes

1 to ∞

WRITE VOLATILE

CONFIGURATION REGISTER

1

1 to ∞

1

2, 13

2

READ ENHANCED VOLATILE

CONFIGURATION REGISTER

WRITE ENHANCED VOLATILE

CONFIGURATION REGISTER

2, 13

READ EXTENDED ADDRESS REGISTER

WRITE EXTENDED ADDRESS REGISTER

PROGRAM Operations

C8h

C5h

0

2

2, 16

PAGE PROGRAM

02h

12h

A2h

Yes

No

1 to 256

4, 13

4, 13, 14

4, 13

4-BYTE PAGE PROGRAM

DUAL INPUT FAST PROGRAM

EXTENDED DUAL INPUT

FAST PROGRAM

02h

A2h

D2h

4, 11, 13

QUAD INPUT FAST PROGRAM

32h

34h

Yes

No

Yes

1 to 256

4, 13

4-BYTE QUAD INPUT FAST PROGRAM

4, 13, 14

EXTENDED QUAD INPUT

FAST PROGRAM

02h

32h

4, 12, 13, 15

12h/38h

ERASE Operations

SUBSECTOR ERASE

20h

21h

Yes

29

Yes

0

4, 13

4-BYTE SUBSECTOR ERASE

4, 13, 14

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3V, 256Mb: Multiple I/O Serial Flash Memory

Command Definitions

Table 18: Command Set (Continued)

Note 1 applies to entire table

Dual

I/O

Quad

I/O

Data

Bytes

Command

Code

D8h

DCh

C7h

Extended

Notes

4, 13

SECTOR ERASE

Yes

0

4-BYTE SECTOR ERASE

BULK ERASE

4, 13, 14

4, 13

Yes

0

PROGRAM/ERASE RESUME

PROGRAM/ERASE SUSPEND

7Ah

75h

2, 13

ONE-TIME PROGRAMMABLE (OTP) Operations

READ OTP ARRAY

4Bh

42h

Yes

1 to 64

5

PROGRAM OTP ARRAY

4-BYTE ADDRESS MODE Operations

ENTER 4-BYTE ADDRESS MODE

EXIT 4-BYTE ADDRESS MODE

QUAD Operations

4, 13

B7h

E9h

0

2, 16

ENTER QUAD

35h

F5h

2, 14

EXIT QUAD

1. Yes in the protocol columns indicates that the command is supported and has the same

functionality and command sequence as other commands marked Yes.

Notes:

2. Address bytes = 0. Dummy clock cycles = 0.

3. Address bytes = 3. Dummy clock cycles default = 8.

4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0.

5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy

clock cycles are configurable by the user.

6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy

clock cycles are configurable by the user.

7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-

fault = 8. Dummy clock cycles are configurable by the user.

8. Address bytes = 4. Dummy clock cycles = 0.

9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10

(when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user.

10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable

by the user.

11. When the device is in dual SPI protocol, the command can be entered with any of these

three codes. The different codes enable compatibility between dual SPI and extended

SPI protocols.

12. When the device is in quad SPI protocol, the command can be entered with any of these

three codes. The different codes enable compatibility between quad SPI and extended

SPI protocols.

13. The WRITE ENABLE command must be issued first before this command can be execu-

ted.

14. This command is only for part numbers N25Q256A83ESF40x and N25Q256A83E1240x.

15. The code 38h is valid only for part numbers N25Q256A83ESF40x and

N25Q256A83E1240x; the code 12h is valid for the other part numbers.

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3V, 256Mb: Multiple I/O Serial Flash Memory

Command Definitions

16. The WRITE ENABLE command must be issued first before this command can be execu-

ted. Not necessary for part numbers N25Q256A83ESF40x and N25Q256A83E1240x.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

READ STATUS REGISTER or FLAG STATUS REGISTER Command

To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI

protocol, the command code is input on DQ0, and output on DQ1. For dual SPI proto-

col, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI proto-

col, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is

terminated by driving S# HIGH at any time during data output.

The status register can be read continuously and at any time, including during a PRO-

GRAM, ERASE, or WRITE operation.

The flag status register can be read continuously and at any time, including during an

ERASE or WRITE operation.

If one of these operations is in progress, checking the write in progress bit or P/E con-

troller bit is recommended before executing the command.

Figure 10: READ REGISTER Command

Extended

0

7

8

9

10

11

12

13

14

15

C

LSB

DQ0

DQ1

Command

High-Z

MSB

LSB

D_OUT

MSB

D_OUT

Dual

0

3

4

5

6

7

C

LSB

D_OUT

MSB

DQ[1:0]

Command

MSB

Quad

0

1

2

3

C

LSB

D_OUT

MSB

D_OUT

DQ[3:0]

Command

Don’t Care

MSB

1. Supports all READ REGISTER commands except READ LOCK REGISTER.

Notes:

2. A READ NONVOLATILE CONFIGURATION REGISTER operation will output data starting

from the least significant byte.

READ NONVOLATILE CONFIGURATION REGISTER Command

To execute a READ NONVOLATILE CONFIGURATION REGISTER command, S# is driv-

en LOW. For extended SPI protocol, the command code is input on DQ0, and output on

DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output

on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data

output.

The nonvolatile configuration register can be read continuously. After all 16 bits of the

register have been read, a 0 is output. All reserved fields output a value of 1.

READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command

To execute a READ VOLATILE CONFIGURATION REGISTER command or a READ EN-

HANCED VOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For ex-

tended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual

SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad

SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The op-

eration is terminated by driving S# HIGH at any time during data output.

When the register is read continuously, the same byte is output repeatedly.

READ EXTENDED ADDRESS REGISTER Command

To initiate a READ EXTENDED ADDRESS REGISTER command, S# is driven LOW. For

extended SPI protocol, the command code is input on DQ0, and output on DQ1. For

dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For

quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0].

The operation is terminated by driving S# HIGH at any time during data output.

When the register is read continuously, the same byte is output repeatedly.

WRITE STATUS REGISTER Command

To issue a WRITE STATUS REGISTER command, the WRITE ENABLE command must be

executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the

eighth bit of the last data byte has been latched in, after which it must be driven HIGH.

For extended SPI protocol, the command code is input on DQ0, followed by the data

bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the da-

ta bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the

data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its

duration is ^tW.

This command is used to write new values to status register bits 7:2, enabling software

data protection. The status register can also be combined with the W#/V_PPsignal to

provide hardware data protection. The WRITE STATUS REGISTER command has no ef-

fect on status register bits 1:0.

When the operation is in progress, the write in progress bit is set to 1. The write enable

latch bit is cleared to 0, whether the operation is successful or not. The status register

and flag status register can be polled for the operation status. When the operation com-

pletes, the write in progress bit is cleared to 0, whether the operation is successful or

not. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

Figure 11: WRITE REGISTER Command

Extended

0

7

8

9

10

11

12

13

14

15

C

LSB

D_IN

MSB

D_IN

DQ0

Command

MSB

Dual

0

3

4

5

6

7

C

LSB

D_IN

MSB

D_IN

DQ[1:0]

Command

0

Quad

1

2

3

C

LSB

D_IN

MSB

D_IN

DQ[3:0]

Command

1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER.

Notes:

2. Waveform must be extended for each protocol, to 23 for extended, 11 for dual, and 5

for quad.

3. A WRITE NONVOLATILE CONFIGURATION REGISTER operation requires data being sent

starting from least significant byte.

WRITE NONVOLATILE CONFIGURATION REGISTER Command

To execute the WRITE NONVOLATILE CONFIGURATION REGISTER command, the

WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is

driven LOW and held LOW until the 16th bit of the last data byte has been latched in,

after which it must be driven HIGH. For extended SPI protocol, the command code is

input on DQ0, followed by two data bytes. For dual SPI protocol, the command code is

input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code

is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation,

which is self-timed, is initiated; its duration is ^tNVCR.

When the operation is in progress, the write in progress bit is set to 1. The write enable

latch bit is cleared to 0, whether the operation is successful or not. The status register

and flag status register can be polled for the operation status. When the operation com-

pletes, the write in progress bit is cleared to 0, whether the operation is successful or

not. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1.

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command

To execute a WRITE VOLATILE CONFIGURATION REGISTER command or a WRITE

ENHANCED VOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE

command must be executed to set the write enable latch bit to 1. S# is driven LOW and

held LOW until the eighth bit of the last data byte has been latched in, after which it

must be driven HIGH. For extended SPI protocol, the command code is input on DQ0,

followed by the data bytes. For dual SPI protocol, the command code is input on

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input

on DQ[3:0], followed by the data bytes.

Because register bits are volatile, change to the bits is immediate. If S# is not driven

HIGH, the command is not executed, flag status register error bits are not set, and the

write enable latch remains set to 1. Reserved bits are not affected by this command.

WRITE EXTENDED ADDRESS REGISTER Command

To initiate a WRITE EXTENDED ADDRESS REGISTER command, the WRITE ENABLE

command must be executed to set the write enable latch bit to 1. (Note: The WRITE EN-

ABLE command must NOT be executed on the N25Q256A83ESF40x and

N25Q256A83E1240x devices.) S# is driven LOW and held LOW until the eighth bit of the

last data byte has been latched in, after which it must be driven HIGH. The command

code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command

code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the com-

mand code is input on DQ[3:0], followed by the data bytes.

Because register bits are volatile, change to the bits is immediate. If S# is not driven

HIGH, the command is not executed, the flag status register error bits are not set, and

the write enable latch remains set to 1. Reserved bits are not affected by this command.

READ LOCK REGISTER Command

To execute the READ LOCK REGISTER command, S# is driven LOW. For extended SPI

protocol, the command code is input on DQ0, followed by address bytes that point to a

location in the sector. For dual SPI protocol, the command code is input on DQ[1:0]. For

quad SPI protocol, the command code is input on DQ[3:0]. Each address bit is latched

in during the rising edge of the clock. For extended SPI protocol, data is shifted out on

DQ1 at a maximum frequency ^fC during the falling edge of the clock. For dual SPI proto-

col, data is shifted out on DQ[1:0], and for quad SPI protocol, data is shifted out on

DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data out-

put.

When the register is read continuously, the same byte is output repeatedly. Any READ

LOCK REGISTER command that is executed while an ERASE, PROGRAM, or WRITE cy-

cle is in progress is rejected with no affect on the cycle in progress.

Table 19: Lock Register

Note 1 applies to entire table

Bit

7:2

1

Name

Settings

Description

Reserved

0

Bit values are 0.

Sector lock down

0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,

1 = Set

which means sector lock down and sector write lock bits can be

set.

When this bit set, neither of the lock register bits can be written

to until the next power cycle.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

Table 19: Lock Register (Continued)

Note 1 applies to entire table

Bit

Name

Settings

Description

0

Sector write lock

0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared,

1 = Set

which means that PROGRAM and ERASE operations in this sector

can be executed and sector content modified.

When this bit is set, PROGRAM and ERASE operations in this sec-

tor will not be executed.

1. Sector lock register bits 1:0 are written by the WRITE LOCK REGISTER command. The

command will not execute unless the sector lock down bit is cleared.

Note:

Figure 12: READ LOCK REGISTER Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

DQ[0]

DQ1

Command

High-Z

MSB

A[MAX]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

DQ[1:0]

Command

MSB

A[MAX]

Quad

0

1

2

C_x

C

LSB

A[MIN]

LSB

D_OUT

MSB

D_OUT

DQ[3:0]

Command

Don’t Care

MSB

A[MAX]

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + ((A[MAX] + 1)/2).

For quad SPI protocol, C_x= 1 + ((A[MAX] + 1)/4).

Note:

WRITE LOCK REGISTER Command

To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must

be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until

the eighth bit of the last data byte has been latched in, after which it must be driven

HIGH. The command code is input on DQn, followed by address bytes that point to a

location in the sector, and then one data byte that contains the desired settings for lock

register bits 0 and 1. Each address bit is latched in during the rising edge of the clock.

When execution is complete, the write enable latch bit is cleared within ^tSHSL2 and no

error bits are set. Because lock register bits are volatile, change to the bits is immediate.

WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef-

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ REGISTER and WRITE REGISTER Operations

fect. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1.

Figure 13: WRITE LOCK REGISTER Command

Extended

0

7

8

C

x

C

LSB

A[MIN]

LSB

D

IN

DQ[0]

Command

IN

MSB

A[MAX]

MSB

Dual

0

3

4

C

x

C

LSB

A[MIN]

LSB

D

IN

DQ[1:0]

Command

IN

MSB

A[MAX]

MSB

Quad

0

1

2

C

x

C

LSB

A[MIN]

LSB

D

IN

DQ[3:0]

Command

IN

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + ((A[MAX] + 1)/2).

For quad SPI protocol, C_x= 1 + ((A[MAX] + 1)/4).

Note:

CLEAR FLAG STATUS REGISTER Command

To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits

(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-

mand code is input on DQ0. For dual SPI protocol, the command code is input on

DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation

is terminated by driving S# HIGH at any time.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ IDENTIFICATION Operations

READ ID and MULTIPLE I/O READ ID Commands

To execute the READ ID or MULTIPLE I/O READ ID commands, S# is driven LOW and

the command code is input on DQn. The device outputs the information shown in the

tables below. If an ERASE or PROGRAM cycle is in progress when the command is exe-

cuted, the command is not decoded and the command cycle in progress is not affected.

When S# is driven HIGH, the device goes to standby. The operation is terminated by

driving S# HIGH at any time during data output.

Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands

Unique ID

is Output

Command Name

READ ID

Data In

DQ0

Data Out

DQ0

Extended

Yes

Dual

No

Quad

No

Yes

No

MULTIPLE I/O READ ID

DQ[3:0]

DQ[1:0]

No

Yes

1. Yes in the protocol columns indicates that the command is supported and has the same

functionality and command sequence as other commands marked Yes.

Note:

Table 21: Read ID Data Out

Size

(Bytes) Name

Content Value

Assigned by

1

2

Manufacturer ID

20h (selected by READ

MANUFACTURER ID)

JEDEC

Device ID

Memory Type

BAh

Manufacturer

Factory

Memory Capacity

Unique ID

19h (256Mb)

17

1 Byte: Length of data to follow

10h

2 Bytes: Extended device ID and device

configuration information

ID and information such as uniform

architecture, and HOLD

or RESET functionality

14 Bytes: Customized factory data

Optional

1. The 17 bytes of information in the unique ID is read by the READ ID command, but can-

not be read by the MULTIPLE I/O READ ID command.

Note:

Table 22: Extended Device ID, First Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Reserved 1 = Alternate BP Volatile configuration

HOLD#/RESET#:

0 = HOLD

Addressing:

0 = by byte

Architecture:

00 = Uniform

scheme

0 = Standard BP

scheme

register bit setting:

0 = Required

1 = Not required

1 = RESET

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ IDENTIFICATION Operations

Figure 14: READ ID and MULTIPLE I/O Read ID Commands

Extended

0

7

8

15

16

31

32

C

LSB

DQ0

DQ1

Command

MSB

LSB

D

High-Z

OUT

MSB

Manufacturer

identification

Device

identification

UID

Dual

0

3

4

7

8

15

C

LSB

D

DQ[1:0]

Command

OUT

MSB

Manufacturer

identification

Device

identification

Quad

0

1

2

3

4

7

C

LSB

D

DQ[3:0]

Command

OUT

MSB

Manufacturer

identification

Device

identification

Don’t Care

1. The READ ID command is represented by the extended SPI protocol timing shown first.

The MULTIPLE I/O READ ID command is represented by the dual and quad SPI protocols

are shown below extended SPI protocol.

Note:

READ SERIAL FLASH DISCOVERY PARAMETER Command

To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven

LOW. The command code is input on DQ0, followed by three address bytes and eight

dummy clock cycles (address is always 3 bytes, even for 4-byte address mode). The de-

vice outputs the information starting from the specified address. When the 2048-byte

boundary is reached, the data output wraps to address 0 of the serial Flash discovery

parameter table. The operation is terminated by driving S# HIGH at any time during da-

ta output.

The operation always executes in continuous mode so the read burst wrap setting in the

volatile configuration register does not apply.

Note: Data to be stored in the serial Flash discovery parameter area is still in the defini-

tion phase.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ IDENTIFICATION Operations

Table 23: Serial Flash Discovery Parameter Data Structure

Compliant with JEDEC standard JC-42.4 1775.03

Address

Description

(Byte Mode)

Address (Bit)

7:00

Data

53h

46h

44h

50h

00h

01h

00h

FFh

00h

01h

09h

30h

00h

FFh

Serial Flash discoverable parameters signature

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

15:8

23:16

31:24

7:0

Serial Flash discoverable parameters

Minor revision

Major revision

15:8

Number of parameter headers

Reserved

7:0

15:8

Parameter ID (0) JEDEC-defined parameter table

7:0

Parameter

Minor revision

15:8

Major revision

23:16

31:24

7:0

Parameter length (DW)

Parameter table pointer

15:8

23:16

31:24

7:0

Reserved

Parameter ID (1)

Parameter

Minor revision

Major revision

15:8

23:16

31:24

7:0

Parameter length (DW)

Parameter table pointer

15:8

23:16

31:24

7:0

Reserved

Parameter ID (2)

Parameter

Minor revision

Major revision

15:8

23:16

31:24

7:0

Parameter length (DW)

Parameter table pointer

15:8

23:16

31:24

Reserved

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ IDENTIFICATION Operations

Table 24: Parameter ID

Compliant with JEDEC standard JC-42.4 1775.03

Address

Description

(Byte Mode)

Address (Bit)

Data

Minimum block/sector erase sizes

30h

0

1

10

Write granularity

2

1

0

WRITE ENABLE command required for writing to volatile status reg-

isters

3

4

Reserved

5

1

6

7

1

4KB erase command code

31h

32h

15:8

16

20h

1

Supports DUAL OUTPUT FAST READ operation (single input address,

dual output)

Number of address bytes used (3-byte or 4-byte) for array READ,

WRITE, and ERASE commands

17

18

19

20

1

Supports double transfer rate clocking

1

Supports DUAL INPUT/OUTPUT FAST READ operation (dual input ad-

dress, dual output)

Supports QUAD INPUT/OUTPUT FAST READ operation (quad input

address, quad output)

21

22

1

Supports QUAD OUTPUT FAST READ operation (single input address,

quad output)

Reserved

23

1

Reserved

33h

34h–37h

38h

31:24

31:0

4:00

FFh

Flash size (bits)

0FFFFFFFh

01001b

Number of dummy clock cycles required before valid output from

QUAD INPUT/OUTPUT FAST READ operation

Number of XIP confirmation bits for QUAD INPUT/OUTPUT FAST

READ operation

7:5

001b

Command code for QUAD INPUT/OUTPUT FAST READ operation

39h

3Ah

15:8

EBh

Number of dummy clock cycles required before valid output from

QUAD OUTPUT FAST READ operation

20:16

00111b

Number of XIP confirmation bits for QUAD OUTPUT FAST READ op-

eration

23:21

001b

Command code for QUAD OUTPUT FAST READ operation

3Bh

3Ch

31:24

4:0

6Bh

Number of dummy clock cycles required before valid output from

DUAL OUTPUT FAST READ operation

01000b

Number of XIP confirmation bits for DUAL OUTPUT FAST READ oper-

ation

7:5

000b

3Bh

Command code for DUAL OUTPUT FAST READ operation

3Dh

15:8

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ IDENTIFICATION Operations

Table 24: Parameter ID (Continued)

Compliant with JEDEC standard JC-42.4 1775.03

Address

Description

(Byte Mode)

Address (Bit)

Data

Number of dummy clock cycles required before valid output from

DUAL INPUT/OUTPUT FAST READ operation

3Eh

20:16

00111b

Number of XIP confirmation bits for DUAL INPUT/OUTPUT FAST

READ

23:21

001b

Command code for DUAL INPUT/OUTPUT FAST READ operation

3Fh

40h

31:24

0

BBh

1

Supports FAST READ operation in dual SPI protocol

Reserved

3:1

4

111b

1

Supports FAST READ operation in quad SPI protocol

Reserved

7:5

–

111b

FFFFFFh

FFFFh

00111b

41h–43h

44h–45h

46h

–

Number of dummy clock cycles required before valid output from

FAST READ operation in dual SPI protocol

4:0

Number of XIP confirmation bits for FAST READ operation in dual SPI

protocol

46h

7:5

001b

Command code for FAST READ operation in dual SPI protocol

Reserved

47h

48h–49h

4Ah

7:0

–

BBh

FFFFh

01001b

Number of dummy clock cycles required before valid output from

FAST READ operation in quad SPI protocol

4:0

Number of XIP confirmation bits for FAST READ operation in quad

SPI protocol

7:5

001b

Command code for FAST READ operation in quad SPI protocol

Sector type 1 size (4k)

4Bh

4Ch

4Eh

4Fh

50h

51h

52h

53h

7:0

EBh

0Ch

10h

D8h

00h

Sector type 1 command code (4k)

Sector type 2 size (64KB)

Sector type 2 command code 64KB)

Sector type 3 size (not present)

Sector type 4 size (not present)

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

The device supports default reading and writing to an A[MAX:MIN] of A[23:0] (3-byte

address).

Reading and writing to an A[MAX:MIN] of A[31:0] (4-byte address) is also supported. Se-

lection of the 3-byte or 4-byte address range can be enabled in two ways: setting the

nonvolatile configuration register or entering the ENABLE 4-BYTE ADDRESS MODE or

EXIT 4-BYTE ADDRESS MODE commands. Further details for these settings and com-

mands are in the respective register and command sections of the data sheet.

Note: When the device is set to the default address range of A[23:0], another method for

enabling 4-byte addressing is through the extended address register. Details can be

found in Nonvolatile and Volatile Registers.

3-Byte Address

To execute READ MEMORY commands, S# is driven LOW. The command code is input

on DQn, followed by input on DQn of three address bytes. Each address bit is latched in

during the rising edge of the clock. The addressed byte can be at any location, and the

address automatically increments to the next address after each byte of data is shifted

out; therefore, the entire memory can be read with a single command. The operation is

terminated by driving S# HIGH at any time during data output.

Table 25: Command/Address/Data Lines for READ MEMORY Commands

Note 1 applies to entire table

Command Name

DUAL

QUAD

FAST

DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT

READ

03h

–

READ

FAST READ

STR Mode

0Bh

0Dh

3Bh

BBh

6Bh

EBh

DTR Mode

3Dh

BDh

6Dh

EDh

Extended SPI Protocol

Supported

Yes

DQ0

Yes

DQ0

Yes

Command Input

Address Input

Data Output

DQ0

DQ1

DQ0

DQ1

DQ0

DQ[1:0]

DQ0

DQ[3:0]

DQ[1:0]

DQ[3:0]

Dual SPI Protocol

Supported

No

–

Yes

No

–

No

–

Command Input

Address Input

Data Output

DQ[1:0]

–

Quad SPI Protocol

Supported

No

–

Yes

No

–

No

–

Yes

Command Input

Address Input

DQ[3:0]

–

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Table 25: Command/Address/Data Lines for READ MEMORY Commands (Continued)

Note 1 applies to entire table

Command Name

DUAL

QUAD

FAST

DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT

READ

FAST READ

STR Mode

DTR Mode

Data Output

03h

0Bh

0Dh

3Bh

3Dh

–

BBh

BDh

–

6Bh

EBh

–

6Dh

EDh

–

DQ[3:0]

1. Yes in the "Supported" row for each protocol indicates that the command in that col-

umn is supported; when supported, a command's functionality is identical for the entire

column regardless of the protocol. For example, a FAST READ functions the same for all

three protocols even though its data is input/output differently depending on the pro-

tocol.

Notes:

2. FAST READ is similar to READ, but requires dummy clock cycles following the address

bytes and can operate at a higher frequency (^fC).

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

4-Byte Address

To execute 4-byte READ MEMORY commands, S# is driven LOW. The command code is

input on DQn, followed by input on DQn of four address bytes. Each address bit is

latched in during the rising edge of the clock. The addressed byte can be at any location,

and the address automatically increments to the next address after each byte of data is

shifted out; therefore, the entire memory can be read with a single command. The oper-

ation is terminated by driving S# HIGH at any time during data output.

Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address

Notes 1 and 2 apply to entire table

Command Name (4-Byte Address)

DUAL

QUAD

FAST

DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT

READ

03h/13h

–

READ

FAST READ

3Bh/3Ch

3Dh

FAST READ

BBh/BCh

BDh

FAST READ

6Bh/6Ch

6Dh

FAST READ

EBh/ECh

EDh

STR Mode

0Bh/0Ch

0Dh

DTR Mode

Extended SPI Protocol

Supported

Yes

DQ0

Yes

DQ0

Yes

Command Input

Address Input

Data Output

DQ0

DQ1

DQ0

DQ1

DQ0

DQ[1:0]

DQ0

DQ[3:0]

DQ[1:0]

DQ[3:0]

Dual SPI Protocol

Supported

No

–

Yes

No

–

No

–

Command Input

Address Input

Data Output

DQ[1:0]

–

Quad SPI Protocol

Supported

No

–

Yes

No

–

No

–

Yes

Command Input

Address Input

Data Output

DQ[3:0]

–

1. Yes in the "Supported" row for each protocol indicates that the command in that col-

umn is supported; when supported, a command's functionality is identical for the entire

column regardless of the protocol. For example, a FAST READ functions the same for all

three protocols even though its data is input/output differently depending on the pro-

tocol.

Notes:

2. Command codes 13h, 0Ch, 3Ch, BCh, 6Ch, and ECh do not need to be set up in the ad-

dressing mode; they will work directly in 4-byte addressing mode.

3. A 4-BYTE FAST READ command is similar to 4-BYTE READ operation, but requires dum-

my clock cycles following the address bytes and can operate at a higher frequency (^fC).

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Figure 15: READ Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

DQ[0]

DQ1

Command

High-Z

MSB

A[MAX]

LSB

D_OUT

MSB

D_OUT

Don’t Care

1. C_x= 7 + (A[MAX] + 1).

Note:

READ MEMORY Operations Timing – Single Transfer Rate

Figure 16: FAST READ Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

DQ0

Command

MSB

A[MAX]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

DQ1

High-Z

Dummy cycles

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

DQ[1:0]

Command

MSB

A[MAX]

Dummy cycles

Quad

0

1

2

C_x

C

LSB

A[MIN]

LSB

D_OUT

MSB

D_OUT

DQ[3:0]

Command

MSB

A[MAX]

Don’t Care

Dummy cycles

1. For extended protocol, C_x= 7 + (A[MAX] + 1).

For dual protocol, C_x= 3 + (A[MAX] + 1)/2.

For quad protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Figure 17: DUAL OUTPUT FAST READ Command – STR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUT

D_OUT

DQ0

Command

High-Z

MSB

A[MAX]

D_OUT

MSB

D_OUT

DQ1

Dummy cycles

1. C_x= 7 + (A[MAX] + 1).

Notes:

2. Shown here is the DUAL OUTPUT FAST READ timing for the extended SPI protocol. The

dual timing shown for the FAST READ command is the equivalent of the DUAL OUTPUT

FAST READ timing for the dual SPI protocol.

Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUT

D_OUT

DQ0

Command

High-Z

MSB

D_OUT

MSB

D_OUT

DQ1

A[MAX]

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/2.

Notes:

2. Shown here is the DUAL INPUT/OUTPUT FAST READ timing for the extended SPI proto-

col. The dual timing shown for the FAST READ command is the equivalent of the DUAL

INPUT/OUTPUT FAST READ timing for the dual SPI protocol.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Figure 19: QUAD OUTPUT FAST READ Command – STR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUT

DQ0

Command

High-Z

‘1’

MSB

A[MAX]

D_OUT

DQ[2:1]

DQ3

D_OUT

MSB

Dummy cycles

1. C_x= 7 + (A[MAX] + 1).

Notes:

2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol. The

quad timing shown for the FAST READ command is the equivalent of the QUAD OUT-

PUT FAST READ timing for the quad SPI protocol.

Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUT

DQ0

Command

High-Z

‘1’

MSB

D_OUT

DQ[2:1]

DQ3

D_OUT

A[MAX]

MSB

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/4.

Notes:

2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI proto-

col. The quad timing shown for the FAST READ command is the equivalent of the QUAD

INPUT/OUTPUT FAST READ timing for the quad SPI protocol.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

READ MEMORY Operations Timing – Double Transfer Rate

Figure 21: FAST READ Command – DTR

Extended

0

7

8

C

x

C

LSB

A[MIN]

DQ0

Command

MSB

A[MAX]

LSB

OUT

D

OUT

DQ1

High-Z

OUT

MSB

Dummy cycles

Dual

0

3

4

C

x

C

LSB

A[MIN]

LSB

D

DQ[1:0]

Command

OUT

MSB

A[MAX]

MSB

Dummy cycles

Quad

0

1

2

C

x

C

LSB

A[MIN]

LSB

D

DQ[3:0]

Command

OUT

OUT OUT

MSB

A[MAX]

MSB

Don’t Care

Dummy cycles

1. For extended protocol, C_x= 7 + (A[MAX] + 1)/2.

For dual protocol, C_x= 3 + (A[MAX] + 1)/4.

For quad protocol, C_x= 1 + (A[MAX] + 1)/8.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Figure 22: DUAL OUTPUT FAST READ Command – DTR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUT

DQ0

Command

High-Z

MSB

A[MAX]

D_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUT

DQ1

MSB

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/2.

Notes:

2. Shown here is the DUAL OUTPUT FAST READ timing for the extended SPI protocol. The

dual timing shown for the FAST READ command is the equivalent of the DUAL OUTPUT

FAST READ timing for the dual SPI protocol.

Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUT

DQ0

Command

High-Z

MSB

D_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUTD_OUT

DQ1

A[MAX]

MSB

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/4.

Notes:

2. Shown here is the DUAL INPUT/OUTPUT FAST READ timing for the extended SPI proto-

col. The dual timing shown for the FAST READ command is the equivalent of the DUAL

INPUT/OUTPUT FAST READ timing for the dual SPI protocol.

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3V, 256Mb: Multiple I/O Serial Flash Memory

READ MEMORY Operations

Figure 24: QUAD OUTPUT FAST READ Command – DTR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUTD_OUTD_OUT

DQ0

Command

High-Z

‘1’

MSB

A[MAX]

D_OUTD_OUTD_OUTD_OUT

DQ[2:1]

DQ3

D_OUTD_OUTD_OUTD_OUT

MSB

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/2.

Notes:

2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol. The

quad timing shown for the FAST READ command is the equivalent of the QUAD OUT-

PUT FAST READ timing for the quad SPI protocol.

Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUTD_OUTD_OUT

DQ0

Command

High-Z

‘1’

MSB

D_OUTD_OUTD_OUTD_OUT

DQ[2:1]

DQ3

D_OUTD_OUTD_OUTD_OUT

MSB

A[MAX]

Dummy cycles

1. C_x= 7 + (A[MAX] + 1)/8.

Notes:

2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI proto-

col. The quad timing shown for the FAST READ command is the equivalent of the QUAD

INPUT/OUTPUT FAST READ timing for the quad SPI protocol.

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3V, 256Mb: Multiple I/O Serial Flash Memory

PROGRAM Operations

PROGRAM commands are initiated by first executing the WRITE ENABLE command to

set the write enable latch bit to 1. S# is then driven LOW and held LOW until the eighth

bit of the last data byte has been latched in, after which it must be driven HIGH. The

command code is input on DQ0, followed by input on DQ[n] of address bytes and at

least one data byte. Each address bit is latched in during the rising edge of the clock.

When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is

^tPP.

If the bits of the least significant address, which is the starting address, are not all zero,

all data transmitted beyond the end of the current page is programmed from the start-

ing address of the same page. If the number of bytes sent to the device exceed the maxi-

mum page size, previously latched data is discarded and only the last maximum page-

size number of data bytes are guaranteed to be programmed correctly within the same

page. If the number of bytes sent to the device is less than the maximum page size, they

are correctly programmed at the specified addresses without any effect on the other

bytes of the same page.

When the operation is in progress, the write in progress bit is set to 1. The write enable

latch bit is cleared to 0, whether the operation is successful or not. The status register

and flag status register can be polled for the operation status. An operation can be

paused or resumed by the PROGRAM/ERASE SUSPEND or PROGRAM/ERASE RESUME

command, respectively. When the operation completes, the write in progress bit is

cleared to 0.

If the operation times out, the write enable latch bit is reset and the program fail bit is

set to 1. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1. When a command is applied

to a protected sector, the command is not executed, the write enable latch bit remains

set to 1, and flag status register bits 1 and 4 are set.

Table 27: Data/Address Lines for PROGRAM Commands

Note 1 applies to entire table

Command Name

Data In

DQ0

Address In

DQ0

Extended

Yes

Dual

Yes

Quad

Yes

PAGE PROGRAM

DUAL INPUT FAST PROGRAM

DQ[1:0]

DQ0

Yes

No

EXTENDED DUAL INPUT

FAST PROGRAM

DQ[1:0]

Yes

No

QUAD INPUT FAST PROGRAM

DQ[3:0]

DQ0

Yes

No

Yes

EXTENDED QUAD INPUT

FAST PROGRAM

DQ[3:0]

1. Yes in the protocol columns indicates that the command is supported and has the same

functionality and command sequence as other commands marked Yes.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

PROGRAM Operations

Figure 26: PAGE PROGRAM Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[0]

Command

MSB

A[MAX]

MSB

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[1:0]

Command

MSB

A[MAX]

MSB

Quad

0

1

2

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[3:0]

Command

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

PROGRAM Operations

Figure 27: DUAL INPUT FAST PROGRAM Command

Extended

0

7

8

C

x

C

LSB

A[MIN]

LSB

D

DQ0

DQ1

Command

IN

MSB

A[MAX]

High-Z

IN

MSB

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[1:0]

Command

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

Note:

Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ0

Command

MSB

D_IN

High-Z

0

DQ1

A[MAX]

MSB

Dual

3

4

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[1:0]

Command

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1)/2.

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

PROGRAM Operations

Figure 29: QUAD INPUT FAST PROGRAM Command

Extended

0

7

8

C

x

C

LSB

A[MIN]

LSB

D

DQ0

Command

IN

MSB

A[MAX]

High-Z

0

DQ[3:1]

IN

MSB

Quad

1

2

C

x

C

LSB

A[MIN]

LSB

D

DQ[3:0]

Command

IN

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1)/4.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

PROGRAM Operations

Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command

Extended

0

7

8

C

x

C

LSB

A[MIN]

LSB

D

Command

DQ0

DQ[2:1]

DQ3

IN

MSB

High-Z

‘1’

0

A[MAX]

MSB

Quad

1

2

C

x

C

LSB

A[MIN]

LSB

D

Command

DQ[3:0]

IN

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1)/4.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

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56

3V, 256Mb: Multiple I/O Serial Flash Memory

WRITE Operations

WRITE ENABLE Command

The WRITE ENABLE operation sets the write enable latch bit. To execute a WRITE ENA-

BLE command, S# is driven LOW and held LOW until the eighth bit of the command

code has been latched in, after which it must be driven HIGH. The command code is

input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on

DQ[3:0] for quad SPI protocol.

The write enable latch bit must be set before every PROGRAM, ERASE, WRITE, ENTER

4-BYTE ADDRESS MODE, and EXIT 4-BYTE ADDRESS MODE command. If S# is not

driven HIGH after the command code has been latched in, the command is not execu-

ted, flag status register error bits are not set, and the write enable latch remains cleared

to its default setting of 0.

WRITE DISABLE Command

The WRITE DISABLE operation clears the write enable latch bit. To execute a WRITE

DISABLE command, S# is driven LOW and held LOW until the eighth bit of the com-

mand code has been latched in, after which it must be driven HIGH. The command

code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and

on DQ[3:0] for quad SPI protocol.

If S# is not driven HIGH after the command code has been latched in, the command is

not executed, flag status register error bits are not set, and the write enable latch re-

mains set to 1.

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3V, 256Mb: Multiple I/O Serial Flash Memory

WRITE Operations

Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence

Extended

0

1

2

3

4

5

6

7

C

S#

Command Bits

LSB

DQ[0]

0

1

0

MSB

DQ1

High-Z

Dual

0

1

2

3

C

S#

Command Bits

LSB

DQ[0]

DQ[1]

0

1

0

1

MSB

Quad

0

1

C

S#

Command Bits

LSB

DQ[0]

DQ[1]

DQ[2]

DQ[3]

0

1

0

Don’t Care

MSB

1. Shown here is the WRITE ENABLE command code, which is 06h or 0000 0110 binary. The

WRITE DISABLE command sequence is identical, except the WRITE DISABLE command

code is 04h or 0000 0100 binary.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

ERASE Operations

SUBSECTOR ERASE Command

To execute the SUBSECTOR ERASE command and set the selected subsector bits set to

FFh, the WRITE ENABLE command must be issued to set the write enable latch bit to 1.

S# is driven LOW and held LOW until the eighth bit of the last data byte has been latch-

ed in, after which it must be driven HIGH. The command code is input on DQ0, fol-

lowed by address bytes; any address within the subsector is valid. Each address bit is

latched in during the rising edge of the clock. When S# is driven HIGH, the operation,

which is self-timed, is initiated; its duration is ^tSSE. The operation can be suspended

and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME

commands, respectively.

If the write enable latch bit is not set, the device ignores the SUBSECTOR ERASE com-

mand and no error bits are set to indicate operation failure.

When the operation is in progress, the write in progress bit is set to 1. The write enable

latch bit is cleared to 0, whether the operation is successful or not. The status register

and flag status register can be polled for the operation status. When the operation com-

pletes, the write in progress bit is cleared to 0.

If the operation times out, the write enable latch bit is reset and the erase error bit is set

to 1. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1. When a command is applied

to a protected subsector, the command is not executed. Instead, the write enable latch

bit remains set to 1, and flag status register bits 1 and 5 are set.

SECTOR ERASE Command

To execute the SECTOR ERASE command (and set selected sector bits to FFh), the

WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is

driven LOW and held LOW until the eighth bit of the last data byte has been latched in,

after which it must be driven HIGH. The command code is input on DQ0, followed by

address bytes; any address within the sector is valid. Each address bit is latched in dur-

ing the rising edge of the clock. When S# is driven HIGH, the operation, which is self-

timed, is initiated; its duration is ^tSE. The operation can be suspended and resumed by

the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respec-

tively.

If the write enable latch bit is not set, the device ignores the SECTOR ERASE command

and no error bits are set to indicate operation failure.

When the operation is in progress, the write in progress bit is set to 1 and the write ena-

ble latch bit is cleared to 0, whether the operation is successful or not. The status regis-

ter and flag status register can be polled for the operation status. When the operation

completes, the write in progress bit is cleared to 0.

If the operation times out, the write enable latch bit is reset and erase error bit is set to

1. If S# is not driven HIGH, the command is not executed, flag status register error bits

are not set, and the write enable latch remains set to 1. When a command is applied to a

protected sector, the command is not executed. Instead, the write enable latch bit re-

mains set to 1, and flag status register bits 1 and 5 are set.

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3V, 256Mb: Multiple I/O Serial Flash Memory

ERASE Operations

Figure 32: SUBSECTOR and SECTOR ERASE Command

Extended

0

7

8

4

C

x

C

LSB

A[MIN]

DQ0

Command

MSB

A[MAX]

Dual

0

3

C

x

C

LSB

A[MIN]

DQ0[1:0]

Command

MSB

Quad

0

1

2

C

x

C

LSB

A[MIN]

DQ0[3:0]

Command

MSB

A[MAX]

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

BULK ERASE Command

To initiate the BULK ERASE command, the WRITE ENABLE command must be issued

to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit

of the last data byte has been latched in, after which it must be driven HIGH. The com-

mand code is input on DQ0. When S# is driven HIGH, the operation, which is self-

timed, is initiated; its duration is ^tBE.

If the write enable latch bit is not set, the device ignores the SECTOR ERASE command

and no error bits are set to indicate operation failure.

When the operation is in progress, the write in progress bit is set to 1 and the write ena-

ble latch bit is cleared to 0, whether the operation is successful or not. The status regis-

ter and flag status register can be polled for the operation status. When the operation

completes, the write in progress bit is cleared to 0.

If the operation times out, the write enable latch bit is reset and erase error bit is set to

1. If S# is not driven HIGH, the command is not executed, the flag status register error

bits are not set, and the write enable latch remains set to 1.

The command is not executed if any sector is locked. Instead, the write enable latch bit

remains set to 1, and flag status register bits 1 and 5 are set.

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3V, 256Mb: Multiple I/O Serial Flash Memory

ERASE Operations

Figure 33: BULK ERASE Command

Extended

0

7

C

LSB

DQ0

Command

0

MSB

Dual

3

C

LSB

DQ0[1:0]

Command

0

Quad

1

C

LSB

DQ0[3:0]

Command

MSB

PROGRAM/ERASE SUSPEND Command

To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The com-

mand code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RE-

SUME command.

PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt

and suspend an array PROGRAM or ERASE operation within the program/erase latency.

If a SUSPEND command is issued during a PROGRAM operation, then the flag status

register bit 2 is set to 1. After erase/program latency time, the flag status register bit 7 is

also set to 1, showing the device to be in a suspended state, waiting for any operation

(see the Operations Allowed/Disallowed During Device States table).

If a SUSPEND command is issued during an ERASE operation, then the flag status regis-

ter bit 6 is set to 1. After erase/program latency time, the flag status register bit 7 is also

set to 1, showing that device to be in a suspended state, waiting for any operation (see

the Operations Allowed/Disallowed During Device States table).

If the time remaining to complete the operation is less than the suspend latency, the de-

vice completes the operation and clears the flag status register bits 2 or 6, as applicable.

Because the suspend state is volatile, if there is a power cycle, the suspend state infor-

mation is lost and the flag status register powers up as 80h.

During an ERASE SUSPEND operation, a PROGRAM or READ operation is possible in

any sector except the one in a suspended state. Reading from a sector that is in a sus-

pended state will output indeterminate data. The device ignores a PROGRAM com-

mand to a sector that is in an ERASE SUSPEND state; it also sets to 1 the flag status reg-

ister bit 4: program failure/protection error, and leaves the write enable latch bit un-

changed. The WRITE LOCK REGISTER, WRITE VOLATILE CONFIGURATION REGIS-

TER, and WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands are

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61

3V, 256Mb: Multiple I/O Serial Flash Memory

ERASE Operations

allowed during an ERASE SUSPEND state. When the ERASE operation resumes, it does

not check the new lock status of the WRITE LOCK REGISTER command.

During a PROGRAM SUSPEND operation, a READ operation is possible in any page ex-

cept the one in a suspended state. Reading from a page that is in a suspended state will

output indeterminate data. The commands allowed during a program suspend state in-

clude the WRITE VOLATILE CONFIGURATION REGISTER command and the WRITE

ENHANCED VOLATILE CONFIGURATION REGISTER command.

It is possible to nest a PROGRAM/ERASE SUSPEND operation inside a PROGRAM/

ERASE SUSPEND operation just once. Issue an ERASE command and suspend it. Then

issue a PROGRAM command and suspend it also. With the two operations suspended,

the next PROGRAM/ERASE RESUME command resumes the latter operation, and a sec-

ond PROGRAM/ERASE RESUME command resumes the former (or first) operation.

Table 28: Suspend Parameters

Parameter

Condition

Typ

700

5

Max

Units Notes

Erase to suspend

Program to suspend

Sector erase or erase resume to erase suspend

Program resume to program suspend

–

µs

1

Subsector erase to sus-

pend

Subsector erase or subsector erase resume to erase sus-

pend

50

Suspend latency

Program

7

–

µs

2

3

Subsector erase

Erase

15

1. Timing is not internally controlled.

2. Any READ command accepted.

Notes:

3. Any command except the following are accepted: SECTOR, SUBSECTOR, or BULK ERASE;

WRITE STATUS REGISTER; WRITE NONVOLATILE CONFIGURATION REGISTER; and PRO-

GRAM OTP.

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3V, 256Mb: Multiple I/O Serial Flash Memory

ERASE Operations

Table 29: Operations Allowed/Disallowed During Device States

Note 1 applies to entire table

Standby

Program or

Erase State

Subsector Erase Suspend or

Program Suspend State

Erase Suspend

State

Operation

State

Yes

No

Notes

READ

No

Yes

No

Yes

No

Yes

Yes/No

No

2

3

4

5

6

7

8

PROGRAM

ERASE

WRITE

No

WRITE

Yes

READ

Yes

SUSPEND

No

1. The device can be in only one state at a time. Depending on the state of the device,

some operations are allowed (Yes) and others are not (No). For example, when the de-

vice is in the standby state, all operations except SUSPEND are allowed in any sector. For

all device states except the erase suspend state, if an operation is allowed or disallowed

in one sector, it is allowed or disallowed in all other sectors. In the erase suspend state, a

PROGRAM operation is allowed in any sector except the one in which an ERASE opera-

tion has been suspended.

Notes:

2. All READ operations except READ STATUS REGISTER and READ FLAG REGISTER. When is-

sued to a sector or subsector that is simultaneously in an erase suspend state, the READ

operation is accepted, but the data output is not guaranteed until the erase has comple-

ted.

3. All PROGRAM operations except PROGRAM OTP. In the erase suspend state, a PROGRAM

operation is allowed in any sector (Yes) except the sector (No) in which an ERASE opera-

tion has been suspended.

4. Applies to the SECTOR ERASE or SUBSECTOR ERASE operation.

5. Applies to the following operations: WRITE STATUS REGISTER, WRITE NONVOLATILE

CONFIGURATION REGISTER, PROGRAM OTP, and BULK ERASE.

6. Applies to the WRITE ENABLE/DISABLE, CLEAR FLAG STATUS REGISTER, WRITE EXTEN-

DED ADDRESS REGISTER, WRITE LOCK REGISTER, ENTER or EXIT 4-BYTE ADDRESS MODE,

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER operation.

7. Applies to the READ STATUS REGISTER or READ FLAG STATUS REGISTER operation.

8. Applies to the PROGRAM SUSPEND or ERASE SUSPEND operation.

PROGRAM/ERASE RESUME Command

To initiate the PROGRAM/ERASE RESUME command, S# is driven LOW. The command

code is input on DQ0. The operation is terminated by driving S# HIGH.

When this command is executed, the status register write in progress bit is set to 1, and

the flag status register program erase controller bit is set to 0. This command is ignored

if the device is not in a suspended state.

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63

3V, 256Mb: Multiple I/O Serial Flash Memory

RESET Operations

RESET ENABLE and RESET MEMORY Command

To reset the device, the RESET ENABLE command must be followed by the RESET

MEMORY command. To execute each command, S# is driven LOW. The command code

is input on DQ0. A minimum de-selection time of ^tSHSL2 must come between the RE-

SET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these

two commands are executed and S# is driven HIGH, the device enters a power-on reset

condition. A time of ^tSHSL3 is required before the device can be re-selected by driving

S# LOW. It is recommended that the device exit XIP mode before executing these two

commands to initiate a reset.

All volatile lock bits, the volatile configuration register, the enhanced volatile configura-

tion register, and the extended address register are reset to the power-on reset default

condition. The power-on reset condition depends on settings in the nonvolatile config-

uration register.

If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or

suspended, the operation is aborted and data may be corrupted.

Figure 34: RESET ENABLE and RESET MEMORY Command

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

C

S#

Reset enable

Reset memory

DQ0

1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

ONE TIME PROGRAMMABLE Operations

READ OTP ARRAY Command

To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is in-

put on DQ0, followed by address bytes and dummy clock cycles. Each address bit is

latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the

specified address and at a maximum frequency of ^fC (MAX) on the falling edge of the

clock. The address increments automatically to the next address after each byte of data

is shifted out. There is no rollover mechanism; therefore, if read continuously, after lo-

cation 0x64, the device continues to output data at location 0x64. The operation is ter-

minated by driving S# HIGH at any time during data output.

Figure 35: READ OTP Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

DQ0

DQ1

Command

MSB

A[MAX]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

High-Z

Dummy cycles

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_OUTD_OUT

D_OUT

MSB

D_OUT

DQ[1:0]

Command

MSB

A[MAX]

Dummy cycles

Quad

0

1

2

C_x

C

LSB

A[MIN]

LSB

D_OUT

MSB

D_OUT

DQ[3:0]

Command

MSB

A[MAX]

Don’t Care

Dummy cycles

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

PROGRAM OTP ARRAY Command

To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must

be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY

command is ignored and flag status register bits are not set. S# is driven LOW and held

LOW until the eighth bit of the last data byte has been latched in, after which it must be

driven HIGH. The command code is input on DQ0, followed by address bytes and at

least one data byte. Each address bit is latched in during the rising edge of the clock.

When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is

^tPOTP. There is no rollover mechanism; therefore, after a maximum of 65 bytes are

latched in and subsequent bytes are discarded.

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3V, 256Mb: Multiple I/O Serial Flash Memory

ONE TIME PROGRAMMABLE Operations

PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one

OTP control byte. When the operation is in progress, the write in progress bit is set to 1.

The write enable latch bit is cleared to 0, whether the operation is successful or not, and

the status register and flag status register can be polled for the operation status. When

the operation completes, the write in progress bit is cleared to 0.

If the operation times out, the write enable latch bit is reset and the program fail bit is

set to 1. If S# is not driven HIGH, the command is not executed, flag status register error

bits are not set, and the write enable latch remains set to 1.

The OTP control byte (byte 64) is used to permanently lock the OTP memory array.

Table 30: OTP Control Byte (Byte 64)

Bit Name

Settings

Description

0

OTP control byte

0 = Locked

1 = Unlocked

(Default)

Used to permanently lock the 64B OTP array. When bit 0 = 1, the 64B OTP

array can be programmed. When bit 0 = 0, the 64B OTP array is read only.

Once bit 0 has been programmed to 0, it can no longer be changed to 1.

PROGRAM OTP ARRAY is ignored, write enable latch bit remains set, and

flag status register bits 1 and 4 are set.

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3V, 256Mb: Multiple I/O Serial Flash Memory

ONE TIME PROGRAMMABLE Operations

Figure 36: PROGRAM OTP Command

Extended

0

7

8

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[0]

Command

MSB

A[MAX]

MSB

Dual

0

3

4

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[1:0]

Command

MSB

A[MAX]

MSB

Quad

0

1

2

C_x

C

LSB

A[MIN]

LSB

D_IN

DQ[3:0]

Command

MSB

A[MAX]

MSB

1. For extended SPI protocol, C_x= 7 + (A[MAX] + 1).

For dual SPI protocol, C_x= 3 + (A[MAX] + 1)/2.

For quad SPI protocol, C_x= 1 + (A[MAX] + 1)/4.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

ADDRESS MODE Operations – Enter and Exit 4-Byte Address

Mode

ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode

ENTER or EXIT 4-BYTE ADDRESS MODE Command

Both ENTER 4-BYTE ADDRESS MODE and EXIT 4-BYTE ADDRESS MODE commands

share the same requirements.

To enter or exit the 4-byte address mode, the WRITE ENABLE command must be execu-

ted to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must

NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must

be driven LOW. The command must be input on DQn. The effect of the command is im-

mediate; after the command has been executed, the write enable latch bit is cleared to

0.

The default address mode is three bytes, and the device returns to the default upon exit-

ing the 4-byte address mode.

ENTER or EXIT QUAD Command

The ENTER or EXIT QUAD (QPI) command is only available on the N25Q256A83ESF40x

and N25Q256A83E1240x devices. To initiate this command, the WRITE ENABLE com-

mand must not be executed. S# must be driven LOW, and the command must be input

on DQn. The effect of the command is immediate.

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3V, 256Mb: Multiple I/O Serial Flash Memory

XIP Mode

Execute-in-place (XIP) mode allows the memory to be read by sending an address to the

device and then receiving the data on one, two, or four pins in parallel, depending on

the customer requirements. XIP mode offers maximum flexibility to the application,

saves instruction overhead, and reduces random access time.

Activate or Terminate XIP Using Volatile Configuration Register

Applications that boot in SPI and must switch to XIP use the volatile configuration reg-

ister. XIP provides faster memory READ operations by requiring only an address to exe-

cute, rather than a command code and an address.

To activate XIP requires two steps. First, enable XIP by setting volatile configuration reg-

ister bit 3 to 0. Next, drive the XIP confirmation bit to 0 during the next FAST READ op-

eration. XIP is then active. Once in XIP, any command that occurs after S# is toggled re-

quires only address bits to execute; a command code is not necessary, and device oper-

ations use the SPI protocol that is enabled. XIP is terminated by driving the XIP confir-

mation bit to 1. The device automatically resets volatile configuration register bit 3 to 1.

Note: For devices with basic XIP, indicated by a part number feature set digit of 2 or 4, it

is not necessary to set the volatile configuration register bit 3 to 0 to enable XIP. Instead,

it is enabled by setting the XIP confirmation bit to 0 during the first dummy clock cycle

after any FAST READ command.

Activate or Terminate XIP Using Nonvolatile Configuration Register

Applications that must boot directly in XIP use the nonvolatile configuration register. To

enable a device to power-up in XIP using the nonvolatile configuration register, set non-

volatile configuration register bits [11:9]. Settings vary according to protocol, as ex-

plained in the Nonvolatile Configuration Register section. Because the device boots di-

rectly in XIP, the confirmation bit is already set to 0, and after the next power cycle, XIP

is active. Once in XIP, a command code is unnecessary, and device operations use the

SPI protocol currently enabled. XIP is terminated by driving the XIP confirmation bit to

1.

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3V, 256Mb: Multiple I/O Serial Flash Memory

XIP Mode

Figure 37: XIP Mode Directly After Power-On

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

C

t

VSI (<100µ)

V_CC

NVCR check:

XIP enabled

S#

A[MIN]

LSB

D_OUTD_OUTD_OUTD_OUTD_OUT

Xb

DQ0

D_OUTD_OUTD_OUTD_OUTD_OUT

MSB

DQ[3:1]

A[MAX]

Dummy cycles

1. Xb is the XIP confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit

XIP mode and return to standard read mode.

Note:

Confirmation Bit Settings Required to Activate or Terminate XIP

The XIP confirmation bit setting activates or terminates XIP after it has been enabled or

disabled. This bit is the value on DQ0 during the first dummy clock cycle in the FAST

READ operation. XIP requires at least one additional clock cycle to send the XIP confir-

mation bit to the memory on DQ0 during the first dummy clock cycle.

Table 31: XIP Confirmation Bit

Bit Value

Description

0

1

Activates XIP: While this bit is 0, XIP remains activated.

Terminates XIP: When this bit is set to 1, XIP is terminated and the device returns

to SPI.

Table 32: Effects of Running XIP in Different Protocols

Protocol

Effect

Notes

Extended I/O,

Dual I/O

In a device with a dedicated part number where RST# is enabled, a LOW pulse on RST#

resets XIP and the device to the state it was in previous to the last power-up, as defined

by the nonvolatile configuration register.

Dual I/O

Values of DQ1 during the first dummy clock cycle are "Don't Care."

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3V, 256Mb: Multiple I/O Serial Flash Memory

XIP Mode

Table 32: Effects of Running XIP in Different Protocols (Continued)

Protocol

Effect

Notes

Quad I/O

Values of DQ[3:1] during the first dummy clock cycle are "Don't Care."

In a device with a dedicated part number where RST# is enabled, a LOW pulse on RST#

resets XIP and the device to the state it was in previous to the last power-up, as defined

by the nonvolatile configuration register.

1

1. In a device with a dedicated part number, memory can be reset only when the device is

deselected.

Note:

Terminating XIP After a Controller and Memory Reset

The system controller and the device can become out of synchronization if, during the

life of the application, the system controller is reset without the device being reset. In

such a case, the controller can reset the memory to power-on reset if the memory has

reset functionality. (Reset is available in devices with a dedicated part number.)

If reset functionality is not available, has been disabled, or is not supported by the con-

troller, the controller must execute the following sequence to terminate XIP in the

memory device. In quad I/O protocol, drive DQ0 = 1 with S# held LOW for seven clock

cycles; S# must driven HIGH before the eighth clock cycle. In dual I/O protocol, drive

DQ0 = 1 with S# held LOW for 13 clock cycles; S# must driven HIGH before the four-

teenth clock cycle. If the device is in extended protocol, drive DQ0 = 1 with S# held LOW

for 25 clock cycles; S# must driven HIGH before the twenty-sixth clock cycle.

These sequences cause the controller to set the XIP confirmation bit to 1, thereby termi-

nating XIP. However, it does not reset the device or interrupt PROGRAM/ERASE opera-

tions that may be in progress. After terminating XIP, the controller must execute RESET

ENABLE and RESET MEMORY to implement a software reset and reset the device.

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71

3V, 256Mb: Multiple I/O Serial Flash Memory

Power Up and Power Down

Power Up and Power Down Requirements

At power-up and power-down, the device must not be selected; that is, S# must follow

the voltage applied on V_CCuntil V_CCreaches the correct values: V_CC,minat power-up and

V_SSat power-down.

To avoid data corruption and inadvertent WRITE operations during power-up, a power-

on reset circuit is included. The logic inside the device is held to RESET while V_CCis less

than the power-on reset threshold voltage shown here; all operations are disabled, and

the device does not respond to any instruction. During a standard power-up phase, the

device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS

REGISTER. These operations can be used to check the memory internal state. After

power-up, the device is in standby power mode; the write enable latch bit is reset; the

write in progress bit is reset; and the lock registers are configured as: (write lock bit, lock

down bit) = (0,0).

Normal precautions must be taken for supply line decoupling to stabilize the V_CCsup-

ply. Each device in a system should have the V_CCline decoupled by a suitable capacitor

(typically 100nF) close to the package pins. At power-down, when V_CCdrops from the

operating voltage to below the power-on-reset threshold voltage shown here, all opera-

tions are disabled and the device does not respond to any command.

Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,

data corruption may result.

V_PPHmust be applied only when V_CCis stable and in the V_CC,minto V_CC,maxvoltage

range.

Figure 38: Power-Up Timing

V_CC

V_CC,max

Chip selection not allowed

V_CC,min

^tVTW = ^tVTR

Polling allowed

SPI protocol

Chip

reset

Device fully accessible

V_WI

Starting protocol

defined by NVCR

WIP = 1

WEL = 0

WIP = 0

WEL = 0

Time

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3V, 256Mb: Multiple I/O Serial Flash Memory

Power Up and Power Down

Table 33: Power-Up Timing and V_WIThreshold

Note 1 applies to entire table

Symbol

^tVTR

^tVTW

Parameter

Min

–

Max

150

2.5

Unit

µs

V_CC,minto read

V_CC,minto device fully accessible

Write inhibit voltage

–

µs

V_WI

1.5

V

1. Parameters listed are characterized only.

Note:

Power Loss Recovery Sequence

If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER

command, after the next power-on, the device might begin in an undetermined state

(XIP mode or an unnecessary protocol). If this occurs, until the next power-up, a recov-

ery sequence must reset the device to a fixed state (extended SPI protocol without XIP).

After the recovery sequence, the issue should be resolved definitively by running the

WRITE NONVOLATILE CONFIGURATION REGISTER command again. The recovery se-

quence is composed of two parts that must be run in the correct order. During the en-

tire sequence, ^tSHSL2 must be at least 50ns. The first part of the sequence is DQ0 (PAD

DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed below:

• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)

• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)

• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)

• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)

• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)

• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)

The second part of the sequence is exiting from dual or quad SPI protocol by using the

following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S#

becomes HIGH before 9th clock cycle.

After this two-part sequence the extended SPI protocol is active.

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Reset Specifications

Table 34: AC RESET Conditions

Note 1 applies to entire table

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Reset pulse

width

^tRLRH²

50

–

ns

Reset recovery

time

^tRHSL Device deselected (S# HIGH) and is in XIP mode

Device deselected (S# HIGH) and is in standby mode

–

40

ns

Commands are being decoded, any READ operations are

in progress or any WRITE operation to volatile registers

are in progress

Any device array PROGRAM/ERASE/SUSPEND/RESUME,

PROGRAM OTP, NONVOLATILE SECTOR LOCK, and ERASE

NONVOLATILE SECTOR LOCK ARRAY operations are in

progress

–

30

µs

While a WRITE STATUS REGISTER operation is in progress

–

^tW

^tWNVCR

–

ms

While a WRITE NONVOLATILE CONFIGURATION REGIS-

TER operation is in progress

On completion or suspension of a SUBSECTOR ERASE op-

eration

–

^tSSE

–

s

Software reset ^tSHSL3 Device deselected (S# HIGH) and is in standby mode

–

90

30

ns

µs

recovery time

On completion of any device array PROGRAM/ERASE/

SUSPEND/RESUME, SECTOR ERASE, PROGRAM OTP, PAGE

PROGRAM, DUAL INPUT FAST PROGRAM, EXTENDED

DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PRO-

GRAM, or EXTENDED QUAD INPUT FAST PROGRAM op-

eration

On completion or suspension of a WRITE STATUS REGIS-

TER operation

–

2

^tW

^tWNVCR

^tSSE

–

ms

s

On completion or suspension of a WRITE NONVOLATILE

CONFIGURATION REGISTER operation

On completion or suspension of a SUBSECTOR ERASE op-

eration

^tSHRV Deselect to reset valid in quad output or in QIO-SPI

S# deselect to

reset valid

–

ns

1. Values are guaranteed by characterization; not 100% tested.

2. The device reset is possible but not guaranteed if ^tRLRH < 50ns.

Notes:

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Reset Specifications

Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle

S#

t

SHRH

RHSL

t

RLRH

RESET#

Don’t Care

Figure 40: Reset Enable

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

C

S#

^tSHSL2

^tSHSL3

Reset enable

Reset memory

DQ0

Figure 41: Serial Input Timing

^tSHSL

S#

^tCHSL

^tSLCH

^tCHSH

^tSHCH

C

^tCHCL

^tDVCH ^t

CHDX

^tCLCH

LSB in

DQ0

DQ1

MSB in

High-Z

Don’t Care

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Reset Specifications

Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1)

W#/V_PP

^tWHSL

^tSHWL

S#

C

DQ0

DQ1

High-Z

Don’t Care

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Reset Specifications

Figure 43: Hold Timing

S#

C

^tCHHL ^tHLCH

^tHHCH

^tCHHH

^tHLQZ

^tHHQX

DQ0

DQ1

HOLD#

Don’t Care

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Reset Specifications

Figure 44: Output Timing

S#

^tCLQV

^tCLQX

^tCL

^tCH

C

^tCLQX

^tSHQZ

DQ0

LSB out

Address

DQ1

LSB in

Don’t Care

Figure 45: V_PPHTiming

End of command

(identified by WIP polling)

S#

C

DQ0

^tVPPHSL

V_PPH

V_PP

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78

3V, 256Mb: Multiple I/O Serial Flash Memory

Absolute Ratings and Operating Conditions

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only. Exposure to absolute maximum rating for extended periods may ad-

versely affect reliability. Stressing the device beyond the absolute maximum ratings may

cause permanent damage.

Table 35: Absolute Ratings

Symbol

T_STG

Parameter

Min

–65

Max

150

Units

°C

V

Notes

Storage temperature

T_LEAD

V_CC

Lead temperature during soldering

Supply voltage

–

See note 1

4.0

–0.6

–0.2

–0.6

–2000

V_PP

Fast program/erase voltage

Input/output voltage with respect to ground

10

V

V_IO

V_CC+ 0.6

2000

V

3, 4

2

V_ESD

Electrostatic discharge voltage

(human body model)

V

1. Compliant with JEDEC Standard J-STD-020C (for small-body, Sn-Pb or Pb assembly),

RoHS, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

Notes:

2. JEDEC Standard JESD22-A114A (C1 = 100pF, R1 = 1500Ω, R2 = 500Ω).

3. During signal transitions, minimum voltage may undershoot to –1V for periods less than

10ns.

4. During signal transitions, maximum voltage may overshoot to V_CC+ 1V for periods less

than 10ns.

Table 36: Operating Conditions

Symbol

V_CC

Parameter

Min

2.7

Max

3.6

9.5

85

Units

Supply voltage

V

V_PPH

T_A

Supply voltage on V_PP

Ambient operating temperature

8.5

–40

°C

Table 37: Input/Output Capacitance

Note 1 applies to entire table

Symbol

Description

Test Condition

Min

Max

Units

C_IN/OUT

Input/output capacitance

(DQ0/DQ1/DQ2/DQ3)

V_OUT= 0V

–

8

pF

C_IN

Input capacitance (other pins)

V_IN= 0V

–

6

pF

1. These parameters are sampled only, not 100% tested. T_A= 25°C at 54 MHz.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

Absolute Ratings and Operating Conditions

Table 38: AC Timing Input/Output Conditions

Symbol

Description

Min

30

–

Max

30

Units

pF

ns

Notes

C_L

–

Load capacitance

1

Input rise and fall times

Input pulse voltages

5

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

V

2

Input timing reference voltages

Output timing reference voltages

V

V_CC/2

V

1. Output buffers are configurable by user.

2. For quad/dual operations: 0V to V_CC

Notes:

.

Figure 46: AC Timing Input/Output Reference Levels

Input levels¹

I/O timing

reference levels

0.8V_CC

0.7V_CC

0.5V_CC

0.3V_CC

0.2V_CC

1. 0.8V_CC= V_CCfor dual/quad operations; 0.2V_CC= 0V for dual/quad operations.

Note:

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3V, 256Mb: Multiple I/O Serial Flash Memory

DC Characteristics and Operating Conditions

Table 39: DC Current Characteristics and Operating Conditions

Parameter

Symbol

I_LI

Test Conditions

Min

Max

±2

Unit

µA

Input leakage current

Output leakage current

Standby current

–

I_LO

±2

µA

I_CC1

S = V_CC, V_IN= V_SSor V_CC

100

150

µA

Standby current

I_CC1

µA

(grade 3)

Operating current

(fast-read extended I/O)

I_CC3

C = 0.1V_CC/0.9V_CCat 108 MHz, DQ1

= open

–

15

6

mA

C = 0.1V_CC/0.9V_CCat 54 MHz, DQ1

= open

Operating current (fast-read dual I/O)

Operating current (fast-read quad I/O)

Operating current (program)

C = 0.1V_CC/0.9V_CCat 108 MHz

S# = V_CC

–

18

20

mA

I_CC4

I_CC5

Operating current (write status regis-

ter)

S# = V_CC

Operating current (erase)

I_CC6

S# = V_CC

–

20

mA

Table 40: DC Voltage Characteristics and Operating Conditions

Parameter

Symbol

V_IL

Conditions

Min

Max

Unit

V

Input low voltage

Input high voltage

Output low voltage

Output high voltage

–0.5

0.3V_CC

V_CC+ 0.4

0.4

V_IH

0.7V_CC

–

V

V_OL

I_OL= 1.6mA

V

V_OH

I_OH= –100µA

V_CC- 0.2

–

V

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Characteristics and Operating Conditions

Table 41: AC Characteristics and Operating Conditions

Parameter

Symbol

Min

Typ¹

Max

Unit

Notes

Clock frequency for all commands other than

READ (SPI-ER, QIO-SPI protocol)

^fC

DC

–

108

MHz

Clock frequency for READ commands

Clock HIGH time

^fR

^tCH

^tCL

DC

4

–

54

–

8

7

8

5

6

–

8

–

MHz

ns

2

Clock LOW time

4

ns

1

Clock rise time (peak-to-peak)

Clock fall time (peak-to-peak)

S# active setup time (relative to clock)

S# not active hold time (relative to clock)

Data in setup time

^tCLCH

^tCHCL

^tSLCH

^tCHSL

^tDVCH

^tCHDX

^tCHSH

^tSHCH

^tSHSL1

^tSHSL2

^tSHQZ

^tCLQV

0.1

4

V/ns

ns

3, 4

4

ns

2

ns

Data in hold time

3

ns

S# active hold time (relative to clock)

S# not active setup time (relative to clock)

S# deselect time after a READ command

S# deselect time after a nonREAD command

Output disable time

4

ns

4

ns

20

50

–

ns

3

Clock LOW to output valid under 30pF

STR

–

ns

DTR

STR

DTR

–

ns

Clock LOW to output valid under 10pF

–

ns

–

ns

Output hold time (clock LOW)

Output hold time (clock HIGH)

^tCLQX

^tCHQX

^tHLCH

^tCHHH

^tHHCH

^tCHHL

^tHHQX

^tHLQZ

^tWHSL

^tSHWL

^tVPPHSL

1

ns

1

ns

HOLD command setup time (relative to clock)

HOLD command hold time (relative to clock)

HOLD command setup time (relative to clock)

HOLD command hold time (relative to clock)

HOLD command to output Low-Z

4

ns

4

ns

4

ns

4

ns

–

ns

3

5

6

HOLD command to output High-Z

Write protect setup time

–

ns

20

100

200

ns

Write protect hold time

ns

Enhanced V_PPHHIGH to S# LOW for extended and

dual I/O page program

ns

WRITE STATUS REGISTER cycle time

^tW

^tWNVCR

–

1.3

0.2

8

3

ms

s

Write NONVOLATILE CONFIGURATION REGISTER

cycle time

CLEAR FLAG STATUS REGISTER cycle time

^tCFSR

–

40

–

ns

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3V, 256Mb: Multiple I/O Serial Flash Memory

AC Characteristics and Operating Conditions

Table 41: AC Characteristics and Operating Conditions (Continued)

Parameter

Symbol

Min

Typ¹

Max

Unit

Notes

WRITE VOLATILE CONFIGURATION REGISTER cycle

time

^tWVCR

–

40

–

ns

WRITE VOLATILE ENHANCED CONFIGURATION

REGISTER cycle time

^tWRVECR

^tWNVCR

–

40

–

ns

s

WRITE NONVOLATILE CONFIGURATION REGISTER

cycle time

0.2

3

WRITE EXTENDED ADDRESS REGISTER cycle time

PAGE PROGRAM cycle time (256 bytes)

PAGE PROGRAM cycle time (n bytes)

^tWREAR

^tPP

–

40

–

5

ns

ms

0.5

7

int(n/8) ×

0.15⁸

PAGE PROGRAM cycle time, V_PP= V_PPH( 256 bytes)

PROGRAM OTP cycle time (64 bytes)

Subsector ERASE cycle time

–

0.4

0.2

5

–

ms

s

7

^tSSE

^tSE

0.25

0.7

0.8

3

Sector ERASE cycle time

s

Sector ERASE cycle time (with V_PP= V_PPH

Bulk ERASE cycle time

)

0.6

3

s

^tBE

240

200

480

s

Bulk ERASE cycle time (with V_PP= V_PPH

)

s

1. Typical values given for T_A= 25°C.

2. ^tCH + ^tCL must add up to 1/^fC.

Notes:

3. Value guaranteed by characterization; not 100% tested.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRITE STATUS REGISTER command when STATUS

REGISTER WRITE is set to 1.

6. V_PPHshould be kept at a valid level until the PROGRAM or ERASE operation has comple-

ted and its result (success or failure) is known.

7. When using the PAGE PROGRAM command to program consecutive bytes, optimized

timings are obtained with one sequence including all the bytes versus several sequences

of only a few bytes (1 < n < 256).

8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4

int(15.3) = 16.

PDF: 09005aef84566603

n25q_256mb_65nm.pdf - Rev. P 01/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

83

3V, 256Mb: Multiple I/O Serial Flash Memory

Package Dimensions

Figure 47: V-PDFN-8/8mm x 6mm

A

8.00 TYP

Pin 1 ID

0.15

C

B

Ø0.3

Pin 1 ID R 0.20

8

7

6

5

1

2

3

4

1.27

TYP

6.00 TYP

4.80 TYP

+0.08

-0.05

0.40

0.40 ±0.05

5.16 TYP

0.2

MIN

0.10

0.05

C

0.85 TYP/

1 MAX

0.05 MAX

1. All dimensions are in millimeters.

Notes:

2. See Part Number Ordering Information for complete package names and details.

PDF: 09005aef84566603

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

84

3V, 256Mb: Multiple I/O Serial Flash Memory

Package Dimensions

Figure 48: SOP2-16/300 mils

10.30 ±0.20

16

h x 45°

9

0.23 MIN/

0.32 MAX

10.00 MIN/

10.65 MAX

7.50 ±0.10

1

8

0° MIN/8° MAX

2.5 ±0.15

0.20 ±0.1

0.1

Z

0.33 MIN/

0.51 MAX

0.40 MIN/

1.27 MAX

1.27 TYP

Z

1. All dimensions are in millimeters.

Notes:

2. See Part Number Ordering Information for complete package names and details.

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n25q_256mb_65nm.pdf - Rev. P 01/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

85

3V, 256Mb: Multiple I/O Serial Flash Memory

Package Dimensions

Figure 49: T-PBGA-24b05/6mm x 8mm

0.79 TYP

Seating

plane

A

0.1 A

Ball A1 ID

24X Ø0.40 ±0.05

Ball A1 ID

5

4

3

2

1

A

B

C

D

E

4.00

8 ±0.10

1.00 TYP

4.00

6 ±0.10

1. All dimensions are in millimeters.

1.20 MAX

0.20 MIN

Notes:

2. See Part Number Ordering Information for complete package names and details.

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n25q_256mb_65nm.pdf - Rev. P 01/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

86

3V, 256Mb: Multiple I/O Serial Flash Memory

Part Number Ordering Information

Micron Serial NOR Flash devices are available in different configurations and densities.

Verify valid part numbers by using Micron’s part catalog search at micron.com. To com-

pare features and specifications by device type, visit micron.com/products. Contact the

factory for devices not found.

For more information on how to identify products and top-side marking by the process

identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device

Marking for the M25P, M25PE, M25PX, and N25Q Product Families."

Table 42: Part Number Information

Part Number


型号：	N25Q256A
厂家：	MICRON TECHNOLOGY
描述：	Micron Serial NOR Flash Memory 美光的串行NOR闪存闪存
文件：	总90页 (文件大小：987K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

N25Q256A [MICRON]

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