RC28F00BM29EWHA_技术文档

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

Parallel NOR Flash Embedded Memory

JS28F256M29EWxx, PC28F256M29EWxx, RC28F256M29EWxx

JS28F512M29EWxx, PC28F512M29EWxx, RC28F512M29EWxx

JS28F00AM29EWxx, PC28F00AM29EWxx, RC28F00AM29EWxx

PC28F00BM29EWxx, RC28F00BM29EWxx

• V_PP/WP# pin protection

– Protects first or last block regardless of block

protection settings

• Software protection

Features

• 2Gb = stacked device (two 1Gb die)

• Supply voltage

– V_CC= 2.7–3.6V (program, erase, read)

– V_CCQ= 1.65–3.6V (I/O buffers)

• Asynchronous random/page read

– Page size: 16 words or 32 bytes

– Page access: 25ns

– Random access: 100ns (Fortified BGA);

110ns (TSOP)

• Buffer program: 512-word program buffer

• Program time

– Volatile protection

– Nonvolatile protection

– Password protection

– Password access

• Extended memory block

– 128-word (256-byte) block for permanent, secure

identification

– Programmed or locked at the factory or by the

customer

– 0.88µs per byte (1.14 MB/s) TYP when using full

512-word buffer size in buffer program

• Memory organization

– Uniform blocks: 128-Kbytes or 64-Kwords each

• Program/erase controller

– Embedded byte/word program algorithms

• Program/erase suspend and resume capability

– Read from any block during a PROGRAM SUS-

PEND operation

– Read or program another block during an ERASE

SUSPEND operation

• Low power consumption: Standby mode

• JESD47H-compliant

– 100,000 minimum ERASE cycles per block

– Data retention: 20 years (TYP)

• 65nm multilevel cell (MLC) process technology

• Fortified BGA and TSOP packages

• Green packages available

– RoHS-compliant

– Halogen-free

• Operating temperature

– Ambient: –40°C to +85°C

• BLANK CHECK operation to verify an erased block

• Unlock bypass, block erase, chip erase, and write to

buffer capability

– Fast buffered/batch programming

– Fast block/chip erase

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

Part Numbering Information

Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory

content bits erased to 1. For available options, such as packages or high/low protection, or for further information,

contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specifica-

tion comparison by device type is available at www.micron.com/products. Contact the factory for devices not

found.

Table 1: Part Number Information

Part Number

Category

Category Details

Notes

Package

JS = 56-pin TSOP, 14mm x 20mm, lead-free, halogen-free, RoHS-compliant

PC = 64-ball Fortified BGA, 11mm x 13mm, lead-free, halogen-free, RoHS-compliant

RC = 64-ball Fortified BGA, 11mm x 13mm, leaded

28F = NOR parallel interface

256 = 256Mb

Product designator

Density

512 = 512Mb

00A = 1Gb

00B = 2Gb

Device type

M29EW = Embedded Flash memory (3V core, page, uniform block)

H = Highest block protected by V_PP/WP#

L = Lowest block protected by V_PP/WP#

Device function

1

Features

A/B/D/E or an asterisk (*) = Combination of features, including packing media, special

features, and specific customer request information

1. For 2Gb device, H also indicates protection of the lowest block by V_PP/WP#.

Note:

Table 2: Standard Part Numbers by Density, Medium, and Package

Package

Density

Medium

JS

PC

RC

256Mb

Tray

JS28F256M29EWHA

JS28F256M29EWLA

JS28F256M29EWHB

JS28F256M29EWLB

JS28F512M29EWHA

JS28F512M29EWLA

JS28F512M29EWHB

JS28F512M29EWLB

JS28F00AM29EWHA

JS28F00AM29EWLA

JS28F00AM29EWHB

–

PC28F256M29EWHA

PC28F256M29EWLA

PC28F256M29EWHB

PC28F256M29EWLB

PC28F512M29EWHD

PC28F512M29EWLA

PC28F512M29EWHB

PC28F512M29EWLB

PC28F00AM29EWHA

PC28F00AM29EWLA

PC28F00AM29EWHB

PC28F00BM29EWHA

RC28F256M29EWHA

RC28F256M29EWLA

RC28F256M29EWHB

–

Tape and Reel

Tray

512Mb

1Gb

RC28F512M29EWHA

RC28F512M29EWLA

RC28F512M29EWHB

–

Tape and Reel

Tray

RC28F00AM29EWHA

RC28F00AM29EWLA

RC28F00AM29EWHB

RC28F00BM29EWHA

Tape and Reel

Tray

2Gb

1. For security features and part numbers, contact your local Micron sales representative.

Note:

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m29ew_256mb_2gb.pdf - Rev. B 8/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

Table 3: Part Numbers with Security Features by Density, Medium, and Package

Package

PC

Density

Medium

JS

–

RC

–

256Mb

Tray

PC28F256M29EWHD

PC28F256M29EWLD

–

Tape and Reel

Tray

–

512Mb

1Gb

–

PC28F512M29EWHA

PC28F512M29EWLE

PC28F512M29EWHE

PC28F00AM29EWHD

PC28F00AM29EWLE

–

Tape and Reel

Tray

–

Tape and Reel

–

1. This data sheet covers only standard parts. For security parts, contact your local Micron sales representative.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

Contents

General Description ......................................................................................................................................... 8

Device Configurability .................................................................................................................................. 9

Signal Assignments ......................................................................................................................................... 10

Signal Descriptions ......................................................................................................................................... 12

Memory Organization .................................................................................................................................... 13

Memory Configuration ............................................................................................................................... 13

Memory Map – 256Mb–2Gb Density ........................................................................................................... 13

Bus Operations ............................................................................................................................................... 14

Read .......................................................................................................................................................... 14

Write .......................................................................................................................................................... 14

Standby ..................................................................................................................................................... 14

Output Disable ........................................................................................................................................... 15

Reset .......................................................................................................................................................... 15

Registers ........................................................................................................................................................ 16

Status Register ............................................................................................................................................ 16

Lock Register .............................................................................................................................................. 21

Standard Command Definitions – Address-Data Cycles .................................................................................... 24

READ and AUTO SELECT Operations .............................................................................................................. 26

READ/RESET Command ............................................................................................................................ 26

READ CFI Command .................................................................................................................................. 26

AUTO SELECT Command ........................................................................................................................... 26

Bypass Operations .......................................................................................................................................... 28

UNLOCK BYPASS Command ...................................................................................................................... 28

UNLOCK BYPASS RESET Command ............................................................................................................ 28

Program Operations ....................................................................................................................................... 29

PROGRAM Command ................................................................................................................................ 29

UNLOCK BYPASS PROGRAM Command ..................................................................................................... 29

WRITE TO BUFFER PROGRAM Command .................................................................................................. 29

UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 31

WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 32

BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 32

PROGRAM SUSPEND Command ................................................................................................................ 32

PROGRAM RESUME Command .................................................................................................................. 33

Erase Operations ............................................................................................................................................ 33

CHIP ERASE Command .............................................................................................................................. 33

UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 33

BLOCK ERASE Command ........................................................................................................................... 34

UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 34

ERASE SUSPEND Command ....................................................................................................................... 35

ERASE RESUME Command ........................................................................................................................ 35

BLANK CHECK Operation .............................................................................................................................. 35

BLANK CHECK Commands ........................................................................................................................ 35

Block Protection Command Definitions – Address-Data Cycles ........................................................................ 37

Protection Operations .................................................................................................................................... 40

LOCK REGISTER Commands ...................................................................................................................... 40

PASSWORD PROTECTION Commands ....................................................................................................... 40

NONVOLATILE PROTECTION Commands .................................................................................................. 40

NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 43

VOLATILE PROTECTION Commands .......................................................................................................... 43

EXTENDED MEMORY BLOCK Commands .................................................................................................. 43

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

EXIT PROTECTION Command .................................................................................................................... 44

Device Protection ........................................................................................................................................... 45

Hardware Protection .................................................................................................................................. 45

Software Protection .................................................................................................................................... 45

Volatile Protection Mode ............................................................................................................................. 46

Nonvolatile Protection Mode ...................................................................................................................... 46

Password Protection Mode .......................................................................................................................... 47

Password Access ......................................................................................................................................... 47

Common Flash Interface ................................................................................................................................ 49

Power-Up and Reset Characteristics ................................................................................................................ 53

Absolute Ratings and Operating Conditions ..................................................................................................... 55

DC Characteristics .......................................................................................................................................... 57

Read AC Characteristics .................................................................................................................................. 59

Write AC Characteristics ................................................................................................................................. 62

Accelerated Program, Data Polling/Toggle AC Characteristics ........................................................................... 69

Program/Erase Characteristics ........................................................................................................................ 71

Package Dimensions ....................................................................................................................................... 72

Additional Resources ...................................................................................................................................... 74

Revision History ............................................................................................................................................. 75

Rev. B – 08/12 ............................................................................................................................................. 75

Rev. A – 04/12 ............................................................................................................................................. 75

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 8

Figure 2: 2Gb Configuration ............................................................................................................................ 9

Figure 3: 56-Pin TSOP (Top View) .................................................................................................................. 10

Figure 4: 64-Ball Fortified BGA ....................................................................................................................... 11

Figure 5: Data Polling Flowchart .................................................................................................................... 18

Figure 6: Toggle Bit Flowchart ........................................................................................................................ 19

Figure 7: Status Register Polling Flowchart ..................................................................................................... 20

Figure 8: Lock Register Program Flowchart ..................................................................................................... 22

Figure 9: Boundary Condition of Program Buffer Size ..................................................................................... 30

Figure 10: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 31

Figure 11: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 42

Figure 12: Software Protection Scheme .......................................................................................................... 47

Figure 13: Power-Up Timing .......................................................................................................................... 53

Figure 14: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 54

Figure 15: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 54

Figure 16: AC Measurement Load Circuit ....................................................................................................... 56

Figure 17: AC Measurement I/O Waveform ..................................................................................................... 56

Figure 18: Random Read AC Timing (8-Bit Mode) ........................................................................................... 60

Figure 19: Random Read AC Timing (16-Bit Mode) ......................................................................................... 60

Figure 20: BYTE# Transition Read AC Timing .................................................................................................. 61

Figure 21: Page Read AC Timing (16-Bit Mode) ............................................................................................... 61

Figure 22: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 63

Figure 23: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 64

Figure 24: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 66

Figure 25: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 67

Figure 26: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 68

Figure 27: Accelerated Program AC Timing ..................................................................................................... 69

Figure 28: Data Polling AC Timing .................................................................................................................. 69

Figure 29: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 70

Figure 30: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 72

Figure 31: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 73

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Features

List of Tables

Table 1: Part Number Information ................................................................................................................... 2

Table 2: Standard Part Numbers by Density, Medium, and Package ................................................................... 2

Table 3: Part Numbers with Security Features by Density, Medium, and Package ................................................ 3

Table 4: Signal Descriptions ........................................................................................................................... 12

Table 5: Blocks[2047:0] .................................................................................................................................. 13

Table 6: Bus Operations ................................................................................................................................. 14

Table 7: Status Register Bit Definitions ........................................................................................................... 16

Table 8: Operations and Corresponding Bit Settings ........................................................................................ 17

Table 9: Lock Register Bit Definitions ............................................................................................................. 21

Table 10: Block Protection Status ................................................................................................................... 21

Table 11: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ........................................... 24

Table 12: Read Electronic Signature ............................................................................................................... 27

Table 13: Block Protection ............................................................................................................................. 27

Table 14: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 37

Table 15: Extended Memory Block Address and Data ...................................................................................... 43

Table 16: V_PP/WP# Functions ......................................................................................................................... 45

Table 17: Query Structure Overview ............................................................................................................... 49

Table 18: CFI Query Identification String ........................................................................................................ 49

Table 19: CFI Query System Interface Information .......................................................................................... 50

Table 20: Device Geometry Definition ............................................................................................................ 50

Table 21: Primary Algorithm-Specific Extended Query Table ........................................................................... 51

Table 22: Power-Up Specifications ................................................................................................................. 53

Table 23: Reset AC Specifications ................................................................................................................... 54

Table 24: Absolute Maximum/Minimum Ratings ............................................................................................ 55

Table 25: Operating Conditions ...................................................................................................................... 55

Table 26: Input/Output Capacitance .............................................................................................................. 56

Table 27: DC Current Characteristics .............................................................................................................. 57

Table 28: DC Voltage Characteristics .............................................................................................................. 58

Table 29: Read AC Characteristics .................................................................................................................. 59

Table 30: WE#-Controlled Write AC Characteristics ......................................................................................... 62

Table 31: CE#-Controlled Write AC Characteristics ......................................................................................... 65

Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 69

Table 33: Program/Erase Characteristics ........................................................................................................ 71

Table 34: Technical Notes .............................................................................................................................. 74

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

General Description

The M29EW is an asynchronous, uniform block, parallel NOR Flash memory device

manufactured on 65nm multilevel cell (MLC) technology. READ, ERASE, and PROGRAM

operations are performed using a single low-voltage supply. Upon power-up, the device

defaults to read array mode.

The main memory array is divided into uniform blocks that can be erased independent-

ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE

commands are written to the command interface of the memory. An on-chip program/

erase controller simplifies the process of programming or erasing the memory by taking

care of all special operations required to update the memory contents. The end of a

PROGRAM or ERASE operation can be detected and any error condition can be identi-

fied. The command set required to control the device is consistent with JEDEC stand-

ards.

CE#, OE#, and WE# control the bus operation of the device and enable a simple con-

nection to most microprocessors, often without additional logic.

The M29EW supports asynchronous random read and page read from all blocks of the

array. It also features an internal program buffer that improves throughput by program-

ming 512 words via one command sequence. The device contains a 128-word extended

memory block which overlaps addresses with array block 0. The user can program this

additional space and then protect it to permanently secure the contents. The device al-

so features different levels of hardware and software protection to secure blocks from

unwanted modification.

Figure 1: Logic Diagram

V_CC

V_CCQ

V_PP/WP#

15

A[MAX:0]

DQ[14:0]

DQ15/A-1

RY/BY#

WE#

CE#

OE#

RST#

BYTE#

V_SS

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

General Description

Device Configurability

Figure 2: 2Gb Configuration

V

/WP#

CE#

PP

Upper die

(1Gb)

V

OE#

CC

V

WE#

RST#

CCQ

V

SS

DQ[14:0]

DQ15/A-1

BYTE#

Lower die

(1Gb)

A[26:0]

RY/BY#

1. A[26] = V_IHselects the upper die; A[26] = V_ILselects the lower die.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Signal Assignments

Figure 3: 56-Pin TSOP (Top View)

A23

1

A24

A25

A16

BYTE#

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

A22

2

A15

3

A14

4

A13

5

V

SS

A12

6

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

A11

7

A10

8

A9

9

A8

10

A19

11

A20

12

WE#

RST#

A21

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

/WP#

PP

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

RFU

V

SS

CE#

A0

RFU

V

CCQ

1. A-1 is the least significant address bit in x8 mode.

2. A23 is valid for 256Mb and above; otherwise, it is RFU.

3. A24 is valid for 512Mb and above; otherwise, it is RFU.

4. A25 is valid for 1Gb and above; otherwise, it is RFU.

Notes:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Signal Assignments

Figure 4: 64-Ball Fortified BGA

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

RFU A3

A7 RY/BY# WE# A9 A13 RFU

RFU A13 A9 WE# RY/BY# A7

A3 RFU

A26 A4 A17

V

/WP#RST# A8 A12 A22

A22 A12 A8 RST#V /WP# A17 A4 A26

PP

RFU A2

RFU A1

RFU A0

A6 A18 A21 A10 A14 A23

A5 A20 A19 A11 A15 V_CCQ

A23 A14 A10 A21 A18 A6

V_CCQA15 A11 A19 A20 A5

A2 RFU

A1 RFU

A0 RFU

D0

D2

D5

D7 A16 V_SS

V_SSA16 D7

D5

D2

D0

F

V_CCQCE# D8 D10 D12 D14 BYTE# A24

RFU OE# D9 D11 V_CCD13 D15/A-1 A25

A24 BYTE# D14 D12 D10 D8 CE# V_CCQ

A25 D15/A-1 D13 V_CCD11 D9 OE# RFU

G

H

G

H

RFU V_SS

D1

D3

D4

D6

V_SSRFU

RFU V_SS

D6

D4

D3

D1

V_SSRFU

Fortified BGA

Top view – ball side down

Fortified BGA

Bottom view – ball side up

1. A-1 is the least significant address bit in x8 mode.

2. A23 is valid for 256Mb and above; otherwise, it is RFU.

3. A24 is valid for 512Mb and above; otherwise, it is RFU.

4. A25 is valid for 1Gb and above; otherwise, it is RFU.

5. A26 is valid for 2Gb only; otherwise it is RFU.

Notes:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Signal Descriptions

The signal description table below is a comprehensive list of signals for this device fami-

ly. All signals listed may not be supported on this device. See Signal Assignments for in-

formation specific to this device.

Table 4: Signal Descriptions

Name

Type

Description

A[MAX:0]

Input

Address: Selects the cells in the array to access during READ operations. During WRITE oper-

ations, they control the commands sent to the command interface of the program/erase con-

troller.

CE#

Input

Chip enable: Activates the device, enabling READ and WRITE operations to be performed.

When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.

OE#

WE#

Input

Output enable: Controls the bus READ operation.

Write enable: Controls the bus WRITE operation of the command interface.

V_PP/WP#

V_PP/Write Protect: Provides WRITE PROTECT function and V_PPHfunction. These functions

protect the lowest or highest block and enable the device to enter unlock bypass mode, re-

spectively. (Refer to Hardware Protection and Bypass Operations for details.)

BYTE#

RST#

Input

Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is

LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.

Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at

least ^tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after

^tPHEL or ^tRHEL, whichever occurs last). See RESET AC Specifications for more details.

DQ[7:0]

I/O

Data I/O: Outputs the data stored at the selected address during a READ operation. During

WRITE operations, they represent the commands sent to the command interface of the inter-

nal state machine.

DQ[14:8]

Data I/O: Outputs the data stored at the selected address during a READ operation when

BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE

operations, these bits are not used. When reading the status register, these bits should be ig-

nored.

DQ15/A-1

RY/BY#

I/O

Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as

data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves

as the least significant bit of the address.

Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8

mode).

Output Ready busy: Open-drain output that can be used to identify when the device is performing

a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,

and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard-

ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET

AC Specifications for more details).

The use of an open-drain output enables the RY/BY# pins from several devices to be connec-

ted to a single pull-up resistor to V_CCQ. A low value will then indicate that one (or more) of

the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to

achieve 0.1V V_OL

.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Memory Organization

Table 4: Signal Descriptions (Continued)

Name

Type

Description

V_CC

Supply

Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.

The command interface is disabled when V_CC<= V_LKO. This prevents WRITE operations from

accidentally damaging the data during power-up, power-down, and power surges. If the pro-

gram/erase controller is programming or erasing during this time, then the operation aborts

and the contents being altered will be invalid.

A 0.1μF capacitor should be connected between V_CCand V_SSto decouple the current surges

from the power supply. The PCB track widths must be sufficient to carry the currents required

during PROGRAM and ERASE operations (see DC Characteristics).

V_CCQ

Supply

I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be

powered independently from V_CC

.

V_SS

Supply

–

Ground: All V_SSpins must be connected to the system ground.

Reserved for future use: RFUs should be not connected.

RFU

Memory Organization

Memory Configuration

The main memory array is divided into 128KB or 64KW uniform blocks.

Memory Map – 256Mb–2Gb Density

Table 5: Blocks[2047:0]

Address Range (x8)

Address Range (x16)

Block

Size

Block

Size

Block

Start

End

Start

End

2047

128KB

FFE 0000h

FFF FFFFh

64KW

7FF 0000h

7FF FFFFh

⋮

1023

7FE 0000h

7FF FFFFh

3FF 0000h

3FF FFFFh

⋮

511

3FE 0000h

3FF FFFFh

1FF 0000h

1FF FFFFh

⋮

255

1FE 0000h

1FF FFFFh

0FF 0000h

0FF FFFFh

⋮

127

⋮

0FE 0000h

0FF FFFFh

07F 0000h

07F FFFFh

⋮

63

⋮

07E 0000h

⋮

07F FFFFh

⋮

03F 0000h

⋮

03F FFFFh

⋮

0

000 0000h

001 FFFFh

000 0000h

000 FFFFh

1. 256Mb device = blocks 0–255; 512Mb device = blocks 0–511; 1Gb device = blocks 0–1023;

2Gb device = blocks 0–2047, including upper and lower die.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Bus Operations

Table 6: Bus Operations

Notes 1 and 2 apply to entire table

8-Bit Mode

16-Bit Mode

DQ15/A-1,

DQ[14:0]

Data output Cell address Data output

A[MAX:0],

DQ15/A-1

Operation CE# OE# WE# RST# V_PP/WP#

DQ[14:8]

High-Z

DQ[7:0]

A[MAX:0]

READ

L

H

L

H

X

H³

Cell address

WRITE

H

Command

address

High-Z

Data input⁴

Command

address

Data input⁴

STANDBY

H

L

X

H

X

H

X

High-Z

X

High-Z

OUTPUT

DISABLE

RESET

X

L

X

High-Z

X

High-Z

1. Typical glitches of less than 3ns on CE#, WE#, and RST# are ignored by the device and do

not affect bus operations.

Notes:

2. H = Logic level HIGH (V_IH); L = Logic level LOW (V_IL); X = HIGH or LOW.

3. If WP# is LOW, then the highest or the lowest block remains protected, depending on

line item.

4. Data input is required when issuing a command sequence or when performing data

polling or block protection.

Read

Bus READ operations read from the memory cells, registers, or CFI space. To accelerate

the READ operation, the memory array can be read in page mode where data is inter-

nally read and stored in a page buffer.

Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus

mode and A[3:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI

area do not support page read mode.

A valid bus READ operation involves setting the desired address on the address inputs,

taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.

(See AC Characteristics for details about when the output becomes valid.)

Write

Bus WRITE operations write to the command interface. A valid bus WRITE operation

begins by setting the desired address on the address inputs. The address inputs are

latched by the command interface on the falling edge of CE# or WE#, whichever occurs

last. The data I/Os are latched by the command interface on the rising edge of CE# or

WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-

ation. (See AC Characteristics for timing requirement details.)

Standby

Driving CE# HIGH in read mode causes the device to enter standby, and data I/Os to be

High-Z. To reduce the supply current to the standby supply current (I_CC2), CE# must be

held within V_CC±0.3V. (See DC Characteristics.)

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Bus Operations

During PROGRAM or ERASE operations the device will continue to use the program/

erase supply current (I_CC3) until the operation completes.

Output Disable

Reset

Data I/Os are High-Z when OE# is HIGH.

During reset mode the device is deselected and the outputs are High-Z. The device is in

reset mode when RST# is LOW. The power consumption is reduced to the standby level,

independently from CE#, OE#, or WE# inputs.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Status Register

Table 7: Status Register Bit Definitions

Note 1 applies to entire table

Bit

Name

Settings

Description

Notes

DQ7 Data polling 0 or 1, depending on

Monitors whether the program/erase controller has successful- 2, 3, 4

ly completed its operation, or has responded to an ERASE SUS-

PEND operation.

bit

operations

DQ6 Toggle bit

Toggles: 0 to 1; 1 to 0;

and so on

Monitors whether the program/erase controller has successful- 3, 4, 5

ly completed its operations, or has responded to an ERASE

SUSPEND operation. During a PROGRAM/ERASE operation,

DQ6 toggles from 0 to 1, 1 to 0, and so on, with each succes-

sive READ operation from any address.

DQ5 Error bit

0 = Success

1 = Failure

Identifies errors detected by the program/erase controller. DQ5

is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE op-

eration fails to write the correct data to the memory, or when

a BLANK CHECK operation fails.

4, 6

DQ3 Erase timer 0 = Erase not in progress Identifies the start of program/erase controller operation dur-

4

bit

1 = Erase in progress

ing a BLOCK ERASE command. Before the program/erase con-

troller starts, this bit set to 0, and additional blocks to be

erased can be written to the command interface.

DQ2 Alternative Toggles: 0 to 1; 1 to 0;

Monitors the program/erase controller during ERASE opera-

tions. During CHIP ERASE, BLOCK ERASE, and ERASE SUSPEND

operations, DQ2 toggles from 0 to 1, 1 to 0, and so on, with

each successive READ operation from addresses within the

blocks being erased.

3, 4

toggle bit

and so on

DQ1 Buffered

program

1 = Abort

Indicates a BUFFER PROGRAM operation abort. The BUFFERED

PROGRAM ABORT and RESET command must be issued to re-

turn the device to read mode (see WRITE TO BUFFER PRO-

GRAM command).

abort bit

1. The status register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations;

the READ operation outputs data on DQ[7:0].

Notes:

2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being

programmed. For a READ operation from the address previously programmed success-

fully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks

to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon

successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE or

BLANK CHECK operation in progress, DQ7 outputs 0; upon either operation's successful

completion, DQ7 outputs 1.

3. After successful completion of a PROGRAM, ERASE, or BLANK CHECK operation, the de-

vice returns to read mode.

4. During erase suspend mode, READ operations to addresses within blocks not being

erased output memory array data as if in read mode. A protected block is treated the

same as a block not being erased. See the Toggle Flowchart for more information.

5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being

erased. The toggling stops when the program/erase controller has suspended the ERASE

operation. See the Toggle Flowchart for more information.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent

command.

Table 8: Operations and Corresponding Bit Settings

Note 1 applies to entire table

Operation

PROGRAM

Address

DQ7

DQ6

DQ5

DQ3

DQ2

–

DQ1

RY/BY# Notes

Any address

DQ7#

Toggle

0

–

1

0

1

0

–

0

2

BLANK CHECK

CHIP ERASE

1

0

–

0

Any address

Toggle

No toggle

Toggle

No toggle

0

BLOCK ERASE

before time-out

Erasing block

Non-erasing block

Erasing block

Non-erasing block

0

BLOCK ERASE

0

PROGRAM

SUSPEND

Programming

block

Invalid operation

High-Z

Nonprogramming

block

Outputs memory array data as if in read mode

High-Z

ERASE

SUSPEND

Erasing block

Non-erasing block

Erasing block

1

No Toggle

0

–

Toggle

–

High-Z

0

Outputs memory array data as if in read mode

PROGRAM during

ERASE SUSPEND

DQ7#

Toggle

0

–

Toggle

No Toggle

–

1

2

Non-erasing block DQ7#

0

BUFFERED

Any address

DQ7#

High-Z

PROGRAM ABORT

PROGRAM Error

ERASE Error

Any address

DQ7#

Toggle

1

–

1

–

High-Z

2

0

1

Toggle

BLANK CHECK Er-

ror

1. Unspecified data bits should be ignored.

2. DQ7# for buffer program is related to the last address location loaded.

Notes:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Figure 5: Data Polling Flowchart

Start

Read DQ7, DQ5, and DQ1

at valid address¹

Yes

DQ7 = Data

No

DQ5 = 1

Yes

DQ1 = 1

Yes

Read DQ7 at valid address

Yes

DQ7 = Data

No

Failure²

Success

1. Valid address is the address being programmed or an address within the block being

erased or on which a BLANK CHECK operation has been executed.

Notes:

2. The data polling process does not support the BLANK CHECK operation. The process

represented in the Toggle Bit Flowchart figure can provide information on the BLANK

CHECK operation.

3. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF-

FER PROGRAM ABORT operation.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Figure 6: Toggle Bit Flowchart

Start

Read DQ6 at valid address

Read DQ6, DQ5, and DQ1

at valid address

No

DQ6 = Toggle

Yes

No

DQ5 = 1

DQ1 = 1

Yes

Read DQ6 (twice) at valid address

No

DQ6 = Toggle

Yes

Failure¹

Success

1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF-

FER PROGRAM ABORT operation.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Figure 7: Status Register Polling Flowchart

Start

Yes

PROGRAM operation

No

Read 3 correct data?

No

DQ7 = Valid data

No

PROGRAM operation

failure

DQ5 = 1

No

Yes

DQ6 = Toggling

Device error

Read2.DQ6 = Read3.DQ6

No

Yes

DQ2 = Toggling

Read2.DQ2 = Read3.DQ2

DQ6 = Toggling

Timeout failure

Erase/suspend mode

Read1.DQ6 = Read2.DQ6

No

ERASE operation

complete

PROGRAM operation

complete

Device busy: Repolling

WRITE TO BUFFER

Yes

WRITE TO BUFFER

PROGRAM

DQ1 = 1

No

PROGRAM

abort

No

Device busy: Repolling

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Lock Register

Table 9: Lock Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

Description

Notes

DQ2 Password

protection

0 = Password protection

mode enabled

Places the device permanently in password protection mode.

2

mode lock bit 1 = Password protection

mode disabled (Default)

DQ1 Nonvolatile

protection

0 = Nonvolatile protection Places the device in nonvolatile protection mode with pass-

mode enabled with pass- word protection mode permanently disabled. When shipped

2

mode lock bit word protection mode

from the factory, the device will operate in nonvolatile protec-

tion mode, and the memory blocks are unprotected.

permanently disabled

1 = Nonvolatile protection

mode enabled (Default)

DQ0 Extended

memory

0 = Protected

If the device is shipped with the extended memory block un-

1 = Unprotected (Default) locked, the block can be protected by setting this bit to 0. The

extended memory block protection status can be read in auto

select mode by issuing an AUTO SELECT command.

block

protection bit

1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and

are set to a default value of 1.

Notes:

2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot

both be programmed to 0. Any attempt to program one while the other is programmed

causes the operation to abort, and the device returns to read mode. The device is ship-

ped from the factory with the default setting.

Table 10: Block Protection Status

Nonvolatile

Block

Protection

Status

Protection Bit

Lock Bit¹

Nonvolatile

Volatile

Protection Bit²Protection Bit³

Block Protection Status

1

0

1

0

1

0

00h

01h

Block unprotected; nonvolatile protection bit changea-

ble.

Block protected by volatile protection bit; nonvolatile

protection bit changeable.

Block protected by nonvolatile protection bit; nonvola-

tile protection bit changeable.

Block protected by nonvolatile protection bit and vola-

tile protection bit; nonvolatile protection bit changea-

ble.

0

1

0

1

0

1

00h

01h

Block unprotected; nonvolatile protection bit un-

changeable.

Block protected by volatile protection bit; nonvolatile

protection bit unchangeable.

Block protected by nonvolatile protection bit; nonvola-

tile protection bit unchangeable.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

Table 10: Block Protection Status (Continued)

Nonvolatile

Protection Bit

Lock Bit¹

Block

Protection

Status

Nonvolatile

Volatile

Protection Bit²Protection Bit³

Block Protection Status

0

01h

Block protected by nonvolatile protection bit and vola-

tile protection bit; nonvolatile protection bit unchange-

able.

1. Nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are

unlocked; when set to 0, all nonvolatile protection bits are locked.

Notes:

2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set

to 0, the block is protected.

3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0,

the block is protected.

Figure 8: Lock Register Program Flowchart

Start

ENTER LOCK REGISTER COMMAND SET

Address-data (unlock) cycle 1

Address-data (unlock) cycle 2

Address-data cycle 3

PROGRAM LOCK REGISTER

Address-data cycle 1

Address-data cycle 2

Polling algorithm

Yes

Done?

No

DQ5 = 1

Yes

Success:

Failure:

EXIT PROTECTION COMMAND SET

(Returns to device read mode)

Address-data cycle 1

READ/RESET

(Returns device to read mode)

Address-data cycle 2

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Registers

1. Each lock register bit can be programmed only once.

Notes:

2. See the Block Protection Command Definitions table for address-data cycle details.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Standard Command Definitions – Address-Data Cycles

Table 11: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit

Note 1 applies to entire table

Address and Data Cycles

1st

2nd

3rd

4th

5th

6th

Command and

Code/Subcode

Bus

Size

A

D

A

D

A

D

A

D

A

D

A

D

Notes

READ and AUTO SELECT Operations

READ/RESET (F0h)

x8

X

F0

AAA AA

555

55

X

F0

x16

X

F0

555

AA

55

AA 2AA

98

READ CFI (98h)

x8

x16

x8

AUTO SELECT (90h)

AAA AA

555

55

AAA

555

90 Note Note

2, 3, 4

2

x16

2AA

BYPASS Operations

UNLOCK BYPASS (20h)

x8

x16

x8

AAA AA

555

2AA

X

55

00

AAA

555

20

UNLOCK BYPASS

RESET (90h/00h)

X

90

x16

PROGRAM Operations

PROGRAM (A0h)

x8

x16

x8

AAA AA

555

2AA

PA

55

PD

55

N

AAA A0

555

PA

PD

N

UNLOCK BYPASS

PROGRAM (A0h)

X

A0

5

6, 7, 8

5

x16

x8

WRITE TO BUFFER

PROGRAM (25h)

AAA AA

555

2AA

BAd

PA

25

BAd

PA

PD

x16

x8

UNLOCK BYPASS

WRITE TO BUFFER

PROGRAM (25h)

BAd

25

PD

x16

WRITE TO BUFFER

PROGRAM CONFIRM

(29h)

x8

BAd

29

x16

BUFFERED PROGRAM

ABORT and RESET (F0h)

x8

x16

x8

AAA AA

555

55

AAA

555

F0

2AA

PROGRAM SUSPEND

(B0h)

X

B0

x16

x8

PROGRAM RESUME

(30h)

X

30

x16

ERASE Operations

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Standard Command Definitions – Address-Data Cycles

Table 11: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)

Note 1 applies to entire table

Address and Data Cycles

1st

2nd

3rd

4th

5th

6th

Command and

Code/Subcode

Bus

Size

A

D

A

D

A

D

A

D

A

D

A

D

Notes

CHIP ERASE (80/10h)

x8

x16

x8

AAA AA

555

2AA

X

55

AAA

555

80 AAA AA

555

55

AAA

555

10

2AA

UNLOCK BYPASS

CHIP ERASE (80/10h)

X

80

10

55

30

5

9

5

x16

x8

BLOCK ERASE (80/30h)

AAA AA

555

2AA

BAd

AAA

555

80 AAA AA

555

55

BAd

30

x16

x8

2AA

UNLOCK BYPASS

BLOCK ERASE (80/30h)

X

80

B0

30

x16

x8

ERASE SUSPEND (B0h)

x16

x8

ERASE RESUME (30h)

x16

BLANK CHECK Operations

BLANK CHECK

SETUP (EB/76h)

x8

x16

AAA AA

555

55

BAd

EB

BAd

76

BAd

00

BAd

00

2AA

BLANK CHECK CONFIRM x8

BAd

29

BAd Note

2

and READ (29h)

x16

1. A = Address; D = Data; X = "Don't Care;" BAd = Any address in the block; N = Number of

bytes to be programmed; PA = Program address; PD = Program data; Gray shading = Not

applicable. All values in the table are hexadecimal. Some commands require both a com-

mand code and subcode. For the 2Gb device, the set-up command must be issued for

each selected die.

Notes:

2. These cells represent READ cycles (versus WRITE cycles for the others).

3. AUTO SELECT enables the device to read the manufacturer code, device code, block pro-

tection status, and extended memory block protection indicator.

4. AUTO SELECT addresses and data are specified in the Electronic Signature table and the

Extended Memory Block Protection table.

5. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are

unnecessary.

6. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM

3rd and 4th cycles.

7. WRITE TO BUFFER PROGRAM operation: maximum cycles = 261 (x8) and 517 (x16). UN-

LOCK BYPASS WRITE TO BUFFER PROGRAM operation: maximum cycles = 259 (x8), 515

(x16). WRITE TO BUFFER PROGRAM operation: N + 1 = bytes to be programmed; maxi-

mum buffer size = 256 bytes (x8) and 1024 bytes (x16).

8. For x8, A[MAX:7] address pins should remain unchanged while A[6:0] and A-1 pins are

used to select a byte within the N + 1 byte page. For x16, A[MAX:9] address pins should

remain unchanged while A[8:0] pins are used to select a word within the N+1 word

page.

9. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on

the number of blocks to erase.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

READ and AUTO SELECT Operations

READ/RESET Command

The READ/RESET (F0h) command returns the device to read mode and resets the errors

in the status register. One or three bus WRITE operations can be used to issue the

READ/RESET command.

To return the device to read mode, this command can be issued between bus WRITE

cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET com-

mand is issued during the timeout of a BLOCK ERASE operation, the device requires up

to 10μs to abort, during which time no valid data can be read.

This command will not abort an ERASE operation while in erase suspend.

READ CFI Command

The READ CFI (98h) command puts the device in read CFI mode and is only valid when

the device is in read array or auto select mode. One bus WRITE cycle is required to issue

the command.

Once in read CFI mode, bus READ operations will output data from the CFI memory

area (Refer to the Common Flash Interface for details). A READ/RESET command must

be issued to return the device to the previous mode (read array or auto select ). A sec-

ond READ/RESET command is required to put the device in read array mode from auto

select mode.

AUTO SELECT Command

At power-up or after a hardware reset, the device is in read mode. It can then be put in

auto select mode by issuing an AUTO SELECT (90h) command. Auto select mode ena-

bles the following device information to be read:

• Electronic signature, which includes manufacturer and device code information as

shown in the Electronic Signature table.

• Block protection, which includes the block protection status and extended memory

block protection indicator, as shown in the Block Protection table.

Electronic signature or block protection information is read by executing a READ opera-

tion with control signals and addresses set, as shown in the Read Electronic Signature

table or the Block Protection table, respectively. In addition, this device information can

be read or set by issuing an AUTO SELECT command.

Auto select mode can be used by the programming equipment to automatically match a

device with the application code to be programmed.

Three consecutive bus WRITE operations are required to issue an AUTO SELECT com-

mand. The device remains in auto select mode until a READ/RESET or READ CFI com-

mand is issued.

The device cannot enter auto select mode when a PROGRAM or ERASE operation is in

progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or

ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUS-

PEND command.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

READ and AUTO SELECT Operations

Auto select mode is exited by performing a reset. The device returns to read mode un-

less it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND

command, in which case it returns to erase or program suspend mode.

Table 12: Read Electronic Signature

Note 1 applies to entire table

Address Input

Data Input/Output

8-Bit Only 16-Bit Only

DQ[15]/A-1,

CE# OE# WE# A[MAX:4] A3 A2 A1 A0 DQ[15]/A-1 DQ[14:8] DQ[7:0] DQ[14:0]

8-Bit/16-Bit

8-Bit Only

Read Cycle

Manufacturer code

Device code 1

L

H

L

H

L

X

89h

7Eh

22h

23h

28h

48h

01h

0089h

227Eh

2222h

2223h

2228h

2248h

2201h

L

Device

code 2

256Mb

512Mb

1Gb

H

L

2Gb

L

Device code 3

H

1. H = Logic level HIGH (V_IH); L = Logic level LOW (V_IL); X = HIGH or LOW.

Note:

Table 13: Block Protection

Note 1 applies to entire table

Address Input

8-Bit/16-Bit

Data Input/Output

8-Bit Only

16-Bit Only

DQ[15]/A-1,

CE# OE# WE# A[MAX:16] A[15:2] A1 A0 DQ[15]/A-1 DQ[14:8] DQ[7:0] DQ[14:0]

Read Cycle

Extended M29EWL

memory

L

H

L

H

X

89h²

09h³

99h²

19h³

0089h²

0009h³

0099h²

0019h³

Block

M29EWH

protection

L

H

L

H

X

indicator

(DQ7)

Block protection

status

L

H

Block base

address

L

H

L

X

01h⁴

00h⁵

0001h⁴

0000h⁵

1. H = Logic level HIGH (V_IH); L = Logic level LOW (V_IL); X = HIGH or LOW.

2. Micron-prelocked (permanent).

Notes:

3. Customer-lockable.

4. Protected: 01h (in x8 mode) is output on DQ[7:0]; indicates that the extended memory

block is permanently prelocked by Micron.

5. Unprotected: 00h (in x8 mode) is output on DQ[7:0]; indicates that the extended memo-

ry block can be locked by customer.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Bypass Operations

UNLOCK BYPASS Command

The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass

mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS com-

mand.

When the device enters unlock bypass mode, the two initial UNLOCK cycles required

for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total

program or erase time.

The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PRO-

GRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster

than with standard PROGRAM or ERASE commands. When the cycle time to the device

is long, considerable time savings can be gained by using these commands. When in

unlock bypass mode, only the following commands are valid:

• The UNLOCK BYPASS PROGRAM command can be issued to program addresses

within the device.

• The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or

more memory blocks.

• The UNLOCK BYPASS CHIP ERASE command can be issued to erase the whole mem-

ory array.

• The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command can be issued to

speed up the programming operation.

• The UNLOCK BYPASS RESET command can be issued to return the device to read

mode.

In unlock bypass mode, the device can be read as if in read mode.

In addition to the UNLOCK BYPASS command, when V_PP/WP# is raised to V_PPH, the de-

vice automatically enters unlock bypass mode. When V_PP/WP# returns to V_IHor V_IL, the

device is no longer in unlock bypass mode and normal operation resumes. The transi-

tions from V_IHto V_PPHand from V_PPHto V_IHmust be slower than ^tVHVPP (see the Accel-

erated Program, Data Polling/Toggle AC Characteristics).

Note: Micron recommends the user enter and exit unlock bypass mode using ENTER

UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising V_PP/WP#

to V_PPH. V_PP/WP# should never be raised to V_PPHfrom any mode except read mode; oth-

erwise, the device may be left in an indeterminate state.

UNLOCK BYPASS RESET Command

The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode

from unlock bypass mode. Two bus WRITE operations are required to issue the UN-

LOCK BYPASS RESET command. The READ/RESET command does not exit from un-

lock bypass mode.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Program Operations

PROGRAM Command

The PROGRAM (A0h) command can be used to program a value to one address in the

memory array. The command requires four bus WRITE operations, and the final WRITE

operation latches the address and data in the internal state machine and starts the pro-

gram/erase controller. After programming has started, bus READ operations output the

status register content.

Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND

command and a PROGRAM RESUME command, respectively.

If the address falls in a protected block, the PROGRAM command is ignored, and the

data remains unchanged. The status register is not read, and no error condition is given.

After the PROGRAM operation has completed, the device returns to read mode, unless

an error has occurred. When an error occurs, bus READ operations to the device contin-

ue to output the status register. A READ/RESET command must be issued to reset the

error condition and return the device to read mode.

The PROGRAM command cannot change a bit set to 0 back to 1, and an attempt to do

so is masked during a PROGRAM operation. Instead, an ERASE command must be used

to set all bits in one memory block or in the entire memory from 0 to 1.

The PROGRAM operation is aborted by performing a reset or by powering-down the de-

vice. In this case, data integrity cannot be ensured, and it is recommended that the

words or bytes that were aborted be reprogrammed.

UNLOCK BYPASS PROGRAM Command

When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h)

command can be used to program one address in the memory array. The command re-

quires two bus WRITE operations instead of four required by a standard PROGRAM

command; the final WRITE operation latches the address and data and starts the pro-

gram/erase controller (The standard PROGRAM command requires four bus WRITE op-

erations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command

behaves identically to the PROGRAM operation using the PROGRAM command. The

operation cannot be aborted. A bus READ operation to the memory outputs the status

register.

WRITE TO BUFFER PROGRAM Command

The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to

speed up programming and dramatically reduces system programming time compared

to the standard non-buffered PROGRAM command. 256Mb through 2Gb devices sup-

port a 512-word maximum program buffer.

When issuing a WRITE TO BUFFER PROGRAM command, V _PP/WP# can be held HIGH

or raised to V_PPH. Also, it can be held LOW if the block is not the lowest or highest block,

depending on the part number.

The following successive steps are required to issue the WRITE TO BUFFER PROGRAM

command:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Program Operations

First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE

TO BUFFER PROGRAM command. The set-up code can be addressed to any location

within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/

bytes to be programmed. Value n is written to the same block address, where n + 1 is the

number of words/bytes to be programmed. Value n + 1 must not exceed the size of the

program buffer, or the operation will abort. A fifth cycle loads the first address and data

to be programmed. Last, n bus WRITE cycles load the address and data for each word/

byte into the program buffer. Addresses must lie within the range from the start address

+1 to the start address + (n - 1).

Optimum programming performance and lower power usage are achieved by aligning

the starting address at the beginning of a 512-word boundary (A[8:0] = 0x000h). Any

buffer size smaller than 512 words is allowed within a 512-word boundary, while all ad-

dresses used in the operation must lie within the 512-word boundary. In addition, any

crossing boundary buffer program will result in a program abort. For a x8 device, maxi-

mum buffer size is 256 bytes; for a x16 device, the maximum buffer size is 1024 bytes.

To program the content of the program buffer, this command must be followed by a

WRITE TO BUFFER PROGRAM CONFIRM command.

If an address is written several times during a WRITE TO BUFFER PROGRAM operation,

the address/data counter will be decremented at each data load operation, and the data

will be programmed to the last word loaded into the buffer.

Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort

the WRITE TO BUFFER PROGRAM command.

The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status

during a WRITE TO BUFFER PROGRAM operation.

The WRITE TO BUFFER PROGRAM command should not be used to change a bit set to

0 back to 1, and an attempt to do so is masked during the operation. Rather than the

WRITE TO BUFFER PROGRAM command, the ERASE command should be used to set

memory bits from 0 to 1.

Figure 9: Boundary Condition of Program Buffer Size

0000h

511 words

or less are

allowed

in the

program

buffer

512-word

program

buffer is

allowed

512 Words

Any

buffer

program

attempt

is not

0200h

allowed

512-word

program

buffer is

allowed

512 Words

0400h

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Program Operations

Figure 10: WRITE TO BUFFER PROGRAM Flowchart

Start

WRITE TO BUFFER

command,

WRITE TO BUFFER

confirm, block address

block address

Read status register

(DQ1, DQ5, DQ7) at

last loaded address

1

Write n,

block address

First three cycles of the

WRITE TO BUFFER

PROGRAM command

Write buffer data,

start address

Yes

DQ7 = Data

No

X = n

No

DQ1 = 1

Yes

DQ5 = 1

Yes

X = 0

No

Check status register

(DQ5, DQ7) at

last loaded address

Abort

WRITE TO BUFFER

Write to a different

block address

Yes

No

4

DQ7 = Data

WRITE TO BUFFER

and PROGRAM

3

Write next data,

program address pair

2

aborted

No

Fail or

abort

End

5

X = X - 1

1. n + 1 is the number of addresses to be programmed.

Notes:

2. The BUFFERED PROGRAM ABORT and RESET command must be issued to return the de-

vice to read mode.

3. When the block address is specified, any address in the selected block address space is

acceptable. However, when loading program buffer address with data, all addresses

must fall within the selected program buffer page.

4. DQ7 must be checked because DQ5 and DQ7 may change simultaneously.

5. If this flowchart location is reached because DQ5 = 1, then the WRITE TO BUFFER PRO-

GRAM command failed. If this flowchart location is reached because DQ1 = 1, then the

WRITE TO BUFFER PROGRAM command aborted. In both cases, the appropriate RESET

command must be issued to return the device to read mode: A RESET command if the

operation failed; a WRITE TO BUFFER PROGRAM ABORT AND RESET command if the op-

eration aborted.

6. See the Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit table for

details about the WRITE TO BUFFER PROGRAM command sequence.

UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command

When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER

(25h) command can be used to program the device in fast program mode. The com-

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Program Operations

mand requires two bus WRITE operations fewer than the standard WRITE TO BUFFER

PROGRAM command.

The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way

as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and

a bus READ operation to the memory outputs the status register.

The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UN-

LOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n + 1

words/bytes loaded in the program buffer by this command.

WRITE TO BUFFER PROGRAM CONFIRM Command

The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a

WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded

in the program buffer by this command.

BUFFERED PROGRAM ABORT AND RESET Command

A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset

the device to read mode when the BUFFER PROGRAM operation is aborted. The buffer

programming sequence can be aborted in the following ways:

• Load a value that is greater than the page buffer size during the number of locations

to program in the WRITE TO BUFFER PROGRAM command.

• Write to an address in a different block than the one specified during the WRITE BUF-

FER LOAD command.

• Write an address/data pair to a different write buffer page than the one selected by

the starting address during the program buffer data loading stage of the operation.

• Write data other than the CONFIRM command after the specified number of data

load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location

loaded), DQ6 = toggle, and DQ5 = 0 (all of which are status register bits). A BUFFERED

PROGRAM ABORT and RESET command sequence must be written to reset the device

for the next operation.

Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command se-

quence is required when using buffer programming features in unlock bypass mode.

PROGRAM SUSPEND Command

The PROGRAM SUSPEND (B0h) command can be used to interrupt a program opera-

tion so that data can be read from any block. When the PROGRAM SUSPEND command

is issued during a program operation, the device suspends the operation within the pro-

gram suspend latency time and updates the status register bits.

After the program operation has been suspended, data can be read from any address.

However, data is invalid when read from an address where a program operation has

been suspended.

The PROGRAM SUSPEND command may also be issued during a PROGRAM operation

while an erase is suspended. In this case, data may be read from any address not in

erase suspend or program suspend mode. To read from the extended memory block

area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK

command sequences must be issued.

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Erase Operations

The system may also issue the AUTO SELECT command sequence when the device is in

program suspend mode. The system can read as many auto select codes as required.

When the device exits auto select mode, the device reverts to program suspend mode

and is ready for another valid operation.

The PROGRAM SUSPEND operation is aborted by performing a device reset or power-

down. In this case, data integrity cannot be ensured, and it is recommended that the

words or bytes that were aborted be reprogrammed.

PROGRAM RESUME Command

The PROGRAM RESUME (30h) command must be issued to exit a program suspend

mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status

bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME

command is issued, subsequent PROGRAM RESUME commands are ignored. Another

PROGRAM SUSPEND command can be issued after the device has resumed program-

ming.

Erase Operations

CHIP ERASE Command

The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations

are required to issue the command and start the program/erase controller.

Protected blocks are not erased. If all blocks are protected, the CHIP ERASE operation

appears to start, but will terminate within approximately100μs, leaving the data un-

changed. No error is reported when protected blocks are not erased.

During the CHIP ERASE operation, the device ignores all other commands, including

ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur-

ing CHIP ERASE output the status register on the data I/Os. See the Status Register sec-

tion for more details.

After the CHIP ERASE operation completes, the device returns to read mode, unless an

error has occurred. If an error occurs, the device will continue to output the status regis-

ter. A READ/RESET command must be issued to reset the error condition and return to

read mode.

The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1.

All previous data is lost.

The operation is aborted by performing a reset or by powering-down the device. In this

case, data integrity cannot be ensured, and it is recommended that the entire chip be

erased again.

UNLOCK BYPASS CHIP ERASE Command

When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h)

command can be used to erase all memory blocks at one time. The command requires

only two bus WRITE operations instead of six using the standard CHIP ERASE com-

mand. The final bus WRITE operation starts the program/erase controller.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Erase Operations

The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP

ERASE command: the operation cannot be aborted, and a bus READ operation to the

memory outputs the status register.

BLOCK ERASE Command

The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all of

the bits in the unprotected selected blocks to 1. All previous data in the selected blocks

is lost.

Six bus WRITE operations are required to select the first block in the list. Each addition-

al block in the list can be selected by repeating the sixth bus WRITE operation using the

address of the additional block. After the command sequence is written, a block erase

timeout occurs. During the timeout period, additional block addresses and BLOCK

ERASE commands can be written. After the program/erase controller has started, it is

not possible to select any more blocks. Each additional block must therefore be selected

within the timeout period of the last block. The timeout timer restarts when an addi-

tional block is selected. After the sixth bus WRITE operation, a bus READ operation out-

puts the status register. See the WE#-Controlled Program waveforms for details on how

to identify if the program/erase controller has started the BLOCK ERASE operation.

After the BLOCK ERASE operation completes, the device returns to read mode, unless

an error has occurred. If an error occurs, bus READ operations will continue to output

the status register. A READ/RESET command must be issued to reset the error condi-

tion and return to read mode.

If any selected blocks are protected, they are ignored, and all the other selected blocks

are erased. If all of the selected blocks are protected, the BLOCK ERASE operation ap-

pears to start, but will terminate within approximately100μs, leaving the data un-

changed. No error condition is given when protected blocks are not erased.

During the BLOCK ERASE operation, the device ignores all commands except the

ERASE SUSPEND command and the READ/RESET command, which is accepted only

during the timeout period. The operation is aborted by performing a reset or powering-

down the device. In this case, data integrity cannot be ensured, and it is recommended

that the aborted blocks be erased again.

UNLOCK BYPASS BLOCK ERASE Command

When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE

(80/30h) command can be used to erase one or more memory blocks at a time. The

command requires two bus WRITE operations instead of six using the standard BLOCK

ERASE command. The final bus WRITE operation latches the address of the block and

starts the program/erase controller.

To erase multiple blocks (after the first two bus WRITE operations have selected the first

block in the list), each additional block in the list can be selected by repeating the sec-

ond bus WRITE operation using the address of the additional block.

The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK

ERASE command: the operation cannot be aborted, and a bus READ operation to the

memory outputs the status register. See the BLOCK ERASE Command section for de-

tails.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

BLANK CHECK Operation

ERASE SUSPEND Command

The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE opera-

tion. One bus WRITE operation is required to issue the command. The block address is

"Don't Care."

The program/erase controller suspends the ERASE operation within the erase suspend

latency time of the ERASE SUSPEND command being issued. However, when the

ERASE SUSPEND command is written during the block erase timeout, the device im-

mediately terminates the timeout period and suspends the ERASE operation. After the

program/erase controller has stopped, the device operates in read mode, and the erase

is suspended.

During an ERASE SUSPEND operation, it is possible to read and execute PROGRAM op-

erations or WRITE TO BUFFER PROGRAM operations in blocks that are not suspended.

Both READ and PROGRAM operations behave normally on these blocks. Reading from

blocks that are suspended will output the status register. If any attempt is made to pro-

gram in a protected block or in the suspended block, the PROGRAM command is ignor-

ed, and the data remains unchanged. In this case, the status register is not read, and no

error condition is given.

It is also possible to issue AUTO SELECT, READ CFI, and UNLOCK BYPASS commands

during an ERASE SUSPEND operation. The READ/RESET command must be issued to

return the device to read array mode before the RESUME command will be accepted.

During an ERASE SUSPEND operation, a bus READ operation to the extended memory

block will output the extended memory block data. After the device enters extended

memory block mode, the EXIT EXTENDED MEMORY BLOCK command must be issued

before the ERASE operation can be resumed.

An ERASE SUSPEND command is ignored if it is written during a CHIP ERASE opera-

tion.

If the ERASE SUSPEND operation is aborted by performing a device reset or power-

down, data integrity cannot be ensured, and it is recommended that the suspended

blocks be erased again.

ERASE RESUME Command

The ERASE RESUME (30h) command restarts the program/erase controller after an

ERASE SUSPEND operation.

The device must be in read array mode before the RESUME command will be accepted.

An erase can be suspended and resumed more than once.

BLANK CHECK Operation

BLANK CHECK Commands

Two commands are required to execute a BLANK CHECK operation: BLANK CHECK

SETUP (EB/76h) and BLANK CHECK CONFIRM AND READ (29h).

The BLANK CHECK operation determines whether a specified block is blank (that is,

completely erased). It can also be used to determine whether a previous ERASE opera-

tion was successful, including ERASE operations that might have been interrupted by

power loss.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

BLANK CHECK Operation

The BLANK CHECK operation checks for cells that are programmed or over-erased. If it

finds any, it returns a failure status, indicating that the block is not blank. If it returns a

passing status, the block is guaranteed blank (all 1s) and is ready to program.

Before executing, the ERASE operation initiates a BLANK CHECK operation, and if the

target block is blank, the ERASE operation is skipped, benefitting overall cycle perform-

ance; otherwise, the ERASE operation continues.

The BLANK CHECK operation can occur in only one block at a time, and during its exe-

cution, reading the status register is the only other operation allowed. Reading from any

address in the device enables reading the status register to monitor blank check pro-

gress or errors. Operations such as READ (array data), PROGRAM, ERASE, and any sus-

pended operation are not allowed.

After the BLANK CHECK operation has completed, the device returns to read mode un-

less an error has occurred. When an error occurs, the device continues to output status

register data. A READ/RESET command must be issued to reset the error condition and

return the device to read mode.

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Block Protection Command Definitions – Address-Data Cycles

Table 14: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit

Notes 1 and 2 apply to entire table

Address and Data Cycles

1st

2nd

3rd

4th

nth

Command and

Code/Subcode

Bus

Size

A

D

A

D

A

D

A

D

…

A

D

Notes

LOCK REGISTER Commands

ENTER LOCK REGISTER

COMMAND SET (40h)

x8

x16

x8

AAA

555

X

AA

A0

555

55

AAA

555

40

3

5

2AA

X

PROGRAM LOCK REGISTER

(A0h)

Data

x16

x8

READ LOCK REGISTER

X

Data

4, 5, 6

x16

PASSWORD PROTECTION Commands

ENTER PASSWORD

PROTECTION COMMAND

SET (60h)

x8

AAA

555

AA

555

55

AAA

555

60

3

7

x16

2AA

PROGRAM PASSWORD

(A0h)

x8

x16

x8

X

A0

PWAn PWDn

READ PASSWORD

00

PWD0

25

01

00

PWD1

03

02

00

PWD2 03 PWD3 … 07 PWD7 4, 6, 8,

9

x16

x8

PWD2 03 PWD3

UNLOCK PASSWORD (25h/

03h)

PWD0 01 PWD1 … 00

29

8, 10

x16

NONVOLATILE PROTECTION Commands

ENTER NONVOLATILE

PROTECTION COMMAND

SET (C0h)

x8

AAA

555

AA

555

55

AAA

555

C0

3

x16

2AA

PROGRAM NONVOLATILE

PROTECTION BIT (A0h)

x8

x16

x8

X

A0

BAd

00

11

READ NONVOLATILE

PROTECTION BIT STATUS

BAd READ(0)

4, 6,

11

x16

x8

CLEAR ALL NONVOLATILE

PROTECTION BITS (80/30h)

X

80

00

30

12

x16

NONVOLATILE PROTECTION BIT LOCK BIT Commands

ENTER NONVOLATILE

PROTECTION BIT LOCK BIT

COMMAND SET (50h)

x8

AAA

555

AA

555

55

AAA

555

50

3

x16

2AA

PROGRAM NONVOLATILE

PROTECTION BIT LOCK BIT

(A0h)

x8

X

A0

X

00

11

x16

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Block Protection Command Definitions – Address-Data Cycles

Table 14: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)

Notes 1 and 2 apply to entire table

Address and Data Cycles

1st

2nd

3rd

4th

nth

Command and

Code/Subcode

Bus

Size

A

D

A

D

A

D

A

D

…

A

D

Notes

READ NONVOLATILE

PROTECTION BIT LOCK BIT

STATUS

x8

X

READ(0)

4, 6,

11

x16

VOLATILE PROTECTION Commands

ENTER VOLATILE

PROTECTION COMMAND

SET (E0h)

x8

AAA

555

AA

555

55

AAA

555

E0

3

x16

2AA

PROGRAM VOLATILE

PROTECTION BIT (A0h)

x8

x16

x8

X

A0

BAd

00

11

4, 6

11

READ VOLATILE

PROTECTION BIT STATUS

BAd READ(0)

x16

x8

CLEAR VOLATILE

X

A0

BAd

01

PROTECTION BIT (A0h)

x16

EXTENDED MEMORY BLOCK Commands

ENTER EXTENDED

MEMORY BLOCK (88h)

x8

x16

x8

AAA

555

AA

555

2AA

555

55

AAA

555

88

90

3

EXIT EXTENDED

MEMORY BLOCK (90/00h)

AAA

555

AAA

555

X

00

x16

2AA

EXIT PROTECTION Commands

EXIT PROTECTION

COMMAND SET (90/00h)

x8

x16

X

90

X

00

3

1. Key: A = Address and D = Data; X = "Don’t Care;" BAd = any address in the block; PWDn

= password bytes 0 to 7; PWAn = password address, n = 0 to 7; Gray = not applicable. All

values in the table are hexadecimal.

Notes:

2. DQ[15:8] are "Don’t Care" during UNLOCK and COMMAND cycles. A[MAX:16] are

"Don’t Care" during UNLOCK and COMMAND cycles, unless an address is required.

3. The ENTER command sequence must be issued prior to any operation. It disables READ

and WRITE operations from and to block 0. READ and WRITE operations from and to

any other block are allowed. Also, when an ENTER COMMAND SET command is issued,

an EXIT PROTECTION COMMAND SET command must be issued to return the device to

READ mode.

4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven

LOW and data is read according to a specified address.

5. Data = Lock register content.

6. All address cycles shown for this command are READ cycles.

7. Only one portion of the password can be programmed or read by each PROGRAM PASS-

WORD command.

8. Each portion of the password can be entered or read in any order as long as the entire

64-bit password is entered or read.

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Block Protection Command Definitions – Address-Data Cycles

9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th

address cycle. From the 5th to the 8th address cycle, the values for each address and da-

ta pair continue the pattern shown in the table as follows: for x8, address and data = 04

and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.

10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the

11th address cycle. From the 5th to the 10th address cycle, the values for each address

and data pair continue the pattern shown in the table as follows: address and data = 02

and PWD2; 03 and PWD3; 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.

For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the

7th address cycle. For the 5th and 6th address cycles, the values for the address and data

pair continue the pattern shown in the table as follows: address and data = 02 and

PWD2; 03 and PWD3.

11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00;

Unprotected state= 01.

12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile pro-

tection bits before erasure. This prevents over-erasure of previously cleared nonvolatile

protection bits.

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Protection Operations

Blocks can be protected individually against accidental PROGRAM, ERASE, or READ op-

erations on both 8-bit and 16-bit configurations. The block protection scheme is shown

in the Software Protection Scheme figure.

Memory block and extended memory block protection is configured through the lock

register (see Lock Register section).

LOCK REGISTER Commands

After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all

bus READ or PROGRAM operations can be issued to the lock register.

The PROGRAM LOCK REGISTER (A0h) command allows the lock register to be config-

ured. The programmed data can then be checked with a READ LOCK REGISTER com-

mand by driving CE# and OE# LOW with the appropriate address data on the address

bus.

PASSWORD PROTECTION Commands

After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been

issued, the commands related to password protection mode can be issued to the device.

The PROGRAM PASSWORD (A0h) command is used to program the 64-bit password

used in the password protection mode. To program the 64-bit password, the complete

command sequence must be entered eight times at eight consecutive addresses selec-

ted by A[1:0] plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses

selected by A[1:0] in 16-bit mode. By default, all password bits are set to 1. The password

can be checked by issuing a READ PASSWORD command.

Note: To use the password protection feature on the 2Gb device, the password must be

programmed to both upper die and lower die.

The READ PASSWORD command is used to verify the password used in password pro-

tection mode. To verify the 64-bit password, the complete command sequence must be

entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1 in

8-bit mode, or four times at four consecutive addresses selected by A[1:0] in 16-bit

mode. If the password mode lock bit is programmed and the user attempts to read the

password, the device will output FFh onto the I/O data bus.

The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protec-

tion bit lock bit, allowing the nonvolatile protection bits to be modified. The UNLOCK

PASSWORD command must be issued, along with the correct password, and requires a

1μs delay between successive UNLOCK PASSWORD commands in order to prevent

hackers from cracking the password by trying all possible 64-bit combinations. If this

delay does not occur, the latest command will be ignored. Approximately 1μs is required

for unlocking the device after the valid 64-bit password has been provided.

NONVOLATILE PROTECTION Commands

After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has

been issued, the commands related to nonvolatile protection mode can be issued to the

device.

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Protection Operations

A block can be protected from program or erase by issuing a PROGRAM NONVOLATILE

PROTECTION BIT (A0h) command, along with the block address. This command sets

the nonvolatile protection bit to 0 for a given block.

The status of a nonvolatile protection bit for a given block or group of blocks can be

read by issuing a READ NONVOLATILE MODIFY PROTECTION BIT command, along

with the block address.

The nonvolatile protection bits are erased simultaneously by issuing a CLEAR ALL

NONVOLATILE PROTECTION BITS (80/30h) command. No specific block address is re-

quired. If the nonvolatile protection bit lock bit is set to 0, the command fails.

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Protection Operations

Figure 11: Program/Erase Nonvolatile Protection Bit Algorithm

Start

ENTER Nonvolatile

Protection

COMMAND SET

PROGRAM Nonvolatile

Protection Bit

Addr = BAd

Read byte twice

Addr = BAd

No

DQ6 = Toggle

Yes

No

DQ5 = 1

Yes

Wait 500µs

Read byte twice

Addr = BAd

No

Read byte twice

Addr = BAd

DQ6 = Toggle

Yes

DQ0 =

1 (erase)

0 (program)

No

Yes

Fail

Reset

Pass

EXIT PROTECTION

COMMAND SET

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Protection Operations

NONVOLATILE PROTECTION BIT LOCK BIT Commands

After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h)

command has been issued, the commands that allow the nonvolatile protection bit lock

bit to be set can be issued to the device.

The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to

set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection

bits and preventing them from being modified.

The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to

read the status of the nonvolatile protection bit lock bit.

VOLATILE PROTECTION Commands

After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been

issued, commands related to the volatile protection mode can be issued to the device.

The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a vola-

tile protection bit to 0 for a given block. If the nonvolatile protection bit for the same

block is set, the block is locked regardless of the value of the volatile protection bit. (See

the Block Protection Status table.)

The status of a volatile protection bit for a given block can be read by issuing a READ

VOLATILE PROTECTION BIT STATUS command along with the block address.

The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1)

the volatile protection bit for a given block. If the nonvolatile protection bit for the same

block is set, the block is locked regardless of the value of the volatile protection bit. (See

the Block Protection Status table.)

EXTENDED MEMORY BLOCK Commands

The device has one extra 128-word extended memory block that can be accessed only

by the ENTER EXTENDED MEMORY BLOCK (88h) command. The extended memory

block is 128 words (x16) or 256 bytes (x8). It is used as a security block to provide a per-

manent 128-bit security identification number or to store additional information. The

device can be shipped with the extended memory block prelocked permanently by Mi-

cron, including the 128-bit security identification number. Or, the device can be ship-

ped with the extended memory block unlocked, enabling customers to permanently

program and lock it. (See Lock Register, the AUTO SELECT command, and the Block

Protection table.)

Table 15: Extended Memory Block Address and Data

Address

x16

Data

x8

Micron prelocked

Customer Lockable

000000h–00000Fh 000000h–000007h

000010h–0000FFh 000008h–00007Fh

Secure ID number

Determined by customer

Secure ID number

Determined by customer

Protected and

unavailable

After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device

enters the extended memory block mode. All bus READ or PROGRAM operations are

conducted on the extended memory block, and the extended memory block is ad-

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Protection Operations

dressed using the addresses occupied by block 0 in the other operating modes (see the

Memory Map table).

In extended memory block mode, ERASE, CHIP ERASE, ERASE SUSPEND, and ERASE

RESUME commands are not allowed. The extended memory block cannot be erased,

and each bit of the extended memory block can only be programmed once.

The extended memory block is protected from further modification by programming

lock register bit 0. Once invoked, this protection cannot be undone.

The device remains in extended memory block mode until the EXIT EXTENDED MEM-

ORY BLOCK (90/00h) command is issued, which returns the device to read mode, or

until power is removed from the device. After a power-up sequence or hardware reset,

the device will revert to reading memory blocks in the main array.

EXIT PROTECTION Command

The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock

register, password protection, nonvolatile protection, volatile protection, and nonvola-

tile protection bit lock bit command set modes and return the device to read mode.

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Device Protection

Hardware Protection

The V_PP/WP# function provides a hardware method of protecting either the highest/

lowest block. When V_PP/WP# is LOW, PROGRAM and ERASE operations on either of

these block options is ignored to provide protection. When V_PP/WP# is HIGH, the de-

vice reverts to the previous protection status for the highest/lowest block or top/bottom

two blocks. PROGRAM and ERASE operations can modify the data in either of these

block options unless block protection is enabled.

Note: Micron highly recommends driving V_PP/WP# HIGH or LOW. If a system needs to

float the V_PP/WP# pin, without a pull-up/pull-down resistor and no capacitor, then an

internal pull-up resistor is enabled.

Table 16: V_PP/WP# Functions

V_PP/WP# Settings

Function

V_IL

Highest/lowest block is protected; for a 2Gb device, both the highest and the lowest blocks

are hardware-protected (block 0 and block 2047)

V_IH

Highest/lowest block or the top/bottom two blocks are unprotected unless software pro-

tection is activated.

Software Protection

Four software protection modes are available:

• Volatile protection

• Nonvolatile protection

• Password protection

• Password access

The device is shipped with all blocks unprotected. On first use, the device defaults to

the nonvolatile protection mode but can be activated in either the nonvolatile protec-

tion or password protection mode.

The desired protection mode is activated by setting either the nonvolatile protection

mode lock bit or the password protection mode lock bit of the lock register (see the Lock

Register section). Both bits are one-time-programmable and nonvolatile; therefore, af-

ter the protection mode has been activated, it cannot be changed, and the device is set

permanently to operate in the selected protection mode. It is recommended that the

desired software protection mode be activated when first programming the device.

For the lowest and highest blocks, a higher level of block protection can be achieved by

locking the blocks using nonvolatile protection mode and holding V_PP/WP# LOW.

Blocks with volatile protection and nonvolatile protection can coexist within the memo-

ry array. If the user attempts to program or erase a protected block, the device ignores

the command and returns to read mode.

The block protection status can be read by performing a read electronic signature or by

issuing an AUTO SELECT command (see the Block Protection table).

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Device Protection

Refer to the Block Protection Status table and the Software Protection Scheme figure for

details on the block protection scheme. Refer to the Protection Operations section for a

description of the command sets.

Volatile Protection Mode

Volatile protection enables the software application to protect blocks against inadver-

tent change and can be disabled when changes are needed. Volatile protection bits are

unique for each block and can be individually modified. Volatile protection bits control

the protection scheme only for unprotected blocks whose nonvolatile protection bits

are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE

PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and pla-

ces the associated blocks in the protected (0) or unprotected (1) state, respectively. The

volatile protection bit can be set or cleared as often as needed.

When the device is first shipped, or after a power-up or hardware reset, the volatile pro-

tection bits default to 1 (unprotected).

Nonvolatile Protection Mode

A nonvolatile protection bit is assigned to each block. Each of these bits can be set for

protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT com-

mand. Also, each device has one global volatile bit called the nonvolatile protection bit

lock bit; it can be set to protect all nonvolatile protection bits at once. This global bit

must be set to 0 only after all nonvolatile protection bits are configured to the desired

settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the

state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection

bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and

CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively.

No software command unlocks the nonvolatile protection bit lock bit unless the device

is in password protection mode; in nonvolatile protection mode, the nonvolatile protec-

tion bit lock bit can be cleared only by taking the device through a hardware reset or

power-up.

Nonvolatile protection bits cannot be cleared individually; they must be cleared all at

once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will re-

main set through a hardware reset or a power-down/power-up sequence.

If one of the nonvolatile protection bits needs to be cleared (unprotected), additional

steps are required: First, the nonvolatile protection bit lock bit must be cleared to 1, us-

ing either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be

changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit

must be set to 0 to lock the nonvolatile protection bits. The device now will operate nor-

mally.

To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT

command should be executed early in the boot code, and the boot code should be pro-

tected by holding V_PP/WP# LOW.

Nonvolatile protection bits and volatile protection bits have the same function when

V_PP/WP# is HIGH or when V_PP/WP# is at the voltage for program acceleration (V_PPH).

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Device Protection

Password Protection Mode

The password protection mode provides a higher level of security than the nonvolatile

protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit

lock bit. In addition to this password requirement, the nonvolatile protection bit lock

bit is set to 0 after power-up and reset to maintain the device in password protection

mode.

Executing the UNLOCK PASSWORD command by entering the correct password clears

the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to

be modified. If the password provided is incorrect, the nonvolatile protection bit lock

bit remains locked, and the state of the nonvolatile protection bits cannot be modified.

To place the device in password protection mode, the following two steps are required:

First, before activating the password protection mode, a 64-bit password must be set

and the setting verified. Password verification is allowed only before the password pro-

tection mode is activated. Next, password protection mode is activated by program-

ming the password protection mode lock bit to 0. This operation is irreversible. After the

bit is programmed, it cannot be erased, the device remains permanently in password

protection mode, and the 64-bit password can be neither retrieved nor reprogrammed.

In addition, all commands to the address where the password is stored are disabled.

Note: There is no means to verify the password after password protection mode is ena-

bled. If the password is lost after enabling the password protection mode, there is no

way to clear the nonvolatile protection bit lock bit.

Password Access

Password access is a security enhancement that protects information stored in the main

array blocks by preventing content alteration or reads until a valid 64-bit password is

received. Password access may be combined with nonvolatile and/or volatile protection

to create a multi-tiered solution. Contact your Micron sales representative for further

details.

Figure 12: Software Protection Scheme

Volatile protection bit

Nonvolatile protection bit

1 = unprotected (default)

1 = unprotected

0 = protected

(Default setting depends on the product order option)

Volatile

protection

Nonvolatile

protection

Nonvolatile protection bit lock bit (volatile)

Array block

1 = unlocked (default, after power-up or hardware reset)

0 = locked

Nonvolatile protection

mode

Password protection

mode

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Device Protection

1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection

bits are programmed individually and cleared collectively.

Notes:

2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by

taking the device through a power-up or hardware reset.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Common Flash Interface

The common Flash interface (CFI) is a JEDEC-approved, standardized data structure

that can be read from the Flash memory device. It allows a system's software to query

the device to determine various electrical and timing parameters, density information,

and functions supported by the memory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when necessary.

When the READ CFI command is issued, the device enters CFI query mode and the data

structure is read from memory. The following tables show the addresses (A-1, A[7:0])

used to retrieve the data. The query data is always presented on the lowest order data

outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0.

Table 17: Query Structure Overview

Note 1 applies to the entire table

Address

x16

10h

1Bh

27h

40h

x8

Subsection Name

Description

20h

36h

4Eh

80h

CFI query identification string

System interface information

Device geometry definition

Command set ID and algorithm data offset

Device timing and voltage information

Flash device layout

Primary algorithm-specific extended query table Additional information specific to the primary al-

gorithm (optional)

1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]

are set to 0.

Note:

Table 18: CFI Query Identification String

Note 1 applies to the entire table

Address

x16

10h

11h

12h

x8

Data Description

Value

"Q"

"R"

"Y"

–

20h

22h

24h

0051h Query unique ASCII string "QRY"

0052h

0059h

13h

14h

26h

28h

0002h Primary algorithm command set and control interface ID code 16-bit ID

0000h code defining a specific algorithm

15h

16h

2Ah

2Ch

0040h Address for primary algorithm extended query table (see the Primary Algo-

0000h rithm-Specific Extended Query Table)

P = 40h

17h

18h

2Eh

30h

0000h Alternate vendor command set and control interface ID code second ven-

0000h dor-specified algorithm supported

–

19h

1Ah

32h

34h

0000h Address for alternate algorithm extended query table

0000h

1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]

are set to 0.

Note:

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Common Flash Interface

Table 19: CFI Query System Interface Information

Note 1 applies to the entire table

Address

x16

x8

Data

Description

Value

1Bh

36h

0027h

V_CClogic supply minimum program/erase voltage

Bits[7:4] BCD value in volts

2.7V

Bits[3:0] BCD value in 100mV

1Ch

1Dh

1Eh

38h

3Ah

3Ch

0036h

00B5h

00C5h

V_CClogic supply maximum program/erase voltage

Bits[7:4] BCD value in volts

Bits[3:0] BCD value in 100mV

3.6V

11.5V

12.5V

V_PPH(programming) supply minimum program/erase voltage

Bits[7:4] hex value in volts

Bits[3:0] BCD value in 100mV

V_PPH(programming) supply maximum program/erase voltage

Bits[7:4] hex value in volts

Bits[3:0] BCD value in 10mV

1Fh

20h

21h

22h

3Eh

40h

42h

44h

0009h

000Ah

0012h

0013h

0014h

0015h

0001h

0002h

Typical timeout for single byte/word program = 2ⁿμs

Typical timeout for maximum size buffer program = 2ⁿμs

Typical timeout per individual block erase = 2ⁿms

Typical timeout for full chip erase = 2ⁿms

512µs

1024µs

1s

256Mb: 262s

512Mb: 524s

1Gb: 1048s

2Gb: 2097s

1024µs

23h

24h

25h

26h

46h

48h

4Ah

4Ch

Maximum timeout for byte/word program = 2ⁿtimes typical

Maximum timeout for buffer program = 2ⁿtimes typical

Maximum timeout per individual block erase = 2ⁿtimes typical

Maximum timeout for chip erase = 2ⁿtimes typical

4096µs

4s

256Mb: 1048s

512Mb: 2096s

1Gb: 4194s

2Gb: 8388s

1. The values in this table are valid for both packages.

Note:

Table 20: Device Geometry Definition

Address

x16

x8

Data

0019h

001Ah

001Bh

001Ch

Description

Device size = 2ⁿin number of bytes

Value

32MB

27h

4Eh

64MB

128MB

256MB

28h

29h

50h

52h

0002h

0000h

Flash device interface code description

x8, x16

asynchronous

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Common Flash Interface

Table 20: Device Geometry Definition (Continued)

Address

x16

x8

Data

Description

Value

2Ah

2Bh

54h

56h

000Ah

0000h

Maximum number of bytes in multi-byte program or page =

2ⁿ

1024¹

2Ch

58h

0001h

Number of erase block regions. It specifies the number of

regions containing contiguous erase blocks of the same size.

1

256

2Dh

2Eh

5Ah

5Ch

00FFh

0000h

Erase block region 1 information

Number of identical-size erase blocks = 00FFh + 1 / 01FFh +

1 / 03FFh + 1 / 07FFh + 1

00FFh

0001h

512

00FFh

0003h

1024

2048

128KB

0

00FFh

0007h

2Fh

30h

5Eh

60h

0000h

0002h

Erase block region 1 information

Block size in region 1 = 0200h × 256 bytes

31h

32h

33h

34h

62h

64h

66h

68h

0000h

Erase block region 2 information

Erase block region 3 information

Erase block region 4 information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

1. For x16/x8 mode, the maximum buffer size is 1024/256 bytes, respectively.

Note:

Table 21: Primary Algorithm-Specific Extended Query Table

Note 1 applies to the entire table

Address

x16

40h

41h

42h

43h

44h

45h

x8

Data

0050h

0052h

0049h

0031h

0033h

0018h

Description

Value

"P"

80h

82h

84h

86h

88h

8Ah

Primary algorithm extended query table unique ASCII string “PRI”

"R"

"I"

Major version number, ASCII

Minor version number, ASCII

"1"

"3"

Address sensitive unlock (bits[1:0]):

00 = Required

Required

01 = Not required

Silicon revision number (bits[7:2])

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Common Flash Interface

Table 21: Primary Algorithm-Specific Extended Query Table (Continued)

Note 1 applies to the entire table

Address

x16

x8

Data

Description

Value

46h

8Ch

0002h

Erase suspend:

2

00 = Not supported

01 = Read only

02 = Read and write

47h

48h

8Eh

90h

0001h

0000h

Block protection:

00 = Not supported

x = Number of blocks per group

1

Temporary block unprotect:

00 = Not supported

01 = Supported

Not supported

49h

4Ah

4Bh

92h

94h

96h

0008h

0000h

Block protect/unprotect:

08 = M29EWH/M29EWL

8

Simultaneous operations:

Not supported

–

Burst mode:

Not supported

00 = Not supported

01 = Supported

4Ch

98h

0003h

Page mode:

16-word page

00 = Not supported

01 = 8-word page

02 = 8-word page

03 = 16-word page

4Dh

4Eh

4Fh

9Ah

9Ch

9Eh

00B5h

00C5h

00xxh

V_PPHsupply minimum program/erase voltage:

Bits[7:4] hex value in volts

Bits[3:0] BCD value in 100mV

11.5V

12.5V

V_PPHsupply maximum program/erase voltage:

Bits[7:4] hex value in volts

Bits[3:0] BCD value in 100mV

Top/bottom boot block flag:

xx = 04h: Uniform device, HW protection for lowest block

xx = 05h: Uniform device, HW protection for highest block

Uniform +

V_PP/WP# protect-

ing highest or

lowest block

50h

A0h

0001h

Program suspend:

00 = Not supported

01 = Supported

Supported

1. The values in this table are valid for both packages.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Power-Up and Reset Characteristics

Table 22: Power-Up Specifications

Symbol

Parameter

Legacy

JEDEC

Min

0

Unit

µs

Notes

V_CCHIGH to V_CCQHIGH

–

^tVCHVCQH

^tVCHPH

^tVCQHPH

^tPHEL

1

2

V_CCHIGH to rising edge of RST#

V_CCQHIGH to rising edge of RST#

RST# HIGH to chip enable LOW

RST# HIGH to write enable LOW

^tVCS

^tVIOS

^tRH

300

0

µs

50

ns

–

^tPHWL

150

ns

1. V_CCand V_CCQramps must be synchronized during power-up.

Notes:

2. If RST# is not stable for ^tVCS or ^tVIOS, the device will not allow any READ or WRITE oper-

ations, and a hardware reset is required.

Figure 13: Power-Up Timing

^tVCHVCQH

V_CC

V_CCQ

^tRH

CE#

^tVIOS

RST#

^tVCS

WE#

^tPHWL

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Power-Up and Reset Characteristics

Table 23: Reset AC Specifications

Symbol

Legacy

Condition/Parameter

JEDEC

Min

Max

Unit

Notes

RST# LOW to read mode during program or

erase

^tREADY

^tPLRH

–

32

µs

1

RST# pulse width

^tRP

^tRH

^tRPD

^tPLPH

^tPHEL, ^tPHGL

–

100

50

–

ns

µs

RST# HIGH to CE# LOW, OE# LOW

RST# LOW to standby mode during read mode

1

10

RST# LOW to standby mode during program or

erase

50

RY/BY# HIGH to CE# LOW, OE# LOW

^tRB

^tRHEL, ^tRHGL

0

–

ns

1. Sampled only; not 100% tested.

Note:

Figure 14: Reset AC Timing – No PROGRAM/ERASE Operation in Progress

RY/BY#

CE#, OE#

t

RH

RST#

t

RP

Figure 15: Reset AC Timing During PROGRAM/ERASE Operation

t

READY

RY/BY#

t

RB

CE#, OE#

t

RH

RST#

t

RP

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Absolute Ratings and Operating Conditions

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions outside those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may ad-

versely affect reliability.

Table 24: Absolute Maximum/Minimum Ratings

Parameter

Symbol

T_BIAS

T_STG

Min

–50

Max

125

Unit

°C

V

Notes

1, 2

3

Temperature under bias

Storage temperature

Input/output voltage

Supply voltage

–65

150

V_IO

–0.6

V_CC+ 0.6

4

V_CC

V

Input/output supply voltage

Program voltage

V_CCQ

V_PPH

4

V

14.5

V

1. During signal transitions, minimum voltage may undershoot to −2V for periods less than

20ns.

Notes:

2. During signal transitions, maximum voltage may overshoot to V_CC+ 2V for periods less

than 20ns.

3. V_PPHmust not remain at 12V for more than 80 hours cumulative.

Table 25: Operating Conditions

Parameter

Symbol

Min

2.7

Max

3.6

Unit

V

Supply voltage

V_CC

V_CCQ

V_PP

T_A

C_L

Input/output supply voltage (V_CCQ≤ V_CC

)

1.65

–2.0

–40

3.6

V

Program voltage

12.5

85

V

Ambient operating temperature

Load capacitance

°C

pF

ns

V

30

Input rise and fall times

Input pulse voltages

–

10

–

0 to V_CCQ

V_CCQ/2

Input and output timing reference voltages

–

V

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Absolute Ratings and Operating Conditions

Figure 16: AC Measurement Load Circuit

V_CCQ

V_CC

25kΩ

Device

under

test

C

L

0.1µF

1. C_Lincludes jig capacitance.

Note:

Figure 17: AC Measurement I/O Waveform

V_CCQ

V_CCQ/2

0V

Table 26: Input/Output Capacitance

Parameter

Input capacitance for 256Mb and 512Mb

Input capacitance for 1Gb

Input capacitance for 2Gb

Output capacitance

Symbol

Test Condition

Min

Max

8

Unit

pF

C_IN

V_IN= 0V

3

4

8

3

9

pF

18

6

pF

C_OUT

V_OUT= 0V

pF

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

DC Characteristics

Table 27: DC Current Characteristics

Parameter

Symbol

Conditions

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

Min

Typ

–

Max

±1

Unit Notes

Input leakage current

Output leakage current

I_LI

–

µA

1

I_LO

–

±1

VCC read

current

Random read

I_CC1

CE# = V_IL, OE# = V_IH,

26

31

mA

f = 5 MHz

Page read

CE# = V_IL, OE# = V_IH,

–

12

16

mA

f = 13 MHz

VCC standby

current

256Mb

512Mb

1Gb

I_CC2

CE# = V_CCQ±0.2V,

RST# = V_CCQ±0.2V

–

65

70

210

225

240

480

50

µA

mA

75

2Gb

150

35

VCC program/erase/blank

check current

I_CC3

Program/

erase

V_PP/WP# = V_IL

or V_IH

2

controller

active

V_PP/WP# =

V_PPH

–

35

50

mA

V_PPcurrent

Read

I_PP1

V_PP/WP# ≤ V_CC

–

0.2

2

5

µA

Standby

Reset

15

I_PP2

I_PP3

RST# = V_SS±0.2V

V_PP/WP# = 12V ±5%

V_PP/WP# = V_CC

0.2

5

µA

PROGRAM operation

ongoing

0.05

0.10

mA

ERASE operation

ongoing

I_PP4

V_PP/WP# = 12V ±5%

V_PP/WP# = V_CC

1. The maximum input leakage current is ±5µA on the V_PP/WP# pin.

2. Sampled only; not 100% tested.

Notes:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

DC Characteristics

Table 28: DC Voltage Characteristics

Parameter

Input LOW voltage

Symbol

V_IL

Conditions

V_CC≥ 2.7V

I_OL= 100µA,

Min

–0.5

Typ

Max

0.8

Unit

V

Notes

–

Input HIGH voltage

Output LOW voltage

V_IH

0.7V_CCQ

–

V_CCQ+ 0.4

0.15V_CCQ

V

V_OL

V

V_CC= V_CC,min

,

V_CCQ= V_CCQ,min

Output HIGH voltage

V_OH

I_OH= 100µA,

0.85V_CCQ

–

V

V_CC= V_CC,min

V_CCQ= V_CCQ,min

–

,

Voltage for V_PP/WP# program

acceleration

V_PPH

V_LKO

11.5

2.3

–

12.5

–

V

Program/erase lockout supply

voltage

–

1

1. Sampled only; not 100% tested.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Read AC Characteristics

Table 29: Read AC Characteristics

Symbol

Legacy JEDEC

Parameter

Condition

Package

Min Max Unit Notes

Address valid to next address valid

^tRC

^tACC

^tPAGE

^tLZ

^tAVAV

^tAVQV

^tAVQV1

^tELQX

^tELQV

^tGLQX

^tGLQV

^tEHQZ

^tGHQZ

CE# = V_IL,

OE# = V_IL

Fortified BGA 100

–

ns

TSOP

Fortified BGA

TSOP

110

–

Address valid to output valid

CE# = V_IL,

OE# = V_IL

100

110

25

–

Address valid to output valid

(page)

CE# = V_IL,

OE# = V_IL

Fortified BGA

TSOP

–

CE# LOW to output transition

OE# = V_IL

CE# = V_IL

OE# = V_IL

CE# = V_IL

–

Fortified BGA

TSOP

0

–

1

–

CE# LOW to output valid

^tE

Fortified BGA

TSOP

100

110

–

OE# LOW to output transition

OE# LOW to output valid

CE# HIGH to output High-Z

OE# HIGH to output High-Z

^tOLZ

^tOE

Fortified BGA

TSOP

0

–

1

–

Fortified BGA

TSOP

25

20

15

–

^tHZ

Fortified BGA

TSOP

–

1

–

^tDF

Fortified BGA

TSOP

–

CE#, OE#, or address transition to

output transition

^tOH

^tEHQX,

^tGHQX,

^tAXQX

Fortified BGA

TSOP

0

–

CE# to BYTE# LOW

^tELFL

^tELFH

^tFLQV

^tFHQV

^tELBL

^tELBH

^tBLQV

^tBHQV

–

Fortified BGA

TSOP

–

10

1

ns

µs

CE# to BYTE# HIGH

Fortified BGA

TSOP

BYTE# LOW to output valid

BYTE# HIGH to output valid

Fortified BGA

TSOP

1

Fortified BGA

TSOP

1

1. Sampled only; not 100% tested.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Read AC Characteristics

Figure 18: Random Read AC Timing (8-Bit Mode)

t

RC

Valid

A[MAX:0]/A-1

CE#

t

ACC

OH

t

E

OH

t

LZ

t

HZ

OE#

t

OLZ

t

OH

t

OE

DF

DQ[7:0]

BYTE#

Valid

t

ELFL

Figure 19: Random Read AC Timing (16-Bit Mode)

t

RC

Valid

A[MAX:0]

t

ACC

OH

CE#

t

E

OH

t

LZ

HZ

OE#

t

OLZ

OH

t

OE

DF

Valid

DQ[15:0]

BYTE#

t

ELFH

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Read AC Characteristics

Figure 20: BYTE# Transition Read AC Timing

Valid

A[MAX:0]

A–1

Valid

t

ACC

OH

BYTE#

t

FHQV

Data-out

DQ[7:0]

DQ[15:8]

t

BLQX

High-Z

Figure 21: Page Read AC Timing (16-Bit Mode)

Valid

A[MAX:4]

Valid

^tACC

Valid

A[3:0]

CE#

^tE

^tOH

^tHZ

OE#

^tOE

^tPAGE

^tOH

^tDF

DQ[15:0]

Valid

1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus

mode and A[3:0] plus DQ15/A−1 in x8 bus mode.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Table 30: WE#-Controlled Write AC Characteristics

Parameter

Symbol

Package

Min

Typ

Max Unit

Notes

Legacy

JEDEC

Address valid to next address valid

CE# LOW to WE# LOW

^tWC

^tAVAV

Fortified BGA

TSOP

100

110

0

–

ns

µs

^tCS

^tELWL

^tWLWH

^tDVWH

^tWHDX

^tWHEH

^tWHWL

^tAVWL

^tWLAX

^tGHWL

^tWHGL

^tWHRL

^tVCHEL

^tWHWH1

Fortified BGA

TSOP

–

0

–

WE# LOW to WE# HIGH

Input valid to WE# HIGH

WE# HIGH to input transition

WE# HIGH to CE# HIGH

WE# HIGH to WE# LOW

Address valid to WE# LOW

WE# LOW to address transition

OE# HIGH to WE# LOW

WE# HIGH to OE# LOW

Program/erase valid to RY/BY# LOW

V_CCHIGH to CE# LOW

^tWP

Fortified BGA

TSOP

35

30

0

–

^tDS

Fortified BGA

TSOP

–

1

–

^tDH

Fortified BGA

TSOP

–

0

–

^tCH

Fortified BGA

TSOP

0

–

0

–

^tWPH

^tAS

Fortified BGA

TSOP

20

0

–

Fortified BGA

TSOP

–

0

–

^tAH

Fortified BGA

TSOP

45

0

–

Fortified BGA

TSOP

–

0

–

^tOEH

^tBUSY

^tVCS

^tWHWH1

Fortified BGA

TSOP

0

–

0

–

Fortified BGA

TSOP

–

30

–

2

–

Fortified BGA

TSOP

300

–

WRITE TO BUFFER PROGRAM opera-

tion (512 words)

Fortified BGA

TSOP

900

210

–

PROGRAM operation (single word or

byte)

Fortified BGA

TSOP

–

1. The user's write timing must comply with this specification. Any violation of this write

timing specification may result in permanent damage to the NOR Flash device.

Notes:

2. Sampled only; not 100% tested.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Figure 22: WE#-Controlled Program AC Timing (8-Bit Mode)

3rd Cycle 4th Cycle

Data Polling

READ Cycle

t

WC

AAAh

t

PA

A[MAX:0]/A-1

CE#

t

AS

AH

t

CH

t

E

CS

t

GHWL

OE

OE#

t

WP

WPH

WE#

t

DF

OH

t

WHWH1

t

DS

DQ[7:0]

AOh

DH

PD

DQ7#

D

OUT

t

1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-

GRAM command is followed by checking of the status register data polling bit and by a

READ operation that outputs the data (D_OUT) programmed by the previous PROGRAM

command.

Notes:

2. PA is the address of the memory location to be programmed. PD is the data to be pro-

grammed.

3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit

[DQ7]).

4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Figure 23: WE#-Controlled Program AC Timing (16-Bit Mode)

3rd Cycle 4th Cycle

Data Polling

READ Cycle

t

WC

555h

t

PA

A[MAX:0]

CE#

t

AS

AH

t

CH

t

E

CS

t

GHWL

OE

OE#

t

WP

WPH

WE#

t

^tWHWH1

DF

OH

t

DS

DQ[15:0]

Notes:

AOh

DH

PD

DQ7#

D

OUT

t

1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-

GRAM command is followed by checking of the status register data polling bit and by a

READ operation that outputs the data (D_OUT) programmed by the previous PROGRAM

command.

2. PA is the address of the memory location to be programmed. PD is the data to be pro-

grammed.

3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit

[DQ7]).

4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Table 31: CE#-Controlled Write AC Characteristics

Parameter

Address valid to next address valid

WE# LOW to CE# LOW

Symbol

Package

Min

Typ

Max

Unit Notes

Legacy

JEDEC

^tWC

^tWS

^tCP

^tAVAV

Fortified BGA

TSOP

100

110

0

–

ns

^tWLEL

^tELEH

^tDVEH

^tEHDX

^tEHWH

^tEHEL

^tAVEL

^tELAX

^tGHEL

Fortified BGA

TSOP

–

0

–

CE# LOW to CE# HIGH

Fortified BGA

TSOP

35

30

0

–

Input valid to CE# HIGH

CE# HIGH to input transition

CE# HIGH to WE# HIGH

CE# HIGH to CE# LOW

^tDS

^tDH

^tWH

^tCPH

^tAS

^tAH

–

Fortified BGA

TSOP

–

ns

µs

1

–

Fortified BGA

TSOP

–

0

–

Fortified BGA

TSOP

0

–

0

–

Fortified BGA

TSOP

20

0

–

Address valid to CE# LOW

CE# LOW to address transition

OE# HIGH to CE# LOW

Fortified BGA

TSOP

–

0

–

Fortified BGA

TSOP

45

0

–

Fortified BGA

TSOP

–

0

–

WRITE TO BUFFER PROGRAM opera-

tion (512 words)

^tWHWH1 ^tWHWH1

Fortified BGA

TSOP

–

900

210

–

PROGRAM operation (single word or

byte)

Fortified BGA

TSOP

–

1. The user's write timing must comply with this specification. Any violation of this write

timing specification may result in permanent damage to the NOR Flash device.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Figure 24: CE#-Controlled Program AC Timing (8-Bit Mode)

3rd Cycle 4th Cycle

Data Polling

PA

t

WC

WS

AAAh

t

PA

A[MAX:0]/A-1

WE#

t

AS

AH

t

WH

t

GHEL

OE#

CE#

t

CP

CPH

PD

t

WHWH1

DS

DQ[7:0]

AOh

DQ7#

D

OUT

t

DH

1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-

GRAM command is followed by checking of the status register data polling bit.

Notes:

2. PA is the address of the memory location to be programmed. PD is the data to be pro-

grammed.

3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit

[DQ7]).

4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Figure 25: CE#-Controlled Program AC Timing (16-Bit Mode)

3rd Cycle 4th Cycle

Data Polling

PA

t

WC

WS

A[MAX:0]

WE#

555h

t

PA

t

AS

AH

t

WH

t

GHEL

OE#

CE#

t

CP

CPH

PD

^tWHWH1

DQ7#

DS

DQ[15:0]

AOh

D

OUT

t

DH

1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-

GRAM command is followed by checking of the status register data polling bit.

Notes:

2. PA is the address of the memory location to be programmed. PD is the data to be pro-

grammed.

3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit

[DQ7]).

4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Write AC Characteristics

Figure 26: Chip/Block Erase AC Timing (8-Bit Mode)

t

WC

A[MAX:0]/

A–1

AAAh

BAh¹

AAAh

t

555h

AAAh

555h

t

AS

AH

t

CH

t

CS

CE#

t

GHWL

OE#

t

WP

WPH

55h

WE#

t

DS

t

10h/

30h

DQ[7:0]

Notes:

AAh

80h

AAh

55h

DH

1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE

command, the address is BAd, and the data is 30h.

2. BAd is the block address.

3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Accelerated Program, Data Polling/Toggle AC Characteristics

Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics

Symbol

Parameter

Legacy

JEDEC

^tVHVPP

^tAXGL

Min

250

15

Max

Unit

ns

V_PP/WP# rising or falling time

–

Address setup time to OE# LOW during toggle bit polling

Address hold time from OE# during toggle bit polling

CE# HIGH during toggle bit polling

^tASO

^tAHT

^tEPH

^tOEH

ns

^tGHAX, ^tEHAX

^tEHEL2

0

ns

30

ns

Output hold time during data and toggle bit polling

^tWHGL2,

^tGHGL2

20

ns

Program/erase valid to RY/BY# LOW

^tBUSY

^tWHRL

–

90

ns

1. Sampled only; not 100% tested.

Note:

Figure 27: Accelerated Program AC Timing

V_PPH

V_PP/WP#

V_ILor V_IH

^tVHVPP

Figure 28: Data Polling AC Timing

t

CH

E

HZ/ DF

CE#

t

OE

OE#

t

OEH

WE#

DQ7

Valid DQ7

Data

DQ7#

Valid

DQ[6:0] Data

Output flag

t

BUSY

RY/BY#

1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.

Notes:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Accelerated Program, Data Polling/Toggle AC Characteristics

2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-

gram and Data Polling/Data Toggle AC Characteristics.

Figure 29: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode)

A[MAX:0]/

A–1

t

AHT

ASO

CE#

WE#

OE#

t

OEH

AHT

AS

t

OEH

EPH

OEH

t

DH

Data

OE

E

Stop

toggling

Output

Valid

DQ6/DQ2

RY/BY#

Toggle

t

BUSY

1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops

toggling when the CHIP ERASE or BLOCK ERASE command has completed.

Notes:

2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-

gram and Data Polling/Data Toggle AC Characteristics.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Program/Erase Characteristics

Table 33: Program/Erase Characteristics

Notes 1 and 2 apply to the entire table.

Buffer

Size

Parameter

Byte

Word

Min

Typ

0.8

Max

4

Unit

s

Notes

Block erase (128KB)

Erase suspend latency time

Block erase timeout

–

27

32

µs

–

50

–

µs

Byte program

Single-byte program

–

210

270

310

375

4.22

2.42

1.46

210

270

310

375

505

900

8.44

4.84

2.93

1.97

1.76

27

456

716

900

1140

11.2

7

µs

Byte write to buffer program

64

128

256

64

128

256

–

64

128

256

1

–

µs

–

µs

–

µs

Effective write to buffer

program per byte

–

µs

1

–

µs

1

–

4.45

456

716

900

1140

1690

3016

22.4

14.1

8.9

6.6

5.89

32

µs

Word program Single-word program

Word write to buffer program

–

µs

32

64

128

256

512

32

64

128

256

512

–

32

64

128

256

512

1

–

µs

–

µs

–

µs

–

µs

–

µs

Effective write to buffer

program per word

–

µs

–

1

–

µs

–

1

–

µs

–

1

–

µs

–

1

–

µs

Program suspend latency time

–

µs

Blank check

–

100,000

–

3.2

–

ms

cycles

µs

PROGRAM/ERASE cycles (per block)

Erase to suspend

–

500

–

3

1. Typical values measured at room temperature and nominal voltages.

2. Typical and maximum values are sampled, but not 100% tested.

Notes:

3. Erase to suspend is the typical time between an initial BLOCK ERASE or ERASE RESUME

command and a subsequent ERASE SUSPEND command. Violating the specification re-

peatedly during any particular block erase may cause erase failures.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Package Dimensions

Figure 30: 56-Pin TSOP – 14mm x 20mm

20.00 ±0.20

18.40 ±0.10

Pin #1

0.50 TYP

14.00 ±0.10

0.22 ± 0.05

0.10 MIN/

0.21 MAX

1.00 ±0.05

+0.10

0.10

α

See Detail A

1.20 MAX

0.10

-0.05

0.50 ±0.10

3 TYP/

5 MAX

Detail A

1. All dimensions are in millimeters.

Notes:

2. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05.

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Package Dimensions

Figure 31: 64-Ball Fortified BGA – 11mm x 13mm

0.80 TYP

Seating

plane

0.10

64X

Ball A1 ID

8

7

6

5 4 3 2 1

3.00

TYP

A

B

C

D

E

13.00 ±0.10

7.00 TYP

F

G

H

1.00

TYP

1.00

TYP

0.60 ±0.05

2.00 TYP

1.40 MAX

0.49 TYP/

0.40 MIN

7.00 TYP

11.00 ±0.10

1. All dimensions are in millimeters.

Note:

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Additional Resources

Table 34: Technical Notes

Visit www.micron.com to access the following documents.

Reference

Number

Title

Password Protecting Flash Memory Blocks

TN-12-05

TN-13-12

TN-13-07

Software Driver for M29EW NOR Flash Memory

Patching the Linux Kernel and U-Boot for Micron® M29 Flash Memory

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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash

Revision History

Rev. B – 08/12

• Added Table 3: Part Numbers with Security Features by Density, Medium, and Pack-

age

• Updated Table 8: Operations and Corresponding Bit Settings

Rev. A – 04/12

• Initial Micron brand release

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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75


型号：	RC28F00BM29EWHA
厂家：	MICRON TECHNOLOGY
描述：	Parallel NOR Flash Embedded Memory 并行NOR闪存的嵌入式存储器闪存存储
文件：	总75页 (文件大小：855K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RC28F00BM29EWHA [MICRON]

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