7P096ATA2003I25 [MICROSEMI]
Flash Card, 48MX16, 250ns, CARD-68;
| 型号： | 7P096ATA2003I25 |
| 厂家： | 
Microsemi |
| 描述： | Flash Card, 48MX16, 250ns, CARD-68 内存集成电路 |
| 文件： | 总66页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
7PxxxATA20xxC25
TECHNICAL SPECIFICATIONS
ATA 20 SERIES FLASH CARDS
7P008ATA2003C25
8MB
7P016ATA2003C25 16MB
7P032ATA2003C25 32MB
7P048ATA2003C25 48MB
7P064ATA2003C25 64MB
7P080ATA2003C25 80MB
7P096ATA2003C25 96MB
7P112ATA2003C25 112MB
7P128ATA2003C25 128MB
7P160ATA2003C25 160MB
Description
Models 7P008ATA20, 7P016ATA20, 7P032ATA20, 7P048ATA20, 7P064ATA20, 7P080ATA20,
7P096ATA20, 7P112ATA20, 7P128ATA20 and 7P160ATA20 are Flash ATA cards. They comply with
the PC card ATA standard and are suitable for usage as a data storage memory medium for PCs or other
electronic equipment. These cards are built with Hitachi 64 Mb Flash memory devices HN29W6411. The
cards are suitable for the ISA (Industry Standard Architecture) bus interface standard. The read/write unit is
1 sector (512 bytes) sequential access.
Features
•
PC card ATA standard specification
68 pin two piece connector and type I (3.3 mm) or type II (5 mm) stainless steel housing
3.3 V/5 V single power supply operation
ISA standard and Read/Write unit is 512 bytes (sector) sequential access
Sector Read/Write transfer rate: 8MB/sec burst
High reliability based on internal ECC (Error Correcting Code) function
Maximum card density is 160MB
•
•
•
•
Cards are built with Hitachi 64 Mb Flash memory devices (HN29W6411A)
3 variations of mode access
Memory card mode
I/O card mode
True-IDE mode
•
•
•
•
•
•
Internal self-diagnostic program operates at VCC power on
High reliability based on wear leveling function
Data write endurance is 300,000 cycles (with approximately 500 kB DOS file)
Data reliability is 1 error in 1014 bits read.
Industrial temperature range version: -40°C to +85°C
Auto Sleep Function
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
Card Line Up
Card type
Card
Capacity (3)
Total sectors/ Sectors Number of Number of
density
card (2)
/ track
heads
cylinder
7P008ATA2003C25
8MB
8,060,928 Byte
16,121,856 Byte
32,243,712 Byte
48,365,568 Byte
64,487,424 Byte
80,609,280 Byte
96,731,136 Byte
112,852,992 Byte
128,974,848 Byte
161,218,560 Byte
15,744
32
2
246
7P016ATA2003C25 16MB
7P032ATA2003C25 32MB
7P048ATA2003C25 48MB
7P064ATA2003C25 64MB
7P080ATA2003C25 80MB
7P096ATA2003C25 96MB
7P112ATA2003C25 112MB
7P128ATA2003C25 128MB
7P160ATA2003C25 160MB
31,488
62,976
32
32
32
32
32
32
32
32
32
4
4
246
492
738
984
615
738
861
984
615
94,464
4
125,952
157,440
188,928
220,416
251,904
314,880
4
8
8
8
8
16
Notes: 1. Total tracks = number of head × number of cylinder.
2. Total sectors/card = sectors/track × number of head × number of cylinder.
3. It is the logical address capacity including the area which is used for file system.
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Card Pin Assignment
Memory card mode
Signal name I/O
I/O card mode
True IDE mode
Pin NO.
1
Signal name
GND
D3
I/O
—
I/O
I/O
I/O
I/O
I/O
I
Signal name
GND
D3
I/O
—
I/O
I/O
I/O
I/O
I/O
I
GND
D3
—
I/O
I/O
I/O
I/O
I/O
I
2
3
D4
D4
D4
4
D5
D5
D5
5
D6
D6
D6
6
D7
D7
D7
7
-CE1
A10
-OE
—
-CE1
A10
-OE
—
-CE1
A10
-ATASEL
—
8
I
I
I
9
I
I
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
—
I
—
I
—
I
A9
A9
A9
A8
I
A8
I
A8
I
—
—
—
I
—
—
—
I
—
—
—
I
—
—
—
-WE
RDY/-BSY
VCC
—
-WE
-IREQ
VCC
—
-WE
INTRQ
VCC
—
O
—
—
—
—
—
I
O
—
—
—
—
—
I
O
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
A7
A7
A7
A6
I
A6
I
A6
I
A5
I
A5
I
A5
I
A4
I
A4
I
A4
I
A3
I
A3
I
A3
I
A2
I
A2
I
A2
I
A1
I
A1
I
A1
I
A0
I
A0
I
A0
I
D0
I/O
I/O
I/O
O
—
—
D0
I/O
I/O
I/O
O
—
—
D0
I/O
I/O
I/O
O
—
—
D1
D1
D1
D2
D2
D2
WP
GND
GND
-IOIS16
GND
GND
-IOIS16
GND
GND
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Memory card mode
Signal name I/O
-CD1
I/O card mode
Signal name
-CD1
D11
True IDE mode
Signal name
-CD1
D11
Pin NO.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O
O
I/O
O
O
D11
D12
D13
D14
D15
-CE2
-VS1
-IORD
-IOWR
—
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
D12
D12
D13
D13
D14
D14
D15
D15
-CE2
-VS1
-IORD
-IOWR
—
-CE2
-VS1
-IORD
-IOWR
—
O
O
O
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
—
—
—
VCC
—
VCC
—
VCC
—
—
—
—
—
—
—
—
—
—
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
D8
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D8
-CSEL
-VS2
-RESET
IORDY
-INPACK
-REG
-DASP
-PDIAG
D8
O
O
O
I
I
I
O
O
O
O
O
O
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
D9
D9
D9
D10
-CD2
GND
D10
D10
-CD2
GND
-CD2
GND
—
—
—
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB
and A0 is LSB. In True IDE Mode only HA [2 : 0] are used for selecting the one of eight registers in the
Task File, the remaining address lines should be grounded.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the
Word. D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are
controlled by -CE1 and odd addresses are by -CE2. In True IDE Mode -CE2 is used for select the
Alternate Status Register and the Device Control Register while -CE1 is the chip select for the other task
file registers.
Output enable, ATA select (-OE, -ASTEL: input): -OE is used for the control of data read in Attribute
area or Common memory area. To enable True IDE Mode this input should be grounded by the host.
Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or
Common memory area. In True IDE Mode this input signal is not used and should be connected to VCC.
I/O read (-IORD: input): -IORD is used for control of read data in the Task File area. This card does
not respond to -IORD until I/O card interface setting up.
I/O write (-IOWR: input): -IOWR is used for control of data write in the Task File area. This card does
not respond to -IOWR until I/O card interface setting up.
Ready/Busy, Interrupt request (RDY/-BSY, -IREQ, INTRQ: output): In the I/O card mode, this signal
is -IREQ pin. The signal of low level indicates that the card is requesting software service to the host, and
high level indicates that the card is not requesting. In memory card mode, the signal is RDY/-BSY pin.
RDY/-BSY pin turns low level during the card internal initialization operation at VCC applied or reset
applied, so the next access to the card should be after the signal turns high level. In True IDE Mode signal
is the active high Interrupt Request to the host.
Card detection (-CD1, -CD2: output): -CD1 and -CD2 are the card detection signals. -CD1 and -CD2
are connected to ground in this card, so the host can detect if the card is inserted or not.
Write protect, 16 bit I/O port (WP, -IOIS16: output): In memory card mode, WP is held low because
this card does not have a write protect switch. In the I/O card mode, -IOIS16 is asserted when Task File
registers are accessed in 16-bit mode. In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
Attribute memory area selection (-REG: input): -REG should be high level during common memory
area accessing, and low level during Attribute area accessing. The attribute memory area is located only in
an even address, so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses
are invalid in the byte access mode. In True IDE Mode this input signal is not used and should be
connected to VCC.
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Battery voltage detection, Digital audio output, Disk active/slave present (BVD2, -SPKR, -DASP:
input/output): In memory card mode, BVD2 outputs the battery voltage status in the card. This card has
no battery, so this output is high level constantly. In the I/O card mode, -SPKR is held High because this
card does not have digital audio output. In True IDE Mode -DASP is the Disk Active/Slave Present signal
in the Master/Slave handshake protocol.
Reset (RESET, -RESET: input): By assertion of the RESET signal, all registers of this card are cleared
and the RDY/-BSY signal turns to high level. In True IDE Mode -RESET is the active low hardware reset
from the host.
Wait (-WAIT, IORDY: output): This signal outputs low level for the purpose of delaying memory access
cycle or I/O access cycle. In True IDE Mode this output signal may be used as IORDY. As for this
controller, this output is high impedance state constantly.
Input acknowledge (-INPACK: output): This signal is not used in the memory card mode. This signal
is asserted by this card when the card is selected and responding to an I/O read cycle at the address that is
on the address bus. This signal is used for the input data buffer control. In True IDE Mode this output
signal is not used and should be kept open at the host side.
Battery voltage detection, Status change, Pass diagnostic (BVD1, -STSCHG, -PDIAG: input/output):
In the memory card mode, BVD1 outputs the battery voltage status in the card. This card has no battery, so
this output is high level constantly. In the I/O card mode, -STSCHG is used for changing the status of the
Configuration status register in the Attribute area, while the card is set I/O card interface. In True IDE
Mode, -PDIAG is the Pass Diagnostic signal in the Master/Slave handshake protocol.
VCC voltage sense (-VS1, -VS2: output): These signals are intended to notify the socket of the PC Card's
CIS VCC requirement. -VS1 is held low and -VS2 is nonconnected in this card.
Card select (-CSEL: input): This signal is not used in the memory card mode and I/O card mode. This
internally pulled up signal is used to configure this device as a Master or a Slave when configured in the
True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open,
this device is configured as a Slave.
June 2000 Rev. 5 – ECO #12935
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Card Block Diagram
Internal Vcc
Vcc
GND
A0 to A10
Reset IC
-CE1, -CE2
-OE, -ATASEL
-WE
X’tal
-IORD
-IOWR
Flash
memory
bus
-REG
RESET/-RESET
-CSEL
HN29W6411A
D0 TO D15
WP/-IOIS16
Control signal
-INPACK
BVD1/STSCHG/-PDIAG
-WAIT/IORDY
VS1
VS2
OPEN
BVD2/-SPKR/-DASP
-CD1
-CD2
Note:
-CE1, -CE2, -OE, -WE, -IORD, -IOWR, -REG, RESET, -CSEL pins are pulled up in the card.
-PDIAG PIN IS Schmitt trigger type input output buffer.
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Card Function Explanation
Register Construction
•
Attribute region
Configuration register
•
•
•
•
Configuration Option register
Configuration and Status register
Pin Replacement register
Socket and Copy register
CIS (Card Information Structure)
•
Task File region
Data register
Error register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Drive Head register
Status register
Alternate Status register
Command register
Device Control register
Drive Address register
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Host Access Specifications
1. Attribute Access Specifications
When the CIS-ROM region or the Configuration register region is accessed, read and write operations are
executed under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/Odd-
byte modes which are defined by the PC card standard specifications.
Attribute Read Access Mode
Mode
-REG
-CE2
-CE1
A0
×
-OE
×
-WE
×
D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
High-Z
High-Z
High-Z
invalid
invalid
High-Z
L
L
H
even byte
invalid
L
H
×
L
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
L
H
even byte
High-Z
L
H
×
L
H
Attribute Write Access Mode
Mode
-REG
-CE2
-CE1
A0
×
-OE
×
-WE
D8 to D15 D0 to D7
Don’t care Don’t care
Don’t care even byte
Don’t care Don’t care
Don’t care even byte
Don’t care Don’t care
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
×
L
L
L
L
L
H
L
H
×
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
H
L
H
×
H
Attribute Access Timing Example
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
Dout
Din
D0 to D15
read cycle
write cycle
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
2. Task File Register Access Specifications
There are two cases of Task File register mapping, one is the mapped I/O address area, the other is the mapped
Memory address area. Each case of Task File register read and write operations is executed under the condition as
follows. That area can be accessed by Byte/Word/Odd Byte mode which is defined by the PC card standard
specifications.
(1) I/O address map
Task File Register Read Access Mode (1)
Mode
-REG -CE2 -CE1 A0
-IORD -IOWR -OE
-WE
×
D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
×
L
H
×
×
×
L
L
L
L
×
×
High-Z
High-Z
H
H
H
H
H
H
H
H
H
High-Z
even byte
odd byte
even byte
High-Z
L
H
High-Z
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
H
odd byte
odd byte
L
H
H
Task File Register Write Access Mode (1)
Mode
-REG -CE2 -CE1 A0
-IORD -IOWR -OE
-WE
×
D8 to D15 D0 to D7
Don’t care Don’t care
Don’t care even byte
Don’t care odd byte
Standby mode
Byte access (8-bit)
×
L
L
L
L
H
H
H
L
H
L
×
L
H
×
×
×
×
L
L
L
L
×
H
H
H
H
H
H
H
H
H
L
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
H
odd byte
odd byte
even byte
Don’t care
L
H
H
Task File Register Access Timing Example (1)
A0 to A10
-REG
-CE2/-CE1
-IORD
-IOWR
D0 to D15
Dout
Din
read cycle
write cycle
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
(2) Memory address map
Task File Register Read Access Mode (2)
Mode
-REG -CE2 -CE1 A0
-OE
×
-WE
×
-IORD -IOWR D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
H
H
H
L
H
L
×
L
H
×
×
×
×
High-Z
High-Z
H
H
H
H
L
H
H
H
H
H
H
H
H
H
High-Z
even byte
odd byte
even byte
High-Z
L
L
H
High-Z
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
L
H
odd byte
odd byte
L
H
L
H
Task File Register Write Access Mode (2)
Mode
-REG -CE2 -CE1 A0
-OE
×
-WE
-IORD -IOWR D8 to D15 D0 to D7
Standby mode
Byte access (8-bit)
×
H
H
H
L
H
L
×
L
H
×
×
×
L
L
L
L
×
×
Don’t care Don’t care
Don’t care even byte
Don’t care odd byte
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
Word access (16-bit)
Odd byte access (8-bit)
Note: ×: L or H
L
H
odd byte
odd byte
even byte
Don’t care
L
H
H
Task File Register Access Timing Example (2)
A0 to A10
-REG
-CE2/-CE1
-OE
-WE
Dout
Din
D0 to D15
read cycle
write cycle
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
3. True IDE Mode
The card can be configured in a True IDE Mode of operation. This card is configured in this mode only when the -OE
input signal is asserted low by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA
protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. In this
mode no Memory or Attribute Registers are accessible to the host. The card permits 8 bit access if the user issues a
Set Feature Command to put the device in the 8 bit Mode.
True IDE Mode Read I/O Function
Mode
-CE2
-CE1
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
Invalid mode
L
L
×
×
×
L
L
L
×
High-Z
High-Z
odd byte
High-Z
High-Z
High-Z
Standby mode
Data register access
All status access
Other task file access
Note: ×: L or H
H
H
L
H
L
×
×
High-Z
0
H
H
H
even byte
status out
data
H
L
6H
1-7H
H
True IDE Mode Write I/O Function
Mode
-CE2
-CE1
A0 to A2 -IORD
-IOWR
D8 to D15 D0 to D7
don’t care don’t care
don’t care don’t care
Invalid mode
L
L
×
×
×
×
L
L
L
Standby mode
H
H
L
H
L
×
×
Data register access
Control register access
Other task file access
Note: ×: L or H
0
H
H
H
odd byte
even byte
H
L
6H
1-7H
don’t care control in
don’t care data
H
True IDE Mode I/O Access Timing Example
A0 to A2
-CE
-IORD
-IOWR
-IOIS16
D0 to D15
Dout
Din
read cycle
write cycle
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Configuration Register Specifications
This card supports four Configuration registers for the purpose of the configuration and observation of this
card.
1. Configuration Option Register (Address 200H)
This register is used for the configuration of the card configuration status and for the issuing the soft reset
to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRESET
LevlREQ
INDEX
Note: initial value: 00H
Name
R/W Function
SRESET
(HOST->)
R/W Setting this bit to "1", places the card in the reset state (Card Hard Reset). This
operation is equal to Hard Reset, except this bit is not cleared. Then this bit is set to "0",
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so the next access to the card should be the same
sequence as the power on sequence.
LevlREQ
(HOST->)
R/W This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode
interrupt is selected.
INDEX
R/W This bit is used to select the operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose
of Memory card interface recognition.
(HOST->)
INDEX bit assignment
INDEX bit
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Card mode
Task File register address
Mapping mode
Memory card 0H to FH, 400H to 7FFH
memory mapped
I/O card
I/O card
I/O card
xx0H to xxFH
contiguous I/O mapped
primary I/O mapped
secondary I/O mapped
1F0H to 1F7H, 3F6H to 3F7H
170H to 177H, 376H to 377H
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2. Configuration and Status Register (Address 202H)
This register is used for observing the card state.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CHGED
SIGCHG
IOIS8
0
0
PWD
INTR
0
Note: initial value: 00H
Name
R/W Function
CHGED
R
This bit indicates that the CRDY/-BSY bit on the Pin Replacement register is set to "1".
When CHGED bit is set to "1", the -STSCHG pin is held "L" at the condition of SIGCHG
bit set to "1" and the card configured for the I/O interface.
(CARD->)
SIGCHG
R/W This bit is set or reset by the host for enabling and disabling the status-change signal (-
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -
STSCHG pin is controlled by the CHGED bit. If this bit is set to "0", the -STSCHG pin is
kept "H".
(HOST->)
IOIS8
R/W The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus
(D7 to D0).
(HOST->)
PWD
R/W When this bit is set to "1", the card enters the sleep state (Power Down mode). When
this bit is reset to "0", the card transfers to the idle state (active mode). RRDY/-BSY bit
on the Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-
BSY will not become Ready until the power state requested has been entered. This
card automatically powers down when it is idle, and powers back up when it receives a
command.
(HOST->)
INTR
R
This bit indicates the internal state of the interrupt request. This bit state is available
whether the I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
(CARD->)
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3. Pin Replacement Register (Address 204H)
This register is used for providing the signal state of the -IREQ signal when the card configured I/O card interface.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
CRDY/-BSY 0
1
1
RRDY/-BSY 0
Note: initial value: 0CH
Name
CRDY/-BSY R/W This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be
(HOST->) written by the host.
RRDY/-BSY R/W When read, this bit indicates +READY pin states. When written, this bit is used for
(HOST->) CRDY/-BSY bit masking.
R/W Function
4. Socket and Copy Register (Address 206H)
This register is used for identification of the card from the other cards. The host can read and write this
register. This register should be set by the host before this card's Configuration Option register set.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
DRV#
0
0
0
0
Note: initial value: 00H
Name
R/W Function
R/W This field is used for the configuration of the plural cards.
DRV#
(HOST->)
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CIS Information
CIS information is defined as follows. By reading the attribute address from "0000 H", the card CIS
information can be confirmed.
Address Data 7
6
5
4
3
2
1
0
Description of contents
Device info tuple
CIS function
Tuple code
000H 01H CISTPL DEVICE
002H 04H TPL_LINK
Link length is 4 bytes
Link to next tuple
004H DFH Device type
W Device speed Device type = DH: I/O device Device type, WPS, speed
P
WPS = 1: No WP
S
Device speed = 7: ext speed
006H 4AH EXT Speed
mantissa
Speed
400 ns if no wait
Extended speed
exponent
008H 01H 1x
2k units
2k byte of address space
End of device
Device size
END marker
00AH FFH List end marker
00CH 1CH CISTPL DEVICE OC
Other conditions device info Tuple code
tuple
00EH 04H TPL_LINK
Link length is 4 bytes
Link to next tuple
Other conditions info field
010H 02H EXT Reserved
012H D9H Device type
VCC
MWAI 3 V, wait is not used
T
W Device speed Device type = DH: I/O device Device type, WPS, speed
P
S
WPS = 1: No WP
Device speed = 1: 250 ns
014H 01H 1x
2k units
2k byte of address space
End of device
Device size
END marker
016H FFH List end marker
018H 18H CISTPL JEDEC C
01AH 02H TPL_LINK
JEDEC ID common memory Tuple code
Link length is 2 bytes Link to next tuple
01CH DFH PCMCIA’s manufacturer’s JEDEC Manufacturer’s ID code
ID code
JEDEC ID of PC Card ATA
01EH 01H PCMCIA JEDEC device code
020H 20H CISTPL MANFID
022H 04H TPL_LINK
2nd byte of JEDEC ID
Manufacturer’s ID code
Link length is 4 bytes
Tuple code
Link to next tuple
024H 07H Low byte of PCMCIA
manufacturer’s code
HITACHI JEDEC
manufacturer’s ID
Low byte of manufacturer’s
ID code
026H 00H High byte of PCMCIA
manufacturer’s code
Code of 0 because other byte High byte of manufacturer’s
is JEDEC 1 byte manufac ID ID code
028H 00H Low byte of product code
HITACHI code for PC CARD Low byte of product code
ATA
02AH 00H High byte of product code
High byte of product code
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
Tuple code
02CH 15H CISTPL_VER_1
02EH 15H TPL_LINK
Level 1 version/product info
Link length is 15h bytes
Link to next tuple
Major version
Minor version
Info string 1
030H 04H TPPLV1_MAJOR
032H 01H TPPLV1_MINOR
034H 48H
PCMCIA2.0/JEIDA4.1
PCMCIA2.0/JEIDA4.1
‘ H ’
036H 49H
‘ I ’
038H 54H
‘ T ’
03AH 41H
‘ A ’
03CH 43H
‘ C ’
03EH 48H
‘ H ’
040H 49H
‘ I ’
042H 00H
Null terminator
044H 46H
‘ F ’
Info string 2
046H 4CH
‘ L ’
048H 41H
‘ A ’
04AH 53H
‘ S ’
04CH 48H
‘ H ’
04EH 00H
Null terminator
‘ 4 ’
050H 34H
Vender specific strings
052H 2EH
‘ . ’
054H 30H
‘ 0 ’
056H 00H
Null terminator
End of device
Function ID tuple
Link length is 2 bytes
058H FFH List end marker
05AH 21H CISTPL FUNCID
05CH 02H TPL_LINK
END marker
Tuple code
Link to next tuple
05EH 04H TPLFID_FUNCTION = 04H
Disk function, may be silicon, PC card function code
may be removable
060H 01H Reserved
R
P
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Address Data 7
6
5
4
3
2
1
0
Description of contents
Function extension tuple
Link length is 2 bytes
Disk interface type
CIS function
062H 22H CISTPL FUNCE
064H 02H TPL_LINK
Tuple code
Link to next tuple
Extension tuple type for disk
066H 01H Disk function extension tuple
type
068H 01H Disk interface type
06AH 22H CISTPL FUNCE
06CH 03H TPL_LINK
PC card ATA interface
Function extension tuple
Link length is 3 bytes
Single drive
Interface type
Tuple code
Link to next tuple
Extension tuple type for disk
06EH 02H Disk function extension tuple
type
070H 0CH Reserved
D
U
S
V
No VPP, silicon, single drive
V = 0: No VPP required
S = 1: Silicon
Basic ATA option parameters
byte 1
U = 1: Unique serial #
D = 0: Single drive on card
072H 0FH
R
I
E
N
P3 P2 P1 P0
P0: Sleep mode supported
Basic ATA option parameters
P1: Standby mode supported byte 2
P2: Idle mode supported
P3: Drive auto power control
N: Some config excludes 3X7
E: Index bit is emulated
I: Twin IOIS16# data reg only
R: Reserved
074H 1AH CISTPL CONF
076H 05H TPL LINK
Configuration tuple
Tuple code
Link length is 5 bytes
Link to next tuple
078H 01H RFS
RMS
RAS
RFS: Reserved
Size of fields byte TPCC_SZ
RMS: TPCC_RMSK size - 1 = 0
RAS: TPCC_RADR size - 1 = 1
1 byte register mask
2 byte config base address
07AH 03H TPCC_LAST
Entry with config index of 03H Last entry of config registers
is final entry in table
07CH 00H TPCC RADR (LSB)
Configuration registers are
Location of config registers
located at 200 H in REG space
07EH 02H TPCC RADR (MSB)
080H 0FH Reserved
S
P
C
I
I: Configuration Index
C: Config. and Status
P: Pin Replacement
S: Socket and Copy
Configuration registers
present mask
TPCC_RMSK
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
082H 1BH CISTPL_CFTABLE ENTRY
084H 08H TPL_LINK
Configuration table entry tuple Tuple code
Link length is 8 bytes
Link to next tuple
086H C0H
I
D
Configuration index
Memory mapped I/O
configuration
Configuration table index
byte
I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 0
TPCE_INDX
088H C0H
W
R
P
B
Interface type
W = 1: Wait used
R = 1: Ready active
P = 0: WP used
Interface description field
TPCE_IF
B = 0: BVD1 and BVD2 not
used
IF type = 0: Memory interface
08AH A1H
08CH 01H
08EH 55H
M
R
X
MS
IR IO T
P
M = 1: Misc info present
Feature selection byte
MS = 01: Memory space info TPCE_FS
single 2-byte length
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
090H 08H Length in 256 bytes pages (LSB) Length of memory space is 2 Memory space description
kB
structures (TPCE MS)
092H 00H Length in 256 bytes pages (MSB)
094H 20H
X
R
P
R
O
A
T
X = 0: No more misc fields
R: Reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
096H 1BH CISTPL_CFTABLE ENTRY
098H 06H TPL_LINK
Configuration table entry tuple Tuple code
Link length is 6 bytes
Link to next tuple
09AH 00H
I
D
Configuration index
Memory mapped I/O
configuration
Configuration table index
byte
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 0
TPCE_INDX
09CH 01H
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
09EH 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0A0H B5H
0A2H 1EH
0A4H 4DH
X
X
X
Mantissa
Mantissa
Mantissa
Exponent
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
Max average current over 10 Max. average current
msec is 45 mA
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0A6H 1BH CISTPL_CFTABLE ENTRY
0A8H 0AH TPL_LINK
Configuration table entry tuple Tuple code
Link length is 10 bytes
Link to next tuple
0AAH C1H
I
D
Configuration INDEX
Contiguous I/O mapped ATA Configuration table index
registers configuration
I = 1: Interface byte follows
D = 1: Default entry
byte TPCE_INDX
Configuration index = 1
0ACH 41H
W
R
P
B
interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
0AEH 99H
M
R
MS
IR IO T
P
M = 1: Misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0B0H 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0B2H 55H
0B4H 64H
X
R
Mantissa
Exponent
Nominal voltage = 5 V
VCC nominal value
S
E
IO AddrLine
S = 1: 16-bit hosts supported I/O space description field
E = 1: 8-bit hosts supported TPCE_IO
IO AddrLine: 4 lines decoded
0B6H F0H
S
P
L
M V
B
I
N
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 1: Bit mask of IRQs
present
V = 0: No vender unique IRQ
B = 0: No bus error IRQ
I = 0: No IO check IRQ
N = 0: No NMI
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Address Data 7
0B8H FFH IRQ IR IR IR IR IR IR IRQ0 IRQ level to be routed 0 to 15 Mask extension byte 1
Q Q Q Q Q Q recommended TPCE_IR
6
5
4
3
2
1
0
Description of contents
CIS function
7
6
5
4
3
2
1
0BAH FFH IRQ IR IR IR IR IR IR IRQ8 Recommended routing to any Mask extension byte 2
15 Q Q Q Q Q Q
14 13 12 11 10 9
“normal, maskable” IRQ.
TPCE_IR
0BCH 20H
X
R
P
R
O
A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0BEH 1BH CISTPL_CFTABLE ENTRY
0C0H 06H TPL_LINK
Configuration table entry tuple Tuple code
Link length is 6 bytes
Link to next tuple
0C2H 01H
I
D
Configuration index
Contiguous I/O mapped ATA Configuration table index
registers configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 1
byte
TPCE_INDX
0C4H 01H
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0C6H 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0C8H B5H
0CAH 1EH
0CCH 4DH
X
X
X
Mantissa
Mantissa
Mantissa
Exponent
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
Max average current over 10 Max. average current
msec is 45 mA
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0CEH 1BH CISTPL_CFTABLE ENTRY
0D0H 0FH TPL_LINK
Configuration table entry tuple Tuple code
Link length is 15 bytes
Link to next tuple
0D2H C2H
I
D
Configuration INDEX
ATA primary I/O mapped
configuration
Configuration table index
byte TPCE_INDX
I = 1: Interface byte follows
D = 1: default entry follows
Configuration index = 2
0D4H 41H
W
R
P
B
interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
0D6H 99H
M
R
MS
IR IO T
P
M = 1: misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0D8H 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0DAH 55H
X
Mantissa
Exponent
Nominal voltage = 5 V
R = 1: Range follows
VCC nominal value
0DCH EAH R
S
E
IO AddrLine
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
0DEH 61H LS
AS
N range
LS = 1: Size of lengths is 1
byte
I/O range format description
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
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Address Data 7
0E0H F0H
0E2H 01H
0E4H 07H
0E6H F6H
0E8H 03H
0EAH 01H
0ECH EEH S
6
5
4
3
2
1
0
Description of contents
1st I/O base address (LSB)
1st I/O base address (MSB)
1st I/O length - 1
CIS function
1st I/O range address
1st I/O range length
2nd I/O base address (LSB) 2nd I/O range address
2nd I/O base address (MSB)
2nd I/O length - 1
2nd I/O range length
P
R
L
M IRQ level
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14
0EEH 20H
X
P
R
O
A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
0F0H 1BH CISTPL_CFTABLE ENTRY
0F2H 06H TPL_LINK
Configuration table entry tuple Tuple code
Link length is 6 bytes
Link to next tuple
0F4H 02H
I
D
Configuration index
ATA primary I/O mapped
configuration
Configuration table index
byte
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 2
TPCE_INDX
0F6H 01H
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
0F8H 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
0FAH B5H
0FCH 1EH
0FEH 4DH
X
X
X
Mantissa
Mantissa
Mantissa
Exponent
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
Max average current over 10 Max. average current
msec is 45 mA
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Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
100H 1BH CISTPL_CFTABLE ENTRY
102H 0FH TPL_LINK
Configuration table entry tuple Tuple code
Link length is 15 bytes
Link to next tuple
104H C3H
I
D
Configuration INDEX
ATA secondary I/O mapped Configuration table index
configuration
byte TPCE_INDX
I = 1: Interface byte follows
D = 1: default entry
Configuration index = 3
106H 41H
W
R
P
B
interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
Interface description field
TPCE_IF
IF type = 1: I/O interface
108H 99H
M
R
MS
IR IO T
P
M = 1: misc info present
Feature selection byte
MS = 00: No memory space TPCE_FS
info
IR = 1: Interrupt info present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
10AH 01H
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
10CH 55H
X
Mantissa
Exponent
Nominal voltage = 5 V
R = 1: Range follows
VCC nominal value
10EH EAH R
S
E
IO AddrLine
I/O space description field
S = 1: 16-bit hosts supported TPCE_IO
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
110H 61H LS
AS
N range
LS = 1: Size of lengths is 1
byte
I/O range format description
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
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Address Data 7
112H 70H
114H 01H
116H 07H
118H 76H
11AH 03H
11CH 01H
11EH EEH S
6
5
4
3
2
1
0
Description of contents
1st I/O base address (LSB)
1st I/O base address (MSB)
1st I/O length - 1
CIS function
1st I/O range address
1st I/O range length
2nd I/O base address (LSB) 2nd I/O range address
2nd I/O base address (MSB)
2nd I/O length - 1
2nd I/O range length
P
R
L
M IRQ level
S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
Interrupt request description
structure
TPCE_IR
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level isIRQ14
120H 20H
X
P
R
O
A
T
X = 0: No more misc fields
R: reserved
Miscellaneous features field
TPCE_MI
P = 1: Power down supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
122H 1BH CISTPL_CFTABLE ENTRY
124H 06H TPL_LINK
Configuration table entry tuple Tuple code
Link length is 6 bytes
Link to next tuple
126H 03H
I
D
Configuration index
ATA secondary I/O mapped Configuration table index
configuration
byte
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 3
TPCE_INDX
128H 01H
M
MS
IR IO T
P
M = 0: No Misc info
Feature selection byte
MS = 00: No Memory space TPCE_FS
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: VCC only info
12AH 21H
R
DI PI AI SI HV LV NV
Nominal voltage only follows Power parameters for VCC
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
12CH B5H
12EH 1EH
130H 4DH
X
X
X
Mantissa
Mantissa
Mantissa
Exponent
Exponent
Exponent
Nominal voltage = 3.0 V
+0.3 V
VCC nominal value
Extension byte
Max average current over 10 Max. average current
msec is 45 mA
132H 14H CISTPL_NO_LINK
134H 00H
No link control tuple
Link is 0 bytes
Tuple code
Link to next tuple
Tuple code
136H FFH CISTPL_END
End of list tuple
June 2000 Rev. 5 – ECO #12935
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Task File Register Specification
These registers are used for reading and writing the storage data in this card. These registers are mapped
four types by the configuration of INDEX in the Configuration Option register. The decoded addresses are
shown as follows.
Memory Map (INDEX = 0)
-REG A10 A9 to A4 A3
A2
0
0
0
0
1
1
1
1
0
0
1
1
1
×
×
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
×
×
A0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
Offset
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
DH
EH
FH
8H
9H
-OE = L
-WE = L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
0
1
1
1
1
1
×
×
Data register
Error register
Sector count register
Data register
Feature register
Sector count register
Sector number register Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Cylinder low register
Cylinder high register
Drive head register
Command register
Dup. even data register Dup. even data register
Dup. odd data register Dup. odd data register
Dup. error register
Alt. status register
Dup. feature register
Device control register
Drive address register Reserved
Even data register
Odd data register
Even data register
Odd data register
June 2000 Rev. 5 – ECO #12935
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Contiguous I/O Map (INDEX = 1)
-REG A10 to A4 A3
A2
0
0
0
0
1
1
1
1
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
1
0
1
Offset
0H
-IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
0
1
1
1
1
1
Data register
Data register
1H
Error register
Sector count register
Feature register
Sector count register
2H
3H
Sector number register Sector number register
4H
Cylinder low register
Cylinder high register
Drive head register
Status register
Cylinder low register
Cylinder high register
Drive head register
Command register
5H
6H
7H
8H
Dup. even data register Dup. even data register
Dup. odd data register Dup. odd data register
9H
DH
EH
FH
Dup. error register
Alt. status register
Drive address register
Dup. feature register
Device control register
Reserved
Primary I/O Map (INDEX = 2)
-REG A10 A9 to A4 A3
A2
0
A1
0
A0
0
-IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
3FH
3FH
0
0
0
0
0
0
0
0
0
0
Data register
Data register
0
0
1
Error register
Sector count register
Feature register
Sector count register
0
1
0
0
1
1
Sector number register Sector number register
1
0
0
Cylinder low register
Cylinder high register
Drive head register
Status register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
1
0
1
1
1
0
1
1
1
1
1
0
Alt. status register
Drive address register
1
1
1
June 2000 Rev. 5 – ECO #12935
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Secondary I/O Map (INDEX = 3)
-REG A10
A9 to A4 A3
A2
0
A1
0
A0
0
-IORD = L
-IOWR = L
0
0
0
0
0
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
17H
17H
17H
17H
17H
17H
17H
17H
37H
37H
0
0
0
0
0
0
0
0
0
0
Data register
Data register
0
0
1
Error register
Sector count register
Feature register
Sector count register
0
1
0
0
1
1
Sector number register Sector number register
1
0
0
Cylinder low register
Cylinder high register
Drive head register
Status register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
1
0
1
1
1
0
1
1
1
1
1
0
Alt. status register
Drive address register
1
1
1
True IDE Mode I/O Map
-CE2
-CE1
A2
0
A1
0
A0
0
-IORD = L
-IOWR = L
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Data register
Data register
0
0
1
Error register
Feature register
0
1
0
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Drive head register
Command register
Device control register
Reserved
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
Alt. status register
Drive address register
1
1
1
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
1. Data register: This register is a 16 bit register that has read/write ability, and it is used for transferring
1 sector data between the card and the host. This register can be accessed in word mode and byte mode.
This register overlaps the Error or Feature register.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D0 to D15
2. Error register: This register is a read only register, and it is used for analyzing the error content at the
card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are
set to "0" (Ready).
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BBK
UNC
“0”
IDNF
“0”
ABRT
“0”
AMNF
bit
7
Name
Function
BBK (Bad block detected)
UNC (Data ECC error)
This bit is set when a Bad Block is detected in requested ID field.
6
This bit is set when an uncorrectable error occurs when reading the
card.
4
2
IDNF (I D Not Found)
The requested sector ID is in error or cannot be found.
ABRT (ABoRTed command)
This bit is set if the command has been aborted because of the card
status condition. (Not ready, Write fault, Invalid command, etc.)
0
AMNF (Address Mark Not Found) This bit is set in case of a general error.
3. Feature register: This register is a write only register and provides information regarding features of
the drive which the host wishes to utilize.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Feature byte
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred
on a read or write operation between the host and the card. In this card, the plural sector transfer is
available across the Track or Cylinder. If the value of this register is zero, a count of 256 sectors is
specified. In the plural sector transfer, if not successfully completed, the register contains the number of
sectors which need to be transferred in order to complete the request. This register's initial value is "01H".
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector count byte
June 2000 Rev. 5 – ECO #12935
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5. Sector number register: This register contains the starting sector number which is started by following
a sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector number byte
6. Cylinder low register: This register contains the low 8 bits of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder low byte
7. Cylinder high register: This register contains the high 8 bits of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder high byte
8. Drive head register: This register is used for selecting the Drive of Master/Slave organization and
Head number for the following command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
LBA
1
DRV
Head number
bit
7
Name
1
Function
This bit is set to "1".
6
LBA
LBA is a flag to select either Cylinder / Head / Sector (CHS) or
Logical Block Address (LBA) mode. When LBA=0, CHS mode is
selected. When LBA=1, LBA mode is selected. In LBA mode, the
Logical Block Address is interrupted as follows:
LBA07-LBA00 : Sector Number Register D7-D0.
LBA15-LBA08 : Cylinder Low Register D7-D0.
LBA23-LBA16 : Cylinder High Register D7-D0.
LBA27-LBA24 : Drive / Head Register bits HS3-HS0.
5
4
1
This bit is set to "1".
DRV (DRiVe select)
This bit is used for selecting the Master (Card 0) and Slave (Card 1)
in Master/Slave organization. The card is set to be Card 0 or 1 by
using the DRV# of the Socket and Copy register.
3 to 0 Head number
This bit is used for selecting the Head number for the following
command. Bit 3 is MSB.
June 2000 Rev. 5 – ECO #12935
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9. Status register: This register is a read only register, and it indicates the card status of command
execution. Other bits are invalid when BSY bit is "1". When this register is read, -IREQ is negated. When
the host writes the command code to Command register, bits 0, 4 and 6 are cleared and bit 7 is set.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
bit
Name
BSY (BuSY)
Function
7
This bit is set when the card internal operation is executing. When
this bit is set to "1", other bits in this register are invalid.
6
DRDY (Drive ReaDY)
If this bit and DSC bit are set to "1", the card is capable of receiving
the read or write or seek requests. If this bit is set to "0", the card
prohibits these requests.
5
4
3
DWF (Drive Write Fault)
DSC (Drive Seek Complete)
DRQ (Data ReQuest)
This bit is set if this card indicates the write fault status.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred between the
host and Data register. This bit is cleared when the card receives
the other command.
2
CORR (CORRected data
This bit is set when a correctable data error has occurred and the
data has been corrected.
1
0
IDX (InDeX)
This bit is always set to "0".
ERR (ERRor)
This bit is set when the previous command has ended in some type
of error. The error information is set in the other Status register or
Error register. This bit is cleared by the next command.
10. Alternate status register: This register is the same as the Status register physically, so the bit
assignment refers to a previous item of Status register. But this register is different from the Status register
that -IREQ is not negated when data is read.
11. Command register: This register is a write only register, and it is used for writing the command at
executing the drive operation. The command code written in the command register, after the parameter is
written in the Task File during the card, is Ready state.
June 2000 Rev. 5 – ECO #12935
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Used parameter
Command
Command code
E5H or 98H
90H
FR
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
SC
N
N
Y
Y
N
Y
N
Y
N
Y
N
Y
Y
N
N
N
N
Y
N
N
N
Y
N
N
N
Y
Y
Y
Y
Y
SN
N
N
Y
N
N
N
N
N
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
CY
N
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
DR
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
N
N
Y
Y
N
N
N
Y
N
Y
Y
Y
Y
N
N
Y
N
N
N
N
N
Y
Y
N
Y
Y
Y
Y
Y
Y
LBA
N
N
Y
Check power mode
Execute drive diagnostic
Erase sector
C0H
Format track
50H
Y
Identify Drive
ECH
N
N
N
N
N
Y
Idle
E3H or 97H
E1H or 95H
91H
Idle immediate
Initialize drive parameters
Read buffer
E4H
Read multiple
Read long sector
Read sector
C4H
22H or 23H
20H or 21H
40H or 41H
1XH
Y
Y
Read verify sector
Recalibrate
Y
N
N
Y
Request sense
Seek
03H
7XH
Set features
EFH
N
N
N
N
N
Y
Set multiple mode
Set sleep mode
Stand by
C6H
N
N
N
N
N
N
N
N
N
N
N
N
N
E6H or 99H
E2H or 96H
E0H or 94H
87H
Stand by immediate
Translate sector
Wear level
F5H
N
N
Y
Write buffer
E8H
Write long sector
Write multiple
Write multiple w/o erase
Write sector
32H or 33H
C5H
Y
CDH
Y
30H or 31H
38H
Y
Write sector w/o erase
Write verify
Y
3CH
Y
Note: FR: Feature register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Y: The register contains a valid parameter for this command.
N: The register does not contain a valid parameter for this command.
June 2000 Rev. 5 – ECO #12935
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12. Device control register: This register is a write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
1
SRST
nIEN
0
bit
Name
Function
7 to 4 ×
don't care
3
2
1
This bit is set to "1".
SRST (Software ReSeT)
This bit is set to "1" in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".
1
0
nIEN (Interrupt ENable)
0
This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ
is enabled. When this bit is set to "1", -IREQ is disabled.
This bit is set to "0".
13. Drive Address register: This register is a read only register, and it is used for confirming the drive
status. This register provides for compatibility with the AT disk drive interface. It is recommended that
this register not be mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
bit
7
Name
Function
×
This bit is unknown
This bit is unknown
6
nWTG (WriTing Gate)
5 to 2 nHS3-0 (Head Select3-0)
These bits are the negative value of Head Select bits (bit 3 to 0) in
theDrive/Head register.
1
0
nDS1 (Idrive Select1)
nDS0 (Idrive Select0)
This bit is unknown
This bit is unknown
June 2000 Rev. 5 – ECO #12935
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ATA Command Specifications
This table summarizes the ATA command set with the paragraphs. The following shows the support
commands and command codes which are written in the command registers.
June 2000 Rev. 5 – ECO #12935
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ATA Command Set
No.
1
Command set
Check power mode
Execute drive diagnostic
Erase sector(s)
Format track
Code
FR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
SC
—
—
Y
SN
—
—
Y
CY
—
—
Y
DR
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
—
—
Y
LBA
—
—
Y
E5H or 98H
90H
2
3
C0H
4
50H
Y
—
—
—
—
—
—
Y
Y
Y
Y
5
Identify Drive
ECH
—
Y
—
—
—
—
—
Y
—
—
—
Y
—
—
—
—
—
Y
6
Idle
E3H or 97H
E1H or 95H
91H
7
Idle immediate
Initialize drive parameters
Read buffer
—
Y
8
9
E4H
—
Y
—
Y
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Read multiple
C4H
Read long sector
Read sector (s)
Read verify sector (s)
Recalibrate
22H, 23H
20H, 21H
40H, 41H
1XH
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
Y
—
—
Y
—
—
Y
—
—
Y
—
—
Y
Request sense
Seek
03H
7XH
Set features
EFH
—
—
—
—
—
Y
—
—
—
—
—
Y
—
—
—
—
—
Y
—
—
—
—
—
Y
Set multiple mode
Set sleep mode
Stand by
C6H
—
—
—
—
—
—
—
—
—
—
—
—
—
E6H or 99H
E2H or 96H
E0H or 94H
87H
—
—
—
Y
Stand by immediate
Translate sector
Wear level
F5H
—
—
—
Y
—
—
Y
—
—
Y
Y
—
—
Y
Write buffer
E8H
—
Y
Write long sector
Write multiple
32H or 33H
C5H
Y
Y
Y
Y
Write multiple w/o erase
Write sector
CDH
Y
Y
Y
Y
Y
30H or 31H
38H
Y
Y
Y
Y
Y
Write sector(s) w/o erase
Write verify
Y
Y
Y
Y
Y
3CH
Y
Y
Y
Y
Y
Note: FR: Feature Register
SC: Sector Count register
(00H to FFH)
SN: Sector Number register (01H to 20H)
CY: Cylinder Low/High register (to)
DR: Drive bit of Drive/Head register
HD: Head No.(0 to 3) of Drive/Head register
NH: No. of Heads
Y: Set up
—: Not set up
June 2000 Rev. 5 – ECO #12935
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1. Check Power Mode (code: E5H or 98H): This command checks the power mode.
2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests
implemented by the Card.
3. Erase Sector(s) (code: C0H): This command is used to pre-erase and condition data sectors in advance
of a Write without Erase or Write Multiple without Erase command.
4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive
but the selected sector data is not exchanged. This card accepts a sector buffer of data from the host to
follow the command with same protocol as the Write Sector Command.
5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the
Card.
Identify Drive Information
Word address Default value Total bytes Data field type information
0
848AH
XXXX
0000H
00XXH
0000H
XXXX
XXXX
XXXX
0000H
XXXX
0002H
0002H
0004H
XXXX
0001H
0000H
0200H
2
General configuration bit-significant information
Default number of cylinders
1
2
2
2
Reserved
3
2
Default number of heads
4
2
Number of unformatted bytes per track
Number of unformatted bytes per sector
Default number of sectors per track
Number of sectors per card (Word7 = MSW, Word8 = LSW)
Reserved
5
2
6
2
7 to 8
9
4
2
10 to 19
20
20
2
Reserved
Buffer type (dual ported)
21
2
Buffer size in 512 byte increments
# of ECC bytes passed on Read/Write Long Commands
Firmware revision in ASCII etc.
Maximum of 1 sector on Read/Write Multiple command
Double Word not supported
22
2
23 to 46
47
48
2
48
2
49
2
Capabilities: DMA NOT Supported (bit 8), LBA supported
(bit9)
50
0000H
0100H
0000H
XXXX
010XH
XXXX
0000H
2
Reserved
51
2
PIO data transfer cycle timing mode 1
DMA data transfer cycle timing mode not Supported
Reserved
52
2
53 to 58
59
12
2
Multiple sector setting is valid
Total number of sectors addressable in LBA Mode
Reserved
60 to 61
62 to 255
4
388
June 2000 Rev. 5 – ECO #12935
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6. Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY
and generate an interrupt. If the sector count is non-zero, the automatic power down mode is enabled.
If the sector count is zero, the automatic power down mode is disabled.
7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read)
mode, clear BSY and generate an interrupt.
8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors
per track and the number of heads per cylinder.
9. Read Buffer (code: E4H): This command enables the host to read the current contents of the card's
sector buffer.
10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command.
Interrupts are not generated on each sector, but on the transfer of a block which contains the number of
sectors defined by a Set Multiple command.
11. Read Long Sector (code: 22H or 23H): This command performs similarly to the Read Sector(s)
command except that it returns 516 bytes of data instead of 512 bytes.
12. Read Sector(s) (code: 20H, 21H): This command reads from 1 to 256 sectors as specified in the
Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector
specified in the Sector Number register.
13. Read Verify Sector (code: 40H or 41H): This command is identical to the Read Sectors command,
except that DRQ is never set and no data is transferred to the host .
14. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided
for compatibility purposes.
15. Request Sense (code: 03H): This command requests an extended error code after a command ends
with an error.
16. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does
perform a range check.
17. Set Features (code: EFH): This command is used by the host to establish or select certain features.
Feature
01H
Operation
Enable 8-bit data transfers.
55H
Disable Read Look Ahead.
66H
Disable Power on Reset (POR) establishment of defaults at Soft Reset.
Enable 8-bit data transfers.
81H
BBH
CCH
4 bytes of data apply on Read/Write Long commands.
Enable Power on Reset (POR) establishment of defaults at Soft Reset.
18. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple
operations and establishes the block count for these commands.
19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep
mode, clear BSY and generate an interrupt.
20. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode
(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
21. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep
mode(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt
immediately.
22. Translate Sector (code: 87H): This command allows the host a method of determining the exact
number of times a user sector has been erased and programmed.
23. Wear Level (code: F5H): This command is effectively a NOP command and is only implemented for
backward compatibility.
24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card's sector
buffer with any data pattern desired.
25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is
similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.
26. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are
not presented on each sector, but on the transfer of a block which contains the number of sectors
defined by Set Multiple command.
27. Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command
with the exception that an implied erase before write operation is not performed.
28. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the
Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector
specified in the Sector Number register.
29. Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command
with the exception that an implied erase before write operation is not performed.
30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each
sector is verified immediately after being written.
June 2000 Rev. 5 – ECO #12935
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Sector Transfer Protocol
1. Sector read: 1 sector read procedure after the card configured I/O interface is shown as follows.
Start
I/O Access index = 1
Set the cylinder low / high register
Set the head No. of drive head register
(1) Set the logical sector number
Set the sector number register
Set “01H” in sector count register
Set “20H” in command register
(2)
Read Status register
(3)
58H
Read 256 times the data (512 bytes)
(4) Burst data transfer
Read Status register
50H
(5)
Wait the command input
(1)
4H 5H 6H 3H 2H 7H
(2)
(3)
(4)
(5)
7H
7H
0H
0H
7H 7H
A0 to A10
-CE1
-CE2
-IOWR
-IORD
01H20H 80H
58H (Transfer data)
80H
50H
D0 to D15
-IREQ
June 2000 Rev. 5 – ECO #12935
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2. Sector write: 1 sector write procedure after the card configured I/O interface is shown as follows.
Start
I/O Access index = 1
Set the cylinder low / high register
Set the head No. of drive head register
(1) Set the logical sector number
Set the sector number register
Set “01H” in sector count register
Set “30H” in command register
(2)
Read Status register
(3)
58H
Write 256 times the data (512 bytes)
(4) Burst data transfer
Read Status register
50H
(5)
Wait the command input
(1)
4H 5H 6H 3H 2H 7H
(2)
(3)
(4)
(5)
7H
7H
0H
0H
7H 7H
A0 to A10
-CE1
-CE2
-IOWR
-IORD
01H30H 80H
58H (data Transfer)
80H
50H
D0 to D15
-IREQ
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Absolute Maximum Ratings
Parameter
Symbol
Vin, Vout
VCC
Value
Unit
V
Note
All input/output voltages
VCC voltage
–0.3 to VCC + 0.3
–0.3 to +6.5
0 to +60
-40 to +85
–20 to +65
-40 to +85
1
V
Operating temperature range Commercial
Industrial
Topr
°C
Storage temperature range
Commercial
Industrial
Tstg
°C
Note: 1. Vin, Vout min = –2.0 V for pulse width ≤ 20 ns.
Recommended DC Operating Conditions
Voltage reference to GND, Commercial Ta =0 to 65C , industrial Ta=-40 to +85C
Parameter
Operating
temperature
VCC voltage
Symbol
Min
0
-40
4.5
3.15
Typ
Max
+60
+85
5.5
Unit
Note
Commercial
Industrial
Ta
25
°C
VCC
5.0
3.3
V
V
3.45
Capacitance (Ta = 25°C, f = 1MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
Unit
pF
Test conditions
Vin = 0 V
Input capacitance
Output capacitance
35
35
Cout
—
—
pF
Vout = 0 V
System Performance
Item
Performance
100 ms (max)
2 ms (max)
Start up times (Reset to ready)
Start up times (Sleep to idle)
Data transfer rate to/from host
8 MB/s burst
2 ms (max)
Controller overhead (Command to DRQ)
Data transfer cycle end to ready (Sector write)
1.2 ms (typ)
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
DC Characteristics-1
(Commercial Ta = 0 to +60°C, VCC = 5.0 V ± 10%)
(Industrial Ta = -40 to +85°C, VCC = 5.0 V ± 10%)
Parameter
Symbol Min
Typ
Max
± 1
0.8
—
Unit Test conditions
Note
Input leakage current
Input voltage (CMOS)
ILI
—
—
4.0
—
—
—
—
µA
V
Vin = GND to VCC
1
VIL
VIH
—
—
V
Input voltage (schmitt trigger) VIL
VIH
2.0
2.8
—
—
V
—
V
Output voltage
VOL
VOH
0.4
—
V
IOL = 8 mA
VCC – 0.8 —
V
IOH = –8 mA
Note: 1. Except pulled up input pin.
DC Characteristics-2
(Ta = 0 to +60°C, VCC = 3.3 V ± 5%)
(Ta = -40 to +85°C, VCC = 3.3 V ± 5%)
Parameter
Symbol Min
Typ
Max
± 1
0.6
—
Unit Test conditions
Note
Input leakage current
Input voltage (CMOS)
ILI
—
—
2.4
—
—
—
—
µA
V
Vin = GND to VCC
1
VIL
VIH
—
—
V
Input voltage (schmitt trigger) VIL
VIH
1.0
1.8
—
—
V
—
V
Output voltage
VOL
VOH
0.4
—
V
IOL = 8 mA
VCC – 0.8 —
V
IOH = –8 mA
Note: 1. Except pulled up input pin.
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
DC Characteristics-3
(Ta = 0 to +60°C, VCC = 5.0 V ± 10%)
(Industrial Ta = -40 to +85°C, VCC = 5.0 V ± 10%)
8MB/16MB 64MB/80MB 112MB/128
32MB/48MB 96MB
MB/150MB
Parameter
Symbol
Typ Max
Typ Max
Typ Max
Unit Test conditions
Sleep/standby ISP1
current
0.5 1.0
0.7 1.5
1.0 2.0
mA CMOS level (control signal =
VCC – 0.2 V in Memory Card
Mode and I/O Card Mode)
Sector read ICCR (DC)
current
40 75
40 75
40 75
mA CMOS level (control signal =
VCC – 0.2 V) during sector read
transfer
ICCR (Peak) 80 120
80 120
45 75
80 120
45 75
Sector write ICCW (DC)
current
45 75
mA CMOS level (control signal =
VCC – 0.2 V) during sector write
transfer
ICCW (Peak) 80 120
80 120
80 120
DC Characteristics-4 (Ta = 0 to +60°C, VCC = 3.3 V ± 5%)
(Ta = -40 to +85°C, VCC = 3.3 V ± 5%)
8MB/16MB 64MB/80MB 112MB/128
32MB/48MB 96MB
MB/160MB
Parameter
Symbol
Typ Max
Typ Max
Typ Max
Unit Test conditions
Sleep/standby ISP1
current
0.3 0.6
0.4 0.8
0.5 1.0
mA CMOS level (control signal =
V
CC – 0.2 V in Memory Card
Mode and I/O Card Mode)
Sector read ICCR (DC)
current
25 50
25 50
25 50
mA CMOS level (control signal =
VCC – 0.2 V) during sector read
transfer
ICCR (Peak) 50 80
50 80
25 50
50 80
25 50
Sector write ICCW (DC)
current
25 50
mA CMOS level (control signal =
V
CC – 0.2 V) during sector write
transfer
ICCW (Peak) 50 80
50 80
50 80
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
DC Current Waveform (Example of sector read or write: VCC = 5 V, Ta = 25°C)
Power on Operation (Reference only)
DC
Time
Power on
June 2000 Rev. 5 – ECO #12935
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Sector Read
ICCR(peak)
ICCR(DC)
Time
Complete of sector read
Command write
Sector Write
ICCW(peak)
ICCW(DC)
Time
Command write
Complete of sector write
June 2000 Rev. 5 – ECO #12935
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AC Characteristics (Commercial Ta=0 to +60°C, VCC = 5 V ± 10%, VCC = 3.3 V ±5%)
(Industrial Ta= -40 to +85°C, VCC = 5.0 V ± 10%, VCC = 3.3 V ±5%)
Attribute Memory Read AC Characteristics
250 ns
Parameter
Symbol
Min
250
—
—
—
—
—
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tCR
Address access time
-CE access time
ta(A)
250
250
125
100
100
—
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
-OE access time
Output disable time (-CE)
Output disable time (-OE)
Output enable time (-CE)
Output enable time (-OE)
Data valid time (A)
Address setup time
Address hold time
-CE setup time
5
—
0
—
tsu(A)
th(A)
30
20
0
—
—
tsu(CE)
th(CE)
—
-CE hold time
20
—
Attribute Memory Read Timing
June 2000 Rev. 5 – ECO #12935
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White Electronic Designs Corporation • (508) 366-5151
7PxxxATA20xxC25
Attribute Memory Write AC Characteristics
250 ns
Min
250
150
30
Parameter
Symbol
tCW
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse time
tw(WE)
tsu(A)
—
Address setup time
Address setup time (-WE)
-CE setup time (-WE)
Data setup time (-WE)
Data hold time
—
tsu(A-WEH)
180
—
tsu(CE-WEH) 180
—
tsu(D-WEH)
th(D)
80
30
30
—
—
5
—
—
Write recover time
trec(WE)
tdis(WE)
tdis(OE)
ten(WE)
ten(OE)
—
Output disable time (-WE)
Output disable time (-OE)
Output enable time (-WE)
Output enable time (-OE)
Output enable setup time (-WE)
Output enable hold time (-WE)
-CE setup time
100
100
—
5
—
tsu(OE-WE)
th(OE-WE)
tsu(CE)
10
10
0
—
—
—
-CE hold time
th(CE)
20
—
Attribute Memory Write Timing
June 2000 Rev. 5 – ECO #12935
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I/O Access Read AC Characteristics
Parameter
Symbol
Min
—
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
100
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data delay after -IORD
td(IORD)
Data hold following -IORD
-IORD pulse width
th(IORD)
tw(IORD)
165
70
20
5
—
Address setup before -IORD
Address hold following -IORD
-CE setup before -IORD
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
—
—
—
-CE hold following -IORD
-REG setup before -IORD
-REG hold following -IORD
-INPACK delay falling from -IORD
-INPACK delay rising from -IORD
-IOIS16 delay falling from address
-IOIS16 delay rising from address
20
5
—
—
0
—
tdfINPCAK(IORD) 0
tdrINPACK(IORD) —
45
45
35
35
tdfIOIS16(IORD)
tdrIOIS16(IORD)
—
—
I/O Access Read Timing
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
I/O Access Write AC Characteristics
Parameter
Symbol
Min
60
30
165
70
20
5
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data setup before -IOWR
Data hold following -IOWR
-IOWR pulse width
tsu(IOWR)
th(IOWR)
tw(IOWR)
Address setup before -IOWR
Address hold following -IOWR
-CE setup before -IOWR
-CE hold following -IOWR
-REG setup before -IOWR
-REG hold following -IOWR
-IOIS16 delay falling from address
-IOIS16 delay rising from address
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
20
5
0
—
—
I/O Access Write Timing
June 2000 Rev. 5 – ECO #12935
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Common Memory Access Read AC Characteristics
Parameter
Symbol
ta(OE)
tdis(OE)
tsu(A)
Min
—
—
30
20
0
Typ
—
Max
125
100
—
Unit
ns
-OE access time
Output disable time (-OE)
Address setup time
Address hold time
-CE setup time
—
ns
—
ns
th(A)
—
—
ns
tsu(CE)
th(CE)
—
—
ns
-CE hold time
20
—
—
ns
Common Access Read Timing
June 2000 Rev. 5 – ECO #12935
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Common Memory Access Write AC Characteristics
Parameter
Symbol
tsu(D-WEH)
th(D)
Min
80
30
150
30
0
Typ
—
—
—
—
—
—
—
Max
—
Unit
ns
Data setup time (-WE)
Data hold time
—
ns
Write pulse time
Address setup time
-CE setup time
tw(WE)
tsu(A)
—
ns
—
ns
tsu(CE)
trec(WE)
th(CE)
—
ns
Write recover time
-CE hold following -WE
30
20
—
ns
—
ns
Common Access Write Timing
June 2000 Rev. 5 – ECO #12935
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True IDE Mode Access Read AC Characteristics
Parameter
Symbol
Min
—
0
Typ
—
—
—
—
—
—
—
—
—
Max
100
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data delay after IORD
Data hold follwing IORD
IORD width time
td(IORD)
th(IORD)
tw(IORD)
165
70
20
5
—
Address setup before IORD
Address hold following IORD
CE setup before IORD
CE hold following IORD
IOIS16 delay falling from address
IOIS16 delay rising from address
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tdfIOIS16(ADR)
tdfIOIS16(ADR)
—
—
—
20
—
—
—
35
35
True IDE Mode Access Read Timing
A0 to A2
thA(IORD)
thCE(IORD)
tsuA(IORD)
tsuCE(IORD)
-CE2/-CE1
-IORD
tw(IORD)
tdrIOIS(ADR)
td(IORD)
-IOIS16
tdrIOIS(ADR)
th(IOIS)
Valid Output
D0 to D15
-I/OWR: High Fix, -OE: Low Fix, -WE: High Fix
June 2000 Rev. 5 – ECO #12935
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True IDE Mode Access Write AC Characteristics
Parameter
Symbol
Min
60
30
165
70
20
5
Typ
—
—
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data setup before IOWR
data hold following IOWR
IORD width time
tsu(IOWR)
th(IOWR)
—
tw(IOWR)
—
address setup before IOWR
address hold following IOWR
CE setup before IOWR
CE hold following IOWR
IOIS16 delay falling from address
IOIS16 delay rising from address
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tdfIOIS16(ADR)
tdfIOIS16(ADR)
—
—
—
20
—
—
35
35
—
True IDE Mode Access Write Timing
A0 to A2
thA(IOWR)
thCE(IORD)
tsuA(IOWR)
tsuCE(IORD)
-CE2/-CE1
-IOWR
tw(IOWR)
tdrIOIS(ADR)
-IOIS16
tdrIOIS(ADR)
tsu(IOWR
th(IOWR)
Valid Output
D0 to D15
-I/ORD: High Fix,
-OE: Low Fix,
-WE: High
June 2000 Rev. 5 – ECO #12935
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Reset Characteristics (only Memory Card Mode or I/O Card Mode)
Hard Reset Characteristics
Parameter
Symbol
tsu(RESET)
trec(VCC)
tpr
Min
100
1
Typ
—
—
—
—
—
—
—
Max
—
Unit
ms
µs
Test conditions
Reset setup time
-CE recover time
VCC rising up time
VCC falling down time
Reset pulse width
—
0.1
3
100
300
—
ms
ms
µs
tpf
tw(RESET)
10
th(Hi-ZRESET) 1
ts(Hi-ZRESET) 0
—
ms
ms
—
Hard Reset Timing
June 2000 Rev. 5 – ECO #12935
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Power on Reset Characteristics
All card status are reset automatically when VCC voltage goes over about 2.3 V.
Parameter
Symbol
tsu(VCC)
tpr
Min
100
0.1
Typ
—
Max
—
Unit
ms
Test conditions
-CE setup time
VCC rising up time
—
100
ms
Power on Reset Timing
tpr
Vcc
tsu(Vcc)
-CE1, -CE2
Attention for Card Use
•
•
•
In the reset or power off, all register information is cleared.
All card status are cleared automatically when Vcc voltage turns below about 2.5V.
After the card hard reset, soft reset, or power on reset, the card cannot access during +READY pin is
"low" level.
•
Please notice that the card insertion/removal should be executed after card internal operations are
completed (status register bit 7 turns from "1" to "0").
•
•
Unused pins of data bus (D0 to D15) signals should not be opened.
V
CC should not be supplied to the card until it is completely inserted. After confirmation that the –CD1
and –CD2 pins are inserted VCC can be supplied to the card. Only use drives that will wait until the
card is completely inserted to supply VCC
.
•
-OE must be kept at the VCC level during power on reset in Memory Card Mode. –OE must be kept
constantly at the GND level in True IDE Mode.
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
Physical Outline
Interconnect area
3.0mm MIN
1.6mm ± 0.05
10.0mm MIN
1.0mm ± 0.05
Substrate area
54.0mm ± 0.10
85.6mm ± 0.20
1.0mm ± 0.05
10.0mm MIN
3.3mm ± T1 (0.130”)
T1=0.10mm interconnect area
1.6mm ± 0.05
85.6mm ± 0.20
1.0mm
Substrate area
54.0mm ± 0.10
1.0mm
10.0mm
Interconnect area
5.0mm ± T1
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PRODUCT MARKING
WED7P016ATA2000C15 C995 9915
EDI
Date code
Lot code / trace number
Part number
Company Name
Note:
Some products are currently marked with our pre-merger company name/acronym (EDI). During our
transition period some products will also be marked with our new company name/acronym (WED). Starting
October 2000 all PCMCIA products will be marked only with WED prefix.
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7PxxxATA20xxC25
PART NUMBERING
7P016ATA2000C15
Card access time
15
25
150ns
250ns
Temperature range
C
I
Commercial 0C to +70C
Industrial -40C to +85C
Packaging option
00
Standard, type 1
Card family and version
- see Card Family and Version Info. for details (next page)
Card capacity
016 16MB
PC card
P
Standard PCMCIA
R
RuggedizedPCMCIA
Card technology
7
8
FLASH
SRAM
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7PxxxATA20xxC25
Ordering Information
7P XXX ATA YY SS T ZZ
Where
XXX (unformatted capacity):
008
016
032
048
064
080
96
112
128
160
8MB
16MB
32MB
48MB
64MB
80MB
96MB
112MB
128MB
160MB
YY:
SS:
20
Standard, 3V/5V: (Controller type = HN)
00
01
02
03
04
05
WEDC Flash ATA logo
Blank Housing
Type I
Type I
Blank Housing
WEDC Flash ATA logo
Blank Housing
Type I Recessed
Type II
Type II
Blank Housing
Type II Recessed
T:
C
I
Commercial Temperature Range
Industrial Temperature Range
ZZ:
25
250ns
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7PxxxATA20xxC25
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
0.0 June 16, 1998
Initial issue
W. Brys
Card Line up table
0.1 January 25,
1999
W. Brys
W. Wrotek
Card pin explanation
changes for WAIT and INPACK
New Block Diag and Note
CIS changes: reformat CIS and changes in
addresses: 004H, 010H, 012H, 050H, 05AH, 070H,
072H, 07AH, 080H, 088H,
ATA Command specifications
-
5. Identify Drive Information (table) (page 40)
Change of data field type information: word
address 1
Change of total bytes: word address 7 to 8
Change of total default value: word address 51
DC Characteristics-3 (5 V)
Change of test conditions:
CMOS level between to CMOS level during
I
I
typ: 0.5 mA to 0.5/0.7/1.0 mA
SP1 max: TBD to 1.0/1.5/2.0 mA
ISP1 (DC) typ: 50 mA to 40/40/40 mA
I
I
I
CCR , ICCW (DC) max: TBD to 75/75/75 mA
CCR (DC) typ: 0.5 mA to 45/45/45 mA
CCW, I (Peak) typ: 100 mA to 80 mA
ICCR , ICCW (Peak) max: TBD to 120 mA
DC CharCaCcR teCrCisWtics-4 (3.3 V)
Change of test conditions:
CMOS level between to CMOS level during
I
I
typ: 0.3 mA to 0.3/0.4/0.5 mA
SP1 max: TBD to
0.6/0.8/1.0 mA
ISP1 , I (DC) typ: 30 mA to 25/25/25 mA
CCR , ICCW (DC) max: TBD to
50/50/50 mA
CCR , ICCW (Peak) typ: 60 mA to 50/50/50 mA
I
I
I
CCCCRR , ICCCCWW (Peak) max: TBD to 80/80/80 mA
Power On Reset Characteristics
tsu(RESET), tsu(VCC) min: 250 ms to 100 ms
Page 1: add “industrial temp range”
0.2 April 9, 1999
0.3 May 14, 1999
W. Brys
W. Brys
W. Wrotek
W. Wrotek
Add industrial temp range to the specification
Company name change
Page 1: Added the 112MB and 128MB capacities and their
part numbers to the list of ATA20 series cards.
0.4 August 27, 1999
M. Garrett W. Brys
In the Features section, type I housing was added
to the specifications to reflect the choice between
type I and type II housing.
In the Features section, the part number for the
Hitachi memory component was changed from
HN29W6411 to HN29W6411A, to reflect the new
memory component used for these cards.
In the features section, the data write endurance
was changed from 100,000 cycles to 300,000. This
change is resulting from the change in memory
June 2000 Rev. 5 – ECO #12935
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7PxxxATA20xxC25
components.
Page 2: Two rows were added to the Card Line Up to show
the values for the new 112MB and 128MB
capacities.
Page 17: In the CIS information, at address 050H, the value
was changed from 033H from 034H (from 3 to 4 in
decimal), to reflect the new revision of the card.
Page 43: “Wait the Command Input” was added to the
bottom bubble of the Sector read flow chart. This
was previously missing from the chart.
The Sector read timing diagram was converted
from a picture to a Microsoft Word Object to
decrease file size.
Page 44: The Sector write timing diagram was converted
from a picture to a Microsoft Word Object to
decrease file size.
Page 45: The data transfer cycle end to ready (Sector write)
value was changed from 2ms to 1.2ms (typ.). This
change is resulting from the change in memory
components.
Page 47: The capacity headings on both the DC
Characteristics-3 and DC Characteristics-4 tables
changed from 8MB/15MB/30MB/45MB,
60MB/75MB/90MB, and 150MB to
8MB/16MB/32MB/48MB, 64MB/80MB/96MB, and
112MB/128MB/160MB. This change reflects the
addition of the 112MB and 128MB capacities, and
the change of designations for the other cards,
which were labeled with the old capacity values,
though the capacities were actually what they are
labeled now.
The Test conditions for the Sleep/standby current,
for both the DC Charcteristics-3 and DC
Characteristics-4 tables have the phrase “in
Memory Card Mode and I/O Card Mode” appended
to them.
The Sector write current values for each capacity
column in the DC Characteristics-3 table were
changed from 50/100,TBD/TBD to 45/80,75/120 in
mA (DC/Peak for Typ and Max respectively).
Page 48: New waveform (MS Word object) added for Power
on Operation, in the DC Current Waveform section.
Page 49: The old waveforms (MS Word objects) for Sector
Read Current and Sector Write Current, in the DC
Current Waveform section, were replaced with
updated waveforms for each.
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Page 57: In the Hard Reset Characteristics table, The
minimum value for Reset setup time changed from
250ms to 100ms.
Page 59: Under “Attention for Card Use”, the information
following the final two bullets was added.
Page 60: The Mechanical Drawing for a Type I housing was
added to the Physical Outline section, since the
cards are now available in a Type I housing.
Page 61: Under Ordering Information, The digits needed to
order the new 112MB and 128MB capacity cards
were added.
Under Ordering Information, The digits needed to
order cards in a Type I housing were added, since
this option was not available before.
0.5 June 2, 2000
Added Page 61 & 62
M. Garrett
File: F:\Marcom\Data Sheets-New\Data Sheets – Commercial\ATA20 Dsht Rev 5.doc
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