A1240A-2PQG144I [MICROSEMI]
Field Programmable Gate Array, 100MHz, 684-Cell, CMOS, PQFP144,;型号: | A1240A-2PQG144I |
厂家: | Microsemi |
描述: | Field Programmable Gate Array, 100MHz, 684-Cell, CMOS, PQFP144, 栅 |
文件: | 总54页 (文件大小:2468K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 8
ACT 2 Family FPGAs
Features
• Up to 8,000 Gate Array Gates
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL® Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequence Functions
• Wide-Input Combinatorial Functions
• Up to 1,232 Programmable Logic Modules
• Up to 998 Flip-Flops
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0 micron CMOS Technology
Table 1 • ACT 2 Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
Logic Modules
2,500
6,250
63
4,000
10,000
100
8,000
20,000
200
25
40
80
451
231
220
382
684
1,232
624
S-Module
348
C-Module
336
608
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
User I/Os (maximum)
Performance1
568
998
36
15
36
15
36
15
250,000
83
400,000
104
750,000
140
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
Packages2
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
85 MHz
67 MHz
36 MHz
CPGA
PLCC
PQFP
VQFP
TQFP
CQFP
PG100
PL84
PQ100
VQ100
PG132
PL84
PQ144
–
TQ176
–
PG176
PL84
PQ160
–
TQ176
CQ172
–
–
Notes:
1. Performance is based on –2 speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1,
Version 1.2, dated 3-28-93. Any analysis is not endorsed by PREP.
2. See the "Product Plan" on page III for package availability.
January 2012
I
© 2012 Microsemi Corporation
ACT 2 Family FPGAs
Ordering Information
_
PG
G
176
A
1
A1280
C
Application (T emperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0 μm CMOS Process
Part Number
A1225 = 2,500 Gates
A1240 = 4,000 Gates
A1280 = 8,000 Gates
II
Revision 8
ACT 2 Family FPGAs
Product Plan
Speed Grade1
–1
Application1
Device/Package
Std.
–2
C
I
M
B
A1225A Device
84-Pin Plastic Leaded Chip Carrier (PL)
✓
✓
✓
✓
–
–
–
–
–
–
–
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
100-Pin Plastic Quad Flatpack (PQ)
100-Pin Very Thin Quad Flatpack (VQ)
100-Pin Ceramic Pin Grid Array (PG)
–
A1240A Device
84-Pin Plastic Leaded Chip Carrier (PL)
✓
✓
✓
✓
–
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
132-Pin Ceramic Pin Grid Array (PG)
144-Pin Plastic Quad Flat Pack (PQ)
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
✓
–
✓
–
✓
–
–
–
A1280A Device
160-Pin Plastic Quad Flatpack (PQ)
✓
✓
✓
✓
–
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
172-Pin Ceramic Quad Flatpack (CQ)
176-Pin Ceramic Pin Grid Array (PG)
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
✓
✓
–
✓
✓
–
–
–
Notes:
Availability:
Speed Grade:
–1 = Approx. 15% faster than Std.
–2 = Approx. 25% faster than Std.
1. Applications:
C = Commercial
I = Industrial
M = Military
✓ = Available
P = Planned
– = Not planned
B = MIL-STD-883
2. Contact your Microsemi SoC Products Group sales representative for product availability.
Device Resources
User I/Os
Device
Series
Logic
Modules Gates
PG176 PG132 PG100 PQ160 PQ144 PQ100
PL84
72
CQ172 TQ176 VQ100
A1225A
A1240A
A1280A
451
684
2,500
4,000
8,000
–
–
–
104
–
83
–
–
–
–
104
–
83
–
–
–
–
83
–
72
104
140
1,232
140
–
125
–
72
140
–
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
Revision 8
III
ACT 2 Family FPGAs
Table of Contents
ACT 2 Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Detailed Specifications
Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
ACT 2 Timing Model1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Package Pin Assignments
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
PG176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Revision 8
IV
1 – ACT 2 Family Overview
General Description
The ACT 2 family represents Actel’s second generation of field programmable gate arrays
(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-
modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family provides significant enhancements to gate
density and performance while maintaining downward compatibility with the ACT 1 design environment
and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon
gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary
architecture offers gate array design flexibility, high performance, and fast time-to-production with user
programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which
offers automatic pin assignment, validation of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are
supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems
®
provide CAE interfaces to the following design environments: Cadence, Viewlogic®, Mentor Graphics ,
and OrCAD™.
Revision 8
1-1
2 – Detailed Specifications
Operating Conditions
Table 2-1 • Absolute Maximum Ratings1
Symbol
VCC
VI
Parameter
DC supply voltage
Limits
–0.5 to +7.0
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
±20
Units
V
Input voltage
V
VO
Output voltage
V
IIO
I/O source sink current2
Storage temperature
mA
°C
TSTG
Notes:
–65 to +150
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be
operated outside the recommended operating conditions.
2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater
than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will be forward biased and can draw
excessive current.
Table 2-2 • Recommended Operating Conditions
Parameter
Commercial
0 to +70
±5
Industrial
–40 to +85
±10
Military
–55 to +125
±10
Units
°C
Temperature range*
Power supply tolerance
%VCC
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.
Revision 8
2-1
Detailed Specifications
Table 2-3 • Electrical Specifications
Commercial
Industrial
Min. Max.
Military
Max.
Symbol
Parameter
(IOH = –10 mA)2
Min.
Max.
Min.
–
Units
V
VOH1
2.4
3.84
–
–
–
–
–
–
(IOH = –6 mA)
(IOH = –4 mA)
(IOL = 10 mA)2
(IOL = 6 mA)
–
–
–
–
–
V
3.7
–
–
–
3.7
–
–
–
V
VOL1
–
0.5
V
–
0.33
0.8
–
0.40
0.8
–
0.40
0.8
V
VIL
–0.3
2.0
–
–0.3
2.0
–
–0.3
2.0
–
V
VIH
VCC + 0.3
500
10
VCC + 0.3
500
VCC + 0.3
500
V
2
Input Transition Time tR, tF
CIO I/O capacitance2,3
ns
pF
mA
µA
–
–
10
–
10
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
–
2
–
10
–
20
–10
+10
–10
+10
–10
+10
ICC(D)
Dynamic VCC supply current. See the Power Dissipation section.
Notes:
1. Only one output tested at a time. VCC = minimum.
2. Not tested, for information only.
3. Includes worst-case PG176 package capacitance. VOUT = 0 V, f = 1 MHz
4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal
operations.
5. VOUT, VIN = VCC or GND.
2-2
Revision 8
ACT 2 Family FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is
θja. The thermal characteristics for θja are shown with two different air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power dissipation allowed for a PQ160 package at
commercial temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 70°C
---------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------
=
= 2.4 W
θja°C/W
33°C/W
EQ 1
Table 2-4 • Package Thermal Characteristics
θja
θja
Package Type*
Pin Count
100
θjc
5
Still Air
300 ft./min.
Units
Ceramic Pin Grid Array
35
17
15
12
15
40
32
30
28
35
25
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
132
5
30
176
8
23
Ceramic Quad Flatpack
Plastic Quad Flatpack1
172
8
25
100
13
15
15
12
12
15
48
144
40
160
38
Plastic Leaded Chip Carrier
Very Thin Quad Flatpack
Thin Quad Flatpack
84
37
100
43
176
32
Notes: (Maximum Power in Still Air)
1. Maximum power dissipation values for PQFP packages are 1.9 W (PQ100), 2.3 W (PQ144), and 2.4 W
(PQ160).
2. Maximum power dissipation for PLCC packages is 2.7 W.
3. Maximum power dissipation for VQFP packages is 2.3 W.
4. Maximum power dissipation for TQFP packages is 3.1 W.
Power Dissipation
P = [ICC standby + ICCactive] * VCC + IOL * VOL * N + IOH* (VCC – VOH) * M
EQ 2
where:
ICC standby is the current flowing when no inputs or outputs are changing
ICCactive is the current flowing due to CMOS switching.
IOL and IOH are TTL sink/source currents.
VOL and VOH are TTL level output voltages.
N is the number of outputs driving TTL loads to VOL.
M is the number of outputs driving TTL loads to VOH.
An accurate determination of N and M is problematical because their values depend on the family type,
design details, and on the system I/O. The power can be divided into two components: static and active.
Revision 8
2-3
Detailed Specifications
Static Power Component
Microsemi FPGAs have small static power components that result in lower power dissipation than PALs
or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level
power dissipation can be achieved.
The power due to standby current is typically a small component of the overall power. Standby power is
calculated in Table 2-5 for commercial, worst case conditions.
Table 2-5 • Standby Power Calculation
ICC
VCC
Power
2 mA
5.25 V
10.5 mW
The static power dissipated by TTL loads depends on the number of outputs driving high or low and the
DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will
generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual
dissipation will average somewhere between as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This
component is frequency dependent, a function of the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module
inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is the totem-pole current in CMOS transistor
pairs. The net effect can be associated with an equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by EQ 3.
Power (µW) = CEQ * VCC2 * F
EQ 3
Where:
CEQ is the equivalent capacitance expressed in pF.
VCC is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used
over a wide range of operating conditions. Equivalent capacitance values are shown in Table 2-6.
Table 2-6 • CEQ Values for Microsemi FPGAs
Item
CEQ Value
5.8
Modules (CEQM
)
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer Loads (CEQCR
)
12.9
)
23.8
)
3.9
2-4
Revision 8
ACT 2 Family FPGAs
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. EQ 4 shows a piece-wise linear summation over all components.
Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs
+ (p * (CEQO+ CL) * fp)outputs
+ 0.5 * (q1 * CEQCR * fq1 routed_Clk1
)
+ (r1 * fq1 routed_Clk1
)
+ 0.5 * (q2 * CEQCR * fq2 routed_Clk2
)
+ (r2 * fq2 routed_Clk2
)
EQ 4
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output lead capacitance in pF
m = Average logic module switching rate in MHz
f
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
f
f
q1 = Average first routed array clock rate in MHz
q2 = Average second routed array clock rate in MHz
Table 2-7 • Fixed Capacitance Values for Microsemi FPGAs
Device Type
r1, routed_Clk1
r2, routed_Clk2
106.0
A1225A
106
134
168
A1240A
A1280A
134.2
167.8
Revision 8
2-5
Detailed Specifications
Determining Average Switching Frequency
To determine the switching frequency for a design, you must have a detailed understanding of the data
input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that
they can be generally used to predict the upper limits of power dissipation. These guidelines are given in
Table 2-8.
Table 2-8 • Guidelines for Predicting Power Dissipation
Data
Value
80% of modules
Logic Modules (m)
Inputs switching (n)
# inputs/4
Outputs switching (p)
# output/4
First routed array clock loads (q1)
Second routed array clock loads (q2)
Load capacitance (CL)
40% of sequential modules
40% of sequential modules
35 pF
F/10
F/5
Average logic module switching rate (fm)
Average input switching rate (fn)
Average output switching rate (fp)
F/10
F
Average first routed array clock rate (fq1
)
Average second routed array clock rate (fq2
)
F/2
2-6
Revision 8
ACT 2 Family FPGAs
1
ACT 2 Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Logic Module
I/O Module
I/O Module
t
= 2.6 ns
t
= 4.8 ns(2)
INYL
IRD2
t
= 8.0 ns
DLH
t
t
t
t
= 1.4 ns
= 1.7 ns
= 3.1 ns
= 4.7 ns
RD1
RD2
RD4
RD8
D
G
Q
t
= 3.8 ns
PD
I/O Module
t
= 8.0 ns
DLH
Sequential
Logic Module
t
= 2.0 ns
= 4.0 ns
= 4.7 ns
INH
t
t
INSU
INGL
D
D
G
Q
Q
Combin-
atorial
t
= 1.4 ns
Logic
t
= 7.1 ns
RD1
ENHZ
Included
in tSUD
t
= 0.0 ns
= 0.4 ns
= 9.0 ns
OUTH
t
OUTSU
t
= 3.8 ns
t
= 0.4 ns
= 0.0 ns
CO
SUD
HD
ARRAY
t
GLH
t
CLOCKS
t
= 11.8 ns
FO = 256
CKH
F
= 100 MHz
MAX
Notes:
1. Values shown for A1240A-2 at worst-case commercial conditions.
2. Input module predicted routing delay
Figure 2-1 • Timing Model
Revision 8
2-7
Detailed Specifications
Parameter Measurement
E
D
TRIBUFF
To AC test loads (shown below)
PAD
VCC
50%
VCC
VCC
In
GND
1.5 V
50%
E
GND
10%
E
GND
90%
50%
50%
VCC
50%
VOH
50%
VOH
1.5 V
VOL
PAD
VOL
PAD
PAD
GND
1.5 V
1.5 V
t
t
t
t
t
t
ENHZ
DHS,
DHS
ENZL
ENLZ
ENZH
Figure 2-2 • Output Buffer Delays
Load 2
(Used to measure rising/falling edges)
Load 1
(Used to measure propagation delay)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ / tPZL
R to GND for tPHZ / tPZH
R = 1 kΩ
To the output under test
50 pF
Figure 2-3 • AC Test Loads
Y
PAD
INBUF
3 V
PAD
0 V
50%
1.5 V
VCC
1.5 V
Y
GND
50%
t
t
INYL
INYH
Figure 2-4 • Input Buffer Delays
2-8
Revision 8
ACT 2 Family FPGAs
S
A
B
Y
VCC
GND
S, A or B
50% 50%
VCC
50%
Y
50%
GND
t
t
PHL
PLH
VCC
50%
Y
GND
50%
t
t
PLH
PHL
Figure 2-5 • Module Delays
Sequential Module Timing Characteristics
Y
D
E
CLK
CLR
(Positive edge triggered)
t
HD
D*
t
t
t
A
WCLKA
SUD
G, CLK
tSUENA
t
WCLKI
tHENA
E
t
CO
Q
tRS
PRE, CLR
t
WASYN
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 2-6 • Flip-Flops and Latches
Revision 8
2-9
Detailed Specifications
PAD
G
DATA
IBDL
PAD
CLK
CLKBUF
DATA
G
t
INH
t
INSU
t
HEXT
CLK
t
SUEXT
Figure 2-7 • Input Buffer Latches
D
PAD
OBDLHS
G
D
G
tOUTSU
tOUTH
Figure 2-8 • Output Buffer Latches
2-10
Revision 8
ACT 2 Family FPGAs
Timing Derating Factor (Temperature and Voltage)
Table 2-9 • Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Military
Min.
0.69
Max.
Min.
Max.
1.23
1.11
0.67
Table 2-10 • Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)
and Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Table 2-11 • Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
0.75
0.71
0.69
0.68
0.67
–40
0.79
0.75
0.72
0.69
0.69
0
25
70
85
125
1.23
1.13
1.13
1.09
1.08
4.50
4.75
5.00
5.25
5.50
0.86
0.82
0.80
0.77
0.76
0.92
0.87
0.85
0.82
0.81
1.06
1.00
0.97
0.95
0.93
1.11
1.05
1.02
0.98
0.97
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
125˚C
85˚C
70˚C
25˚C
0˚C
–40˚C
–55˚C
4.504.755.005.255.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 2-9 • Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
Revision 8
2-11
Detailed Specifications
A1225A Timing Characteristics
Table 2-12 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max.
Min.
Max.
5.0
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
ns
ns
ns
ns
Sequential Clock to Q
Latch G to Q
5.0
5.0
Flip-Flop (Latch) Reset to Q
5.0
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.1
1.7
2.3
2.8
4.4
1.2
1.9
2.6
3.1
4.9
1.4
2.2
3.0
3.7
5.8
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
0.4
0.0
0.8
0.0
4.5
0.4
0.0
0.9
0.0
5.0
5.0
11.0
0.0
0.4
0.0
0.4
0.5
0.0
1.0
0.0
6.0
6.0
13.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Clock Asynchronous Pulse Width 4.5
Flip-Flop Clock Input Period
Input Buffer Latch Hold
9.4
0.0
0.4
0.0
0.4
tINH
tINSU
tOUTH
tOUTSU
fMAX
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
105.0
90.0
75.0 MHz
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
—whichever is appropriate.
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
2-12
Revision 8
ACT 2 Family FPGAs
A1225A Timing Characteristics (continued)
Table 2-13 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Units
I/O Module Input Propagation Delays
Parameter/Description
–2 Speed
–1 Speed
Std. Speed
Min. Max. Min. Max. Min.
Max.
3.8
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.6
5.0
4.7
3.3
3.0
5.7
5.4
ns
ns
ns
ns
3.5
6.6
6.3
Input Module Predicted Input Routing Delays*
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
4.1
4.6
5.3
5.7
7.4
4.6
5.2
6.0
6.4
8.3
5.4
6.1
7.1
7.6
9.8
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
10.2
11.8
10.2
12.0
11.0
13.0
11.0
13.2
12.8
15.7
12.8
15.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCKL
Input High to Low
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.4
3.8
3.4
3.8
4.1
4.5
4.1
4.5
4.5
5.0
4.5
5.0
0.7
3.5
0.7
3.5
0.7
3.5
Input Latch External Setup
Input Latch External Hold
Minimum Period
0.0
0.0
7.0
11.2
7.7
8.1
0.0
0.0
7.0
11.2
8.3
8.8
0.0
0.0
7.0
11.2
9.1
10.0
fMAX
Maximum Frequency
130.0
125.0
120.0
115.0
110.0
100.0
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Revision 8
2-13
Detailed Specifications
A1225A Timing Characteristics (continued)
Table 2-14 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max. Min.
Max.
10.6
13.4
11.8
15.5
9.4
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.0
10.1
8.9
9.0
11.4
10.0
13.2
8.0
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.09
0.16
ns
8.9
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.2
0.07
0.12
ns
dTLH
Delta Low to High
Delta High to Low
ns/pF
ns/pF
dTHL
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.1
8.4
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
8.9
10.0
13.2
8.0
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.16
0.12
ns
8.9
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.2
0.12
0.09
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
2-14
Revision 8
ACT 2 Family FPGAs
A1240A Timing Characteristics
Table 2-15 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max.
Min.
Max.
5.0
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
ns
ns
ns
ns
Sequential Clock to Q
Latch G to Q
5.0
5.0
Flip-Flop (Latch) Reset to Q
5.0
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.4
1.7
2.3
3.1
4.7
1.5
2.0
2.6
3.5
5.4
1.8
2.3
3.0
4.1
6.3
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
0.4
0.0
0.8
0.0
4.5
0.4
0.0
0.9
0.0
6.0
6.0
12.0
0.0
0.4
0.0
0.4
0.5
0.0
1.0
0.0
6.5
6.5
15.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Clock Asynchronous Pulse Width 4.5
Flip-Flop Clock Input Period
Input Buffer Latch Hold
9.8
0.0
0.4
0.0
0.4
tINH
tINSU
tOUTH
tOUTSU
fMAX
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
100.0
80.0
66.0 MHz
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
—whichever is appropriate.
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
Revision 8
2-15
Detailed Specifications
A1240A Timing Characteristics (continued)
Table 2-16 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Units
I/O Module Input Propagation Delays
Parameter/Description
–2 Speed
–1 Speed
Std. Speed
Min. Max. Min. Max. Min.
Max.
3.8
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.6
5.0
4.7
3.3
3.0
5.7
5.4
ns
ns
ns
ns
3.5
6.6
6.3
Input Module Predicted Input Routing Delays*
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
4.2
4.8
5.4
5.9
7.9
4.8
5.4
6.1
6.7
8.9
5.6
6.4
ns
ns
ns
ns
ns
7.2
7.9
10.5
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
10.2
11.8
10.2
12.0
11.0
13.0
11.0
13.2
12.8
15.7
12.8
15.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCKL
Input High to Low
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.8
4.1
3.8
4.1
4.5
5.0
4.5
5.0
5.5
5.8
5.5
5.8
0.5
2.5
0.5
2.5
0.5
2.5
Input Latch External Setup
Input Latch External Hold
Minimum Period
0.0
0.0
7.0
11.2
8.1
8.8
0.0
0.0
0.0
0.0
7.0
7.0
11.2
9.1
11.2
11.1
11.7
10.0
fMAX
Maximum Frequency
125.0
115.0
110.0
100.0
90.0
85.0
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
2-16
Revision 8
ACT 2 Family FPGAs
A1240A Timing Characteristics (continued)
Table 2-17 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max. Min.
Max.
10.6
13.4
11.8
15.5
9.4
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.0
10.1
8.9
9.0
11.4
10.0
13.2
8.0
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.7
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.09
0.16
ns
9.0
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.2
0.07
0.12
ns
dTLH
Delta Low to High
Delta High to Low
ns/pF
ns/pF
dTHL
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.2
8.4
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
8.9
10.0
13.2
8.0
ns
11.7
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.16
0.12
ns
9.0
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.2
0.12
0.09
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
Revision 8
2-17
Detailed Specifications
A1280A Timing Characteristics
Table 2-18 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max.
Min.
Max.
5.0
tPD1
tCO
tGO
tRS
Single Module
3.8
3.8
3.8
3.8
4.3
4.3
4.3
4.3
ns
ns
ns
ns
Sequential Clock to Q
Latch G to Q
5.0
5.0
Flip-Flop (Latch) Reset to Q
5.0
Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.7
2.5
3.0
3.7
6.7
2.0
2.8
3.4
4.2
7.5
2.3
3.3
4.0
4.9
8.8
ns
ns
ns
ns
ns
Sequential Timing Characteristics3,4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
0.4
0.0
0.8
0.0
5.5
0.4
0.0
0.9
0.0
6.0
6.0
13.3
0.0
0.4
0.0
0.4
0.5
0.0
1.0
0.0
7.0
7.0
18.0
0.0
0.5
0.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
tWASYN
tA
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Clock Asynchronous Pulse Width 5.5
Flip-Flop Clock Input Period
Input Buffer Latch Hold
11.7
0.0
0.4
0.0
0.4
tINH
tINSU
tOUTH
tOUTSU
fMAX
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
85.0
75.0
50.0 MHz
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
—whichever is appropriate.
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
2-18
Revision 8
ACT 2 Family FPGAs
A1280A Timing Characteristics (continued)
Table 2-19 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Units
I/O Module Input Propagation Delays
Parameter/Description
–2 Speed
–1 Speed
Std. Speed
Min. Max. Min. Max. Min.
Max.
3.8
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
2.9
2.7
5.0
4.8
3.3
3.0
5.7
5.4
ns
ns
ns
ns
3.5
6.6
6.3
Input Module Predicted Input Routing Delays*
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
4.6
5.2
5.6
6.5
9.4
5.1
5.9
6.0
6.9
ns
ns
ns
ns
ns
6.3
7.4
7.3
8.6
10.5
12.4
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
10.2
13.1
10.2
13.3
11.0
14.6
11.0
14.9
12.8
17.2
12.8
17.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCKL
Input High to Low
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
5.0
5.8
5.0
5.8
5.5
6.4
5.5
6.4
6.6
7.6
6.6
7.6
0.5
2.5
0.5
2.5
0.5
2.5
Input Latch External Setup
Input Latch External Hold
Minimum Period
0.0
0.0
0.0
0.0
0.0
0.0
7.0
7.0
7.0
11.2
9.6
11.2
11.2
12.6
11.2
13.3
15.3
10.6
fMAX
Maximum Frequency
105.0
95.0
90.0
80.0
75.0
65.0
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
A1280A Timing Characteristics (continued)
Revision 8
2-19
Detailed Specifications
Table 2-20 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min. Max. Min. Max. Min.
Max.
10.6
13.4
11.8
15.5
9.4
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.1
10.2
9.0
9.0
11.4
10.0
13.2
8.0
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.8
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.09
0.16
ns
9.0
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.3
0.07
0.12
ns
dTLH
Delta Low to High
Delta High to Low
ns/pF
ns/pF
dTHL
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.3
8.5
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
9.0
10.0
13.2
8.0
ns
11.8
7.1
ns
ns
8.4
9.5
11.1
11.9
14.9
0.16
0.12
ns
9.0
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.3
0.12
0.09
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
2-20
Revision 8
ACT 2 Family FPGAs
Pin Descriptions
CLKA
Clock A (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
CLKB
Clock B (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is
High. This pin functions as an I/O when the MODE pin is Low.
GND
Ground
Low supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven Low
by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is
High, the special functions are active. When the MODE pin is Low, the pins function as I/Os. To provide
Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the
MODE pin can be pulled High when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA Probe A (Output)
The Probe A pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic
output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic
output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO
Serial Data Output (Output)
Serial data output for diagnostic probe. SDO is active when the MODE pin is High. This pin functions as
an I/O when the MODE pin is Low.
VCC
5.0 V Supply Voltage
High supply voltage.
Revision 8
2-21
3 – Package Pin Assignments
PL84
11 10
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75
12
74
13
14
73
72
15
16
17
18
71
70
69
68
19
20
21
22
23
24
25
26
27
28
67
66
65
64
63
62
61
60
59
58
84-Pin
PLCC
29
30
31
32
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 8
3-1
Package Pin Assignments
PL84
A1240A Function
Pin Number
A1225A Function
A1280A Function
CLKB, I/O
PRB, I/O
GND
2
CLKB, I/O
PRB, I/O
GND
CLKB, I/O
PRB, I/O
GND
4
6
10
12
22
23
28
43
49
52
63
64
65
70
76
81
83
84
DCLK, I/O
MODE
VCC
DCLK, I/O
MODE
VCC
DCLK, I/O
MODE
VCC
VCC
VCC
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
GND
SDO
SDO
SDO
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
SDI, I/O
PRA, I/O
CLKA, I/O
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-2
Revision 8
ACT 2 Family FPGAs
PQ100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
100-Pin
PQFP
100
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3-3
Package Pin Assignments
PQ100
PQ100
A1225A Function
Pin Number
A1225A Function
DCLK, I/O
MODE
GND
Pin Number
2
65
66
67
72
79
84
87
89
90
92
94
96
VCC
VCC
4
9
VCC
16
17
22
34
40
46
52
57
64
VCC
GND
VCC
SDI, I/O
GND
GND
GND
PRA, I/O
CLKA, I/O
VCC
VCC
GND
SDO
CLKB, I/O
PRB, I/O
GND
GND
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-4
Revision 8
ACT 2 Family FPGAs
PQ144
1
144
144-Pin
PQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3-5
Package Pin Assignments
PQ144
PQ144
Pin Number
A1240A Function
MODE
GND
Pin Number
89
A1240A Function
VCC
2
9
90
VCC
10
11
18
19
20
21
28
29
30
44
45
46
54
55
56
64
65
71
79
80
81
88
GND
91
VCC
GND
92
VCC
VCC
93
VCC
VCC
100
101
102
110
116
117
118
123
125
126
127
128
130
132
136
137
138
144
GND
VCC
GND
VCC
GND
GND
SDI, I/O
GND
GND
GND
GND
GND
GND
GND
PRA, I/O
CLKA, I/O
VCC
GND
VCC
VCC
VCC
VCC
VCC
GND
CLKB, I/O
PRB, I/O
GND
GND
SDO
GND
GND
GND
GND
GND
DCLK, I/O
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-6
Revision 8
ACT 2 Family FPGAs
PQ160
1
2
3
4
5
6
7
8
9
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
160-Pin
PQFP
82
81
Note: This is the top view of the package
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3-7
Package Pin Assignments
PQ160
PQ160
A1280A Function
Pin Number
A1280A Function
DCLK, I/O
VCC
Pin Number
69
2
GND
GND
SDO
VCC
GN
6
80
11
16
18
20
21
23
30
35
38
40
44
49
54
57
58
59
60
61
64
GND
82
PRB, I/O
CLKB, I/O
VCC
86
89
98
GND
GND
GND
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
MODE
GND
CLKA, I/O
PRA, I/O
GND
99
109
114
120
125
130
135
138
139
140
145
150
155
159
160
VCC
SDI, I/O
GND
GND
GND
VCC
VCC
VCC
GND
VCC
GND
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-8
Revision 8
ACT 2 Family FPGAs
VQ100
1
75
2
3
74
73
4
5
6
7
72
71
70
69
8
9
68
67
66
65
64
63
62
61
60
59
10
11
12
13
14
15
16
17
100-Pin
VQFP
18
19
20
21
58
57
56
55
22
23
24
25
54
53
52
51
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3-9
Package Pin Assignments
VQ100
VQ100
Pin Number
A1225A Function
MODE
GND
Pin Number
A1225A Function
VCC
2
64
65
70
77
82
85
87
88
90
92
94
100
7
VCC
14
15
20
32
38
44
50
55
62
63
VCC
GND
VCC
SDI, I/O
GND
GND
GND
PRA, I/O
CLKA, I/O
VCC
VCC
GND
SDO
CLKB, I/O
PRB, I/O
GND
GND
GND
VCC
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-10
Revision 8
ACT 2 Family FPGAs
TQ176
1
2
3
4
5
6
7
8
9
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-Pin
TQFP
98
97
96
95
94
93
92
91
90
89
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3-11
Package Pin Assignments
TQ176
Pin Number A1240A Function A1280A Function
TQ176
Pin Number A1240A Function A1280A Function
1
GND
MODE
NC
GND
MODE
NC
82
NC
NC
VCC
I/O
2
86
8
87
SDO
GND
NC
SDO
GND
I/O
10
11
13
18
19
20
22
23
24
25
26
27
28
29
33
37
38
45
52
54
55
57
61
64
66
67
68
74
77
78
80
NC
I/O
89
NC
I/O
96
NC
VCC
GND
I/O
97
NC
I/O
GND
NC
101
103
106
107
108
109
110
111
112
113
114
115
116
121
124
125
126
133
135
136
140
143
144
145
147
151
152
154
NC
NC
NC
I/O
NC
I/O
GND
NC
GND
I/O
NC
I/O
GND
NC
GND
VCC
VCC
I/O
NC
I/O
GND
VCC
GND
VCC
VCC
NC
GND
VCC
GND
VCC
VCC
I/O
VCC
NC
NC
I/O
VCC
NC
VCC
I/O
NC
NC
NC
I/O
NC
I/O
NC
VCC
NC
NC
NC
NC
GND
NC
GND
VCC
I/O
NC
I/O
NC
I/O
NC
NC
NC
NC
I/O
GND
SDI, I/O
NC
GND
SDI, I/O
I/O
NC
NC
NC
I/O
NC
I/O
NC
VCC
I/O
NC
I/O
NC
GND
VCC
NC
GND
VCC
I/O
NC
I/O
NC
NC
NC
I/O
NC
NC
NC
I/O
NC
I/O
PRA, I/O
CLKA, I/O
PRA, I/O
CLKA, I/O
NC
I/O
3-12
Revision 8
ACT 2 Family FPGAs
TQ176
Pin Number A1240A Function A1280A Function
155
156
158
160
161
165
166
168
170
173
175
VCC
GND
VCC
GND
CLKB, I/O
PRB, I/O
NC
CLKB, I/O
PRB, I/O
I/O
NC
NC
NC
I/O
NC
I/O
NC
VCC
NC
I/O
DCLK, I/O
DCLK, I/O
Notes:
1. NC denotes no connection.
2. All unlisted pin numbers are user I/Os.
3. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3-13
Package Pin Assignments
CQ172
172
Pin #1
Index
1
172-Pin
CQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3-14
Revision 8
ACT 2 Family FPGAs
CQ172
A1280A Function
CQ172
A1280A Function
Pin Number
Pin Number
107
1
7
MODE
GND
VCC
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
GND
VCC
GND
VCC
SDO
GND
GND
GND
VCC
GND
108
12
17
22
23
24
27
32
37
50
55
65
66
75
80
85
98
103
106
109
VCC
110
VCC
113
VCC
118
GND
123
GND
131
SDI, I/O
VCC
136
141
GND
148
PRA, I/O
CLKA, I/O
VCC
150
151
152
GND
154
CLKB, I/O
PRB, I/O
GND
156
161
166
VCC
171
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3-15
Package Pin Assignments
PG100
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
100-Pin
CPGA
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3-16
Revision 8
ACT 2 Family FPGAs
PG100
PG100
Pin Number
A1225A Function
PRB, I/O
PRA, I/O
VCC
Pin Number
A1225A Function
VCC
A4
A7
B6
C2
C3
C5
C6
C7
C8
D6
D10
E3
E11
F3
VCC
F9
VCC
MODE
F10
F11
G1
G3
G9
J5
VCC
DCLK, I/O
GND
GND
VCC
CLKA, I/O
GND
GND
GND
SDI, I/O
CLKB, I/O
GND
GND
J7
GND
J9
SDO
GND
K6
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3-17
Package Pin Assignments
PG132
1
2
3
4
5
6
7
8
9
10 11 12 13
A
B
C
D
E
F
A
B
C
D
E
F
132-Pin
CPGA
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3-18
Revision 8
ACT 2 Family FPGAs
PG132
A1240A Function
PG132
A1240A Function
Pin Number
A1
Pin Number
G3
MODE
GND
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
GND
GND
VCC
GND
GND
SDO
B5
G4
B6
CLKB, I/O
CLKA, I/O
PRA, I/O
GND
G10
G11
G12
G13
H13
J2
B7
B8
B9
B12
C3
SDI, I/O
DCLK, I/O
GND
C5
J3
C6
PRB, I/O
VCC
J11
C7
K7
C9
GND
K12
L5
D7
VCC
E3
GND
L7
E11
E12
F4
GND
L9
GND
M9
GND
N12
G2
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3-19
Package Pin Assignments
PG176
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
176-Pin
CPGA
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3-20
Revision 8
ACT 2 Family FPGAs
PG176
A1280A Function
PG176
A1280A Function
Pin Number
A9
Pin Number
H3
CLKA, I/O
DCLK, I/O
CLKB, I/O
SDI, I/O
MODE
GND
VCC
GND
GND
VCC
VCC
VCC
GND
GND
VCC
GND
GND
GND
GND
VCC
GND
GND
GND
VCC
GND
VCC
SDO
B3
H4
B8
H12
H13
H14
J4
B14
C3
C8
C9
PRA, I/O
GND
J12
J13
J14
K4
D4
D5
VCC
D6
GND
D7
PRB, I/O
VCC
K12
L4
D8
D10
D11
D12
E4
GND
M4
VCC
M5
GND
M6
GND
M8
E12
F4
GND
M10
M11
M12
N8
VCC
F12
G4
GND
GND
G12
H2
VCC
P13
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3-21
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the datasheet.
Revision
Changes
Page
Revision 8
(January 2012)
The ACT 2 datasheet was formatted newly in the style used for current datasheets.
The same information is present (other than noted in the list of changes for this
revision) but divided into chapters.
N/A
Package names used in Table 1 • ACT 2 Product Family Profile and throughout the
document were revised to match standards given in Package Mechanical Drawings
(SAR 27395).
I
The description for SDO pins had earlier been removed from the datasheet and has
now been included again, in the "Pin Descriptions" section (SAR 35819).
2-21
3-2
II
SDO pin numbers had earlier been removed from package pin assignment tables in
the datasheet, and have now been restored to the pin tables (SAR 35819).
Revision 7
(June 2006)
The "Ordering Information" section was revised to include RoHS information.
Revision 6
In the "PG176" package, pin A3 was incorrectly assigned as CLKA, I/O. A3 is a user
3-21
(December 2000) I/O. Pin A9 is CLKA, I/O.
Revision 8
4-1
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device is
designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these
categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
4-2
Revision 8
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