A3P250-1QNGG132T [MICROSEMI]
FPGA;Revision 5
Automotive ProASIC3 Flash Family FPGAs
Low Power
Features and Benefits
Extended Temperature AEC-Q100–Qualified Devices
•
•
•
1.5 V Core Voltage
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
•
•
•
Grade 2: –40°C to 105°C T (115°C T )
A J
High-Performance Routing Hierarchy
Grade 1: –40°C to 125°C T (135°C T )
A
J
•
•
•
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
PPAP Documentation
Firm-Error Immune
•
•
Only Automotive FPGAs to Offer Firm-Error Immunity
Can Be Used without Configuration Upset Risk
Advanced I/O
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
•
•
•
60 k to 1 M System Gates
Up to 144 kbits of SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
•
•
•
Instant On Level 0 Support
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Single-Chip Solution
Retains Programmed Design when Powered Off
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
On-Chip User Nonvolatile Memory
IEEE 1149.1 (JTAG) Boundary Scan Test
•
1 kbit of FlashROM with Synchronous Interface
®
Pin-Compatible Packages across the Automotive ProASIC 3
High Performance
Family
•
•
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
Clock Conditioning Circuit (CCC) and PLL
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
In-System Programming (ISP) and Security
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
•
Wide Input Frequency Range (1.5 MHz up to 350 MHz)
®
•
FlashLock Designed to Provide High-Level Security for FPGA
SRAMs
Contents (anti-tampering)
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
Table 1 • Automotive ProASIC3 Product Family
ProASIC3 Devices
System Gates
A3P060
60 k
1,536
18
A3P125
125 k
3,072
36
A3P250
250 k
6,144
36
A3P1000
1 M
24,576
144
32
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
4
8
8
FlashROM Bits
1 k
Yes
1
1 k
1 k
1 k
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals1
I/O Banks
Yes
1
Yes
1
Yes
1
18
18
18
18
2
2
4
4
Maximum User I/Os
96
133
157
300
Package Pins
VQFP
VQ100
FG144
VQ100
FG144
QNG132
VQ100
FG144, FG256
QNG132
FBGA
FG144, FG256, FG484
QFN2
Notes:
1. Six chip-wide (main) globals and three additional global networks in each quadrant are available.
2. QFN packages are available as RoHS compliant only.
January 2013
I
© 2013 Microsemi Corporation
Automotive ProASIC3 Flash Family FPGAs
I/Os Per Package
ProASIC3 Devices
A3P060
A3P125
A3P250
I/O Type
A3P1000
Package
VQ100
FG144
FG256
FG484
QNG132
Notes:
71
96
–
71
97
–
68
97
157
–
13
24
38
–
–
97
–
25
44
74
–
177
300
–
–
–
–
84
87
19
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide
to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of available single-ended I/Os by two.
3. FG256 and FG484 are footprint-compatible packages.
Automotive ProASIC3 Device Status
Automotive ProASIC3 Devices
Status
A3P060
Production
Production
Production
Production
A3P125
A3P250
A3P1000
II
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Automotive ProASIC3 Ordering Information
_
A3P1000
1
FG
G
144
Y
T
Application (Temperature Range)
T = Grade 2 and Grade 1 AEC-Q100
1
Grade 2 = 105°C TA and 115°C TJ1
Grade 1 = 125°C TA and 135°C TJ
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
=
=
=
VQ
FG
QN
Very Thin Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Quad Flat Pack (0.5 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
Automotive ProASIC3 Devices
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P1000 = 1,000,000 System Gates
Notes:
1. TA = Ambient temperature and TJ = Junction temperature.
2. Minimum order quantities apply. Contact your local Microsemi SoC Products Group sales office for details.
Revision 5
III
Automotive ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
VQ100
FG144
FG256
FG484
QNG132
Notes:
A3P060
A3P125
C, I, T
C, I, T
–
A3P250
C, I, T
C, I, T
C, I, T
–
A3P1000
–
C, I, T
C, I, T
C, I, T
C, I, T
C, I, T
–
–
–
–
–
C, I, T
C, I, T
1. C = Commercial temperature range: 0°C to 70°C
2. I = Industrial temperature range: –40°C to 85°C
3. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C TA and 115°C TJ
Grade 1 = 125°C TA and 135°C TJ
4. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs datasheet.
Speed Grade and Temperature Grade Matrix
Temperature Grade
Std.
–1
T (Grade 1 and Grade 2), Commercial, Industrial
3
3
Notes:
1. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C TA and 115°C TJ
Grade 1 = 125°C TA and 135°C TJ
2. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs datasheet.
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
IV
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table of Contents
Automotive ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Automotive ProASIC3 DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Package Pin Assignments
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Revision 5
V
1 – Automotive ProASIC3 Device Family Overview
General Description
Automotive ProASIC3 nonvolatile flash technology gives automotive system designers the advantage of
a secure, low-power, single-chip solution that is Instant On. Automotive ProASIC3 is reprogrammable
and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create
high-density systems using existing ASIC or FPGA design flows and tools.
Automotive ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as
well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). Automotive
ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of SRAM and up to
300 user I/Os.
Automotive ProASIC3 devices are the only firm-error-immune automotive grade FPGAs. Firm-error
immunity makes them ideally suited for demanding applications in powertrain, safety, and telematics-
based subsystems, where firm-error failure is not an option.
Firm errors in SRAM-based FPGAs can result in high defect levels in field-deployed systems. These
unavoidable defects must be considered separately from standard defects and failure mechanisms when
looking at overall system quality and reliability.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based Automotive ProASIC3 devices allow all functionality to be Instant On; no
external boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Flash-based FPGAs are LAPU Class
0 devices, offering the lowest available power in a single-chip device and providing firm-error immunity.
The Automotive ProASIC3 family device architecture mitigates the need for ASIC migration at high user
volumes. This makes the Automotive ProASIC3 family a cost-effective ASIC replacement solution,
especially for automotive applications.
Security
Nonvolatile, flash-based Automotive ProASIC3 devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. Automotive ProASIC3 devices incorporate
FlashLock, which provides a unique combination of reprogrammability and design security without
external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
Automotive ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the
highest level of protection in the FPGA industry for intellectual property and configuration data. In
addition, all FlashROM data in Automotive ProASIC3 devices can be encrypted prior to loading, using
the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES was adopted by
the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.
Automotive ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that
make them the most comprehensive programmable logic device security solution available today.
Automotive ProASIC3 devices with AES-based security provide a high level of protection for secure,
remote field updates over public networks such as the Internet, and are designed to ensure that valuable
IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Additionally, security
features of Automotive ProASIC3 devices provide anti-tampering protection.
Security, built into the FPGA fabric, is an inherent component of the Automotive ProASIC3 family. The
flash cells are located beneath seven metal layers, and many device design and layout techniques have
been used to make invasive attacks extremely difficult. The Automotive ProASIC3 family, with FlashLock
and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your
valuable IP is protected with industry-standard security, making remote ISP possible. An Automotive
ProASIC3 device provides the best available security for programmable logic designs.
Revision 5
1-1
Automotive ProASIC3 Device Family Overview
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Automotive
ProASIC3 FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area,
and increases security and system reliability.
Instant On
The Microsemi flash-based Automotive ProASIC3 devices support Level 0 of the Instant On classification
standard. This feature helps in system component initialization, execution of critical tasks before the
processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The Instant On feature of flash-based Automotive ProASIC3 devices greatly simplifies
total system design and reduces total system cost, often eliminating the need for CPLDs and external
clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the
Automotive ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not
have to be reloaded when system power is restored. This enables the reduction or complete removal of
the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices
from the PCB design. Flash-based Automotive ProASIC3 devices simplify total system design and
reduce cost and design risk while increasing system reliability and improving system initialization time.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of Automotive ProASIC3
flash-based FPGAs. Once it is programmed, the flash cell configuration element of Automotive ProASIC3
FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or
soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using
error detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based Automotive ProASIC3 devices exhibit very low power characteristics, similar to those of an
ASIC, making them an ideal choice for power-sensitive applications. Automotive ProASIC3 devices have
only a very limited power-on current surge and no high-current transition period, both of which occur on
many FPGAs.
Automotive ProASIC3 devices also have low dynamic power consumption to further maximize power
savings.
Advanced Flash Technology
The Automotive ProASIC3 family offers many benefits, including nonvolatility and reprogrammability,
through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard
CMOS design techniques are used to implement logic and control functions. The combination of fine
granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic
utilization without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
1-2
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Advanced Architecture
The proprietary Automotive ProASIC3 architecture provides granularity comparable to standard-cell
ASICs. The Automotive ProASIC3 device consists of five distinct and programmable architectural
features (Figure 1-1 and Figure 1-2 on page 1-4):
•
•
•
•
•
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM memory
Extensive CCCs and PLLs
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the Automotive ProASIC3 core tile as either a three-input lookup table
(LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The
VersaTile capability is unique to the Microsemi ProASIC family of third-generation-architecture flash
FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are
distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming.
Maximum core utilization is possible for virtually any design.
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 1
Figure 1-1 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125)
Revision 5
1-3
Automotive ProASIC3 Device Family Overview
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
(A3P600 and A3P1000)
Bank 2
Figure 1-2 • Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P600 and A3P1000)
VersaTiles
The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the
ProASICPLUS® core tiles. The Automotive ProASIC3 VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
1-4
Revision 5
Automotive ProASIC3 Flash Family FPGAs
User Nonvolatile FlashROM
Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
•
•
•
•
•
•
•
•
Unique protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, infotainment systems)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard Automotive ProASIC3 IEEE 1532 JTAG programming
interface.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
Automotive ProASIC3 development software solutions, Libero® System-on-Chip (SoC) and Designer,
have extensive support for the FlashROM. One such feature is auto-generation of sequential
programming files for applications requiring a unique serial number in each part. Another feature allows
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly
and easily using Libero SoC and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM
Automotive ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each
variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can
be configured with different bit widths on each port. For example, data can be sent through a 4-bit port
and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
PLL and CCC
Automotive ProASIC3 devices provide designers with very flexible clock conditioning circuit (CCC)
capabilities. Each member of the Automotive ProASIC3 family contains six CCCs. One CCC (center west
side) has a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Revision 5
1-5
Automotive ProASIC3 Device Family Overview
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
•
•
•
•
Maximum acquisition time is 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 350 MHz /
f
OUT_CCC (for PLL only)
Global Clocking
Automotive ProASIC3 devices have extensive support for multiple clocking domains. In addition to the
CCC and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The Automotive ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of
voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3 FPGAs support many different I/O
standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
Automotive ProASIC3 banks for the A3P250 and A3P1000 devices support LVPECL, LVDS, B-LVDS,
and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-4 on page 1-7).
1-6
Revision 5
Automotive ProASIC3 Flash Family FPGAs
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tristate: I/O is tristated
Figure 1-4 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
Revision 5
1-7
2 – Automotive ProASIC3 DC and Switching
Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximums are stress ratings only; functional operation of the device at these or any other
conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on
page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
V
VJTAG
–0.3 to 3.75
VPUMP Programming voltage
–0.3 to 3.75
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
–0.3 to 3.75
VCCI
VMV
VI
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 to 3.75
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+150
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-3 on page 2-3.
2. For flash programming and retention maximum limits, refer to Figure 2-1 on page 2-2. For recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 5
2-1
Automotive ProASIC3 DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions
Symbol
TJ
Parameter
Junction temperature
Automotive Grade 1 Automotive Grade 2 Units
–40 to +135
1.425 to 1.575
1.4 to 3.6
–40 to +115
1.425 to 1.575
1.4 to 3.6
°C
V
V
V
V
V
V
V
V
V
V
V
VCC
1.5 V DC core supply voltage
JTAG DC voltage
VJTAG
VPUMP
Programming voltage Programming Mode 3
Operation 4
3.15 to 3.45
0 to 3.6
3.15 to 3.45
0 to 3.6
VCCPLL
Analog power supply (PLL)
and 1.5 V DC supply voltage
1.8 V DC supply voltage
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
VCCI
VMV
2.5 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
3.3 V DC supply voltage
3.0 to 3.6
3.0 to 3.6
LVDS/B-LVDS/M-LVDS differential I/O
LVPECL differential I/O
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
Notes:
1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-14 on page 2-16. VMV and V should be at the same voltage within a given I/O bank.
CCI
2. All parameters representing voltages are measured with respect to GND unless otherwise specified.
3. The programming temperature range supported is T = 0°C to 85°C.
ambient
4.
V
can be left floating during operation (not programming mode).
PUMP
110
100
90
80
70
60
50
40
30
20
10
0
HTR
Lifetime
(yrs)
Tj (°C)
70
85
100
105
102.7
43.8
20.0
15.6
110
115
120
125
130
12.3
9.7
7.7
6.2
5.0
135
140
145
150
4.0
3.3
2.7
2.2
70 85 100 105 110 115 120 125 130 135 140 145 150
Temperature (ºC)
Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.
Figure 2-1 • High-Temperature Data Retention (HTR)
2-2
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-3 • Overshoot and Undershoot Limits (as measured on quiet I/Os)
VCCI and
VMV
Average VCCI–GND Overshoot or Undershoot Maximum Overshoot/ Maximum Overshoot/
Duration as a Percentage of Clock Cycle
Undershoot (115°C)
Undershoot (135°C)
2.7 V or less
10%
5%
0.81 V
0.90 V
0.80 V
0.90 V
0.79 V
0.88 V
N/A
0.72 V
0.82 V
0.72 V
0.81 V
0.69 V
0.79 V
N/A
3 V
10%
5%
3.3 V
10%
5%
3.6 V
10%
5%
N/A
N/A
Notes:
1. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot
occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
2. This table refers only to overshoot/undershoot limits for simultaneously switching I/Os and does not provide PCI
overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2
on page 2-4.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
Revision 5
2-3
Automotive ProASIC3 DC and Switching Characteristics
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Region 1: I/O buffers are OFF
Vd = 0.75 V ± 0.25 V
VCCI
Activation trip point:
a = 0.9 V ± 0.3 V
Deactivation trip point:
d = 0.8 V ± 0.3 V
Min VCCI datasheet specification
V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
V
Figure 2-2 • I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because dynamic and static power consumption cause the
chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Table 2-4 on page 2-5.
P = Power dissipation
2-4
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction
temperature is 110°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 110C – 70C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 1.951 W
ja(C/W)
20.5°C/W
EQ 2
Table 2-4 • Package Thermal Resistivities
ja
200
ft./min. ft./min. Units
Pin
Count jc
Still
Air
500
Package Type
Device
Very Thin Quad Flat Pack (VQFP)
Fine Pitch Ball Grid Array (FBGA)
All devices
See note*
See note*
See note*
A3P1000
A3P1000
A3P1000
100
144
256
484
144
256
484
10.0 35.3
3.8 26.9
3.8 26.6
3.2 20.5
6.3 31.6
6.6 28.1
8.0 23.3
29.4
22.9
22.8
17.0
26.2
24.4
19.0
27.1
21.5
21.5
15.9
24.2
22.7
16.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package
thermal information will be available in future revisions of the datasheet.
Temperature and Voltage Derating Factors
Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 115°C, VCC = 1.425 V)
Array Voltage VCC (V)
–40°C
0.83
0°C
0.88
0.83
0.80
25°C
0.90
0.85
0.82
70°C
0.95
0.90
0.87
85°C
0.97
0.92
0.88
115°C 125°C 135°C
1.425
1.5
1.00
0.95
0.91
1.01
0.96
0.93
1.02
0.97
0.94
0.79
1.575
0.76
Revision 5
2-5
Automotive ProASIC3 DC and Switching Characteristics
Calculating Power Dissipation
Quiescent Supply Current
Table 2-6 • Quiescent Supply Current Characteristics
A3P060
A3P125
2 mA
A3P250
3 mA
A3P1000
8 mA
Typical (25°C)
2 mA
53 mA
26 mA
Maximum (Automotive Grade 1) – 135°C
Maximum (Automotive Grade 2) – 115°C
53 mA
26 mA
106 mA
53 mA
265 mA
131 mA
Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static
contribution, which is shown in Table 2-7 and Table 2-10 on page 2-8.
Power per I/O Pin
Table 2-7 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Advanced I/O Banks
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
16.69
5.12
2.13
1.45
18.11
18.11
3.3 V PCI-X
Differential
LVDS
2.5
3.3
2.26
5.72
1.20
1.87
LVPECL
Notes:
1.
2.
P
P
is the static power (where applicable) measured on VMV.
DC2
AC9
is the total dynamic power measured on V and VMV.
CC
2-6
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Standard Plus I/O Banks
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
16.72
5.14
2.13
1.48
18.13
18.13
3.3 V PCI-X
Notes:
1.
2.
P
P
is the static power (where applicable) measured on VMV.
DC2
AC9
is the total dynamic power measured on V and VMV.
CC
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Advanced I/O Banks
Static Power
PDC3 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL /
35
3.3
–
468.67
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
35
35
35
2.5
1.8
1.5
–
–
–
267.48
149.46
103.12
1.5 V LVCMOS
(JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
10
10
3.3
3.3
–
–
201.02
201.02
–
–
2.5
3.3
7.74
88.92
LVPECL
Notes:
19.54
166.52
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2.
P
is the static power (where applicable) measured on VMV.
DC3
3.
P
is the total dynamic power measured on V
and VMV.
AC10
CCI
Revision 5
2-7
Automotive ProASIC3 DC and Switching Characteristics
Table 2-10 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1
Applicable to Standard Plus I/O Banks
Static Power
PDC3 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL /
35
3.3
–
452.67
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
35
35
35
2.5
1.8
1.5
–
–
–
258.32
133.59
92.84
1.5 V LVCMOS
(JESD8-11)
3.3 V PCI
3.3 V PCI-X
Notes:
10
10
3.3
3.3
–
–
184.92
184.92
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2. PDC3 is the static power (where applicable) measured on VMV.
3. PAC10 is the total dynamic power measured on VCCI and VMV.
2-8
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Power Consumption of Various Internal Resources
Table 2-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
Device Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
A3P1000 A3P250 A3P125 A3P060
14.50
2.48
11.00
1.58
11.00
0.81
9.30
0.81
PAC2
Clock contribution of a Global Spine
PAC3
Clock contribution of a VersaTile row
0.81
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
0.12
0.07
0.29
0.29
0.70
PAC5
PAC6
PAC7
PAC8
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
See Table 2-7 on page 2-6.
PAC10
See Table 2-7 and Table 2-10 on
page 2-8.
PAC11
PAC12
PAC13
PAC14
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Static PLL contribution
25.00
30.00
2.55 mW
2.60
Dynamic contribution for PLL
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
spreadsheet calculator or SmartPower tool in Libero SoC.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on
page 2-11.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-13 on
page 2-12.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-13 on page 2-12. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
P
Revision 5
2-9
Automotive ProASIC3 DC and Switching Characteristics
Total Static Power Consumption—P
STAT
PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the Automotive ProASIC3 FPGA
Fabric User's Guide.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in the Automotive
ProASIC3 FPGA Fabric User's Guide.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
F
N
Sequential Cells Contribution—P
S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
2-10
Revision 5
Automotive ProASIC3 Flash Family FPGAs
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-12.
FCLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on page 2-12.
PLL Contribution—P
F
PLL
PPLL = PAC13 + PAC14 * FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT is the output clock frequency.1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
1
2
10%
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
Revision 5
2-11
Automotive ProASIC3 DC and Switching Characteristics
Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
1
2
3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
User I/O Characteristics
Timing Model
I/O Module
(non-registered)
Combinational Cell
Combinational Cell
Y
LVPECL (applicable to
Advanced I/O banks only)
Y
tPD = 0.67 ns
tPD = 0.58 ns
tDP = 1.66 ns
I/O Module
(non-registered)
Combinational Cell
Y
Output Drive Strength = 12 mA
High Slew Rate
LVTTL
tDP = 3.25 ns (Advanced I/O banks)
tPD = 1.04 ns
I/O Module
(non-registered)
Combinational Cell
I/O Module
(registered)
Y
Output drive Strength = 8 mA
High Slew Rate
LVTTL
tPY = 1.29 ns
tDP = 4.52 ns (Advanced I/O banks)
LVPECL
(applicable
to Advanced
I/O banks only)
t
PD = 0.60 ns
I/O Module
(non-registered)
D
Q
Combinational Cell
Y
Output Drive Strength = 4 mA
High Slew Rate
LVCMOS 1.5 V
tICLKQ = 0.29 ns
tISUD = 0.31 ns
tDP = 4.89 ns (Advanced I/O banks)
tPD = 0.56 ns
Input LVTTL
Clock
I/O Module
(registered)
Register Cell
Register Cell
Combinational Cell
Y
tPY = 0.94 ns (Advanced I/O banks)
LVTTL 3.3 V Output Drive
Strength = 12 mA
High Slew Rate
D
Q
D
Q
D
Q
I/O Module
(non-registered)
tPD = 0.56 ns
tDP = 3.25 ns
(Advanced I/O banks)
tOCLKQ = 0.70 ns
OSUD = 0.37 ns
tCLKQ = 0.66 ns
tSUD = 0.51 ns
tCLKQ = 0.66 ns
tSUD = 0.51 ns
LVDS,
BLVDS,
t
M-LVDS
(Applicable for
Advanced I/O
Banks only)
Input LVTTL
Clock
Input LVTTL
Clock
tPY = 1.47 ns
tPY = 0.94 ns
t
PY = 0.94 ns
(Advanced I/O banks)
(Advanced I/O banks)
Figure 2-3 • Timing Model
Operating Conditions: –1 Speed, Automotive Grade 2 Temp. Range (TJ = 115°C), Worst Case
VCC = 1.425 V
2-12
Revision 5
Automotive ProASIC3 Flash Family FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
t
t
PY = MAX(tPY(R), tPY(F))
DIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
Revision 5
2-13
Automotive ProASIC3 DC and Switching Characteristics
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
VCC
50%
50%
D
0 V
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
2-14
Revision 5
Automotive ProASIC3 Flash Family FPGAs
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
Revision 5
2-15
Automotive ProASIC3 DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH
Drive Slew Min.
Strength Rate
Max.
V
Max.
V
Min.
V
I/O Standard
V
V
mA mA
3.3 V LVTTL /
12 mA High –0.3
0.8
2
3.6
0.4
2.4
12 12
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA High –0.3
0.7
1.7
3.6
3.6
0.7
1.7
12 12
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI
12 mA High –0.3 0.30 * VCCI 0.7 * VCCI
0.45
VCCI – 0.45 12 12
3.6 0.25 * VCCI 0.75 * VCCI 12 12
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Note: Currents are measured at 125°C junction temperature.
Table 2-15 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
VIL
VIH
VOL
VOH
IOL IOH
Drive
Slew
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard Strength Rate
mA mA
3.3 V LVTTL /
3.3 V
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12 12
LVCMOS
2.5 V
LVCMOS
12 mA
8 mA
4 mA
High
High
High
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
1.7
12 12
1.8 V
LVCMOS
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
0.45
VCCI – 0.45
8
4
8
4
1.5 V
0.25 * VCCI 0.75 * VCCI
LVCMOS
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Note: Currents are measured at 125°C junction temperature.
2-16
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-16 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH
mA mA
Drive
Strength Rate
Slew Min.
Max.
V
Max.
V
Min.
V
I/O Standard
V
V
3.3 V LVTTL /
8 mA
High –0.3
0.8
2
3.6
0.4
2.4
8
8
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
8 mA
4 mA
2 mA
High –0.3
0.7
1.7
3.6
3.6
0.7
1.7
8
4
2
8
4
2
High –0.3 0.35 * VCCI 0.65 * VCCI
High –0.3 0.30 * VCCI 0.7 * VCCI
0.45
VCCI – 0.45
3.6 0.25 * VCCI 0.75 * VCCI
Note: Currents are measured at 125°C junction temperature.
Table 2-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Automotive Grade 1 and
Grade 2
Automotive Grade 1 1
Automotive Grade 2 2
IIL
µA
10
10
10
10
10
10
IIH
µA
10
10
10
10
10
10
IIL
µA
15
15
15
15
15
15
IIH
µA
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Notes:
1. Automotive range Grade 1 (–40°C < T < 135°C)
J
2. Automotive range Grade 2 (–40°C < T < 115°C)
J
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-18 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
1.4 V
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
Revision 5
2-17
Automotive ProASIC3 DC and Switching Characteristics
Table 2-19 • I/O AC Parameter Definitions
Parameter
Parameter Definition
Data-to-Pad delay through the Output Buffer
tDP
tPY
Pad-to-Data delay through the Input Buffer
tDOUT
tEOUT
tDIN
tHZ
Data–to–Output Buffer delay through the I/O interface
Enable–to–Output Buffer Tristate Control delay through the I/O interface
Input Buffer–to–Data delay through the I/O interface
Enable-to-Pad delay through the Output Buffer—High to Z
Enable-to-Pad delay through the Output Buffer—Z to High
Enable-to-Pad delay through the Output Buffer—Low to Z
Enable-to-Pad delay through the Output Buffer—Z to Low
Enable-to-Pad delay through the Output Buffer with delayed enable—Z to High
Enable-to-Pad delay through the Output Buffer with delayed enable—Z to Low
tZH
tLZ
tZL
tZHS
tZLS
Table 2-20 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Worst Case VCCI = 3.0 V
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA High 35 pF
–
0.53 3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37 2.71 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High 35 pF
1.8 V LVCMOS 12 mA High 35 pF
1.5 V LVCMOS 12 mA High 35 pF
–
–
–
0.53 3.28 0.04 1.19 0.38 3.34 3.16 1.77 1.80 5.39 5.22 ns
0.53 3.25 0.04 1.12 0.38 1.89 1.63 3.41 3.75 3.06 2.82 ns
0.53 3.75 0.04 1.32 0.38 2.18 1.91 3.63 3.87 3.35 3.11 ns
3.3 V PCI
Per PCI High 10 pF 25 2 0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns
spec
3.3 V PCI-X
Per PCI-X High 10 pF 25 2 0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns
spec
LVDS
24 mA High
24 mA High
–
–
–
–
0.53 1.68 0.04 1.47
0.53 1.66 0.04 1.29
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-48 for
connectivity. This resistor is not required during normal operation.
2-18
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-21 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Worst Case VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA High 35 pF
–
0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High 35 pF
–
–
–
0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns
0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns
0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
8 mA
High 35 pF
4 mA
High 35 pF
Per PCI High 10 pF 25 2 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns
spec
3.3 V PCI-X
Per PCI-X High 10 pF 25 2 0.55 2.19 0.04 0.79 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns
spec
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-48 for
connectivity. This resistor is not required during normal operation.
Revision 5
2-19
Automotive ProASIC3 DC and Switching Characteristics
Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 135°C, Worst Case VCC = 1.425 V
Worst Case VCCI = 3.0 V
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA High 35 pF
–
0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High 35 pF
1.8 V LVCMOS 12 mA High 35 pF
1.5 V LVCMOS 12 mA High 35 pF
–
–
–
0.55 3.39 0.04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.39 ns
0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.92 ns
0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.21 ns
3.3 V PCI
Per PCI High 10 pF 25 2 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
spec
3.3 V PCI-X
Per PCI-X High 10 pF 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
spec
LVDS
24 mA High
24 mA High
–
–
–
–
0.55 1.74 0.04 1.52
0.55 1.71 0.04 1.34
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-48 for
connectivity. This resistor is not required during normal operation.
2-20
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Worst Case VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
12 mA High 35 pF
–
0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High 35 pF
–
–
–
0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns
0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns
0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
8 mA
High 35 pF
4 mA
High 35 pF
Per PCI High 10 pF 25 2 0.55 2.55 0.04 0.82 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
spec
3.3 V PCI-X
Per PCI-X High 10 pF 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
spec
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-48 for
connectivity. This resistor is not required during normal operation.
Revision 5
2-21
Automotive ProASIC3 DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-24 • Input Capacitance
Symbol
CIN
Definition
Input capacitance
Input capacitance on the clock pin
Conditions
Min. Max. Units
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
pF
pF
CINCLK
Table 2-25 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
()2
()3
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
25
16 mA
17
50
24 mA
11
33
2.5 V LVCMOS
1.8 V LVCMOS
2 mA
100
50
200
100
50
6 mA
12 mA
25
16 mA
20
40
24 mA
11
22
2 mA
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on V , drive strength selection, temperature, and process. For board design
CCI
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / I
(PULL-DOWN-MAX) OLspec
= (VCCImax – VOHspec) / I
(PULL-UP-MAX)
OHspec
2-22
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-26 • I/O Output Buffer Maximum Resistances1
Applicable to Standard Plus I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
()2
()3
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
25
16 mA
25
75
2.5 V LVCMOS
1.8 V LVCMOS
2 mA
100
50
200
100
50
6 mA
12 mA
25
2 mA
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
1.5 V LVCMOS
2 mA
4 mA
200
100
0
224
112
0
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
3.
R
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
Table 2-27 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
()
()
VCCI
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
Min.
10 k
11 k
18 k
19 k
Max.
45 k
55 k
70 k
90 k
Min.
10 k
12 k
17 k
19 k
Max.
45 k
74 k
110 k
140 k
1.
2.
R
R
= (VCCImax – VOHspec) / I
(WEAK PULL-UP-MAX)
(WEAK PULL-UP-MIN)
(WEAK PULL-DOWN-MIN)
= (VOLspec) / I
(WEAK PULL-DOWN-MAX)
Revision 5
2-23
Automotive ProASIC3 DC and Switching Characteristics
Table 2-28 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
Drive Strength
IOSL (mA)*
27
IOSH (mA)*
25
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
27
25
6 mA
54
51
8 mA
54
51
12 mA
16 mA
24 mA
2 mA
109
127
181
27
103
132
268
25
3.3 V LVCMOS
4 mA
27
25
6 mA
54
51
8 mA
54
51
12 mA
16 mA
24 mA
2 mA
109
127
181
18
103
132
268
16
2.5 V LVCMOS
6 mA
37
32
12 mA
16 mA
24 mA
2 mA
74
65
87
83
124
11
169
9
1.8 V LVCMOS
4 mA
22
17
6 mA
44
35
8 mA
51
45
12 mA
16 mA
2 mA
74
91
74
91
1.5 V LVCMOS
16
13
4 mA
33
25
6 mA
39
32
8 mA
55
66
12 mA
Per PCI/PCI-X specification
55
66
3.3 V PCI/PCI-X
109
103
Note: *TJ = 100°C
2-24
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-29 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
Drive Strength
IOSL (mA)*
27
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
25
25
51
51
103
103
16
32
65
9
4 mA
27
6 mA
54
8 mA
54
12 mA
109
109
18
16 mA
2.5 V LVCMOS
1.8 V LVCMOS
2 mA
6 mA
37
12 mA
74
2 mA
11
4 mA
22
17
35
35
13
25
103
6 mA
44
8 mA
44
1.5 V LVCMOS
2 mA
4 mA
16
33
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
109
Note: *TJ = 100°C
The length of time an I/O can withstand IOSH OSL events depends on the junction temperature. The
/I
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection, but
such protection would only be needed in extremely prolonged stress conditions.
Table 2-30 • Duration of Short Circuit Event before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
110°C
125°C
135°
6 months
3 months
25 days
12 days
Revision 5
2-25
Automotive ProASIC3 DC and Switching Characteristics
Table 2-31 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Rise/Fall Time
(min.)
Input Rise/Fall Time
(max.)
Input Buffer
Reliability
LVTTL/LVCMOS
No requirement
No requirement
10 ns *
10 ns *
20 years (110°C)
10 years (100°C)
LVDS/B-LVDS/M-
LVDS/LVPECL
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, the rise time and fall time of input buffers can be increased beyond the maximum
value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure there
is no excessive noise coupling into input signals.
2-26
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-32 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
V
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
8
2
4
6
8
27
27
25
25
4 mA
6 mA
54
51
8 mA
54
51
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
109
127
181
103
132
268
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-33 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
V
mA mA
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
8
2
4
6
8
27
27
25
25
4 mA
6 mA
54
51
8 mA
54
51
12 mA
16 mA
Notes:
12 12
16 16
109
109
103
103
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Revision 5
2-27
Automotive ProASIC3 DC and Switching Characteristics
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Datapath
Test Point
Enable Path
35 pF
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
35
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
2-28
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
8.56 0.05 1.14
7.28 0.04 0.97
5.49 0.05 1.14
4.67 0.04 0.97
5.49 0.05 1.14
4.67 0.04 0.97
3.95 0.05 1.14
3.36 0.04 0.97
3.73 0.05 1.14
3.17 0.04 0.97
3.44 0.05 1.14
2.92 0.04 0.97
8.72 7.37 1.46 1.42 11.22 9.866
7.42 6.27 1.46 1.42
5.59 4.55 1.65 1.74
4.75 3.87 1.65 1.74
5.59 4.55 1.65 1.74
4.75 3.87 1.65 1.74
4.02 1.56 3.59 1.94
3.42 1.56 3.05 1.94
1.84 1.42 3.65 4.11
1.84 1.42 3.10 3.50
1.70 1.17 3.72 4.54
1.70 1.17 3.16 3.86
9.54
8.09
6.88
8.09
6.88
6.52
5.55
3.05
3.05
2.91
2.91
8.393
7.05
ns
6 mA
STD
-1
ns
5.997
7.05
ns
8 mA
STD
-1
ns
5.997
2.795
2.797
2.651
2.653
2.405
2.407
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
11.47 0.05 1.14 0.46
9.75 0.04 0.97 0.39
8.13 0.05 1.14 0.46
6.92 0.04 0.97 0.39
8.13 0.05 1.14 0.46
6.92 0.04 0.97 0.39
6.24 0.05 1.14 0.46
5.31 0.04 0.97 0.39
5.82 0.05 1.14 0.46
4.95 0.04 0.97 0.39
5.42 0.05 1.14 0.46
4.61 0.04 0.97 0.39
11.68 9.95 1.46 1.33 14.18 12.449
9.94 8.46 1.46 1.33 12.06
8.28 7.03 1.65 1.65 10.79
7.05 5.98 1.65 1.65 9.17
8.28 7.03 1.65 1.65 10.79
7.05 5.98 1.65 1.65 9.17
6.36 5.45 1.77 1.85 8.86
5.41 4.63 1.77 1.85 7.53
5.93 5.10 1.80 1.90 8.43
5.04 4.34 1.80 1.90 7.17
5.52 5.08 1.83 2.10 8.02
10.59
9.526
8.103
9.526
8.103
7.946
6.76
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
7.604
6.468
7.581
6.449
ns
ns
STD
-1
ns
4.70 4.32 1.83 2.11
6.82
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-29
Automotive ProASIC3 DC and Switching Characteristics
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
8.06 0.05 1.12
6.85 0.04 .095
5.03 0.05 1.12
4.28 0.04 0.95
5.03 0.05 1.12
4.28 0.04 0.95
3.53 0.05 1.12
3.01 0.04 0.95
3.53 0.05 1.12
3.01 0.04 0.95
8.20 7.03 1.26 1.27 8.20 7.027
6.98 5.98 1.26 1.27 6.98 5.978
5.13 4.27 1.42 1.56 5.13 4.267
ns
6 mA
STD
-1
ns
4.36 3.63 1.42 1.56 4.36
5.13 4.27 1.42 1.56 5.13 4.267
4.36 3.63 1.42 1.56 4.36 3.63
3.63
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
Notes:
STD
-1
1.74 1.43 3.12 3.60 1.74 1.427
1.74 1.43 2.65 3.06 1.74 1.428
1.74 1.43 3.12 3.60 1.74 1.427
1.74 1.43 2.65 3.06 1.74 1.428
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
10.82 0.05 1.12
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
11.02 9.42 1.26 1.20 11.02 9.419
9.21
7.49
6.37
7.49
6.37
5.64
4.80
5.64
4.80
0.04 0.95
0.05 1.12
0.04 0.95
0.05 1.12
0.04 0.95
0.05 1.12
0.04 0.95
0.05 1.12
0.04 0.95
9.38
7.63
6.49
7.63
6.49
5.75
4.89
5.75
4.89
8.01 1.26 1.20
6.58 1.43 1.48
5.60 1.43 1.49
6.58 1.43 1.48
5.60 1.43 1.49
5.04 1.54 1.67
4.29 1.54 1.67
5.04 1.54 1.67
4.29 1.54 1.67
9.38
7.63
6.49
7.63
6.49
5.75
4.89
5.75
4.89
8.012
6.58
ns
STD
-1
ns
5.598
6.58
ns
STD
-1
ns
5.598
5.042
4.289
5.042
4.289
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-30
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
8.28 0.05 1.10
7.05 0.04 0.94
5.31 0.05 1.10
4.52 0.04 0.94
5.31 0.05 1.10
4.52 0.04 0.94
3.82 0.05 1.10
3.25 0.04 0.94
3.60 0.05 1.10
3.07 0.04 0.94
3.33 0.05 1.10
2.83 0.04 0.94
8.44 7.13 1.42 1.37 10.85 9.55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.18 6.06 1.42 1.37
5.41 4.40 1.60 1.68
4.60 3.74 1.60 1.68
5.41 4.40 1.60 1.68
4.60 3.74 1.60 1.68
3.89 1.51 3.47 1.88
3.31 1.51 2.96 1.88
1.78 1.37 3.53 3.98
1.78 1.37 3.00 3.38
1.64 1.13 3.60 4.39
1.64 1.13 3.06 3.74
9.23
7.83
6.66
7.83
6.66
6.31
5.37
2.95
2.95
2.81
2.82
8.12
6.82
5.80
6.82
5.80
2.70
2.71
2.57
2.57
2.33
2.33
6 mA
STD
-1
8 mA
STD
-1
12 mA
16 mA
24 mA
Notes:
STD
-1
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
11.09 0.05 1.10
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
11.30 9.63 1.41 1.29 13.72 12.04
9.44
7.87
6.69
7.87
6.69
6.04
5.14
5.63
4.79
5.25
4.46
0.04 0.94
0.05 1.10
0.04 0.94
0.05 1.10
0.04 0.94
0.05 1.10
0.04 0.94
0.05 1.10
0.04 0.94
0.05 1.10
0.04 0.94
9.61
8.02
6.82
8.02
6.82
6.15
5.23
5.74
4.88
5.34
4.55
8.19 1.41 1.29 11.67 10.25
ns
6 mA
STD
-1
6.80 1.59 1.59 10.43
5.78 1.59 1.60 8.88
6.80 1.59 1.59 10.43
9.22
7.84
9.22
7.84
7.69
6.54
7.36
6.26
7.34
6.24
ns
ns
8 mA
STD
-1
ns
5.78 1.59 1.60
5.27 1.71 1.79
4.48 1.71 1.79
4.94 1.74 1.84
4.20 1.74 1.84
4.92 1.77 2.04
4.18 1.77 2.04
8.88
8.57
7.29
8.16
6.94
7.76
6.60
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-31
Automotive ProASIC3 DC and Switching Characteristics
Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade
STD
-1
tDOUT
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
tDP
tDIN
tPY
tEOUT
0.45
0.39
0.45
0.39
0.45
0.39
0.45
0.39
0.45
0.39
tZL
tZH
tLZ
tHZ
tZLS tZHS Units
4 mA
7.79 0.05 1.08
6.85 0.04 0.95
4.87 0.05 1.08
4.28 0.04 0.95
4.87 0.05 1.08
4.28 0.04 0.95
3.42 0.05 1.08
3.01 0.04 0.95
3.42 0.05 1.08
3.01 0.04 0.95
7.94 6.80 1.22 1.23 7.94 6.80
6.98 5.98 1.26 1.27 6.98 5.98
4.96 4.13 1.38 1.51 4.96 4.13
4.36 3.63 1.42 1.56 4.36 3.63
4.96 4.13 1.38 1.51 4.96 4.13
4.36 3.63 1.42 1.56 4.36 3.63
1.69 1.38 3.02 3.48 1.69 1.38
1.74 1.43 2.65 3.06 1.74 1.43
1.69 1.38 3.02 3.48 1.69 1.38
1.74 1.43 2.65 3.06 1.74 1.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
STD
-1
8 mA
STD
-1
12 mA
16 mA
Notes:
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.39
0.45
0.39
0.45
0.39
0.45
0.39
0.45
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
10.47 0.05 1.08
10.66 9.11 1.22 1.16 10.66 9.11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.21
7.25
6.37
7.25
6.37
5.46
4.80
5.46
4.80
0.04 0.95
0.05 1.08
0.04 0.95
0.05 1.08
0.04 0.95
0.05 1.08
0.04 0.95
0.05 1.08
0.04 0.95
9.38
7.38
6.49
7.38
6.49
5.56
4.89
5.56
4.89
8.01 1.26 1.20
6.37 1.38 1.44
5.60 1.43 1.49
6.37 1.38 1.44
5.60 1.43 1.49
4.88 1.49 1.61
4.29 1.54 1.67
4.88 1.49 1.61
4.29 1.54 1.67
9.38
7.38
6.49
7.38
6.49
5.56
4.89
5.56
4.89
8.01
6.37
5.60
6.37
5.60
4.88
4.29
4.88
4.29
STD
-1
STD
-1
STD
-1
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-32
Revision 5
Automotive ProASIC3 Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-43 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
µA2 µA2
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
6
2
6
18
37
16
32
6 mA
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
74
65
87
83
124
169
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-44 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
V
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
–0.3
–0.3
–0.3
0.7
0.7
0.7
1.7
1.7
1.7
3.6
3.6
3.6
0.7
0.7
0.7
1.7
1.7
1.7
2
6
2
6
18
37
74
16
32
65
10 10
10 10
10 10
6 mA
12 mA
Notes:
12 12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
35
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
Revision 5
2-33
Automotive ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-46 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
9.69 0.05 1.45
8.24 0.04 1.23
5.78 0.05 1.45
4.91 0.04 1.23
3.98 0.05 1.45
3.39 0.04 1.23
3.75 0.05 1.45
3.19 0.04 1.23
3.45 0.05 1.45
2.94 0.04 1.23
8.76 9.69 1.48 1.25 11.26 12.187
7.45 8.24 1.48 1.25
5.63 5.78 1.68 1.62
4.79 4.91 1.69 1.63
4.05 3.84 1.82 1.86
3.45 3.27 1.83 1.86
1.85 1.69 3.76 3.97
1.85 1.69 3.20 3.38
1.70 1.35 3.84 4.47
1.71 1.35 3.27 3.80
9.58
8.13
6.92
6.55
5.58
3.06
3.06
2.92
2.92
10.367
8.277
7.04
ns
6 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
6.338
5.392
2.926
2.929
2.585
2.586
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-47 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
12.12 0.05 1.45 0.46 12.54 12.74 1.48 1.19 15.04 15.243
10.31 0.04 1.23 0.39 10.67 10.84 1.48 1.20 12.80 12.966
ns
6 mA
STD
-1
8.24 0.05 1.45 0.46
7.01 0.04 1.23 0.39
6.91 0.05 1.45 0.46
5.88 0.04 1.23 0.39
6.44 0.05 1.45 0.46
5.48 0.04 1.23 0.39
6.16 0.05 1.45 0.46
5.24 0.04 1.23 0.39
9.07
7.71
7.04
5.99
6.56
5.58
6.15
5.23
8.74 1.68 1.57 11.57 11.237
ns
7.43 1.69 1.57 9.84
6.62 1.82 1.80 9.54
5.63 1.83 1.80 8.11
6.18 1.86 1.86 9.06
5.26 1.86 1.86 7.71
6.16 1.90 2.10 8.65
5.24 1.90 2.10 7.36
9.559
9.117
7.756
8.678
7.382
8.657
7.364
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-34
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-48 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
9.26 0.05 1.45
7.87 0.04 1.23
5.43 0.05 1.45
4.62 0.04 1.23
3.59 0.05 1.45
3.05 0.04 1.23
8.28 9.26 1.24 1.12 10.78 11.756
7.05 7.87 1.24 1.13
5.19 5.43 1.43 1.47
4.42 4.62 1.43 1.47
3.65 3.51 1.56 1.69
3.11 2.99 1.56 1.69
9.17
7.69
6.55
6.15
5.23
10
ns
6 mA
STD
-1
7.926
6.743
6.012
5.114
ns
ns
12 mA
Notes:
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-49 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
12.12 0.05 1.45 0.46
10.31 0.04 1.23 0.39 10.12 10.31 1.25 1.08 12.24 12.438
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
6 mA
12 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
11.89 12.12 1.25 1.08 14.39 14.622
ns
STD
-1
8.24 0.05 1.45 0.46
7.01 0.04 1.23 0.39
6.30 0.05 1.45 0.46
5.35 0.04 1.23 0.39
8.39
7.14
6.41
5.45
8.23 1.43 1.42 10.89
7.00 1.43 1.42 9.26
6.16 1.56 1.63 8.91
5.24 1.56 1.63 7.58
10.73
9.128
8.656
7.364
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-35
Automotive ProASIC3 DC and Switching Characteristics
Table 2-50 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
9.37 0.05 1.40
7.97 0.04 1.19
5.59 0.05 1.40
4.75 0.04 1.19
3.85 0.05 1.40
3.28 0.04 1.19
3.63 0.05 1.40
3.08 0.04 1.19
3.34 0.05 1.40
2.84 0.04 1.19
8.47 9.37 1.43 1.21 10.89 11.79
7.21 7.97 1.43 1.21
5.45 5.59 1.63 1.57
4.63 4.75 1.63 1.57
3.92 3.71 1.77 1.80
3.34 3.16 1.77 1.80
1.79 1.64 3.64 3.84
1.79 1.64 3.09 3.27
1.65 1.31 3.72 4.32
1.65 1.31 3.16 3.68
9.27
7.87
6.69
6.34
5.39
2.96
2.96
2.82
2.82
10.03
8.01
6.81
6.13
5.22
2.83
2.83
2.50
2.50
ns
6 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-51 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
11.73 0.05 1.40 0.45
9.98 0.04 1.19 0.38
7.97 0.05 1.40 0.45
6.78 0.04 1.19 0.38
6.68 0.05 1.40 0.45
5.69 0.04 1.19 0.38
6.24 0.05 1.40 0.45
5.30 0.04 1.19 0.38
5.96 0.05 1.40 0.45
5.07 0.04 1.19 0.38
12.14 12.33 1.43 1.16 14.55 14.75
10.32 10.49 1.43 1.16 12.38 12.55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
STD
-1
8.77
7.46
6.81
5.79
6.35
5.40
5.95
5.06
8.45 1.63 1.51 11.19 10.87
7.19 1.63 1.52 9.52
6.40 1.77 1.74 9.23
5.45 1.77 1.74 7.85
5.98 1.80 1.80 8.77
5.08 1.80 1.80 7.46
5.96 1.84 2.03 8.37
5.07 1.84 2.03 7.12
9.25
8.82
7.50
8.40
7.14
8.38
7.12
12 mA
16 mA
24 mA
STD
-1
STD
-1
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-36
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-52 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
8.95 0.05 1.40
7.62 0.04 1.19
5.25 0.05 1.40
4.47 0.04 1.19
3.47 0.05 1.40
2.95 0.04 1.19
8.01 8.95 1.20 1.09 10.43 11.37
6.82 7.62 1.20 1.09
5.03 5.25 1.38 1.42
4.27 4.47 1.38 1.42
3.53 3.40 1.51 1.63
3.01 2.89 1.51 1.63
8.87
7.44
6.33
5.95
5.06
9.68
7.67
6.52
5.82
4.95
ns
6 mA
STD
-1
ns
ns
12 mA
Notes:
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-53 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
6 mA
12 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
11.73 0.05 1.40 0.45
9.98 0.04 1.19 0.38
7.97 0.05 1.40 0.45
6.78 0.04 1.19 0.38
6.09 0.05 1.40 0.45
5.18 0.04 1.19 0.38
11.51 11.73 1.21 1.04 13.93 14.15
ns
ns
ns
ns
ns
ns
9.79
8.12
6.91
6.20
5.28
9.98 1.21 1.04 11.85 12.03
7.96 1.38 1.37 10.54 10.38
STD
-1
6.77 1.39 1.37 8.96
5.96 1.51 1.58 8.62
5.07 1.51 1.58 7.33
8.83
8.38
7.12
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-37
Automotive ProASIC3 DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-54 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
µA2 µA2
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
3.6
3.6
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
11
22
44
51
74
74
9
4 mA
17
35
45
91
91
6 mA
8 mA
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 2-55 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
µA2 µA2
10 10
10 10
10 10
10 10
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
11
22
44
44
9
17
35
35
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-56 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
35
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
2-38
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-57 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
13.26 0.05 1.36 0.46 10.22 13.26 1.53 0.90 12.72 15.764
11.28 0.04 1.16 0.39
7.73 0.05 1.36 0.46
6.58 0.04 1.16 0.39
4.97 0.05 1.36 0.46
4.23 0.04 1.16 0.39
4.39 0.05 1.36 0.46
3.73 0.04 1.16 0.39
3.95 0.05 1.36 0.46
3.36 0.04 1.16 0.39
3.95 0.05 1.36 0.46
3.36 0.04 1.16 0.39
8.69
6.55
5.58
4.67
3.98
4.39
3.74
1.95
1.95
1.95
1.95
11.28 1.53 0.90 10.82
7.73 1.78 1.54 9.05
6.58 1.78 1.54 7.70
4.97 1.95 1.83 7.17
4.23 1.95 1.83 6.10
4.39 1.99 1.91 6.89
3.73 1.99 1.91 5.86
1.68 4.14 4.56 3.16
1.68 3.52 3.88 3.16
1.68 4.14 4.56 3.16
1.68 3.52 3.88 3.16
13.41
10.232
8.704
7.472
6.356
6.888
5.859
2.915
2.918
2.915
2.918
ns
4 mA
STD
-1
ns
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-39
Automotive ProASIC3 DC and Switching Characteristics
Table 2-58 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
17.36 0.05 1.45 0.46 15.78 17.36 1.53 0.87 18.28 19.864
14.77 0.04 1.23 0.39 13.42 14.77 1.54 0.87 15.55 16.897
ns
STD
-1
11.71 0.05 1.45 0.46
9.96 0.04 1.23 0.39
9.00 0.05 1.45 0.46
7.66 0.04 1.23 0.39
8.39 0.05 1.45 0.46
7.14 0.04 1.23 0.39
8.15 0.05 1.45 0.46
6.94 0.04 1.23 0.39
8.15 0.05 1.45 0.46
6.94 0.04 1.23 0.39
11.64 11.71 1.78 1.48 14.14 14.214
ns
9.90
9.17
7.80
8.54
7.27
8.09
6.88
8.09
6.88
9.96 1.78 1.48 12.03 12.091
8.77 1.95 1.77 11.67 11.267
ns
STD
-1
ns
7.46 1.95 1.77 9.92
8.16 1.99 1.85 11.04
6.94 1.99 1.85 9.40
9.585
10.66
9.068
ns
STD
-1
ns
ns
STD
-1
8.15 2.05 2.14 10.59 10.654
6.94 2.05 2.14 9.01 9.063
8.15 2.05 2.14 10.59 10.654
6.94 2.05 2.14 9.01 9.063
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-59 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
13.26 0.05 1.36 0.46 9.75 12.67 1.24 0.82 12.26
15.17
11.28 0.04 1.16 0.39 8.30 10.78 1.24 0.83 10.43 12.905
ns
STD
-1
7.73 0.05 1.36 0.46 6.13 7.25 1.46 1.41 8.63
6.58 0.04 1.16 0.39 5.21 6.17 1.46 1.41 7.34
4.97 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79
4.23 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78
4.39 0.05 1.36 0.46 4.29 4.54 1.62 1.68 6.79
3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78
9.749
8.293
7.039
5.987
7.039
5.987
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-40
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-60 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
17.36 0.05 1.45 0.46 15.09 16.55 1.24 0.79 17.59 19.052
14.77 0.04 1.23 0.39 12.84 14.08 1.24 0.79 14.96 16.207
11.71 0.05 1.45 0.46 10.88 11.07 1.47 1.35 13.38 13.567
ns
STD
-1
ns
9.96 0.04 1.23 0.39
9.00 0.05 1.45 0.46
7.66 0.04 1.23 0.39
8.39 0.05 1.45 0.46
7.14 0.04 1.23 0.39
9.26
8.47
7.21
8.47
7.21
9.41 1.47 1.35 11.38 11.541
8.18 1.62 1.62 10.97 10.685
ns
STD
-1
ns
6.96 1.62 1.62 9.33
8.18 1.62 1.62 10.97 10.685
6.96 1.62 1.62 9.33 9.089
9.089
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-61 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
12.83 0.05 1.32
10.92 0.04 1.12
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
9.88 12.83 1.48 0.87 12.30 15.25
8.41 10.92 1.48 0.87 10.46 12.97
ns
4 mA
STD
-1
7.48
6.36
4.81
4.09
4.25
3.61
3.82
3.25
3.82
3.25
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
6.34
5.39
4.52
3.85
4.25
3.61
1.89
1.89
1.89
1.89
7.48
6.36
4.81
4.09
4.25
3.61
1.63
1.63
1.63
1.63
1.72 1.49
1.72 1.49
1.89 1.77
1.89 1.77
1.92 1.85
1.93 1.85
4.00 4.41
3.41 3.75
4.00 4.41
3.41 3.75
8.76
7.45
6.94
5.90
6.67
5.67
3.06
3.06
3.06
3.06
9.90
8.42
7.23
6.15
6.66
5.67
2.82
2.82
2.82
2.82
ns
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-41
Automotive ProASIC3 DC and Switching Characteristics
Table 2-62 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
16.80 0.05 1.40 0.45
14.29 0.04 1.19 0.38
11.33 0.05 1.40 0.45
9.64 0.04 1.19 0.38
8.71 0.05 1.40 0.45
7.41 0.04 1.19 0.38
8.12 0.05 1.40 0.45
6.90 0.04 1.19 0.38
7.89 0.05 1.40 0.45
6.71 0.04 1.19 0.38
7.89 0.05 1.40 0.45
6.71 0.04 1.19 0.38
15.27 16.80 1.48 0.84 17.69 19.22
12.99 14.29 1.49 0.84 15.05 16.35
11.26 11.33 1.73 1.43 13.68 13.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
9.58
8.87
7.54
8.27
7.03
7.83
6.66
7.83
6.66
9.64 1.73 1.43 11.64 11.70
8.48 1.89 1.72 11.29 10.90
STD
-1
7.22 1.89 1.72 9.60
7.89 1.93 1.79 10.69 10.31
6.72 1.93 1.79 9.09 8.77
7.89 1.98 2.07 10.25 10.31
6.71 1.98 2.07 8.72 8.77
7.89 1.98 2.07 10.25 10.31
6.71 1.98 2.07 8.72 8.77
9.27
STD
-1
STD
-1
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-63 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
12.83 0.05 1.32
10.92 0.04 1.12
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
9.44 12.26 1.20 0.80 11.86 14.68
8.03 10.43 1.20 0.80 10.09 12.49
ns
STD
-1
7.48
6.36
4.81
4.09
4.25
3.61
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
0.05 1.32
0.04 1.12
5.93
5.04
4.15
3.53
4.15
3.53
7.01
5.97
4.39
3.74
4.39
3.74
1.41 1.36
1.42 1.37
1.57 1.63
1.57 1.63
1.57 1.63
1.57 1.63
8.35
7.10
6.57
5.59
6.57
5.59
9.43
8.02
6.81
5.79
6.81
5.79
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-42
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-64 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
16.80 0.05 1.40 0.45
14.29 0.04 1.19 0.38
11.33 0.05 1.40 0.45
9.64 0.04 1.19 0.38
8.71 0.05 1.40 0.45
7.41 0.04 1.19 0.38
8.12 0.05 1.40 0.45
6.90 0.04 1.19 0.38
14.60 16.01 1.20 0.77 17.02 18.43
12.42 13.62 1.20 0.77 14.48 15.68
10.53 10.71 1.42 1.31 12.95 13.13
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
8.96
8.19
6.97
8.19
6.97
9.11
7.92 1.57 1.57 10.61 10.34
6.74 1.57 1.57 9.03 8.79
7.92 1.57 1.57 10.61 10.34
6.74 1.57 1.57 9.03 8.79
1.42 1.31 11.01 11.17
STD
-1
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-65 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA1
mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
3.6
3.6
3.6
3.6
3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
6
8
16
33
39
55
55
13
25
32
66
66
10 10
10 10
10 10
10 10
10 10
0.25 * VCCI 0.75 * VCCI 12 12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Revision 5
2-43
Automotive ProASIC3 DC and Switching Characteristics
Table 2-66 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA1
mA1 µA2 µA2
2 mA
4 mA
Notes:
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
2
4
0
0
0
0
10 10
10 10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
35
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
2-44
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-68 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
9.35 0.05 1.61
7.95 0.04 1.37
5.94 0.05 1.61
5.05 0.04 1.37
5.22 0.05 1.61
4.44 0.04 1.37
4.56 0.05 1.61
3.88 0.04 1.37
4.56 0.05 1.61
3.88 0.04 1.37
7.63 9.35 1.87 1.50 10.13 11.851
6.49 7.95 1.87 1.50
5.42 5.94 2.07 1.84
4.61 5.05 2.07 1.85
5.09 5.22 2.11 1.93
4.33 4.44 2.11 1.93
2.25 1.98 4.41 4.70
2.25 1.98 3.75 4.00
2.25 1.98 4.41 4.70
2.25 1.98 3.75 4.00
8.62
7.92
6.74
7.59
6.45
3.46
3.46
3.46
3.46
10.081
8.442
7.181
7.718
6.566
3.211
3.213
3.211
3.213
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-69 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
14.29 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794
12.16 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286
ns
STD
-1
11.19 0.05 1.45 0.46
9.52 0.04 1.23 0.39
11.40 10.67 2.07 1.77 13.90 13.175
9.70 9.08 2.07 1.77 11.82 11.207
ns
ns
STD
-1
10.44 0.05 1.45 0.46 10.63 9.94 2.12 1.86 13.13 12.442
8.88 0.04 1.23 0.39 9.04 8.46 2.12 1.86 11.17 10.584
9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445
8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586
9.96 0.05 1.45 0.46 10.15 9.94 2.18 2.19 12.65 12.445
8.47 0.04 1.23 0.39 8.63 8.46 2.19 2.20 10.76 10.586
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-45
Automotive ProASIC3 DC and Switching Characteristics
Table 2-70 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
8.76 0.05 1.59
7.45 0.04 1.35
5.41 0.05 1.59
4.60 0.04 1.35
7.63 9.35 1.87 1.50 10.13 11.851
6.49 7.95 1.87 1.50
5.42 5.94 2.07 1.84
4.61 5.05 2.07 1.85
8.62
7.92
6.74
10.081
8.442
7.181
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-71 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
STD
-1
0.64
0.55
0.64
0.55
13.51 0.05 1.45 0.46 14.32 14.29 1.88 1.43 16.82 16.794
11.49 0.04 1.23 0.39 12.18 12.16 1.88 1.43 14.31 14.286
ns
STD
-1
10.38 0.05 1.45 0.46
8.83 0.04 1.23 0.39
11.40 10.67 2.07 1.77 13.90 13.175
9.70 9.08 2.07 1.77 11.82 11.207
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-72 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
9.05 0.05 1.56
7.70 0.04 1.32
5.75 0.05 1.56
4.89 0.04 1.32
5.05 0.05 1.56
4.29 0.04 1.32
4.41 0.05 1.56
3.75 0.04 1.32
4.41 0.05 1.56
3.75 0.04 1.32
7.38 9.05 1.81 1.45 9.80 11.47
6.28 7.70 1.81 1.45 8.34
5.25 5.75 2.00 1.78 7.67
4.46 4.89 2.00 1.78 6.52
4.92 5.05 2.04 1.87 7.34
4.19 4.29 2.04 1.87 6.24
2.18 1.91 4.27 4.55 3.35
2.18 1.91 3.63 3.87 3.35
2.18 1.91 4.27 4.55 3.35
2.18 1.91 3.63 3.87 3.35
9.75
8.17
6.95
7.47
6.35
3.11
3.11
3.11
3.11
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-46
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-73 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
13.83 0.05 1.40 0.45
11.76 0.04 1.19 0.38
10.83 0.05 1.40 0.45
9.21 0.04 1.19 0.38
10.10 0.05 1.40 0.45
8.59 0.04 1.19 0.38
9.64 0.05 1.40 0.45
8.20 0.04 1.19 0.38
9.64 0.05 1.40 0.45
8.20 0.04 1.19 0.38
13.86 13.83 1.82 1.39 16.28 16.25
11.79 11.76 1.82 1.39 13.85 13.82
11.03 10.33 2.00 1.71 13.45 12.75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
9.38
10.28
8.75
9.82
8.35
9.82
8.35
8.79 2.01 1.72 11.44 10.84
9.62 2.05 1.80 12.70 12.04
8.18 2.05 1.80 10.81 10.24
STD
-1
STD
-1
9.62
8.18
9.62
8.18
2.11 2.12 12.23 12.04
2.11 2.12 10.41 10.24
2.11 2.12 12.23 12.04
2.11 2.12 10.41 10.24
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-74 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
8.47 0.05 1.54
7.21 0.04 1.31
5.24 0.05 1.54
4.45 0.04 1.31
7.38 9.05 1.81 1.45 9.80 11.47
6.28 7.70 1.81 1.45 8.34
5.25 5.75 2.00 1.78 7.67
4.46 4.89 2.00 1.78 6.52
9.75
8.17
6.95
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-75 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
STD
-1
0.63
0.53
0.63
0.53
13.07 0.05 1.40 0.45
11.12 0.04 1.19 0.38
10.04 0.05 1.40 0.45
8.54 0.04 1.19 0.38
13.86 13.83 1.82 1.39 16.28 16.25
11.79 11.76 1.82 1.39 13.85 13.82
11.03 10.33 2.00 1.71 13.45 12.75
ns
ns
ns
ns
STD
-1
9.38
8.79 2.01 1.72 11.44 10.84
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-47
Automotive ProASIC3 DC and Switching Characteristics
3.3 V PCI, 3.3 V PCI-X
The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI
Bus applications.
Table 2-76 • Minimum and Maximum DC Input and Output Levels
3.3 V
PCI/PCI-X
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL
IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA1
Max.
mA1
V
mA mA
µA2 µA2
Per PCI
Per PCI curves
10 10
specification
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-11.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-11 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is
described in Table 2-77.
Table 2-77 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
10
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
Timing Characteristics
Table 2-78 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.64
tDP
tDIN
tPY
tEOUT
0.46
tZL
1.27 0.94 3.12 3.60 2.49 2.18
1.27 0.94 2.65 3.06 2.49 2.18
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
Std.
–1
2.58 0.05 0.95
2.19 0.04 0.81
0.55
0.39
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-79 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
0.64
tDP
tDIN
tPY
tEOUT
0.46
tZL
1.27 0.94 3.12 3.60 2.49 2.18
1.27 0.94 2.65 3.06 2.49 2.18
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
Std.
–1
3.00 0.05 0.93
2.55 0.04 0.79
0.55
0.39
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-48
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-80 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.628
0.53
tDP
tDIN
tPY
tEOUT
0.45
tZL
1.23 0.91 3.02 3.48 2.40
1.23 0.91 2.57 2.96 2.41
tZH
tLZ
tHZ
tZLS
tZHS
2.11
2.11
Units
ns
Std.
–1
2.50 0.05 0.92
2.12 0.04 0.78
0.38
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-81 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
0.628
0.53
tDP
tDIN
tPY
tEOUT
0.45
tZL
1.23 0.91 3.02 3.48 2.40
1.23 0.91 2.57 2.96 2.41
tZH
tLZ
tHZ
tZLS
tZHS
2.11
2.11
Units
ns
Std.
–1
2.90 0.05 0.90
2.47 0.04 0.77
0.38
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the
user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-12 on
page 2-50. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver
macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for
the three driver resistors are different from those used in the LVPECL implementation because the output
standard specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Revision 5
2-49
Automotive ProASIC3 DC and Switching Characteristics
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
N
P
N
165
165
Z0 = 50
140
Z0 = 50
INBUF_LVDS
+
–
100
Figure 2-12 • LVDS Circuit Diagram and Board-Level Implementation
Table 2-82 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Min.
Typ.
Max.
Units
V
Supply Voltage
2.375
0.9
2.5
1.075
1.425
–
2.625
1.25
1.6
VOL
Output Low Voltage
V
VOH
Output High Voltage
1.25
0
V
VI
Input Voltage
2.925
450
V
VODIFF
VOCM
VICM
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
250
1.125
0.05
100
350
mV
V
1.25
1.25
350
1.375
2.35
–
V
VIDIFF
mV
Table 2-83 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.075
1.325
Cross point
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
Timing Characteristics
Table 2-84 • LVDS
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
0.64
tDP
2.05
1.74
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.79
1.52
0.55
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-85 • LVDS
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
0.63
tDP
1.98
1.68
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.73
1.47
0.53
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-50
Revision 5
Automotive ProASIC3 Flash Family FPGAs
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A
sample application is given in Figure 2-13. The input and output buffer delays are available in the LVDS
section in Table 2-84 on page 2-50.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and
RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-13 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-14 on
page 2-52. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The
values for the three driver resistors are different from those used in the LVDS implementation because
the output standard specifications are different.
Revision 5
2-51
Automotive ProASIC3 DC and Switching Characteristics
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
N
P
N
OUTBUF_LVPECL
100
100
Z = 50
0
INBUF_LVPECL
+
–
187 W
Z = 50
100
0
Figure 2-14 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-86 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max. Units
3.0
3.3
3.6
V
VOL
Output Low Voltage
0.96
1.8
0
1.27
2.11
3.6
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.6
V
V
VOH
Output High Voltage
VIL, VIH
VODIFF
VOCM
VICM
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
V
0.625 0.97 0.625 0.97 0.625 0.97
1.762 1.98 1.762 1.98 1.762 1.98
V
V
1.01
300
2.57
1.01
300
2.57
1.01
300
2.57
V
VIDIFF
mV
Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.64
1.94
Cross point
Note: *Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points.
Timing Characteristics
Table 2-88 • LVPECL
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.64
tDP
2.01
1.71
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.57
1.34
0.55
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-89 • LVPECL
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.63
tDP
1.95
1.66
tDIN
0.05
0.04
tPY
Units
ns
Std.
–1
1.52
1.29
0.53
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-52
Revision 5
Automotive ProASIC3 Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
DFN1E1P1
DFN1E1P1
G
E
E
EOUT
B
A
H
I
PRE
J
D
Q
DFN1E1P1
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
INBUF
INBUF
CLKBUF
Postive-Edge Triggered
Figure 2-15 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Revision 5
2-53
Automotive ProASIC3 DC and Switching Characteristics
Table 2-90 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
G, H
tOHE
G, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
J, H
tOESUE
tOEHE
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
K, H
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tISUE
Enable Setup Time for the Input Data Register
B, A
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 2-15 on page 2-53 for more information.
2-54
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
AA
DD
CLR
LL
HH
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-16 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Revision 5
2-55
Automotive ProASIC3 DC and Switching Characteristics
Table 2-91 • Parameter Definitions and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
II, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-16 on page 2-55 for more information.
2-56
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
Data
tIHD
50%
50%
1
0
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-17 • Input Register Timing Diagram
Timing Characteristics
Table 2-92 • Input Data Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
–1 Std. Units
Clock-to-Q of the Input Data Register
0.29 0.34
0.32 0.38
0.00 0.00
0.45 0.53
0.00 0.00
0.55 0.65
0.55 0.65
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Table 2-93 • Input Data Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
–1 Std. Units
0.29 0.34
0.31 0.37
0.00 0.00
0.44 0.52
0.00 0.00
0.54 0.64
0.54 0.64
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-58
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
tOREMPRE
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOHE
50%
50%
tOSUE
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-18 • Output Register Timing Diagram
Timing Characteristics
Table 2-94 • Output Data Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–1 Std. Units
Clock-to-Q of the Output Data Register
0.72 0.84
0.38 0.45
0.00 0.00
0.53 0.63
0.00 0.00
0.98 1.15
0.98 1.15
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-59
Automotive ProASIC3 DC and Switching Characteristics
Table 2-95 • Output Data Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
–1 Std. Units
0.70 0.82
0.37 0.44
0.00 0.00
0.52 0.61
0.00 0.00
0.96 1.12
0.96 1.12
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Revision 5
Automotive ProASIC3 Flash Family FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD OEHD
t
50% 50%
1
0
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
50%
tOERECPRE
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
EOUT
Figure 2-19 • Output Enable Register Timing Diagram
Timing Characteristics
Table 2-96 • Output Enable Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
–1 Std. Units
Clock-to-Q of the Output Enable Register
0.54 0.64
0.38 0.45
0.00 0.00
0.53 0.62
0.00 0.00
0.81 0.95
0.81 0.95
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Table 2-97 • Output Enable Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
Clock-to-Q of the Output Enable Register
–1 Std. Units
0.53 0.62
0.37 0.44
0.00 0.00
0.52 0.61
0.00 0.00
0.79 0.93
0.79 0.93
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-62
Revision 5
Automotive ProASIC3 Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-20 • Input DDR Timing Model
Table 2-98 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR Input
Data Hold Time of DDR Input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
Revision 5
2-63
Automotive ProASIC3 DC and Switching Characteristics
CLK
tDDRISUD
6
tDDRIHD
8
Data
CLR
1
2
3
4
5
7
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
2
6
4
tDDRICLKQ2
tDDRICLR2Q2
7
3
5
Figure 2-21 • Input DDR Timing Diagram
Timing Characteristics
Table 2-99 • Input DDR Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
–1
Std. Units
Clock-to-Out Out_QR for Input DDR
0.33 0.39
0.47 0.56
0.34 0.40
0.00 0.00
0.56 0.66
0.69 0.82
0.00 0.00
0.27 0.32
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-64
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-100 • Input DDR Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
Clock-to-Out Out_QR for Input DDR
–1
Std. Units
0.33 0.38
0.46 0.54
0.34 0.40
0.00 0.00
0.55 0.65
0.68 0.80
0.00 0.00
0.27 0.31
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-65
Automotive ProASIC3 DC and Switching Characteristics
Output DDR Module
Output DDR
A
Data_F
X
(from core)
FF1
Out
B
0
1
CLK
X
E
X
CLKBUF
C
X
X
OUTBUF
D
Data_R
(from core)
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-22 • Output DDR Timing Model
Table 2-101 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
2-66
Revision 5
Automotive ProASIC3 Flash Family FPGAs
CLK
t
t
DDROHD2
DDROSUD2
4
9
5
Data_F
1
2
3
t
t
DDROHD1
DDROREMCLR
Data_R 6
CLR
7
8
10
11
t
DDRORECCLR
t
DDROREMCLR
t
t
DDROCLKQ
DDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-23 • Output DDR Timing Diagram
Timing Characteristics
Table 2-102 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
–1
Std. Units
Clock-to-Out of DDR for Output DDR
0.85 1.00
0.46 0.54
0.46 0.54
0.00 0.00
0.00 0.00
0.97 1.15
0.00 0.00
0.27 0.32
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-67
Automotive ProASIC3 DC and Switching Characteristics
Table 2-103 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
–1
Std. Units
0.84 0.98
0.45 0.53
0.45 0.53
0.00 0.00
0.00 0.00
0.96 1.12
0.00 0.00
0.27 0.31
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-68
Revision 5
Automotive ProASIC3 Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e,
and ProASIC3/E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-24 • Sample of Combinatorial Cells
Revision 5
2-69
Automotive ProASIC3 DC and Switching Characteristics
tPD
A
B
NAND2 or
Any Combinatorial
Logic
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)
)
where edges are applicable for the particular
combinatorial cell
VCC
50%
50%
A, B, C
GND
50%
VCC
50%
OUT
OUT
GND
VCC
tPD
tPD
(RR)
(FF)
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-25 • Timing Model and Waveforms
2-70
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-104 • Combinatorial Cell Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Combinatorial Cell Equation Parameter –1 Std.
tPD 0.49
Units
ns
INV
Y = !A
0.57
0.67
0.67
0.69
0.69
1.05
1.00
1.25
0.72
0.80
AND2
NAND2
OR2
Y = A · B
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
0.57
0.57
0.59
0.59
0.90
0.85
1.06
0.62
0.68
ns
Y = !(A · B)
ns
Y = A + B
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y = !(A + B)
Y = A B
Y = MAJ(A , B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for
derating values.
Table 2-105 • Combinatorial Cell Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Parameter
tPD
–1
Std.
0.56
0.66
0.66
0.68
0.68
1.03
0.98
1.23
0.71
0.79
Units
ns
Y = !A
0.48
0.56
0.56
0.58
0.58
0.88
0.83
1.04
0.60
0.67
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
tPD
ns
Y = A + B
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A , B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for
derating values.
Revision 5
2-71
Automotive ProASIC3 DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the Fusion, IGLOO/e and ProASIC3/E
Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-26 • Sample of Sequential Cells
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Automotive ProASIC3 Flash Family FPGAs
tCKMPWH CKMPWL
t
50%
tSUD
50%
50%
50%
50%
50%
50%
CLK
tHD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
tREMPRE
50%
tHE
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-27 • Timing Model and Waveforms
Timing Characteristics
Table 2-106 • Register Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–1
Std. Units
Clock-to-Q of the Core Register
0.67 0.79
0.52 0.61
0.00 0.00
0.55 0.65
0.00 0.00
0.49 0.57
0.49 0.57
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Automotive ProASIC3 DC and Switching Characteristics
Table 2-107 • Register Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–1
Std. Units
Clock-to-Q of the Core Register
0.66 0.77
0.51 0.60
0.00 0.00
0.54 0.64
0.00 0.00
0.48 0.56
0.48 0.56
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Automotive ProASIC3 Flash Family FPGAs
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 2-28 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-28 is driven by a CCC located on the west side of the A3P250 device. It
is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-28 • Example of Global Tree Use in an A3P250 Device for Clock Routing
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Automotive ProASIC3 DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-80. Table 2-114 on page 2-79 to Table 2-125 on
page 2-97 present minimum and maximum global clock delays within each device. Minimum and
maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 2-108 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.87
0.86
0.80
0.98
1.16
1.20
1.02
1.01
0.94
1.15
1.37
1.42
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.35
0.41
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-109 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.85
0.84
0.80
0.98
1.13
1.18
1.00
0.99
0.94
1.15
1.33
1.38
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.34
0.40
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Automotive ProASIC3 Flash Family FPGAs
Table 2-110 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.93
0.92
0.80
0.98
1.22
1.26
1.09
1.08
0.94
1.15
1.43
1.49
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.35
0.41
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-111 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.90
0.90
0.80
0.98
1.19
1.23
1.06
1.05
0.94
1.15
1.40
1.45
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.34
0.40
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Automotive ProASIC3 DC and Switching Characteristics
Table 2-112 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Units
Input Low Delay for Global Clock
0.96
0.94
0.80
0.98
1.25
1.28
1.13
1.10
0.94
1.15
1.47
1.51
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.35
0.41
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-113 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
0.94
0.92
0.80
0.98
1.22
1.25
1.10
1.08
0.94
1.15
1.44
1.47
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.34
0.40
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-114 • A3P1000 Global Resource
Automotive-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.17
1.15
0.80
0.98
1.46
1.50
1.37
1.36
0.94
1.15
1.72
1.76
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.35
0.41
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Table 2-115 • A3P1000 Global Resource
Automotive-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Units
1.14
1.13
0.80
0.98
1.43
1.46
1.34
1.32
0.94
1.15
1.68
1.72
ns
ns
ns
ns
ns
tRCKH
Input High Delay for Global Clock
tRCKMPWH
tRCKMPWL
tRCKSW
Notes:
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.34
0.40
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-116 • Automotive ProASIC3 CCC/PLL Specification
Parameter
Minimum Typical Maximum Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
1.5
350
350
MHz
MHz
ps
0.75
1603
32
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
0.50%
1.00%
1.75%
2.50%
0.70%
1.20%
2.00%
5.60%
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
300
300
300
6.0
µs
µs
(all other dies)
µs
ms
Tracking Jitter 4
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1.6
1.6
ns
ns
ns
ns
%
(all other dies)
1.6
0.8
Output Duty Cycle
48.5
0.6
51.5
5.56
5.56
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
ns
ns
ns
0.025
2.2
1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-5 for deratings.
2. T = 25°C, VCC = 1.5 V
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
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Revision 5
Automotive ProASIC3 Flash Family FPGAs
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-29 • Peak-to-Peak Jitter Definition
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512x18
FIFO4K18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RW2
RW1
RW0
WW2
WW1
WW0
RD17
RD16
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
DINA7
RADDR0
RD0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
RW1
RW0
DINA0
AEVAL11
AEVAL10
AEMPTY
WIDTHA1
WIDTHA0
PIPEA
PIPE
AEVAL0
WMODEA
BLKA
WENA
AFVAL11
AFVAL10
REN
RCLK
CLKA
AFVAL0
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
REN
RBLK
RCLK
ADDRB0
DOUTB0
WADDR0
WD17
WD16
WD17
WD16
DINB8
DINB7
WD0
DINB0
WD0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WBLK
WCLK
RPIPE
WEN
WCLK
WENB
CLKB
RESET
RESET
RESET
Figure 2-30 • RAM Models
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Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
[R|W]ADDR
BLK
tBKS
tBKH
tENS
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-31 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-32 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
t
CYC
t
t
CKL
CKH
CLK
t
t
AH
AS
A
A
A
2
[R|W]ADDR
BLK
0
1
t
t
BKS
ENS
t
BKH
t
ENH
WEN
t
t
DH
DS
DI
DI
DIN|WD
DOUT|RD
0
1
D
D
2
n
Figure 2-33 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
ADDR
BLK
tAS tAH
A0
tBKS
A1
A2
tBKH
tENS
WEN
DIN
tDS tDH
DI1
DI0
DI2
DOUT
Dn
DI0
DI1
(pass-through)
DOUT
DI0
Dn
DI1
(pipelined)
Figure 2-34 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.
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Automotive ProASIC3 Flash Family FPGAs
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
Dm
Dn
DOUT|RD
Figure 2-35 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-117 • RAM4K9
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter Description
–1 Std. Units
0.30 0.36 ns
0.00 0.00 ns
0.17 0.20 ns
0.12 0.14 ns
0.28 0.33 ns
0.02 0.03 ns
0.22 0.26 ns
0.00 0.00 ns
2.17 2.55 ns
2.86 3.37 ns
1.09 1.28 ns
tAS
Address Setup Time
tAH
Address Hold Time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
BLK Hold Time
Input Data (DIN) Setup Time
tDH
Input Data (DIN) Hold Time
tCKQ1
Clock High to New Data Valid on DOUT (output retained, WMODE = 0)
Clock High to New Data Valid on DOUT (flow-through, WMODE = 1)
Clock High to New Data Valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address— 0.28 0.33 ns
Applicable to Closing Edge
1
tC2CWWH
Address collision clk-to-clk delay for reliable write after write on same address— 0.26 0.30 ns
Applicable to Rising Edge
1
tC2CRWH
tC2CWRH
tRSTBQ
Address collision clk-to-clk delay for reliable read access after write on same 0.38 0.45 ns
address—Applicable to Opening Edge
1
Address collision clk-to-clk delay for reliable write access after read on same 0.42 0.49 ns
address— Applicable to Opening Edge
RESET Low to Data Out Low on DO (flow-through)
RESET Low to Data Out Low on DO (pipelined)
1.12 1.32 ns
1.12 1.32 ns
0.35 0.41 ns
1.82 2.14 ns
0.26 0.30 ns
3.93 4.62 ns
255 217 MHz
tREMRSTB RESET Removal
tRECRSTB RESET Recovery
tMPWRSTB RESET Minimum Pulse Width
tCYC
Clock Cycle Time
FMAX
Notes:
Maximum Frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
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Automotive ProASIC3 Flash Family FPGAs
Table 2-118 • RAM512X18
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
Description
–1 Std. Units
0.30 0.35 ns
0.00 0.00 ns
0.11 0.13 ns
0.07 0.08 ns
0.22 0.26 ns
0.00 0.00 ns
2.58 3.03 ns
1.07 1.26 ns
tAS
Address Setup Time
tAH
Address Hold Time
tENS
tENH
tDS
REN, WEN Setup Time
REN, WEN Hold Time
Input data (WD) Setup Time
Input data (WD) Hold Time
tDH
tCKQ1
tCKQ2
tC2CRWH
Clock High to New Data Valid on RD (output retained)
Clock High to New Data Valid on RD (pipelined)
1
1
Address collision clk-to-clk delay for reliable read access after write on same 0.43 0.50 ns
address—Applicable to Opening Edge
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.50 0.59 ns
address—Applicable to Opening Edge
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
1.10 1.29 ns
1.10 1.29 ns
0.34 0.40 ns
1.79 2.10 ns
0.25 0.30 ns
3.85 4.53 ns
255 217 MHz
tREMRSTB RESET Removal
tRECRSTB RESET Recovery
tMPWRSTB RESET Minimum Pulse Width
tCYC
Clock Cycle Time
FMAX
Notes:
Maximum Frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
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Automotive ProASIC3 DC and Switching Characteristics
Table 2-119 • RAM4K9
Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Parameter Description
–1 Std. Units
0.30 0.35 ns
0.00 0.00 ns
0.17 0.20 ns
0.12 0.14 ns
0.28 0.33 ns
0.02 0.03 ns
0.22 0.26 ns
0.00 0.00 ns
2.13 2.50 ns
2.81 3.30 ns
1.07 1.25 ns
tAS
Address Setup Time
tAH
Address Hold Time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
BLK Hold Time
Input data (DIN) Setup Time
tDH
Input data (DIN) Hold Time
tCKQ1
Clock High to New Data Valid on DOUT (output retained, WMODE = 0)
Clock High to New Data Valid on DOUT (flow-through, WMODE = 1)
Clock High to New Data Valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address— 0.28 0.33 ns
Applicable to Closing Edge
1
tC2CWWH
Address collision clk-to-clk delay for reliable write after write on same address— 0.26 0.30 ns
Applicable to Rising Edge
1
tC2CRWH
tC2CWRH
tRSTBQ
Address collision clk-to-clk delay for reliable read access after write on same 0.38 0.45 ns
address—Applicable to Opening Edge
1
Address collision clk-to-clk delay for reliable write access after read on same 0.42 0.49 ns
address— Applicable to Opening Edge
RESET Low to Data Out Low on DOUT (flow-through)
RESET Low to Data Out Low on DOUT (pipelined)
1.10 1.29 ns
1.10 1.29 ns
0.34 0.40 ns
1.79 2.10 ns
0.25 0.30 ns
3.85 4.53 ns
260 221 MHz
tREMRSTB RESET Removal
tRECRSTB RESET Recovery
tMPWRSTB RESET Minimum Pulse Width
tCYC
Clock Cycle Time
FMAX
Notes:
Maximum Frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
2-88
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-120 • RAM512X18
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
Description
–1 Std. Units
0.30 0.35 ns
0.00 0.00 ns
0.11 0.13 ns
0.07 0.08 ns
0.22 0.26 ns
0.00 0.00 ns
2.58 3.03 ns
1.07 1.26 ns
tAS
Address Setup Time
tAH
Address Hold Time
tENS
tENH
tDS
REN, WEN Setup Time
REN, WEN Hold Time
Input data (WD) Setup Time
Input data (WD) Hold Time
tDH
tCKQ1
tCKQ2
tC2CRWH
Clock High to New Data Valid on RD (output retained, WMODE = 0)
Clock High to New Data Valid on RD (pipelined)
1
1
Address collision clk-to-clk delay for reliable read access after write on same 0.43 0.50 ns
address—Applicable to Opening Edge
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.50 0.59 ns
address—Applicable to Opening Edge
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
1.10 1.29 ns
1.10 1.29 ns
0.34 0.40 ns
1.79 2.10 ns
0.25 0.30 ns
3.85 4.53 ns
260 221 MHz
tREMRSTB RESET Removal
tRECRSTB RESET Recovery
tMPWRSTB RESET Minimum Pulse Width
tCYC
Clock Cycle Time
FMAX
Notes:
Maximum Frequency
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
Revision 5
2-89
Automotive ProASIC3 DC and Switching Characteristics
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-36 • FIFO Model
2-90
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKS
tBKH
RBLK
tCKQ1
RD
D1
Dn
D0
D2
(flow-through)
tCKQ2
RD
(pipelined)
Dn
D0
D1
Figure 2-37 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
tBKS
tBKH
WBLK
tDS
tDH
DI1
DI0
WD
Figure 2-38 • FIFO Write
Revision 5
2-91
Automotive ProASIC3 DC and Switching Characteristics
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET
EMPTY
AEMPTY
FULL
tRSTFG
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
MATCH (A0)
(Address Counter)
Figure 2-39 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
t
CKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion
2-92
Revision 5
Automotive ProASIC3 Flash Family FPGAs
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
tRCKEF
tCKAF
AEMPTY
Figure 2-42 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
t
WCKF
t
CKAF
AFULL
Figure 2-43 • FIFO FULL Flag and AFULL Flag Deassertion
Revision 5
2-93
Automotive ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-121 • FIFO
Worst-Case Automotive Conditions: TJ = 135°C, VCC = 1.425 V
Parameter
tENS
Description
–1
Std. Units
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
1.97 1.67
0.03 0.02
0.28 0.32
0.00 0.00
0.26 0.22
0.00 0.00
3.37 2.86
1.28 1.09
2.45 2.09
2.33 1.98
8.85 7.53
2.42 2.06
8.76 7.45
1.32 1.12
1.32 1.12
0.41 0.35
2.14 1.82
0.30 0.26
4.62 3.93
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tENH
tBKS
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
tDH
Input Data (WD) Hold Time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
217 255 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for
derating values.
2-94
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Table 2-122 • FIFO
Worst-Case Automotive Conditions: TJ = 115°C, VCC = 1.425 V
Parameter
tENS
Description
–1
Std. Units
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
1.93 1.64
0.03 0.02
0.27 0.32
0.00 0.00
0.26 0.22
0.00 0.00
3.30 2.81
1.25 1.07
2.41 2.05
2.29 1.95
8.68 7.38
2.37 2.02
8.59 7.30
1.29 1.10
1.29 1.10
0.40 0.34
2.10 1.79
0.30 0.25
4.53 3.85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tENH
tBKS
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
tDH
Input Data (WD) Hold Time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
221 260 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for
derating values.
Revision 5
2-95
Automotive ProASIC3 DC and Switching Characteristics
Embedded FlashROM Characteristics
t
t
t
SU
SU
SU
CLK
t
t
t
HOLD
HOLD
HOLD
Address
A
A
1
0
t
t
t
CKQ2
CKQ2
CKQ2
D
D
D
Data
0
0
1
Figure 2-44 • Timing Diagram
Timing Characteristics
Table 2-123 • Embedded FlashROM Access Time
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
–1
0.65
0.00
19.73
15
Std.
Units
ns
0.76
0.00
23.20
15
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
Table 2-124 • Embedded FlashROM Access Time
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
–1
0.64
0.00
19.35
15
Std.
0.75
0.00
22.74
15
Units
ns
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
2-96
Revision 5
Automotive ProASIC3 Flash Family FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-12 for more details.
Timing Characteristics
Table 2-125 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
–2
–1
Std.
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
20
20
20
MHz
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for
derating values.
Revision 5
2-97
3 – Pin Descriptions and Packaging
Supply Pins
GND
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Ground
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
four I/O banks on Automotive ProASIC3 devices, plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or
3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV
and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs
to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.
Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise
from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices" chapter of the Automotive ProASIC3 FPGA Fabric User’s Guide for a
complete board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on Automotive ProASIC3 devices.
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on Automotive ProASIC3 devices.
VJTAG
JTAG Supply Voltage
Automotive ProASIC3 devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be
run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
Revision 5
3-1
Pin Descriptions and Packaging
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
Automotive ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO
and ProASIC3 Devices" chapter of the Automotive ProASIC3 FPGA Fabric User’s Guide. All inputs
labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input,
GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are
direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to
the global network are multiplexed, and only one input can be used as a global input.
Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter of the Automotive ProASIC3
FPGA Fabric User’s Guide for an explanation of the naming of global pins.
3-2
Revision 5
Automotive ProASIC3 Flash Family FPGAs
JTAG Pins
Automotive ProASIC3 devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be
run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine
to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to
the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply
in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Actel recommends tying off TCK to GND through a resistor placed
close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-1
for more information.
Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The
values in Table 3-1 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Actel recommends tying off TRST to GND through a resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
Revision 5
3-3
Pin Descriptions and Packaging
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Actel offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Related Documents
User’s Guides
Automotive ProASIC FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/PA3_Auto_UG.pdf
Packaging
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsmei.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
3-4
Revision 5
4 – Package Pin Assignments
VQ100
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 5
4-1
Package Pin Assignments
VQ100
VQ100
A3P060 Function
VQ100
A3P060 Function
Pin Number
A3P060 Function
Pin Number
35
Pin Number
69
1
GND
IO62RSB1
IO61RSB1
VCC
IO31RSB0
GBC2/IO29RSB0
GBB2/IO27RSB0
IO26RSB0
2
GAA2/IO51RSB1
IO52RSB1
36
70
3
37
71
4
GAB2/IO53RSB1
IO95RSB1
38
GND
72
5
39
VCCIB1
73
GBA2/IO25RSB0
VMV0
6
GAC2/IO94RSB1
IO93RSB1
40
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
74
7
41
75
GNDQ
8
IO92RSB1
42
76
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
9
GND
43
77
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
44
78
45
79
46
80
GFA0/IO85RSB1
VCCPLF
47
81
48
TDI
82
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
49
TMS
83
IO17RSB0
50
VMV1
84
IO15RSB0
51
GND
85
IO13RSB0
VCCIB1
52
VPUMP
86
IO11RSB0
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
53
NC
87
VCCIB0
54
TDO
88
GND
55
TRST
89
VCC
56
VJTAG
90
IO10RSB0
57
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
91
IO09RSB0
58
92
IO08RSB0
GNDQ
59
93
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GEA2/IO71RSB1
GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
60
94
61
95
62
96
63
97
IO67RSB1
64
98
IO66RSB1
65
99
IO65RSB1
66
100
IO00RSB0
IO64RSB1
67
GND
IO63RSB1
68
VCC
4-2
Revision 5
Automotive ProASIC3 Flash Family FPGAs
VQ100
VQ100
VQ100
Pin Number A3P125 Function
Pin Number A3P125 Function
Pin Number A3P125 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41RSB0
VMV0
2
GAA2/IO67RSB1
IO68RSB1
3
VCCIB1
GNDQ
4
GAB2/IO69RSB1
IO132RSB1
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
5
6
GAC2/IO131RSB1
IO130RSB1
7
8
IO129RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
IO28RSB0
TDI
IO25RSB0
GFA0/IO122RSB1
VCCPLF
TMS
IO22RSB0
VMV1
IO19RSB0
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO15RSB0
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO09RSB0
IO07RSB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO106RSB1
GEB2/IO105RSB1
GEC2/IO104RSB1
IO102RSB1
IO100RSB1
IO99RSB1
GND
IO97RSB1
VCC
IO96RSB1
IO47RSB0
GBC2/IO45RSB0
GBB2/IO43RSB0
IO42RSB0
IO95RSB1
IO94RSB1
IO93RSB1
Revision 5
4-3
Package Pin Assignments
VQ100
VQ100
A3P250 Function
VQ100
A3P250 Function
Pin Number
A3P250 Function
Pin Number
35
Pin Number
69
1
GND
IO85RSB2
IO84RSB2
VCC
IO43NDB1
GBC2/IO43PDB1
GBB2/IO42PSB1
IO41NDB1
2
GAA2/IO118UDB3
IO118VDB3
36
70
3
37
71
4
GAB2/IO117UDB3
IO117VDB3
38
GND
72
5
39
VCCIB2
73
GBA2/IO41PDB1
VMV1
6
GAC2/IO116UDB3
IO116VDB3
40
IO77RSB2
IO74RSB2
IO71RSB2
GDC2/IO63RSB2
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
74
7
41
75
GNDQ
8
IO112PSB3
42
76
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO29RSB0
9
GND
43
77
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
44
78
45
79
46
80
GFA0/IO108NPB3
VCCPLF
47
TCK
81
48
TDI
82
GFA1/IO108PPB3
GFA2/IO107PSB3
VCC
49
TMS
83
IO27RSB0
50
VMV2
84
IO25RSB0
51
GND
85
IO23RSB0
VCCIB3
52
VPUMP
86
IO21RSB0
GFC2/IO105PSB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
53
NC
87
VCCIB0
54
TDO
88
GND
55
TRST
89
VCC
56
VJTAG
90
IO15RSB0
57
GDA1/IO60USB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO52NDB1
GCB2/IO52PDB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
VCCIB1
91
IO13RSB0
58
92
IO11RSB0
GNDQ
59
93
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO97RSB2
GEB2/IO96RSB2
GEC2/IO95RSB2
IO93RSB2
60
94
61
95
62
96
63
97
IO92RSB2
64
98
IO91RSB2
65
99
IO90RSB2
66
100
VMV0
IO88RSB2
67
GND
IO86RSB2
68
VCC
4-4
Revision 5
Automotive ProASIC3 Flash Family FPGAs
QN132
A37
A48
B44
C40
B34
C31
Pin A1Mark
D4
D1
A36
B33
C30
A1
B1
C1
C21
B23
A25
C10
B11
A12
D3
D2
Optional
Corner Pad (4x)
C20
B22
C11
B12
A13
A24
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 5
4-5
Package Pin Assignments
QN132
QN132
A3P125 Function
QN132
A3P125 Function
Pin Number
A1
A3P125 Function
Pin Number
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
Pin Number
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GAB2/IO69RSB1
IO130RSB1
VCCIB1
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
GND
NC
A2
A3
GCB2/IO58RSB0
GND
A4
GFC1/IO126RSB1
GFB0/IO123RSB1
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO54RSB0
GCC1/IO51RSB0
GND
A6
A7
GFA1/IO121RSB1
GFC2/IO118RSB1
IO115RSB1
VCC
A8
GBB2/IO43RSB0
VMV0
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEB1/IO110RSB1
GEA0/IO107RSB1
GEC2/IO104RSB1
IO100RSB1
VCC
GAC1/IO05RSB0
GAB0/IO02RSB0
IO68RSB1
GAC2/IO131RSB1
GND
IO26RSB0
IO21RSB0
GND
B2
B3
IO99RSB1
B4
GFC0/IO125RSB1
VCOMPLF
GND
IO13RSB0
IO08RSB0
GND
IO96RSB1
B5
IO94RSB1
B6
IO91RSB1
B7
GFB2/IO119RSB1
IO116RSB1
GND
GAC0/IO04RSB0
GNDQ
IO85RSB1
B8
IO79RSB1
B9
GAA2/IO67RSB1
IO132RSB1
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO109RSB1
VMV1
C2
GDB2/IO71RSB1
TDI
C3
GEB2/IO105RSB1
IO101RSB1
GND
C4
GFB1/IO124RSB1
GFA0/IO122RSB1
GFA2/IO120RSB1
IO117RSB1
VCCIB1
TRST
C5
GDC1/IO61RSB0
VCC
C6
IO98RSB1
IO95RSB1
GND
C7
IO60RSB0
C8
GCC2/IO59RSB0
GCA2/IO57RSB0
GCA0/IO56RSB0
GCB1/IO53RSB0
IO49RSB0
C9
GEA1/IO108RSB1
GNDQ
IO87RSB1
IO81RSB1
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO106RSB1
IO103RSB1
VCCIB1
GNDQ
VCC
TMS
IO97RSB1
IO93RSB1
IO89RSB1
IO44RSB0
TDO
GBA2/IO41RSB0
GDC0/IO62RSB0
4-6
Revision 5
Automotive ProASIC3 Flash Family FPGAs
QN132
A3P125 Function
Pin Number
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO83RSB1
VCCIB1
TCK
VMV1
VPUMP
VJTAG
VCCIB0
NC
NC
GCA1/IO55RSB0
GCC0/IO52RSB0
VCCIB0
IO42RSB0
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
Revision 5
4-7
Package Pin Assignments
QN132
QN132
A3P250 Function
QN132
A3P250 Function
Pin Number
A1
A3P250 Function
Pin Number
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
Pin Number
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GAB2/IO117UPB3
IO117VPB3
VCCIB3
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
GND
IO54PDB1
A2
A3
GCB2/IO52PDB1
GND
A4
GFC1/IO110PDB3
GFB0/IO109NPB3
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO49NDB1
GCC1/IO48PDB1
GND
A6
A7
GFA1/IO108PPB3
GFC2/IO105PPB3
IO103NDB3
VCC
A8
GBB2/IO42PDB1
VMV1
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEA1/IO98PPB3
GEA0/IO98NPB3
GEC2/IO95RSB2
IO91RSB2
GAC1/IO05RSB0
GAB0/IO02RSB0
IO118VDB3
GAC2/IO116UDB3
GND
IO26RSB0
B2
IO21RSB0
VCC
B3
GND
IO90RSB2
B4
GFC0/IO110NDB3
VCOMPLF
GND
IO13RSB0
IO87RSB2
B5
IO08RSB0
IO85RSB2
B6
GND
IO82RSB2
B7
GFB2/IO106PSB3
IO103PDB3
GND
GAC0/IO04RSB0
GNDQ
IO76RSB2
B8
IO70RSB2
B9
GAA2/IO118UDB3
IO116VDB3
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO99NDB3
VMV3
C2
GDB2/IO62RSB2
TDI
C3
GEB2/IO96RSB2
IO92RSB2
GND
C4
GFB1/IO109PPB3
GFA0/IO108NPB3
GFA2/IO107PSB3
IO105NPB3
VCCIB3
TRST
C5
GDC1/IO58UDB1
VCC
C6
IO89RSB2
IO86RSB2
GND
C7
IO54NDB1
C8
IO52NDB1
C9
GEB1/IO99PDB3
GNDQ
GCA2/IO51PPB1
GCA0/IO50NPB1
GCB1/IO49PDB1
IO47NSB1
IO78RSB2
IO72RSB2
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO97RSB2
IO94RSB2
GNDQ
VCCIB2
VCC
TMS
IO88RSB2
IO41NPB1
TDO
IO84RSB2
GBA2/IO41PPB1
GDC0/IO58VDB1
IO80RSB2
4-8
Revision 5
Automotive ProASIC3 Flash Family FPGAs
QN132
A3P250 Function
Pin Number
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO74RSB2
VCCIB2
TCK
VMV2
VPUMP
VJTAG
VCCIB1
IO53NSB1
IO51NPB1
GCA1/IO50PPB1
GCC0/IO48NDB1
VCCIB1
IO42NDB1
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
Revision 5
4-9
Package Pin Assignments
FG144
A1 Ball Pad Corner
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
4-10
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG144
A3P060 Function
FG144
A3P060 Function
FG144
Pin Number
A1
Pin Number
D1
Pin Number
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
A3P060 Function
GFA1/IO84RSB1
GND
GNDQ
VMV0
IO91RSB1
IO92RSB1
A2
D2
A3
GAB0/IO04RSB0
GAB1/IO05RSB0
IO08RSB0
D3
IO93RSB1
VCCPLF
A4
D4
GAA2/IO51RSB1
GAC0/IO06RSB0
GAC1/IO07RSB0
GBC0/IO19RSB0
GBC1/IO20RSB0
GBB2/IO27RSB0
IO18RSB0
GFA0/IO85RSB1
GND
A5
D5
A6
GND
D6
GND
A7
IO11RSB0
D7
GND
A8
VCC
D8
GDC1/IO45RSB0
IO32RSB0
A9
IO16RSB0
D9
A10
A11
A12
B1
GBA0/IO23RSB0
GBA1/IO24RSB0
GNDQ
D10
D11
D12
E1
GCC2/IO43RSB0
IO31RSB0
IO28RSB0
GCB1/IO37RSB0
VCC
GCB2/IO42RSB0
VCC
GAB2/IO53RSB1
GND
B2
E2
GFC0/IO88RSB1
GFC1/IO89RSB1
VCCIB1
H2
GFB2/IO82RSB1
GFC2/IO81RSB1
GEC1/IO77RSB1
VCC
B3
GAA0/IO02RSB0
GAA1/IO03RSB0
IO00RSB0
E3
H3
B4
E4
H4
B5
E5
IO52RSB1
H5
B6
IO10RSB0
E6
VCCIB0
H6
IO34RSB0
B7
IO12RSB0
E7
VCCIB0
H7
IO44RSB0
B8
IO14RSB0
E8
GCC1/IO35RSB0
VCCIB0
H8
GDB2/IO55RSB1
GDC0/IO46RSB0
VCCIB0
B9
GBB0/IO21RSB0
GBB1/IO22RSB0
GND
E9
H9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
H10
H11
H12
J1
GCA0/IO40RSB0
IO30RSB0
IO33RSB0
VMV0
VCC
IO95RSB1
GFB0/IO86RSB1
VCOMPLF
GEB1/IO75RSB1
IO78RSB1
C2
GFA2/IO83RSB1
GAC2/IO94RSB1
VCC
F2
J2
C3
F3
GFB1/IO87RSB1
IO90RSB1
J3
VCCIB1
C4
F4
J4
GEC0/IO76RSB1
IO79RSB1
C5
IO01RSB0
F5
GND
J5
C6
IO09RSB0
F6
GND
J6
IO80RSB1
C7
IO13RSB0
F7
GND
J7
VCC
C8
IO15RSB0
F8
GCC0/IO36RSB0
GCB0/IO38RSB0
GND
J8
TCK
C9
IO17RSB0
F9
J9
GDA2/IO54RSB1
TDO
C10
C11
C12
GBA2/IO25RSB0
IO26RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO39RSB0
GCA2/IO41RSB0
GDA1/IO49RSB0
GDB1/IO47RSB0
GBC2/IO29RSB0
Revision 5
4-11
Package Pin Assignments
FG144
Pin Number
K1
A3P060 Function
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
GEA2/IO71RSB1
IO65RSB1
IO64RSB1
GND
K2
K3
K4
K5
K6
K7
K8
IO57RSB1
GDC2/IO56RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO50RSB0
GDB0/IO48RSB0
GND
L2
VMV1
L3
GEB2/IO70RSB1
IO67RSB1
VCCIB1
L4
L5
L6
IO62RSB1
IO59RSB1
IO58RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO69RSB1
IO68RSB1
IO66RSB1
IO63RSB1
IO61RSB1
IO60RSB1
NC
TDI
VCCIB1
VPUMP
GNDQ
4-12
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG144
A3P125 Function
FG144
A3P125 Function
FG144
Pin Number
A1
Pin Number
D1
Pin Number
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
A3P125 Function
GFA1/IO121RSB1
GND
GNDQ
VMV0
IO128RSB1
IO129RSB1
IO130RSB1
GAA2/IO67RSB1
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO43RSB0
IO28RSB0
A2
D2
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO11RSB0
D3
VCCPLF
A4
D4
GFA0/IO122RSB1
GND
A5
D5
A6
GND
D6
GND
A7
IO18RSB0
D7
GND
A8
VCC
D8
GDC1/IO61RSB0
IO48RSB0
A9
IO25RSB0
D9
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
D10
D11
D12
E1
GCC2/IO59RSB0
IO47RSB0
IO44RSB0
GCB1/IO53RSB0
VCC
GCB2/IO58RSB0
VCC
GAB2/IO69RSB1
GND
B2
E2
GFC0/IO125RSB1
GFC1/IO126RSB1
VCCIB1
H2
GFB2/IO119RSB1
GFC2/IO118RSB1
GEC1/IO112RSB1
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO08RSB0
E3
H3
B4
E4
H4
B5
E5
IO68RSB1
H5
B6
IO14RSB0
E6
VCCIB0
H6
IO50RSB0
B7
IO19RSB0
E7
VCCIB0
H7
IO60RSB0
B8
IO22RSB0
E8
GCC1/IO51RSB0
VCCIB0
H8
GDB2/IO71RSB1
GDC0/IO62RSB0
VCCIB0
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
H9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
H10
H11
H12
J1
GCA0/IO56RSB0
IO46RSB0
IO49RSB0
VMV0
VCC
IO132RSB1
GFA2/IO120RSB1
GAC2/IO131RSB1
VCC
GFB0/IO123RSB1
VCOMPLF
GEB1/IO110RSB1
IO115RSB1
VCCIB1
C2
F2
J2
C3
F3
GFB1/IO124RSB1
IO127RSB1
GND
J3
C4
F4
J4
GEC0/IO111RSB1
IO116RSB1
IO117RSB1
VCC
C5
IO10RSB0
F5
J5
C6
IO12RSB0
F6
GND
J6
C7
IO21RSB0
F7
GND
J7
C8
IO24RSB0
F8
GCC0/IO52RSB0
GCB0/IO54RSB0
GND
J8
TCK
C9
IO27RSB0
F9
J9
GDA2/IO70RSB1
TDO
C10
C11
C12
GBA2/IO41RSB0
IO42RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO55RSB0
GCA2/IO57RSB0
GDA1/IO65RSB0
GDB1/IO63RSB0
GBC2/IO45RSB0
Revision 5
4-13
Package Pin Assignments
FG144
Pin Number
K1
A3P125 Function
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
GEA2/IO106RSB1
IO100RSB1
IO98RSB1
GND
K2
K3
K4
K5
K6
K7
K8
IO73RSB1
GDC2/IO72RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO66RSB0
GDB0/IO64RSB0
GND
L2
VMV1
L3
GEB2/IO105RSB1
IO102RSB1
VCCIB1
L4
L5
L6
IO95RSB1
IO85RSB1
IO74RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO104RSB1
IO103RSB1
IO101RSB1
IO97RSB1
IO94RSB1
IO86RSB1
IO75RSB1
TDI
VCCIB1
VPUMP
GNDQ
4-14
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG144
A3P250 Function
FG144
A3P250 Function
FG144
Pin Number
A1
Pin Number
D1
Pin Number
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
A3P250 Function
GFA1/IO108PPB3
GND
GNDQ
VMV0
IO112NDB3
IO112PDB3
A2
D2
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
D3
IO116VDB3
VCCPLF
A4
D4
GAA2/IO118UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO42PDB1
IO42NDB1
GFA0/IO108NPB3
GND
A5
D5
A6
GND
D6
GND
A7
IO29RSB0
D7
GND
A8
VCC
D8
GDC1/IO58UPB1
IO53NDB1
A9
IO33RSB0
D9
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
D10
D11
D12
E1
GCC2/IO53PDB1
IO52NDB1
IO43NPB1
GCB1/IO49PPB1
VCC
GCB2/IO52PDB1
VCC
GAB2/IO117UDB3
GND
B2
E2
GFC0/IO110NDB3
GFC1/IO110PDB3
VCCIB3
H2
GFB2/IO106PDB3
GFC2/IO105PSB3
GEC1/IO100PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
H3
B4
E4
H4
B5
E5
IO118VPB3
H5
B6
IO19RSB0
E6
VCCIB0
H6
IO79RSB2
B7
IO22RSB0
E7
VCCIB0
H7
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
VCCIB1
H8
GDB2/IO62RSB2
GDC0/IO58VPB1
VCCIB1
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
H9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
H10
H11
H12
J1
GCA0/IO50NDB1
IO51NDB1
IO54PSB1
VMV1
VCC
IO117VDB3
GFA2/IO107PPB3
GAC2/IO116UDB3
VCC
GFB0/IO109NPB3
VCOMPLF
GEB1/IO99PDB3
IO106NDB3
VCCIB3
C2
F2
J2
C3
F3
GFB1/IO109PPB3
IO107NPB3
GND
J3
C4
F4
J4
GEC0/IO100NDB3
IO88RSB2
C5
IO12RSB0
F5
J5
C6
IO17RSB0
F6
GND
J6
IO81RSB2
C7
IO24RSB0
F7
GND
J7
VCC
C8
IO31RSB0
F8
GCC0/IO48NDB1
GCB0/IO49NPB1
GND
J8
TCK
C9
IO34RSB0
F9
J9
GDA2/IO61RSB2
TDO
C10
C11
C12
GBA2/IO41PDB1
IO41NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO50PDB1
GCA2/IO51PDB1
GDA1/IO60UDB1
GDB1/IO59UDB1
GBC2/IO43PPB1
Revision 5
4-15
Package Pin Assignments
FG144
Pin Number
K1
A3P250 Function
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
GEA2/IO97RSB2
IO90RSB2
IO84RSB2
GND
K2
K3
K4
K5
K6
K7
K8
IO66RSB2
GDC2/IO63RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO60VDB1
GDB0/IO59VDB1
GND
L2
VMV3
L3
GEB2/IO96RSB2
IO91RSB2
VCCIB2
L4
L5
L6
IO82RSB2
IO80RSB2
IO72RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO95RSB2
IO92RSB2
IO89RSB2
IO87RSB2
IO85RSB2
IO78RSB2
IO76RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-16
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG144
FG144
FG144
Pin Number
A1
A3P1000 Function
GNDQ
Pin Number
D1
A3P1000 Function
IO213PDB3
IO213NDB3
IO223NDB3
GAA2/IO225PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO72RSB0
GBC1/IO73RSB0
GBB2/IO79PDB1
IO79NDB1
Pin Number
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
A3P1000 Function
GFA1/IO207PPB3
GND
A2
VMV0
D2
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
D3
VCCPLF
A4
D4
GFA0/IO207NPB3
GND
A5
D5
A6
GND
D6
GND
A7
IO44RSB0
D7
GND
A8
VCC
D8
GDC1/IO111PPB1
IO96NDB1
A9
IO69RSB0
D9
A10
A11
A12
B1
GBA0/IO76RSB0
GBA1/IO77RSB0
GNDQ
D10
D11
D12
E1
GCC2/IO96PDB1
IO95NDB1
IO80NPB1
GCB1/IO92PPB1
VCC
GCB2/IO95PDB1
VCC
GAB2/IO224PDB3
GND
B2
E2
GFC0/IO209NDB3
GFC1/IO209PDB3
VCCIB3
H2
GFB2/IO205PDB3
GFC2/IO204PSB3
GEC1/IO190PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
H3
B4
E4
H4
B5
E5
IO225NPB3
VCCIB0
H5
B6
IO26RSB0
E6
H6
IO105PDB1
IO105NDB1
GDB2/IO115RSB2
GDC0/IO111NPB1
VCCIB1
B7
IO35RSB0
E7
VCCIB0
H7
B8
IO60RSB0
E8
GCC1/IO91PDB1
VCCIB1
H8
B9
GBB0/IO74RSB0
GBB1/IO75RSB0
GND
E9
H9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
H10
H11
H12
J1
GCA0/IO93NDB1
IO94NDB1
IO101PSB1
VCC
VMV1
IO224NDB3
GFA2/IO206PPB3
GAC2/IO223PDB3
VCC
GFB0/IO208NPB3
VCOMPLF
GEB1/IO189PDB3
IO205NDB3
VCCIB3
C2
F2
J2
C3
F3
GFB1/IO208PPB3
IO206NPB3
GND
J3
C4
F4
J4
GEC0/IO190NDB3
IO160RSB2
IO157RSB2
VCC
C5
IO16RSB0
F5
J5
C6
IO29RSB0
F6
GND
J6
C7
IO32RSB0
F7
GND
J7
C8
IO63RSB0
F8
GCC0/IO91NDB1
GCB0/IO92NPB1
GND
J8
TCK
C9
IO66RSB0
F9
J9
GDA2/IO114RSB2
TDO
C10
C11
C12
GBA2/IO78PDB1
IO78NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO93PDB1
GCA2/IO94PDB1
GDA1/IO113PDB1
GDB1/IO112PDB1
GBC2/IO80PPB1
Revision 5
4-17
Package Pin Assignments
FG144
Pin Number
K1
A3P1000 Function
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
GEA2/IO187RSB2
IO169RSB2
IO152RSB2
GND
K2
K3
K4
K5
K6
K7
K8
IO117RSB2
GDC2/IO116RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO113NDB1
GDB0/IO112NDB1
GND
L2
VMV3
L3
GEB2/IO186RSB2
IO172RSB2
VCCIB2
L4
L5
L6
IO153RSB2
IO144RSB2
IO140RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO185RSB2
IO173RSB2
IO168RSB2
IO161RSB2
IO156RSB2
IO145RSB2
IO141RSB2
TDI
VCCIB2
VPUMP
GNDQ
4-18
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG256
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Revision 5
4-19
Package Pin Assignments
FG256
FG256
A3P250 Function
FG256
A3P250 Function
Pin Number
A1
A3P250 Function
Pin Number
C5
Pin Number
E9
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO13RSB0
IO17RSB0
IO22RSB0
IO27RSB0
IO31RSB0
GBC0/IO35RSB0
IO34RSB0
NC
IO24RSB0
VCCIB0
VCCIB0
VMV1
A2
C6
E10
E11
E12
E13
E14
E15
E16
F1
A3
C7
A4
C8
A5
C9
GBC2/IO43PDB1
IO46RSB1
NC
A6
IO10RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO11RSB0
A8
IO15RSB0
IO45PDB1
IO113NDB3
IO112PPB3
NC
A9
IO20RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO25RSB0
F2
IO29RSB0
IO42NPB1
IO44PDB1
IO114VDB3
IO114UDB3
GAC2/IO116UDB3
NC
F3
IO33RSB0
F4
IO115VDB3
VCCIB3
GND
GBB1/IO38RSB0
GBA0/IO39RSB0
GBA1/IO40RSB0
GND
F5
D2
F6
D3
F7
VCC
D4
F8
VCC
GAB2/IO117UDB3
GAA2/IO118UDB3
NC
D5
GNDQ
F9
VCC
B2
D6
IO08RSB0
IO14RSB0
IO18RSB0
IO23RSB0
IO28RSB0
IO32RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO06RSB0
D8
VCCIB1
IO43NDB1
NC
B5
D9
B6
IO09RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO12RSB0
IO47PPB1
IO45NDB1
IO111NDB3
IO111PDB3
IO112NPB3
GFC1/IO110PPB3
VCCIB3
VCC
B8
IO16RSB0
B9
IO21RSB0
NC
B10
B11
B12
B13
B14
B15
B16
C1
IO26RSB0
GBB2/IO42PPB1
NC
G2
IO30RSB0
G3
GBC1/IO36RSB0
GBB0/IO37RSB0
NC
IO44NDB1
IO113PDB3
NC
G4
G5
E2
G6
GBA2/IO41PDB1
IO41NDB1
E3
IO116VDB3
IO115UDB3
VMV0
G7
GND
E4
G8
GND
IO117VDB3
IO118VDB3
NC
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
NC
E8
IO19RSB0
VCCIB1
4-20
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG256
A3P250 Function
FG256
A3P250 Function
FG256
Pin Number
G13
G14
G15
G16
H1
Pin Number
K1
Pin Number
M5
A3P250 Function
VMV3
GCC1/IO48PPB1
IO47NPB1
IO54PDB1
IO54NDB1
GFB0/IO109NPB3
GFA0/IO108NDB3
GFB1/IO109PPB3
VCOMPLF
GFC0/IO110NPB3
VCC
GFC2/IO105PDB3
IO107NPB3
IO104PPB3
NC
K2
M6
VCCIB2
K3
M7
VCCIB2
K4
M8
NC
K5
VCCIB3
VCC
M9
IO74RSB2
VCCIB2
H2
K6
M10
M11
M12
M13
M14
M15
M16
N1
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
K9
GND
NC
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO59UPB1
GDC1/IO58UDB1
IO56NDB1
IO103NDB3
IO101PPB3
GEC1/IO100PPB3
NC
H7
GND
VCC
H8
GND
VCCIB1
IO52NPB1
IO55RSB1
IO53NPB1
IO51NDB1
IO105NDB3
IO104NPB3
NC
H9
GND
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO48NPB1
GCB1/IO49PPB1
GCA0/IO50NPB1
NC
N4
N5
GNDQ
L2
N6
GEA2/IO97RSB2
IO86RSB2
IO82RSB2
IO75RSB2
IO69RSB2
IO64RSB2
GNDQ
L3
N7
GCB0/IO49NPB1
GFA2/IO107PPB3
GFA1/IO108PDB3
VCCPLF
L4
IO102RSB3
VCCIB3
GND
N8
L5
N9
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO106NDB3
GFB2/IO106PDB3
VCC
L8
VCC
J5
L9
VCC
NC
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO58VDB1
GDA1/IO60UDB1
GEB1/IO99PDB3
GEB0/IO99NDB3
NC
J8
GND
VCCIB1
GDB0/IO59VPB1
IO57VDB1
IO57UDB1
IO56PDB1
IO103PDB3
NC
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO52PPB1
GCA1/IO50PPB1
GCC2/IO53PPB1
NC
P4
NC
P5
IO92RSB2
IO89RSB2
IO85RSB2
IO81RSB2
P6
IO101NPB3
GEC0/IO100NPB3
P7
GCA2/IO51PDB1
P8
Revision 5
4-21
Package Pin Assignments
FG256
FG256
A3P250 Function
Pin Number
P9
A3P250 Function
Pin Number
T13
IO76RSB2
IO71RSB2
IO66RSB2
NC
IO67RSB2
GDA2/IO61RSB2
TMS
P10
P11
P12
P13
P14
P15
P16
R1
T14
T15
T16
GND
TCK
VPUMP
TRST
GDA0/IO60VDB1
GEA1/IO98PDB3
GEA0/IO98NDB3
NC
R2
R3
R4
GEC2/IO95RSB2
IO91RSB2
IO88RSB2
IO84RSB2
IO80RSB2
IO77RSB2
IO72RSB2
IO68RSB2
IO65RSB2
GDB2/IO62RSB2
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
NC
TDO
GND
T2
IO94RSB2
GEB2/IO96RSB2
IO93RSB2
IO90RSB2
IO87RSB2
IO83RSB2
IO79RSB2
IO78RSB2
IO73RSB2
IO70RSB2
GDC2/IO63RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
4-22
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO47RSB0
VCCIB0
A3
C7
VCCIB0
A4
C8
VMV1
A5
C9
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
A6
IO22RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO28RSB0
A8
IO35RSB0
A9
IO45RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO50RSB0
F2
IO55RSB0
IO78NDB1
IO81NDB1
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
F3
IO61RSB0
F4
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
D5
F9
VCC
B2
D6
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO17RSB0
D8
VCCIB1
B5
D9
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
IO210PSB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
B6
IO21RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO27RSB0
B8
IO34RSB0
B9
IO44RSB0
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NSB1
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
B10
B11
B12
B13
B14
B15
B16
C1
IO51RSB0
G2
IO57RSB0
G3
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
G4
G5
E2
G6
VCC
GBA2/IO78PDB1
IO81PDB1
E3
G7
GND
E4
G8
GND
IO224NDB3
IO225NDB3
VMV3
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
IO11RSB0
E8
IO38RSB0
VCCIB1
Revision 5
4-23
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
G13
G14
G15
G16
H1
GCC1/IO91PPB1
IO90NPB1
K1
K2
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
IO88PDB1
K3
VCCIB2
IO88NDB1
K4
IO147RSB2
IO136RSB2
VCCIB2
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
K5
H2
K6
VCC
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
GFC0/IO209NPB3
VCC
K9
GND
IO110NDB1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
IO194PSB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
GND
VCC
H8
GND
VCCIB1
H9
GND
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
N4
N5
L2
N6
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
L3
N7
GCB0/IO92NPB1
GFA2/IO206PSB3
GFA1/IO207PDB3
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO205NDB3
GFB2/IO205PDB3
VCC
L8
VCC
J5
L9
VCC
IO110PDB1
VJTAG
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
J7
GND
GND
GDC0/IO111NDB1
GDA1/IO113PDB1
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
J8
GND
VCCIB1
J9
GND
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
IO197NSB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PSB1
P4
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
P5
P6
P7
P8
4-24
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG256
FG256
Pin Number A3P1000 Function
Pin Number A3P1000 Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
T13
T14
T15
T16
IO120RSB2
GDA2/IO114RSB2
TMS
GND
TCK
VPUMP
TRST
GDA0/IO113NDB1
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Revision 5
4-25
Package Pin Assignments
FG484
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
4-26
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG484
FG484
Pin Number A3P1000 Function
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GND
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO63RSB0
IO66RSB0
IO68RSB0
IO70RSB0
NC
D7
D8
GAB0/IO02RSB0
IO16RSB0
IO22RSB0
IO28RSB0
IO35RSB0
IO45RSB0
IO50RSB0
IO55RSB0
IO61RSB0
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
GND
A3
VCCIB0
D9
A4
IO07RSB0
IO09RSB0
IO13RSB0
IO18RSB0
IO20RSB0
IO26RSB0
IO32RSB0
IO40RSB0
IO41RSB0
IO53RSB0
IO59RSB0
IO64RSB0
IO65RSB0
IO67RSB0
IO69RSB0
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
A6
NC
A7
VCCIB1
GND
A8
A9
VCCIB3
IO220PDB3
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
C2
C3
C4
NC
C5
GND
C6
IO10RSB0
IO14RSB0
VCC
NC
C7
NC
C8
NC
C9
VCC
IO219NDB3
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
IO30RSB0
IO37RSB0
IO43RSB0
NC
E2
E3
GND
VCCIB0
E4
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
GND
E5
GND
VCC
E6
GND
VCC
E7
GAB1/IO03RSB0
IO17RSB0
IO21RSB0
IO27RSB0
IO34RSB0
IO44RSB0
IO51RSB0
IO57RSB0
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
GBA2/IO78PDB1
IO81PDB1
GND
B2
VCCIB3
NC
E8
B3
NC
NC
E9
B4
IO06RSB0
IO08RSB0
IO12RSB0
IO15RSB0
IO19RSB0
IO24RSB0
IO31RSB0
IO39RSB0
IO48RSB0
IO54RSB0
IO58RSB0
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
B6
NC
B7
NC
B8
VCCIB1
IO219PDB3
IO220NDB3
NC
B9
B10
B11
B12
B13
B14
D2
D3
D4
GND
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
D6
Revision 5
4-27
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
E21
E22
F1
NC
IO84PDB1
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO52RSB0
IO60RSB0
GNDQ
J5
J6
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
GND
J7
F2
IO215PDB3
IO215NDB3
IO224NDB3
IO225NDB3
VMV3
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NPB1
IO85PDB1
IO85NDB1
NC
J8
F3
J9
F4
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
F5
VCC
F6
VCC
F7
IO11RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
VCC
F8
GND
F9
NC
VCCIB1
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
H4
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
H5
H6
H7
IO89PDB1
IO89NDB1
IO211PDB3
IO211NDB3
NC
H8
H9
VCCIB0
IO78NDB1
IO81NDB1
IO82PPB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
VCCIB0
K2
IO38RSB0
IO47RSB0
VCCIB0
K3
K4
IO210PPB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
VCC
K5
IO84NDB1
IO214NDB3
IO214PDB3
NC
VCCIB0
K6
VMV1
K7
G2
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
VCC
K8
G3
K9
G4
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
G5
GND
G6
GND
G7
NC
GND
G8
NC
VCC
G9
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO212NDB3
IO212PDB3
NC
VCCIB1
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
G10
G11
G12
J2
J3
J4
IO217NDB3
4-28
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG484
FG484
Pin Number A3P1000 Function
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
K19
K20
K21
K22
L1
IO88NDB1
IO94NPB1
IO98NDB1
IO98PDB1
NC
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
GND
P3
P4
IO199NDB3
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
GND
P5
VCC
P6
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PPB1
IO101PPB1
IO99PPB1
NC
P7
L2
IO200PDB3
IO210NPB3
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
P8
L3
P9
GND
L4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
VCC
L6
VCC
L7
VCC
L8
GND
L9
IO201NDB3
IO201PDB3
NC
VCCIB1
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
NC
GND
N3
GND
N4
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
GND
N5
VCC
N6
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
IO97PDB1
IO97NDB1
IO99NPB1
NC
N7
IO104PDB1
IO103NDB1
NC
N8
N9
VCC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
IO197PPB3
VCC
GND
R3
GND
R4
IO197NPB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
GND
R5
VCC
R6
VCCIB1
R7
IO200NDB3
IO206NDB3
GFA2/IO206PDB3
GFA1/IO207PDB3
VCCPLF
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
NC
R8
R9
VCCIB2
R10
R11
R12
R13
R14
R15
R16
VCCIB2
IO147RSB2
IO136RSB2
VCCIB2
IO205NDB3
GFB2/IO205PDB3
VCC
IO101NPB1
IO103PDB1
NC
VCCIB2
VMV2
GND
P2
IO199PDB3
IO110NDB1
Revision 5
4-29
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
R17
R18
R19
R20
R21
R22
T1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
VCC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
W1
W2
NC
IO191PDB3
NC
W3
W4
GND
IO104NDB1
IO105PDB1
IO198PDB3
IO198NDB3
NC
W5
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
W6
W7
T2
TCK
W8
T3
VPUMP
W9
T4
IO194PPB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO113NDB1
NC
T6
T7
IO108NDB1
IO109PDB1
NC
T8
T9
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
V5
GND
V6
NC
V7
NC
IO110PDB1
VJTAG
V8
NC
V9
VCCIB3
GDC0/IO111NDB1
GDA1/IO113PDB1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
IO191NDB3
NC
Y3
Y4
IO182RSB2
GND
IO108PDB1
IO105NDB1
IO195PDB3
IO195NDB3
IO194NPB3
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
Y5
Y6
IO177RSB2
IO174RSB2
VCC
Y7
U2
Y8
U3
Y9
VCC
U4
GNDQ
Y10
Y11
Y12
Y13
Y14
IO154RSB2
IO148RSB2
IO140RSB2
NC
U5
TDO
U6
GND
U7
IO179RSB2
IO171RSB2
NC
U8
IO109NDB1
VCC
4-30
Revision 5
Automotive ProASIC3 Flash Family FPGAs
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Y15
Y16
VCC
NC
AB7
AB8
IO167RSB2
IO162RSB2
IO156RSB2
IO150RSB2
IO145RSB2
IO144RSB2
IO132RSB2
IO127RSB2
IO126RSB2
IO123RSB2
IO121RSB2
IO118RSB2
NC
Y17
NC
AB9
Y18
GND
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y19
NC
Y20
NC
Y21
NC
Y22
VCCIB1
GND
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AB2
AB3
AB4
AB5
AB6
VCCIB3
NC
IO181RSB2
IO178RSB2
IO175RSB2
IO169RSB2
IO166RSB2
IO160RSB2
IO152RSB2
IO146RSB2
IO139RSB2
IO133RSB2
NC
VCCIB2
GND
GND
NC
IO122RSB2
IO119RSB2
IO117RSB2
NC
NC
VCCIB1
GND
GND
GND
VCCIB2
IO180RSB2
IO176RSB2
IO173RSB2
Revision 5
4-31
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the Automotive ProASIC3
datasheet.
Revision
Changes
Page
Revision 5
(January 2013)
The "Automotive ProASIC3 Ordering Information" section has been updated to
mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement
IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43222).
1-III
Added a note to Table 2-2 • Recommended Operating Conditions (SAR 43675): The
programming temperature range supported is Tambient = 0°C to 85°C.
2-2
The note in Table 2-116 • Automotive ProASIC3 CCC/PLL Specification referring the
reader to SmartGen was revised to refer instead to the online help associated with
the core (SAR 42560).
2-80
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
1-6
2-2
Revision 4
(September 2012)
The "Specifying I/O States During Programming" section is new (SAR 34691).
Table 2-2 • Recommended Operating Conditions was revised to change VPUMP
values for programming mode from "3.0 to 3.6" to "3.15 to 3.45" (SAR 34703).
Maximum values for VIL and VIH were corrected in LVPECL Table 2-86 • Minimum
and Maximum DC Input and Output Levels (SAR 37693).
2-52
Values were added for FDDRIMAX and FDDOMAX in the following tables (SAR 34804):
Table 2-99 • Input DDR Propagation Delays (TJ = 135°C)
2-64 to
2-68
Table 2-100 • Input DDR Propagation Delays (TJ = 115°C)
Table 2-102 • Output DDR Propagation Delays (TJ = 135°C)
Table 2-103 • Output DDR Propagation Delays (TJ = 115°C)
Added values for minimum pulse width and removed the FRMAX row from
Table 2-108 through Table 2-115 in the "Global Tree Timing Characteristics" section.
Use the software to determine the FRMAX for the device you are using (SAR 36966).
2-76
SRAM collision data was added to Table 2-117 • RAM4K9 through Table 2-120 • 2-86 to
RAM512X18. Maximum frequency, FMAX, was updated in Table 2-118 • RAM512X18
(SAR 40859).
2-89
The "VMVx I/O Supply Voltage (quiet)" section was revised. The sentence, "Within
the package, the VMV plane is decoupled from the simultaneous switching noise
originating from the output buffer VCCI domain" was replaced with, "Within the
package, the VMV plane biases the input stage of the I/Os in the I/O banks" (SAR
38323). VMV pins must be connected to the corresponding VCCI pins, as noted in
the "VMVx I/O Supply Voltage (quiet)" section, for an ESD enhancement.
3-1
Libero Integrated Design Environment (IDE) was changed to Libero Systeom-on-
Chip (SoC) throughout the document (SAR 40266).
N/A
1-1
Revision 3
The "Security" section was modified to clarify that Microsemi does not support
(September 2012) read-back of programmed data.
Revision 5
5-1
Datasheet Information
Revision
Changes
Page
Revision 2
(May 2012)
The "Extended Temperature AEC-Q100–Qualified Devices" section was modified to
include the low end of the temperature range, –40°C, for Grade 1 and Grade 2
AEC-Q100 qualified devices (SAR 34915).
I
The "In-System Programming (ISP) and Security" section and "Security" section
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 34674).
I, 1-1
III
The Y security option and Licensed DPA Logo were added to the "Automotive
ProASIC3 Ordering Information" section. The trademarked Licensed DPA Logo
identifies that a product is covered by a DPA counter-measures license from
Cryptography Research (SAR 34719).
A note defining TA and TJ was added to the "Automotive ProASIC3 Ordering
Information" section (SAR 37547).
III
The following sentence was deleted from the "Advanced Architecture" section: "In
addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of Automotive ProASIC3 devices via an IEEE 1532 JTAG
interface" (SAR 34682).
1-3
In Table 2-2 • Recommended Operating Conditions, VCCPLL analog power supply
(PLL) was changed from "1.4 to 1.6" to "1.425 to 1.575" (SAR 34718).
2-2
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"
section of the Global Resources chapter in the Automotive ProASIC3 FPGA Fabric
User's Guide (SAR 34738).
2-10
tDOUT was corrected to tDIN in Figure 2-4 • Input Buffer Timing Model and Delays
(example) (SAR 37111).
2-13
2-23
2-27
The equations in the notes for Table 2-27 • I/O Weak Pull-Up/Pull-Down Resistances
were corrected (SAR 34754).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34882).
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34795):
"It uses a 5 V–tolerant input buffer and push-pull output buffer."
2-33
2-50
The table notes for Table 2-82 • Minimum and Maximum DC Input and Output Levels
were not necessary and were removed (SAR 34811).
The following figures were deleted (SAR 29991). Reference was made to a new
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs, which covers these cases in detail (SAR 34861).
Figure 2-35 • Write Access after Write to Same Address
Figure 2-36 • Read Access after Write to Same Address
Figure 2-35 • Read Access after Write to Same Address
2-83,
2-86,
2-92, 2-94
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-39 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35744).
Figure 2-37 • FIFO Read and Figure 2-38 • FIFO Write are new (SAR 34838).
2-91
2-80
Table 2-116 • Automotive ProASIC3 CCC/PLL Specification was updated. A note
was added to indicate that when the CCC/PLL core is generated by Microsemi core
generator software, not all delay values of the specified delay increments are
available (SAR 34822).
5-2
Revision 5
Automotive ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Revision 2
(continued)
The "Pin Descriptions and Packaging" chapter has been added (SAR 34767),
The "VQ100" pin table for A3P125 has been added (SAR 37944).
3-1
4-3
4-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34767).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "Automotive
ProASIC3 Device Status" table on page II indicates the status for each device in the
device family.
N/A
Revision
Changes
Page
Revision 1
(Dec 2009)
The QNG132 package was added to the "Automotive ProASIC3 Product Family"
table, "I/Os Per Package" table, "Automotive ProASIC3 Ordering Information", and
"Temperature Grade Offerings".
I – IV
Product Brief v1.1
Packaging v1.1
Pin tables for A3P125 and A3P250 were added for the "QN132" package.
4-6
Revision 5
5-3
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "Automotive ProASIC3 Device Status" table on page II, is designated as either "Product
Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
5-4
Revision 5
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solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
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