A3P250-FGG144C [MICROSEMI]
Field Programmable Gate Array, 6144 CLBs, 250000 Gates, 350MHz, CMOS, PBGA144, 1 MM PITCH, GREEN, FBGA-144;
| 型号： | A3P250-FGG144C |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 6144 CLBs, 250000 Gates, 350MHz, CMOS, PBGA144, 1 MM PITCH, GREEN, FBGA-144 栅 |
| 文件： | 总192页 (文件大小：2773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v2.0
Automotive ProASIC®3 Flash Family FPGAs
®
with Grade 2 and Grade 1 AEC-Q100 Support
Low Power
Features and Benefits
•
•
•
1.5 V Core Voltage
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Temperature AEC-Q100–Qualified Devices
•
•
•
Grade 2 105°C T (115°C T )
A J
Grade 1 125°C T (135°C T )
A
J
High-Performance Routing Hierarchy
PPAP Documentation
•
•
•
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Firm-Error Immune
•
•
Only Automotive FPGAs to Offer Firm-Error Immunity
Can Be Used Without Configuration Upset Risk
Advanced I/O
High Capacity
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
•
•
•
60 k to 1 Million System Gates
Up to 144 kbits of SRAM
Up to 300 User I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Reprogrammable Flash Technology
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and A3P1000)
•
•
•
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the Automotive
ProASIC3 Family
On-Chip User Nonvolatile Memory
•
1 kbit of FlashROM with Synchronous Interface
High Performance
•
•
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
Clock Conditioning Circuit (CCC) and PLL
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
In-System Programming (ISP) and Security
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–
compliant)
•
Wide Input Frequency Range (1.5 MHz up to 350 MHz)
SRAMs
®
•
FlashLock to Secure FPGA Contents (anti-tampering)
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
Table 1 •
Automotive ProASIC3 Product Family
ProASIC3 Devices
System Gates
A3P060
A3P125
125 k
3,072
36
A3P250
250 k
6,144
36
A3P1000
60 k
1,536
18
1 M
24,576
144
32
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
4
8
8
FlashROM Bits
1 k
Yes
1
1 k
1 k
1 k
Yes
Yes
Yes
1
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals*
I/O Banks
1
1
18
18
18
18
2
2
4
4
Maximum User I/Os
96
133
157
300
Package Pins
VQFP
VQ100
FG144
VQ100
FG144
VQ100
FG144, FG256
FBGA
FG144, FG256, FG484
Note: *Six chip-wide (main) globals and three additional global networks in each quadrant are available.
August 2007
i
© 2007 Actel Corporation
See the Actel website for the latest version of the datasheet.
Automotive ProASIC3 Flash Family FPGAs
I/Os Per Package
ProASIC3 Devices
A3P060
A3P125
A3P250
I/O Type
A3P1000
Package
VQ100
71
96
–
71
97
–
68
97
13
24
38
–
–
–
FG144
97
25
44
74
FG256 3
FG484 3
Notes:
157
–
177
300
–
–
1. When considering migrating your design to a lower- or higher-density device, refer to "Package Pin Assignments" starting on page
4-1 to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of available single-ended I/Os by two.
3. FG256 and FG484 are footprint-compatible packages.
Automotive ProASIC3 Ordering Information
_
A3P1000
1
FG
144
T
G
Application (Temperature Range)
T = Grade 2 and Grade 1 AECQ100
Grade 2 = 105°C TA and 115°C TJ
Grade 1 = 125°C TA and 135°C TJ
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
=
=
VQ
FG
Very Thin Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
Automotive ProASIC3 Devices
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P1000 = 1,000,000 System Gates
Note: Minimum order quantities apply. Contact your local Actel sales office for details.
ii
v2.0
Automotive ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
VQ100
FG144
A3P060
A3P125
A3P250
C, I, T
C, I, T
C, I, T
–
A3P1000
–
C, I, T
C, I, T
C, I, T
C, I, T
C, I, T
C, I, T
C, I, T
FG256
–
–
–
–
FG484
Notes:
1. C = Commercial temperature range: 0°C to 70°C
2. I = Industrial temperature range: –40°C to 85°C
3. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C TA and 115°C TJ
Grade 1 = 125°C TA and 135°C TJ
4. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs datasheet.
Speed Grade and Temperature Grade Matrix
Temperature Grade
Std.
–1
T (Grade 1 and Grade 2), Commercial, Industrial
Notes:
✓
✓
1. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C TA and 115°C TJ
Grade 1 = 125°C TA and 135°C TJ
2. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs datasheet.
Contact your local Actel representative for device availability (http://www.actel.com/contact/default.aspx).
v2.0
iii
Automotive ProASIC3 Flash Family FPGAs
Table of Contents
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97
Package Pin Assignments
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Datasheet Information
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
v2.1
v
Automotive ProASIC3 Flash Family FPGAs
Introduction and Overview
Security
General Description
The nonvolatile, flash-based Automotive ProASIC3
devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied.
Automotive ProASIC3 devices incorporate FlashLock,
Automotive ProASIC3 nonvolatile flash technology gives
automotive system designers the advantage of a secure,
low-power, single-chip solution that is live at power-up
(LAPU). Automotive ProASIC3 is reprogrammable and
offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density
systems using existing ASIC or FPGA design flows and
tools.
which
provides
a
unique
combination
of
reprogrammability and design security without external
overhead, advantages that only an FPGA with
nonvolatile flash programming can offer.
Automotive ProASIC3 devices utilize a 128-bit flash-
Automotive ProASIC3 devices offer 1 kbit of on-chip,
reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated
phase-locked loop (PLL). Automotive ProASIC3 devices
have up to 1 million system gates, supported with up to
144 kbits of SRAM and up to 300 user I/Os.
based lock and
a
separate AES key to secure
programmed intellectual property and configuration
data. In addition, all FlashROM data in Automotive
ProASIC3 devices can be encrypted prior to loading,
using the industry-leading AES-128 (FIPS192) bit block
cipher encryption standard. The AES was adopted by the
National Institute of Standards and Technology (NIST) in
2000 and replaces the 1977 DES standard. Automotive
ProASIC3 devices have a built-in AES decryption engine
and a flash-based AES key that make them the most
comprehensive programmable logic device security
solution available today. Automotive ProASIC3 devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed Automotive ProASIC3 device
cannot be read back, although secure design verification
is possible. Additionally, security features of Automotive
ProASIC3 devices provide anti-tampering protection.
Automotive ProASIC3 devices are the only firm-error-
immune automotive grade FPGAs. Firm-error immunity
makes them ideally suited for demanding applications in
powertrain, safety, and telematics-based subsystems,
where firm-error failure is not an option.
Firm errors in SRAM-based FPGAs can result in high
defect levels in field-deployed systems. These
unavoidable defects must be considered separately from
standard defects and failure mechanisms when looking
at overall system quality and reliability.
Flash Advantages
Reduced Cost of Ownership
Security, built into the FPGA fabric, is an inherent
component of the Automotive ProASIC3 family. The flash
cells are located beneath seven metal layers, and many
device design and layout techniques have been used to
make invasive attacks extremely difficult. The
Automotive ProASIC3 family, with FlashLock and AES
security, is unique in being highly resistant to both
invasive and noninvasive attacks. Your valuable IP is
protected and secure. An Automotive ProASIC3 device
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, flash-based Automotive ProASIC3 devices allow
all functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic. Flash-
based FPGAs are LAPU Class 0 devices, offering the
lowest available power in a single-chip device and
providing firm-error immunity. The Automotive ProASIC3
family device architecture mitigates the need for ASIC
migration at high user volumes. This makes the
provides
the
most
impenetrable
security
for
programmable logic designs.
Single Chip
Automotive ProASIC3 family
a
cost-effective ASIC
Flash-based FPGAs store their configuration information
in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
FPGAs). Therefore, flash-based Automotive ProASIC3
replacement solution, especially for automotive
applications.
v2.0
1-1
Automotive ProASIC3 Flash Family FPGAs
FPGAs do not require system configuration components
such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs
and PCB area, and increases security and system
reliability.
applications. Automotive ProASIC3 devices have only a
very limited power-on current surge and no high-current
transition period, both of which occur on many FPGAs.
Automotive ProASIC3 devices also have low dynamic
power consumption to further maximize power savings.
Live at Power-Up
Advanced Flash Technology
The Actel flash-based Automotive ProASIC3 devices
support Level 0 of the LAPU classification standard. This
feature helps in system component initialization,
execution of critical tasks before the processor wakes up,
setup and configuration of memory blocks, clock
generation, and bus activity management. The LAPU
feature of flash-based Automotive ProASIC3 devices
greatly simplifies total system design and reduces total
system cost, often eliminating the need for CPLDs and
external clock generation PLLs. In addition, glitches and
brownouts in system power will not corrupt the
Automotive ProASIC3 device's flash configuration, and
unlike SRAM-based FPGAs, the device will not have to be
reloaded when system power is restored. This enables
the reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flash-
based Automotive ProASIC3 devices simplify total system
design and reduce cost and design risk while increasing
system reliability and improving system initialization
time.
The Automotive ProASIC3 family offers many benefits,
including nonvolatility and reprogrammability, through
an advanced flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
Advanced Architecture
The proprietary Automotive ProASIC3 architecture
provides granularity comparable to standard-cell ASICs.
The Automotive ProASIC3 device consists of five distinct
and programmable architectural features (Figure 1-1 and
Figure 1-2 on page 1-3):
•
•
•
•
•
FPGA VersaTiles
Refer to the "I/O Power-Up and Supply Voltage
Thresholds for Power-On Reset (Commercial and
Industrial)" section on page 3-4 for more information.
Dedicated FlashROM
Dedicated SRAM memory
Extensive CCCs and PLLs
Advanced I/O structure
Firm-Error Immune
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of Automotive
ProASIC3 flash-based FPGAs. Once it is programmed, the
flash cell configuration element of Automotive ProASIC3
FPGAs cannot be altered by high-energy neutrons and is
therefore immune to them. Recoverable (or soft) errors
occur in the user data SRAM of all FPGA devices. These
can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a
latch by programming the appropriate flash switch
interconnections. The versatility of the Automotive
ProASIC3 core tile as either a three-input lookup table
(LUT) equivalent or a D-flip-flop/latch with enable allows
for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Actel ProASIC family of third-
generation-architecture flash FPGAs. VersaTiles are
connected with any of the four levels of routing
hierarchy. Flash switches are distributed throughout the
device
to
provide
nonvolatile,
reconfigurable
interconnect programming. Maximum core utilization is
possible for virtually any design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
Automotive ProASIC3 devices via an IEEE 1532 JTAG
interface.
Low Power
Flash-based Automotive ProASIC3 devices exhibit very
low power characteristics, similar to those of an ASIC,
making them an ideal choice for power-sensitive
1-2
v2.0
Automotive ProASIC3 Flash Family FPGAs
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 1
Figure 1-1 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125)
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
(A3P600 and A3P1000)
Bank 2
Figure 1-2 • Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P600 and A3P1000)
v2.0
1-3
Automotive ProASIC3 Flash Family FPGAs
VersaTiles
The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles.
The Automotive ProASIC3 VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
For more information about VersaTiles, refer to the "VersaTile" section on page 2-2.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
determine the bank, and the four least significant bits
(LSBs) of the FlashROM address define the byte.
User Nonvolatile FlashROM
Actel Automotive ProASIC3 devices have 1 kbit of on-
chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
The Actel Automotive ProASIC3 development software
solutions, Libero® Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM.
One such feature is auto-generation of sequential
programming files for applications requiring a unique
serial number in each part. Another feature allows the
inclusion of static data for system version control. Data
for the FlashROM can be generated quickly and easily
using Actel Libero IDE and Designer software tools.
Comprehensive programming file support is also
included to allow for easy programming of large
numbers of parts with differing FlashROM contents.
•
•
•
•
Unique protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example,
infotainment systems)
•
Secure key storage for secure communications
algorithms
•
•
•
Asset management/tracking
Date stamping
SRAM
Version management
The FlashROM is written using the standard Automotive
ProASIC3 IEEE 1532 JTAG programming interface.
Automotive ProASIC3 devices have embedded SRAM
blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256×18, 512×9, 1k×4, 2k×2,
and 4k×1 bits. The individual blocks have independent
read and write ports that can be configured with
different bit widths on each port. For example, data can
be sent through a 4-bit port and read as a single
bitstream. The embedded SRAM blocks can be initialized
via the device JTAG port (ROM emulation mode) using
the UJTAG macro. For more information, refer to the
application note, UJTAG Applications in ProASIC3/E
Devices.
The FlashROM can be programmed via the JTAG
programming interface, and its contents can be read
back either through the JTAG programming interface or
via direct FPGA core addressing. Note that the FlashROM
can only be programmed from the JTAG interface and
cannot be programmed from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits;
however, reading is performed on a byte-by-byte basis
using a synchronous interface. A 7-bit address from the
FPGA core defines which of the 8 banks and which of the
16 bytes within that bank are being read. The three most
significant bits (MSBs) of the FlashROM address
1-4
v2.0
Automotive ProASIC3 Flash Family FPGAs
•
•
Exceptional tolerance to input period jitter—
allowable input jitter is up to 1.5 ns (for PLL only)
PLL and CCC
Automotive ProASIC3 devices provide designers with
very flexible clock conditioning circuit (CCC) capabilities.
Each member of the Automotive ProASIC3 family
contains six CCCs. One CCC (center west side) has a PLL.
Four precise phases; maximum misalignment
between adjacent phases of 40 ps × 350 MHz /
fOUT_CCC (for PLL only)
The six CCC blocks are located at the four corners and the
centers of the east and west sides. One CCC (center west
side) has a PLL.
Global Clocking
Automotive ProASIC3 devices have extensive support for
multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive
global clock distribution network.
All six CCC blocks are usable; the four corner CCCs and
the east CCC allow simple clock delay operations as well
as clock spine access (refer to the "Clock Conditioning
Circuits" section on page 2-13 for more information).
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks. The VersaNets can be driven by the CCC or
directly accessed from the core via multiplexers (MUXes).
The VersaNets can be used to distribute low-skew clock
signals or for rapid distribution of high-fanout nets.
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several inputs located near the
CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
I/Os with Advanced I/O Standards
The Automotive ProASIC3 family of FPGAs features a
flexible I/O structure, supporting a range of voltages
(1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3
FPGAs support many different I/O standards—single-
ended and differential.
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock delay adjustment via programmable and
fixed delays from –7.56 ns to +11.12 ns
2
programmable delay types for clock skew
The I/Os are organized into banks, with two or four
banks per device. Refer to Table 2-18 on page 2-44 for
details on I/O bank configuration. The configuration of
these banks determines the I/O standards supported (see
Table 2-18 on page 2-44 for more information).
minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration (for PLL only).
Each I/O module contains several input, output, and
enable
registers.
These
registers
allow
the
implementation of the following:
•
•
Output duty cycle = 50% 1.5% or better (for PLL
only)
•
•
Single-Data-Rate applications
Low output jitter: worst case < 2.5% × clock period
peak-to-peak period jitter when single global
network used (for PLL only)
Double-Data-Rate applications—DDR LVDS, BLVDS,
and M-LVDS I/Os for point-to-point communications
See the "DDR Module Specifications" section on page 3-
64 for more information.
•
•
Maximum acquisition time is 300 µs (for PLL only)
Low power consumption of 5 mW
Automotive ProASIC3 banks for the A3P250 and A3P1000
devices support LVPECL, LVDS, BLVDS, and M-LVDS.
BLVDS and M-LVDS can support up to 20 loads.
v2.0
1-5
Automotive ProASIC3 Flash Family FPGAs
Related Documents
Application Notes
ProASIC3/E I/O Usage Guide
http://www.actel.com/documents/PA3_E_IO_AN.pdf
In-System Programming (ISP) in ProASIC3/E Using FlashPro3
http://www.actel.com/documents/PA3_E_ISP_AN.pdf
ProASIC3/E FlashROM
http://www.actel.com/documents/PA3_E_FROM_AN.pdf
ProASIC3/E Security
http://www.actel.com/documents/PA3_E_Security_AN.pdf
ProASIC3/E SRAM/FIFO Blocks
http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf
Programming ProASIC3/E Using a Microprocessor
http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf
UJTAG Applications in ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf
Using DDR for ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_DDR_AN.pdf
Using Global Resources in Actel ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_Global_AN.pdf
Power-Up/Down Behavior of ProASIC3/E Devices
http://www.actel.com/documents/ProASIC3_E_PowerUp_AN.pdf
For additional Automotive ProASIC3 application notes, go to http://www.actel.com/techdocs/an.aspx.
User’s Guides
SmartGen Cores Reference Guide
http://www.actel.com/documents/gen_refguide_ug.pdf
Designer User’s Guide
http://www.actel.com/documents/designer_ug.pdf
Fusion, IGLOO/e and ProASIC3/E Macro Library Guide
http://www.actel.com/documents/pa3_libguide_ug.pdf
1-6
v2.0
Automotive ProASIC3 Flash Family FPGAs
Device Architecture
stores the programming information (Figure 2-1). One is
the sensing transistor, which is only used for writing and
verification of the floating gate voltage. The other is the
switching transistor. The latter is used to connect or
separate routing nets, or to configure VersaTile logic. It is
also used to erase the floating gate. Dedicated high-
performance lines are connected as required using the
flash switch for fast, low-skew, global signal distribution
throughout the device core. Maximum core utilization is
possible for virtually any design. The use of the flash
switch technology also removes the possibility of firm
errors.
Introduction
Flash Technology
Advanced Flash Switch
Unlike SRAM FPGAs, the Automotive ProASIC3 family
uses
a
live-at-power-up ISP flash switch as its
programming element. Flash cells are distributed
throughout the device to provide nonvolatile,
reconfigurable programming to connect signal lines to
the appropriate VersaTile inputs and outputs. In the flash
switch, two transistors share the floating gate, which
Switch In
Floating Gate
Sensing
Switching
Word
Switch Out
Figure 2-1 • Automotive ProASIC3 Flash-Based Switch
v2.0
2-1
Automotive ProASIC3 Flash Family FPGAs
•
•
D-flip-flop with clear or set
Device Overview
The Automotive ProASIC3 device family consists of
distinct programmable architectural features (Figure 2-2
and Figure 2-3 on page 2-3):
Enable D-flip-flop with clear or set (on a fourth
input)
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions can be connected with
any of the four levels of routing hierarchy.
•
•
•
•
FPGA fabric/core (VersaTiles)
Routing and clock resources (VersaNets)
FlashROM
Dedicated SRAM memory
When the VersaTile is used as an enable D-flip-flop,
SET/CLR is supported by a fourth input. The SET/CLR
signal can only be routed to this fourth input over the
VersaNet (global) network. However, if, in the user’s
design, the SET/CLR signal is not routed over the
VersaNet network, a compile warning message will be
given, and the intended logic function will be
implemented by two VersaTiles instead of one.
Core Architecture
VersaTile
The proprietary Automotive ProASIC3 family architecture
provides granularity comparable to gate arrays. The
Automotive ProASIC3 device core consists of a sea-of-
VersaTiles architecture.
The output of the VersaTile is F2 (Figure 2-4 on page 2-4)
when the connection is to the ultra-fast local lines, or YL
when the connection is to the efficient long-line or very-
long-line resources.
As illustrated in Figure 2-4 on page 2-4, there are four
inputs in a logic VersaTile cell, and each VersaTile can be
configured using the appropriate flash switch
connections:
•
•
Any 3-input logic function
Latch with clear or set
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 1
Figure 2-2 • Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125)
2-2
v2.0
Automotive ProASIC3 Flash Family FPGAs
Bank 0
CCC
RAM Block
4,608-Bit SRAM
or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
(A3P600 and A3P1000)
Bank 2
Figure 2-3 • Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
v2.0
2-3
Automotive ProASIC3 Flash Family FPGAs
0
1
Y
Pin 1
Data
X3
0
1
0
1
F2
YL
0
1
CLK
X2
CLR/
Enable
X1
CLR
XC*
Ground
Legend:
Via (hard connection)
Switch (flash connection)
Note: *This input can only be connected to the global clock distribution network.
Figure 2-4 • Automotive ProASIC3 Core VersaTile
2-4
v2.0
Automotive ProASIC3 Flash Family FPGAs
Array Coordinates
During many place-and-route operations in the Actel
Designer software tool, it is possible to set constraints
that require array coordinates. Table 2-1 provides array
coordinates of core cells and memory blocks. The array
coordinates are measured from the lower left (0, 0). They
can be used in region constraints for specific logic
groups/blocks, designated by a wildcard, and can contain
core cells, memories, and I/Os.
not listed in Table 2-1. The Designer ChipPlanner tool
provides the array coordinates of all I/O locations. I/O
and cell coordinates are used for placement constraints.
However, I/O placement is easier by package pin
assignment.
Figure 2-5 illustrates the array coordinates of an A3P1000
device. For more information on how to use array
coordinates for region/placement constraints, see the
Designer User's Guide or online help (available in the
software) for Automotive ProASIC3 software tools.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
cells and core cells. In addition, the I/O coordinate system
changes depending on the die/package combination. It is
Table 2-1 • Automotive ProASIC3 Array Coordinates
VersaTiles
Memory Rows
Entire Die
Min.
Max.
Bottom
Top
(x, y)
(3, 26)
(3, 26)
(3, 50)
(3, 100)
Min.
Max.
(x, y)
Device
A3P060
A3P125
A3P250
A3P1000
x
3
3
3
3
y
2
2
2
4
x
y
(x, y)
None
None
None
(3, 2)
(x, y)
(0, 0)
(0, 0)
(0, 0)
(0, 0)
66
25
25
49
99
(69, 29)
(133, 29)
(133, 53)
(261, 103)
130
130
258
Top Row (7, 103) to (253, 103)
Bottom Row (5, 102) to (256, 102)
I/O Tile
(0, 103)
(261, 103)
(3, 101)
(3, 100)
Memory
Blocks
(258, 101)
(258, 100)
Memory
Blocks
VersaTile (Core)
(3, 99)
(258, 99)
VersaTile (Core)
(258, 4)
VersaTile (Core)
VersaTile (Core)
(3, 4)
(258, 3)
(258, 2)
Memory
Blocks
(3, 3)
(3, 2)
Memory
Blocks
(261, 1)
(261, 0)
(0, 0)
I/O Tile
UJTAG FlashROM
Top Row (5, 1) to (242, 1)
Top Row (233, 1) to (256, 1)
Bottom Row (7, 0) to (239, 0)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 101) to (2, 101)}; east side
coordinates are {(259, 2) to (261, 2)} to {(259, 101) to (261, 101)}.
Figure 2-5 • Array Coordinates for A3P1000
v2.0
2-5
Automotive ProASIC3 Flash Family FPGAs
Routing Architecture
Routing Resources
The routing structure of Automotive ProASIC3 devices is
designed to provide high performance through a flexible
four-level hierarchy of routing resources: ultra-fast local
resources; efficient long-line resources; high-speed, very-
long-line resources; and the high-performance VersaNet
networks.
The high-speed, very-long-line resources, which span the
entire device with minimal delay, are used to route very
long or high-fanout nets: length +/–12 VersaTiles in the
vertical direction and length +/–16 in the horizontal
direction from a given core VersaTile (Figure 2-8 on page
2-8). Very long lines in Automotive ProASIC3 devices
have been enhanced over those in previous ProASIC
families. This provides a significant performance boost
for long-reach signals.
The ultra-fast local resources are dedicated lines that allow
the output of each VersaTile to connect directly to every
input of the eight surrounding VersaTiles (Figure 2-6). The
exception to this is that the SET/CLR input of a VersaTile
configured as a D-flip-flop is driven only by the VersaTile
global network.
The high-performance VersaNet global networks are
low-skew, high-fanout nets that are accessible from
external pins or internal logic (Figure 2-9 on page 2-9).
These nets are typically used to distribute clocks, resets,
and other high-fanout nets requiring minimum skew.
The VersaNet networks are implemented as clock trees,
and signals can be introduced at any junction. These can
be employed hierarchically, with signals accessing every
input on all VersaTiles.
The efficient long-line resources provide routing for longer
distances and higher-fanout connections. These resources
vary in length (spanning one, two, or four VersaTiles), run
both vertically and horizontally, and cover the entire
Automotive ProASIC3 device (Figure 2-7 on page 2-7).
Each VersaTile can drive signals onto the efficient long-line
resources, which can access every input of every VersaTile.
Routing software automatically inserts active buffers to
limit loading effects.
Long Lines
L
L
L
L
L
L
Inputs
Ultra-Fast Local Lines
(connects a VersaTile to the
adjacent VersaTile, I/O buffer,
or memory block)
L
L
L
Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.
Figure 2-6 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
2-6
v2.0
Automotive ProASIC3 Flash Family FPGAs
Spans 4 VersaTiles
L
Spans 1 VersaTile
Spans 2 VersaTiles
L
VersaTile
L
L
L
L
L
L
L
L
L
L
L
L
Spans 1 VersaTile
L
L
L
L
Spans 2 VersaTiles
Spans 4 VersaTiles
L
L
L
L
L
L
L
L
L
L
L
L
Figure 2-7 • Efficient Long-Line Resources
v2.0
2-7
Automotive ProASIC3 Flash Family FPGAs
High-Speed, Very-Long-Line Resources
Pad Ring
SRAM
16×12 Block of VersaTiles
Pad Ring
Figure 2-8 • Very-Long-Line Resources
2-8
v2.0
Automotive ProASIC3 Flash Family FPGAs
quadrants. Each core VersaTile has access to nine global
network resources: three quadrant and six chip-wide (main)
global networks, and a total of 18 globals on the device.
Each of these networks contains spines and ribs that reach
all the VersaTiles in the quadrants (Figure 2-10 on page 2-
10). This flexible VersaNet global network architecture
allows users to map up to 144 different internal/external
clocks in an Automotive ProASIC3 device. Details on the
VersaNet networks are given in Table 2-2 on page 2-10.
The flexible use of the Automotive ProASIC3 VersaNet
global network allows the designer to address several
design requirements. User applications that are clock-
resource-intensive can easily route external or gated
internal clocks using VersaNet global routing networks.
Designers can also drastically reduce delay penalties and
minimize resource usage by mapping critical, high-fanout
nets to the VersaNet global network.
Clock Resources (VersaNets)
Automotive ProASIC3 devices offer powerful and flexible
control of circuit timing through the use of analog
circuitry. Each chip has up to six CCCs. The west CCC also
contains a phase-locked loop (PLL) core, delay lines, a
phase shifter (0°, 90°, 180°, 270°), and clock
multipliers/dividers. Each CCC has all the circuitry needed
for the selection and interconnection of inputs to the
VersaNet global network. The east and west CCCs each
have access to three VersaNet global lines on each side of
the chip (six total lines).
Advantages of the VersaNet Approach
One of the architectural benefits of Automotive ProASIC3
is the set of powerful and low-delay VersaNet global
networks. Automotive ProASIC3 offers six chip (main)
global networks that are distributed from the center of the
FPGA array (Figure 2-9). In addition, Automotive ProASIC3
devices have three regional globals in each of the four chip
High-Performance
VersaNet Global Network
Quadrant Global Pads
Pad Ring
Top Spine
Chip (main)
Global Network
Global
Pads
Chip (main)
Global Pads
Global Spine
Global Ribs
Bottom Spine
Spine-Selection
Tree MUX
Pad Ring
Note:
Figure 2-9 • Overview of Automotive ProASIC3 VersaNet Global Network
v2.0
2-9
Automotive ProASIC3 Flash Family FPGAs
Northwest Quadrant Global Network
CCC
CCC
3
3
3
3
3
Chip (main)
Global
Network
6
6
6
6
6
6
6
CCC
3
CCC
6
3
3
3
3
CCC
CCC
Southeast Quadrant Global Network
Figure 2-10 • Global Network Architecture
Table 2-2 • Automotive ProASIC3 Globals/Spines/Rows by Device
A3P060
A3P125
A3P250
A3P1000
9
Global VersaNets (Trees)
VersaNet Spines/Tree
9
9
4
9
8
4
36
16
Total Spines
36
72
144
VersaTiles in Each Top or Bottom Spine
Total VersaTiles
384
1,536
12
384
3,072
12
768
6,144
24
1,536
24,576
48
Rows in Each Top or Bottom Spine
other high-fanout nets in ProASIC3 devices. Optimal
usage of these low-skew networks can result in
significant improvement in design performance on
Automotive ProASIC3 devices.
VersaNet Global Networks and Spine Access
The ProASIC3 architecture contains
a total of 18
segmented global networks that can access the
VersaTiles, SRAM, and I/O tiles of the Automotive
ProASIC3 device. There are nine global network
resources in each device quadrant: three quadrant
globals and six chip (main) global networks. Each device
has a total of 18 globals. These VersaNet global networks
offer fast, low-skew routing resources for high-fanout
nets, including clock signals. In addition, these highly
segmented global networks offer users the flexibility to
create low-skew local networks using spines for up to
144 internal/external clocks (in an A3P1000 device) or
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
Note that there are three quadrant spines in each
quadrant of the device. There are four quadrant global
network regions per device (Figure 2-10).
The spines are the vertical branches of the global
network tree, shown in Figure 2-11 on page 2-11. Each
2-10
v2.0
Automotive ProASIC3 Flash Family FPGAs
spine in a vertical column of a chip (main) global
network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of
the die.
can have a significant effect on system performance for
high-fanout inputs to a design.
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-12 on page 2-12. The
spine drivers for each spine are located in the middle of
the die.
Each spine and its associated ribs cover a certain area of
the Automotive ProASIC3 device (the "scope" of the
spine; see Figure 2-9 on page 2-9). Each spine is accessed
by the dedicated global network MUX tree architecture,
which defines how a particular spine is driven—either by
the signal on the global network from a CCC, for
example, or by another net defined by the user (Figure 2-
12 on page 2-12). Quadrant spines can be driven from
user I/Os on the north and south sides of the die. The
ability to drive spines in the quadrant global networks
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/Os on the north and south sides of the
device.
For details on using spines in ProASIC3 devices, see the
Actel application note Using Global Resources in Actel
ProASIC3/E Devices.
Quadrant Global Pads
High-Performance
Global Network
T1
T2
T3
Pad Ring
Top Spine
Global
Pads
Chip (main)
Global Pads
Global Spine
Global Ribs
Bottom Spine
Scope of Spine
(shaded area
plus local RAMs
and I/Os)
Spine-Selection
MUX
Embedded
RAM Blocks
Pad Ring
Logic Tiles
B1
B2
B3
Figure 2-11 • Automotive ProASIC3 Spines in a Global Clock Tree Network
v2.0
2-11
Automotive ProASIC3 Flash Family FPGAs
Clock Aggregation
Clock aggregation allows for multi-spine clock domains.
A MUX tree provides the necessary flexibility to allow
long lines or I/Os to access domains of one, two, or four
global spines. Signal access to the clock aggregation
system is achieved through long-line resources in the
central rib, and also through local resources in the north
and south ribs, allowing I/Os to feed directly into the
clock system. As Figure 2-13 indicates, this access system
is contiguous.
There is no break in the middle of the chip for the north
and south I/O VersaNet access. This is different from the
quadrant clocks located in these ribs, which only reach
the middle of the rib. Refer to the Using Global
Resources in Actel ProASIC3/E Devices application note.
Internal/External
Signals
Internal/External
Signals
Tree Node MUX
Tree Node MUX
Internal/External
Signal
Tree Node MUX
Global Rib
Internal/External
Signal
Global Driver MUX
Spine
Figure 2-12 • Spine Selection MUX of Global Tree
Global Spine
I/O Tiles
I/O Access
Global Rib
Global Driver and MUX
Tree Node MUX
Internal Signal Access
Global Signal Access
Figure 2-13 • Clock Aggregation Tree Architecture
2-12
v2.0
Automotive ProASIC3 Flash Family FPGAs
Electrical Specifications" section on page 2-18 for more
information.
Clock Conditioning Circuits
Overview of Clock Conditioning Circuitry
In Automotive ProASIC3 devices, the CCCs are used to
implement frequency division, frequency multiplication,
phase shifting, and delay operations.
Global Buffers with No Programmable Delays
The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS
macros are composite macros that include an I/O macro
driving
a global buffer, which uses a hardwired
connection.
The CCCs are available in six chip locations—each of the
four chip corners and the middle of the east and west
chip sides.
The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and
CLKINT macros are pass-through clock sources and do
not use the PLL or provide any programmable delay
functionality.
Each CCC can implement up to three independent global
buffers (with or without programmable delay) or a PLL
function (programmable frequency division/multiplication,
phase shift, and delays) with up to three global outputs.
Unused global outputs of a PLL can be used to
The CLKINT macro provides a global buffer function
driven by the FPGA core.
Many specific CLKBUF macros support the wide variety of
single-ended and differential I/O standards supported by
Automotive ProASIC3 devices. The available CLKBUF
macros are described in the Fusion, IGLOO/e and
ProASIC3/E Macro Library Guide.
implement independent global buffers, up to
maximum of three global outputs for a given CCC.
a
A global buffer can be placed in any of the three global
locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given
CCC.
Global Buffer with Programmable Delay
A PLL macro uses the CLKA CCC input to drive its reference
clock. It uses the GLA and, optionally, the GLB and GLC
global outputs to drive the global networks. A PLL macro
can also drive the YB and YC regular core outputs. The GLB
(or GLC) global output cannot be reused if the YB (or YC)
output is used (Figure 2-14 on page 2-14). Refer to the
"PLL Macro" section on page 2-15 for more information.
The CLKDLY macro is a pass-through clock source that
does not use the PLL, but provides the ability to delay the
clock input using a programmable delay. The CLKDLY
macro takes the selected clock input and adds a user-
defined delay element. This macro generates an output
clock phase shift from the input clock.
The CLKDLY macro can be driven by an INBUF* macro to
create a composite macro, where the I/O macro drives
the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be
placed in one of the dedicated global I/O locations.
Each global buffer, as well as the PLL reference clock, can
be driven from one of the following:
•
•
•
3 dedicated single-ended I/Os using a hardwired
connection
Many specific INBUF macros support the wide variety of
single-ended and differential I/O standards supported by
the Automotive ProASIC3 family. The available INBUF
macros are described in the Fusion, IGLOO/e and
ProASIC3/E Macro Library Guide.
2 dedicated differential I/Os using a hardwired
connection
The FPGA core
The CCC block is fully configurable, either via flash
configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous
interface is dynamically accessible from inside the
Automotive ProASIC3 device to permit parameter
changes (such as divide ratios) during device operation.
To increase the versatility and flexibility of the clock
conditioning system, the CCC configuration is
determined either by the user during the design process,
with configuration data being stored in flash memory as
part of the device programming procedure, or by writing
data into a dedicated shift register during normal device
operation. This latter mode allows the user to
dynamically reconfigure the CCC without the need for
core programming. The shift register is accessed through
a simple serial interface. Refer to the UJTAG Applications
in ProASIC3/E Devices application note and the "CCC
The CLKDLY macro can be driven directly from the FPGA
core.
The CLKDLY macro can also be driven from an I/O that is
routed through the FPGA regular routing fabric. In this
case, users must instantiate a special macro, PLLINT, to
differentiate from the hardwired I/O connection
described earlier.
The visual CLKDLY configuration in the SmartGen part of
the Libero IDE and Designer tools allows the user to
select the desired amount of delay and configures the
delay elements appropriately. SmartGen also allows the
user to select the input clock source. SmartGen will
automatically instantiate the special macro, PLLINT,
when needed.
v2.0
2-13
Automotive ProASIC3 Flash Family FPGAs
Clock Source
Clock Conditioning
Output
Input LVDS/LVPECL Macro
PLL Macro
GLA
or
CLKA
GLA
LOCK
GLB
YB
GLC
YC
PADN
POWERDOWN
Y
PADP
GLA and (GLB or YB)
or
OADIV[4:0]*
OAMUX[2:0]*
DLYGLA[4:0]*
OBDIV[4:0]*
OBMUX[2:0]*
DLYYB[4:0]*
DLYGLB[4:0]*
OCDIV[4:0]*
OCMUX[2:0]*
DLYYC[4:0]*
DLYGLC[4:0]*
FINDIV[6:0]*
FBDIV[6:0]*
FBDLY[4:0]*
FBSEL[1:0]*
INBUF* Macro
GLA and (GLC or YC)
or
PAD
Y
GLA and (GLB or YB) and
(GLC or YC)
For INBUF* driving a PLL macro
or CLKDLY macro, the I/O will
be hard-routed to the CCC; i.e., will
be placed by software to a dedicated
Global I/O.
XDLYSEL*
VCOSEL[2:0]*
CLKDLY Macro
CLK GL
GLA
or
GLB
or
DLYGL[4:0]
GLC
CLKBUF_LVDS/LVPECL Macro
PADN
CLKBUF Macro
CLKINT Macro
PAD
Y
PADP
Y
A
Y
Notes:
1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. The PLL is only supported on the west
center CCC. Refer to the "PLL Macro" section on page 2-15 for signal descriptions.
2. Refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide for more information.
3. Many standard-specific INBUF macros (for example, INBUF_LVDS) support the wide variety of single-ended and differential I/O
standards supported by the Automotive ProASIC3 family. The available INBUF macros are described in the Fusion, IGLOO/e and
ProASIC3/E Macro Library Guide.
Figure 2-14 • Automotive ProASIC3 CCC Options
2-14
v2.0
Automotive ProASIC3 Flash Family FPGAs
There are five delay elements to support phase control
on all five outputs (GLA, GLB, GLC, YB, and YC).
PLL Macro
The PLL functionality of the clock conditioning block is
supported by the PLL macro. Note that the PLL macro
reference clock uses the CLKA input of the CCC block,
which is only accessible from the global A[0:2] package
pins. Refer to Figure 2-15 on page 2-17 for more
information.
There is also a delay element in the feedback loop that
can be used to advance the clock relative to the
reference clock.
The PLL macro reference clock can be driven by an INBUF*
macro to create a composite macro, where the I/O macro
drives the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be placed
in one of the dedicated global I/O locations.
The PLL macro provides five derived clocks (three
independent) from a single reference clock. The PLL
macro also provides power-down input and lock output
signals. See Figure 2-17 on page 2-16 for more
information.
The PLL macro reference clock can be driven directly
from the FPGA core.
Inputs:
The PLL macro reference clock can also be driven from an
I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro,
PLLINT, to differentiate from the hardwired I/O
connection described earlier.
•
•
CLKA: selected clock input
POWERDOWN (active low): disables PLLs. The
default state is Powerdown On (active low).
Outputs:
During power-up, the PLL outputs will toggle around the
maximum frequency of the voltage-controlled oscillator
(VCO) gear selected. Toggle frequencies can range from
40 MHz to 250 MHz. This will continue as long as the
clock input (CLKA) is constant (HIGH or LOW). This can be
prevented by LOW assertion of the POWERDOWN signal.
•
•
•
LOCK: indicates that PLL output has locked on the
input reference signal
GLA, GLB, GLC: outputs to respective global
networks
YB, YC: allows output from the CCC to be routed
back to the FPGA core
The visual PLL configuration in SmartGen, part of the
Libero IDE and Designer tools, will derive the necessary
internal divider ratios based on the input frequency and
desired output frequencies selected by the user.
SmartGen also allows the user to select the various delays
and phase shift values necessary to adjust the phases
between the reference clock (CLKA) and the derived
clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows
the user to select the input clock source. SmartGen
automatically instantiates the special macro, PLLINT,
when needed.
As previously described, the PLL allows up to five flexible
and independently configurable clock outputs. Figure 2-20
on page 2-19 illustrates the various clock output options
and delay elements.
As illustrated, the PLL supports three distinct output
frequencies from a given input clock. Two of these (GLB
and GLC) can be routed to the B and C global network
access, respectively, and/or routed to the device core (YB
and YC).
CLKBUF
PAD
CLKINT
A
Y
Y
CLKBUF_LVDS/LVPECL
Y
PADN
PADP
Figure 2-16 • CLKBUF and CLKINT
v2.0
2-15
Automotive ProASIC3 Flash Family FPGAs
CLKDLY
CLKA
GLA
GLB
YB
POWERDOWN
CLK
GL
GLC
YC
LOCK
DLYGL[4:0]
OADIV[4:0]*
OAMUX[2:0]*
DLYGLA[4:0]*
OBDIV[4:0]*
OBMUX[2:0]*
DLYYB[4:0]*
DLYGLB[4:0]*
OCDIV[4:0]*
OCMUX[2:0]*
DLYYC[4:0]*
DLYGLC[4:0]*
FINDIV[6:0]*
FBDIV[6:0]*
FBDLY[4:0]*
FBSEL[1:0]*
Note: The CLKDLY macro uses programmable delay element type 2.
Figure 2-18 • CLKDLY
XDLYSEL*
VCOSEL[2:0]*
Note: *Visit the Actel website for future application notes
concerning the dynamic PLL.
Figure 2-17 • TCCC/PLL Macro
2-16
v2.0
Automotive ProASIC3 Flash Family FPGAs
Each shaded box represents an
INBUF or INBUF_LVDS/LVPECL
macro, as appropriate.
To Core
Sample Pin Names
GAA0/IO0NDB0V01
GAA1/IO00PDB0V01
+
Source for CCC
(CLKA or CLKB or CLKC)
Routed Clock
(from FPGA core)2
GAA2/IO13PDB7V11
+
GAA[0:2]: GA represents global in the northwest corner
of the device. A[0:2]: designates specific A clock source.
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.
Refer to the "User I/O Naming Convention" section on page 2-46 for more information.
2. Instantiate the routed clock source input as follows:
a) Connect the output of a logic element to the clock input of a PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS/BLVDS/M-LVDS/DDR) in a relevant global pin location.
3. LVDS-, BLVDS-, and M-LVDS–based clock sources are only available on A3P250 and A3P1000 devices.A3P060 and A3P125 devices
support single-ended clock sources only.
Figure 2-15 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
v2.0
2-17
Automotive ProASIC3 Flash Family FPGAs
CCC Electrical Specifications
Timing Characteristics
Table 2-3 • Automotive ProASIC3 CCC/PLL Specification
Parameter
Minimum
1.5
Typical
Maximum
350
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks1, 2
0.75
350
160
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
3 Global
Network Used
Networks Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
0.50%
1.00%
1.75%
2.50%
0.70%
1.20%
2.00%
5.60%
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
300
300
300
6.0
µs
µs
(all other dies)
µs
ms
Tracking Jitter4
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1.6
ns
ns
ns
ns
%
ns
ns
ns
1.6
(all other dies)
1.6
0.8
Output Duty Cycle
48.5
0.6
51.5
Delay Range in Block: Programmable Delay 11, 2
Delay Range in Block: Programmable Delay 21, 2
Delay Range in Block: Fixed Delay1, 2
Notes:
5.56
0.025
5.56
2.2
1. This delay is a function of voltage and temperature. See Table 3-5 on page 3-5 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking
jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
Figure 2-19 • Peak-to-Peak Jitter Definition
.
2-18
v2.0
Automotive ProASIC3 Flash Family FPGAs
CCC Physical Implementation
CCC Programming
The CCC is composed of the following (Figure 2-20):
The CCC block is fully configurable, either via static flash
configuration bits in the array, set by the user in the
programming bitstream, or through an asynchronous
dedicated shift register dynamically accessible from
inside the Automotive ProASIC3 device. The dedicated
shift register permits changes in parameters, such as PLL
divide ratios and delays, during device operation. This
latter mode allows the user to dynamically reconfigure
the PLL without the need for core programming. The
register file is accessed through a simple serial interface.
Refer to the UJTAG Applications in ProASIC3/E Devices
application note for more information.
•
•
•
PLL core
3 phase selectors
6 programmable delays and 1 fixed delay that
advances/delays phase
•
5 programmable frequency dividers that provide
frequency multiplication/division (not shown in
Figure 2-20 because they are automatically
configured based on the user's required
frequencies)
•
1 dynamic shift register that provides CCC dynamic
reconfiguration capability
CLKA
GLA
Four-Phase Output
PLL Core
Programmable
Delay Type 2
Phase
Select
Programmable
Delay Type 1
Fixed Delay
GLB
Programmable
Delay Type 2
Phase
Select
YB
Programmable
Delay Type 1
GLC
Programmable
Delay Type 2
Phase
Select
YC
Programmable
Delay Type 1
Notes:
1. Refer to the "Clock Conditioning Circuits" section on page 2-13 and Table 2-3 on page 2-18 for signal descriptions.
2. Clock divider and clock multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the
user's required frequencies.
Figure 2-20 • Automotive ProASIC3 PLL Block
v2.0
2-19
Automotive ProASIC3 Flash Family FPGAs
Nonvolatile Memory (NVM)
Overview of User Nonvolatile FlashROM
Automotive ProASIC3 devices have 1 kbit of on-chip
nonvolatile flash memory that can be read from the
FPGA core fabric. The FlashROM is arranged in 8 banks of
128 bits during programming. The 128 bits in each bank
are addressable as 16 bytes during the read-back of the
FlashROM from the FPGA core (Figure 2-21).
bank erase prior to reprogramming the bank. The
FlashROM supports synchronous read. The address is
latched on the rising edge of the clock, and the new
output data is stable after the falling edge of the same
clock cycle. Refer to Table 3-44 on page 3-96 for the
timing diagram. The FlashROM can be read on byte
boundaries. The upper three bits of the FlashROM
address from the FPGA core define the bank being
accessed. The lower four bits of the FlashROM address
from the FPGA core define which of the 16 bytes in the
bank is being accessed.
The FlashROM can only be programmed via the IEEE
1532 JTAG port. It cannot be programmed directly from
the FPGA core. When programming, each of the eight
128-bit banks can be selectively reprogrammed. The
FlashROM can only be reprogrammed on a bank
boundary. Programming involves an automatic, on-chip
Byte Number in Bank
4 LSB of ADDR (READ)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 2-21 • FlashROM Architecture
2-20
v2.0
Automotive ProASIC3 Flash Family FPGAs
SRAM and FIFO
Automotive ProASIC3 devices (A3P250 and A3P1000)
have embedded SRAM blocks along their north and
south sides; A3P060 and A3P125 devices have embedded
SRAM blocks on the north side only. To meet the needs
of high-performance designs, the memory blocks
operate strictly in synchronous mode for both read and
write operations. The read and write clocks are
completely independent, and each may operate at any
desired frequency up to 250 MHz.
diagrams of the memory modules are illustrated in
Figure 2-22 on page 2-22.
Simultaneous dual-port read/write and write/write
operations at the same address are allowed when certain
timing requirements are met.
During RAM operation, addresses are sourced by the
user logic and the FIFO controller is ignored. In FIFO
mode, the internal addresses are generated by the FIFO
controller and routed to the RAM array by internal
MUXes. Refer to Figure 2-23 on page 2-23 for more
information about the implementation of the embedded
FIFO controller.
•
4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—2 read,
2 write or 1 read, 1 write)
•
•
512×9, 256×18 (2-port RAM—1 read and 1 write)
Sync write, sync pipelined / nonpipelined read
The Automotive ProASIC3 architecture enables the read
and write sizes of RAMs to be organized independently,
allowing for bus conversion. For example, the write side
size can be set to 256×18 and the read size to 512×9.
ProASIC3 Automotive devices support single-port SRAM
capabilities or dual-port SRAM only under specific
conditions. Dual-port mode is supported if the clocks to
the two SRAM ports are the same and 180° out of phase
(i.e., the port A clock is the inverse of the port B clock).
Both the write width and read width for the RAM blocks
can be specified independently with the WW (write
width) and RW (read width) pins. The different D×W
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
The Actel Libero IDE software macro libraries support a
dual-port macro only.
Refer to the allowable RW and WW values supported for
each of the RAM macro types in Table 2-7 on page 2-25.
For use of this macro as a single-port SRAM, the inputs
and clock of one port should be tied off (grounded) to
prevent errors during design compile.
When widths of one, two, or four are selected, the ninth
bit is unused. For example, when writing nine-bit values
and reading four-bit values, only the first four bits and
the second four bits of each nine-bit value are
addressable for read operations. The ninth bit is not
accessible.
For use in dual-port mode, the same clock with an
inversion between the two clock pins of the macro
should be used in design to prevent errors during
compile.
The ProASIC3 memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag logic (FULL, EMPTY, AFULL, AEMPTY). Block
Conversely, when writing four-bit values and reading
nine-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte
order for read and write operations.
v2.0
2-21
Automotive ProASIC3 Flash Family FPGAs
RAM4K9
RAM512x18
FIFO4K18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RW2
RW1
RW0
WW2
WW1
WW0
ESTOP
FSTOP
RD17
RD16
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
DINA7
RADDR0
RD0
RD0
FULL
AFULL
EMPTY
RW1
RW0
DINA0
AEVAL11
AEVAL10
AEMPTY
WIDTHA1
WIDTHA0
PIPEA
PIPE
AEVAL0
WMODEA
BLKA
WENA
AFVAL11
AFVAL10
REN
RCLK
CLKA
AFVAL0
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
REN
RBLK
RCLK
ADDRB0
DOUTB0
WADDR0
WD17
WD16
WD17
WD16
DINB8
DINB7
WD0
DINB0
WD0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WBLK
WCLK
RPIPE
WEN
WCLK
RESET
RESET
RESET
Note: ProASIC3 Automotive devices restrict RAM4K9 to a single port or to dual ports with the same clock 180° out of phase (inverted)
between clock pins. In single-port mode, inputs to port B should be tied to ground to prevent errors during compile. For FIFO4K18,
the same clock 180° out of phase (inverted) between clock pins should be used.
Figure 2-22 • Supported Basic RAM Macros
2-22
v2.0
Automotive ProASIC3 Flash Family FPGAs
RD
RD[17:0]
WD[17:0]
RCLK
WD
RCLK
WCLK
RADD[J:0]
WADD[J:0]
WCLK
RAM
REN
WEN
FREN
FWEN
CNT 12
RBLK
REN
E
=
FULL
ESTOP
AFVAL
AFULL
AEMPTY
EMPTY
AEVAL
=
CNT 12
WBLK
WEN
SUB 12
E
FSTOP
Reset
Note: For FIFO4K18, the same clock 180° out of phase (inverted) between clock pins should be used.
Figure 2-23 • Automotive ProASIC3 RAM Block with Embedded FIFO Controller
v2.0
2-23
Automotive ProASIC3 Flash Family FPGAs
When using the SRAM in single-port mode for ProASIC3
automotive devices, WENB should be tied to ground.
Signal Descriptions for RAM4K9
ProASIC3 Automotive devices support single-port SRAM
capabilities, or dual-port SRAM only under specific
conditions. Dual-port mode is supported if the clocks to
the two SRAM ports are the same and 180° out of phase
(i.e., the port A clock is the inverse of the port B clock).
CLKA and CLKB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
The Actel Libero IDE macro libraries support a dual-port
macro only.
For ProASIC3 Automotive devices, dual-port mode is
supported if the clocks to the two SRAM ports are the
same and 180° out of phase (i.e., the port A clock is the
inverse of the port B clock).
For use of this macro as a single-port SRAM, the inputs
and clock of one port should be tied off (grounded) to
prevent errors during design compile.
For use of this macro as a single-port SRAM, the inputs
and clock of one port should be tied off (grounded) to
prevent errors during design compile.
For use in dual-port mode, the same clock with an
inversion between the two clock pins of the macro
should be used in design to prevent errors during
compile.
PIPEA and PIPEB
These signals are used to specify pipelined read on the
The following signals are used to configure the RAM4K9
memory element:
output.
A LOW on PIPEA or PIPEB indicates a
nonpipelined read, and the data appears on the
corresponding output in the same clock cycle. A HIGH
indicates a pipelined read, and data appears on the
corresponding output in the next clock cycle.
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of
four allowable aspect ratios (Table 2-4).
When using the SRAM in single-port mode for ProASIC3
Automotive devices, PIPEB should be tied to ground.
When using the SRAM in single-port mode for ProASIC3
automotive devices, WIDTHB should be tied to ground.
WMODEA and WMODEB
Table 2-4 • Allowable Aspect Ratio Settings for
These signals are used to configure the behavior of the
output when the RAM is in write mode. A LOW on these
signals makes the output retain data from the previous
read. A HIGH indicates pass-through behavior, wherein
the data being written will appear immediately on the
output. This signal is overridden when the RAM is being
read.
WIDTHA[1:0]
WIDTHA[1:0]
WIDTHB[1:0]
D×W
4k×1
2k×2
1k×4
512×9
00
01
10
11
00
01
10
11
When using the SRAM in single-port mode for ProASIC3
Automotive devices, WMODEB should be tied to ground.
Note: The aspect ratio settings are constant and cannot be
RESET
changed on the fly.
This active low signal resets the control logic, forces the
output hold state registers to zero, disables reads and
writes from the SRAM block, and clears the data hold
registers when asserted. It does not reset the contents of
the memory array.
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, that port’s outputs hold the previous value.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-117 on page 3-88 for the
specifications.
When using the SRAM in single-port mode for ProASIC3
automotive devices, BLKB should be tied to ground.
WENA and WENB
These signals switch the RAM between read and write
modes for the respective ports. A LOW on these signals
indicates a write operation, and a HIGH indicates a read.
2-24
v2.0
Automotive ProASIC3 Flash Family FPGAs
ADDRA and ADDRB
WW and RW
These are used as read or write addresses, and they are 12
bits wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded (Table 2-5).
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-7).
Table 2-7 • Aspect Ratio Settings for WW[1:0]
When using the SRAM in single-port mode for ProASIC3
Automotive devices, ADDRB should be tied to ground.
WW[1:0]
01
RW[1:0]
01
D×W
512×9
Table 2-5 • Address Pins Unused/Used for Various
Supported Bus Widths
10
10
256×18
Reserved
ADDRx
00, 11
00, 11
D×W
4k×1
2k×2
1k×4
512×9
Unused
None
Used
[11:0]
[10:0]
[9:0]
WD and RD
These are the input and output data signals, and they
are 18 bits wide. When a 512×9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, RD[17:9] are undefined.
[11]
[11:10]
[11:9]
[8:0]
WADDR and RADDR
Note: The "x" in ADDRx implies A or B.
These are read and write addresses, and they are nine
bits wide. When the 256×18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
DINA and DINB
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded (Table 2-6).
WCLK and RCLK
These signals are the write and read clocks, respectively.
They can be clocked on the rising or falling edge of
WCLK and RCLK.
When using the SRAM in single-port mode for ProASIC3
Automotive devices, DINB should be tied to ground.
WEN and REN
DOUTA and DOUTB
These signals are the write and read enables,
respectively. They are both active low by default. These
signals can be configured as active high.
These are the nine-bit output data signals. Not all nine
bits are valid in all configurations. As with DINA and
DINB, high-order bits may not be used (Table 2-6). The
output data on unused pins is undefined.
RESET
This active low signal resets the control logic, forces the
output hold state registers to zero, disables reads and
writes from the SRAM block, and clears the data hold
registers when asserted. It does not reset the contents of
the memory array.
Table 2-6 • Unused/Used Input and Output Data Pins for
Various Supported Bus Widths
DINx/DOUTx
D×W
4k×1
2k×2
1k×4
512×9
Unused
[8:1]
Used
[0]
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-117 on page 3-88 for the
specifications.
[8:2]
[1:0]
[3:0]
[8:0]
[8:4]
None
Note: The "x" in DINx or DOUTx implies A or B.
PIPE
This signal is used to specify pipelined read on the
output. A LOW on PIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
Signal Descriptions for RAM512X18
RAM512X18 has slightly different behavior from
RAM4K9, as it has dedicated read and write ports.
v2.0
2-25
Automotive ProASIC3 Flash Family FPGAs
register for a target block can be selected and loaded
with the proper bit configuration to enable serial
loading. The 4,608 bits of data can be loaded in a single
operation.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge-triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, the same clock, with an
inversion between the two clock pins of the macro,
should be used in design to prevent errors during
compile.
Signal Descriptions for FIFO4K18
The following signals are used to configure the FIFO4K18
memory element:
WW and RW
Automotive ProASIC3 devices support inversion (bubble
pushing) throughout the FPGA architecture, including
the clock input to the SRAM modules. Inversions added
to the SRAM clock pin on the design schematic or in the
HDL code will be automatically accounted for during
design compile without incurring additional delay in the
clock path.
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios (Table 2-8).
Table 2-8 • Aspect Ratio Settings for WW[2:0]
WW[2:0]
000
RW[2:0]
000
D×W
4k×1
001
001
2k×2
The two-port SRAM can be clocked on the rising or
falling edge of WCLK and RCLK.
010
010
1k×4
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the
Automotive ProASIC3 development tools, without
performance penalty.
011
011
512×9
256×18
Reserved
100
100
101, 110, 111
101, 110, 111
Modes of Operation
There are two read modes and one write mode:
WBLK and RBLK
These signals are active low and will enable the
respective ports when LOW. When the RBLK signal is
HIGH, that port’s outputs hold the previous value.
•
Read Nonpipelined (synchronous—1 clock edge):
In the standard read mode, new data is driven
onto the RD bus in the same clock cycle following
RA and REN valid. The read address is registered
on the read port clock active edge, and data
appears at RD after the RAM access time. Setting
PIPE to OFF enables this mode.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
WCLK and RCLK
•
Read Pipelined (synchronous—2 clock edges): The
pipelined mode incurs an additional clock delay
from address to data but enables operation at a
much higher frequency. The read address is
registered on the read port active clock edge, and
the read data is registered and appears at RD after
the second read clock edge. Setting PIPE to ON
enables this mode.
These are the clock signals for the synchronous read and
write operations. For FIFO4K18, the same clock 180° out
of phase (inverted) between clock pins should be used.
RPIPE
This signal is used to specify pipelined read on the
output. A LOW on RPIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
•
Write (synchronous—1 clock edge): On the write
clock active edge, the write data is written into
the SRAM at the write address when WEN is HIGH.
The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "DDR
Module Specifications" section on page 3-64.
RESET
This active low signal resets the control logic and forces
the output hold state registers to zero when asserted. It
does not reset the contents of the memory array
(Table 2-9 on page 2-27).
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous RESET
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-120 on page 3-94 for the
specifications.
RAM Initialization
Each SRAM block can be individually initialized on power-
up by means of the JTAG port using the UJTAG mechanism
(refer to the "JTAG 1532" section on page 2-51 and the
ProASIC3/E SRAM/FIFO Blocks application note). The shift
2-26
v2.0
Automotive ProASIC3 Flash Family FPGAs
WD
AFULL, AEMPTY
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded (Table 2-9).
These are programmable flags and will be asserted on
the threshold specified by AFVAL and AEVAL,
respectively.
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
AEMPTY output will go HIGH. Likewise, when the
number of words stored in the FIFO reaches the amount
specified by AFVAL while writing, the AFULL output will
go HIGH.
RD
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
(Table 2-9).
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values. They are
12-bit signals. For more information on these signals,
refer to the "FIFO Flag Usage Considerations" section.
Table 2-9 • Input Data Signal Usage for Different Aspect
Ratios
D×W
4k×1
WD/RD Unused
WD[17:1], RD[17:1]
WD[17:2], RD[17:2]
WD[17:4], RD[17:4]
WD[17:9], RD[17:9]
–
ESTOP and FSTOP Usage
The ESTOP pin is used to stop the read counter from
counting any further once the FIFO is empty (i.e., the
EMPTY flag goes HIGH). Likewise, the FSTOP pin is used
to stop the write counter from counting any further once
the FIFO is full (i.e., the FULL flag goes HIGH).
2k×2
1k×4
512×9
256×18
The FIFO counters in the ProASIC3 device start the count
at zero, reach the maximum depth for the configuration
(e.g., 511 for a 512×9 configuration), and then restart at
zero. An example application for ESTOP, where the read
counter keeps counting, would be writing to the FIFO
once and reading the same content over and over
without doing another write.
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the EMPTY flag
goes HIGH). A HIGH on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the FULL flag goes
HIGH). A HIGH on this signal inhibits the counting.
FIFO Flag Usage Considerations
The AEVAL and AFVAL pins are used to specify the 12-bit
AEMPTY and AFULL threshold values. The FIFO contains
separate 12-bit write address (WADDR) and read address
(RADDR) counters. WADDR is incremented every time a
write operation is performed, and RADDR is incremented
every time a read operation is performed. Whenever the
difference between WADDR and RADDR is greater than
or equal to AFVAL, the AFULL output is asserted.
Likewise, whenever the difference between WADDR and
RADDR is less than or equal to AEVAL, the AEMPTY
output is asserted. To handle different read and write
aspect ratios, AFVAL and AEVAL are expressed in terms
of total data bits instead of total data words. When users
specify AFVAL and AEVAL in terms of read or write
words, the SmartGen tool translates them into bit
addresses and configures these signals automatically.
SmartGen configures the AFULL flag to assert when the
write address exceeds the read address by at least a
predefined value. In a 2k×8 FIFO, for example, a value of
1,500 for AFVAL means that the AFULL flag will be
asserted after a write when the difference between the
write address and the read address reaches 1,500 (there
have been at least 1,500 more writes than reads). It will
stay asserted until the difference between the write and
read addresses drops below 1,500.
For more information on these signals, refer to "ESTOP
and FSTOP Usage" section.
FULL, EMPTY
When the FIFO is full and no more data can be written,
the FULL flag asserts HIGH. The FULL flag is synchronous
to WCLK to inhibit writing immediately upon detection
of a full condition and to prevent overflows. Since the
write address is compared to a resynchronized (and thus
time-delayed) version of the read address, the FULL flag
will remain asserted until two WCLK active edges after a
read operation eliminates the full condition.
When the FIFO is empty and no more data can be read,
the EMPTY flag asserts HIGH. The EMPTY flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time-delayed) version of the
write address, the EMPTY flag will remain asserted until
two RCLK active edges after a write operation removes
the empty condition.
For more information on these signals, refer to the "FIFO
Flag Usage Considerations" section.
v2.0
2-27
Automotive ProASIC3 Flash Family FPGAs
The AEMPTY flag is asserted when the difference
between the write address and the read address is less
than a predefined value. In the example above, a value
of 200 for AEVAL means that the AEMPTY flag will be
asserted when a read causes the difference between the
write address and the read address to drop to 200. It will
stay asserted until that difference rises above 200. Note
that the FIFO can be configured with different read and
write widths; in this case, the AFVAL setting is based on
the number of write data entries, and the AEVAL setting
is based on the number of read data entries. For aspect
ratios of 512×9 and 256×18, only 4,096 bits can be
addressed by the 12 bits of AFVAL and AEVAL. The
number of words must be multiplied by 8 and 16 instead
of 9 and 18. The SmartGen tool automatically uses the
proper values. To avoid halfwords being written or read,
which could happen if different read and write aspect
ratios were specified, the FIFO will assert FULL or EMPTY
as soon as at least one word cannot be written or read.
For example, if a two-bit word is written and a four-bit
word is being read, the FIFO will remain in the empty
state when the first word is written. This occurs even if
the FIFO is not completely empty, because in this case, a
complete word cannot be read. The same is applicable in
the full state. If a four-bit word is written and a two-bit
word is read, the FIFO is full and one word is read. The
FULL flag will remain asserted because a complete word
cannot be written at this point.
Advanced I/Os
Introduction
Automotive ProASIC3 devices feature a flexible I/O
structure, supporting a range of mixed voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V) through
a bank-selectable
voltage. Table 2-10 on page 2-29 shows the voltages and
compatible I/O standards. I/Os provide programmable
slew rates, drive strengths, and weak pull-up and pull-
down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V–tolerant.
See the "5 V Input Tolerance" section on page 2-36 for
possible implementations of 5 V tolerance.
All I/Os are in a known state during power-up, and any
power-up sequence is allowed without current impact.
Refer to the "I/O Power-Up and Supply Voltage
Thresholds for Power-On Reset (Commercial and
Industrial)" section on page 3-4 for more information.
During power-up, before reaching activation levels, the
I/O input and output buffers are disabled while the weak
pull-up is enabled. Activation levels are described in
Table 3-2 on page 3-2.
I/O Tile
The Automotive ProASIC3 I/O tile provides a flexible,
programmable structure for implementing
a large
number of I/O standards. In addition, the registers
available in the I/O tile in selected I/O banks can be used
to support high-performance register inputs and
outputs, with register enable if desired (Figure 2-24 on
page 2-31). The registers can also be used to support the
JESD-79C Double Data Rate (DDR) standard within the
I/O structure (see the "Double Data Rate (DDR) Support"
section on page 2-32 for more information).
As depicted in Figure 2-24 on page 2-31, all I/O registers
share one CLR port. The output register and output
enable register share one CLK port. Refer to the "I/O
Registers" section on page 2-31 for more information.
2-28
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 2-11 shows the required voltage compatibility
values for each of these voltages.
I/O Banks and I/O Standards Compatibility
I/Os are grouped into I/O voltage banks. There are four I/O
banks on the A3P250 and A3P1000. The A3P060 and
A3P125 have two I/O banks. Each I/O voltage bank has
dedicated I/O supply and ground voltages (VMV/GNDQ for
input buffers and VCCI/GND for output buffers). Because
of these dedicated supplies, only I/Os with compatible
standards can be assigned to the same I/O voltage bank.
For more information about I/O and global assignments
to I/O banks in a device, refer to the specific pin table for
the device in the "Package Pin Assignments" section on
page 4-1 and the "User I/O Naming Convention" section
on page 2-46.
Table 2-10 • Automotive ProASIC3 Supported I/O Standards
A3P060
A3P125
A3P250
A3P1000
Single-Ended
LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V
✓
✓
✓
✓
✓
✓
✓
✓
3.3 V PCI/PCI-X
Differential
LVPECL, LVDS, BLVDS, M-LVDS
–
–
✓
✓
Table 2-11 • VCCI Voltages and Compatible Standards
VCCI and VMV (typical)
Compatible Standards
3.3 V
2.5 V
1.8 V
1.5 V
LVTTL/LVCMOS 3.3, PCI 3.3, PCI-X 3.3 LVPECL
LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS, BLVDS, M-LVDS
LVCMOS 1.8
LVCMOS 1.5
Advanced I/O banks offer single-ended and differential
capabilities. These banks are available on the east and
west sides of A3P250 and A3P1000 devices.
I/O Banks
Automotive ProASIC3 I/Os are divided into multiple
technology banks. The ProASIC3 family has two to four
banks, and the number of banks is device-dependent.
Standard Plus I/O banks offer LVTTL/LVCMOS and PCI
single-ended I/O standards. These banks are available on
the north and south sides of A3P250 and A3P1000.
A3P060 and A3P125 support two I/O banks, whereas
A3P250 and A3P1000 support four I/O banks. The bank
types have different characteristics, such as drive strength,
the I/O standards supported, and timing and power
differences.
Table 2-12 shows the I/O bank types, devices and bank
locations supported, drive strength, slew rate control,
and supported standards.
There are two types of banks in the Automotive ProASIC3
family: Advanced I/O banks and Standard Plus I/O banks.
Table 2-12 • Automotive ProASIC3 Bank Type Definitions and Differences
I/O Standards Supported
LVPECL, LVDS,
Device and Bank
Location
Slew Rate
Control
LVTTL/
LVCMOS
I/O Bank Type
Drive Strength
PCI/PCI-X
BLVDS, M-LVDS
Standard Plus
A3P060 and A3P125 (all
banks)
Refer to Table 2-20
on page 2-45
Yes
✓
✓
✓
Not Supported
North and south banks of Refer to Table 2-20
A3P250 and A3P1000
devices
Yes
✓
✓
Not Supported
on page 2-45
Advanced
East and west banks of
A3P250 and A3P1000
devices
Refer to Table 2-21
on page 2-45
Yes
✓
✓
v2.0
2-29
Automotive ProASIC3 Flash Family FPGAs
Features Supported on Every I/O
Table 2-13 lists all features supported by transmitter/receiver for single-ended and differential I/Os.
Table 2-13 • ProASIC3 I/O Features
Feature
Description
Weak pull-up and pull-down
Single-Ended Transmitter Features
•
•
•
2 slew rates
Skew between output buffer enable/disable time: 2 ns delay
on rising edge and 0 ns delay on falling edge (see "Selectable
Skew between Output Buffer Enable and Disable Times" on
page 2-41 for more information)
•
•
3 drive strengths
5 V–tolerant receiver ("5 V Output Tolerance" section on
page 2-40)
•
•
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs
("5 V Output Tolerance" section on page 2-40)
High performance (Table 2-14)
Single-Ended Receiver Features
•
•
•
High performance (Table 2-14)
Electrostatic discharge (ESD) protection
Separate ground plane for GNDQ pin and power plane for VMV
pin are used for input buffer to reduce output-induced noise.
Differential Receiver Features (A3P250 and A3P1000)
CMOS-Style LVDS, BLVDS, M-LVDS, or LVPECL Transmitter
•
•
•
High performance (Table 2-14)
ESD protection
Separate ground plane for GNDQ pin and power plane for VMV
pin are used for input buffer to reduce output-induced noise.
•
Two I/Os and external resistors are used to provide a CMOS-
style LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL transmitter
solution.
•
•
Weak pull-up and pull-down
High slew rate
Table 2-14 • Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in Automotive ProASIC3 Devices
(maximum drive strength and high slew selected)
Specification
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI
Performance Up To
200 MHz
250 MHz
200 MHz
130 MHz
200 MHz
PCI-X
200 MHz
LVDS
350 MHz
LVPECL
350 MHz
2-30
v2.0
Automotive ProASIC3 Flash Family FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-24 for a simplified
representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-24) between registers to
implement single-ended or differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does
not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain
rules. For more information, refer to the ProASIC3/E I/O Usage Guide.
I/O / Q0
1
2
Input
Input
Register
Register
To FPGA Core
Y
Pull-Up/-Down
Resistor Control
CLR/PRE
I/O / Q1
3
Input
Register
PAD
ICE
CLR/PRE
I/O / ICLK
Signal Drive Strength
and Slew Rate Control
E = Enable Pin
A
I/O / D0
4
Output
Register
OCE
ICE
From FPGA Core
CLR/PRE
I/O / D1 / ICE
5
Output
Register
I/O / OCLK
I/O / OE
CLR/PRE
6
Output
Enable
Register
OCE
I/O / CLR or I/O / PRE / OCE
CLR/PRE
Note: Automotive ProASIC3 I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on
page 2-32 for more information).
Figure 2-24 • I/O Block Logical Representation
v2.0
2-31
Automotive ProASIC3 Flash Family FPGAs
Each I/O tile on Automotive ProASIC3 devices supports
DDR inputs.
Double Data Rate (DDR) Support
Automotive ProASIC3 devices support 350 MHz DDR
inputs and outputs. In DDR mode, new data is present on
every transition of the clock signal. Clock and data lines
have identical bandwidths and signal integrity
requirements, making them very efficient for
implementing very high-speed systems.
Output Support for DDR
The basic DDR output structure is shown in Figure 2-26 on
page 2-33. New data is presented to the output every half
clock cycle. Note: DDR macros and I/O registers do not
require additional routing. The combiner automatically
recognizes the DDR macro and pushes its registers to the
I/O register area at the edge of the chip. The routing
delay from the I/O registers to the I/O buffers is already
taken into account in the DDR macro.
High-speed DDR interfaces can be implemented using
LVDS. The DDR feature is primarily implemented in the
FPGA core periphery and is not limited to any I/O
standard.
Refer to the Actel application note Using DDR for
ProASIC3/E Devices for more information.
Input Support for DDR
The basic structure to support a DDR input is shown in
Figure 2-25. Three input registers are used to capture
incoming data, which is presented to the core on each
rising edge of the I/O register clock.
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
XX
X
X
FF1
E
B
Out_QR
(to core)
CLK
CLR
X
CLKBUF
INBUF
FF2
C
X
DDR_IN
Figure 2-25 • DDR Input Register Support in Automotive ProASIC3 Devices
2-32
v2.0
Automotive ProASIC3 Flash Family FPGAs
Output DDR
A
Data_F
XX
(from core)
FF1
Out
B
C
0
1
CLK
X
X
X
E
CLKBUF
X
OUTBUF
D
Data_R
(from core)
FF2
B
C
X
X
CLR
INBUF
DDR_OUT
Figure 2-26 • DDR Output Support in Automotive ProASIC3 Devices
v2.0
2-33
Automotive ProASIC3 Flash Family FPGAs
Hot-Swap Support
Hot-swapping (also called hot-plugging) is the operation of hot insertion or hot removal of a card in a powered-up
system. The levels of hot-swap support and examples of related applications are described in Table 2-15.
Table 2-15 • Levels of Hot-Swap Support
Device
Example of
Hot-
Swapping
Level
Power
Applied
Card
Circuitry
Application with
Cards Containing
Ground Connected
Compliance of
ProASIC3 Devices
Description to Device Bus State Connection to Bus Pins ProASIC3 Devices
1
2
Cold-swap
No
–
–
–
System and card with
Actel FPGA chip are
powered down and the from the rest of the
card is plugged into the system.
system. Then the power
supplies are turned on for
the system but not for the
FPGA on the card.
Yes, if the bus switch is
used to isolate FPGA I/Os
Hot-swapwhile
reset
Yes
Held in reset Must be made
–
In the PCI hot-plug
specification, reset control
circuitry isolates the card
busses until the card
supplies are at their
nominal operating levels
and stable.
Yes
state
and
maintained
for 1 ms
before,
during, and
after
insertion/
removal
3
Hot-swapwhile
bus idle
Yes
Held idle (no Same as Level Must remain Board bus shared with
Option 1 – 2 levels of
ongoing I/O
processes
during
2
glitch-free
during
power-up or activity on the bus. It is
card bus is "frozen," and staging (first: GND,
there is no toggling
second: all other pins)
together with bus switch
insertion/
removal)
power-down critical that the logic states on the I/Os
set on the bus signal are
Option 2 – 3 levels of
not disturbed during card
insertion/removal.
staging (first: GND,
second: supplies, third:
all other pins)
4
Hot-swap on
an active bus
Yes
Bus may have Same as Level Same as
There is activity on the
system bus, and it is
Option 1 – 2 levels of
staging (first: GND,
active I/O
2
Level 3
processes
critical that the logic states second: all other pins)
set on the bus signal not together with bus switch
be disturbed during card on the I/Os
ongoing, but
device being
inserted or
removed
insertion/removal.
Option 2 – 3 levels of
staging (first: GND,
second: supplies, third:
all other pins)
must be idle.
For boards and cards with three levels of staging, card
power supplies must have time to reach their final values
before the I/Os are connected. Pay attention to the sizing
of power supply decoupling capacitors on the card to
ensure that the power supplies are not overloaded with
capacitance.
Cards with three levels of staging should have the
following sequence:
•
•
•
Grounds
Powers
I/Os and other pins
2-34
v2.0
Automotive ProASIC3 Flash Family FPGAs
Cold-Sparing Support
Electrostatic Discharge (ESD) Protection
Automotive ProASIC3 devices are tested per JEDEC
Standard JESD22-A114-B.
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
Automotive ProASIC3 devices contain clamp diodes at
every I/O, global, and power pad. Clamp diodes protect
all device pads against damage from ESD as well as from
excessive voltage transients.
For Automotive ProASIC3 devices, since the I/O clamp
diode is always active, cold-sparing can be accomplished
either by employing a bus switch to isolate the device I/Os
from the rest of the system or by driving each Automotive
ProASIC3 I/O pin to 0 V.
Automotive ProASIC3 devices are tested to the following
models: the Human Body Model (HBM) with a tolerance
of 2,000 V, the Machine Model (MM) with a tolerance of
250 V, and the Charged Device Model (CDM) with a
tolerance of 200 V.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitance
is in parallel with the resistor). The RC time constant
should ensure full discharge of supplies before cold-
sparing functionality is required. The resistor is necessary
to ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND and its N side connected to the
pad. During operation, these diodes are normally
biased in the off state, except when transient voltage is
significantly above VCCI or below GND levels.
In Automotive ProASIC3 devices, the clamp diode is
always on and cannot be switched off.
Refer to Table 2-16 for more information about the I/O
standards and the clamp diode.
Table 2-16 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in Automotive ProASIC3 Devices
Output
Buffer
I/O Assignment
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V / 5.0 V 5
LVCMOS 1.8 V
Clamp Diode1
Hot Insertion
5 V Input Tolerance2 Input Buffer
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes2
Yes2
Yes4
No
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
LVCMOS 1.5 V
No
Differential, LVDS/
No
BLVDS/M-LVDS/ LVPECL
Notes:
1. The clamp diode is always active for ProASIC3 devices.
2. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.
3. Refer to Table 2-15 on page 2-34 for device-compliant information.
4. Can be implemented with an external resistor and an internal clamp diode.
5. The LVCMOS 2.5 V / 5.0 V I/O standard is supported by all Automotive ProASIC3 devices. In the SmartGen Core Reference Guide,
select the LVCMOS5 macro for LVCMOS 2.5 V / 5.0 V I/O standard support for all Automotive ProASIC3 devices.
v2.0
2-35
Automotive ProASIC3 Flash Family FPGAs
Example 1 (high speed, high current):
Rtx_out_high = Rtx_out_low = 10 Ω
5 V Input Tolerance
I/Os can support 5 V input tolerance when LVTTL 3.3 V,
LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS 2.5 V / 5.0 V
configurations are used (see Table 2-16 on page 2-35 for
more details). There are four recommended solutions for
achieving 5 V receiver tolerance (see Figure 2-27 to
Figure 2-30 on page 2-39 for details of board and macro
setups). All the solutions meet a common requirement of
limiting the voltage at the input to 3.6 V or less. In fact,
the I/O absolute maximum voltage rating is 3.6 V, and
any voltage above 3.6 V may cause long-term gate oxide
failures.
R1 = 36 Ω ( 5%), P(r1)min = 0.069 Ω
R2 = 82 Ω ( 5%), P(r2)min = 0.158 Ω
Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA
t
RISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up
to 25% safety margin)
tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to
25% safety margin)
Example 2 (low–medium speed, medium current):
Rtx_out_high = Rtx_out_low = 10 Ω
Solution 1
The board-level design must ensure that the reflected
waveform at the pad does not exceed the limits provided
in Table 3-2 on page 3-2. This is a requirement to ensure
long-term reliability.
R1 = 220 Ω ( 5%), P(r1)min = 0.018 Ω
R2 = 390 Ω ( 5%), P(r2)min = 0.032 Ω
Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA
This scheme will also work for
a 3.3 V PCI/PCI-X
configuration, but the internal diode should not be used for
clamping, and the voltage must be limited by the two
external resistors as explained below. Relying on the
diode clamping would create an excessive pad DC
voltage of 3.3 V + 0.7 V = 4 V.
t
RISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to
25% safety margin)
tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to
25% safety margin)
Other values of resistors are also allowed as long as the
resistors are sized appropriately to limit the voltage at
the receiving end to 2.5 V < Vin (rx) < 3.6 V when the
transmitter sends a logic 1. This range of Vin_dc (rx) must
be assured for any combination of transmitter supply
(5 V 0.5 V), transmitter output resistance, and board
resistor tolerances.
Here are some examples of possible resistor values
(based on a simplified simulation model with no line
effects and 10 Ω transmitter output resistance, where
Rtx_out_high = (VCCI – VOH) / IOH, Rtx_out_low = VOL / IOL).
Temporary overshoots are allowed according to Table 3-3
on page 3-3.
Solution 1
ProASIC3 I/O Input
3.3 V
5.5 V
Rext1
Rext2
Requires two board resistors,
LVCMOS 3.3 V I/Os
Figure 2-27 • Automotive ProASIC3 Solution 1
2-36
v2.0
Automotive ProASIC3 Flash Family FPGAs
Solution 2
The board-level design must ensure that the reflected waveform at the pad does not exceed voltage
overshoot/undershoot limits provided in Table 3-3 on page 3-3. This is a requirement to ensure long-term reliability.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the external resistors and Zener, as shown in Figure 2-28. Relying on the diode
clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
ProASIC3 I/O Input
3.3 V
5.5 V
Rext1
Zener
3.3 V
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os
Figure 2-28 • Automotive ProASIC3 Solution 2
v2.0
2-37
Automotive ProASIC3 Flash Family FPGAs
Solution 3
The board-level design must ensure that the reflected waveform at the pad does not exceed voltage
overshoot/undershoot limits provided in Table 3-3 on page 3-3. This is a requirement to ensure long-term reliability.
This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the bus switch, as shown in Figure 2-29. Relying on the diode clamping would
create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
ProASIC3 I/O Input
3.3 V
Bus
Switch
IDTQS32X23
5.5 V
5.5 V
Requires a bus switch on the board,
LVTTL/LVCMOS 3.3 V I/Os.
Figure 2-29 • Automotive ProASIC3 Solution 3
2-38
v2.0
Automotive ProASIC3 Flash Family FPGAs
Solution 4
Solution 4
ProASIC3 I/O Input
2.5 V
2.5 V On-Chip
5.5 V
Clamp
Diode
Rext
Requires one board resistor.
Available for all I/O standards
excluding 3.3 V I/O standards.
Figure 2-30 • Automotive ProASIC3 Solution 4
Table 2-17 • Comparison Table for 5 V–Compliant Receiver Scheme
Scheme
Board Components
Two resistors
Speed
Current Limitations
1
2
3
4
Low to High1 Limited by transmitter's drive strength
Resistor and Zener 3.3 V
Bus switch
Medium
High
Limited by transmitter's drive strength
N/A
Minimum resistor value2, 3, 4, 5
Medium
Maximum diode current at 100% duty cycle, signal constantly at '1'
•
•
•
R = 47 Ω at TJ = 70°C
R = 150 Ω at TJ = 85°C
R = 420 Ω at TJ = 100°C
•
•
•
52.7 mA at TJ = 70°C / 10-year lifetime
16.5 mA at TJ = 85°C / 10-year lifetime
5.9 mA at TJ = 100°C / 10-year lifetime
For duty cycles other than 100%, the currents can be increased by
a factor of 1 / (duty cycle).
Example: 20% duty cycle at 70°C
Maximum current = (1 / 0.2) × 52.7 mA = 5 × 52.7 mA = 263.5 mA
Notes:
1. Speed and current consumption increase as the board resistance values decrease.
2. Resistor values ensure I/O diode long-term reliability.
3. At 70°C, customers could still use 420 Ω on every I/O.
4. At 85°C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150 Ω) and the current is higher. Also, the
designer can still use 420 Ω and use the solution on every I/O.
5. At 100°C, the 5 V solution on every I/O is permitted, since 420 Ω are used to limit the current to 5.9 mA.
v2.0
2-39
Automotive ProASIC3 Flash Family FPGAs
5 V Output Tolerance
Automotive ProASIC3 I/Os must be set to 3.3 V LVTTL or
3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It
is also critical that there be NO external I/O pull-up
resistor to 5 V, since this resistor would pull the I/O pad
voltage beyond the 3.6 V absolute maximum value and
consequently cause damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode,
Automotive ProASIC3 I/Os can directly drive signals into
5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in
both 3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the
VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL
receivers. Therefore, level
1 and level 0 will be
recognized correctly by 5 V TTL receivers.
Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout
SSOs can cause signal integrity problems on adjacent
signals that are not part of the SSO bus. Both inductive
and capacitive coupling parasitics of bond wires inside
packages and of traces on PCBs will transfer noise from
SSO busses onto signals adjacent to those busses.
Additionally, SSOs can produce ground bounce noise and
VCCI dip noise. These two noise types are caused by
rapidly changing currents through GND and VCCI
package pin inductances during switching activities
(EQ 2-1 and EQ 2-2).
should be done both on the board and inside the
package unless otherwise described.
In-package shielding can be achieved in several ways; the
required shielding will vary depending on whether pins
next to the SSO bus are LVTTL/LVCMOS inputs,
LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL
inputs and outputs. Board traces in the vicinity of the
SSO bus have to be adequately shielded from mutual
coupling and inductive noise that can be generated by
the SSO bus. Also, noise generated by the SSO bus needs
to be reduced inside the package.
Ground bounce noise voltage = L(GND) × di/dt
PCBs perform an important function in feeding stable
supply voltages to the IC and, at the same time,
maintaining signal integrity between devices.
EQ 2-1
VCCI dip noise voltage = L(VCCI) × di/dt
EQ 2-2
Key issues that need to considered are as follows:
Any group of four or more input pins switching on the
same clock edge is considered an SSO bus. The shielding
•
Power and ground plane design and decoupling
network design
•
Transmission line reflections and terminations
2-40
v2.0
Automotive ProASIC3 Flash Family FPGAs
Selectable Skew between Output Buffer Enable and Disable Times
The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion
(disable) time.
ENABLE (IN)
Output Enable
(from FPGA core)
ENABLE (OUT)
MUX
Skew Circuit
I/O Output
Buffers
Skew Select
Figure 2-31 • Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
Figure 2-32 • Timing Diagram (option 1: bypasses skew circuit)
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns
Figure 2-33 • Timing Diagram (option 2: enables skew circuit)
v2.0
2-41
Automotive ProASIC3 Flash Family FPGAs
At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data
lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention
and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. Figure 2-34
presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-35 shows
how bus contention is created, and Figure 2-36 on page 2-43 shows how it can be avoided with the skew circuit.
Transmitter
ENABLE/
DISABLE
Transmitter 1: ProASIC3 I/O
Transmitter 2: Generic I/O
Routing
Skew or
Routing
EN (r1)
EN (b2)
ENABLE(t2)
Bypass
Skew
EN (b1)
Delay (t1)
Delay (t2)
ENABLE (t1)
Bidirectional Data Bus
Figure 2-34 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using Automotive
ProASIC3 Devices
EN (b1)
EN (b2)
ENABLE (r1)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Bus
Contention
Figure 2-35 • Timing Diagram (bypasses skew circuit)
2-42
v2.0
Automotive ProASIC3 Flash Family FPGAs
EN (b1)
EN (b2)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Result: No Bus Contention
Figure 2-36 • Timing Diagram (with skew circuit selected)
v2.0
2-43
Automotive ProASIC3 Flash Family FPGAs
I/O attributes are applicable for all I/O standards. Table 2-
18 lists the valid I/O attributes that can be manipulated
by the user for each I/O standard.
I/O Software Support
In the Automotive ProASIC3 development software,
default settings have been defined for the various I/O
standards supported. Changes can be made to the
default settings via the use of attributes; however, not all
Single-ended I/O standards in Automotive ProASIC3
devices support up to five different drive strengths.
Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications
SLEW
(output
only)
OUT_DRIVE
(output
only)
SKEW
(all macros
with OE)
OUT_LOAD
(output
only)
I/O Standard
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
RES_PULL
COMBINE_REGISTER
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PCI-X (3.3 V)
✓
LVDS, BLVDS, M-LVDS
LVPECL
Table 2-19 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O
standard. See Table 2-20 and Table 2-21 on page 2-45 for SLEW and OUT_DRIVE settings.
Table 2-19 • Automotive ProASIC3 I/O Default Attributes
SKEW
(tribuf and
(output only) bibuf only) RES_PULL
OUT_LOAD
(output
only)
SLEW
OUT_DRIVE
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
(output only)
COMBINE_REGISTER
See Table 2-20
on page 2-45.
See Table 2-20
on page 2-45.
Off
Off
Off
Off
Off
Off
Off
Off
Off
None
None
None
None
None
None
None
None
None
35 pF
35 pF
35 pF
35 pF
35 pF
10 pF
10 pF
0 pF
–
–
–
–
–
–
–
–
–
PCI-X (3.3 V)
LVDS, BLVDS, M-LVDS
LVPECL
0 pF
Weak Pull-Up and Weak Pull-Down Resistors
Automotive ProASIC3 devices support optional weak pull-up and pull-down resistors on each I/O pin. When the I/O is
pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is connected to GND.
Refer to Table 3-20 on page 3-20 through Table 3-23 on page 3-21 for more information.
2-44
v2.0
Automotive ProASIC3 Flash Family FPGAs
The output slew rate and multiple drive strength
controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS
2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and
LVCMOS 1.5 V. All other I/O standards have a high output
slew rate by default.
Slew Rate Control and Drive Strength
Automotive ProASIC3 devices support output slew rate
control: high and low. Actel recommends the high slew
rate option to minimize the propagation delay. This
high-speed option may introduce noise into the system if
appropriate signal integrity measures are not adopted.
Selecting a low slew rate reduces this kind of noise but
adds some delays in the system. Low slew rate is
recommended when bus transients are expected. Drive
strength should also be selected according to the design
requirements and noise immunity of the system.
For Automotive ProASIC3 devices, refer to Table 2-20 and
Table 2-21 for more information about the slew rate and
drive strength specification.
Table 2-20 • Automotive ProASIC3 Output Drive for Standard Plus I/O Bank Type
I/O Standards
LVTTL
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Slew
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
–
✓
✓
–
✓
✓
✓
–
✓
✓
–
High
High
High
High
High
Low
Low
Low
Low
Low
LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
Notes:
✓
✓
✓
–
–
–
–
1. There will be differences in timing between the Standard Plus I/O banks and the Advanced I/O banks (Table 2-21). Refer to the I/O
timing tables beginning on page 3-27 and Table 2-10 on page 2-29 for the standards supported by each device.
2. Refer to Table 2-12 on page 2-29 for I/O bank type definition.
Table 2-21 • Automotive ProASIC3 Output Drive for Advanced I/O Bank Type
I/O Standards
LVTTL
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Slew
✓
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
–
✓
✓
✓
✓
–
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
Notes:
–
–
✓
✓
✓
✓
–
1. There will be differences in timing between the Advanced I/O banks and the Standard Plus I/O banks (Table 2-20). Refer to the I/O
timing tables beginning on page 3-29 and Table 2-10 on page 2-29 for the standards supported by each device.
2. Refer to Table 2-12 on page 2-29 for I/O bank type definition.
v2.0
2-45
Automotive ProASIC3 Flash Family FPGAs
User I/O Naming Convention
Due to the comprehensive and flexible nature of ProASIC3 device user I/Os, a naming scheme is used to show the
details of each I/O (Figure 2-37 and Figure 2-38 on page 2-47). The name identifies to which I/O bank it belongs, as well
as pairing and pin polarity for differential I/Os.
I/O Nomenclature = Gmn/IOuxwBy
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
G
= Global
m
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east
middle), D (southeast corner), E (southwest corner), and F (west middle)
n
= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or
C2. Figure 2-15 on page 2-17 shows the three input pins per clock source MUX at CCC location m.
u
x
= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction
= P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os that support single-
ended and voltage-referenced I/O standards only. U (Positive-LVDS, DDR LVDS, BLVDS, and M-LVDS only) or V
(Negative-LVDS, DDR LVDS, BLVDS, and M-LVDS only) restrict the I/O differential pair from being selected as an
LVPECL pair.
w
= D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded
out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are
bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.
For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal
adjacency does not meet the requirements for a true differential pair.
B
y
= Bank
= Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise
direction.
GND
CCC
"A"
CCC
"B"
Bank 0
GND
GNDQ
VMV0
VCC
VCC
GND
VCCIB1
Bank 1
Bank 0
GND
VCCIB0
A3P060
A3P125
VCOMPLF
VCCPLF
CCC/PLL
"F"
CCC
"C"
GND
VCC
GND
VCC
VCCIB0
GND
VCCIB1
Bank 1
Bank 0
GND
VMV1
VJTAG
GNDQ
GND
TRST
TDO
CCC
"E"
CCC
"D"
VPUMP
Bank 1
GND
Figure 2-37 • Naming Conventions of Automotive ProASIC3 Devices with Two I/O Banks – Top View
2-46
v2.0
Automotive ProASIC3 Flash Family FPGAs
GND
CCC
"A"
CCC
"B"
Bank 0
GND
GNDQ
VMV1
Vcc
GND
VCCIB3
Bank 3
Bank 1
VCC
GND
VCCIB1
A3P250
A3P1000
VCOMPLF
VCCPLF
CCC/PLL
"F"
CCC
"C"
GND
VCC
GND
VCC
VCCIB1
VCCIB3
GND
VMV3
Bank 3
Bank 1
GND
VJTAG
GNDQ
GND
TRST
TDO
CCC
"E"
CCC
"D"
VPUMP
Bank 2
GND
Figure 2-38 • Naming Conventions of Automotive ProASIC3 Devices with Four I/O Banks – Top View
v2.0
2-47
Automotive ProASIC3 Flash Family FPGAs
Pin Descriptions
Supply Pins
GND. VMV and VCCI should be at the same voltage within
a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0
to VCCIB0, VMV1 to VCCIB1, etc.).
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O
logic.
V
PLL Supply Voltage
CCPLF
GNDQ
Ground (quiet)
Supply voltage to analog PLL, nominally 1.5 V. If unused,
VCCPLF should be tied to either the power supply or GND.
Quiet ground supply voltage to input buffers of I/O
banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package and
improves input signal integrity. GNDQ must always be
connected to GND on the board.
V
PLL Ground
COMPLF
Ground to analog PLL power supplies. Unused VCOMPLF
pins should be connected to GND.
V
JTAG Supply Voltage
JTAG
Automotive ProASIC3 devices have a separate bank for
the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG
power supply in a separate I/O bank gives greater
flexibility in supply selection and simplifies power supply
and PCB design. If the JTAG interface is neither used nor
planned for use, the VJTAG pin together with the TRST
pin could be tied to GND. It should be noted that VCC is
required to be powered for JTAG operation; VJTAG alone
is insufficient. If a device is in a JTAG chain of
interconnected boards, the board containing the
Automotive ProASIC3 device can be powered down,
provided both VJTAG and VCC to the Automotive
ProASIC3 part remain powered; otherwise, JTAG signals
will not be able to transition the Automotive ProASIC3
device, even in bypass mode.
V
Core Supply Voltage
CC
Supply voltage to the FPGA core, nominally 1.5 V. VCC is
required for powering the JTAG state machine in
addition to VJTAG. Even when an Automotive ProASIC3
device is in bypass mode in
a
JTAG chain of
interconnected devices, both VCC and VJTAG must remain
powered to allow JTAG signals to pass through the
Automotive ProASIC3 device.
V
Bx
I/O Supply Voltage
CCI
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are eight I/O
banks on Automotive ProASIC3 devices plus a dedicated
VJTAG bank. Each bank can have a separate VCCI
connection. All I/Os in a bank will run off the same VCCIBx
supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their
corresponding VCCI pins tied to GND.
V
Programming Supply Voltage
PUMP
Automotive ProASIC3 devices support single-voltage ISP
of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During
normal device operation, VPUMP can be left floating or
can be tied (pulled up) to any voltage between 0 V and
3.6 V. Programming power supply voltage (VPUMP) range
is 3.3 V +/- 5%.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. x is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package and improves input signal integrity. Each bank
must have at least one VMV connection, and no VMV
should be left unconnected. All I/Os in a bank run off the
same VMVx supply. VMV is used to provide a quiet supply
voltage to the input buffers of each I/O bank. VMVx can
be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O
banks should have their corresponding VMV pins tied to
When the VPUMP pin is tied to ground, it will shut off the
charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors
(both rated at 16 V) are to be connected in parallel
across VPUMP and GND, and positioned as close to the
FPGA pins as possible.
2-48
v2.0
Automotive ProASIC3 Flash Family FPGAs
Automotive ProASIC3 device. Isolating the JTAG power
supply in a separate I/O bank gives greater flexibility in
supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned
for use, the VJTAG pin together with the TRST pin could
be tied to GND.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
TCK
Test Clock
During programming, I/Os become tristated and weakly
pulled up to VCCI. With VCCI, VMV, and VCC supplies
continuously powered up, when the device transitions
from programming to operating mode, the I/Os are
instantly configured to the desired user configuration.
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/-down
resistor. If JTAG is not used, Actel recommends tying off
TCK to GND through a resistor placed close to the FPGA
pin. This prevents JTAG operation in case TMS enters an
undesired state.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high
impedance)
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements. Refer to Table 2-22 for
more information.
Input buffer is disabled (with tristate value of high
impedance)
Weak pull-up is programmed
Table 2-22 • Recommended Tie-Off Values for the TCK and
TRST Pins
GL
Globals
VJTAG
JTAG at 3.3 V
Tie-Off Resistance
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as I/Os, since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors. See more detailed descriptions of global I/O
connectivity in the "Clock Conditioning Circuits" section
on page 2-13. All inputs labeled GC/GF are direct inputs
into the quadrant clocks. For example, if GAA0 is used
for an input, GAA1 and GAA2 are no longer available for
input to the quadrant globals. All inputs labeled GC/GF
are direct inputs into the chip-level globals, and the rest
are connected to the quadrant globals. The inputs to the
global network are multiplexed, and only one input can
be used as a global input.
V
VJTAG at 2.5 V
VJTAG at 1.8 V
V
JTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on
the JTAG chain.
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
Refer to the "User I/O Naming Convention" section on
page 2-46 for an explanation of the naming of global
pins.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
JTAG Pins
Automotive ProASIC3 devices have a separate bank for
the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be
powered for the JTAG state machine to operate, even if
the device is in bypass mode; VJTAG alone is insufficient.
Both VJTAG and VCC to the Automotive ProASIC3 part
must be supplied to allow JTAG signals to transition the
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1532 boundary
scan pins (TCK, TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
v2.0
2-49
Automotive ProASIC3 Flash Family FPGAs
TRST
Boundary Scan Reset Pin
•
Timer—a world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer—a design netlist schematic viewer
ChipPlanner—a graphical floorplanner viewer and
editor
SmartPower—a tool that enables the designer to
quickly estimate the power consumption of a
design
PinEditor—a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor—a tool that displays all
assigned and unassigned I/O macros and their
attributes in a spreadsheet format
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the test access port
(TAP) is held in reset mode. The resistor values must be
chosen from Table 2-22 on page 2-49 and must satisfy
the parallel resistance value requirement. The values in
Table 2-22 on page 2-49 correspond to the resistor
recommended when a single device is used and the
equivalent parallel resistor when multiple devices are
connected via a JTAG chain.
•
•
•
•
•
In critical applications, an upset in the JTAG circuit could
allow entrance to an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
core generator, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements.
Special Function Pins
NC
No Connect
Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors such as Mentor Graphics, Synplicity,
Synopsys, and Cadence.® The Designer software is
available for both the Windows® and UNIX operating
systems.
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the
PCB. These pins should be left unconnected.
Programming
Programming can be performed using tools such as
Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel).
Software Tools
Overview of Tools Flow
The user can generate STP programming files from the
Designer software and use these files to program a
device. ProASIC3 devices can be programmed in-system.
For more information on ISP of ProASIC3 devices, refer to
the In-System Programming (ISP) in ProASIC3/E Using
FlashPro3 and Programming a ProASIC3/E Using a
Microprocessor application notes.
The Automotive ProASIC3 family of FPGAs is fully
supported by both Actel Libero IDE and Designer FPGA
development software. Actel Libero IDE is an integrated
design manager that seamlessly integrates design tools
while guiding the user through the design flow,
managing all design and log files and passing necessary
design data among tools. Additionally, Libero IDE allows
users to integrate both schematic and HDL synthesis into
a single flow and verify the entire design in a single
environment (see the Libero IDE flow diagram located
on the Actel website). Libero IDE includes Synplify® AE
from Synplicity,® ViewDraw® AE from Mentor Graphics,®
ModelSim® HDL Simulator from Mentor Graphics,
WaveFormer LiteTM AE from SynaptiCAD,® PALACE™ AE
Physical Synthesis from Magma Design Automation,TM
and Designer software from Actel.
The Automotive ProASIC3 device can be serialized with a
unique identifier stored in the FlashROM of each device.
Serialization is an automatic assignment of serial
numbers that are stored within the STAPL file used for
programming. The area of the FlashROM used for
holding such identifiers is defined using SmartGen, and
the range of serial numbers to be used is defined at the
time of STAPL file generation with FlashPoint. Serial
number values for STAPL file generation can even be
read from
a file of predefined values. Serialized
programming using a serialized STAPL file can be done
through Actel In-House Programming (IHP), an external
vendor using Silicon Sculptor software, or the ISP
capabilities of the FlashPro software.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
2-50
v2.0
Automotive ProASIC3 Flash Family FPGAs
Security
ISP
Automotive ProASIC3 devices have a built-in 128-bit AES
decryption core. The decryption core facilitates secure in-
system programming of the FPGA core array fabric and
the FlashROM. The FlashROM and the FPGA core fabric
can be programmed independently of each other,
allowing the FlashROM to be updated without the need
for change to the FPGA core fabric. The AES master key is
stored in on-chip nonvolatile memory (flash). The AES
master key can be preloaded into parts in a secure
programming environment (such as the Actel In-House
Programming center), and then "blank" parts can be
shipped to an untrusted programming or manufacturing
center for final personalization with an AES-encrypted
bitstream. Late-stage product changes or personalization
can be implemented easily and securely by simply
sending a STAPL file with AES-encrypted data. Secure
remote field updates over public networks (such as the
Internet) are possible by sending and programming a
STAPL file with AES-encrypted data.
Automotive ProASIC3 devices support IEEE 1532 ISP via
JTAG and require a single VPUMP voltage of 3.3 V during
programming. In addition, programming via
a
microcontroller in a target system can be achieved. See
the application note In-System Programming (ISP) in
ProASIC3/E Using FlashPro3 for more details.
JTAG 1532
Automotive ProASIC3 devices support the JTAG-based
IEEE 1532 standard for ISP. As part of this support, when
an Automotive ProASIC3 device is in an unprogrammed
state, all user I/O pins are disabled. This is achieved by
keeping the global IO_EN signal deactivated, which also
has the effect of disabling the input buffers. The
SAMPLE/PRELOAD instruction captures the status of pads
in parallel and shifts them out as new data is shifted in
for loading into the Boundary Scan Register. When the
Automotive ProASIC3 device is in an unprogrammed
state, the SAMPLE/PRELOAD instruction has no effect on
I/O status; however, it will continue to shift in new data
to be loaded into the BSR. Therefore, when
SAMPLE/PRELOAD is used on an unprogrammed device,
the BSR will be loaded with undefined data. Refer to the
In-System Programming (ISP) in ProASIC3/E Using
FlashPro3 application note for more details.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-192) block cipher is the
NIST (National Institute of Standards and Technology)
replacement for DES (Data Encryption Standard
FIPS46-2). AES has been designed to protect sensitive
government information well into the 21st century. It
replaces the aging DES, which NIST adopted in 1977 as a
Federal Information Processing Standard used by federal
agencies to protect sensitive, unclassified information.
The 128-bit AES standard has 3.4 × 1038 possible 128-bit
key variants, and it has been estimated that it would
take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in
Automotive ProASIC3 devices in nonvolatile flash
memory. All programming files sent to the device can be
authenticated by the part prior to programming to
ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of Automotive ProASIC3 devices remain secure.
For JTAG timing information on setup, hold, and fall
times, refer to the FlashPro User’s Guide.
Boundary Scan
Automotive ProASIC3 devices are compatible with IEEE
Standard 1149.1, which defines a hardware architecture
and the set of mechanisms for boundary scan testing.
The basic Automotive ProASIC3 boundary scan logic
circuit is composed of the TAP controller, test data
registers, and instruction register (Figure 2-41 on page 2-
53). This circuit supports all mandatory IEEE 1149.1
instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS)
and the optional IDCODE instruction (Table 2-23).
Table 2-23 • Boundary Scan Opcodes
AES decryption can also be used on the 1,024-bit
FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support
for subscription model products. See the application
note ProASIC3/E Security for more details.
Hex Opcode
EXTEST
00
07
0E
01
0F
05
FF
HIGHZ
USERCODE
SAMPLE/PRELOAD
IDCODE
CLAMP
BYPASS
v2.0
2-51
Automotive ProASIC3 Flash Family FPGAs
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-49 for pull-up/-down
recommendations for TDO and TCK pins. Table 2-24 gives
pull-down recommendations for the TRST and TCK
pins.
The TAP controller is a 4-bit state machine (16 states)
that operates as shown in Figure 2-40. The 1s and 0s
represent the values that must be present on TMS at a
rising edge of TCK for the given state transition to occur.
IR and DR indicate that the instruction register or the
data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain HIGH for five TCK cycles. The TRST pin
can also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
Table 2-24 • TRST and TCK Pull-Down Recommendations
VJTAG
JTAG at 3.3 V
Tie-Off Resistance*
200 Ω to 1 kΩ
V
Automotive ProASIC3 devices support three types of test
data registers: bypass, device identification, and
boundary scan. The bypass register is selected when no
other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test
data path. The 32-bit device identification register is a
shift register with four fields (LSB, ID number, part
number, and version). The boundary scan register
observes and controls the state of each I/O pin. Each I/O
cell has three boundary scan register cells, each with
serial-in, serial-out, parallel-in, and parallel-out pins.
VJTAG at 2.5 V
VJTAG at 1.8 V
200 Ω to 1 kΩ
500 Ω to 1 kΩ
VJTAG at 1.5 V
500 Ω to 1 kΩ
Note: *Equivalent parallel resistance if more than one device
is on JTAG chain (Figure 2-39 on page 2-52)
1.5 V
VJTAG
JTAG
Header
TRST
1
TCK
GND
TEST_LOGIC_RESET
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0
RUN_TEST_IDLE
0
Actel
TDO
1
1
1
1.5 kΩ
FPGA 1
TDI
TDI
SELECT_DR
0
SELECT_IR
0
Actel
FPGA 2
1
1
TDO
TDO
TDO
1.5 kΩ
1.5 kΩ
1.5 kΩ
CAPTURE_DR
0
CAPTURE_IR
0
0
0
Actel
FPGA 3
SHIFT_DR
1
SHIFT_IR
1
TDI
TDI
1
1
Actel
FPGA 4
EXIT1_DR
0
EXIT1_IR
0
0
0
PAUSE_DR
1
PAUSE_IR
1
Note: TCK is correctly wired with an equivalent tie-off resistance
of 500 Ω, which satisfies the table for VJTAG of 1.5 V. The
resistor values for TRST are not appropriate in this case, as
the tie-off resistance of 375 Ω is below the recommended
minimum for VJTAG = 1.5 V, but would be appropriate for a
VJTAG setting of 2.5 V or 3.3 V.
EXIT2_DR
1
EXIT2_IR
1
0
0
UPDATE_DR
UPDATE_IR
Figure 2-39 • Parallel Resistance on JTAG Chain of Devices
0
1
1
0
Figure 2-40 • TAP Controller State Machine
2-52
v2.0
Automotive ProASIC3 Flash Family FPGAs
The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register
chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic
I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or
observe the logic state of each I/O.
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
Bypass Register
Instruction
Register
TAP
Controller
Device
Logic
I/O
I/O
I/O
I/O
I/O
Figure 2-41 • Boundary Scan Chain in Automotive ProASIC3
v2.0
2-53
Automotive ProASIC3 Flash Family FPGAs
DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute
Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond
those listed under the Recommended Operating Conditions specified in Table 3-2 on page 3-2 is not implied.
Table 3-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
V
VJTAG
VPUMP
VCCPLL
VCCI
–0.3 to 3.75
Programming voltage
–0.3 to 3.75
Analog power supply (PLL)
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 to 1.65
–0.3 to 3.75
VMV
VI
–0.3 to 3.75
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when
I/O hot-insertion mode is disabled)
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+150
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or
overshoot according to the limits shown in Table 3-3 on page 3-3.
2. For Flash programming and retention maximum limits, refer to Figure 3-1 on page 3-2. For recommended operating limits, refer to
Table 3-2 on page 3-2.
v2.0
3-1
Automotive ProASIC3 Flash Family FPGAs
Table 3-2 • Recommended Operating Conditions
Symbol
TJ
Parameter
Junction temperature
Automotive Grade 1 Automotive Grade 2 Units
–40 to +135
1.425 to 1.575
1.4 to 3.6
–40 to +115
1.425 to 1.575
1.4 to 3.6
°C
V
V
V
V
V
V
V
V
V
V
V
VCC
1.5 V DC core supply voltage
JTAG DC voltage
VJTAG
VPUMP
Programming voltage
Programming Mode
Operation3
3.0 to 3.6
3.0 to 3.6
0 to 3.6
0 to 3.6
VCCPLL
Analog power supply (PLL)
1.4 to 1.6
1.4 to 1.6
VCCI and VMV 1.5 V DC supply voltage
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.7 to 1.9
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
3.0 to 3.6
3.0 to 3.6
LVDS/BLVDS/M-LVDS differential I/O
LVPECL differential I/O
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
Notes:
1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given
in Table 3-14 on page 3-17. VMV and VCCI should be at the same voltage within a given I/O bank.
2. All parameters representing voltages are measured with respect to GND unless otherwise specified.
3. VPUMP can be left floating during operation (not programming mode).
110
100
HTR
Lifetime
Tj (°C)
(yrs)
90
80
70
60
50
40
30
20
10
0
70
85
102.7
43.8
20.0
15.6
100
105
110
115
120
125
130
12.3
9.7
7.7
6.2
5.0
135
140
4.0
3.3
145
150
2.7
2.2
70 85 100 105 110 115 120 125 130 135 140 145 150
Temperature (ºC)
Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.
Figure 3-1 • High Temperature Data Retention (HTR)
3-2
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-3 • Overshoot and Undershoot Limits (as measured on quiet I/Os)
Average VCCI–GND Overshoot or Undershoot Maximum Overshoot/ Maximum Overshoot/
VCCI and VMV
Duration as a Percentage of Clock Cycle
Undershoot (115°C)
Undershoot (135°C)
2.7 V or less
10%
5%
0.81 V
0.90 V
0.80 V
0.90 V
0.79 V
0.88 V
N/A
0.72 V
0.82 V
0.72 V
0.81 V
0.69 V
0.79 V
N/A
3 V
10%
5%
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
N/A
N/A
1. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one
out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
2. This table refers only to overshoot/undershoot limits for simultaneously switching I/Os and does not provide PCI
overshoot/undershoot limits.
v2.0
3-3
Automotive ProASIC3 Flash Family FPGAs
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated power-up management circuitry is
designed into every ProASIC3 device. These circuits
ensure easy transition from the powered-off state to the
powered-up state of the device. The many different
supplies can power up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in Figure 3-2.
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV
higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up
oscillations and current surges. Note the following:
•
During programming, I/Os become tristated and
weakly pulled up to VCCI
JTAG supply, PLL power supplies, and charge pump
PUMP supply have no influence on I/O behavior.
There are five regions to consider during power-up.
.
ProASIC3 I/Os are activated only if ALL of the following
three conditions are met:
•
V
1. VCC and VCCI are above the minimum specified trip
points (Figure 3-2).
Internal Power-Up Activation Sequence
2. VCCI > VCC – 0.75 V (typical)
1. Core
3. Chip is in the operating mode.
2. Input buffers
V
CCI Trip Point:
3. Output buffers, after 200 ns delay from input
buffer activation
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
= V + VT
CCI
CC
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
V
CC
V
= 1.575 V
CC
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
V
= 1.425 V
CC
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
V = 0.85 V 0.25 V
a
Deactivation trip point:
Region 1: I/O buffers are OFF
V = 0.75 V 0.25 V
d
V
Activation trip point:
CCI
Min V datasheet specification
CCI
V = 0.9 V 0.3 V
voltage at a selected I/O
a
Deactivation trip point:
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
V = 0.8 V 0.3 V
d
Figure 3-2 • I/O State as a Function of VCCI and VCC Voltage Levels
3-4
v2.0
Automotive ProASIC3 Flash Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because dynamic and static power consumption cause the chip junction
to be higher than the ambient temperature.
EQ 3-1 can be used to calculate junction temperature.
TJ = Junction Temperature = ΔT + TA
EQ 3-1
where:
TA = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P
θja = Junction-to-ambient of the package. θja numbers are located in Table 3-4.
P = Power dissipation
rates. The absolute maximum junction temperature is
110°C. EQ 3-2 shows a sample calculation of the absolute
maximum power dissipation allowed for a 484-pin FBGA
package at commercial temperature and in still air.
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and
the junction-to-ambient air thermal resistivity is θja. The
thermal characteristics for θja are shown for two air flow
Max. junction temp. (°C) – Max. ambient temp. (°C)
110°C – 70°C
20.5°C/W
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.951 W
θja(°C/W)
EQ 3-2
Table 3-4 • Package Thermal Resistivities
θja
200
500
Package Type
Device
Pin Count
θjc
10.0
3.8
3.8
3.2
6.3
6.6
8.0
Still Air
35.3
ft./min.
ft./min.
Units
Very Thin Quad Flat Pack (VQFP)
Fine Pitch Ball Grid Array (FBGA)
All devices
See note*
See note*
See note*
A3P1000
A3P1000
A3P1000
100
144
256
484
144
256
484
29.4
22.9
22.8
17.0
26.2
24.4
19.0
27.1
21.5
21.5
15.9
24.2
22.7
16.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
26.9
26.6
20.5
31.6
28.1
23.3
Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be
available in future revisions of the datasheet.
Temperature and Voltage Derating Factors
Table 3-5 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 115°C, VCC = 1.425 V)
Array Voltage VCC (V)
–40°C
0.83
0°C
0.88
0.83
0.80
25°C
0.90
0.85
0.82
70°C
0.95
0.90
0.87
85°C
0.97
0.92
0.88
115°C
1.00
125°C
1.01
135°C
1.02
1.425
1.5
0.79
0.95
0.96
0.97
1.575
0.76
0.91
0.93
0.94
v2.0
3-5
Automotive ProASIC3 Flash Family FPGAs
Calculating Power Dissipation
Quiescent Supply Current
Table 3-6 • Quiescent Supply Current Characteristics
A3P060
A3P125
2 mA
A3P250
3 mA
A3P1000
8 mA
Typical (25°C)
2 mA
53 mA
26 mA
Maximum (Automotive Grade 1) – 135°C
Maximum (Automotive Grade 2) – 115°C
Notes:
53 mA
26 mA
106 mA
53 mA
265 mA
131 mA
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-7 and
Table 3-10 on page 3-8.
Power Per I/O Pin
Table 3-7 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
VMV (V)
Single-Ended
3.3 V LVTTL /
3.3
–
16.69
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
5.12
2.13
1.45
18.11
18.11
3.3 V PCI-X
Differential
LVDS
2.5
3.3
2.26
5.72
1.20
1.87
LVPECL
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
Table 3-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
Static Power
Dynamic Power
PAC9 (µW/MHz)2
VMV (V)
PDC2 (mW)1
Single-Ended
3.3 V LVTTL /
3.3
–
16.72
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
2.5
1.8
–
–
5.14
2.13
3-6
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
Static Power
P
Dynamic Power
AC9 (µW/MHz)2
VMV (V)
DC2 (mW)1
P
1.5 V LVCMOS (JESD8-11)
1.5
3.3
3.3
–
–
–
1.48
18.13
18.13
3.3 V PCI
3.3 V PCI-X
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
Table 3-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
Static Power
Dynamic Power
PAC10 (µW/MHz)3
CLOAD (pF)
VCCI (V)
PDC3 (mW)2
Single-Ended
3.3 V LVTTL /
35
3.3
–
468.67
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
35
35
35
10
10
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
267.48
149.46
103.12
201.02
201.02
3.3 V PCI-X
Differential
LVDS
–
–
2.5
3.3
7.74
88.92
LVPECL
19.54
166.52
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VMV.
3. PAC10 is the total dynamic power measured on VCCI and VMV.
v2.0
3-7
Automotive ProASIC3 Flash Family FPGAs
Table 3-10 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
Static Power
Dynamic Power
P
CLOAD (pF)
VCCI (V)
PDC3 (mW)2
AC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
35
35
35
35
10
10
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
452.67
258.32
133.59
92.84
184.92
184.92
3.3 V PCI-X
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VMV.
3. PAC10 is the total dynamic power measured on VCCI and VMV.
3-8
v2.0
Automotive ProASIC3 Flash Family FPGAs
Power Consumption of Various Internal Resources
Table 3-11 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
Device Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
A3P1000
14.50
A3P250
A3P125
11.00
A3P060
9.30
11.00
1.58
PAC2
2.48
0.81
0.81
PAC3
0.81
0.12
PAC4
Clock contribution of
sequential module
a VersaTile used as a
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a sequential
module
0.07
0.29
0.29
0.70
Second contribution of a VersaTile used as a
sequential module
Contribution of a VersaTile used as a combinatorial
module
PAC8
PAC9
Average contribution of a routing net
Contribution of an I/O input pin (standard-
dependent)
See Table 3-7 on page 3-6.
PAC10
PAC11
PAC12
Contribution of an I/O output pin (standard-
dependent)
See Table 3-7 and Table 3-10 on page 3-8.
Average contribution of a RAM block during a read
operation
25.00
30.00
Average contribution of a RAM block during a write
operation
PAC13
PAC14
Static PLL contribution
2.55 mW
2.60
Dynamic contribution for PLL
Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or
SmartPower tool in Libero IDE.
v2.0
3-9
Automotive ProASIC3 Flash Family FPGAs
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and
detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-12 on page 3-12.
Enable rates of output buffers—guidelines are provided for typical applications in Table 3-13 on page 3-12.
Read rate and write rate to the memory—guidelines are provided for typical applications in Table 3-13 on
page 3-12. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
P
STAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in Table 3-12 on page 3-12.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-12 on page 3-12.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
F
N
P
S-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell
is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-12.
FCLK is the global clock signal frequency.
3-10
v2.0
Automotive ProASIC3 Flash Family FPGAs
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-12.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
N
C-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-12 on page 3-12.
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
F
INPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-12 on page 3-12.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-12 on page 3-12.
β1 is the I/O buffer enable rate—guidelines are provided in Table 3-13 on page 3-12.
FCLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
β3 is the RAM enable rate for write operations—guidelines are provided in Table 3-13 on page 3-12.
F
PLL Contribution—P
PLL
PPLL = PAC13 + PAC14 * FCLKOUT
FCLKIN is the input clock frequency.
F
CLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
v2.0
3-11
Automotive ProASIC3 Flash Family FPGAs
–
–
–
–
–
Bit 1
Bit 2
…
= 50%
= 25%
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic
element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net
switches at half the clock frequency. Below are some
examples:
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% +
12.5% + . . . + 0.78125%) / 8.
Enable Rate Definition
•
The average toggle rate of a shift register is 100%
because all flip-flop outputs toggle at half of the
clock frequency.
Output enable rate is the average percentage of time
during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate
should be 100%.
•
The average toggle rate of an 8-bit counter is
25%:
–
Bit 0 (LSB) = 100%
Table 3-12 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 3-13 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
100%
β1
β2
β3
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
3-12
v2.0
Automotive ProASIC3 Flash Family FPGAs
User I/O Characteristics
Timing Model
I/O Module
(non-registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL (applicable to
Advanced I/O banks only)
t
PD = 0.67 ns
tPD = 0.58 ns
tDP = 1.66 ns
I/O Module
(non-registered)
Combinational Cell
Y
Output Drive Strength = 12 mA
High Slew Rate
LVTTL
tDP = 3.25 ns (Advanced I/O banks)
tPD = 1.04 ns
I/O Module
(non-registered)
Combinational Cell
I/O Module
(registered)
Y
Output drive Strength = 8 mA
LVTTL
t
PY = 1.29 ns
High Slew Rate
tDP = 4.52 ns (Advanced I/O banks)
LVPECL
(applicable
to Advanced
I/O banks only)
tPD = 0.60 ns
I/O Module
(non-registered)
D
Q
Combinational Cell
Y
Output Drive Strength = 4 mA
High Slew Rate
LVCMOS 1.5 V
t
ICLKQ = 0.29 ns
tDP = 4.89 ns (Advanced I/O banks)
t
PD = 0.56 ns
tISUD = 0.31 ns
Input LVTTL
Clock
I/O Module
(registered)
Register Cell
Register Cell
Combinational Cell
Y
tPY = 0.94 ns (Advanced I/O banks)
LVTTL 3.3 V Output Drive
Strength = 12 mA
High Slew Rate
DP = 3.25 ns
D
Q
D
Q
D
Q
I/O Module
t
PD = 0.56 ns
t
(non-registered)
(Advanced I/O banks)
tOCLKQ = 0.70 ns
OSUD = 0.37 ns
tCLKQ = 0.66 ns
tSUD = 0.51 ns
t
CLKQ = 0.66 ns
LVDS,
BLVDS,
M-LVDS
t
tSUD = 0.51 ns
Input LVTTL
Clock
Input LVTTL
Clock
(Applicable for
Advanced I/O
Banks only)
tPY = 1.47 ns
tPY = 0.94 ns
t
PY = 0.94 ns
(Advanced I/O banks)
(Advanced I/O banks)
Figure 3-3 • Timing Model
Operating Conditions: –1 Speed, Automotive Grade 2 Temp. Range (TJ = 115°C), Worst Case VCC = 1.425 V
v2.0
3-13
Automotive ProASIC3 Flash Family FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VCC
VIL
PAD
Y
50%
50%
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 3-4 • Input Buffer Timing Model and Delays (example)
3-14
v2.0
Automotive ProASIC3 Flash Family FPGAs
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
tDOUT
(F)
VCC
(R)
50%
50%
VCC
D
0 V
50%
50%
0 V
DOUT
PAD
VOH
Vtrip
Vtrip
VOL
tDP
(R)
tDP
(F)
Figure 3-5 • Output Buffer Model and Delays (example)
v2.0
3-15
Automotive ProASIC3 Flash Family FPGAs
t
EOUT
D
Q
CLK
t , t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
t
CLK
D
= MAX(t
(r), t
(f))
V
I/O interface
EOUT
EOUT
EOUT
V
CC
D
E
CC
50%
t
50%
t
EOUT (F)
EOUT (R)
V
CC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
V
HZ
CCI
90% V
CCI
V
V
trip
trip
V
10% V
OL
CCI
V
CC
D
E
V
CC
50%
50%
t
t
EOUT (F)
EOUT (R)
V
CC
50%
50%
EOUT
PAD
50%
t
ZHS
t
V
ZLS
OH
V
V
trip
trip
V
OL
Figure 3-6 • Tristate Output Buffer Timing Model and Delays (example)
3-16
v2.0
Automotive ProASIC3 Flash Family FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software Settings
Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Advanced I/O Banks
VIL
Max, V
VIH
Min, V
VOL
Max, V
0.4
VOH
Min, V
2.4
IOL
mA
12
IOH
mA
12
Drive
Slew
Rate Min, V
I/O Standard Strength
Max, V
3.3 V LVTTL /
12 mA
High
–0.3
0.8
2
3.6
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12mA
12mA
High
High
High
–0.3
–0.3
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
1.7
12
12
12
12
12
12
0.35 * VCCI 0.65 * VCCI
0.30 * VCCI 0.7 * VCCI
0.45
VCCI – 0.45
0.25 * VCCI 0.75 * VCCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Note: Currents are measured at 125°C junction temperature.
Table 3-15 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
VIL
Max, V
VIH
Min, V
VOL
Max, V
0.4
VOH
Min, V
2.4
IOL
mA
12
IOH
mA
12
Drive
Slew
I/O Standard Strength Rate Min, V
Max, V
3.3 V LVTTL /
12 mA
High
–0.3
0.8
2
3.6
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
8 mA
4 mA
High
High
High
–0.3
–0.3
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
0.45
1.7
12
8
12
8
0.35 * VCCI 0.65 * VCCI
0.30 * VCCI 0.7 * VCCI
VCCI – 0.45
0.75 * VCCI
0.25 * VCCI
4
4
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Note: Currents are measured at 125°C junction temperature.
Table 3-16 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions—Software Default Settings
Applicable to Standard I/O Banks
VIL
Max, V
VIH
Min, V
VOL
VOH
Min, V
2.4
IOL
mA
8
IOH
mA
8
Drive
Slew
I/O Standard Strength Rate Min, V
Max, V Max, V
3.3 V LVTTL /
3.3 V LVCMOS
8 mA
High
–0.3
0.8
2
3.6
0.4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
8 mA
4 mA
2 mA
High
High
High
–0.3
–0.3
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
1.7
8
4
2
8
4
2
0.35 * VCCI 0.65 * VCCI
0.45
VCCI – 0.45
0.75 * VCCI
0.30 * VCCI
0.7 * VCCI
0.25 *
VCCI
Note: Currents are measured at 125°C junction temperature.
v2.0
3-17
Automotive ProASIC3 Flash Family FPGAs
Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Automotive Grade 1 and Grade 2
Automotive Grade 11
Automotive Grade 22
IIL
IIH
µA
10
10
10
10
10
10
IIL
IIH
µA
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL /3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
µA
10
10
10
10
10
10
µA
15
15
15
15
15
15
3.3 V PCI-X
Notes:
1. Automotive range Grade 1 (–40°C < TJ < 135°C)
2. Automotive range Grade 2 (–40°C < TJ < 115°C)
3-18
v2.0
Automotive ProASIC3 Flash Family FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 3-18 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip
)
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
1.4 V
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
Table 3-19 • I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data-to-Pad delay through the Output Buffer
Pad-to-Data delay through the Input Buffer
tPY
tDOUT
tEOUT
tDIN
tHZ
Data–to–Output Buffer delay through the I/O interface
Enable–to–Output Buffer Tristate Control delay through the I/O interface
Input Buffer–to–Data delay through the I/O interface
Enable-to-Pad delay through the Output Buffer—HIGH to Z
Enable-to-Pad delay through the Output Buffer—Z to HIGH
Enable-to-Pad delay through the Output Buffer—LOW to Z
tZH
tLZ
tZL
Enable-to-Pad delay through the Output Buffer—Z to LOW
tZHS
tZLS
Enable-to-Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable-to-Pad delay through the Output Buffer with delayed enable—Z to LOW
v2.0
3-19
Automotive ProASIC3 Flash Family FPGAs
Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
35 pF
–
0.53 3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37 2.71 ns
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
High
High
High
High
High
High
High
35 pF
35 pF
35 pF
–
–
–
0.53 3.28 0.04 1.19 0.38 3.34 3.16 1.77 1.80 5.39 5.22 ns
0.53 3.25 0.04 1.12 0.38 1.89 1.63 3.41 3.75 3.06 2.82 ns
0.53 3.75 0.04 1.32 0.38 2.18 1.91 3.63 3.87 3.35 3.11 ns
12 mA
Per PCI spec
PerPCI-Xspec
24 mA
10 pF 252 0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns
10 pF 252 0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns
3.3 V PCI-X
LVDS
–
–
–
–
0.53 1.68 0.04 1.47
0.53 1.66 0.04 1.29
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
24 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-11 on page 3-49 for connectivity.
This resistor is not required during normal operation.
Table 3-21 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
35 pF
–
0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
8 mA
High
High
High
High
High
35 pF
35 pF
35 pF
–
–
–
0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns
0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns
0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns
4 mA
Per PCI spec
Per PCI-X spec
10 pF 25 2 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns
10 pF 25 2 0.55 2.19 0.04 0.79 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns
3.3 V PCI-X
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-11 on page 3-49 for connectivity.
This resistor is not required during normal operation.
3-20
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-22 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 135°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
35 pF
–
0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
High
High
High
High
High
High
High
35pF
35pF
35pF
–
–
–
0.55 3.39 0.04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.39 ns
0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.92 ns
0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.21 ns
12 mA
Per PCI spec
Per PCI-X spec
24 mA
10pF 252 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
10pF 252 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
3.3 V PCI-X
LVDS
–
–
–
–
0.55 1.74 0.04 1.52
0.55 1.71 0.04 1.34
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
24 mA
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-11 on page 3-49 for connectivity.
This resistor is not required during normal operation.
Table 3-23 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
35 pF
–
0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
8 mA
High
High
High
High
High
35pF
35pF
35pF
–
–
–
0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns
0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns
0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns
4 mA
Per PCI spec
Per PCI-X spec
10pF 25 2 0.55 2.55 0.04 0.82 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
10pF 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns
3.3 V PCI-X
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-11 on page 3-49 for connectivity.
This resistor is not required during normal operation.
v2.0
3-21
Automotive ProASIC3 Flash Family FPGAs
Detailed I/O DC Characteristics
Table 3-24 • Input Capacitance
Symbol
CIN
Definition
Input capacitance
Input capacitance on the clock pin
Conditions
Min.
Max.
Units
pF
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
pF
Table 3-25 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
RPULL-DOWN
(Ω)2
100
100
50
RPULL-UP
Standard
Drive Strength
(Ω)3
300
300
150
150
75
3.3 V LVTTL / 3.3V LVCMOS
2 mA
4 mA
6 mA
8 mA
50
12 mA
16 mA
24 mA
2 mA
25
17
50
11
33
2.5 V LVCMOS
1.8 V LVCMOS
100
50
200
100
50
6 mA
12 mA
16 mA
24 mA
2 mA
25
20
40
11
22
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
12 mA
16 mA
2 mA
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
Per PCI/PCI-X specification
33
37
3.3 V PCI / PCI-X
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
3-22
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-26 • I/O Output Buffer Maximum Resistances1
Applicable to Standard Plus I/O Banks
RPULL-DOWN
RPULL-UP
(Ω)3
300
300
150
150
75
Standard
Drive Strength
(Ω)2
100
100
50
3.3 V LVTTL/ 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
50
12 mA
25
16 mA
25
75
2.5 V LVCMOS
1.8 V LVCMOS
2 mA
100
50
200
100
50
6 mA
12 mA
25
2 mA
200
100
50
225
112
56
4 mA
6 mA
8 mA
2 mA
50
56
1.5 V LVCMOS
200
100
0
224
112
0
4 mA
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
Table 3-27 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 k
11 k
18 k
19 k
Max.
45 k
55 k
70 k
90 k
Min.
10 k
12 k
17 k
19 k
Max.
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
45 k
74 k
110 k
140 k
1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
v2.0
3-23
Automotive ProASIC3 Flash Family FPGAs
Table 3-28 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
Drive Strength
2 mA
I
OSL (mA)*
27
IOSH (mA)*
25
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
6 mA
27
25
54
51
8 mA
54
51
12 mA
16 mA
24 mA
2 mA
109
127
181
27
103
132
268
25
3.3 V LVCMOS
4 mA
27
25
6 mA
54
51
8 mA
54
51
12 mA
16 mA
24 mA
2 mA
109
127
181
18
103
132
268
16
2.5 V LVCMOS
1.8 V LVCMOS
6 mA
37
32
12 mA
16 mA
24 mA
2 mA
74
65
87
83
124
11
169
9
4 mA
22
17
6 mA
44
35
8 mA
51
45
12 mA
16 mA
2 mA
74
91
74
91
1.5 V LVCMOS
16
13
4 mA
33
25
6 mA
39
32
8 mA
55
66
12 mA
Per PCI/PCI-X specification
55
66
3.3 V PCI/PCI-X
109
103
Note: *TJ = 100°C
3-24
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-29 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
Drive Strength
I
OSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
27
27
25
25
51
51
103
103
16
32
65
9
4 mA
6 mA
54
8 mA
54
12 mA
109
109
18
16 mA
2.5 V LVCMOS
1.8 V LVCMOS
2 mA
6 mA
37
12 mA
74
2 mA
11
4 mA
22
17
35
35
13
25
103
6 mA
44
8 mA
2 mA
44
1.5 V LVCMOS
16
4 mA
33
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
109
Note: *TJ = 100°C
The length of time an I/O can withstand IOSH/IOSL events
depends on the junction temperature. The reliability
data below is based on a 3.3 V, 12 mA I/O setting, which
is the worst case for this type of analysis.
v2.0
3-25
Automotive ProASIC3 Flash Family FPGAs
For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a
reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be
needed in extremely prolonged stress conditions.
Table 3-30 • Short Current Event Duration before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
110°C
125°C
135°
6 months
3 months
25 days
12 days
Table 3-31 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.)
No requirement
Input Rise/Fall Time (max.)
Reliability
20 years (110°C)
10 years (100°C)
LVTTL/LVCMOS
10 ns *
10 ns *
LVDS/BLVDS.M-LVDS/LVPECL
No requirement
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, the rise time and
fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the
input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure there is no
excessive noise coupling into input signals.
3-26
v2.0
Automotive ProASIC3 Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses
an LVTTL input buffer and push-pull output buffer.
Table 3-32 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V
LVTTL /
3.3 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max.,
mA1
Max.,
mA1
Min., V Max., V Min., V Max., V Max., V
Min., V mA mA
µA2 µA2
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
2
27
27
25
25
10
10
10
10
10
10
10
10
10
10
10
10
10
10
4 mA
4
4
6 mA
6
6
54
51
8 mA
8
8
54
51
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
109
127
181
103
132
268
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 3-33 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V
LVTTL /
3.3 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max.,
mA1
Max.,
mA1
Min., V Max., V Min., V Max., V Max., V
Min., V mA mA
µA2 µA2
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
2
4
27
27
25
25
10
10
10
10
10
10
10
10
10
10
10
10
4 mA
6 mA
6
6
54
51
8 mA
8
8
54
51
12 mA
16 mA
Notes:
12
16
12
16
109
109
103
103
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
v2.0
3-27
Automotive ProASIC3 Flash Family FPGAs
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 3-7 • AC Loading
Table 3-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
1.4
35
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
3-28
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
8.56 0.05 1.14 0.46 8.72 7.37 1.46 1.42 11.22 9.866
7.28 0.04 0.97 0.39 7.42 6.27 1.46 1.42 9.54
5.49 0.05 1.14 0.46 5.59 4.55 1.65 1.74 8.09
4.67 0.04 0.97 0.39 4.75 3.87 1.65 1.74 6.88
5.49 0.05 1.14 0.46 5.59 4.55 1.65 1.74 8.09
4.67 0.04 0.97 0.39 4.75 3.87 1.65 1.74 6.88
3.95 0.05 1.14 0.46 4.02 1.56 3.59 1.94 6.52
3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55
3.73 0.05 1.14 0.46 1.84 1.42 3.65 4.11 3.05
3.17 0.04 0.97 0.39 1.84 1.42 3.10 3.50 3.05
3.44 0.05 1.14 0.46 1.70 1.17 3.72 4.54 2.91
2.92 0.04 0.97 0.39 1.70 1.17 3.16 3.86 2.91
8.393
7.05
ns
6 mA
STD
-1
ns
5.997
7.05
ns
8 mA
STD
-1
ns
5.997
2.795
2.797
2.651
2.653
2.405
2.407
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.64 11.47 0.05 1.14 0.46 11.68 9.95 1.46 1.33 14.18 12.449
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
9.75 0.04 0.97 0.39 9.94 8.46 1.46 1.33 12.06 10.59
8.13 0.05 1.14 0.46 8.28 7.03 1.65 1.65 10.79 9.526
ns
6 mA
STD
-1
ns
6.92 0.04 0.97 0.39 7.05 5.98 1.65 1.65 9.17
8.103
ns
8 mA
STD
-1
8.13 0.05 1.14 0.46 8.28 7.03 1.65 1.65 10.79 9.526
ns
6.92 0.04 0.97 0.39 7.05 5.98 1.65 1.65 9.17
6.24 0.05 1.14 0.46 6.36 5.45 1.77 1.85 8.86
5.31 0.04 0.97 0.39 5.41 4.63 1.77 1.85 7.53
5.82 0.05 1.14 0.46 5.93 5.10 1.80 1.90 8.43
4.95 0.04 0.97 0.39 5.04 4.34 1.80 1.90 7.17
5.42 0.05 1.14 0.46 5.52 5.08 1.83 2.10 8.02
4.61 0.04 0.97 0.39 4.70 4.32 1.83 2.11 6.82
8.103
7.946
6.76
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
7.604
6.468
7.581
6.449
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-29
Automotive ProASIC3 Flash Family FPGAs
Table 3-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
7.027
5.978
4.267
3.63
Units
ns
4 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
8.06 0.05 1.12 0.46 8.20 7.03 1.26 1.27 8.20
6.85 0.04 .095 0.39 6.98 5.98 1.26 1.27 6.98
5.03 0.05 1.12 0.46 5.13 4.27 1.42 1.56 5.13
4.28 0.04 0.95 0.39 4.36 3.63 1.42 1.56 4.36
5.03 0.05 1.12 0.46 5.13 4.27 1.42 1.56 5.13
4.28 0.04 0.95 0.39 4.36 3.63 1.42 1.56 4.36
3.53 0.05 1.12 0.46 1.74 1.43 3.12 3.60 1.74
3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74
3.53 0.05 1.12 0.46 1.74 1.43 3.12 3.60 1.74
3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
4.267
3.63
ns
ns
12 mA
16 mA
Notes:
STD
-1
1.427
1.428
1.427
1.428
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.64 10.82 0.05 1.12 0.46 11.02 9.42 1.26 1.20 11.02 9.419
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
9.21 0.04 0.95 0.39 9.38 8.01 1.26 1.20 9.38
7.49 0.05 1.12 0.46 7.63 6.58 1.43 1.48 7.63
6.37 0.04 0.95 0.39 6.49 5.60 1.43 1.49 6.49
7.49 0.05 1.12 0.46 7.63 6.58 1.43 1.48 7.63
6.37 0.04 0.95 0.39 6.49 5.60 1.43 1.49 6.49
5.64 0.05 1.12 0.46 5.75 5.04 1.54 1.67 5.75
4.80 0.04 0.95 0.39 4.89 4.29 1.54 1.67 4.89
5.64 0.05 1.12 0.46 5.75 5.04 1.54 1.67 5.75
4.80 0.04 0.95 0.39 4.89 4.29 1.54 1.67 4.89
8.012
6.58
ns
STD
-1
ns
5.598
6.58
ns
STD
-1
ns
5.598
5.042
4.289
5.042
4.289
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-30
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
9.55
8.12
6.82
5.80
6.82
5.80
2.70
2.71
2.57
2.57
2.33
2.33
Units
ns
4 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
8.28 0.05 1.10 0.45 8.44 7.13 1.42 1.37 10.85
7.05 0.04 0.94 0.38 7.18 6.06 1.42 1.37 9.23
5.31 0.05 1.10 0.45 5.41 4.40 1.60 1.68 7.83
4.52 0.04 0.94 0.38 4.60 3.74 1.60 1.68 6.66
5.31 0.05 1.10 0.45 5.41 4.40 1.60 1.68 7.83
4.52 0.04 0.94 0.38 4.60 3.74 1.60 1.68 6.66
3.82 0.05 1.10 0.45 3.89 1.51 3.47 1.88 6.31
3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37
3.60 0.05 1.10 0.45 1.78 1.37 3.53 3.98 2.95
3.07 0.04 0.94 0.38 1.78 1.37 3.00 3.38 2.95
3.33 0.05 1.10 0.45 1.64 1.13 3.60 4.39 2.81
2.83 0.04 0.94 0.38 1.64 1.13 3.06 3.74 2.82
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-40 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
4 mA
STD
-1
0.63 11.09 0.05 1.10 0.45 11.30 9.63 1.41 1.29 13.72 12.04
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
9.44 0.04 0.94 0.38 9.61 8.19 1.41 1.29 11.67 10.25
ns
6 mA
STD
-1
7.87 0.05 1.10 0.45 8.02 6.80 1.59 1.59 10.43
6.69 0.04 0.94 0.38 6.82 5.78 1.59 1.60 8.88
7.87 0.05 1.10 0.45 8.02 6.80 1.59 1.59 10.43
6.69 0.04 0.94 0.38 6.82 5.78 1.59 1.60 8.88
6.04 0.05 1.10 0.45 6.15 5.27 1.71 1.79 8.57
5.14 0.04 0.94 0.38 5.23 4.48 1.71 1.79 7.29
5.63 0.05 1.10 0.45 5.74 4.94 1.74 1.84 8.16
4.79 0.04 0.94 0.38 4.88 4.20 1.74 1.84 6.94
5.25 0.05 1.10 0.45 5.34 4.92 1.77 2.04 7.76
4.46 0.04 0.94 0.38 4.55 4.18 1.77 2.04 6.60
9.22
7.84
9.22
7.84
7.69
6.54
7.36
6.26
7.34
6.24
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-31
Automotive ProASIC3 Flash Family FPGAs
Table 3-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
6.80
5.98
4.13
3.63
4.13
3.63
1.38
1.43
1.38
1.43
Units
ns
4 mA
STD
-1
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
7.79 0.05 1.08 0.45 7.94 6.80 1.22 1.23 7.94
6.85 0.04 0.95 0.39 6.98 5.98 1.26 1.27 6.98
4.87 0.05 1.08 0.45 4.96 4.13 1.38 1.51 4.96
4.28 0.04 0.95 0.39 4.36 3.63 1.42 1.56 4.36
4.87 0.05 1.08 0.45 4.96 4.13 1.38 1.51 4.96
4.28 0.04 0.95 0.39 4.36 3.63 1.42 1.56 4.36
3.42 0.05 1.08 0.45 1.69 1.38 3.02 3.48 1.69
3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74
3.42 0.05 1.08 0.45 1.69 1.38 3.02 3.48 1.69
3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74
ns
6 mA
STD
-1
ns
ns
8 mA
STD
-1
ns
ns
12 mA
16 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive Strength Speed Grade tDOUT
tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS
9.11
8.01
6.37
5.60
6.37
5.60
4.88
4.29
4.88
4.29
Units
ns
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.63 10.47 0.05 1.08 0.45 10.66 9.11 1.22 1.16 10.66
0.55
0.63
0.55
0.63
0.55
0.63
0.55
0.63
0.55
9.21 0.04 0.95 0.39 9.38 8.01 1.26 1.20 9.38
7.25 0.05 1.08 0.45 7.38 6.37 1.38 1.44 7.38
6.37 0.04 0.95 0.39 6.49 5.60 1.43 1.49 6.49
7.25 0.05 1.08 0.45 7.38 6.37 1.38 1.44 7.38
6.37 0.04 0.95 0.39 6.49 5.60 1.43 1.49 6.49
5.46 0.05 1.08 0.45 5.56 4.88 1.49 1.61 5.56
4.80 0.04 0.95 0.39 4.89 4.29 1.54 1.67 4.89
5.46 0.05 1.08 0.45 5.56 4.88 1.49 1.61 5.56
4.80 0.04 0.95 0.39 4.89 4.29 1.54 1.67 4.89
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-32
v2.0
Automotive ProASIC3 Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V
applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 3-43 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max.,
mA1
Max.,
mA1
Min., V Max., V Min., V Max., V Max., V
Min., V mA mA
µA2 µA2
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
2
18
37
16
32
10
10
10
10
10
10
10
10
10
10
6 mA
6
6
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
74
65
87
83
124
169
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 3-44 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max.,
mA1
Max.,
mA1
Min., V Max., V Min., V Max., V Max., V
Min., V mA mA
µA2 µA2
2 mA
–0.3
–0.3
–0.3
0.7
0.7
0.7
1.7
1.7
1.7
3.6
3.6
3.6
0.7
0.7
0.7
1.7
1.7
1.7
2
2
18
37
74
16
32
65
10
10
10
10
10
10
6 mA
6
6
12 mA
Notes:
12
12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
35 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 3-8 • AC Loading
Table 3-45 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
2.5
1.2
35
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
v2.0
3-33
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-46 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
9.69
8.24
5.78
4.91
3.98
3.39
3.75
3.19
3.45
2.94
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
8.76
7.45
5.63
4.79
4.05
3.45
1.85
1.85
1.70
1.71
9.69
8.24
5.78
4.91
3.84
3.27
1.69
1.69
1.35
1.35
1.48
1.48
1.68
1.69
1.82
1.83
3.76
3.20
3.84
3.27
1.25
1.25
1.62
1.63
1.86
1.86
3.97
3.38
4.47
3.80
11.26 12.187
9.58
8.13
6.92
6.55
5.58
3.06
3.06
2.92
2.92
10.367
8.277
7.04
ns
6 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
6.338
5.392
2.926
2.929
2.585
2.586
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-47 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
12.12
10.31
8.24
7.01
6.91
5.88
6.44
5.48
6.16
5.24
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
12.54
10.67
9.07
7.71
7.04
5.99
6.56
5.58
6.15
5.23
tZH
12.74
10.84
8.74
7.43
6.62
5.63
6.18
5.26
6.16
5.24
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.48
1.48
1.68
1.69
1.82
1.83
1.86
1.86
1.90
1.90
1.19
1.20
1.57
1.57
1.80
1.80
1.86
1.86
2.10
2.10
15.04 15.243
12.80 12.966
11.57 11.237
ns
6 mA
STD
-1
ns
9.84
9.54
8.11
9.06
7.71
8.65
7.36
9.559
9.117
7.756
8.678
7.382
8.657
7.364
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-34
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-48 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
9.26
7.87
5.43
4.62
3.59
3.05
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
8.28
7.05
5.19
4.42
3.65
3.11
9.26
7.87
5.43
4.62
3.51
2.99
1.24
1.24
1.43
1.43
1.56
1.56
1.12
1.13
1.47
1.47
1.69
1.69
10.78 11.756
9.17
7.69
6.55
6.15
5.23
10
ns
6 mA
STD
-1
7.926
6.743
6.012
5.114
ns
ns
12 mA
Notes:
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-49 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
12.12
10.31
8.24
7.01
6.30
5.35
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
tZL
11.89
10.12
8.39
7.14
6.41
5.45
tZH
12.12
10.31
8.23
7.00
6.16
5.24
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.25
1.25
1.43
1.43
1.56
1.56
1.08
1.08
1.42
1.42
1.63
1.63
14.39 14.622
12.24 12.438
ns
6 mA
STD
-1
10.89
9.26
8.91
7.58
10.73
9.128
8.656
7.364
ns
ns
12 mA
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-35
Automotive ProASIC3 Flash Family FPGAs
Table 3-50 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
10.89
9.27
7.87
6.69
6.34
5.39
2.96
2.96
2.82
2.82
tZHS
11.79
10.03
8.01
6.81
6.13
5.22
2.83
2.83
2.50
2.50
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
9.37
7.97
5.59
4.75
3.85
3.28
3.63
3.08
3.34
2.84
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
8.47
7.21
5.45
4.63
3.92
3.34
1.79
1.79
1.65
1.65
9.37
7.97
5.59
4.75
3.71
3.16
1.64
1.64
1.31
1.31
1.43
1.43
1.63
1.63
1.77
1.77
3.64
3.09
3.72
3.16
1.21
1.21
1.57
1.57
1.80
1.80
3.84
3.27
4.32
3.68
ns
6 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
Notes:
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-51 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
11.73
9.98
7.97
6.78
6.68
5.69
6.24
5.30
5.96
5.07
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
12.14
10.32
8.77
7.46
6.81
5.79
6.35
5.40
5.95
5.06
tZH
12.33
10.49
8.45
7.19
6.40
5.45
5.98
5.08
5.96
5.07
tLZ
tHZ
tZLS
14.55
12.38
11.19
9.52
9.23
7.85
8.77
7.46
8.37
7.12
tZHS
14.75
12.55
10.87
9.25
8.82
7.50
8.40
7.14
8.38
7.12
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.43
1.43
1.63
1.63
1.77
1.77
1.80
1.80
1.84
1.84
1.16
1.16
1.51
1.52
1.74
1.74
1.80
1.80
2.03
2.03
ns
6 mA
STD
-1
ns
ns
12 mA
16 mA
24 mA
STD
-1
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-36
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-52 • 2.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
8.95
7.62
5.25
4.47
3.47
2.95
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
10.43
8.87
7.44
6.33
5.95
5.06
tZHS
11.37
9.68
7.67
6.52
5.82
4.95
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
8.01
6.82
5.03
4.27
3.53
3.01
8.95
7.62
5.25
4.47
3.40
2.89
1.20
1.20
1.38
1.38
1.51
1.51
1.09
1.09
1.42
1.42
1.63
1.63
ns
6 mA
STD
-1
ns
ns
12 mA
Notes:
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-53 • 2.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Streng Speed
th
Grade tDOUT
tDP
11.73
9.98
7.97
6.78
6.09
5.18
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
tZL
11.51
9.79
8.12
6.91
6.20
5.28
tZH
11.73
9.98
7.96
6.77
5.96
5.07
tLZ
tHZ
tZLS
13.93
11.85
10.54
8.96
tZHS
14.15
12.03
10.38
8.83
Units
ns
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
1.21
1.21
1.38
1.39
1.51
1.51
1.04
1.04
1.37
1.37
1.58
1.58
ns
6 mA
STD
-1
ns
ns
12 mA
STD
-1
8.62
8.38
ns
7.33
7.12
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-37
Automotive ProASIC3 Flash Family FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V
applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 3-54 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max., Max.,
Min., V
Max., V
Min., V
Max., V
Max., V
Min., V
mA mA mA1 mA1 µA2 µA2
2 mA
–0.3
0.35 *
VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
2
11
22
44
51
74
74
9
10
10
10
10
10
10
10
10
10
10
10
10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.35 *
VCCI
3.6
3.6
3.6
3.6
3.6
0.45
0.45
0.45
0.45
0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
4
4
17
35
45
91
91
6 mA
0.35 *
VCCI
6
6
8 mA
0.35 *
VCCI
8
8
12
16
12 mA
16 mA
Notes:
0.35 *
VCCI
VCCI –0.45 12
VCCI – 0.45 16
0.35 *
VCCI
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 3-55 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max., Max.,
Min., V Max., V
Min., V
Max., V
Max., V
Min., V mA mA
mA1
mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3
–0.3
–0.3
–0.3
0.35 * 0.65 * VCCI
VCCI
3.6
0.45
VCCI –0.45
VCCI –0.45
VCCI –0.45
VCCI –0.45
2
4
2
4
11
9
10
10
10
10
10
10
10
10
0.35 * 0.65 * VCCI
VCCI
3.6
3.6
3.6
0.45
0.45
0.45
22
44
44
17
35
35
0.35 * 0.65 * VCCI
VCCI
6
6
0.35 * 0.65 * VCCI
VCCI
8
8
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
3-38
v2.0
Automotive ProASIC3 Flash Family FPGAs
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 3-9 • AC Loading
Table 3-56 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
1.8
0.9
35
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
v2.0
3-39
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-57 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
13.26
11.28
7.73
6.58
4.97
4.23
4.39
3.73
3.95
3.36
3.95
3.36
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
10.22
8.69
6.55
5.58
4.67
3.98
4.39
3.74
1.95
1.95
1.95
1.95
tZH
13.26
11.28
7.73
6.58
4.97
4.23
4.39
3.73
1.68
1.68
1.68
1.68
tLZ
tHZ
tZLS
tZHS Units
2 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.36
1.16
1.36
1.16
1.36
1.16
1.36
1.16
1.36
1.16
1.36
1.16
1.53
1.53
1.78
1.78
1.95
1.95
1.99
1.99
4.14
3.52
4.14
3.52
0.90
0.90
1.54
1.54
1.83
1.83
1.91
1.91
4.56
3.88
4.56
3.88
12.72 15.764
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.82
9.05
7.70
7.17
6.10
6.89
5.86
3.16
3.16
3.16
3.16
13.41
10.232
8.704
7.472
6.356
6.888
5.859
2.915
2.918
2.915
2.918
4 mA
STD
-1
6 mA
STD
-1
8 mA
STD
-1
12 mA
16 mA
Notes:
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-58 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
17.36
14.77
11.71
9.96
9.00
7.66
8.39
7.14
8.15
6.94
8.15
6.94
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
15.78
13.42
11.64
9.90
9.17
7.80
8.54
7.27
8.09
6.88
8.09
6.88
tZH
17.36
14.77
11.71
9.96
8.77
7.46
8.16
6.94
8.15
6.94
8.15
6.94
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.53
1.54
1.78
1.78
1.95
1.95
1.99
1.99
2.05
2.05
2.05
2.05
0.87
0.87
1.48
1.48
1.77
1.77
1.85
1.85
2.14
2.14
2.14
2.14
18.28 19.864
15.55 16.897
14.14 14.214
12.03 12.091
11.67 11.267
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
9.92
11.04
9.40
9.585
10.66
9.068
STD
-1
STD
-1
10.59 10.654
9.01 9.063
10.59 10.654
9.01 9.063
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-40
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-59 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
13.26
11.28
7.73
6.58
4.97
4.23
4.39
3.73
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
12.67
10.78
7.25
6.17
4.54
3.86
4.54
3.86
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.36
1.16
1.36
1.16
1.36
1.16
1.36
1.16
9.75
8.30
6.13
5.21
4.29
3.65
4.29
3.65
1.24
1.24
1.46
1.46
1.62
1.62
1.62
1.62
0.82
0.83
1.41
1.41
1.68
1.68
1.68
1.68
12.26
15.17
10.43 12.905
ns
STD
-1
8.63
7.34
6.79
5.78
6.79
5.78
9.749
8.293
7.039
5.987
7.039
5.987
ns
ns
STD
-1
ns
ns
STD
-1
ns
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-60 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
17.36
14.77
11.71
9.96
9.00
7.66
8.39
7.14
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
15.09
12.84
10.88
9.26
8.47
7.21
8.47
7.21
tZH
16.55
14.08
11.07
9.41
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.24
1.24
1.47
1.47
1.62
1.62
1.62
1.62
0.79
0.79
1.35
1.35
1.62
1.62
1.62
1.62
17.59 19.052
14.96 16.207
13.38 13.567
11.38 11.541
10.97 10.685
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
8.18
6.96
9.33
10.97 10.685
9.33 9.089
9.089
STD
-1
8.18
6.96
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-41
Automotive ProASIC3 Flash Family FPGAs
Table 3-61 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
12.83
10.92
7.48
6.36
4.81
4.09
4.25
3.61
3.82
3.25
3.82
3.25
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
12.83
10.92
7.48
6.36
4.81
4.09
4.25
3.61
1.63
1.63
1.63
1.63
tLZ
tHZ
tZLS
12.30
10.46
8.76
7.45
6.94
5.90
6.67
5.67
3.06
3.06
3.06
3.06
tZHS Units
2 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.32
1.12
1.32
1.12
1.32
1.12
1.32
1.12
1.32
1.12
1.32
1.12
9.88
8.41
6.34
5.39
4.52
3.85
4.25
3.61
1.89
1.89
1.89
1.89
1.48
1.48
1.72
1.72
1.89
1.89
1.92
1.93
4.00
3.41
4.00
3.41
0.87
0.87
1.49
1.49
1.77
1.77
1.85
1.85
4.41
3.75
4.41
3.75
15.25
12.97
9.90
8.42
7.23
6.15
6.66
5.67
2.82
2.82
2.82
2.82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
STD
-1
6 mA
STD
-1
8 mA
STD
-1
12 mA
16 mA
Notes:
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-62 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
16.80
14.29
11.33
9.64
8.71
7.41
8.12
6.90
7.89
6.71
7.89
6.71
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
15.27
12.99
11.26
9.58
8.87
7.54
8.27
7.03
7.83
6.66
7.83
6.66
tZH
16.80
14.29
11.33
9.64
8.48
7.22
7.89
6.72
7.89
6.71
7.89
6.71
tLZ
tHZ
tZLS
17.69
15.05
13.68
11.64
11.29
9.60
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.48
1.49
1.73
1.73
1.89
1.89
1.93
1.93
1.98
1.98
1.98
1.98
0.84
0.84
1.43
1.43
1.72
1.72
1.79
1.79
2.07
2.07
2.07
2.07
19.22
16.35
13.75
11.70
10.90
9.27
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
STD
-1
10.69
9.09
10.31
8.77
STD
-1
10.25
8.72
10.31
8.77
STD
-1
10.25
8.72
10.31
8.77
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-42
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-63 • 1.8 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
12.83
10.92
7.48
6.36
4.81
4.09
4.25
3.61
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
12.26
10.43
7.01
5.97
4.39
3.74
4.39
3.74
tLZ
tHZ
0.80
0.80
1.36
1.37
1.63
1.63
1.63
1.63
tZLS
11.86
10.09
8.35
7.10
6.57
5.59
6.57
5.59
tZHS Units
2 mA
4 mA
6 mA
8 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.32
1.12
1.32
1.12
1.32
1.12
1.32
1.12
9.44
8.03
5.93
5.04
4.15
3.53
4.15
3.53
1.20
1.20
1.41
1.42
1.57
1.57
1.57
1.57
14.68
12.49
9.43
8.02
6.81
5.79
6.81
5.79
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-64 • 1.8 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
16.80
14.29
11.33
9.64
8.71
7.41
8.12
6.90
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
14.60
12.42
10.53
8.96
8.19
tZH
16.01
13.62
10.71
9.11
7.92
6.74
7.92
6.74
tLZ
tHZ
tZLS
17.02
14.48
12.95
11.01
10.61
9.03
tZHS Units
2 mA
4 mA
6 mA
8 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.20
1.20
1.42
1.42
1.57
1.57
1.57
1.57
0.77
0.77
1.31
1.31
1.57
1.57
1.57
1.57
18.43
15.68
13.13
11.17
10.34
8.79
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
6.97
8.19
STD
-1
10.61
9.03
10.34
8.79
6.97
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-43
Automotive ProASIC3 Flash Family FPGAs
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V
applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 3-65 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Max.,
mA1
Max.,
mA1
Strength Min., V Max., V Min., V Max., V Max., V
Min., V
mA mA
µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
3.6
3.6
3.6
3.6
3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
2
4
16
33
39
55
55
13
25
32
66
66
10
10
10
10
10
10
10
10
10
10
6
6
8
8
0.25 * VCCI 0.75 * VCCI 12
12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
Table 3-66 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Max.,
mA1
Max.,
mA1
Min., V Max., V Min., V Max., V Max., V
Min., V mA mA
µA2 µA2
2 mA
4 mA
Notes:
–0.3
–0.3
0.30 * VCCI 0.7 * VCCI
0.30 * VCCI 0.7 * VCCI
3.6
3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
2
4
0
0
0
0
10
10
10
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 3-10 • AC Loading
Table 3-67 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
1.5
0.75
35
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
3-44
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-68 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
9.35
7.95
5.94
5.05
5.22
4.44
4.56
3.88
4.56
3.88
1.61
1.37
1.61
1.37
1.61
1.37
1.61
1.37
1.61
1.37
7.63
6.49
5.42
4.61
5.09
4.33
2.25
2.25
2.25
2.25
9.35
7.95
5.94
5.05
5.22
4.44
1.98
1.98
1.98
1.98
1.87
1.87
2.07
2.07
2.11
2.11
4.41
3.75
4.41
3.75
1.50
1.50
1.84
1.85
1.93
1.93
4.70
4.00
4.70
4.00
10.13 11.851
8.62 10.081
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
7.92
6.74
7.59
6.45
3.46
3.46
3.46
3.46
8.442
7.181
7.718
6.566
3.211
3.213
3.211
3.213
STD
-1
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-69 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
14.29
12.16
11.19
9.52
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
0.46
0.39
tZL
tZH
14.29
12.16
10.67
9.08
9.94
8.46
9.94
8.46
9.94
8.46
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
STD
-1
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
0.64
0.55
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
1.45
1.23
14.32
12.18
11.40
9.70
1.88
1.88
2.07
2.07
2.12
2.12
2.18
2.19
2.18
2.19
1.43
1.43
1.77
1.77
1.86
1.86
2.19
2.20
2.19
2.20
16.82 16.794
14.31 14.286
13.90 13.175
11.82 11.207
13.13 12.442
11.17 10.584
12.65 12.445
10.76 10.586
12.65 12.445
10.76 10.586
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
10.44
8.88
10.63
9.04
STD
-1
9.96
10.15
8.63
8.47
STD
-1
9.96
10.15
8.63
8.47
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-45
Automotive ProASIC3 Flash Family FPGAs
Table 3-70 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
8.76
7.45
5.41
4.60
tDIN
0.05
0.04
0.05
0.04
tPY
1.59
1.35
1.59
1.35
tEOUT
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
1.50
1.50
1.84
1.85
tZLS
tZHS Units
2 mA
4 mA
Notes:
STD
-1
0.64
0.55
0.64
0.55
7.63
6.49
5.42
4.61
9.35
7.95
5.94
5.05
1.87
1.87
2.07
2.07
10.13 11.851
ns
ns
ns
ns
8.62
7.92
6.74
10.081
8.442
7.181
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-71 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
tDIN
0.05
0.04
0.05
0.04
tPY
1.45
1.23
1.45
1.23
tEOUT
0.46
0.39
0.46
0.39
tZL
tZH
tLZ
tHZ
1.43
1.43
1.77
1.77
tZLS
tZHS Units
2 mA
4 mA
STD
-1
0.64
0.55
0.64
0.55
13.51
11.49
10.38
8.83
14.32
12.18
11.40
9.70
14.29
12.16
10.67
9.08
1.88
1.88
2.07
2.07
16.82 16.794
14.31 14.286
13.90 13.175
11.82 11.207
ns
ns
ns
ns
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-46
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-72 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
9.05
7.70
5.75
4.89
5.05
4.29
4.41
3.75
4.41
3.75
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
tZLS
9.80
8.34
7.67
6.52
7.34
6.24
3.35
3.35
3.35
3.35
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.56
1.32
1.56
1.32
1.56
1.32
1.56
1.32
1.56
1.32
7.38
6.28
5.25
4.46
4.92
4.19
2.18
2.18
2.18
2.18
9.05
7.70
5.75
4.89
5.05
4.29
1.91
1.91
1.91
1.91
1.81
1.81
2.00
2.00
2.04
2.04
4.27
3.63
4.27
3.63
1.45
1.45
1.78
1.78
1.87
1.87
4.55
3.87
4.55
3.87
11.47
9.75
8.17
6.95
7.47
6.35
3.11
3.11
3.11
3.11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
STD
-1
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-73 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
13.83
11.76
10.83
9.21
tDIN
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
0.05
0.04
tPY
tEOUT
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
0.45
0.38
tZL
tZH
13.83
11.76
10.33
8.79
9.62
8.18
9.62
8.18
9.62
8.18
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
STD
-1
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
0.63
0.53
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
1.40
1.19
13.86
11.79
11.03
9.38
1.82
1.82
2.00
2.01
2.05
2.05
2.11
2.11
2.11
2.11
1.39
1.39
1.71
1.72
1.80
1.80
2.12
2.12
2.12
2.12
16.28
13.85
13.45
11.44
12.70
10.81
12.23
10.41
12.23
10.41
16.25
13.82
12.75
10.84
12.04
10.24
12.04
10.24
12.04
10.24
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STD
-1
STD
-1
10.10
8.59
10.28
8.75
STD
-1
9.64
9.82
8.20
8.35
STD
-1
9.64
9.82
8.20
8.35
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-47
Automotive ProASIC3 Flash Family FPGAs
Table 3-74 • 1.5 V LVCMOS High Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
8.47
7.21
5.24
4.45
tDIN
0.05
0.04
0.05
0.04
tPY
1.54
1.31
1.54
1.31
tEOUT
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
1.45
1.45
1.78
1.78
tZLS
9.80
8.34
7.67
6.52
tZHS Units
2 mA
4 mA
Notes:
STD
-1
0.63
0.53
0.63
0.53
7.38
6.28
5.25
4.46
9.05
7.70
5.75
4.89
1.81
1.81
2.00
2.00
11.47
9.75
8.17
6.95
ns
ns
ns
ns
STD
-1
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-75 • 1.5 V LVCMOS Low Slew
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength Grade tDOUT
tDP
tDIN
0.05
0.04
0.05
0.04
tPY
1.40
1.19
1.40
1.19
tEOUT
0.45
0.38
0.45
0.38
tZL
tZH
tLZ
tHZ
1.39
1.39
1.71
1.72
tZLS
tZHS Units
2 mA
4 mA
STD
-1
0.63
0.53
0.63
0.53
13.07
11.12
10.04
8.54
13.86
11.79
11.03
9.38
13.83
11.76
10.33
8.79
1.82
1.82
2.00
2.01
16.28
13.85
13.45
11.44
16.25
13.82
12.75
10.84
ns
ns
ns
ns
STD
-1
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-48
v2.0
Automotive ProASIC3 Flash Family FPGAs
3.3 V PCI, 3.3 V PCI-X
The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
Table 3-76 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
Drive Strength
Per PCI specification
Notes:
VIL
Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
Per PCI curves 10 10
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 125°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path
characterization are described in Figure 3-11.
R to VCCI for tDP (F)
R to GND for tDP (R)
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH /tZHS/tZL/tZLS
5 pF for tHZ /tLZ
Figure 3-11 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 3-77.
Table 3-77 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
C
LOAD (pF)
0
3.3
10
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
v2.0
3-49
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-78 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.64
tDP
2.58
2.19
tDIN
0.05
0.04
tPY
0.95
0.81
tEOUT
0.46
tZL
tZH
0.94
0.94
tLZ
tHZ
3.60
3.06
tZLS
2.49
2.49
tZHS
2.18
2.18
Units
ns
Std.
–1
1.27
1.27
3.12
2.65
0.55
0.39
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-79 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
0.64
tDP
3.00
2.55
tDIN
0.05
0.04
tPY
0.93
0.79
tEOUT
0.46
tZL
tZH
0.94
0.94
tLZ
tHZ
3.60
3.06
tZLS
2.49
2.49
tZHS
2.18
2.18
Units
ns
Std.
–1
1.27
1.27
3.12
2.65
0.55
0.39
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-80 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
0.628
0.53
tDP
2.50
2.12
tDIN
0.05
0.04
tPY
0.92
0.78
tEOUT
0.45
tZL
tZH
0.91
0.91
tLZ
tHZ
3.48
2.96
tZLS
2.40
2.41
tZHS
2.11
2.11
Units
ns
Std.
–1
1.23
1.23
3.02
2.57
0.38
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-81 • 3.3 V PCI/PCI-X
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
0.628
0.53
tDP
2.90
2.47
tDIN
0.05
0.04
tPY
0.90
0.77
tEOUT
0.45
tZL
tZH
0.91
0.91
tLZ
tHZ
3.48
2.96
tZLS
2.40
2.41
tZHS
2.11
2.11
Units
ns
Std.
–1
1.23
1.23
3.02
2.57
0.38
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-50
v2.0
Automotive ProASIC3 Flash Family FPGAs
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is
handled by Actel Designer software when the user
instantiates a differential I/O macro in the design.
pins are needed. It also requires external resistor
termination.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-12. The
building blocks of the LVDS transmitter-receiver are one
transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVPECL implementation
because the output standard specifications are different.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
(OutReg), Enable Register (EnReg), and Double Data
Rate (DDR). However, there is no support for
bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Along with LVDS I/O, ProASIC3 also supports Bus LVDS
structure and Multipoint LVDS (M-LVDS) configuration
(up to 40 nodes).
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is
a high-speed, differential I/O standard. It requires that
one data bit be carried through two signal lines, so two
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
165 Ω
165 Ω
Z0 = 50 Ω
140 Ω
Z0 = 50 Ω
INBUF_LVDS
+
–
100 Ω
N
N
Figure 3-12 • LVDS Circuit Diagram and Board-Level Implementation
Table 3-82 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
Max.
Units
2.5
1.075
1.425
–
2.625
1.25
1.6
V
V
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
1.25
0
V
VI
Input Voltage
2.925
450
V
VODIFF
VOCM
VICM
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
250
350
1.25
1.25
350
mV
V
1.125
0.05
100
1.375
2.35
–
V
VIDIFF
mV
Notes:
1.
5%
2. Differential input voltage = 350 mV
Table 3-83 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
1.075
1.325
Cross point
Note: *Measuring point = Vtrip. See Table 3-5 on page 3-5 for a complete table of trip points.
v2.0
3-51
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-84 • LVDS
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
0.64
tDP
2.05
1.74
tDIN
0.05
0.04
tPY
1.79
1.52
Units
ns
Std.
–1
0.55
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-85 • LVDS
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
0.63
tDP
1.98
1.68
tDIN
0.05
0.04
tPY
1.73
1.47
Units
ns
Std.
–1
0.53
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
BLVDS/M-LVDS
Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS)
specifications extend the existing LVDS standard to high-
performance multipoint bus applications. Multidrop and
multipoint bus configurations may contain any
combination of drivers, receivers, and transceivers. Actel
LVDS drivers provide the higher drive current required by
BLVDS and M-LVDS to accommodate the loading. The
drivers require series terminations for better signal quality
and to control voltage swing. Termination is also required
at both ends of the bus since the driver can be located
anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS
macros along with appropriate terminations. Multipoint
designs using Actel LVDS macros can achieve up to
200 MHz with a maximum of 20 loads. A sample
application is given in Figure 3-13. The input and output
buffer delays are available in the LVDS section in Table 3-
84.
Example: For a bus consisting of 20 equidistant loads, the
following terminations provide the required differential
voltage, in worst-case Industrial operating conditions, at
the farthest receiver: RS = 60 Ω and RT = 70 Ω, given
Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 3-13 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
3-52
v2.0
Automotive ProASIC3 Flash Family FPGAs
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-14. The
building blocks of the LVPECL transmitter-receiver are
one transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVDS implementation
because the output standard specifications are different.
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is
another differential I/O standard. It requires that one
data bit be carried through two signal lines. Like LVDS,
two pins are needed. It also requires external resistor
termination.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
OUTBUF_LVPECL
100 Ω
100 Ω
Z0 = 50 Ω
187 W
Z0 = 50 Ω
INBUF_LVPECL
+
–
100 Ω
N
N
Figure 3-14 • LVPECL Circuit Diagram and Board-Level Implementation
Table 3-86 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max.
Units
3.0
3.3
3.6
V
V
VOL
Output LOW Voltage
0.96
1.8
1.27
2.11
3.3
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.9
VOH
Output HIGH Voltage
V
VIL, VIH
VODIFF
VOCM
Input LOW, Input HIGH Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
0
V
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
V
V
VICM
V
VIDIFF
mV
Table 3-87 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
1.64
1.94
Cross point
Note: *Measuring point = Vtrip. See Table 3-18 on page 3-19 for a complete table of trip points.
Timing Characteristics
Table 3-88 • LVPECL
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.64
tDP
2.01
1.71
tDIN
0.05
0.04
tPY
1.57
1.34
Units
Std.
–1
ns
ns
0.55
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-89 • LVPECL
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.63
tDP
1.95
1.66
tDIN
0.05
0.04
tPY
1.52
1.29
Units
ns
Std.
–1
0.53
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-53
Automotive ProASIC3 Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Preset
L
D
DOUT
EOUT
Data_out
PRE
DFN1E1P1
F
PRE
DFN1E1P1
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
G
E
E
B
H
I
A
PRE
DFN1E1P1
J
D
Q
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
CLKBUF
INBUF
INBUF
Figure 3-15 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
3-54
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-90 • Parameter Definition and Measuring Nodes
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (from, to)*
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
G, H
G, H
L, DOUT
L, H
tOHE
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
J, H
tOESUE
K, H
tOEHE
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
C, A
B, A
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 3-15 on page 3-54 for more information.
v2.0
3-55
Automotive ProASIC3 Flash Family FPGAs
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
CLR
LL
HH
AA
DD
JJ
D
Q
CLR
DFN1E1C1
KK
E
CLR
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
INBUF
INBUF
CLKBUF
Active High Clear
Positive-Edge Triggered
Figure 3-16 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
3-56
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-91 • Parameter Definitions and Measuring Nodes
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (from, to)*
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
KK, HH
KK, HH
II, EOUT
II, HH
tOEHE
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 3-16 on page 3-56 for more information.
v2.0
3-57
Automotive ProASIC3 Flash Family FPGAs
Input Register
tICKMPWH tICKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tIHD
tISUD
50%
50%
1
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 3-17 • Input Register Timing Diagram
3-58
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-92 • Input Data Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
–1
Std.
0.34
0.38
0.00
0.53
0.00
0.65
0.65
0.00
0.32
0.00
0.32
0.30
0.30
0.48
0.43
Units
ns
0.29
0.32
0.00
0.45
0.00
0.55
0.55
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tISUD
Data Setup Time for the Input Data Register
ns
tIHD
Data Hold Time for the Input Data Register
ns
tISUE
Enable Setup Time for the Input Data Register
ns
tIHE
Enable Hold Time for the Input Data Register
ns
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
ns
ns
ns
ns
ns
ns
ns
tIWPRE
ns
tICKMPWH
tICKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-93 • Input Data Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Clock-to-Q of the Input Data Register
–1
Std.
0.34
0.37
0.00
0.52
0.00
0.64
0.64
0.00
0.31
0.00
0.31
0.30
0.30
0.48
0.43
Units
ns
0.29
0.31
0.00
0.44
0.00
0.54
0.54
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tISUD
Data Setup Time for the Input Data Register
ns
tIHD
Data Hold Time for the Input Data Register
ns
tISUE
Enable Setup Time for the Input Data Register
ns
tIHE
Enable Hold Time for the Input Data Register
ns
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
ns
ns
ns
ns
ns
ns
ns
tIWPRE
ns
tICKMPWH
tICKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-59
Automotive ProASIC3 Flash Family FPGAs
Output Register
t
t
OCKMPWH OCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OSUD OHD
50%
50%
1
0
Data_out
t
OREMPRE
Enable
Preset
50%
t
t
ORECPRE
OWPRE
t
OHE
50%
50%
50%
t
OSUE
t
t
OREMCLR
t
ORECCLR
OWCLR
50%
50%
50%
Clear
t
OPRE2Q
50%
50%
50%
DOUT
t
OCLR2Q
t
OCLKQ
Figure 3-18 • Output Register Timing Diagram
3-60
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-94 • Output Data Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
–1
Std.
0.84
0.45
0.00
0.63
0.00
1.15
1.15
0.00
0.32
0.00
0.32
0.30
0.30
0.48
0.43
Units
ns
0.72
0.38
0.00
0.53
0.00
0.98
0.98
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tOSUD
Data Setup Time for the Output Data Register
ns
tOHD
Data Hold Time for the Output Data Register
ns
tOSUE
Enable Setup Time for the Output Data Register
ns
tOHE
Enable Hold Time for the Output Data Register
ns
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
ns
ns
ns
ns
ns
ns
ns
ns
tOCKMPWH
tOCKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-95 • Output Data Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Clock-to-Q of the Output Data Register
–1
Std.
0.82
0.44
0.00
0.61
0.00
1.12
1.12
0.00
0.31
0.00
0.31
0.30
0.30
0.48
0.43
Units
ns
0.70
0.37
0.00
0.52
0.00
0.96
0.96
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tOSUD
Data Setup Time for the Output Data Register
ns
tOHD
Data Hold Time for the Output Data Register
ns
tOSUE
Enable Setup Time for the Output Data Register
ns
tOHE
Enable Hold Time for the Output Data Register
ns
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
ns
ns
ns
ns
ns
ns
ns
ns
tOCKMPWH
tOCKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-61
Automotive ProASIC3 Flash Family FPGAs
Output Enable Register
t
t
OECKMPWH OECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OESUD OEHD
50%
50%
0
1
D_Enable
50%
t
Enable
Preset
t
t
OEWPRE
OEREMPRE
t
OERECPRE
50%
50%
50%
t
OESUE OEHE
t
t
t
OERECCLR
OEREMCLR
OEWCLR
50%
50%
50%
Clear
EOUT
t
t
OECLR2Q
OEPRE2Q
50%
50%
50%
t
OECLKQ
Figure 3-19 • Output Enable Register Timing Diagram
3-62
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-96 • Output Enable Register Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
Description
Clock-to-Q of the Output Enable Register
–1
Std.
0.64
0.45
0.00
0.62
0.00
0.95
0.95
0.00
0.32
0.00
0.32
0.30
0.30
0.48
0.43
Units
ns
0.54
0.38
0.00
0.53
0.00
0.81
0.81
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tOESUD
Data Setup Time for the Output Enable Register
ns
tOEHD
Data Hold Time for the Output Enable Register
ns
tOESUE
Enable Setup Time for the Output Enable Register
ns
tOEHE
Enable Hold Time for the Output Enable Register
ns
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
tOECKMPWH
tOECKMPWL
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width HIGH for the Output Enable Register
Clock Minimum Pulse Width LOW for the Output Enable Register
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-97 • Output Enable Register Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
Description
Clock-to-Q of the Output Enable Register
–1
Std.
0.62
0.44
0.00
0.61
0.00
0.93
0.93
0.00
0.31
0.00
0.31
0.30
0.30
0.48
0.43
Units
ns
0.53
0.37
0.00
0.52
0.00
0.79
0.79
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tOESUD
Data Setup Time for the Output Enable Register
ns
tOEHD
Data Hold Time for the Output Enable Register
ns
tOESUE
Enable Setup Time for the Output Enable Register
ns
tOEHE
Enable Hold Time for the Output Enable Register
ns
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
tOECKMPWH
tOECKMPWL
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width HIGH for the Output Enable Register
Clock Minimum Pulse Width LOW for the Output Enable Register
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-63
Automotive ProASIC3 Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 3-20 • Input DDR Timing Model
Table 3-98 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR Input
Data Hold Time of DDR Input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
3-64
v2.0
Automotive ProASIC3 Flash Family FPGAs
CLK
tDDRISUD
tDDRIHD
8
Data
CLR
1
2
3
4
5
6
7
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
2
4
tDDRICLKQ2
tDDRICLR2Q2
7
3
5
Figure 3-21 • Input DDR Timing Diagram
v2.0
3-65
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-99 • Input DDR Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Out Out_QR for Input DDR
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
–1
Std.
0.39
0.56
0.40
0.00
0.66
0.82
0.00
0.32
0.30
0.48
0.43
TBD
Units
ns
0.33
0.47
0.34
0.00
0.56
0.69
0.00
0.27
0.25
0.41
0.37
TBD
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-100 • Input DDR Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
Clock-to-Out Out_QR for Input DDR
–1
Std.
0.38
0.54
0.40
0.00
0.65
0.80
0.00
0.31
0.30
0.48
0.43
TBD
Units
ns
0.33
0.46
0.34
0.00
0.55
0.68
0.00
0.27
0.25
0.41
0.37
TBD
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-66
v2.0
Automotive ProASIC3 Flash Family FPGAs
Output DDR Module
Output DDR
A
Data_F
XX
(from core)
FF1
Out
B
C
0
1
CLK
X
X
X
E
CLKBUF
X
OUTBUF
D
Data_R
(from core)
FF2
B
C
X
X
CLR
INBUF
DDR_OUT
Figure 3-22 • Output DDR Timing Model
Table 3-101 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (from, to)
tDDROCLKQ
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
tDDROSUD2
tDDROHD1
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROHD2
v2.0
3-67
Automotive ProASIC3 Flash Family FPGAs
CLK
tDDROHD2
tDDROSUD2
3
4
9
5
Data_F
1
2
tDDROHD1
tDDROREMCLR
Data_R 6
CLR
7
8
10
tDDRORECCLR
11
tDDROREMCLR
tDDROCLR2Q
tDDROCLKQ
Out
7
2
8
3
9
4
10
Figure 3-23 • Output DDR Timing Diagram
3-68
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-102 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Out of DDR for Output DDR
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
–1
Std.
1.00
0.54
0.54
0.00
0.00
1.15
0.00
0.32
0.30
0.48
0.43
TBD
Units
ns
0.85
0.46
0.46
0.00
0.00
0.97
0.00
0.27
0.25
0.41
0.37
TBD
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-103 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
Clock-to-Out of DDR for Output DDR
–1
Std.
0.98
0.53
0.53
0.00
0.00
1.12
0.00
0.31
0.30
0.48
0.43
TBD
Units
ns
0.84
0.45
0.45
0.00
0.00
0.96
0.00
0.27
0.25
0.41
0.37
TBD
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-69
Automotive ProASIC3 Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are
presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library
Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 3-24 • Sample of Combinatorial Cells
3-70
v2.0
Automotive ProASIC3 Flash Family FPGAs
tPD
A
B
NAND2 or
Any Combinatorial
Logic
Y
tPD = MAX(tPD(RR), tPD(RF)
,
tPD(FF), tPD(FR)) where edges are
applicable for the particular
combinatorial cell
VCC
50%
50%
VCC
A, B, C
GND
50%
50%
OUT
OUT
GND
VCC
tPD
tPD
(RR)
(FF)
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 3-25 • Timing Model and Waveforms
v2.0
3-71
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-104 • Combinatorial Cell Propagation Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Y = !A
Parameter
–1
Std.
0.57
0.67
0.67
0.69
0.69
1.05
1.00
1.25
0.72
0.80
Units
ns
INV
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
0.49
0.57
0.57
0.59
0.59
0.90
0.85
1.06
0.62
0.68
AND2
NAND2
OR2
Y = A · B
ns
Y = !(A · B)
Y = A + B
ns
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A , B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-105 • Combinatorial Cell Propagation Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Y = !A
Parameter
–1
Std.
0.56
0.66
0.66
0.68
0.68
1.03
0.98
1.23
0.71
0.79
Units
ns
INV
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
0.48
0.56
0.56
0.58
0.58
0.88
0.83
1.04
0.60
0.67
AND2
NAND2
OR2
Y = A · B
ns
Y = !(A · B)
Y = A + B
ns
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A , B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-72
v2.0
Automotive ProASIC3 Flash Family FPGAs
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and
optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from
the library. For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
CLK
Out
Data
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLR
Figure 3-26 • Sample of Sequential Cells
v2.0
3-73
Automotive ProASIC3 Flash Family FPGAs
tCKMPWH CKMPWL
t
50%
50%
50%
50%
50%
50%
50%
CLK
tHD
tSUD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
50%
tREMPRE
50%
tHE
tSUE
PRE
CLR
Out
tREMCLR
50%
tRECCLR
50%
tWCLR
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 3-27 • Timing Model and Waveforms
3-74
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-106 • Register Delays
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–1
Std.
0.79
0.61
0.00
0.65
0.00
0.57
0.57
0.00
0.32
0.00
0.32
0.30
0.30
0.48
0.43
Units
ns
Clock-to-Q of the Core Register
0.67
0.52
0.00
0.55
0.00
0.49
0.49
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tSUD
Data Setup Time for the Core Register
ns
tHD
Data Hold Time for the Core Register
ns
tSUE
Enable Setup Time for the Core Register
ns
tHE
Enable Hold Time for the Core Register
ns
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
ns
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
ns
ns
ns
ns
ns
ns
tWPRE
ns
tCKMPWH
tCKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-107 • Register Delays
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–1
Std.
0.77
0.60
0.00
0.64
0.00
0.56
0.56
0.00
0.31
0.00
0.31
0.30
0.30
0.48
0.43
Units
ns
Clock-to-Q of the Core Register
0.66
0.51
0.00
0.54
0.00
0.48
0.48
0.00
0.27
0.00
0.27
0.25
0.25
0.41
0.37
tSUD
Data Setup Time for the Core Register
ns
tHD
Data Hold Time for the Core Register
ns
tSUE
Enable Setup Time for the Core Register
ns
tHE
Enable Hold Time for the Core Register
ns
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
ns
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
ns
ns
ns
ns
ns
ns
tWPRE
ns
tCKMPWH
tCKMPWL
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-75
Automotive ProASIC3 Flash Family FPGAs
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 3-28 is an example of a global tree used for clock routing. The global tree
presented in Figure 3-28 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-
flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 3-28 • Example of Global Tree Use in an A3P250 Device for Clock Routing
3-76
v2.0
Automotive ProASIC3 Flash Family FPGAs
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input
buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by
the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section
on page 2-13. Table 3-114 on page 3-80 to Table 3-124 on page 3-97 present minimum and maximum global clock
delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 3-108 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.87
Max.2
1.16
Min.1
1.02
Max.2
1.37
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.86
1.20
1.01
1.42
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.35
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-109 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.85
Max.2
1.13
Min.1
1.00
Max.2
1.33
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.84
1.18
0.99
1.38
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.34
0.40
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-77
Automotive ProASIC3 Flash Family FPGAs
Table 3-110 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.93
Max.2
1.22
Min.1
1.09
Max.2
1.43
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.92
1.26
1.08
1.49
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.35
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-111 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.90
Max.2
1.19
Min.1
1.06
Max.2
1.40
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.90
1.23
1.05
1.45
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.34
0.40
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-78
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-112 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.96
Max.2
1.25
Min.1
1.13
Max.2
1.47
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.94
1.28
1.10
1.51
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.35
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-113 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
0.94
Max.2
1.22
Min.1
1.10
Max.2
1.44
Units
ns
tRCKH
Input HIGH Delay for Global Clock
0.92
1.25
1.08
1.47
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.34
0.40
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-79
Automotive ProASIC3 Flash Family FPGAs
Table 3-114 • A3P1000 Global Resource
Automotive-Case Conditions: TJ = 135°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.17
Max.2
1.46
Min.1
1.37
Max.2
1.72
Units
ns
tRCKH
Input HIGH Delay for Global Clock
1.15
1.50
1.36
1.76
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.35
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
Table 3-115 • A3P1000 Global Resource
Automotive-Case Conditions: TJ = 115°C, VCC = 1.425 V
–1
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.14
Max.2
1.43
Min.1
1.34
Max.2
1.68
Units
ns
tRCKH
Input HIGH Delay for Global Clock
1.13
1.46
1.32
1.72
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.34
0.40
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-80
v2.0
Automotive ProASIC3 Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512x18
FIFO4K18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RW2
RW1
RW0
WW2
WW1
WW0
ESTOP
FSTOP
RD17
RD16
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
DINA7
RADDR0
RD0
RD0
FULL
AFULL
EMPTY
RW1
RW0
DINA0
AEVAL11
AEVAL10
AEMPTY
WIDTHA1
WIDTHA0
PIPEA
PIPE
AEVAL0
WMODEA
BLKA
WENA
AFVAL11
AFVAL10
REN
RCLK
CLKA
AFVAL0
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
REN
RBLK
RCLK
ADDRB0
DOUTB0
WADDR0
WD17
WD16
WD17
WD16
DINB8
DINB7
WD0
DINB0
WD0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WBLK
WCLK
RPIPE
WEN
WCLK
RESET
RESET
RESET
Figure 3-29 • RAM Models
v2.0
3-81
Automotive ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
tBKS
A1
A2
ADD
BLK_B
WEN_B
DO
tBKH
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 3-30 • RAM Read for Pass-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
tBKS
tBKH
BLK_B
WEN_B
DO
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 3-31 • RAM Read for Pipelined Output
3-82
v2.0
Automotive ProASIC3 Flash Family FPGAs
tCYC
tCKH
tAH
tCKL
CLK
tAS
A0
A1
A2
ADD
BLK_B
WEN_B
DI
tBKS
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 3-32 • RAM Write, Output Retained (WMODE = 0)
t
CYC
t
t
CKH
CKL
CLK
ADD
t
t
AH
AS
A
A
A
2
0
1
t
BKS
t
BKH
BLK_B
WEN_B
DI
t
ENS
t
t
DH
DS
DI
DI
DI
2
0
1
DO
D
DI
DI
1
n
0
(pass-through)
DO
DI
D
DI
1
0
n
(pipelined)
Figure 3-33 • RAM Write, Output as Write Data (WMODE = 1)
v2.0
3-83
Automotive ProASIC3 Flash Family FPGAs
CLK1
tAS tAH
ADD1
DI1
A0
tDS tDH
A1
D2
A3
D3
D1
tCCKH
CLK2
WEN_B1
WEN_B2
tAS tAH
A0
A0
D0
A4
D4
ADD2
DI2
tCKQ1
DO2
(pass-through)
Dn
Dn
D0
tCKQ2
DO2
(pipelined)
D0
Figure 3-34 • Write Access after Write to Same Address
3-84
v2.0
Automotive ProASIC3 Flash Family FPGAs
CLK1
tAS tAH
A0
tDS tDH
A2
D2
A3
D3
ADD1
D0
DI1
tWRO
CLK2
WEN_B1
WEN_B2
ADD2
tAS tAH
A1
A0
tCKQ1
A4
DO2
(pass-through)
Dn
D0
D1
tCKQ2
DO2
Dn
D0
(pipelined)
Figure 3-35 • Read Access after Write to Same Address
v2.0
3-85
Automotive ProASIC3 Flash Family FPGAs
CLK1
tAS
tAH
A0
A1
A0
ADD1
WEN_B1
tCKQ1
tCKQ1
DO1
(pass-through)
Dn
D0
tCKQ2
D1
DO1
(pipelined)
Dn
tCCKH
D0
CLK2
tAS
tAH
A1
ADD2
A0
D1
A3
D3
D2
DI2
WEN_B2
Figure 3-36 • Write Access after Read to Same Address
tCYC
tCKH
tCKL
CLK
RESET_B
DO
tRSTBQ
Dm
Dn
Figure 3-37 • RAM Reset
3-86
v2.0
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-116 • RAM4K9
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–1
Std.
0.36
0.00
0.20
0.14
0.33
0.03
0.26
0.00
2.55
3.37
1.28
TBD
Units
ns
Address Setup Time
0.30
0.00
0.17
0.12
0.28
0.02
0.22
0.00
2.17
2.86
1.09
TBD
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
ns
tENH
REN_B, WEN_B Hold Time
ns
tBKS
BLK_B Setup Time
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
ns
tDH
Input Data (DI) Hold time
ns
tCKQ1
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (flow-through, WMODE = 1)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
tCKQ2
tWRO
ns
Address Collision clk-to-clk Delay for reliable read access after write on same
address
ns
tCCKH
tRSTBQ
Address Collision clk-to-clk Delay for reliable write access after write/read on
same address
TBD
TBD
ns
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
1.12
1.12
0.35
1.82
0.26
3.93
255
1.32
1.32
0.41
2.14
0.30
4.62
217
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-87
Automotive ProASIC3 Flash Family FPGAs
Table 3-117 • RAM512X18
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–1
Std.
0.35
0.00
0.13
0.08
0.26
0.00
3.03
1.26
TBD
Units
ns
Address Setup Time
0.30
0.00
0.11
0.07
0.22
0.00
2.58
1.07
TBD
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
Input data (DI) Setup Time
Input data (DI) Hold Time
ns
tENH
ns
tDS
ns
tDH
ns
tCKQ1
tCKQ2
tWRO
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
Address Collision clk-to-clk Delay for reliable read access after write on same
address
ns
tCCKH
tRSTBQ
Address Collision clk-to-clk Delay for reliable write access after write/read on
same address
TBD
TBD
ns
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
1.10
1.10
0.34
1.79
0.25
3.85
260
1.29
1.29
0.40
2.10
0.30
4.53
221
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-88
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-118 • RAM4K9
Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Parameter Description
–1
Std.
0.35
0.00
0.20
0.14
0.33
0.03
0.26
0.00
2.50
3.30
1.25
TBD
Units
ns
tAS
Address Setup Time
0.30
0.00
0.17
0.12
0.28
0.02
0.22
0.00
2.13
2.81
1.07
TBD
TBD
tAH
Address Hold Time
ns
tENS
tENH
tBKS
tBKH
tDS
REN_B, WEN_B Setup Time
ns
REN_B, WEN_B Hold Time
ns
BLK_B Setup Time
ns
BLK_B Hold Time
ns
Input data (DI) Setup Time
ns
tDH
Input data (DI) Hold Time
ns
tCKQ1
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (flow-through, WMODE = 1)
Clock HIGH to New Data Valid on DO (pipelined)
Address Collision clk-to-clk Delay for reliable read access after write on same address
ns
ns
tCKQ2
tWRO
tCCKH
ns
ns
Address Collision clk-to-clk Delay for reliable write access after write/read on same
address
TBD
ns
tRSTBQ
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
1.10
1.10
0.34
1.79
0.25
3.85
260
1.29
1.29
0.40
2.10
0.30
4.53
221
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-89
Automotive ProASIC3 Flash Family FPGAs
Table 3-119 • RAM512X18
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–1
Std.
0.35
0.00
0.13
0.08
0.26
0.00
3.03
1.26
TBD
Units
ns
Address Setup Time
0.30
0.00
0.11
0.07
0.22
0.00
2.58
1.07
TBD
tAH
Address Hold Time
ns
tENS
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
Input data (DI) Setup Time
Input data (DI) Hold Time
ns
tENH
ns
tDS
ns
tDH
ns
tCKQ1
tCKQ2
tWRO
Clock HIGH to New Data Valid on DO (output retained, WMODE = 0)
Clock HIGH to New Data Valid on DO (pipelined)
ns
ns
Address Collision clk-to-clk Delay for reliable read access after write on same
address
ns
tCCKH
tRSTBQ
Address Collision clk-to-clk Delay for reliable write access after write/read on
same address
TBD
TBD
ns
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
1.10
1.10
0.34
1.79
0.25
3.85
260
1.29
1.29
0.40
2.10
0.30
4.53
221
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-90
v2.0
Automotive ProASIC3 Flash Family FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 3-38 • FIFO Model
v2.0
3-91
Automotive ProASIC3 Flash Family FPGAs
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
tRSTFG
EMPTY
tRSTAF
AEMPTY
FULL
tRSTFG
tRSTAF
AFULL
WA/RA
(Address Counter)
MATCH (A0)
Figure 3-39 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
(Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 3-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion
3-92
v2.0
Automotive ProASIC3 Flash Family FPGAs
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 3-41 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
(EMPTY)
WA/RA
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
1st Rising
2nd Rising
Edge
After 1st
Write
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 3-42 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
NO MATCH
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 1st
Read
Edge
After 2nd
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 3-43 • FIFO FULL Flag and AFULL Flag Deassertion
v2.0
3-93
Automotive ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-120 • FIFO
Worst-Case Automotive Conditions: TJ = 135°C, VCC = 1.425 V
Parameter
tENS
Description
–1
Std.
1.67
0.02
0.32
0.00
0.22
0.00
2.86
1.09
2.09
1.98
7.53
2.06
7.45
1.12
1.12
0.35
1.82
0.26
3.93
255
Units
ns
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
1.97
0.03
0.28
0.00
0.26
0.00
3.37
1.28
2.45
2.33
8.85
2.42
8.76
1.32
1.32
0.41
2.14
0.30
4.62
217
tENH
ns
tBKS
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
ns
ns
ns
WCLK HIGH to Full Flag Valid
ns
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
3-94
v2.0
Automotive ProASIC3 Flash Family FPGAs
Table 3-121 • FIFO
Worst-Case Automotive Conditions: TJ = 115°C, VCC = 1.425 V
Parameter
tENS
Description
–1
Std.
1.64
0.02
0.32
0.00
0.22
0.00
2.81
1.07
2.05
1.95
7.38
2.02
7.30
1.10
1.10
0.34
1.79
0.25
3.85
260
Units
ns
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
1.93
0.03
0.27
0.00
0.26
0.00
3.30
1.25
2.41
2.29
8.68
2.37
8.59
1.29
1.29
0.40
2.10
0.30
4.53
221
tENH
ns
tBKS
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
ns
ns
ns
WCLK HIGH to Full Flag Valid
ns
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-95
Automotive ProASIC3 Flash Family FPGAs
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
tCKQ2
D1
D0
Data
Figure 3-44 • Timing Diagram
Timing Characteristics
Table 3-122 • Embedded FlashROM Access Time
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
–1
Std.
0.76
0.00
23.20
15
Units
0.65
0.00
19.73
15
ns
ns
tHOLD
Address Hold Time
tCK2Q
Clock to Out
ns
FMAX
Maximum Clock Frequency
MHz
Table 3-123 • Embedded FlashROM Access Time
Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V
Parameter
tSU
Description
–1
0.64
0.00
19.35
15
Std.
0.75
0.00
22.74
15
Units
ns
Address Setup Time
Address Hold Time
Clock to Out
tHOLD
ns
tCK2Q
ns
FMAX
Maximum Clock Frequency
MHz
3-96
v2.0
Automotive ProASIC3 Flash Family FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the
corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on
page 3-13 for more details.
Timing Characteristics
Table 3-124 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
–2
–1
Std.
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
20
20
20
MHz
ns
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 3-5 on page 3-5 for derating values.
v2.0
3-97
Automotive ProASIC3 Flash Family FPGAs
Package Pin Assignments
100-Pin VQFP
100
1
100-Pin
VQFP
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v2.0
4-1
Automotive ProASIC3 Flash Family FPGAs
100-Pin VQFP*
100-Pin VQFP*
100-Pin VQFP*
Pin Number
A3P060 Function
GND
Pin Number
A3P060 Function
IO62RSB1
IO61RSB1
VCC
Pin Number
A3P060 Function
IO31RSB0
1
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
GAA2/IO51RSB1
IO52RSB1
GBC2/IO29RSB0
GBB2/IO27RSB0
IO26RSB0
3
4
GAB2/IO53RSB1
IO95RSB1
GND
5
VCCIB1
GBA2/IO25RSB0
VMV0
6
GAC2/IO94RSB1
IO93RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
7
GNDQ
8
IO92RSB1
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
GFA0/IO85RSB1
VCCPLF
TDI
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
TMS
IO17RSB0
VMV1
IO15RSB0
GND
IO13RSB0
VCCIB1
VPUMP
IO11RSB0
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
NC
VCCIB0
TDO
GND
TRST
VCC
VJTAG
IO10RSB0
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
IO09RSB0
IO08RSB0
GNDQ
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GEA2/IO71RSB1
GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO00RSB0
IO64RSB1
GND
IO63RSB1
VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-2
v2.0
Automotive ProASIC3 Flash Family FPGAs
100-Pin VQFP*
100-Pin VQFP*
100-Pin VQFP*
Pin Number
A3P125 Function
GND
Pin Number
A3P125 Function
IO94RSB1
IO93RSB1
VCC
Pin Number
A3P125 Function
IO47RSB0
1
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
GAA2/IO67RSB1
IO68RSB1
GBC2/IO45RSB0
GBB2/IO43RSB0
IO42RSB0
3
4
GAB2/IO69RSB1
IO132RSB1
GND
5
VCCIB1
GBA2/IO41RSB0
VMV0
6
GAC2/IO131RSB1
IO130RSB1
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
7
GNDQ
8
IO129RSB1
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
GFA0/IO122RSB1
VCCPLF
TDI
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
TMS
IO28RSB0
VMV1
IO25RSB0
GND
IO22RSB0
VCCIB1
VPUMP
IO19RSB0
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
NC
VCCIB0
TDO
GND
TRST
VCC
VJTAG
IO15RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO13RSB0
IO11RSB0
GNDQ
IO09RSB0
GEA2/IO106RSB1
GEB2/IO105RSB1
GEC2/IO104RSB1
IO102RSB1
IO07RSB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
IO100RSB1
IO99RSB1
IO97RSB1
IO96RSB1
GND
IO95RSB1
VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-3
Automotive ProASIC3 Flash Family FPGAs
100-Pin VQFP*
100-Pin VQFP*
100-Pin VQFP*
Pin Number
A3P250 Function
GND
Pin Number
A3P250 Function
IO85RSB2
IO84RSB2
VCC
Pin Number
A3P250 Function
IO43NDB1
1
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
GAA2/IO118UDB3
IO118VDB3
GBC2/IO43PDB1
GBB2/IO42PSB1
IO41NDB1
3
4
GAB2/IO117UDB3
IO117VDB3
GND
5
VCCIB2
GBA2/IO41PDB1
VMV1
6
GAC2/IO116UDB3
IO116VDB3
IO77RSB2
IO74RSB2
IO71RSB2
GDC2/IO63RSB2
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
7
GNDQ
8
IO112PSB3
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO29RSB0
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
GFA0/IO108NPB3
VCCPLF
TCK
TDI
GFA1/IO108PPB3
GFA2/IO107PSB3
VCC
TMS
IO27RSB0
VMV2
IO25RSB0
GND
IO23RSB0
VCCIB3
VPUMP
IO21RSB0
GFC2/IO105PSB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
NC
VCCIB0
TDO
GND
TRST
VCC
VJTAG
IO15RSB0
GDA1/IO60USB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO52NDB1
GCB2/IO52PDB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
VCCIB1
IO13RSB0
IO11RSB0
GNDQ
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO97RSB2
GEB2/IO96RSB2
GEC2/IO95RSB2
IO93RSB2
IO92RSB2
IO91RSB2
IO90RSB2
VMV0
IO88RSB2
GND
IO86RSB2
VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-4
v2.0
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA
A1 Ball Pad Corner
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v2.0
4-5
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number
A1
A3P060 Function
GNDQ
Pin Number
A3P060 Function
IO91RSB1
Pin Number
A3P060 Function
GFA1/IO84RSB1
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
A2
VMV0
IO92RSB1
A3
GAB0/IO04RSB0
GAB1/IO05RSB0
IO08RSB0
IO93RSB1
VCCPLF
A4
GAA2/IO51RSB1
GAC0/IO06RSB0
GAC1/IO07RSB0
GBC0/IO19RSB0
GBC1/IO20RSB0
GBB2/IO27RSB0
IO18RSB0
GFA0/IO85RSB1
GND
A5
A6
GND
GND
A7
IO11RSB0
GND
A8
VCC
GDC1/IO45RSB0
IO32RSB0
A9
IO16RSB0
A10
A11
A12
B1
GBA0/IO23RSB0
GBA1/IO24RSB0
GNDQ
GCC2/IO43RSB0
IO31RSB0
IO28RSB0
GCB1/IO37RSB0
VCC
GCB2/IO42RSB0
VCC
GAB2/IO53RSB1
GND
B2
E2
GFC0/IO88RSB1
GFC1/IO89RSB1
VCCIB1
GFB2/IO82RSB1
GFC2/IO81RSB1
GEC1/IO77RSB1
VCC
B3
GAA0/IO02RSB0
GAA1/IO03RSB0
IO00RSB0
E3
B4
E4
B5
E5
IO52RSB1
B6
IO10RSB0
E6
VCCIB0
IO34RSB0
B7
IO12RSB0
E7
VCCIB0
IO44RSB0
B8
IO14RSB0
E8
GCC1/IO35RSB0
VCCIB0
GDB2/IO55RSB1
GDC0/IO46RSB0
VCCIB0
B9
GBB0/IO21RSB0
GBB1/IO22RSB0
GND
E9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
GCA0/IO40RSB0
IO30RSB0
IO33RSB0
VMV0
VCC
IO95RSB1
GFB0/IO86RSB1
VCOMPLF
GEB1/IO75RSB1
IO78RSB1
C2
GFA2/IO83RSB1
GAC2/IO94RSB1
VCC
F2
J2
C3
F3
GFB1/IO87RSB1
IO90RSB1
J3
VCCIB1
C4
F4
J4
GEC0/IO76RSB1
IO79RSB1
C5
IO01RSB0
F5
GND
J5
C6
IO09RSB0
F6
GND
J6
IO80RSB1
C7
IO13RSB0
F7
GND
J7
VCC
C8
IO15RSB0
F8
GCC0/IO36RSB0
GCB0/IO38RSB0
GND
J8
TCK
C9
IO17RSB0
F9
J9
GDA2/IO54RSB1
TDO
C10
C11
C12
GBA2/IO25RSB0
IO26RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO39RSB0
GCA2/IO41RSB0
GDA1/IO49RSB0
GDB1/IO47RSB0
GBC2/IO29RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-6
v2.0
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
Pin Number
144-Pin FBGA*
A3P060 Function
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
GEA2/IO71RSB1
IO65RSB1
Pin Number
A3P060 Function
GND
Pin Number
M1
A3P060 Function
GNDQ
K1
K2
L1
L2
VMV1
M2
GEC2/IO69RSB1
IO68RSB1
IO66RSB1
IO63RSB1
IO61RSB1
IO60RSB1
NC
K3
L3
GEB2/IO70RSB1
IO67RSB1
M3
K4
L4
M4
K5
L5
VCCIB1
M5
K6
IO64RSB1
L6
IO62RSB1
IO59RSB1
IO58RSB1
TMS
M6
K7
GND
L7
M7
K8
IO57RSB1
L8
M8
K9
GDC2/IO56RSB1
GND
L9
M9
TDI
K10
K11
K12
L10
L11
L12
VJTAG
M10
M11
M12
VCCIB1
GDA0/IO50RSB0
GDB0/IO48RSB0
VMV1
VPUMP
TRST
GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-7
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number
A1
A3P125 Function
GNDQ
Pin Number
A3P125 Function
IO128RSB1
Pin Number
A3P125 Function
GFA1/IO121RSB1
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
A2
VMV0
IO129RSB1
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO11RSB0
IO130RSB1
VCCPLF
A4
GAA2/IO67RSB1
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO43RSB0
IO28RSB0
GFA0/IO122RSB1
GND
A5
A6
GND
GND
A7
IO18RSB0
GND
A8
VCC
GDC1/IO61RSB0
IO48RSB0
A9
IO25RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
GCC2/IO59RSB0
IO47RSB0
IO44RSB0
GCB1/IO53RSB0
VCC
GCB2/IO58RSB0
VCC
GAB2/IO69RSB1
GND
B2
E2
GFC0/IO125RSB1
GFC1/IO126RSB1
VCCIB1
GFB2/IO119RSB1
GFC2/IO118RSB1
GEC1/IO112RSB1
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO08RSB0
E3
B4
E4
B5
E5
IO68RSB1
B6
IO14RSB0
E6
VCCIB0
IO50RSB0
B7
IO19RSB0
E7
VCCIB0
IO60RSB0
B8
IO22RSB0
E8
GCC1/IO51RSB0
VCCIB0
GDB2/IO71RSB1
GDC0/IO62RSB0
VCCIB0
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
GCA0/IO56RSB0
IO46RSB0
IO49RSB0
VMV0
VCC
IO132RSB1
GFA2/IO120RSB1
GAC2/IO131RSB1
VCC
GFB0/IO123RSB1
VCOMPLF
GEB1/IO110RSB1
IO115RSB1
VCCIB1
C2
F2
J2
C3
F3
GFB1/IO124RSB1
IO127RSB1
GND
J3
C4
F4
J4
GEC0/IO111RSB1
IO116RSB1
IO117RSB1
VCC
C5
IO10RSB0
F5
J5
C6
IO12RSB0
F6
GND
J6
C7
IO21RSB0
F7
GND
J7
C8
IO24RSB0
F8
GCC0/IO52RSB0
GCB0/IO54RSB0
GND
J8
TCK
C9
IO27RSB0
F9
J9
GDA2/IO70RSB1
TDO
C10
C11
C12
GBA2/IO41RSB0
IO42RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO55RSB0
GCA2/IO57RSB0
GDA1/IO65RSB0
GDB1/IO63RSB0
GBC2/IO45RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-8
v2.0
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number
A3P125 Function
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
GEA2/IO106RSB1
IO100RSB1
Pin Number
A3P125 Function
GND
Pin Number
M1
A3P125 Function
GNDQ
K1
K2
L1
L2
VMV1
M2
GEC2/IO104RSB1
IO103RSB1
IO101RSB1
IO97RSB1
IO94RSB1
IO86RSB1
IO75RSB1
TDI
K3
L3
GEB2/IO105RSB1
IO102RSB1
M3
K4
L4
M4
K5
L5
VCCIB1
M5
K6
IO98RSB1
L6
IO95RSB1
IO85RSB1
IO74RSB1
TMS
M6
K7
GND
L7
M7
K8
IO73RSB1
L8
M8
K9
GDC2/IO72RSB1
GND
L9
M9
K10
K11
K12
L10
L11
L12
VJTAG
M10
M11
M12
VCCIB1
GDA0/IO66RSB0
GDB0/IO64RSB0
VMV1
VPUMP
TRST
GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-9
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number
A1
A3P250 Function
GNDQ
Pin Number
A3P250 Function
IO112NDB3
Pin Number
A3P250 Function
GFA1/IO108PPB3
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
A2
VMV0
IO112PDB3
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
IO116VDB3
VCCPLF
A4
GAA2/IO118UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO42PDB1
IO42NDB1
GFA0/IO108NPB3
GND
A5
A6
GND
GND
A7
IO29RSB0
GND
A8
VCC
GDC1/IO58UPB1
IO53NDB1
GCC2/IO53PDB1
IO52NDB1
GCB2/IO52PDB1
VCC
A9
IO33RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
IO43NPB1
GCB1/IO49PPB1
VCC
GAB2/IO117UDB3
GND
B2
E2
GFC0/IO110NDB3
GFC1/IO110PDB3
VCCIB3
GFB2/IO106PDB3
GFC2/IO105PSB3
GEC1/IO100PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO118VPB3
B6
IO19RSB0
E6
VCCIB0
IO79RSB2
B7
IO22RSB0
E7
V
CCIB0
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
VCCIB1
GDB2/IO62RSB2
GDC0/IO58VPB1
VCCIB1
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
E10
E11
E12
F1
VCC
GCA0/IO50NDB1
IO51NDB1
IO54PSB1
VMV1
VCC
IO117VDB3
GFA2/IO107PPB3
GAC2/IO116UDB3
VCC
GFB0/IO109NPB3
VCOMPLF
GEB1/IO99PDB3
IO106NDB3
VCCIB3
C2
F2
J2
C3
F3
GFB1/IO109PPB3
IO107NPB3
GND
J3
C4
F4
J4
GEC0/IO100NDB3
IO88RSB2
C5
IO12RSB0
F5
J5
C6
IO17RSB0
F6
GND
J6
IO81RSB2
C7
IO24RSB0
F7
GND
J7
VCC
C8
IO31RSB0
F8
GCC0/IO48NDB1
GCB0/IO49NPB1
GND
J8
TCK
C9
IO34RSB0
F9
J9
GDA2/IO61RSB2
TDO
C10
C11
C12
GBA2/IO41PDB1
IO41NDB1
GBC2/IO43PPB1
F10
F11
F12
J10
J11
J12
GCA1/IO50PDB1
GCA2/IO51PDB1
GDA1/IO60UDB1
GDB1/IO59UDB1
4-10
v2.0
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number
A3P250 Function
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
GEA2/IO97RSB2
IO90RSB2
Pin Number
A3P250 Function
GND
Pin Number
M1
A3P250 Function
GNDQ
K1
K2
L1
L2
VMV3
M2
GEC2/IO95RSB2
IO92RSB2
IO89RSB2
IO87RSB2
IO85RSB2
IO78RSB2
IO76RSB2
TDI
K3
L3
GEB2/IO96RSB2
IO91RSB2
M3
K4
L4
M4
K5
L5
V
CCIB2
M5
K6
IO84RSB2
L6
IO82RSB2
IO80RSB2
IO72RSB2
TMS
M6
K7
GND
L7
M7
K8
IO66RSB2
L8
M8
K9
GDC2/IO63RSB2
GND
L9
M9
K10
K11
K12
L10
L11
L12
VJTAG
M10
M11
M12
VCCIB2
GDA0/IO60VDB1
GDB0/IO59VDB1
VMV2
VPUMP
TRST
GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-11
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
Pin Number A3P1000 Function
144-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO213PDB3
IO213NDB3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO207PPB3
GND
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
IO223NDB3
VCCPLF
GAA2/IO225PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO72RSB0
GBC1/IO73RSB0
GBB2/IO79PDB1
IO79NDB1
GFA0/IO207NPB3
GND
GND
GND
IO44RSB0
GND
VCC
GDC1/IO111PPB1
IO96NDB1
IO69RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GNDQ
GCC2/IO96PDB1
IO95NDB1
IO80NPB1
GCB1/IO92PPB1
VCC
GCB2/IO95PDB1
VCC
GAB2/IO224PDB3
GND
B2
E2
GFC0/IO209NDB3
GFC1/IO209PDB3
VCCIB3
GFB2/IO205PDB3
GFC2/IO204PSB3
GEC1/IO190PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO225NPB3
B6
IO26RSB0
E6
VCCIB0
IO105PDB1
IO105NDB1
GDB2/IO115RSB2
GDC0/IO111NPB1
VCCIB1
B7
IO35RSB0
E7
VCCIB0
B8
IO60RSB0
E8
GCC1/IO91PDB1
VCCIB1
B9
GBB0/IO74RSB0
GBB1/IO75RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO93NDB1
IO94NDB1
GFB0/IO208NPB3
VCOMPLF
IO101PSB1
VCC
VMV1
IO224NDB3
GFA2/IO206PPB3
GAC2/IO223PDB3
VCC
GEB1/IO189PDB3
IO205NDB3
VCCIB3
F2
J2
F3
GFB1/IO208PPB3
IO206NPB3
GND
J3
F4
J4
GEC0/IO190NDB3
IO160RSB2
IO157RSB2
VCC
IO16RSB0
F5
J5
IO29RSB0
F6
GND
J6
IO32RSB0
F7
GND
J7
IO63RSB0
F8
GCC0/IO91NDB1
GCB0/IO92NPB1
GND
J8
TCK
IO66RSB0
F9
J9
GDA2/IO114RSB2
TDO
GBA2/IO78PDB1
IO78NDB1
GBC2/IO80PPB1
F10
F11
F12
J10
J11
J12
GCA1/IO93PDB1
GCA2/IO94PDB1
GDA1/IO113PDB1
GDB1/IO112PDB1
Note: *Refer to the User I/O Naming Convention.
4-12
v2.0
Automotive ProASIC3 Flash Family FPGAs
144-Pin FBGA*
144-Pin FBGA*
144-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
K1
K2
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
GEA2/IO187RSB2
IO169RSB2
L1
L2
GND
VMV3
M1
M2
GNDQ
GEC2/IO185RSB2
IO173RSB2
IO168RSB2
IO161RSB2
IO156RSB2
IO145RSB2
IO141RSB2
TDI
K3
L3
GEB2/IO186RSB2
IO172RSB2
M3
K4
L4
M4
K5
L5
V
CCIB2
M5
K6
IO152RSB2
L6
IO153RSB2
IO144RSB2
IO140RSB2
TMS
M6
K7
GND
L7
M7
K8
IO117RSB2
L8
M8
K9
GDC2/IO116RSB2
GND
L9
M9
K10
K11
K12
L10
L11
L12
VJTAG
M10
M11
M12
VCCIB2
GDA0/IO113NDB1
GDB0/IO112NDB1
VMV2
VPUMP
TRST
GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-13
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
4-14
v2.0
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
Pin Number
A3P250 Function
GND
A3P250 Function
GAC0/IO04RSB0
GAC1/IO05RSB0
IO13RSB0
IO17RSB0
IO22RSB0
IO27RSB0
IO31RSB0
GBC0/IO35RSB0
IO34RSB0
NC
Pin Number
E9
A3P250 Function
A1
A2
C5
C6
IO24RSB0
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO07RSB0
E10
E11
E12
E13
E14
E15
E16
F1
VCCIB0
A3
C7
VCCIB0
VMV1
A4
C8
A5
C9
GBC2/IO43PDB1
IO46RSB1
NC
A6
IO10RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO11RSB0
A8
IO15RSB0
IO45PDB1
IO113NDB3
IO112PPB3
NC
A9
IO20RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO25RSB0
F2
IO29RSB0
IO42NPB1
IO44PDB1
IO114VDB3
IO114UDB3
GAC2/IO116UDB3
NC
F3
IO33RSB0
F4
IO115VDB3
VCCIB3
GBB1/IO38RSB0
GBA0/IO39RSB0
GBA1/IO40RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO117UDB3
GAA2/IO118UDB3
NC
D5
GNDQ
F9
VCC
B2
D6
IO08RSB0
IO14RSB0
IO18RSB0
IO23RSB0
IO28RSB0
IO32RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO06RSB0
D8
VCCIB1
B5
D9
IO43NDB1
NC
B6
IO09RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO12RSB0
IO47PPB1
IO45NDB1
IO111NDB3
IO111PDB3
IO112NPB3
GFC1/IO110PPB3
VCCIB3
B8
IO16RSB0
B9
IO21RSB0
NC
B10
B11
B12
B13
B14
B15
B16
C1
IO26RSB0
GBB2/IO42PPB1
NC
G2
IO30RSB0
G3
GBC1/IO36RSB0
GBB0/IO37RSB0
NC
IO44NDB1
IO113PDB3
NC
G4
G5
E2
G6
VCC
GBA2/IO41PDB1
IO41NDB1
IO117VDB3
IO118VDB3
NC
E3
IO116VDB3
IO115UDB3
VMV0
G7
GND
E4
G8
GND
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
NC
E8
IO19RSB0
VCCIB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-15
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
G13
G14
G15
G16
H1
A3P250 Function
GCC1/IO48PPB1
IO47NPB1
IO54PDB1
IO54NDB1
GFB0/IO109NPB3
GFA0/IO108NDB3
GFB1/IO109PPB3
VCOMPLF
Pin Number
A3P250 Function
GFC2/IO105PDB3
IO107NPB3
Pin Number
A3P250 Function
K1
K2
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
K3
IO104PPB3
VCCIB2
NC
K4
NC
K5
VCCIB3
IO74RSB2
VCCIB2
H2
K6
VCC
H3
K7
GND
GND
VCCIB2
H4
K8
VMV2
NC
H5
GFC0/IO110NPB3
VCC
K9
GND
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO59UPB1
GDC1/IO58UDB1
IO56NDB1
IO103NDB3
IO101PPB3
GEC1/IO100PPB3
NC
H7
GND
VCC
H8
GND
VCCIB1
IO52NPB1
IO55RSB1
IO53NPB1
IO51NDB1
IO105NDB3
IO104NPB3
NC
H9
GND
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO48NPB1
GCB1/IO49PPB1
GCA0/IO50NPB1
NC
N4
N5
GNDQ
L2
N6
GEA2/IO97RSB2
IO86RSB2
IO82RSB2
IO75RSB2
IO69RSB2
IO64RSB2
GNDQ
L3
N7
GCB0/IO49NPB1
GFA2/IO107PPB3
GFA1/IO108PDB3
VCCPLF
L4
IO102RSB3
VCCIB3
GND
N8
L5
N9
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO106NDB3
GFB2/IO106PDB3
VCC
L8
VCC
J5
L9
VCC
NC
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO58VDB1
GDA1/IO60UDB1
GEB1/IO99PDB3
GEB0/IO99NDB3
NC
J8
GND
VCCIB1
J9
GND
GDB0/IO59VPB1
IO57VDB1
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
IO57UDB1
IO56PDB1
P3
GCB2/IO52PPB1
GCA1/IO50PPB1
GCC2/IO53PPB1
NC
P4
NC
IO103PDB3
NC
P5
IO92RSB2
IO89RSB2
IO85RSB2
IO81RSB2
P6
IO101NPB3
GEC0/IO100NPB3
P7
GCA2/IO51PDB1
P8
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-16
v2.0
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
Pin Number
A3P250 Function
IO76RSB2
IO71RSB2
IO66RSB2
NC
A3P250 Function
IO84RSB2
IO80RSB2
IO77RSB2
IO72RSB2
IO68RSB2
IO65RSB2
GDB2/IO62RSB2
TDI
Pin Number
A3P250 Function
IO90RSB2
P9
P10
P11
P12
P13
P14
P15
P16
R1
R7
R8
T5
T6
IO87RSB2
R9
T7
IO83RSB2
R10
R11
R12
R13
R14
R15
R16
T1
T8
IO79RSB2
TCK
T9
IO78RSB2
VPUMP
T10
T11
T12
T13
T14
T15
T16
IO73RSB2
TRST
IO70RSB2
GDA0/IO60VDB1
GEA1/IO98PDB3
GEA0/IO98NDB3
NC
GDC2/IO63RSB2
IO67RSB2
NC
R2
TDO
GDA2/IO61RSB2
TMS
R3
GND
R4
GEC2/IO95RSB2
IO91RSB2
IO88RSB2
T2
IO94RSB2
GEB2/IO96RSB2
IO93RSB2
GND
R5
T3
R6
T4
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-17
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
A1
A3P1000 Function
GND
Pin Number
A3P1000 Function
IO25RSB0
Pin Number
A3P1000 Function
GBC2/IO80PDB1
IO83PPB1
C7
C8
E13
E14
E15
E16
F1
A2
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
IO36RSB0
A3
C9
IO42RSB0
IO86PPB1
A4
C10
C11
C12
C13
C14
C15
C16
D1
IO49RSB0
IO87PDB1
A5
IO56RSB0
IO217NDB3
IO218NDB3
IO216PDB3
A6
IO22RSB0
GBC0/IO72RSB0
IO62RSB0
F2
A7
IO28RSB0
F3
A8
IO35RSB0
VMV0
F4
IO216NDB3
A9
IO45RSB0
IO78NDB1
IO81NDB1
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
F5
VCCIB3
A10
A11
A12
A13
A14
A15
A16
B1
IO50RSB0
F6
GND
VCC
IO55RSB0
F7
IO61RSB0
D2
F8
VCC
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
D3
F9
VCC
D4
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
H1
VCC
D5
GND
D6
IO23RSB0
VCCIB1
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
D7
IO29RSB0
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
IO210PSB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
B2
D8
IO33RSB0
B3
D9
IO46RSB0
B4
GAB1/IO03RSB0
IO17RSB0
D10
D11
D12
D13
D14
D15
D16
E1
IO52RSB0
B5
IO60RSB0
B6
IO21RSB0
GNDQ
B7
IO27RSB0
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NSB1
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
B8
IO34RSB0
B9
IO44RSB0
VCCIB3
B10
B11
B12
B13
B14
B15
B16
C1
IO51RSB0
VCC
IO57RSB0
GND
GND
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
E2
E3
GND
E4
GND
GBA2/IO78PDB1
IO81PDB1
E5
VCC
E6
V
CCIB0
CCIB0
VCCIB1
IO224NDB3
IO225NDB3
VMV3
E7
V
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
IO88NDB1
GFB0/IO208NPB3
GFA0/IO207NDB3
C2
E8
IO38RSB0
IO47RSB0
VCCIB0
C3
E9
C4
IO11RSB0
E10
E11
E12
C5
GAC0/IO04RSB0
GAC1/IO05RSB0
VCCIB0
C6
VMV1
H2
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-18
v2.0
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
A3P1000 Function
GFB1/IO208PPB3
VCOMPLF
Pin Number
A3P1000 Function
GND
Pin Number
M15
M16
N1
A3P1000 Function
GDC1/IO111PDB1
IO107NDB1
IO194PSB3
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
K9
K10
K11
K12
K13
K14
K15
K16
L1
GND
GFC0/IO209NPB3
VCC
VCC
VCCIB1
N2
IO192PPB3
GND
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
N3
GEC1/IO190PPB3
IO192NPB3
GNDQ
GND
N4
GND
N5
GND
N6
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
VCC
N7
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
L2
N8
L3
N9
L4
N10
N11
N12
N13
N14
N15
N16
P1
L5
VCCIB3
GCB0/IO92NPB1
GFA2/IO206PSB3
GFA1/IO207PDB3
VCCPLF
L6
GND
VCC
L7
IO110PDB1
VJTAG
J2
L8
VCC
J3
L9
VCC
GDC0/IO111NDB1
GDA1/IO113PDB1
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
J4
IO205NDB3
GFB2/IO205PDB3
VCC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
VCC
J5
GND
J6
VCCIB1
P2
J7
GND
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
IO197NSB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
P3
J8
GND
P4
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
J9
GND
P5
J10
J11
J12
J13
J14
J15
J16
K1
GND
P6
VCC
P7
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PSB1
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
V
CCIB2
CCIB2
V
TCK
K2
IO147RSB2
IO136RSB2
VPUMP
K3
TRST
K4
VCCIB2
GDA0/IO113NDB1
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
K5
K6
K7
K8
VCCIB3
VCCIB2
VMV2
VCC
R2
GND
GND
IO110NDB1
GDB1/IO112PPB1
R3
R4
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-19
Automotive ProASIC3 Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
A3P1000 Function
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
Pin Number
A3P1000 Function
GNDQ
Pin Number
A3P1000 Function
IO142RSB2
R5
R6
R15
R16
T1
T9
TDO
T10
T11
T12
T13
T14
T15
T16
IO135RSB2
R7
GND
IO130RSB2
R8
T2
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
GDC2/IO116RSB2
IO120RSB2
R9
T3
R10
R11
R12
R13
R14
T4
GDA2/IO114RSB2
TMS
T5
T6
GND
T7
T8
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-20
v2.0
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v2.0
4-21
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GND
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO63RSB0
IO66RSB0
IO68RSB0
IO70RSB0
NC
D7
D8
GAB0/IO02RSB0
IO16RSB0
IO22RSB0
IO28RSB0
IO35RSB0
IO45RSB0
IO50RSB0
IO55RSB0
IO61RSB0
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
GND
A3
VCCIB0
D9
A4
IO07RSB0
IO09RSB0
IO13RSB0
IO18RSB0
IO20RSB0
IO26RSB0
IO32RSB0
IO40RSB0
IO41RSB0
IO53RSB0
IO59RSB0
IO64RSB0
IO65RSB0
IO67RSB0
IO69RSB0
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
A6
NC
A7
VCCIB1
A8
GND
VCCIB3
IO220PDB3
NC
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
C2
C3
C4
NC
C5
GND
C6
IO10RSB0
IO14RSB0
VCC
NC
C7
NC
C8
NC
C9
VCC
IO219NDB3
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
IO30RSB0
IO37RSB0
IO43RSB0
NC
E2
E3
GND
VCCIB0
E4
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
GND
E5
GND
VCC
E6
GND
VCC
E7
GAB1/IO03RSB0
IO17RSB0
IO21RSB0
IO27RSB0
IO34RSB0
IO44RSB0
IO51RSB0
IO57RSB0
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
GBA2/IO78PDB1
IO81PDB1
GND
B2
VCCIB3
NC
E8
B3
NC
NC
E9
B4
IO06RSB0
IO08RSB0
IO12RSB0
IO15RSB0
IO19RSB0
IO24RSB0
IO31RSB0
IO39RSB0
IO48RSB0
IO54RSB0
IO58RSB0
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
B6
NC
B7
NC
B8
VCCIB1
IO219PDB3
IO220NDB3
NC
B9
B10
B11
B12
B13
B14
D2
D3
D4
GND
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
D6
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-22
v2.0
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
E21
E22
F1
NC
IO84PDB1
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO52RSB0
IO60RSB0
GNDQ
J5
J6
IO218NDB3
IO216PDB3
IO216NDB3
J7
F2
IO215PDB3
IO215NDB3
IO224NDB3
IO225NDB3
VMV3
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NPB1
IO85PDB1
IO85NDB1
NC
J8
VCCIB3
F3
J9
GND
VCC
F4
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
F5
VCC
F6
VCC
F7
IO11RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
VCC
F8
GND
F9
NC
VCCIB1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H2
NC
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
NC
H3
VCC
H4
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
H5
H6
H7
IO89PDB1
IO89NDB1
IO211PDB3
IO211NDB3
NC
H8
H9
VCCIB0
IO78NDB1
IO81NDB1
IO82PPB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
VCCIB0
K2
IO38RSB0
IO47RSB0
VCCIB0
K3
K4
IO210PPB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
K5
IO84NDB1
IO214NDB3
IO214PDB3
NC
VCCIB0
K6
VMV1
K7
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
VCC
K8
K9
VCC
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
GND
GND
NC
GND
NC
VCC
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO212NDB3
IO212PDB3
NC
VCCIB1
J2
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
J3
J4
IO217NDB3
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-23
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
K19
K20
K21
K22
L1
IO88NDB1
IO94NPB1
IO98NDB1
IO98PDB1
NC
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
GND
P3
P4
IO199NDB3
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
GND
GND
P5
VCC
P6
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PPB1
IO101PPB1
IO99PPB1
NC
P7
L2
IO200PDB3
IO210NPB3
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
P8
L3
P9
L4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
VCC
L6
VCC
L7
VCC
L8
GFC0/IO209NPB3
VCC
GND
L9
IO201NDB3
IO201PDB3
NC
VCCIB1
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
NC
GND
N3
GND
N4
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
GND
N5
VCC
N6
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
IO97PDB1
IO97NDB1
IO99NPB1
NC
N7
IO104PDB1
IO103NDB1
NC
N8
N9
VCC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
IO197PPB3
VCC
GND
R3
GND
R4
IO197NPB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
GND
R5
VCC
R6
VCCIB1
R7
IO200NDB3
IO206NDB3
GFA2/IO206PDB3
GFA1/IO207PDB3
VCCPLF
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
NC
R8
R9
VCCIB2
R10
R11
R12
R13
R14
R15
R16
VCCIB2
IO147RSB2
IO136RSB2
IO205NDB3
GFB2/IO205PDB3
VCC
IO101NPB1
IO103PDB1
NC
VCCIB2
VCCIB2
VMV2
GND
P2
IO199PDB3
IO110NDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-24
v2.0
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
R17
R18
R19
R20
R21
R22
T1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
VCC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
W1
W2
NC
IO191PDB3
NC
W3
W4
GND
IO104NDB1
IO105PDB1
IO198PDB3
IO198NDB3
NC
W5
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
W6
W7
T2
TCK
W8
T3
VPUMP
W9
T4
IO194PPB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO113NDB1
NC
T6
T7
IO108NDB1
IO109PDB1
NC
T8
T9
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
V5
GND
V6
NC
V7
NC
IO110PDB1
VJTAG
V8
NC
V9
VCCIB3
GDC0/IO111NDB1
GDA1/IO113PDB1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
IO191NDB3
NC
Y3
Y4
IO182RSB2
GND
IO108PDB1
IO105NDB1
IO195PDB3
IO195NDB3
IO194NPB3
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
Y5
Y6
IO177RSB2
IO174RSB2
VCC
Y7
U2
Y8
U3
Y9
VCC
U4
GNDQ
Y10
Y11
Y12
Y13
Y14
IO154RSB2
IO148RSB2
IO140RSB2
NC
U5
TDO
U6
GND
U7
IO179RSB2
IO171RSB2
NC
U8
IO109NDB1
VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
v2.0
4-25
Automotive ProASIC3 Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
VCC
NC
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
IO146RSB2
IO139RSB2
IO133RSB2
NC
AB7
AB8
IO167RSB2
IO162RSB2
IO156RSB2
IO150RSB2
IO145RSB2
IO144RSB2
IO132RSB2
IO127RSB2
IO126RSB2
IO123RSB2
IO121RSB2
IO118RSB2
NC
NC
AB9
GND
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
NC
NC
IO122RSB2
IO119RSB2
IO117RSB2
NC
NC
VCCIB1
GND
V
CCIB3
NC
NC
VCCIB1
IO181RSB2
IO178RSB2
IO175RSB2
IO169RSB2
IO166RSB2
IO160RSB2
IO152RSB2
GND
GND
AB2
GND
VCCIB2
AB3
VCCIB2
GND
AB4
IO180RSB2
IO176RSB2
IO173RSB2
GND
AB5
AB6
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4-26
v2.0
ProASIC3 Automotive Flash Family FPGAs
Datasheet Information
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The
definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could
require an approved export license prior to export from the United States. An export includes release of product or
disclosure of technology to a foreign national inside or outside the United States.
v2.0
5-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
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Station Approach, Blackwater
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Tokyo 150 Japan
Phone 650.318.4200
Fax 650.318.4600
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Phone +852 2185 6460
Fax +852 2185 6488
Phone +44 (0) 1276 609 300
Fax +44 (0) 1276 607 540
www.jp.actel.com
www.actel.com.cn
51700090-0/8.07
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