A3P250-FGG256 [MICROSEMI]
Terrestrial FPGA and SoC Product Catalog; 地面FPGA和SoC产品目录
| 型号： | A3P250-FGG256 |
| 厂家： | 
Microsemi |
| 描述： | Terrestrial FPGA and SoC Product Catalog |
| 文件： | 总27页 (文件大小：1893K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Terrestrial FPGA and SoC
Product Catalog
October 2011
Power Matters.
The leader in customizable System-on-Chip devices
and FPGAs for sense and control applications
where reliability, security, and power matter.
wwmcrsem.cmsc
Now, more than ever, power matters.
Whether you’re designing at the board or system level, Microsemi’s customizable System-on-Chip (cSoC) devices and low
power FPGAs are your best choice. The unique, flash-based technology of Microsemi FPGAs, coupled with their history of reliability,
sets them apart from traditional FPGAs.
Design for today’s rapidly growing markets of consumer and portable medical devices, or tomorrow’s environmentally friendly data
centers, industrial controls and military and commercial aircraft. Only Microsemi can meet the power, size, cost and reliability targets
that reduce time-to-market and enable long-term profitability.
Table of Contents
SmartFusion®
Fusion
• Customizable System-on-Chip (cSoC)
• Mixed Signal FPGAs
4
5
• Mixed Signal Integration Down to –55ºC
• Reprogrammable Digital Logic and Configurable Analog
• Embedded Flash Memory
6
Extended Temperature Fusion
• Low Power
• Small Package Footprint
• High Logic Density
IGLOO®/e
7
8
9
• Low Power
• Small Package Footprint
IGLOO nano
IGLOO PLUS
• Low Power
• Small Package Footprint
• High I/O-to-Logic Ratio
• High Logic Density
• High Performance
• Low Cost
ProASIC®3/E
10
11
• Small Package Footprint
• High Performance
• Low Cost
ProASIC3 nano
• Low Power
• High Logic Density
• High Performance
• Low Cost
12
ProASIC3L
• Unprecedented Low Power Consumption Across
the Full Military Temperature Range
• High-Density Fine-Pitch Ball Grid Packaging
13
13
Military ProASIC3/EL
Military ProASICPLUS®
• High Performance and Easy In-System Programming
• Industry’s First Military Screened Flash FPGA
• Full Processing to MIL-STD-883 Class B
• Established Heritage on Commercial and Military Aircraft
• I/O Counts
14
16
18
19
20
21
22
26
27
I/O Table
• Package Dimensions
FPGA Packages
Axcelerator®
SX-A
MX
• Design Environment for Microsemi Flash Devices
• Starter, Evaluation and Demonstration Kits
• FlashPro3 and Silicon Sculptor 3 Programmers
• Microsemi IP Cores
Design Tools
Development Kits
Programmers
Intellectual Property Cores
Please refer to www.microsemi.com/soc and appropriate product datasheets for the latest device information, valid ordering codes and more
information regarding previous generations of flash and antifuse FPGAs.
www.microsemi.com/soc
3
SmartFusion
The customizable system-on-chip (cSoC) device
SmartFusion cSoCs are the only devices that integrate FPGA fabric, an ARM® Cortex™-M3 processor and programmable analog, offering full customization, IP
protection and ease-of-use. Based on Microsemi’s proprietary flash process, SmartFusion cSoCs are ideal for hardware and embedded designers who need a true
system-on-chip that gives more flexibility than traditional fixed-function microcontrollers without the excessive cost of soft processor cores on traditional FPGAs.
•ꢀ Availableꢀinꢀcommercial,ꢀindustrialꢀ
and military* grades
•ꢀ 10/100ꢀEthernetꢀMAC
•ꢀ 8-channelꢀDMAꢀcontroller
•ꢀ Upꢀtoꢀtenꢀ15ꢀnsꢀhigh-speedꢀ
comparators
•ꢀ Twoꢀperipheralsꢀofꢀeachꢀtype:ꢀ
•ꢀ Integratedꢀanalog-to-digitalꢀ
converters (ADCs) and digital-
to-analog converters (DACs)
withꢀ1ꢀpercentꢀaccuracy
2
•ꢀ Hardꢀ100ꢀMHzꢀ32-bitꢀARMꢀ
Cortex-M3 CPU
SPI,ꢀI C,ꢀUART,ꢀandꢀ32-bitꢀtimers
•ꢀ Analogꢀcomputeꢀengineꢀ(ACE)ꢀ
offloadsꢀCPUꢀfromꢀanalogꢀ
processing
•ꢀ Upꢀtoꢀ512ꢀKBꢀflashꢀandꢀ
64ꢀKBꢀSRAMꢀ
•ꢀ Multi-layerꢀAHBꢀcommunicationsꢀ
matrixꢀwithꢀupꢀtoꢀ16ꢀGbpsꢀthroughput
•ꢀ On-chipꢀvoltage,ꢀcurrentꢀandꢀ
temperature monitors
•ꢀ Upꢀtoꢀ35ꢀanalogꢀI/Osꢀandꢀ
169ꢀdigitalꢀGPIOsꢀ
•ꢀ Externalꢀmemoryꢀcontrollerꢀ(EMC)
* Under development
SmartFusion Devices
SmartFusion Devices
A2F060
A2F200
200,000
4,608
8
A2F500
500,000
11,520
24
System Gates
60,000
1,536
8
FPGA Fabric
Tiles (D-flip-flops)
RAM Blocks (4,608 bits)
Flash (Kbytes)
128
16
256
512
SRAM (Kbytes)
64
64
Cortex-M3 with
Memory Protection Unit (MPU)
Yes
No
Yes
Yes
Yes
10/100 Ethernet MAC
External Memory Controller (EMC)
DMA
Yes
24-bit address, 16-bit data
24-bit address, 16-bit data
24-bit address, 16-bit data1
8 Ch
2
8 Ch
2
8 Ch
2
Microcontroller
2
I C
Subsystem (MSS)
SPI
2
2
2
16550 UART
2
2
2
32-Bit Timer
2
2
2
PLL
1
1
22
32 KHz Low Power Oscillator
100 MHz On-Chip RC Oscillator
Main Oscillator (32 KHz to 20 MHz)
ADCs (8-/10-/12-bit SAR)
DACs (12-bit sigma-delta)
Signal Conditioning Blocks (SCBs)
Comparators3
Current Monitors3
Temperature Monitors3
Bipolar High Voltage Monitors3
1
1
1
1
1
1
1
1
1
1
2
34
34
54
104
54
54
104
1
2
1
4
Programmable
Analog
2
8
1
4
1
4
2
8
Notes:
1. Not available on A2F500 for the PQ208 package.
2. Two PLLs are available in CS288 and FG484 (one PLL in FG256 and PQ208).
3. These functions share I/O pins and may not all be available at the same time.
4. Available on FG484 only. PQ208, FG256, and CS288 packages offer the same programmable analog capabilities as A2F200.
Package I/Os: MSS + FPGA I/Os
A2F060
A2F200
A2F500
Device
TQ144
11
CS288
FG256
11
PQ208
8
CS288
8
FG256
8
FG484
8
PQ208
8
CS288
8
FG256
8
FG484
12
Direct Analog Input
Shared Analog Input1
Total Analog Input
Total Analog Output
11
4
4
4
16
16
16
16
16
16
16
20
15
15
1
15
24
24
24
24
24
24
24
32
1
1
1
2
2
2
1
2
2
3
2,3
4
MSS I/Os
214
28
264
22
31
25
41
22
31
25
41
FPGA I/Os
Total I/Os
Notes:
33
68
66
66
78
66
94
665
78
66
128
204
70
112
108
113
135
117
161
113
135
117
1. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.
2. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for the MSS. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
3. 9 MSS I/Os are primarily for 10/00 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS
(1.5 / 1.8 / 2.5, 3.3 V) standards.
4. 10/100 Ethernet MAC is not available on A2F060.
5. EMC is not available on the A2F500 PQ208 package.
4
www.microsemi.com/soc
Fusion
Theꢀworld’sꢀfirstꢀmixedꢀsignalꢀFPGA
Fusion FPGAs integrate configurable analog, large flash memory blocks, comprehensive clock generation and management circuitry and high-performance,
flash-based programmable logic in a monolithic device. The Fusion architecture can be used with soft microcontroller cores, such as the performance-optimized
ARM Cortex-M1, 8051s or Microsemi’s own CoreABC, the smallest soft microcontroller for FPGAs.
•ꢀ IntegratedꢀA/Dꢀconverterꢀ(ADC)ꢀ
withꢀ8-,ꢀ10-ꢀandꢀ12-bitꢀ
resolutionꢀandꢀ30ꢀscalableꢀ
analog input channels
•ꢀ In-systemꢀconfigurableꢀ
analog supports a wide
varietyꢀofꢀapplications
•ꢀ Crystalꢀoscillatorꢀcircuit
•ꢀ Real-timeꢀcounterꢀ(RTC)
•ꢀ FlashꢀFPGAꢀfabric
•ꢀ Ultra-lowꢀpower
•ꢀ Configurationꢀmemoryꢀerrorꢀ
immune
•ꢀ Upꢀtoꢀ1ꢀMBꢀofꢀuserꢀflashꢀmemory
•ꢀ Extensiveꢀclockingꢀresources
•ꢀ AnalogꢀPLLs
•ꢀ Clockꢀmanagement
•ꢀ ADCꢀaccuracyꢀbetterꢀthanꢀ
1ꢀpercent
•ꢀ Reprogrammable
•ꢀ AdvancedꢀI/Oꢀstandards
•ꢀ UserꢀnonvolatileꢀFlashROM
•ꢀ Liveꢀatꢀpower-up
•ꢀ On-chipꢀvoltage,ꢀcurrentꢀandꢀ
temperature monitors
•ꢀ Maximumꢀdesignꢀsecurity
•ꢀ 1ꢀpercentꢀRCꢀoscillator
Fusion Devices
Fusion Devices
AFS090
AFS250ꢀ
AFS600ꢀ
AFS1500ꢀ
Cortex-M1ꢀDevices1
Pigeon Point Devices
MicroBladeꢀDevices
System Gates
M1AFS250ꢀ
M1AFS600ꢀ
M1AFS1500ꢀ
P1AFS15002
P1AFS6002
U1AFS6003
90,000
2,304
Yes
1
250,000
600,000
13,824
Yes
2
1,500,000
38,400
Yes
2
Tilesꢀ(D–flip–flops)ꢀ
6,144
Yes
1
General
Information
AES-protected ISP
PLLs
Globals
18
18
1
18
18
FlashꢀMemoryꢀBlocksꢀ(2ꢀMbits)
TotalꢀFlashꢀMemoryꢀBitsꢀ
FlashROMꢀBitsꢀ
1
2 M
1,024
6
2
4
2 M
1,024
8
4 M
1,024
24
8 M
1,024
60
Memory
RAMꢀBlocksꢀ(4,608ꢀbits)ꢀ
RAMꢀ(Kbits)
27
5
36
6
108
10
270
10
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/OꢀBanksꢀ(+ꢀJTAG)ꢀ
Maximum Digital I/Os
Analog I/Os
15
5
18
6
30
30
10
10
Analog and I/Os
4
4
5
5
75
20
114
24
172
40
252
40
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. Pigeon Point devices only offered in FG484 and FG256 packages.
3. MicroBlade devices only offered in FG256 package.
Package I/Os: Single-/Double-Ended (Analog)
Fusion Mixed Signal FPGAs
Cortex-M1ꢀDevices
Pigeon Point Devices
MicroBladeꢀDevices
QN1083
AFS090
AFS250
AFS600
M1AFS600
P1AFS6001
U1AFS6002
—
AFS1500
M1AFS1500
P1AFS15001
M1AFS250
37/9 (16)
60/16 (20)
—
—
65/15 (24)
93/26 (24)
114/37 (24)
—
—
—
QN1803
—
PQ2084
95/46 (40)
119/58 (40)
172/86 (40)
—
—
FG2565
75/22 (20)
—
119/58 (40)
223/109 (40)
252/126 (40)
FG4845
FG6765
—
—
Notes:
1. Pigeon Point devices only offered in FG484 and FG256 packages.
2. MicroBlade devices only offered in FG256 package.
3. These packages are available only as RoHS-compliant (QNG package specifier).
4. AFS250 and AFS600 PQ208 devices are not pin-compatible.
5. Available in RoHS-compliant and standard leaded packages.
www.microsemi.com/soc
5
Extended Temperature Fusion
Mixed signal integration at extended temperatures
Microsemi Fusion mixed signal FPGAs integrate configurable analog, large flash memory blocks, comprehensive clock generation and management circuitry and
high-performance, flash-based reprogrammable logic in a monolithic device. Innovative Fusion architecture can be used with Microsemi’s soft microcontroller (MCU)
core as well as the performance-maximized 32-bit ARM Cortex-M1 cores. Extended temperature Fusion devices operate at temperatures from 100ºC to as low
as -55ºC.
Extended Temperature Fusion Devices
Extended Temperature Fusion Devices
Cortex-M1ꢀDevices
System Gates
AFS600
AFS1500
M1AFS600
M1AFS1500
600,000
13,824
Yes
2
1,500,000
38,400
Yes
2
Tilesꢀ(D–flip–flops)
AES-Protected ISP
PLLs
Globals
18
18
FlashꢀMemoryꢀBlocksꢀ(2ꢀMbits)
TotalꢀFlashꢀMemoryꢀBits
FlashROMꢀBits
2
4
4 M
1,024
24
8 M
1,024
60
RAMꢀBlocksꢀ(4,608ꢀbits)
RAMꢀ(kbits)
108
10
270
10
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/OꢀBanksꢀ(+ꢀJTAG)
Maximum Digital I/Os
Analog I/Os
30
30
10
10
5
5
172
40
223
40
Package Pins
FG
FG256, FG484
FG256, FG484
6
www.microsemi.com/soc
IGLOO/e
The ultra low power programmable solution
The IGLOO family of reprogrammable, full-featured flash FPGAs is designed to meet the demanding power, area and cost requirements of today’s portable
electronics. Based on nonvolatile flash technology, the 1.2 V to 1.5 V operating voltage family offers the industry’s lowest power consumption—as low as 5 µW.
The IGLOO family supports up to 3,000,000 system gates with up to 504 Kbits of true dual-port SRAM, up to 6 embedded PLLs and up to 620 user I/Os.
Low power applications that require 32-bit processing can use the ARM Cortex-M1 processor without license fee or royalties in M1 IGLOO devices. Developed
specifically for implementation in FPGAs, Cortex-M1 offers an optimal balance between performance and size to minimize power consumption.
•ꢀ UltraꢀlowꢀpowerꢀFPGAs
•ꢀ 1.2ꢀVꢀcoreꢀandꢀI/Oꢀvoltage
•ꢀ 5ꢀµWꢀFlash*Freezeꢀmode
•ꢀ Reprogrammable
•ꢀ Liveꢀatꢀpower-up
•ꢀ AES-protectedꢀin-system
programming (ISP)
•ꢀ Flash*Freezeꢀtechnologyꢀforꢀ
lowest power consumption
•ꢀ UserꢀnonvolatileꢀFlashROM
IGLOO/e Devices
IGLOO Devices
Cortex-M1ꢀDevices1
System Gates
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
M1AGL600
600,000
AGL1000
AGLE600
AGLE3000
M1AGL250
M1AGL1000
M1AGLE3000
30,000
256
768
5
60,000
512
125,000
1,024
3,072
16
250,000
400,000
—
1,000,000
600,000
—
3,000,000
Typical Equivalent
Macrocells
2,048
6,144
24
—
13,824
36
—
24,576
53
—
VersaTilesꢀ(D-flip-flops)
1,536
10
9,216
32
13,824
49
75,264
137
Flash*Freeze Mode
(typical,ꢀµW)
RAMꢀ(1,024ꢀbits)
—
—
18
4
36
8
36
8
54
12
108
24
144
32
108
24
504
112
RAMꢀBlocksꢀ(4,608ꢀbits)
FlashROMꢀKbits
(1,024ꢀbits)
1
1
1
1
1
1
1
1
1
AES-Protected ISP1
Integrated PLLs with CCC2
VersaNetꢀGlobals3
I/OꢀBanks
—
—
6
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
6
Yes
6
18
2
18
2
18
4
18
4
18
4
18
4
18
8
18
8
2
Maximum User I/Os
(packaged device)
81
96
133
143
194
235
300
270
620
Package Pins
UC
CS
UC81
CS81
CS121
QN132
CS81
CS196
QN132
CS81
CS196
CS281
CS281
CS1964
QN1324
QN
QN48
QN68
QN132
VQ100
ꢀꢀVQ
FG
VQ100
VQ100
FG144
VQ100
FG144
FG1445
FG144
FG256
FG484
FG144
FG256
FG484
FG144
FG256
FG484
FG256
FG484
FG484
FG896
Notes:
1. AES is not available for Cortex-M1 IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 devices and above.
4. The M1AGL250 device does not support this package.
I/Os Per Package
IGLOO Devices
AGL030 AGL060 AGL125
AGL250
AGL400
AGL600
AGL1000
M1AGL1000
AGLE600
AGLE3000
Cortex-M1ꢀ
Devices
M1AGL2501
M1AGL600
M1AGLE3000
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O2
Differen- Single- Differen-
Single-
Differen-
tial I/O
Pairs
Single-
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
tial I/O
Pairs
Ended
tial I/O
Pairs
Ended
Ended
I/O Type
I/O2
I/O2
I/O2
QN48
QN68
34
49
66
66
—
77
81
—
—
—
—
—
—
—
—
—
—
96
71
80
—
96
—
—
—
—
—
—
—
—
—
—
—
—
—
13
19
35
24
—
—
—
—
—
—
—
—
—
—
—
35
25
38
—
38
—
—
—
—
—
—
—
—
—
—
—
25
43
53
60
—
—
—
—
—
—
—
—
—
—
—
25
44
53
74
—
—
—
—
—
—
—
—
—
—
—
—
79
—
135
—
—
—
—
—
UC81
—
—
—
—
—
—
—
—
CS81
—
—
—
—
—
—
—
—
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
FG896
Notes:
—
—
—
—
—
—
—
—
71
84
133
97
—
68
87
143
97
—
—
—
—
—
—
—
—
—
—
—
—
—
143
97
178
—
—
—
—
—
—
97
177
215
235
—
97
177
215
300
—
—
—
—
165
—
—
—
—
—
—
—
—
194
—
270
—
341
620
168
310
—
—
—
1. The M1AGL250 device does not support QN132 or CS196 packages.
2. Each used differential pair reduces the number of single-ended I/Os available by two.
www.microsemi.com/soc
7
IGLOO nano
Theꢀindustry’sꢀlowestꢀpower,ꢀsmallest-sizeꢀsolution
IGLOO nano products offer groundbreaking possibilities in power, size, lead-times, operating temperature and cost. Available in logic densities from 10,000 to
250,000 gates, the 1.2 V to 1.5 V IGLOO nano devices have been designed for high-volume applications where power and size are key decision criteria.
IGLOO nano devices are perfect ASIC or ASSP replacements, yet retain the historical FPGA advantages of flexibility and quick time-to-market in low power
and small footprint profiles.
•ꢀ UltraꢀlowꢀpowerꢀinꢀFlash*Freezeꢀ
mode,ꢀasꢀlowꢀasꢀ2ꢀµWꢀ
•ꢀ Zeroꢀlead-timeꢀonꢀselectedꢀdevicesꢀ
•ꢀ Knownꢀgoodꢀdieꢀsupportedꢀ
•ꢀ 1.2ꢀVꢀtoꢀ1.5ꢀVꢀsingleꢀ
voltage operation
•ꢀ EmbeddedꢀSRAMꢀandꢀ
nonvolatileꢀmemoryꢀ(NVM)ꢀ
•ꢀ Varietyꢀofꢀsmallꢀfootprintꢀ
packages as small as 3x3 mm
•ꢀ EnhancedꢀI/Oꢀfeaturesꢀ
•ꢀ ISPꢀandꢀsecurityꢀ
•ꢀ Enhancedꢀcommercialꢀtemperatureꢀ
•ꢀ Reprogrammableꢀflashꢀtechnologyꢀ
•ꢀ Clockꢀconditioningꢀcircuitsꢀ(CCCs)ꢀ
and PLLs
IGLOO nano Devices
IGLOO nano Devices
AGLN010
AGLN020
20,000
AGLN060ꢀ
AGLN125ꢀ
AGLN250
System Gates
10,000
86
260
2
60,000
512
1,536
10
125,000
250,000
Typical Equivalent Macrocells
VersaTilesꢀ(D-flip-flops)
Flash*FreezeꢀModeꢀ(typical,ꢀµW)
RAMꢀKbits1ꢀ(1,024ꢀbits)
4,608-BitꢀBlocks1
172
520
4
1,024
3,072
16
36
8
2,048
6,144
24
36
8
—
—
1
—
—
1
18
4
FlashROMꢀKbitsꢀ(1,024ꢀbits)
AES-Protected ISP1
1
1
1
—
—
4
—
—
4
Yes
1
Yes
1
Yes
1
Integrated PLL in CCCs1,2
VersaNetꢀGlobals
18
18
2
18
4
I/OꢀBanks
2
3
2
Maximum User I/Os (packaged device)
Known Good Die User I/Os
34
34
52
52
71
71
71
68
68
71
Package Pins
UC
CS
UC36
UC81
CS81
QN68
CS81
CS81
CS81
QN
QN48
ꢀꢀVQ
VQ100
VQ100
VQ100
Notes:
1. AGLN030 and smaller devices do not support this feature.
2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
3. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets and FPGA fabric user’s guides.
I/Os Per Package
IGLOO nano Devices
Known Good Die
UC36
AGLN010
AGLN020
AGLN060
AGLN125
AGLN250
34
23
34
—
—
—
—
52
—
—
49
52
52
—
71
—
—
—
—
60
71
71
—
—
—
—
60
71
68
—
—
—
—
60
68
QN48
QN68
UC81
CS81
VQ100
Note:
* When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one.
8
www.microsemi.com/soc
IGLOO PLUS
The low power FPGA with enhanced I/O capabilities
IGLOO PLUS products deliver unrivaled low power and I/O features in a feature-rich programmable device, offering up to 64 percent more I/Os than the
award-winning IGLOO products and supporting independent Schmitt trigger inputs, hot-swapping and Flash*Freeze bus hold. Ranging from 30,000 to
125,000 gates, the 1.2 V to 1.5 V IGLOO PLUS devices have been optimized to meet the needs of I/O-intensive, power-conscious applications that require
exceptional features.
•ꢀ I/O-optimizedꢀFPGAꢀ
•ꢀ Smallꢀfootprintꢀandꢀ
low-cost packages
•ꢀ 1.2ꢀVꢀtoꢀ1.5ꢀVꢀsingleꢀ
voltage operation
•ꢀ CCCsꢀandꢀPLLsꢀ
•ꢀ UltraꢀlowꢀpowerꢀinꢀFlash*Freezeꢀ
mode,ꢀasꢀlowꢀasꢀ5ꢀµW
•ꢀ EmbeddedꢀSRAMꢀNVM
•ꢀ AES-protectedꢀISP
•ꢀ Reprogrammableꢀ
flashꢀtechnologyꢀ
•ꢀ EnhancedꢀI/Oꢀfeaturesꢀ
•ꢀ Lowꢀpowerꢀactiveꢀcapabilityꢀ
IGLOO PLUS Devices
IGLOO PLUS Devices
AGLP030ꢀ
AGLP060ꢀ
AGLP125
System Gates
30,000
256
792
5
60,000
512
1,584
10
125,000
Typical Equivalent Macrocells
VersaTilesꢀ(D-flip-flops)
Flash*FreezeꢀModeꢀ(typical,ꢀµW)
RAMꢀ(1,024ꢀbits)
1,024
3,120
16
36
8
—
18
4,608-BitꢀBlocks
—
4
FlashROMꢀKbitsꢀ(1,024ꢀbits)
AES-Protected ISP
1
1
1
—
Yes
1
Yes
1
Integrated PLL in CCCs1
VersaNetꢀGlobals2
—
6
18
18
4
I/OꢀBanks
4
4
Maximum User I/Os
(packaged device)
120
157
212
Package Pins
CS
CS201, CS289
CS201, CS289
CS281, CS289
ꢀꢀVQ
VQ128
VQ176
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
I/Os Per Package
IGLOO PLUS Devices
AGLP030
AGLP060
AGLP125
I/O Type
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
CS201
120
—
157
—
—
212
212
—
CS281
CS289
120
101
—
157
—
VQ128
VQ176
137
—
Note:
* When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one.
www.microsemi.com/soc
9
ProASIC3/E
Theꢀlowꢀpower,ꢀlow-costꢀFPGAꢀsolution
The ProASIC3 series of flash FPGAs offers a breakthrough in power, price, performance, density and features for today’s most demanding high-volume applications.
ProASIC3 devices support the ARM Cortex-M1 processor, offering the benefits of programmability and time-to-market at low cost. ProASIC3 devices are based
on nonvolatile flash technology and support 30,000 to 3,000,000 gates and up to 620 high-performance I/Os. For automotive applications, selected ProASIC3
devices are qualified to the AEC-Q100 and are available with AEC T1 screening and PPAP documentation.
•ꢀ Lowꢀpower
•ꢀ Lowꢀcost
•ꢀ Configurationꢀmemoryꢀerrorꢀimmune
•ꢀ Clockꢀmanagement
•ꢀ UserꢀnonvolatileꢀFlashROM
•ꢀ SecureꢀISP
•ꢀ Singleꢀchip,ꢀsingleꢀvoltage
•ꢀ Nonvolatile,ꢀreprogrammable
•ꢀ Liveꢀatꢀpower-up
•ꢀ Maximumꢀdesignꢀsecurity
•ꢀ AdvancedꢀI/Oꢀstandards
•ꢀ Highꢀperformance
ProASIC3/E Devices
ProASIC3/E Devices
ꢀCortex-M1ꢀDevices
System Gates
A3P030
A3P060
A3P125
A3P250
M1A3P250
250,000
A3P400
M1A3P400
400,000
A3P600
A3P1000
A3PE600
A3PE1500
A3PE3000
M1A3P600 M1A3P1000
M1A3PE1500 M1A3PE3000
30,000
256
60,000
512
125,000
1,024
600,000
—
1,000,000
—
600,000
—
1,500,000
—
3,000,000
—
Typical Equivalent
Macrocells
2,048
—
ꢀVersaTilesꢀ(D-flip-flops)
ꢀRAMꢀ(1,024ꢀbits)
768
—
1,536
18
3,072
36
6,144
36
9,216
54
13,824
108
24,576
144
13,824
108
38,400
270
75,264
504
ꢀ4,608-BitꢀBlocks
—
4
8
8
12
24
32
24
60
112
ꢀFlashROMꢀKbitsꢀ
ꢀ(1,024ꢀbits)
1
1
1
1
1
1
1
1
1
1
AES-Protected ISP1
Integrated PLL in CCCs
ꢀVersaNetꢀGlobals
—
—
6
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
6
Yes
6
Yes
6
18
18
18
18
18
18
18
18
18
ꢀI/OꢀBanks
2
2
2
4
4
4
4
8
8
8
Maximum User I/Os
(packaged device)
81
96
133
157
194
235
300
270
444
620
Package Pins
QFN
QN48
QN68
QN132
QN1322
QN1322, 3
QN132
CS
ꢀꢀVQ
TQ
CS121
VQ1002
TQ144
VQ100
VQ1002
TQ144
PQ208
FG1442
VQ1002
PQ
FG
PQ208
FG1442
FG2562, 3
PQ208
FG144
FG256
FG484
PQ208
FG144
FG256
FG484
PQ208
FG1442
FG2562
FG4842
PQ208
FG256
FG484
PQ208
FG484
FG676
PQ208
FG324
FG484
FG896
FG1442
Notes:
1. AES is not available for Cortex-M1 ProASIC3 devices.
2. Available as automotive “T” grade
3. The M1A3P250 device does not support this package.
I/Os Per Package
ProASIC3
Devices
Cortex-M1ꢀ
Devices
A3P030 A3P060 A3P125
A3P250
M1A3P250*
A3P400
M1A3P400
A3P600
A3P1000
A3PE600
A3PE1500
M1A3PE1500
A3PE3000
M1A3P600
M1A3P1000
M1A3PE3000
Single- Single- Single- Single- Differen- Single- Differen- Single- Differen- Single- Differen- Single- Differen- Single- Differen- Single- Differen-
I/O Type
Ended
I/O
Ended
I/O
Ended Ended tial I/O Ended tial I/O Ended tial I/O Ended tial I/O Ended tial I/O Ended tial I/O Ended tial I/O
I/O
I/O
Pairs
I/O
Pairs
I/O
Pairs
I/O
Pairs
I/O
Pairs
I/O
Pairs
I/O
Pairs
ꢀQN48
34
49
81
—
77
—
—
—
—
—
—
80
96
71
91
—
96
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ꢀQN68
—
84
—
87
—
19
—
13
—
34
24
38
—
—
—
—
—
—
—
34
25
38
—
—
—
—
—
—
—
—
35
25
43
—
—
—
—
—
—
—
—
35
25
44
—
—
—
—
—
—
—
—
65
—
79
—
—
—
—
—
—
—
—
65
—
—
—
—
—
—
—
ꢀQN132
ꢀCS121
ꢀVQ100
ꢀTQ144
ꢀPQ208
ꢀFG144
ꢀFG256
ꢀFG324
—
—
—
—
—
—
—
—
—
71
68
—
—
—
—
—
—
—
100
133
97
—
—
—
—
—
—
—
—
151
97
151
97
178
—
154
97
177
—
154
97
177
—
147
—
147
—
147
—
65
—
—
157
165
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
221
110
ꢀFG484
194
38
235
60
300
74
270
135
280
139
341
168
ꢀFG676
ꢀFG896
Note:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
444
—
222
—
—
—
620
310
10
* M1A3P250 does not support the FG256 and QN132 packages.
ProASIC3 nano
The lowest-cost solution with enhanced I/O capabilities
Microsemi’s innovative ProASIC3 nano devices bring a new level of value and flexibility to high-volume markets. When measured against the typical project
metrics of performance, cost, flexibility and time-to-market, ProASIC3 nano devices provide an attractive alternative to ASICs and ASSPs in fast moving or highly
competitive markets. Customer-driven total system cost reduction was a key design criterium for the ProASIC3 nano program. Reduced device cost, availability of
known good die, a single-chip implementation and a broad selection of small footprint packages all contribute to lower total system costs.
•ꢀ 1.5ꢀVꢀcoreꢀforꢀlowꢀpower
•ꢀ EmbeddedꢀSRAMꢀNVM
•ꢀ EnhancedꢀI/Oꢀfeatures
•ꢀ ISPꢀandꢀsecurity
•ꢀ Zeroꢀlead-timeꢀonꢀselectedꢀdevices
•ꢀ CCCsꢀandꢀPLLs
•ꢀ Knownꢀgoodꢀdieꢀsupported
•ꢀ 350ꢀMHzꢀsystemꢀperformance
•ꢀ Configurationꢀmemoryꢀerrorꢀimmune
•ꢀ Enhancedꢀcommercialꢀtemperature
•ꢀ Reprogrammableꢀflashꢀtechnology
ProASIC3 nano Devices
ProASIC3 nano Devices
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
System Gates
10,000
86
260
—
20,000
172
520
—
60,000
512
1,536
18
125,000
250,000
Typical Equivalent Macrocells
VersaTilesꢀ(D-flip-flops)
RAM1ꢀ(1,024ꢀbits)
1,024
3,072
36
8
2,048
6,144
36
8
4,608-BitꢀBlocks1
—
—
4
FlashROMꢀKbitsꢀ(1,024ꢀbits)
AES-Protected ISP1
1
1
1
1
1
—
—
Yes
1
Yes
1
Yes
1
Integrated PLL in CCCs1
VersaNetꢀGlobals
—
—
4
4
18
18
2
18
4
I/OꢀBanks
2
3
2
Maximum User I/Os (packaged device)
Known Good Die User I/Os
34
34
49
52
71
71
71
68
68
71
Package Pin
QN
ꢀꢀVQ
QN48
QN68
VQ100
VQ100
VQ100
Notes:
1. A3PN030 and smaller devices do not support this feature.
2. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets and FPGA fabric user’s guides.
I/Os Per Package
ProASIC3 nano Devices
Known Good Die
QN48
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
34
34
—
—
52
—
49
—
71
—
—
71
71
—
—
71
68
—
—
68
QN68
VQ100
www.microsemi.com/soc 11
ProASIC3L
Balancingꢀlowꢀpower,ꢀperformanceꢀandꢀlowꢀcost
ProASIC3L FPGAs feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation ProASIC3 FPGAs and orders of
magnitude lower power than SRAM competitors, combining dramatically reduced power consumption with up to 350 MHz operation. The ProASIC3L family also
supports the free implementation of an FPGA-optimized 32-bit ARM Cortex-M1 processor, enabling system designers to select Microsemi’s flash FPGA solution
that best meets their speed and power design requirements, regardless of application or volume. Optimized software tools using power-driven layout (PDL)
provide instant power reduction capabilities.
•ꢀ Lowꢀpowerꢀ1.2ꢀVꢀtoꢀ1.5ꢀVꢀ
core operation
•ꢀ Upꢀtoꢀ350ꢀMHzꢀ
systemꢀperformance
•ꢀ Configurationꢀmemoryꢀerrorꢀ
immune
•ꢀ Reprogrammableꢀ
flashꢀtechnology
•ꢀ 700ꢀMbpsꢀDDR,ꢀLVDSꢀ
•ꢀ EnhancedꢀI/Oꢀfeatures
•ꢀ ISPꢀandꢀsecurity
•ꢀ CCCsꢀandꢀPLLs
capable I/Os
•ꢀ EmbeddedꢀSRAMꢀandꢀNVM
•ꢀ Flash*Freezeꢀtechnologyꢀ
forꢀlowestꢀpower
ProASIC3L Low Power Devices
ProASIC3L Devices
Cortex-M1ꢀDevices
System Gates
A3P250L
A3P600L
A3P1000L
A3PE3000L
M1A3P600L
M1A3P1000L
M1A3PE3000L
250,000
600,000
1,000,000
3,000,000
VersaTilesꢀ(D-flip-flops)
RAMꢀ(1,024ꢀbits)
6,144
36
8
13,824
108
24
24,576
144
32
75,264
504
112
1
4,608-BitꢀBlocks
FlashROMꢀKbitsꢀ(1,024ꢀbits)
AES-Protected ISP1
Integrated PLL in CCCs2
VersaNetꢀGlobals
I/OꢀBanks
1
1
1
Yes
1
Yes
1
Yes
1
Yes
6
18
4
18
18
18
4
4
8
Maximum User I/Os
(packaged device
157
235
300
620
Package Pins
ꢀꢀVQ
PQ
VQ100
PQ208
PQ208
FG144, FG256, FG484
PQ208
FG144, FG256, FG484
PQ208
FG324, FG484, FG896
FG
FG144, FG256
Notes:
1
2
AES is not available for Cortex-M1 ProASIC3L devices.
For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
I/Os Per Package
ProASIC3L Devices
A3P250L
A3P600L
A3P1000L
A3PE3000L
Cortex-M1ꢀDevices
M1A3P600L
M1A3P1000L
M1A3PE3000L
Single-
Ended I/O
Differential
I/O Pairs
Single-
Ended I/O
Differential
I/O Pairs
Single-
Ended I/O
Differential
I/O Pairs
Single-
Ended I/O
Differential
I/O Pairs
I/O Type
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
68
151
97
13
34
24
38
—
—
—
—
154
97
—
35
25
43
—
60
—
—
154
97
—
35
25
44
—
74
—
—
147
—
—
65
—
157
—
177
—
177
—
—
—
221
341
620
110
168
310
—
235
—
300
—
—
12 www.microsemi.com/soc
Military ProASIC3/EL
LowꢀpowerꢀFPGAsꢀforꢀmilitaryꢀapplicationsꢀ
PLUS
Building on the successful heritage of the Military ProASIC
family, Military ProASIC3 FPGAs offer higher performance, greater density and more memory, while
at the same time offering high reliability combined with compact single-chip logic integration, live at power-up operation and reprogrammability. Military ProASIC3/EL
FPGAs have demonstrated immunity to configuration upsets caused by atmospheric neutrons.
• Supports single-voltage
system operation
• Up to 504 Kbits of true
dual-port SRAM
• ISP protected using on-chip 128-bit
advanced encryption
• Standard (AES) decryption via
JTAG (IEEE 1532–compliant)
• 3,000,000 system gates
• Live-at-power-up level 0 support
Military ProASIC3 Devices
Military ProASIC3 Devices
Cortex-M1ꢀDevices1
System Gates
A3P250
A3PE600L
A3P1000
A3PE3000L
M1A3P1000
M1A3PE3000L
250,000
600,000
13,824
108
24
1,000,000
3,000,000
VersaTilesꢀ(D-flip-flops)
RAMꢀ(1,024ꢀbits)
6,144
36
8
24,576
144
32
75,264
504
112
1
4,608-BitꢀBlocks
FlashROMꢀ(Kbits)
AES-Protected ISP2
Integrated PLL in CCCs
VersaNetꢀGlobals
I/OꢀBanks
1
1
1
Yes
1
Yes
6
Yes
1
Yes
6
18
4
18
18
18
8
4
8
Maximum User I/Os
68
270
154
620
Package Pins
ꢀꢀVQ
PQ
100
208
144
FG
484
484, 896
Notes:
1. Refer to the ARM Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3/EL devices.
PLUS
Military ProASIC
Reprogrammable,ꢀnonvolatileꢀmilitaryꢀFPGAsꢀ
PLUS
Military ProASIC
is the industry’s first nonvolatile, reprogrammable FPGA with testing covering the full military temperature range (–55ºC to 125ºC), with available
PLUS
MIL-STD-883 Class B screening. The flash-based reprogrammable interconnect used in Microsemi’s ProASIC
FPGAs has been proven to be immune to
configuration changes caused by atmospheric neutrons, which plague SRAM-based FPGAs in high-reliability applications.
Military ProASICPLUS Devices
Military ProASICPLUS Devices
Maximum System Gates
Tiles (registers)
RAMꢀKbitsꢀ(1,024ꢀbits)
RAMꢀBlocksꢀ(256x9)
LVPECL
APA300
300,000
8,192
72
APA600
600,000
21,504
126
56
APA1000
1,000,000
56,320
198
88
32
2
2
2
PLL
2
2
2
Global Networks
Maximum Clocks
Maximum User I/Os
JTAGꢀISP
4
4
4
32
56
88
290
Yes
Yes
454
Yes
Yes
712
Yes
Yes
PCI
Package Pins
CQ
CG
208, 352
208, 352
624
208, 352
624
www.microsemi.com/soc 13
I/O Table
SmartFusion
Fusion
A2F060
A2F200
A2F500
AFS090
AFS250
AFS600
AFS600
AGL600
AFS1500
AFS1500
Ext. Temp. Fusion
IGLOO/e
AGL030
AGLN030
AGLP030
A3P030
AGL060
AGLN060
AGLP060
A3P060
AGL125
AGLN125
AGLP125
A3P125
AGL250
AGL400
A3P400
AGL1000
A3P1000
AGLE600
A3PE600
A3PE600L
AGLE3000
A3PE3000
IGLOO nano
AGLN010
A3PN010
AGLN020
A3PN020
AGLN250
IGLOO PLUS
ProASIC3/E
A3P250
A3PN250
A3P250L
A3P250
A3P600
A3P600L
APA600
A3PE1500
ProASIC3 nano
ProASIC3L
A3PN030
A3PN060
A3PN125
A3P1000L
A3P1000
APA1000
A3PE3000L
A3PE3000L
Military ProASIC3/EL
Military ProASICPLUS
APA300
Size (mm)
Name
Pitch (mm)
23
3x3
UC36
0.40
52
52
66
66
4x4
5x5
UC81
CS81
0.40
0.50
0.50
0.40
0.50
0.40
0.50
0.50
0.50
0.50
0.50
0.50
1.00
0.80
0.50
0.40
1.00
1.00
0.50
0.40
1.00
1.00
0.50
1.00
1.27
0.50
0.50
60
96
60
60
6x6
CS121
QN48
34
34
6x6
133
84
143/35
87/19
143/35
8x8
CS196
QN68
49
49
81
8x8
80
8x8
QN132
CS201
QN108
QN180
CS281
CS288
FG144
CS289
VQ100
VQ128
FG256
FG324
TQ144
VQ176
FG484
FG676
PQ208
FG896
CG624
CQ208
CQ352
120
157
8x8
37/9 (16)
10x10
10x10
10x10
11x11
13x13
14x14
14x14
14x14
17x17
19x19
20x20
20x20
23x23
27x27
28x28
31x31
32.5x32.5
29.21x29.21
48x48
60/16 (20)
65/15 (24)
212
215/53
97/25
215/53
97/25
112
96
135
135
97
212
71
97/24
68/13
97/25
120
77
157
71
101
108
75/22 (20)
117
114/37 (24) 157/38
178/38
117
119/58 (40) 177/43
177/44
165/79
119/58 (40)
221/110
341/168
70
91
100
137
161
113
194/38
151/34
204
113
172/86 (40) 235/60
95/46 (40) 154/35
300/74
154/35
270/135
147/65
223/109(40) 280/139
252/126(40) 444/222
147/65
133
93/26 (24) 151/34
147/65
620/310
440
158
248
440
158
248
158
248
Notes: # / # structure shows single-ended/double-ended I/Os. Fusion and Ext. Temp. Fusion I/O counts are in italics. Value in parentheses for Fusion is analog I/Os. SmartFusion values are total analog, MSS and FPGA I/Os.
Go to www.microsemi.com/soc for information regarding previous generations of flash and antifuse FPGAs.
Please refer to the SoC Products Group’s website at www.microsemi.com/soc and appropriate product datasheets for the latest device information and valid ordering codes.
14 www.microsemi.com/soc
www.microsemi.com/soc 15
FPGA Packages
Key:
f – family bs – package body size excluding leads ps – overall package dimensions including package leads
h – package thickness p – pin pitch / ball pitch
FG896
FG324
CS289
CS121
ProASIC3E1
ProASIC3L1
f
IGLOO PLUS
f
IGLOO
f
IGLOOe1
f
ProASIC3E1
ProASIC3L1
ps 14x14 mm
ProASIC3
ps 6x6 mm
ps 19x19 mm
h
p
1.20 mm
0.80 mm
Military
h
p
1.63 mm
1.00 mm
h
p
0.90 mm
0.50 mm
ProASIC3/EL1
ps 31x31 mm
h
2.23 mm
p
1.00 mm
CS288
SmartFusion
ps 11x11 mm
CS81
f
IGLOO
f
FG256
SmartFusion
Fusion1, 3, 4
IGLOO1
IGLOO nano
ps 5x5 mm
f
h
p
1.05 mm
0.50 mm
h
p
0.80 mm
0.50 mm
FG676
f
ProASIC3E1
IGLOOe
Fusion1
ProASIC31, 2
ProASIC3E2
ProASIC3L1
ps 27x27 mm
h
2.23 mm
CS281
UC81
p
1.00 mm
ps 17x17 mm
IGLOO1
f
IGLOO
f
h
p
1.60 mm
1.00 mm
IGLOO nano
ps 4x4 mm
IGLOO PLUS
ps 10x10 mm
h
p
0.80 mm
0.40 mm
h
p
1.05 mm
0.50 mm
FG484
FG144
f
SmartFusion
f
IGLOO1
CS201
IGLOO PLUS
UC36
IGLOO nano
Fusion1, 3
ProASIC31
ProASIC3L1
IGLOO1
f
f
IGLOOe1
Military
ps 8x8 mm
ps 3x3 mm
ProASIC3/EL1
ProASIC31, 2
ProASIC3E1, 2
ProASIC3L1
h
0.89 mm
h
0.80 mm
p
0.50 mm
p
0.40 mm
ps 13x13 mm
h
p
1.45 mm
1.00 mm
Military
ProASIC3/EL1
CS196
IGLOO
ps 23x23 mm
f
h
2.23 mm
ps 8x8 mm
p
1.00 mm
h
1.11 mm
p
0.50 mm
QN180
Fusion
QN108
QN48
f
Fusion
f
IGLOO
f
ps 8x8 mm
IGLOO nano
ProASIC3
ProASIC3 nano
ps 10x10 mm
h
p
0.75 mm
0.50 mm
h
p
0.75 mm
0.50 mm
ps 6x6 mm
h
0.90 mm
p
0.40 mm
QN132
IGLOO
QN68
IGLOO
f
f
ProASIC3
ps 8x8 mm
IGLOO nano
ProASIC3
h
0.75 mm
ProASIC3 nano
p
0.50 mm
ps 8x8 mm
h
0.90 mm
p
0.40 mm
Notes:
1
2
3
4
Includes Cortex-M1 devices.
FG256 and FG484 are footprint-compatible for ProASIC3 and ProASIC3E.
Pigeon Point devices are only offered in FG484 and FG256.
MicroBlade devices are only offered in FG256.
16 www.microsemi.com/soc
PQ208
CQ352
f
SmartFusion
f
Military
ProASICPLUS
ps 48x48 mm
Fusion1
ProASIC31
ProASIC3E1
ProASIC3L1
h
p
2.67 mm
0.50 mm
Military
ProASIC3/EL1
bs 28x28 mm
ps 30.6x30.6 mm
h
3.40 mm
p
0.50 mm
TQ144
ProASIC3
f
bs 20x20 mm
ps 22x22 mm
h
1.40 mm
p
0.50 mm
VQ176
IGLOO PLUS
f
bs 20x20 mm
ps 22x22 mm
CQ208
f
Military
ProASICPLUS
h
1.00 mm
p
0.40 mm
ps 29.21x29.21 mm
h
2.67 mm
p
0.50 mm
VQ128
IGLOO PLUS
f
bs 14x14 mm
ps 16x16 mm
h
1.00 mm
p
0.40 mm
VQ100
f
IGLOO1
IGLOO nano
ProASIC31
ProASIC3 nano
ProASIC3L
Military
ProASIC3/EL1
bs 14x14 mm
ps 16x16 mm
h
p
1.00 mm
0.50 mm
CG624
f
Military
ProASICPLUS
ps 32.5x32.5 mm
h
4.94 mm
p
1.27 mm
Refer to the Package Mechanical Drawings document located at www.microsemi.com/soc/documents/PckgMechDrwngs.pdf for more information concerning package dimensions.
www.microsemi.com/soc 17
Axcelerator
Firstꢀforꢀspeedꢀandꢀperformanceꢀ
The Axcelerator FPGA family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million
equivalent system gates. Utilizing the AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO
control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. Based upon 0.15 µm, seven-layers-of-metal CMOS antifuse process
technology, 350 MHz system performance.
•ꢀ 500+ꢀMHzꢀinternalꢀperformance
•ꢀ 500+ꢀMHzꢀembeddedꢀFIFOs
•ꢀ 6ꢀlevelsꢀofꢀlogicꢀatꢀ156+ꢀMHz
•ꢀ 8ꢀglobalꢀclocksꢀperꢀdevice
•ꢀ Secureꢀprogrammingꢀtechnologyꢀ
is designed to prevent reverse
engineeringꢀandꢀdesignꢀtheft
•ꢀ 1.5ꢀV,ꢀ1.8ꢀV,ꢀ2.5ꢀV,ꢀandꢀ3.3ꢀVꢀ
mixed-voltage operation
•ꢀ 4.5ꢀkbitsꢀvariable-aspectꢀRAMꢀ
blocks with built-in FIFO control
•ꢀ PLLꢀoutputꢀupꢀtoꢀ1ꢀGHzꢀandꢀ
8ꢀPLLsꢀperꢀdevice
•ꢀ Bank-selectableꢀI/Os—8ꢀbanksꢀ
per chip
Axcelerator Devices
Axcelerator Device
AX125
AX250
AX500
AX1000
AX2000
Capacity
(in equivalent system gates)
125,000
250,000
500,000
1,000,000
2,000,000
Typical Gates
82,000
154,000
1,408
2,816
2,816
12
286,000
2,688
5,376
5,376
16
612,000
6,048
12,096
12,096
36
1,060,000
10,752
21,504
21,504
64
Registerꢀ(R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
NumberꢀofꢀCoreꢀRAMꢀBlocks
TotalꢀBitsꢀofꢀCoreꢀRAM
Clocks (hardwired)
Clocks (routed)
672
1,344
1,344
4
18,432
55,296
4
73,728
4
165,888
4
294,912
4
4
4
4
4
4
4
PLLs
8
8
8
8
8
I/OꢀBanks
8
168
8
8
8
8
Maximum User I/Os
MaximumꢀLVDSꢀChannels
TotalꢀI/OꢀRegisters
Speed Grades
248
336
516
684
84
124
168
258
342
504
744
1,008
Std., –1, –2
C, I, M
1,548
Std., –1, –2
C, I, M
2,052
Std., –1, –2
C, I, M
Std., –1, –2
C, I
Std., –1, –2
C, I, M
Temperature Grades
I/Os Per Package
Axcelerator Device
AX125
AX250
AX500
AX1000
AX2000
PQ
208
208
BG
729
484, 676, 896
352
FG
256, 324
256, 484
208, 352
484, 676
208, 352
896, 1152
256, 352
624
CQ
CG/LG
624
18 www.microsemi.com/soc
SX-A
Reducingꢀtheꢀcostꢀofꢀperformance
The SX-A family of FPGAs offers a cost-effective, single-chip solution for low-power, high-performance designs. SX-A devices can be used to generate system-wide
savings by integrating multiple functions into a single-chip solution. Providing a combination of performance, security, and low power, SX-A FPGAs decrease the
premium for performance while providing a solution that is highly resistant to reverse engineering.
•ꢀ 12,000ꢀtoꢀ108,000ꢀusableꢀ
system gates
•ꢀ Hot-swapꢀcompliantꢀI/Os
•ꢀ 66ꢀMHz,ꢀ64-bitꢀ3.3ꢀVꢀ/ꢀ5.0ꢀVꢀPCIꢀ
performanceꢀ(supportingꢀtarget,ꢀ
master and master/target)
•ꢀ 2.5ꢀV,ꢀ3.3ꢀV,ꢀandꢀ5.0ꢀVꢀ
mixed-voltage support
•ꢀ Power-upꢀandꢀpower-downꢀ
friendlyꢀ(noꢀsequencingꢀrequiredꢀ
forꢀsupplyꢀvoltages)
•ꢀ 250ꢀMHzꢀsystemꢀperformance
•ꢀ 350ꢀMHzꢀinternalꢀperformance
•ꢀ 100%ꢀresourceꢀutilizationꢀ
withꢀ100%ꢀpinꢀlocking
SX-A Devices
SX-A Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
72,000
108,000
6,036
Typical Gates
8,000
16,000
32,000
48,000
2,880
1,800
1,080
1,980
249
System Gates
12,000
24,000
Logic Modules
768
1,452
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
512
924
4,024
256
528
2,012
512 *
990
4,024
130
180
360
3
3
3
3
Quadrant Clocks
BoundaryꢀScanꢀTesting
3.3ꢀVꢀ/ꢀ5ꢀVꢀPCI
0
Yes
0
Yes
0
4
Yes
Yes
Yes
Yes
Yes
Yes
Input Set-Up (external)
Speed Grades
0 ns
0 ns
0 ns
0 ns
–F, Std., –1, –2
C, I, A, M
–F, Std., –1, –2
C, I, A, M
–F, Std., –1, –2
C, I, A, M, B
–F, Std., –1, –2
C, I, A, M, B
Temperature Grades
I/Os Per Package
SX-A Devices
A54SX08A
A54SX16A
A54SX32A
A54SX72A
PQ
VQ
TQ
BG
FG
CQ
208
208
208
208
100, 144
144
100, 144
144, 256
100, 144, 176
329
144, 256, 484
84, 208, 256
256, 484
208, 256
www.microsemi.com/soc 19
MX
Theꢀprice/performanceꢀleaderꢀatꢀ5.0ꢀVꢀ
Featuring very low power consumption and the industry’s highest design security, MX FPGAs offer designers a reliable, single-chip ASIC alternative. MX devices
provide high performance while shortening the system design and development cycle. Offering an efficient, flexible 5.0 V architecture, MX is an ideal high-volume
platform for integrating your legacy PLDs into a single device. Example applications include high-speed controllers and address decoding, peripheral bus
interfaces, DSP, and coprocessor functions.
•ꢀ Single-chipꢀASICꢀalternative
•ꢀ 3,000ꢀtoꢀ54,000ꢀsystemꢀgates
•ꢀ Fastꢀwide-decodeꢀcircuitry
•ꢀ PCIꢀcompliant
•ꢀ Ceramicꢀdevicesꢀavailableꢀ
to DSCC SM
•ꢀ Upꢀtoꢀ202ꢀuser-programmableꢀ
I/O pins
•ꢀ Containsꢀembeddedꢀdual-portꢀ
SRAMꢀmodules
•ꢀ Upꢀtoꢀ2.5ꢀkbitsꢀconfigurableꢀ
dual-portꢀSRAM
•ꢀ Highꢀperformanceꢀ
•ꢀ QMLꢀcertification
mixed-voltage solution
MX Devices
MX Devices
System Gates
SRAMꢀBits
Sequential
A40MX02
3,000
—
A40MX04
6,000
—
A42MX09
14,000
—
A42MX16
24,000
—
A42MX24
36,000
—
A42MX36
54,000
2,560
1,230
1,184
24
—
—
348
624
954
Combinatorial
Decode
295
547
336
608
912
—
—
—
—
24
Clock-to-Out
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAMꢀModules
(64x4ꢀorꢀ32x8)
—
—
—
—
—
10
Dedicated Flip-Flops
Clocks
—
1
—
1
348
2
624
2
954
2
1,230
6
Maximum Flip-Flops
User I/Os (maximum)
PCI
147
57
—
273
69
—
516
104
—
928
140
—
1,410
176
Yes
Yes
1,822
202
Yes
Yes
BoundaryꢀScanꢀTestꢀ(BST)
Speed Grades
—
—
—
—
–F, Std., –1, –2, –3 –F, Std., –1, –2, –3 –F, Std., –1, –2, –3 –F, Std., –1, –2, –3 –F, Std., –1, –2, –3 –F, Std., –1, –2, –3
Temperature Grades
C, I, M, A
C, I, M, A
C, I, M, A
C, I, M, A
C, I, M, A
C, I, M, A, B
I/Os Per Package
MX Devices
A40MX02
44, 68
100
A40MX04
44, 68, 84
100
A42MX09
84
A42MX16
A42MX24
84
A42MX36
PL
84
100, 160, 208
100
PQ
VQ
TQ
CQ
BG
100, 160
100
160, 208
208, 240
80
80
176
176
176
208, 256
272
20 www.microsemi.com/soc
Design Environment for Microsemi Flash Devices
Embedded Design
FPGA Design
®
Microsemi’s Libero Integrated Design Environment (IDE) is a comprehensive
software toolset for designing with all Microsemi FPGAs. Libero IDE includes
Software IDE
®
(SoftConsole, Keil, IAR)
industry-leading synthesis, simulation and debug tools from Synopsys
®
and Mentor Graphics, as well as innovative timing and power optimization
MSS Configurator*
and analysis.
MSS Configuration – Analog Configuration
Microsemi’s SmartDesign tool simplifies the use of Microsemi IP in user
designs as well as offering a simple way to build on-chip processors with
custom peripherals. Most Microsemi IP cores are now included by default
in Libero IDE as either obfuscated or RTL versions, depending on the
license selected.
Design Entry and IP Libraries
Simulation and Synthesis
Compile and Layout
Timing and Power Analysis
Hardware Debug
Drivers and Sample Projects
Application Development
Build Project
Simulation
Software Debug
For embedded designers, Microsemi offers FREE SoftConsole Eclipse-based
IDE for use with ARM Cortex-M1, Cortex-M3 and Core8051s, as well as
™
®
evaluation versions from Keil and IAR Systems. Full versions are available
Hardware Interfaces
FlashPro4, ULINK, J-LINK
from respective suppliers.
For SmartFusion cSoCs, the MSS configurator creates a bridge between
the FPGA fabric and embedded designs, so device configuration can be
easily shared among multiple developers. The MSS configurator allows
the designer to choose peripherals, assign configuration settings and
change I/O attributes. Most importantly, the memory map is automatically
generated according to the user’s selections, along with all the required
firmware for the selected configuration. The memory map and firmware are
imported into the software project, whether it is GNU, Keil or IAR.
FPGA Design Support
Libero IDE Licenses
Device Support
Microsemi IP
Synthesis
Goldꢀ(FREE)
Platinum
Platinum Evaluation
Standalone
All devices
RTL
All families
Up to 1,500,000 gates
All devices
All devices
Obfuscated
RTL
Obfuscated
®
Synplify Pro AE
x
x
x
x
x
x
x
x
x
x
x
x
x
x
®
Simulation
ModelSim AE
®
Identify AE
Debug
Microsemi Debug
x
x
Program File
Embedded Design Support
Microsemi
SoftConsole
Free with Libero IDE
N/A
Keil
IARꢀSystems
Keil MDK
32 K Code Limited
Full version
EmbeddedꢀWorkbench®
32 K Code Limited
Full version
FreeꢀVersionsꢀfromꢀMicrosemiꢀ
AvailableꢀfromꢀVendor
Compiler
®
GNU GCC
GDB Debug
No
RealView C/C++
IAR ARM Compiler
®
Debugger
µVision Debugger
µVision Simulator
C-SPY Debugger
Instruction Set Simulator
DebugꢀHardwareꢀ
Yes
®
™
FlashPro4
ULink 2 or ULINK-ME
J-Link or J-Link Lite
Platform Support
Tool
Libero IDE
SoftConsoleꢀ
Keil
IARꢀ
FlashPro
Windows®ꢀXPꢀProfessional
Now
Now
Now
Now
Now
N/A
Now
Now
Now
WindowsꢀVistaꢀBusinessꢀ
andꢀWindowsꢀ7
Now
N/A
Now
N/A
Now
N/A
RedHatꢀLinuxꢀWSꢀ5.0,ꢀ5.2
* MSS configurator is specific to the SmartFusion design flow.
www.microsemi.com/soc 21
SmartFusion Evaluation Kit
•ꢀ SupportsꢀSmartFusionꢀ
cSoC evaluation, including
ARM Cortex-M3, FPGA and
programmable analog
•ꢀ Boardꢀfeaturesꢀ
- Ethernet interface
SmartFusion Device
RVI - Header
OLED Display
- USB port for power and
HyperTerminal
•ꢀ Freeꢀone-yearꢀLiberoꢀIntegratedꢀ
Design Environment (IDE) software
and Gold license with SoftConsole
for program and debug
Potentiometer
USB
Program
- USB port for programming
and debug
and Debug
Interface
5 Debug I/Os
Reset Switch
Debug Select
- J-Link header for debug
•ꢀ USBꢀprogrammingꢀbuiltꢀintoꢀboardꢀ
•ꢀ TwoꢀUSBꢀcables
- Mixed signal header
10/100
Ethernet
Interface
8 User LEDs
- SPI flash – off-chip memory
- Reset and 2 user switches, 8 LEDs
- POT for voltage / current monitor
- Temperature monitor
JTAG Select
PUB Switch
Regulators
•ꢀ User’sꢀguide,ꢀtutorialꢀandꢀ
design examples
USB
Power and
USB-UART
Interface
SPI-Flash
Memory
•ꢀ Printedꢀcircuitꢀboardꢀ(PCB)ꢀ
schematics,ꢀlayoutꢀfilesꢀandꢀ
bill-of-materialsꢀ(BOM)
- Organic light-emitting diode (OLED)
User SW1
Mixed Signal
Header
20 MHz 32.768 KHz
VRPSM
Voltage
Option
User SW2
Crystal
Crystal
Ordering Code
Supported Device
Price
A2F-EVAL-KIT
A2F200M3F-FGG484
$ 99
SmartFusion Development Kit
•ꢀ SupportsꢀSmartFusionꢀ
development, including
ARM Cortex-M3, FPGA and
programmable analog
•ꢀ Boardꢀfeaturesꢀ
DB9
- Ethernet, EtherCAT, CAN, UART,
PSRAM AGLP125V5-
(1.8 V) CSG289
A2F500
Connector
SRAM
(3.3 V)
Connector
CAN
2
for CAN0 Transceivers
I C and SPI interfaces
DB9 Connector
for CAN1
IGLOO PLUS
Header
- USB port for HyperTerminal
•ꢀ Freeꢀone-yearꢀLiberoꢀIDEꢀsoftwareꢀ
and Gold license with SoftConsole
for program and debug
Memory Device
Configuration
Headers
- USB port for programming
and debug
DIP Switch
RealView® Header
AGLP DIP
Switch
- J-Link header for debug
•ꢀ 5ꢀVꢀpowerꢀsupplyꢀandꢀ
international adapters
JTAG_SEL Switch
JTAG MUX
- Mixed signal and A2F500 digital
expansion header
Power Switch
Power Jack
LCPS Connector
•ꢀ TwoꢀUSBꢀcablesꢀandꢀlowꢀcostꢀ
programming stick
JTAG Chain
Configuration Header
1.5 V Header
SmartFusion
cSoC
DirectC Header
- Extensive off-chip memory
- Refer to www.microsemi.com/soc
for a full list of features
DB9 Connector for
RS485 (UART1)
Board Reset
Switch
RJ45 Connector
for 10/100 Ethernet
•ꢀ User’sꢀguide,ꢀtutorialꢀandꢀ
design examples
PUB Switch
RS485 Transceiver
50 MHz Oscillator
•ꢀ PCBꢀschematics,ꢀlayoutꢀfilesꢀ
andꢀBOM
RJ45 Connectors
for EtherCAT
Ports
USB Connector
for UART0
2
I
C Headers
10/100 Ethernet
PHY
SPI Headers
OLED
Ordering Codes
Supported Devices
A2F500M3G-FGG484
Price
DACOUT/
ADC
Headers
Push-Button
Switches
POT for EtherCAT Mixed EtherCAT
DAC0 and DAC1
Callibration POTs
for 15 V Biꢀolar
Outꢀuts
A2F500-DEV-KIT
$ 999
Current
Monitor
PHYs
Signal
ASIC
Header
•ꢀ Supportsꢀdebugꢀaccessꢀtoꢀtheꢀ
mixed signal header of the
SmartFusion Evaluation Kit and
SmartFusion Development Kit
•ꢀ Boardꢀfeaturesꢀ
Mixed Signal Daughter Card
- Test points for signal probing
- Mixed signal header for daughter
card support
•ꢀ 4ꢀ1/2”ꢀplasticꢀstandoffsꢀandꢀ
4 plastic screws to match
development kit height
- 100 Mil header for wire-wrapped
or soldered signals
Mixed Signal Connector
Test Points
•ꢀ Soldꢀstandalone
Ordering Code
Supported Device
No Microsemi device
Price
MIXED-SIGNAL-DC
$ 55
100 mil Connector
22 www.microsemi.com/soc
MPM Daughter Card
•ꢀ Supportsꢀpowerꢀmanagementꢀ
design with the SmartFusion
Evaluation Kit and SmartFusion
Development Kit
•ꢀ Boardꢀfeaturesꢀ
- 4 power supply regulators
- 4 potentiometers to control
regulators
Power Supply Regulator
REG1 - REG4 Interrupt Switches Mixed Signal
•ꢀ MPMꢀdesignꢀexampleꢀimplementsꢀ
configurableꢀpowerꢀmanagementꢀ
in SmartFusion cSoC
(SW8, SW11, SW16, SW15)
Header
- 4 power supply regulator
interrupt switches
- 4 power supply regulator
status LEDs
•ꢀ Graphicalꢀconfigurationꢀdialogꢀ
•ꢀ In-systemꢀreconfigurable
•ꢀ 9ꢀVꢀpowerꢀsupplyꢀ
Power Supply
Regulators
R1 - R4 LEDs
- Mixed signal header connector
connects to SmartFusion board
MPM
Power
Switch
Ordering Code
MPM-DC-KIT
Supported Device
Price
No Microsemi device
$ 299
Power Supply Regulator
REG1 - REG4 Potentiometers
MPM 9 V Jack
Motor Control Development Kit
•ꢀ Circuitryꢀonꢀboardꢀaccommodatesꢀ
•ꢀ Fiveꢀreferenceꢀdesignsꢀincludingꢀ
drivers for up to 4 PMSM motors
(1 supplied with kit)
C source code and RTL
•ꢀ Commutationꢀinꢀtrapezoidalꢀmodeꢀ
usingꢀHallꢀeffectꢀsensorꢀfeedbackꢀ
•ꢀ OneꢀPMSMꢀmotorꢀwithꢀHallꢀsensorꢀ
and encoder included
•ꢀ SinusoidalꢀusingꢀHallꢀeffectꢀ
•ꢀ Referenceꢀdesignꢀsupportingꢀ
sensor feedback
multiple operation modes
- Commutation starts in trapezoidal
mode and switches to sinusoidal
when sufficient speed is achieved
•ꢀ PCꢀinterfaceꢀforꢀdefiningꢀvelocity,ꢀ
torque and other parameters for up
to four motors in real-time over an
Ethernet connection
•ꢀ SinusoidalꢀwithꢀHallꢀeffectꢀ
encoder feedback
•ꢀ 18ꢀVꢀpowerꢀsupplyꢀ
- Commutation starts in trapezoidal
mode and switches to sinusoidal
mode on first edge of Hall sensor
input using incremental encoder
•ꢀ Mainsꢀpowerꢀsupplyꢀwithꢀ
international adapter
•ꢀ Crossꢀoverꢀcableꢀ
•ꢀ Sensorlessꢀtrapezoidalꢀ
•ꢀ Schematicsꢀandꢀdesignꢀ
filesꢀavailable
- Uses back-EMF to generate
six-step commutation feedback
•ꢀ User’sꢀguideꢀ
Ordering Code
Description
Price
$ 2,499
$ 499
A2F-MOTOR-CONTROL-KITꢀ
A2F-MOTOR-CONTROL-DESIGNSꢀ
3-MOTORS
Motor control kit including reference designs and 1 motor
Motor control reference designs
Additional 3 motors
$ 185
www.microsemi.com/soc 23
IGLOO nano Starter Kit
•ꢀ SupportsꢀbasicꢀIGLOOꢀnanoꢀ
low power FPGA design, including
Flash*Freeze mode
•ꢀ Boardꢀfeaturesꢀ
20 MHz
IGLOO nano
FPGA
I/O Test Pin
Headers
- All I/Os available for external
connections
Clock Oscillator
•ꢀ Freeꢀone-yearꢀLiberoꢀIDEꢀsoftwareꢀ
and Gold license
- Full current measurement
capability of independent
I/O banks and VCC
Flash*Freeze
Switch
USB
Interface
Push-Button
Reset Switch
•ꢀ Low-costꢀprogrammingꢀ
stick (LCPS)
- USB connection for USB-to-
serial (RS232) interface for
HyperTerminal or power
5 V Wall
Jack
•ꢀ TwoꢀUSBꢀcablesꢀ
LCPS
Connector
Jumper
for Battery
Option
- 20 MHz clock oscillator
•ꢀ Kitꢀuser’sꢀguide,ꢀLiberoꢀIDEꢀ
tutorial and design examples
Jumpers to
- LEDs and switches for simple
inputs and outputs
Isolate User LEDs,
Push-Button
Switches, DIP
Switches for
I/O Test Pins
•ꢀ PCBꢀschematics,ꢀlayoutꢀfiles
andꢀBOMꢀ
- Ability to switch VCORE from
1.2 V to 1.5 V
Jumpers
for Voltage
Options
4 Push-Button
Switches
- RoHS compliant
Ordering Code
Supported Device
Price
Current Measurement 8 DIP Switches
Headers
8 User LEDs
AGLN-NANO-KIT*
AGLN250V2-VQG100
$ 99
Note:
* Replaces -Z version of the nano Starter Kit.
ProASIC3 Starter Kit
•ꢀ SupportsꢀbasicꢀProASIC3ꢀFPGAꢀ
design and LVDS I/O usage
•ꢀ Boardꢀfeaturesꢀ
Wall Mount
Interboard ISP
Connector
LCD Display
- Eight I/O banks with variety of
voltage options
Power
Module
•ꢀ Freeꢀone-yearꢀLiberoꢀIDEꢀsoftwareꢀ
and Gold license
- Oscillator for system clock or
manual clock option
•ꢀ FlashPro3ꢀorꢀFlashPro4ꢀ
Removable
Shunts to
Isolate All I/Os
for Prototyping
Programmer
CAT5E RJ45
Connectors
for LVDS
- LEDs and switches for simple
inputs and outputs
•ꢀ 9ꢀVꢀpowerꢀsupplyꢀandꢀ
international adapters
Communications
- LCD display module
FlashPro3
ISP Connector
- Two CAT5E RJ45 connectors for
high-speed LVDS communications
Removable
Shunts to
Isolate All I/Os
for Prototyping
•ꢀ Kitꢀuser’sꢀguide,ꢀLiberoꢀIDEꢀ
tutorial and design examples
ProASIC3/E in
PQ208 Package
- All I/Os available for external
connections
•ꢀ PCBꢀschematics,ꢀlayoutꢀfilesꢀ
andꢀBOMꢀ
Oscillator for
System
Every PQ208
Pin Accessible
for Prototyping
Clock
- Not RoHS compliant
Manual
Clock Option
Ordering Codes
Supported Devices
Price
SMA for
Optional
External
A3PE-PROTO-KIT
A3PE1500-PQ208
$ 665
Removable Shunts to Isolate
All I/Os for Prototyping
4 Switches
Oscillator
8 LEDs
Fusion Embedded Development Kit
•ꢀ Supportsꢀroyalty-free,ꢀindustry-
standard ARM Cortex-M1 or
8051s development
•ꢀ Boardꢀfeaturesꢀ
LCPS
Connector
User
LEDs Flash
SPI
- 512 KB SRAM, 2 MB SPI flash
memory provided on board
- 10/100 Ethernet and I2C interfaces
OLED
Potentiometer
•ꢀ Freeꢀone-yearꢀLiberoꢀIDEꢀsoftwareꢀ
and Gold license with SoftConsole
for program and debug
- USB-to-UART connection for
HyperTerminal on a PC
Ethernet
Interface
Push-
Button
Reset
•ꢀ Low-costꢀprogrammingꢀ
stick (LCPS)
- Built-in voltage, current and
temperature monitor and
voltage potentiometer
Ethernet
LEDs
Push-
Button
PUB
•ꢀ 5ꢀVꢀpowerꢀsupplyꢀandꢀ
international adapters
- Mixed signal interface
2
Two I
C
Interfaces
•ꢀ TwoꢀUSBꢀcablesꢀ
- Blue OLED 96x16 pixel display
Interface
Connector
5 V Wall
Jack
- Dynamic reconfigurable analog
and flash memory
•ꢀ Kitꢀuser’sꢀguide,ꢀLiberoꢀIDEꢀ
tutorial and design examples
RealView
Header
SRAM
- FlashPro3 and RealView
debug interface
•ꢀ PCBꢀschematics,ꢀlayoutꢀfilesꢀ
andꢀBOM
Push-
Button
Switch
USB
Interface
- RoHS compliant
Jumpers
for Internal
or External
Regulator
Fusion
FPGA
Push-Button
Switch
Mixed Signal
Header
Mixed Signal
Test Pins
Ordering Code
Supported Device
M1AFS1500-FGG484
Price
M1AFS-EMBEDDED-KIT
$ 250
24 www.microsemi.com/soc
Core1553 Development Kit
•ꢀ Allowsꢀusersꢀtoꢀevaluateꢀ
the functionality of Microsemi’s
Core1553BRMꢀwithoutꢀhavingꢀtoꢀ
createꢀaꢀcompleteꢀMIL-STD-1553Bꢀ
compliant system
•ꢀ Boardꢀfeaturesꢀꢀꢀꢀꢀ
- MIL-STD-1553B transceiver, two
transformers and two concentric
twinax connectors included on
the Core1553 daughter board
Core1553-SA
Fusion Advanced Development Kit
•ꢀ FusionꢀAdvancedꢀDevelopmentꢀKitꢀ
with two 9 V power supplies
~ MIL-STD-1553B concentric
twinax connectors are center
pin signal high and cylindrical
contact signal low
•ꢀ Core1553ꢀdaughterꢀcard
•ꢀ User’sꢀguide,ꢀtutorialꢀandꢀ
design example
~ Connectivity is
MIL-C-49142 compliant
~ Evaluate and develop
•ꢀ PCBꢀschematics,ꢀlayoutꢀfilesꢀ
andꢀBOM
medium speed on-board data
communications bus solutions
for MIL-STD-1553B /
UK DEF-STAN 00-18 (Pt.2) /
NATO STANAG 3838 AVS /
Avionic Standards Coordinating
Committee Air-Std 50/2
•ꢀ Purchasingꢀtheꢀkitꢀgivesꢀtheꢀownerꢀ
theꢀrightꢀtoꢀtheꢀprogrammingꢀfileꢀ
of the demo, but not an evaluation
of the IP. The IP evaluation or
purchase is quoted separately.
- CAN bus interface support
- Connector to ARINC 429
Daughter Board (CORE429-SA)
Ordering Code
Description
Price
$ 3,620
$ 2,900
$ 750
CORE1553-DEV-KIT
CORE1553-SA
Core1553 Development Kit
Core1553 daughter card
M1AFS-ADV-DEV-KIT-PWR
M1AFS-ADV-DEV-KIT with two 9 V power packs
Hardware Summary
Microsemi offers hardware choices for terrestrial products. Most popular kits are listed in the table and shown in further detail in this section. Full details of these
kits can also be found online with user’s guides and accompanying tutorials.
Family
Ordering Code
Name
Device
Price
$ 99
Power
USB
5 V
SmartFusion
SmartFusion
SmartFusion
SmartFusion
Fusion
A2F-EVAL-KIT*
SmartFusion Evaluation Kit
SmartFusion Development Kit
MPM Daughter Card
A2F200M3F-FGG484
A2F500M3G-FGG484
none
A2F500-DEV-KIT
MPM-DC-KIT
$ 999
$ 299
$ 55
9 V
MIXED-SIGNAL-DC
M1AFS-EMBEDDED-KIT*
AFS-EVAL-KIT
Mixed Signal Daughter Card
Fusion Embedded Development Kit
Fusion Starter Kit
none
N/A
M1AFS1500-FGG484
AFS600-FG256
$ 250
$ 500
$ 750
$ 99
USB / 5 V
9 V
Fusion
Fusion
M1AFS-ADV-DEV-KIT-PWR
AGLN-NANO-KIT*
AGL-ICICLE-KIT
Fusion Advanced Development Kit
IGLOO nano Starter Kit
M1AFS1500-FGG484
AGLN250V2-ZVQG100
AGL125V2-QNG132
AGLP125V2-CSG289
M1AGL1000V2-FGG484
A3PE1500-PQ208
M1A3P1000L-FGG484
9 V
IGLOO
USB
USB
5 V
IGLOO
IGLOO Icicle Evaluation Kit
IGLOO PLUS Starter Kit
$ 150
$ 299
$ 550
$ 665
$ 550
IGLOO
AGLP-EVAL-KIT
IGLOO
M1AGL1000-DEV-KIT
A3PE-PROTO-KIT*
M1A3PL-DEV-KIT
ARM Cortex-M1 IGLOO Development Kit
ProASIC3 Starter Kit
5 V
ProASIC3
ProASIC3
9 V
ARM Cortex-M1 ProASIC3L Development Kit
5 V
*Most recommended Kit for each product family
www.microsemi.com/soc 25
FlashPro4 In-System FPGA Programmer
•ꢀ Supportsꢀin-systemꢀprogramming
•ꢀ USBꢀConnectionꢀtoꢀPCꢀꢀ
•ꢀ Operatingꢀsystems
•ꢀ SupportsꢀIEEEꢀ1149ꢀJTAGꢀ
programming through STAPL
- Windows XP Professional
(SP2 recommended)
•ꢀ SupportsꢀIEEEꢀ1532
- Windows 2000 Professional
(SP4 recommended)
•ꢀ UsesꢀFlashProꢀsoftware,ꢀavailableꢀ
as part of Libero IDE or standalone
•ꢀ Freeꢀsoftwareꢀupdates
Ordering Code
Price
FLASHPRO4
$ 49
Silicon Sculptor 3 FPGA Programmer
•ꢀ ProgramsꢀallꢀMicrosemiꢀpackages,ꢀ •ꢀ Protectionꢀfeatures
includingꢀPL,ꢀPQ,ꢀVQ,ꢀQN,ꢀBG,ꢀFG,ꢀ
- Overcurrent shutdown
and CS
- Power failure shutdown
•ꢀ UniversalꢀMicrosemiꢀsocketꢀ
adapters
- ESD protection
- ESD wrist straps with banana
jacks (included as standard)
•ꢀ UseꢀwithꢀSiliconꢀSculptorꢀsoftwareꢀ
•ꢀ Securityꢀfuseꢀcanꢀbeꢀprogrammedꢀ
to secure the devices
•ꢀ Operatingꢀsystems
- Windows XP Professional
(SP2 recommended)
•ꢀ Includesꢀself-testꢀtoꢀtestꢀitsꢀ
own hardware
- Windows 2000 Professional
(SP4 recommended)
Ordering Code
Price
SILICON-SCULPTORꢀ3
$ 4,330
For adapter modules, refer to www.microsemi.com/soc/products/hardware/program_debug/ss/modules.aspx
Programming Devices In-System Using a Microprocessor
Although the FlashPro3 programmer can perform in-system programming, it does require a specific header to be connected externally. For example, if
your system already has external communication available through a microprocessor interface, you may prefer to have the processor perform the in-system
programming. This can be done in two ways.
JTAG scan chain for a single device. The data format is a JEDEC standard
known as the Standard Test and Programming Language (STAPL) format.
For third-generation devices, note that the STAPL Player will not support
serialization of the FlashROM, nor will it support Smart Erase enabled silicon.
DirectC
DirectC v2.3 is a set of C code designed to support embedded
microprocessor–based in-system programming for IGLOO, ProASIC3 and
Fusion families. To use DirectC v2.3, you must make some minor modifications
to the provided source code, add the necessary API and compile the source
The STAPL Player reads the STAPL file and executes the file’s programming
instructions. Because all programming details are in the STAPL file, the
code and the API together to create a binary executable. The target system
STAPL Player itself is completely device-independent. In other words, the
must contain a microprocessor with a minimum 256 bytes of RAM, a JTAG
interface to the target device from the microprocessor and access to the
programming data to be used for programming the FPGA. Access to
system does not need to implement any programming algorithm details; the
STAPL file provides all of the details.
The key differences between the DirectC and the STAPL player methods are
in the memory footprint in the microprocessor and amount of data to transmit.
The DirectC option requires more code space on the processor, but as a
result less data has to be transmitted to perform programming. On the other
hand, the STAPL player communicates both the information to be programmed
and the intelligence needed to perform programming. So the code footprint
is smaller but the amount of data to transmit will be larger. One advantage of
the STAPL player method is that if updates are required to the programming
algorithm, the STAPL method does not require new code in the processor,
but the DirectC would require new code for the processor.
programming data could be provided by a telecommunications link for most
remote systems.
Download DirectC source files and the complete user’s guide at:
www.microsemi.com/soc/products/hardware/program_debug/directc/default.aspx
STAPL Player
The STAPL Player can be used to program third-generation flash devices such
as IGLOO, ProASIC3 and Fusion, and interprets the contents of a STAPL file,
which is generated by Libero IDE software tools. The file contains information
about the programming of Microsemi flash-based devices, as well as the
26 www.microsemi.com/soc
Intellectual Property Cores
Microsemi IP Cores
Tiles
7,254
2,331
3,016
6,787
1,612
740
ObfuscatedꢀCoreꢀ
Free Libero Gold
Purchase
RTLꢀCoreꢀ
Purchase
Core10/100ꢀ
Core1553BBCꢀ
Core1553BRMꢀ
Core1553BRMꢀ
Core1553BRTꢀ
Core429ꢀ
10/100 Mbps Ethernet MAC with Host Controller (AHB/APB option available)
MIL-STD-1553B Bus Controller (BC)
Purchase
MIL-STD-1553B Bus Monitor Only
Purchase
Purchase
MIL-STD-1553B Combined Remote Terminal (RT), Bus Controller, and Bus Monitor (BM)
MIL-STD-1553B Remote Terminal
Purchase
Purchase
Purchase
Purchase
ARINC 429 Bus Interface (1 receive channel)
Purchase
Purchase
Core429ꢀ
ARINC 429 Bus Interface (1 transmit channel)
563
Purchase
Purchase
CorePCIF
PCI Specification 2.3 Bus Controller with FIFO Support (66/64 Target and Master)
PCI Specification 2.3 Bus Controller with FIFO Support (33/32 Target)
Universal Asynchronous Receiver/Transmitter with or without FIFO
3DES Encryption and Decryption
3,808
996
Purchase
Purchase
CorePCIF
Purchase
Purchase
Core16550ꢀ
Core3DES
979
Libero Gold
Libero Gold
Libero Platinum
Libero Platinum
1,413
8-Bit Microprocessor, 100% ASM51 Compatible, Configurable Peripherals,
AHB Bus Compliant
Core8051sꢀ
2,500
Libero Gold
Libero Platinum
CoreABCꢀ
Low-Gate-Count Controller for the APB
241
5,193
1,300
250
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Libero Gold
Web Only
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Libero Platinum
Web Only
CoreAES128ꢀ
CoreAHBꢀ
AES Encryption and Decryption
Multi-Master Advanced High Performance Bus (AHB)
AHB to Advanced Peripheral Bus (APB) Bridge
Single-Master AHB
CoreAHB2APBꢀ
CoreAHBLiteꢀ
CoreAHBNVMꢀ
CoreAHBSRAMꢀ
CoreAI
700
On-Chip Flash Memory Controller with AHB Interface
On-Chip SRAM Memory Controller with AHB Interface
Analog Interface Core (maximum configuration)
APB
396
236
460
CoreAPBꢀ
125
CoreCFI
Common Flash Interface—Typical Configuration
Coordinate Rotational Digital Computer Core (bit-serial architecture)
High Performance Double Data Rate (DDR) SDRAM Controller
DES Encryption and Decryption
600
CoreCORDICꢀ
CoreDDRꢀ
450
1,748
1,271
541
CoreDES
CoreFMEE
CoreGPIO
Flash Memory Endurance Extender (typical configuration)
General-Purpose Input/Output Controller with APB Interface
100
2
CoreI2Cꢀ
I C Master/Slave Interface
658
CoreInterrupt
CoreLPC
CoreMP7 Interrupt Controller
68
Intel Low Pin Count interface for Fusion/IGLOO/PA3 (SERIRQ disabled)
Off-Chip Memory Controller with AHB Interface
340
CoreMemCtrl
CorePWMꢀ
CoreSDLC
CoreSDRꢀ
100
Pulse Width Modulation Core (typical configuration)
Synchronous Data Link Controller
650
1,286
1,350
1,078
733
High Performance Single Data Rate (SDR) SDRAM Controller
System Management Bus Controller (master/slave configuration)
System Management Bus Controller (slave-only configuration)
Serial Peripheral Interface (Combined Mode)
CoreSMBusꢀ
CoreSMBusꢀ
CoreSPI
330
CoreTimer
CoreUARTꢀ
CoreUART_APBꢀ
CoreWatchdogꢀ
Cortex-M1ꢀ
CoreFFT
16- or 32-Bit Timer with APB Interface
310
Universal Asynchronous Receiver/Transmitter
337
Universal Asynchronous Receiver/Transmitter with APB Interface
Watchdog Timer with APB Interface
300
280
High Performance 32-Bit FPGA-Optimized Processor (pre-placed design block)
Fast Fourier Transform Core Generator (1,024 points)
Fast Fourier Transform Core Generator (256 points)
Finite Impulse Response Core Generator (configuration 1)
4,300
9,030
7,364
583
CoreFFT
Web Only
Web Only
CoreFIRꢀ
Web Only
Web Only
Note: Additional Cores and configurations can be found on the website and in core handbooks.
www.microsemi.com/soc 27
www.microsemi.com/soc
Youꢀmayꢀbeꢀinterestedꢀin:
SpaceꢀProductꢀCatalog:ꢀwww.microsemi.com/soc/documents/SpaceProdCat_PIB.pdf
SolutionsꢀandꢀIPꢀCatalog:ꢀwww.microsemi.com/soc/documents/IPPIB.pdf
Microsemi SoC Products Group 2061 Stierlin Court, Mountain View, CA 94043-4655 USA Phone: 650.318.4200
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete
subsystems. Microsemi is headquartered in Aliso Viejo, Calif.
Learn more at www.microsemi.com.
MicrosemiꢀCorporateꢀHeadquarters
One Enterprise Drive, Aliso Viejo, CA 92656
Within the USA: (800) 713-4113
Outside the USA: (949) 221-7100
Fax: (949) 756-0308 · www.microsemi.com
©2011 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks
and service marks are the property of their respective owners.
55700040-9/10.11
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