A3P400-1QNG100YI [MICROSEMI]
ProASIC3 Flash Family FPGAs with Optional Soft ARM Support; 闪光的ProASIC3系列FPGA具有可选的软ARM支持型号: | A3P400-1QNG100YI |
厂家: | Microsemi |
描述: | ProASIC3 Flash Family FPGAs with Optional Soft ARM Support |
文件: | 总220页 (文件大小:10669K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Advanced I/O
Features and Benefits
•
•
•
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
•
•
•
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
•
•
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
Reprogrammable Flash Technology
†
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
2.5 V / 5.0 V Input
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
•
•
•
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
‡
Hot-Swappable and Cold Sparing I/Os
High Performance
†
Programmable Output Slew Rate and Drive Strength
•
•
350 MHz System Performance
Weak Pull-Up/-Down
†
3.3 V, 66 MHz 64-Bit PCI
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL†
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
®
®
(AES) Decryption (except ARM -enabled ProASIC 3 devices)
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
†
via JTAG (IEEE 1532–compliant)
®
•
FlashLock to Secure FPGA Contents
Low Power
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
•
•
•
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
•
•
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
†
High-Performance Routing Hierarchy
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
•
Segmented, Hierarchical Routing and Clock Structure
•
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
®
•
M1 ProASIC3 Devices—ARM Cortex™-M1 Soft Processor
Available with or without Debug
1
ProASIC3 Devices
Cortex-M1 Devices
System Gates
A3P015
A3P030
A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
2
M1A3P250 M1A3P400
M1A3P600 M1A3P1000
15,000
30,000
60,000 125,000
250,000
400,000
600,000
1,000,000
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
128
384
–
256
768
–
512
1,536
18
4
1,024
3,072
36
2,048
6,144
36
–
9,216
54
–
13,824
108
24
–
24,576
144
32
–
–
8
8
12
FlashROM Kbits
1
1
1
1
1
1
1
1
3
Secure (AES) ISP
–
–
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Integrated PLL in CCCs
–
–
4
VersaNet Globals
6
6
18
2
18
18
18
18
18
I/O Banks
2
2
2
4
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
300
Package Pins
5
QFN
QN68
QN48, QN68,
QN132
QN132
QN132
QN132
CS
CS121
VQ100
TQ144
VQFP
TQFP
PQFP
FBGA
VQ100
VQ100
TQ144
PQ208
VQ100
PQ208
PQ208
PQ208
PQ208
5
FG144
FG144 FG144/256
FG144/256/ FG144/256/ FG144/256/
484
484
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
† A3P015 and A3P030 devices do not support this feature.
‡ Supported only by A3P015 and A3P030 devices.
January 2013
I
© 2013 Microsemi Corporation
ProASIC3 Flash Family FPGAs
1
I/Os Per Package
ProASIC3
Devices
A3P0152 A3P030 A3P060 A3P125
A3P250 3
A3P400 3
A3P600
A3P1000
Cortex-M1
Devices
M1A3P250 3,5
I/O Type
M1A3P400 3
M1A3P600
M1A3P1000
Package
QN48
–
49
–
34
49
81
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
QN68
–
–
–
–
QN1325
CS121
VQ100
TQ144
PQ208
FG144
FG2565,6
FG4846
Notes:
80
96
71
91
–
84
–
87
–
19
–
–
–
–
–
–
–
–
–
–
–
77
–
71
100
133
97
–
68
–
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
151
97
157
–
34
24
38
–
151
97
178
194
34
25
38
38
154
97
35
25
43
60
154
97
177
300
35
25
44
74
–
–
96
–
–
–
177
235
–
–
–
–
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide
to ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
the ProASIC3 FPGA Fabric User’s Guide for position assignments of the 15 LVPECL pairs.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 or QN132 packages.
6. FG256 and FG484 are footprint-compatible packages.
Table 1 • ProASIC3 FPGAs Package Sizes Dimensions
Package
CS121
QN48
QN68
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Length × Width
(mm\mm)
6 × 6
6 × 6
8 × 8
8 × 8
14 × 14
20 × 20
28 × 28
13 × 13
17 × 17
23 × 23
Nominal Area
(mm2)
36
36
64
64
196
400
784
169
289
529
Pitch (mm)
0.5
0.4
0.4
0.5
0.5
0.5
0.5
1.0
1.0
1.0
Height (mm)
0.99
0.90
0.90
0.75
1.00
1.40
3.40
1.45
1.60
2.23
II
Revision 13
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
.
_
1
FG
G
144
Y
I
A3P1000
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP= Pre-Production
ES= Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging (some packages also halogen-free)
Package Type
=
=
=
=
=
=
QN
VQ
TQ
PQ
FG
CS
Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
Very Thin Quad Flat Pack (0.5 mm pitch)
Thin Quad Flat Pack (0.5 mm pitch)
Plastic Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Chip Scale Package (0.5 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P015 = 15,000 System Gates (A3P015 is not recommended for new designs.)
A3P030 = 30,000 System Gates
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P400 = 400,000 System Gates
A3P600 = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
ProASIC3 Devices with Cortex-M1
M1A3P250 = 250,000 System Gates
M1A3P400 = 400,000 System Gates
M1A3P600 = 600,000 System Gates
M1A3P1000 = 1,000,000 System Gates
ProASIC3 Device Status
ProASIC3 Devices
Status
Cortex-M1 Devices
Status
A3P015
Not recommended for new designs.
Production
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
Production
Production
Production
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
Production
Production
Production
Production
Production
Production
Production
Revision 13
III
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
Cortex-M1 Devices
QN48
A3P015* A3P030 A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
–
C, I
–
C, I
C, I
C, I
–
–
–
–
–
–
–
–
–
–
–
–
–
QN68
QN132
C, I
C, I
C, I
C, I
–
C, I
–
C, I
–
–
–
–
CS121
–
–
–
–
VQ100
–
C, I
–
C, I
C, I
C, I
C, I
–
C, I
–
–
–
–
TQ144
–
–
–
–
PQ208
–
–
C, I
C, I
C, I
–
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
FG144
–
–
C, I
–
FG256
–
–
FG484
–
–
–
–
Note: *A3P015 is not recommended for new designs.
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
Std.
–1
–2
C 1
I 2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx.
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
A3P015 is not recommended for new designs.
IV
Revision 13
ProASIC3 Flash Family FPGAs
Table of Contents
ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Package Pin Assignments
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Revision 13
V
1 – ProASIC3 Device Family Overview
General Description
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices
the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is
reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable
designers to create high-density systems using existing ASIC or FPGA design flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030
devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported
with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi
ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement
solution, especially for applications in the consumer, networking/ communications, computing, and
avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design security without external overhead, advantages that
only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level
of protection in the FPGA industry for intellectual property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading
AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National
Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3
devices have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. ProASIC3 devices with
AES-based security provide a high level of protection for remote field updates over public networks such
as the Internet, and are designed to ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the
ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams
are always encrypted. There is no user access to encryption for the FlashROM programming data.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks.
Revision 13
1-1
ProASIC3 Device Family Overview
Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3
device provides the best available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The Instant On
feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system
cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in
a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's
flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or complete removal of the configuration PROM,
expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-
based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing
system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
1-2
Revision 13
ProASIC3 Flash Family FPGAs
Advanced Flash Technology
The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and
Figure 1-2 on page 1-4):
•
•
•
•
•
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory†
Extensive CCCs and PLLs†
Advanced I/O structure
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashROM
Charge Pumps
Bank 1
Note: *Not supported by A3P015 and A3P030 devices
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and
A3P125)
† The A3P015 and A3P030 do not support PLL or SRAM.
Revision 13
1-3
ProASIC3 Device Family Overview
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(A3P600 and A3P1000)
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 2
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The ProASIC3 VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop w ith Clear or Set
D-Flip-Flop w ith Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
1-4
Revision 13
ProASIC3 Flash Family FPGAs
User Nonvolatile FlashROM
ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in
security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The ProASIC3 development software solutions, Libero® System-on-Chip (SoC) and Designer, have
extensive support for the FlashROM. One such feature is auto-generation of sequential programming
files for applications requiring a unique serial number in each part. Another feature allows the inclusion of
static data for system version control. Data for the FlashROM can be generated quickly and easily using
Libero SoC and Designer software tools. Comprehensive programming file support is also included to
allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their
north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent
read and write ports that can be configured with different bit widths on each port. For example, data can
be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be
initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015
and A3P030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of
the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and
A3P030 devices do not have a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
Revision 13
1-5
ProASIC3 Device Family Overview
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
•
•
•
•
Maximum acquisition time = 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
f
OUT_CCC) (for PLL only)
Global Clocking
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
1-6
Revision 13
ProASIC3 Flash Family FPGAs
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and
differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported (Table 1-1).
Table 1-1 • I/O Standards Supported
I/O Standards Supported
LVTTL/
LVPECL, LVDS,
I/O Bank Type
Device and Bank Location
LVCMOS PCI/PCI-X B-LVDS, M-LVDS
Advanced
East and west Banks of A3P250 and
larger devices
Standard Plus
Standard
North and south banks of A3P250 and
larger devices
Not supported
All banks of A3P060 and A3P125
All banks of A3P015 and A3P030
Not
supported
Not supported
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B
specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
Revision 13
1-7
ProASIC3 Device Family Overview
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-4 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tristate: I/O is tristated
Figure 1-4 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
1-8
Revision 13
2 – ProASIC3 DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
V
V
V
V
V
V
V
VJTAG
VPUMP Programming voltage
VCCPLL Analog power supply (PLL)
VCCI
VMV
VI
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 V to 3.6 V
(when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+125
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 13
2-1
ProASIC3 DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 1,2
Symbol
TA
Parameters 1
Commercial
0 to +70
Industrial
-40 to +85
-40 to 100
1.425 to 1.575
1.4 to 3.6
Units
°C
°C
V
Ambient temperature
TJ
Junction temperature
1.5 V DC core supply voltage
JTAG DC voltage
0 to 85
VCC3
VJTAG
VPUMP
1.425 to 1.575
1.4 to 3.6
V
Programming voltage
Programming Mode 4
Operation 5
3.15 to 3.45
0 to 3.6
3.15 to 3.45
0 to 3.6
V
V
VCCPLL
Analog power supply (PLL)
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
V
VCCI and VMV 6 1.5 V DC supply voltage
V
1.8 V DC supply voltage
V
2.5 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
3.0 to 3.6
V
3.3 V wide range DC supply voltage 7
LVDS/B-LVDS/M-LVDS differential I/O
LVPECL differential I/O
2.7 to 3.6
2.7 to 3.6
V
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
V
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-18 on page 2-18.
4. The programming temperature range supported is T
= 0°C to 85°C.
ambient
5. VPUMP can be left floating during operation (not programming mode).
6. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the
corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.
7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1
Product
Grade
Programming Program Retention
Maximum Storage
Maximum Operating
Cycles
(biased/unbiased) Temperature TSTG (°C) 2 Junction Temperature TJ (°C) 2
Commercial
Industrial
Notes:
500
20 years
20 years
110
110
100
100
500
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or Undershoot
Maximum Overshoot/
Undershoot2
VCCI and VMV
Duration as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for
information on clock and lock recovery.
Revision 13
2-3
ProASIC3 DC and Switching Characteristics
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
V
= 0.85 V ± 0.25 V
a
Deactivation trip point:
= 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
V
d
VCCI
Activation trip point:
= 0.9 V ± 0.3 V
Min VCCI datasheet specification
V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
a
Deactivation trip point:
= 0.8 V ± 0.3 V
V
d
Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5.
P = Power dissipation
2-4
Revision 13
ProASIC3 Flash Family FPGAs
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction
temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C
·
------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------
= 1.463 W
Maximum Power Allowed =
=
ja(C/W)
20.5C/W
EQ 2
Table 2-5 • Package Thermal Resistivities
ja
Package Type
Device
Pin Count jc Still Air 200 ft./min. 500 ft./min. Units
Quad Flat No Lead
A3P030
A3P060
132
132
132
132
100
144
208
208
144
256
484
144
256
484
0.4
0.3
0.2
0.1
10.0
11.0
8.0
3.8
3.8
3.8
3.2
6.3
6.6
8.0
21.4
21.2
21.1
21.0
35.3
33.5
26.1
16.2
26.9
26.6
20.5
31.6
28.1
23.3
16.8
16.6
16.5
16.4
29.4
28.0
22.5
13.3
22.9
22.8
17.0
26.2
24.4
19.0
15.3
15.0
14.9
14.8
27.1
25.7
20.8
11.9
21.5
21.5
15.9
24.2
22.7
16.7
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
A3P125
A3P250
Very Thin Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
All devices
All devices
All devices
All devices
See note*
See note*
See note*
A3P1000
A3P1000
A3P1000
Plastic Quad Flat Pack (PQFP)
PQFP with embedded heatspreader
Fine Pitch Ball Grid Array (FBGA)
Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal
information will be available in future revisions of the datasheet.
Revision 13
2-5
ProASIC3 DC and Switching Characteristics
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.425 V)
Junction Temperature (°C)
Array Voltage VCC
(V)
–40°C
0°C
0.93
0.88
0.84
25°C
0.95
0.90
0.87
70°C
1.00
0.95
0.91
85°C
1.02
0.96
0.93
100°C
1.04
1.425
1.500
1.575
0.88
0.83
0.98
0.80
0.94
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 • Quiescent Supply Current Characteristics
A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Typical (25°C)
2 mA
2 mA
2 mA
2 mA
3 mA
3 mA
20 mA
30 mA
5 mA
30 mA
45 mA
8 mA
50 mA
75 mA
Max. (Commercial)
Max. (Industrial)
10 mA 10 mA 10 mA 10 mA 20 mA
15 mA 15 mA 15 mA 15 mA 30 mA
Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static
contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8.
Power per I/O Pin
Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
–
16.22
16.22
5.12
2.13
1.45
18.11
18.11
3.3 V PCI-X
Differential
LVDS
2.5
3.3
2.26
5.72
1.20
1.87
LVPECL
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
2-6
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
3.3
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
–
16.23
16.23
5.14
1.8 V LVCMOS
2.13
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
1.48
18.13
18.13
3.3 V PCI-X
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
3.3
3.3
2.5
1.8
1.5
–
–
–
–
–
17.24
17.24
5.19
1.8 V LVCMOS
2.18
1.5 V LVCMOS (JESD8-11)
Notes:
1.52
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Revision 13
2-7
ProASIC3 DC and Switching Characteristics
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Applicable to Advanced I/O Banks
Static Power
Dynamic Power
CLOAD (pF)
VCCI (V)
PDC3 (mW)2
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
35
35
35
35
35
3.3
3.3
2.5
1.8
1.5
–
–
–
–
–
468.67
468.67
267.48
149.46
103.12
1.8 V LVCMOS
1.5 V LVCMOS
(JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
10
10
3.3
3.3
–
–
201.02
201.02
–
–
2.5
3.3
7.74
88.92
LVPECL
Notes:
19.54
166.52
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1
Applicable to Standard Plus I/O Banks
Static Power
PDC3 (mW)2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
35
35
35
35
35
10
10
3.3
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
–
452.67
452.67
258.32
133.59
92.84
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
184.92
184.92
3.3 V PCI-X
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
P
is the static power (where applicable) measured on VMV.
DC3
3.
P
is the total dynamic power measured on VCC and VMV.
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
2-8
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1
Applicable to Standard I/O Banks
Static Power
PDC3 (mW) 2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz) 3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
35
35
35
35
35
3.3
3.3
2.5
1.8
1.5
–
–
–
–
–
431.08
431.08
247.36
128.46
89.46
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCC and VCCI.
DC3
P
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13
2-9
ProASIC3 DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
Device Specific Dynamic Contributions
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30
PAC2
2.48 1.85 1.35 1.58 0.81 0.81 0.41 0.41
PAC3
0.81
0.12
PAC4
Clock contribution of a VersaTile used as a
sequential module
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a
sequential module
0.07
0.29
0.29
0.70
Second contribution of a VersaTile used as a
sequential module
Contribution of a VersaTile used as a
combinatorial Module
PAC8
PAC9
Average contribution of a routing net
Contribution of an I/O input pin (standard
dependent)
See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PAC10
PAC11
PAC12
PAC13
Contribution of an I/O output pin (standard
dependent)
See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
Average contribution of a RAM block during a
read operation
25.00
30.00
2.60
Average contribution of a RAM block during a
write operation
Dynamic contribution for PLL
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
2-10
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices
Definition
Device Specific Static Power (mW)
Parameter
PDC1
Array static power in Active mode
See Table 2-7 on page 2-6.
PDC2
I/O input pin static power (standard-dependent)
See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PDC3
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PDC4
PDC5
Static PLL contribution
2.55 mW
Bank quiescent power (VCCI-dependent)
See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on
page 2-13.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-13.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Revision 13
2-11
ProASIC3 DC and Switching Characteristics
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA
Fabric User's Guide.
NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
User's Guide.
FCLK is the global clock signal frequency.
N
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
P
S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
N
C-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
F
INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13.
FCLK is the global clock signal frequency.
2-12
Revision 13
ProASIC3 Flash Family FPGAs
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13.
PLL Contribution—P
F
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
1
2
10%
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
1
2
3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
Revision 13
2-13
ProASIC3 DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
Y
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.34 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
High slew rate
LVTTL
tDP = 2.64 ns (Advanced I/O Banks)
tPD = 0.87 ns
I/O Module
(Non-Registered)
Combinational Cell
I/O Module
(Registered)
Y
Output drive strength = 8 mA
High slew rate
LVTTL
t
PY = 1.05 ns
tDP = 3.66 ns (Advanced I/O Banks)
LVPECL
(Applicable
to Advanced
I/O Banks only)
tPD = 0.47 ns
I/O Module
(Non-Registered)
D
Q
Combinational Cell
Y
Output drive strength = 4 mA
LVCMOS 1.5 V
High slew rate
t
ICLKQ = 0.24 ns
t
DP = 3.97 ns (Advanced I/O Banks)
tPD = 0.47 ns
tISUD = 0.26 ns
Input LVTTL
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
t
PY = 0.76 ns (Advanced I/O Banks)
Y
D
Q
D
Q
D
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
I/O Module
(Non-Registered)
tPD = 0.47 ns
tDP = 2.64 ns
(Advanced I/O Banks)
tCLKQ = 0.55 ns
SUD = 0.43 ns
t
t
OCLKQ = 0.59 ns
OSUD = 0.31 ns
t
CLKQ = 0.55 ns
LVDS,
BLVDS,
M-LVDS
t
tSUD = 0.43 ns
Input LVTTL
Clock
Input LVTTL
Clock
(Applicable for
Advanced I/O
Banks only)
tPY = 1.20 ns
tPY = 0.76 ns
tPY = 0.76 ns
(Advanced I/O Banks)
(Advanced I/O Banks)
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case
VCC = 1.425 V
2-14
Revision 13
ProASIC3 Flash Family FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
t
t
PY = MAX(tPY(R), tPY(F))
DIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VIL
PAD
VCC
50%
50%
Y
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-3 • Input Buffer Timing Model and Delays (example)
Revision 13
2-15
ProASIC3 DC and Switching Characteristics
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-4 • Output Buffer Model and Delays (example)
2-16
Revision 13
ProASIC3 Flash Family FPGAs
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
Revision 13
2-17
ProASIC3 DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
Equiv.
Software
VIL
VIH
VOL
VOH
IOL1 IOH1
Default
Drive
Drive Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard Strength Option2 Rate
V
mA mA
3.3 V LVTTL / 12 mA
3.3 V
LVCMOS
12 mA High –0.3
12 mA High –0.3
12 mA High –0.3
0.8
2
3.6
3.6
2.7
0.4
2.4
12
12
3.3 V
100 µA
0.8
0.7
2
0.2
VCCI – 0.2 0.1 0.1
LVCMOS
Wide Range3
2.5 V
LVCMOS
12 mA
12 mA
12 mA
1.7
0.7
1.7
12
12
12
12
1.8 V
LVCMOS
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45 12
1.5 V
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 12
LVCMOS
3.3 V PCI
3.3 V PCI-X
Notes:
Per PCI specifications
Per PCI-X specifications
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
2-18
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
Equiv.
Software
Default
IOH
1
VIL
VIH
VOL
VOH
IOL1
Drive
Drive Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard Strength Option2 Rate
V
mA mA
3.3 V LVTTL / 12 mA
3.3 V
LVCMOS
12 mA High –0.3
12 mA High –0.3
12 mA High –0.3
0.8
2
3.6
3.6
2.7
0.4
2.4
12 12
3.3 V
100 µA
0.8
0.7
2
0.2
VCCI – 0.2 0.1 0.1
LVCMOS
Wide Range3
2.5 V
LVCMOS
12 mA
8 mA
4 mA
1.7
0.7
1.7
12 12
1.8 V
LVCMOS
8 mA
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45
8
4
8
4
1.5 V
High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI
LVCMOS
3.3 V PCI
3.3 V PCI-X
Notes:
Per PCI specifications
Per PCI-X specifications
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13
2-19
ProASIC3 DC and Switching Characteristics
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
Equiv.
Software
VIL
VIH
VOL
VOH
IOL1 IOH1
Default
Drive
Drive Strength Slew Min.
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
I/O Standard Strength Option2 Rate
V
mA mA
3.3 V LVTTL / 8 mA
3.3 V
LVCMOS
8 mA
High –0.3
High –0.3
High –0.3
0.8
2
3.6
3.6
3.6
0.4
2.4
8
8
3.3 V
100 µA
8 mA
0.8
0.7
2
0.2
VCCI – 0.2 0.1 0.1
LVCMOS
Wide Range3
2.5 V
LVCMOS
8 mA
4 mA
2 mA
8 mA
4 mA
2 mA
1.7
0.7
1.7
8
4
2
8
4
2
1.8 V
LVCMOS
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45
1.5 V
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
LVCMOS
Notes:
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
IIH4
Industrial2
IIL3
µA
10
10
10
10
10
10
10
IIL3
µA
15
15
15
15
15
15
15
IIH4
µA
15
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
µA
10
10
10
10
10
10
10
3.3 V PCI-X
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3. IIL is the input leakage current per I/O pin over recommended operation conditions where
–0.3V < V <V .
IN
IL
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
2-20
Revision 13
ProASIC3 Flash Family FPGAs
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip
)
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.4 V
1.4 V
1.2 V
1.8 V LVCMOS
0.90 V
1.5 V LVCMOS
0.75 V
3.3 V PCI
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V PCI-X
Table 2-23 • I/O AC Parameter Definitions
Parameter
tDP
Parameter Definition
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
tPY
tDOUT
tEOUT
tDIN
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
tHZ
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
tZH
tLZ
tZL
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
Revision 13
2-21
ProASIC3 DC and Switching Characteristics
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Advanced I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 35
–
–
0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns
0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns
3.3 V LVCMOS 100 µA 12 mA High 35
Wide Range2
2.5 V LVCMOS 12 mA 12 mA High 35
1.8 V LVCMOS 12 mA 12 mA High 35
1.5 V LVCMOS 12 mA 12 mA High 35
–
–
–
0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns
0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns
0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns
3.3 V PCI
Per
PCI
–
High 10 25 4 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
spec
3.3 V PCI-X
Per
PCI-X
spec
–
High 10 25 4 0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
LVDS
24 mA
24 mA
–
–
High
High
–
–
–
–
0.45 1.37 0.03 1.20
0.45 1.34 0.03 1.05
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
LVPECL
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.
2-22
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Standard Plus I/O Banks
I/O Standard
3.3 V LVTTL / 12 mA 12 mA High 35
3.3 V LVCMOS
–
–
0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns
0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns
3.3 V LVCMOS 100 µA 12 mA High 35
Wide Range2
2.5 V LVCMOS 12 mA 12 mA High 35
1.8 V LVCMOS 8 mA 8 mA High 35
1.5 V LVCMOS 4 mA 4 mA High 35
–
–
–
0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns
0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns
0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns
3.3 V PCI
3.3 V PCI-X
Notes:
Per
PCI
spec
–
High 10 25 4 0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
Per
PCI-X
spec
–
High 10 25 4 0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for
connectivity. This resistor is not required during normal operation.
Revision 13
2-23
ProASIC3 DC and Switching Characteristics
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
Standard I/O Banks
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
8 mA 8 mA High
35
35
–
–
0.45 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns
0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77 3.11 ns
3.3 V LVCMOS 100 µA 8 mA High
Wide Range2
2.5 V LVCMOS 8 mA 8 mA High
1.8 V LVCMOS 4 mA 4 mA High
1.5 V LVCMOS 2 mA 2 mA High
Notes:
35
35
35
–
–
–
0.45 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns
0.45 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns
0.45 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-24
Revision 13
ProASIC3 Flash Family FPGAs
Detailed I/O DC Characteristics
Table 2-27 • Input Capacitance
Symbol
CIN
Definition
Input capacitance
Input capacitance on the clock pin
Conditions
Min. Max. Units
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
pF
pF
CINCLK
Table 2-28 • I/O Output Buffer Maximum Resistances1
Applicable to Advanced I/O Banks
Standard
Drive Strength
2 mA
RPULL-DOWN ()2
RPULL-UP ()3
3.3 V LVTTL / 3.3 V LVCMOS
100
100
50
300
300
150
150
75
4 mA
6 mA
8 mA
50
12 mA
16 mA
24 mA
100 µA
25
17
50
11
33
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
100
100
50
200
200
100
100
50
50
25
20
40
11
22
1.8 V LVCMOS
200
100
50
225
112
56
50
56
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
33
37
33
37
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
25
75
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
3.
R
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
Revision 13
2-25
ProASIC3 DC and Switching Characteristics
Table 2-29 • I/O Output Buffer Maximum Resistances 1
Applicable to Standard Plus I/O Banks
Standard
Drive Strength
R
PULL-DOWN ()2
RPULL-UP ()3
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
100
100
50
300
300
150
150
75
6 mA
8 mA
50
12 mA
16 mA
100 µA
25
25
75
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
Same as regular Same as regular
3.3 V LVCMOS
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
100
100
50
200
200
100
100
50
50
25
1.8 V LVCMOS
1.5 V LVCMOS
200
100
50
225
112
56
50
56
200
100
25
224
112
75
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
3.
R
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
2-26
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-30 • I/O Output Buffer Maximum Resistances1
Applicable to Standard I/O Banks
RPULL-DOWN
RPULL-UP
Standard
Drive Strength
2 mA
()2
100
100
50
()3
3.3 V LVTTL / 3.3 V LVCMOS
300
300
150
150
4 mA
6 mA
8 mA
50
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
100
100
50
200
200
100
100
225
112
224
50
1.8 V LVCMOS
200
100
200
1.5 V LVCMOS
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2.
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
3.
R
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
()
()
VCCI
Min.
10 k
10 k
11 k
18 k
19 k
Max.
45 k
45 k
55 k
70 k
90 k
Min.
10 k
10 k
12 k
17 k
19 k
Max.
45 k
3.3 V
3.3 V (wide range I/Os)
45 k
2.5 V
1.8 V
1.5 V
Notes:
74 k
110 k
140 k
1.
2.
R
R
= (VCCI
– VOH
) / I
spec (WEAK PULL-UP-MIN)
(WEAK PULL-UP-MAX)
(WEAK PULL-DOWN-MAX)
MAX
= (VOL
) / I
(WEAK PULL-DOWN-MIN)
spec
Revision 13
2-27
ProASIC3 DC and Switching Characteristics
Table 2-32 • I/O Short Currents IOSH/IOSL
Applicable to Advanced I/O Banks
Drive Strength
IOSL (mA)1
IOSH (mA)1
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
27
27
25
25
6 mA
54
51
8 mA
54
51
12 mA
16 mA
24 mA
100 µA
109
127
181
103
132
268
3.3 V LVCMOS Wide Range2
2.5 V LVCMOS
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
18
18
37
37
74
87
124
11
16
16
32
32
65
83
169
9
1.8 V LVCMOS
22
44
51
74
74
16
33
39
55
55
109
17
35
45
91
91
13
25
32
66
66
103
1.5 V LVCMOS
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Notes:
1. T = 100°C
J
2. Applicable to 3.3 V LVCMOS Wide Range. I
/I
dependent on the I/O buffer drive strength selected
OSL OSH
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD8-B specification.
2-28
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-33 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
27
27
25
25
6 mA
54
51
8 mA
54
51
12 mA
16 mA
100 µA
109
109
103
103
3.3 V LVCMOS Wide Range2
2.5 V LVCMOS
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
18
18
37
37
74
11
16
16
32
32
65
9
1.8 V LVCMOS
1.5 V LVCMOS
22
44
44
16
33
109
17
35
35
13
25
103
3.3 V PCI/PCI-X
Per PCI/PCI-X
specification
Notes:
1. T = 100°C
J
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength
selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range as specified in the JESD8-B specification.
Revision 13
2-29
ProASIC3 DC and Switching Characteristics
Table 2-34 • I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
27
27
54
54
25
25
51
51
6 mA
8 mA
3.3 V LVCMOS Wide Range2
2.5 V LVCMOS
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
18
18
37
37
11
22
16
16
16
32
32
9
1.8 V LVCMOS
17
13
1.5 V LVCMOS
Notes:
1. T = 100°C
J
2. Applicable to 3.3 V LVCMOS Wide Range. I
/I
dependent on the I/O buffer drive strength selected
OSL OSH
for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as
specified in the JESD-8B specification.
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-35 • Duration of Short Circuit Event Before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
6 months
Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
No requirement
No requirement
10 ns *
10 ns *
20 years (110°C)
10 years (100°C)
LVDS/B-LVDS/
M-LVDS/LVPECL
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum
value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure that
there is no excessive noise coupling into input signals.
2-30
Revision 13
ProASIC3 Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-37 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2
2
27
27
25
25
4 mA
4
4
6 mA
6
6
54
51
8 mA
8
8
54
51
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
109
127
181
103
132
268
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-38 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
2
27
27
25
25
4 mA
4
6 mA
6
54
51
8 mA
8
8
54
51
12 mA
16 mA
Notes:
12
16
12
16
109
109
103
103
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Revision 13
2-31
ProASIC3 DC and Switching Characteristics
Table 2-39 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
2
2
2
2
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2
4
6
2
25
25
51
51
27
27
54
54
4 mA
4
6 mA
6
8 mA
8
8
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
I
IH
larger when operating outside recommended ranges
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Enable Path
Test Point
Datapath
35 pF
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-6 • AC Loading
Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
3.3
1.4
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
2-32
Revision 13
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS
8.82
7.51
6.59
6.31
5.36
4.71
6.31
5.36
4.71
5.06
4.30
3.78
4.80
4.08
3.58
4.35
3.70
3.25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
7.66 0.04 1.02
6.51 0.04 0.86
5.72 0.03 0.76
4.91 0.04 1.02
4.17 0.04 0.86
3.66 0.03 0.76
4.91 0.04 1.02
4.17 0.04 0.86
3.66 0.03 0.76
3.53 0.04 1.02
3.00 0.04 0.86
2.64 0.03 0.76
3.33 0.04 1.02
2.83 0.04 0.86
2.49 0.03 0.76
3.08 0.04 1.02
2.62 0.04 0.86
2.30 0.03 0.76
7.80 6.59 2.65 2.61 10.03
6.63 5.60 2.25 2.22
5.82 4.92 1.98 1.95
5.00 4.07 2.99 3.20
4.25 3.46 2.54 2.73
3.73 3.04 2.23 2.39
5.00 4.07 2.99 3.20
4.25 3.46 2.54 2.73
3.73 3.04 2.23 2.39
3.60 2.82 3.21 3.58
3.06 2.40 2.73 3.05
2.69 2.11 2.40 2.68
3.39 2.56 3.26 3.68
2.89 2.18 2.77 3.13
2.53 1.91 2.44 2.75
3.13 2.12 3.32 4.06
2.66 1.80 2.83 3.45
2.34 1.58 2.48 3.03
8.54
7.49
7.23
6.15
5.40
7.23
6.15
5.40
5.83
4.96
4.36
5.63
4.79
4.20
5.37
4.57
4.01
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-33
ProASIC3 DC and Switching Characteristics
Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
10.45
8.89
7.80
7.41
6.30
5.53
7.41
6.30
5.53
5.68
4.84
4.24
5.30
4.51
3.96
4.94
4.20
3.69
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
10.26 0.04 1.02 0.43
8.72 0.04 0.86 0.36
7.66 0.03 0.76 0.32
7.27 0.04 1.02 0.43
6.19 0.04 0.86 0.36
5.43 0.03 0.76 0.32
7.27 0.04 1.02 0.43
6.19 0.04 0.86 0.36
5.43 0.03 0.76 0.32
5.58 0.04 1.02 0.43
4.75 0.04 0.86 0.36
4.17 0.03 0.76 0.32
5.21 0.04 1.02 0.43
4.43 0.04 0.86 0.36
3.89 0.03 0.76 0.32
4.85 0.04 1.02 0.43
4.13 0.04 0.86 0.36
3.62 0.03 0.76 0.32
8.90 2.64 2.46 12.68 11.13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.57 2.25 2.09 10.79
6.64 1.98 1.83 9.47
6.28 2.98 3.04 9.65
5.35 2.54 2.59 8.20
4.69 2.23 2.27 7.20
6.28 2.98 3.04 9.65
5.35 2.54 2.59 8.20
4.69 2.23 2.27 7.20
4.87 3.21 3.42 7.92
4.14 2.73 2.91 6.74
3.64 2.39 2.55 5.91
4.56 3.26 3.51 7.54
3.88 2.77 2.99 6.41
3.41 2.43 2.62 5.63
4.54 3.32 3.88 7.18
3.87 2.82 3.30 6.10
3.39 2.48 2.90 5.36
9.47
8.31
8.52
7.25
6.36
8.52
7.25
6.36
7.11
6.05
5.31
6.80
5.79
5.08
6.78
5.77
5.06
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-34
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
9.57
8.14
7.15
6.82
5.80
5.09
6.82
5.80
5.09
5.45
4.64
4.07
5.45
4.64
4.07
tZHS
8.52
7.25
6.36
6.05
5.15
4.52
6.05
5.15
4.52
4.82
4.10
3.60
4.82
4.10
3.60
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
7.20 0.04 1.00
6.13 0.04 0.85
5.38 0.03 0.75
4.50 0.04 1.00
3.83 0.04 0.85
3.36 0.03 0.75
4.50 0.04 1.00
3.83 0.04 0.85
3.36 0.03 0.75
3.16 0.04 1.00
2.69 0.04 0.85
2.36 0.03 0.75
3.16 0.04 1.00
2.69 0.04 0.85
2.36 0.03 0.75
7.34 6.29 2.27 2.34
6.24 5.35 1.93 1.99
5.48 4.69 1.70 1.75
4.58 3.82 2.58 2.88
3.90 3.25 2.19 2.45
3.42 2.85 1.92 2.15
4.58 3.82 2.58 2.88
3.90 3.25 2.19 2.45
3.42 2.85 1.92 2.15
3.22 2.58 2.79 3.22
2.74 2.20 2.37 2.74
2.40 1.93 2.08 2.41
3.22 2.58 2.79 3.22
2.74 2.20 2.37 2.74
2.40 1.93 2.08 2.41
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
Notes:
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-35
ProASIC3 DC and Switching Characteristics
Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.68 0.04 1.00 0.43
8.23 0.04 0.85 0.36
7.23 0.03 0.75 0.32
6.70 0.04 1.00 0.43
5.70 0.04 0.85 0.36
5.00 0.03 0.75 0.32
6.70 0.04 1.00 0.43
5.70 0.04 0.85 0.36
5.00 0.03 0.75 0.32
5.05 0.04 1.00 0.43
4.29 0.04 0.85 0.36
3.77 0.03 0.75 0.32
5.05 0.04 1.00 0.43
4.29 0.04 0.85 0.36
3.77 0.03 0.75 0.32
9.86
8.39
7.36
6.82
5.80
5.10
6.82
5.80
5.10
5.14
4.37
3.84
5.14
4.37
3.84
8.42 2.28 2.21 12.09 10.66
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.17 1.94 1.88 10.29
6.29 1.70 1.65 9.03
5.89 2.58 2.74 9.06
5.01 2.20 2.33 7.71
4.40 1.93 2.05 6.76
5.89 2.58 2.74 9.06
5.01 2.20 2.33 7.71
4.40 1.93 2.05 6.76
4.51 2.79 3.08 7.38
3.84 2.38 2.62 6.28
3.37 2.09 2.30 5.51
4.51 2.79 3.08 7.38
3.84 2.38 2.62 6.28
3.37 2.09 2.30 5.51
9.07
7.96
8.12
6.91
6.06
8.12
6.91
6.06
6.75
5.74
5.04
6.75
5.74
5.04
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
Speed
Grade
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
–1
7.07
6.01
5.28
7.07
6.01
5.28
4.41
3.75
3.29
4.41
3.75
3.29
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
7.20
6.12
5.37
7.20
6.12
5.37
4.49
3.82
3.36
4.49
3.82
3.36
6.23
5.30
4.65
6.23
5.30
4.65
3.75
3.19
2.80
3.75
3.19
2.80
2.07
1.76
1.55
2.07
1.76
1.55
2.39
2.04
1.79
2.39
2.04
1.79
2.15
1.83
1.60
2.15
1.83
1.60
2.69
2.29
2.01
2.69
2.29
2.01
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-36
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
Units
ns
2 mA
4 mA
6 mA
8 mA
9.46
8.05
7.07
9.46
8.05
7.07
6.57
5.59
4.91
6.57
5.59
4.91
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
9.64
8.20
7.20
9.64
8.20
7.20
6.69
5.69
5.00
6.69
5.69
5.00
8.54
7.27
6.38
8.54
7.27
6.38
5.98
5.09
4.47
5.98
5.09
4.47
2.07
1.76
1.55
2.07
1.76
1.55
2.40
2.04
1.79
2.40
2.04
1.79
2.04
1.73
1.52
2.04
1.73
1.52
2.57
2.19
1.92
2.57
2.19
1.92
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-37
ProASIC3 DC and Switching Characteristics
3.3 V LVCMOS Wide Range
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V
Equiv.
LVCMOS
Wide Range Default
Drive
Drive
Strength
Software
VIL
VIH
VOL
VOH
IOL IOH IOSL
Max.
IOSH IIL2 IIH3
Strength Min.
Max. Min. Max. Max.
Min.
V
Max.
Option1
2 mA
V
V
V
2
2
2
2
2
2
2
V
V
µA µA
mA4
25
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.2
0.2
0.2
0.2
0.2
0.2
0.2
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
27
27
10 10
10 10
10 10
10 10
10 10
10 10
10 10
4 mA
25
6 mA
51
54
8 mA
51
54
12 mA
16 mA
24 mA
103
132
268
109
127
181
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
Table 2-48 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVCMOS
Wide Range
Equiv.
Software
Default
Drive
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Strength Min. Max. Min. Max. Max.
Min.
V
Max.
Max.
Drive Strength Option1
V
V
V
2
2
2
2
2
2
V
V
µA µA mA4
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
100 µA
100 A
Notes:
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
3.6
3.6
3.6
3.6
3.6
3.6
0.2
0.2
0.2
0.2
0.2
0.2
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
25
25
51
51
27
27
10 10
10 10
10 10
10 10
10 10
10 10
54
54
VDD – 0.2 100 100 103
VDD – 0.2 100 100 103
109
109
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
2-38
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-49 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V
Equiv.
LVCMOS
Wide Range Default
Drive
Drive
Strength
Software
VIL
VIH
VOL
VOH
IOL IOH
µA µA
IOSL
IOSH IIL2 IIH3
Max.
Strength Min. Max. Min. Max. Max.
Min.
V
Max.
mA4
Option1
2 mA
V
V
V
2
2
2
2
V
V
mA4
27
µA5 µA5
10 10
10 10
10 10
10 10
100 µA
100 µA
100 µA
100 µA
Notes:
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
3.6
3.6
3.6
3.6
0.2
0.2
0.2
0.2
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
25
25
51
51
4 mA
27
6 mA
54
8 mA
54
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
Revision 13
2-39
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
Std.
–1
0.60 11.84 0.04 1.02 0.43 11.84 10.00 4.10 4.04 15.23 13.40 ns
0.51 10.07 0.04 0.86 0.36 10.07 8.51 3.48 3.44 12.96 11.40 ns
0.45 8.84 0.03 0.76 0.32 8.84 7.47 3.06 3.02 11.38 10.00 ns
–2
6 mA
8 mA
Std.
–1
0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57
0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14
0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15
0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57
0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14
0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15
0.60 5.46 0.04 1.02 0.43 5.46 4.29 4.97 5.54 8.86 7.68
0.51 4.65 0.04 0.86 0.36 4.65 3.65 4.22 4.71 7.53 6.54
0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74
0.60 5.15 0.04 1.02 0.43 5.15 3.89 5.04 5.69 8.55 7.29
0.51 4.38 0.04 0.86 0.36 4.38 3.31 4.29 4.84 7.27 6.20
0.45 3.85 0.03 0.76 0.32 3.85 2.91 3.77 4.25 6.38 5.44
0.60 4.75 0.04 1.02 0.43 4.75 3.22 5.14 6.28 8.15 6.61
0.51 4.04 0.04 0.86 0.36 4.04 2.74 4.37 5.34 6.93 5.62
0.45 3.55 0.03 0.76 0.32 3.55 2.40 3.84 4.69 6.09 4.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
Std.
–1
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-40
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
Std.
–1
0.60 15.86 0.04 1.54 0.43 15.86 13.51 4.09 3.80 19.25 16.90 ns
0.51 13.49 0.04 1.31 0.36 13.49 11.49 3.48 3.23 16.38 14.38 ns
0.45 11.84 0.03 1.15 0.32 11.84 10.09 3.05 2.84 14.38 12.62 ns
0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns
0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns
–2
4 mA
6 mA
Std.
–1
–2
0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66
ns
Std.
–1
0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns
0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns
–2
0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66
ns
8 mA
Std.
–1
0.60 8.63 0.04 1.54 0.43 8.63 7.39 4.96 5.28 12.02 10.79 ns
0.51 7.34 0.04 1.31 0.36 7.34 6.29 4.22 4.49 10.23 9.18
0.45 6.44 0.03 1.15 0.32 6.44 5.52 3.70 3.94 8.98 8.06
ns
ns
–2
16 mA
24 mA
Std.
–1
0.60 8.05 0.04 1.54 0.43 8.05 6.93 5.03 5.43 11.44 10.32 ns
0.51 6.85 0.04 1.31 0.36 6.85 5.90 4.28 4.62 9.74 8.78
0.45 6.01 0.03 1.15 0.32 6.01 5.18 3.76 4.06 8.55 7.71
ns
ns
–2
Std.
–1
0.60 7.50 0.04 1.54 0.43 7.50 6.90 5.13 6.00 10.89 10.29 ns
0.51 6.38 0.04 1.31 0.36 6.38 5.87 4.36 5.11 9.27 8.76
0.45 5.60 0.03 1.15 0.32 5.60 5.15 3.83 4.48 8.13 7.69
ns
ns
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-41
ProASIC3 DC and Switching Characteristics
Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
Std.
–1
0.60 11.14 0.04 1.52 0.43 11.14 9.54 3.51 3.61 14.53 12.94 ns
0.51 9.48 0.04 1.29 0.36 9.48 8.12 2.99 3.07 12.36 11.00 ns
–2
0.45 8.32 0.03 1.14 0.32 8.32 7.13 2.62 2.70 10.85 9.66
0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19
0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82
0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86
0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19
0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82
0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86
0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32
0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22
0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46
0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32
0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22
0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
6 mA
8 mA
16 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-42
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength Speed
Option1
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
Std.
–1
0.60 14.97 0.04 1.52 0.43 14.97 12.79 3.52 3.41 18.36 16.18 ns
0.51 12.73 0.04 1.29 0.36 12.73 10.88 2.99 2.90 15.62 13.77 ns
0.45 11.18 0.03 1.14 0.32 11.18 9.55 2.63 2.55 13.71 12.08 ns
0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns
0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns
–2
4 mA
6 mA
8 mA
16 mA
Std.
–1
–2
0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21
ns
Std.
–1
0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns
0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns
–2
0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21
ns
Std.
–1
0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns
0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71
0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65
ns
ns
–2
Std.
–1
0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns
0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71
0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65
ns
ns
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-43
ProASIC3 DC and Switching Characteristics
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
Std.
–1
10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.29
8.16
0.04 1.29 0.36
0.03 1.13 0.32
9.29
8.16
8.04 2.72 2.82
7.06 2.39 2.48
–2
Std.
–1
10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32
9.29
8.16
6.82
5.80
5.09
6.82
5.80
5.09
0.04 1.29 0.36
0.03 1.13 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.13 0.32
0.04 1.52 0.43
0.04 1.29 0.36
0.03 1.13 0.32
9.29
8.16
6.82
5.80
5.09
6.82
5.80
5.09
8.04 2.72 2.82
7.06 2.39 2.48
5.70 3.70 4.16
4.85 3.15 3.54
4.25 2.77 3.11
5.70 3.70 4.16
4.85 3.15 3.54
4.25 2.77 3.11
–2
Std.
–1
–2
Std.
–1
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-44
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Equiv.
Software
Default
Drive
Drive
Strength
Strength
Speed
Grade
Option1
tDOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
tDP
tDIN tPY tEOUT
tZL
tZH
tLZ
tHZ Units
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
6 mA
8 mA
Std.
–1
14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15
12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68
10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35
14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15
12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68
10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35
10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
Std.
–1
–2
Std.
–1
8.64 0.04 1.29 0.36
7.58 0.03 1.13 0.32
8.64
7.58
7.73 3.15 3.39
6.78 2.77 2.97
–2
Std.
–1
10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98
8.64 0.04 1.29 0.36
7.58 0.03 1.13 0.32
8.64
7.58
7.73 3.15 3.39
6.78 2.77 2.97
–2
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-45
ProASIC3 DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-56 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2
4
6
8
2
4
6
8
18
18
16
16
4 mA
6 mA
37
32
8 mA
37
32
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
74
65
87
83
124
169
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
2.5 V LVCMOS
VIL
VIH
Max.
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
V
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
2
18
18
37
37
74
16
16
32
32
65
4 mA
4
4
6 mA
6
6
8 mA
8
8
12 mA
Notes:
12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-46
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-58 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
2.5 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.,
V
Min.
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
2 mA
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
2
2
16
16
32
32
18
18
37
37
4 mA
4
4
6 mA
6
6
8 mA
8
8
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
2.5
1.2
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Revision 13
2-47
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-60 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 mA
Std.
–1
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
8.66
7.37
6.47
5.17
4.39
3.86
5.17
4.39
3.86
3.56
3.03
2.66
3.35
2.85
2.50
3.09
2.63
2.31
0.04 1.31
0.04 1.11
0.03 0.98
0.04 1.31
0.04 1.11
0.03 0.98
0.04 1.31
0.04 1.11
0.03 0.98
0.04 1.31
0.04 1.11
0.03 0.98
0.04 1.31
0.04 1.11
0.03 0.98
0.04 1.31
0.04 1.11
0.03 0.98
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
7.83
6.66
5.85
5.04
4.28
3.76
5.04
4.28
3.76
3.63
3.08
2.71
3.41
2.90
2.55
3.15
2.68
2.35
8.66
7.37
6.47
5.17
4.39
3.86
5.17
4.39
3.86
3.43
2.92
2.56
3.06
2.60
2.29
2.44
2.08
1.82
2.68 2.30 10.07 10.90
2.28 1.96
2.00 1.72
3.05 3.00
2.59 2.55
2.28 2.24
3.05 3.00
2.59 2.55
2.28 2.24
3.30 3.44
2.81 2.92
2.47 2.57
3.36 3.55
2.86 3.02
2.51 2.65
3.44 4.00
2.92 3.40
2.57 2.98
8.56
7.52
7.27
6.19
5.43
7.27
6.19
5.43
5.86
4.99
4.38
5.65
4.81
4.22
5.38
4.58
4.02
9.27
8.14
7.40
6.30
5.53
7.40
6.30
5.53
5.67
4.82
4.23
5.30
4.51
3.96
4.68
3.98
3.49
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-48
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-61 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
11.40 0.04 1.31 0.43
9.69 0.04 1.11 0.36
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
11.22 11.40 2.68 2.20 13.45 13.63
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.54
8.38
8.11
6.90
6.05
8.11
6.90
6.05
6.29
5.35
4.70
5.87
4.99
4.38
5.50
4.68
4.11
9.69 2.28 1.88 11.44 11.60
8.51 2.00 1.65 10.05 10.18
7.81 3.05 2.89 10.34 10.05
–2
8.51 0.03 0.98 0.32
7.96 0.04 1.31 0.43
6 mA
Std.
–1
6.77 0.04 1.11
0.36
6.65 2.59 2.46 8.80
5.84 2.28 2.16 7.72
8.55
7.50
–2
5.94 0.03 0.98 0.32
7.96 0.04 1.31 0.43
8 mA
Std.
–1
7.81 3.05 2.89 10.34 10.05
6.77 0.04 1.11
0.36
6.65 2.59 2.46 8.80
5.84 2.28 2.16 7.72
5.92 3.30 3.32 8.53
5.03 2.81 2.83 7.26
4.42 2.47 2.48 6.37
8.55
7.50
8.15
6.94
6.09
7.76
6.60
5.80
7.74
6.59
5.78
–2
5.94 0.03 0.98 0.32
6.18 0.04 1.31 0.43
12 mA
16 mA
24 mA
Std.
–1
5.26 0.04 1.11
0.36
–2
4.61 0.03 0.98 0.32
5.76 0.04 1.31 0.43
Std.
–1
5.53 3.36 3.44
8.11
4.90 0.04 1.11
0.36
4.70 2.86 2.92 6.90
4.13 2.51 2.57 6.05
5.51 3.43 3.87 7.74
4.68 2.92 3.29 6.58
–2
4.30 0.03 0.98 0.32
5.51 0.04 1.31 0.43
Std.
–1
4.68 0.04 1.11
0.36
–2
4.11 0.03 0.98 0.32
4.11
2.56 2.89 5.78
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-49
ProASIC3 DC and Switching Characteristics
Table 2-62 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
9.64
8.20
7.20
6.88
5.85
5.14
6.88
5.85
5.14
5.50
4.68
4.11
tZHS
10.51
8.94
7.85
7.09
6.03
5.29
7.09
6.03
5.29
5.38
4.57
4.02
Units
ns
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.28 0.04 1.30
7.04 0.04 1.10
6.18 0.03 0.97
4.85 0.04 1.30
4.13 0.04 1.10
3.62 0.03 0.97
4.85 0.04 1.30
4.13 0.04 1.10
3.62 0.03 0.97
3.21 0.04 1.30
2.73 0.04 1.10
2.39 0.03 0.97
7.41 8.28 2.25 2.07
6.30 7.04 1.92 1.76
5.53 6.18 1.68 1.55
4.65 4.85 2.59 2.71
3.95 4.13 2.20 2.31
3.47 3.62 1.93 2.02
4.65 4.85 2.59 2.71
3.95 4.13 2.20 2.31
3.47 3.62 1.93 2.02
3.27 3.14 2.82 3.11
2.78 2.67 2.40 2.65
2.44 2.35 2.11 2.32
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-63 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
10.84 0.04 1.30 0.43
9.22 0.04 1.10 0.36
8.10 0.03 0.97 0.32
7.37 0.04 1.30 0.43
6.27 0.04 1.10 0.36
5.50 0.03 0.97 0.32
7.37 0.04 1.30 0.43
6.27 0.04 1.10 0.36
5.50 0.03 0.97 0.32
5.63 0.04 1.30 0.43
4.79 0.04 1.10 0.36
4.20 0.03 0.97 0.32
10.64 10.84 2.26 1.99 12.87 13.08
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.05
7.94
7.50
6.38
5.60
7.50
6.38
5.60
5.73
4.88
4.28
9.22 1.92 1.69 10.95 11.12
–2
8.10 1.68 1.49 9.61
7.36 2.59 2.61 9.74
6.26 2.20 2.22 8.29
5.50 1.93 1.95 7.27
7.36 2.59 2.61 9.74
6.26 2.20 2.22 8.29
5.50 1.93 1.95 7.27
5.51 2.83 3.01 7.97
4.68 2.41 2.56 6.78
9.77
9.60
8.16
7.17
9.60
8.16
7.17
7.74
6.59
5.78
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
4.11
2.11 2.25 5.95
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-50
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-64 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
8.20
6.98
6.13
8.20
6.98
6.13
4.77
4.05
3.56
4.77
4.05
3.56
1.29
1.10
0.96
1.29
1.10
0.96
1.29
1.10
0.96
1.29
1.10
0.96
7.24
6.16
5.41
7.24
6.16
5.41
4.55
3.87
3.40
4.55
3.87
3.40
8.20
6.98
6.13
8.20
6.98
6.13
4.77
4.05
3.56
4.77
4.05
3.56
2.03
1.73
1.52
2.03
1.73
1.52
2.38
2.03
1.78
2.38
2.03
1.78
1.91
1.62
1.43
1.91
1.62
1.43
2.55
2.17
1.91
2.55
2.17
1.91
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-65 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
tDP
11.00
9.35
8.21
11.00
9.35
8.21
7.50
6.38
5.60
7.50
6.38
5.60
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
10.37
8.83
7.75
10.37
8.83
7.75
7.36
6.26
5.49
7.36
6.26
5.49
tZH
11.00
9.35
8.21
11.00
9.35
8.21
7.50
6.38
5.60
7.50
6.38
5.60
tLZ
tHZ
Units
ns
2 mA
4 mA
6 mA
8 mA
1.29
1.10
0.96
1.29
1.10
0.96
1.29
1.10
0.96
1.29
1.10
0.96
2.03
1.73
1.52
2.03
1.73
1.52
2.39
2.03
1.78
2.39
2.03
1.78
1.83
1.56
1.37
1.83
1.56
1.37
2.46
2.10
1.84
2.46
2.10
1.84
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-51
ProASIC3 DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-66 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.8 V
LVCMOS
VIL
Max.,
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA3
mA3 µA4 µA4
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.35 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
0.65 * VCCI
1.9
1.9
1.9
1.9
1.9
1.9
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
2
4
11
22
44
51
74
74
9
10 10
10 10
10 10
10 10
10 10
10 10
4 mA
17
35
45
91
91
6 mA
6
6
8 mA
8
8
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-67 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
V
mA mA mA3 mA3 µA4 µA4
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
11
22
44
44
9
10 10
10 10
10 10
10 10
17
35
35
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-52
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-68 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS
VIL
Max.
VIH
Min.
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Max. Max.
Drive
Strength
Min.
V
Max. Max.
Min.
V
V
V
V
V
mA mA mA3
mA3 µA4 µA4
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6 0.45 VCCI – 0.45
3.6 0.45 VCCI – 0.45
2
4
2
4
9
11
22
10 10
10 10
17
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Revision 13
2-53
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-70 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
11.86 0.04 1.22 0.43
10.09 0.04 1.04 0.36
8.86 0.03 0.91 0.32
6.91 0.04 1.22 0.43
5.88 0.04 1.04 0.36
5.16 0.03 0.91 0.32
4.45 0.04 1.22 0.43
3.78 0.04 1.04 0.36
3.32 0.03 0.91 0.32
3.92 0.04 1.22 0.43
3.34 0.04 1.04 0.36
2.93 0.03 0.91 0.32
3.53 0.04 1.22 0.43
3.01 0.04 1.04 0.36
2.64 0.03 0.91 0.32
3.53 0.04 1.22 0.43
3.01 0.04 1.04 0.36
2.64 0.03 0.91 0.32
9.14
7.77
6.82
5.86
4.99
4.38
4.18
3.56
3.12
3.93
3.34
2.93
3.60
3.06
2.69
3.60
3.06
2.69
11.86 2.77 1.66 11.37 14.10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.09 2.36 1.41 9.67
8.86 2.07 1.24 8.49
6.91 3.22 2.84 8.10
5.88 2.74 2.41 6.89
5.16 2.41 2.12 6.05
4.45 3.53 3.38 6.42
3.78 3.00 2.88 5.46
3.32 2.64 2.53 4.79
3.92 3.60 3.52 6.16
3.34 3.06 3.00 5.24
2.93 2.69 2.63 4.60
3.04 3.70 4.08 5.84
2.59 3.15 3.47 4.96
2.27 2.76 3.05 4.36
3.04 3.70 4.08 5.84
2.59 3.15 3.47 4.96
2.27 2.76 3.05 4.36
11.99
10.53
9.15
7.78
6.83
6.68
5.69
4.99
6.16
5.24
4.60
5.28
4.49
3.94
5.28
4.49
3.94
–2
4 mA
Std.
–1
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
Notes:
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-54
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-71 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
15.53 0.04 1.22 0.43
14.11 15.53 2.78 1.60 16.35 17.77
13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11
11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27
10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71
–2
Std.
–1
8.91 0.04 1.04 0.36
7.82 0.03 0.91 0.32
8.05 0.04 1.22 0.43
6.85 0.04 1.04 0.36
6.01 0.03 0.91 0.32
7.50 0.04 1.22 0.43
6.38 0.04 1.04 0.36
5.60 0.03 0.91 0.32
7.29 0.04 1.22 0.43
6.20 0.04 1.04 0.36
5.45 0.03 0.91 0.32
7.29 0.04 1.22 0.43
6.20 0.04 1.04 0.36
5.45 0.03 0.91 0.32
8.86
7.77
8.20
6.97
6.12
7.64
6.50
5.71
7.23
6.15
5.40
7.23
6.15
5.40
8.91 2.75 2.33 10.76 10.81
7.82 2.41 2.04 9.44 9.49
7.84 3.54 3.27 10.43 10.08
–2
Std.
–1
6.67 3.01 2.78 8.88
5.86 2.64 2.44 7.79
7.30 3.61 3.41 9.88
6.21 3.07 2.90 8.40
5.45 2.69 2.55 7.38
7.29 3.71 3.95 9.47
6.20 3.15 3.36 8.06
5.45 2.77 2.95 7.07
7.29 3.71 3.95 9.47
6.20 3.15 3.36 8.06
5.45 2.77 2.95 7.07
8.57
7.53
9.53
8.11
7.12
9.53
8.11
7.12
9.53
8.11
7.12
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-55
ProASIC3 DC and Switching Characteristics
Table 2-72 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY tEOUT
tZL
tZH
11.33 2.24 1.52 10.96 13.57
9.64 1.91 1.29 9.32 11.54
8.46 1.68 1.14 8.18 10.13
tLZ
tHZ
tZLS
tZHS
Units
ns
2 mA
4 mA
6 mA
8 mA
Notes:
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
11.33 0.04 1.20 0.43
9.64 0.04 1.02 0.36
8.46 0.03 0.90 0.32
6.48 0.04 1.20 0.43
5.51 0.04 1.02 0.36
4.84 0.03 0.90 0.32
4.06 0.04 1.20 0.43
3.45 0.04 1.02 0.36
3.03 0.03 0.90 0.32
4.06 0.04 1.20 0.43
3.45 0.04 1.02 0.36
3.03 0.03 0.90 0.32
8.72
7.42
6.51
5.48
4.66
4.09
3.84
3.27
2.87
3.84
3.27
2.87
ns
–2
ns
Std.
–1
6.48 2.65 2.60 7.72
5.51 2.25 2.21 6.56
4.84 1.98 1.94 5.76
4.06 2.93 3.10 6.07
3.45 2.49 2.64 5.17
3.03 2.19 2.32 4.54
4.06 2.93 3.10 6.07
3.45 2.49 2.64 5.17
3.03 2.19 2.32 4.54
8.72
7.42
6.51
6.30
5.36
4.70
6.30
5.36
4.70
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
Std.
–1
ns
ns
–2
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-56
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-73 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
14.80 0.04 1.20
12.59 0.04 1.02
11.05 0.03 0.90
0.43 13.49 14.80 2.25 1.46 15.73 17.04
0.36 11.48 12.59 1.91 1.25 13.38 14.49
0.32 10.08 11.05 1.68 1.09 11.75 12.72
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
Std.
–1
9.90
8.42
7.39
7.44
6.33
5.55
7.44
6.33
5.55
0.04 1.20
0.04 1.02
0.03 0.90
0.04 1.20
0.04 1.02
0.03 0.90
0.04 1.20
0.04 1.02
0.03 0.90
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
9.73
8.28
7.27
7.58
6.44
5.66
7.58
6.44
5.66
9.90 2.65 2.50 11.97 12.13
8.42 2.26 2.12 10.18 10.32
–2
7.39 1.98 1.86 8.94
7.32 2.94 2.99 9.81
6.23 2.50 2.54 8.35
5.47 2.19 2.23 7.33
7.32 2.94 2.99 9.81
6.23 2.50 2.54 8.35
5.47 2.19 2.23 7.33
9.06
9.56
8.13
7.14
9.56
8.13
7.14
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-74 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard I/O Banks
Drive
Strength
Speed
Grade
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
tDP
11.21
9.54
8.37
6.34
5.40
4.74
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
11.21
9.54
8.37
6.34
5.40
4.74
tLZ
tHZ
Units
ns
2 mA
4 mA
Notes:
Std.
–1
1.20
1.02
0.90
1.20
1.02
0.90
8.53
7.26
6.37
5.38
4.58
4.02
1.99
1.69
1.49
2.41
2.05
1.80
1.21
1.03
0.90
2.48
2.11
1.85
ns
–2
ns
Std.
–1
ns
ns
–2
ns
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-57
ProASIC3 DC and Switching Characteristics
Table 2-75 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
tZL
13.15
11.19
9.82
9.55
8.13
7.13
tZH
tLZ
tHZ
Units
ns
2 mA
15.01
12.77
11.21
10.10
8.59
1.20
1.02
0.90
1.20
1.02
0.90
15.01
12.77
11.21
10.10
8.59
1.99
1.70
1.49
2.41
2.05
1.80
1.99
1.70
1.49
2.37
2.02
1.77
ns
–2
ns
4 mA
Std.
–1
ns
ns
–2
7.54
7.54
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-76 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Max.,
V
Max.
V
Min.
V
Max. Max.
V
mA mA mA3 mA3 µA4 µA4
2 mA
4 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
16
33
39
55
55
13
25
32
66
66
10 10
10 10
10 10
10 10
10 10
6 mA
6
8 mA
8
12 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2-58
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-77 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL1 IIH2
Drive
Strength
Min.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
V
mA mA mA3
mA3 µA4 µA4
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
2
4
16
33
13
25
10 10
10 10
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Table 2-78 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.5 V
LVCMOS
VIL
Max.
VIH
Min.
V
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Max.
V
Min.
V
Max. Max.
V
mA mA mA3 mA3 µA4 µA4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
2
13
16
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
35
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Revision 13
2-59
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-80 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade tDOUT
tDP
tDIN
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
tZL
6.82 8.36 3.39 2.77 9.06 10.60
5.80 7.11 2.88 2.35 7.71
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.36 0.04 1.44
7.11 0.04 1.22
6.24 0.03 1.07
5.31 0.04 1.44
4.52 0.04 1.22
3.97 0.03 1.07
4.67 0.04 1.44
3.97 0.04 1.22
3.49 0.03 1.07
4.08 0.04 1.44
3.47 0.04 1.22
3.05 0.03 1.07
4.08 0.04 1.44
3.47 0.04 1.22
3.05 0.03 1.07
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.02
7.91
7.55
6.42
5.64
6.90
5.87
5.16
5.81
4.95
4.34
5.81
4.95
4.34
–2
5.10 6.24 2.53 2.06 6.76
4.85 5.31 3.74 3.40 7.09
4.13 4.52 3.18 2.89 6.03
3.62 3.97 2.79 2.54 5.29
4.55 4.67 3.82 3.56 6.78
3.87 3.97 3.25 3.03 5.77
3.40 3.49 2.85 2.66 5.07
4.15 3.58 3.94 4.20 6.39
3.53 3.04 3.36 3.58 5.44
3.10 2.67 2.95 3.14 4.77
4.15 3.58 3.94 4.20 6.39
3.53 3.04 3.36 3.58 5.44
3.10 2.67 2.95 3.14 4.77
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-60
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-81 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Advanced I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
tPY tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02
10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
9.55 0.03 1.07 0.32
9.57 9.55 2.54 1.97 11.24 11.22
Std.
–1
10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78
8.51 0.04 1.22 0.36
7.47 0.03 1.07 0.32
9.33 0.04 1.44 0.43
7.94 0.04 1.22 0.36
6.97 0.03 1.07 0.32
8.91 0.04 1.44 0.43
7.58 0.04 1.22 0.36
6.65 0.03 1.07 0.32
8.91 0.04 1.44 0.43
7.58 0.04 1.22 0.36
6.65 0.03 1.07 0.32
8.67 8.12 3.19 2.78 10.57 10.02
7.61 7.13 2.80 2.44 9.28 8.80
9.51 8.89 3.83 3.43 11.74 11.13
–2
Std.
–1
8.09 7.56 3.26 2.92 9.99
7.10 6.64 2.86 2.56 8.77
9.47
8.31
–2
Std.
–1
9.07 8.89 3.95 4.05 11.31 11.13
7.72 7.57 3.36 3.44 9.62
6.78 6.64 2.95 3.02 8.45
9.47
8.31
–2
Std.
–1
9.07 8.89 3.95 4.05 11.31 11.13
7.72 7.57 3.36 3.44 9.62
6.78 6.64 2.95 3.02 8.45
9.47
8.31
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-61
ProASIC3 DC and Switching Characteristics
Table 2-82 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN
tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
Notes:
7.83 0.04 1.42
6.66 0.04 1.21
5.85 0.03 1.06
4.84 0.04 1.42
4.12 0.04 1.21
3.61 0.03 1.06
6.42 7.83 2.71 2.55 8.65 10.07
ns
ns
ns
ns
ns
ns
5.46 6.66 2.31 2.17 7.36
4.79 5.85 2.02 1.90 6.46
4.49 4.84 3.03 3.13 6.72
3.82 4.12 2.58 2.66 5.72
3.35 3.61 2.26 2.34 5.02
8.56
7.52
7.08
6.02
5.28
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-83 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Applicable to Standard Plus I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
0.66
0.56
0.49
tDP
tDIN tPY
tEOUT
0.43
0.36
0.32
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS tZHS Units
2 mA
12.08 0.04 1.42
10.27 0.04 1.21
9.02 0.03 1.06
9.28 0.04 1.42
7.89 0.04 1.21
6.93 0.03 1.06
12.01 12.08 2.72 2.43 14.24 14.31
10.21 10.27 2.31 2.06 12.12 12.18
8.97 9.02 2.03 1.81 10.64 10.69
9.45 8.91 3.04 3.00 11.69 11.15
8.04 7.58 2.58 2.55 9.94 9.49
7.06 6.66 2.27 2.24 8.73 8.33
ns
ns
ns
ns
ns
ns
–2
4 mA
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-84 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
Speed
Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
Units
ns
2 mA
Std.
–1
7.65
6.50
5.71
1.42
1.21
1.06
6.31
5.37
4.71
7.65
6.50
5.71
2.45
2.08
1.83
2.45
2.08
1.83
ns
–2
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-62
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-85 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Speed
Strength
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
Units
ns
2 mA
12.33
10.49
9.21
1.42
1.21
1.06
11.79
10.03
8.81
12.33
10.49
9.21
2.45
2.08
1.83
2.32
1.98
1.73
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
Table 2-86 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
Max.
VIH
Max.
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL IIH
Min.
V
Min.
V
Max,.
V
Max.
mA1
Max.
mA1
Drive Strength
Per PCI specification
Notes:
V
V
V
mA mA
µA2 µA2
Per PCI curves
10 10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-10.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
Figure 2-10 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
described in Table 2-87.
Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
10
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Revision 13
2-63
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-88 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade tDOUT
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.97
4.22
3.71
tZHS
4.19
3.56
3.13
Units
ns
Std.
–1
0.66
0.56
0.49
2.68
2.28
2.00
0.86
0.73
0.65
2.73
2.32
2.04
1.95
1.66
1.46
3.21
2.73
2.40
3.58
3.05
2.68
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-89 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade tDOUT
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.59
3.90
3.42
tZHS
3.94
3.35
2.94
Units
ns
Std.
–1
0.66
0.56
0.49
2.31
1.96
1.72
0.85
0.72
0.64
2.35
2.00
1.76
1.70
1.45
1.27
2.79
2.37
2.08
3.22
2.74
2.41
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
N
P
N
165
165
Z0 = 50
140
Z0 = 50
INBUF_LVDS
+
–
100
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
2-64
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
2.5
Max.
2.625
1.25
1.6
Units
V
VOL
Output Low Voltage
1.075
1.425
0.91
0.91
V
VOH
Output High Voltage
1.25
0.65
0.65
0
V
IOL 1
Output Lower Current
Output High Current
1.16
1.16
2.925
10
mA
mA
V
IOH 1
VI
Input Voltage
IIH 2,3
IIL 2,4
Input High Leakage Current
Input Low Leakage Current
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
µA
µA
mV
V
10
VODIFF
VOCM
VICM
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
V
VIDIFF
Notes:
mV
1. IOL/ IOH defined by VODIFF/(Resistor Network)
2. Currents are measured at 85°C junction temperature.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is
larger when operating outside recommended ranges.
4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL.
Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.075
1.325
Cross point
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Timing Characteristics
Table 2-92 • LVDS
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
Units
ns
Std.
–1
1.83
1.56
1.37
1.60
1.36
1.20
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-65
ProASIC3 DC and Switching Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in
the LVDS section in Table 2-92.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and
RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
N
OUTBUF_LVPECL
100
100
Z0 = 50
187 W
INBUF_LVPECL
+
–
100
Z0 = 50
N
Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
2-66
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-93 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max.
Units
V
3.0
3.3
3.6
VOL
Output Low Voltage
0.96
1.8
1.27
2.11
3.6
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.6
V
VOH
Output High Voltage
V
VIL, VIH
VODIFF
VOCM
VICM
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
0
V
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
V
V
V
VIDIFF
mV
Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.64
1.94
Cross point
Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.
Timing Characteristics
Table 2-95 • LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
Units
ns
Std.
–1
1.80
1.53
1.34
1.40
1.19
1.05
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-67
ProASIC3 DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
DFN1E1P1
DFN1E1P1
G
E
E
EOUT
B
A
H
I
PRE
J
D
Q
DFN1E1P1
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
INBUF
INBUF
CLKBUF
Postive-Edge Triggered
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2-68
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-96 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
tOHD
F, H
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
G, H
tOHE
G, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
J, H
tOESUE
tOEHE
K, H
K, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, EOUT
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
I, H
I, H
A, E
C, A
C, A
B, A
B, A
D, E
D, A
D, A
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Note: *See Figure 2-14 on page 2-68 for more information.
Revision 13
2-69
ProASIC3 DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
AA
DD
CLR
LL
HH
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2-70
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-97 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
tOHD
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-15 on page 2-70 for more information.
Revision 13
2-71
ProASIC3 DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tIHD
tISUD
50%
50%
1
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-16 • Input Register Timing Diagram
Timing Characteristics
Table 2-98 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
–2 –1 Std. Units
0.24 0.27 0.32 ns
0.26 0.30 0.35 ns
0.00 0.00 0.00 ns
0.37 0.42 0.50 ns
0.00 0.00 0.00 ns
0.45 0.52 0.61 ns
0.45 0.52 0.61 ns
0.00 0.00 0.00 ns
0.22 0.25 0.30 ns
0.00 0.00 0.00 ns
0.22 0.25 0.30 ns
0.22 0.25 0.30 ns
0.22 0.25 0.30 ns
0.36 0.41 0.48 ns
0.32 0.37 0.43 ns
Clock-to-Q of the Input Data Register
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
tIWPRE
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
tICKMPWH Clock Minimum Pulse Width High for the Input Data Register
tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-72
Revision 13
ProASIC3 Flash Family FPGAs
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
tOREMPRE
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOHE
50%
50%
tOSUE
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-17 • Output Register Timing Diagram
Timing Characteristics
Table 2-99 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–2
–1 Std. Units
Clock-to-Q of the Output Data Register
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.59
0.00 0.00 0.00
0.80 0.91 1.07
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
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ProASIC3 DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD OEHD
t
50% 50%
1
0
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
50%
tOERECPRE
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
EOUT
Figure 2-18 • Output Enable Register Timing Diagram
2-74
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-100 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
–2
–1 Std. Units
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.58
0.00 0.00 0.00
0.67 0.76 0.89
0.67 0.76 0.89
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
0.36 0.41 0.48
0.32 0.37 0.43
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-75
ProASIC3 DC and Switching Characteristics
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
Data
A
D
Out_QF
(to core)
FF1
B
C
E
Out_QR
(to core)
CLK
CLKBUF
FF2
CLR
INBUF
DDR_IN
Figure 2-19 • Input DDR Timing Model
Table 2-101 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
2-76
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ProASIC3 Flash Family FPGAs
CLK
tDDRISUD
6
tDDRIHD
Data
CLR
1
2
3
4
5
7
8
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
7
2
4
tDDRICLKQ2
tDDRICLR2Q2
3
5
Figure 2-20 • Input DDR Timing Diagram
Timing Characteristics
Table 2-102 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
–2
–1
Std. Units
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (Fall)
0.27
0.39
0.25
0.25
0.00
0.00
0.46
0.57
0.00
0.22
0.22
0.36
0.32
350
0.31
0.44
0.28
0.28
0.00
0.00
0.53
0.65
0.00
0.25
0.25
0.41
0.37
309
0.37
0.52
0.33
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.30
0.48
0.43
263
ns
ns
ns
Data Setup for Input DDR (Rise)
ns
tDDRIHD
Data Hold for Input DDR (Fall)
ns
Data Hold for Input DDR (Rise)
ns
tDDRICLR2Q1
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
ns
ns
tDDRIREMCLR Asynchronous Clear Removal time for Input DDR
tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR
ns
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
ns
ns
FDDRIMAX
Maximum Frequency for Input DDR
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-77
ProASIC3 DC and Switching Characteristics
Output DDR Module
Output DDR
A
B
Data_F
(from core)
X
X
FF1
Out
0
1
CLK
E
X
CLKBUF
C
X
OUTBUF
D
Data_R
(from core)
X
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-21 • Output DDR Timing Model
Table 2-103 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Measuring Nodes (from, to)
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
2-78
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ProASIC3 Flash Family FPGAs
CLK
t
t
DDROHD2
DDROSUD2
4
9
5
Data_F
1
2
3
t
t
DDROHD1
DDROREMCLR
Data_R 6
CLR
7
8
10
11
t
DDRORECCLR
t
DDROREMCLR
t
t
DDROCLKQ
DDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-22 • Output DDR Timing Diagram
Timing Characteristics
Table 2-104 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
–2
–1
Std. Units
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
0.70 0.80 0.94
0.38 0.43 0.51
0.38 0.43 0.51
0.00 0.00 0.00
0.00 0.00 0.00
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDDROHD2
Data_R Data Hold for Output DDR
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
350 309 263 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-79
ProASIC3 DC and Switching Characteristics
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e,
and ProASIC3/E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-23 • Sample of Combinatorial Cells
2-80
Revision 13
ProASIC3 Flash Family FPGAs
tPD
A
B
NAND2 or
Any Combinatorial
Logic
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)
)
where edges are applicable for the particular
combinatorial cell
VCC
50%
50%
A, B, C
GND
50%
VCC
50%
OUT
OUT
GND
VCC
tPD
tPD
(RR)
(FF)
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-24 • Timing Model and Waveforms
Revision 13
2-81
ProASIC3 DC and Switching Characteristics
Timing Characteristics
Table 2-105 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
–2
–1
Std.
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Units
ns
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A, B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-25 • Sample of Sequential Cells
2-82
Revision 13
ProASIC3 Flash Family FPGAs
tCKMPWH CKMPWL
t
50%
tSUD
50%
50%
50%
50%
50%
50%
CLK
tHD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
tREMPRE
tHE
50%
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-26 • Timing Model and Waveforms
Timing Characteristics
Table 2-106 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–2
–1 Std. Units
Clock-to-Q of the Core Register
0.55 0.63 0.74
0.43 0.49 0.57
0.00 0.00 0.00
0.45 0.52 0.61
0.00 0.00 0.00
0.40 0.45 0.53
0.40 0.45 0.53
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.32 0.37 0.43
0.36 0.41 0.48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-83
ProASIC3 DC and Switching Characteristics
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It
is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-89. Table 2-108 to Table 2-114 on page 2-88
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
2-84
Revision 13
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-107 • A3P015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
–1
Std.
Parameter Description
tRCKL Input Low Delay for Global Clock
tRCKH Input High Delay for Global Clock
0.66 0.81 0.75 0.92 0.88 1.08
0.67 0.84 0.76 0.96 0.89 1.13
ns
ns
ns
ns
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.18
0.21
0.25
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-108 • A3P030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.67 0.81 0.76 0.92 0.89 1.09
0.68 0.85 0.77 0.97 0.91 1.14
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.18
0.21
0.24
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-85
ProASIC3 DC and Switching Characteristics
Table 2-109 • A3P060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
0.71 0.93 0.81 1.05 0.95 1.24
0.70 0.96 0.80 1.09 0.94 1.28
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-110 • A3P125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.77 0.99 0.87 1.12 1.03 1.32
0.76 1.02 0.87 1.16 1.02 1.37
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-86
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-111 • A3P250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.80 1.01 0.91 1.15 1.07 1.36
0.78 1.04 0.89 1.18 1.04 1.39
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-112 • A3P400 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.87 1.09 0.99 1.24 1.17 1.46
0.86 1.11 0.98 1.27 1.15 1.49
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-87
ProASIC3 DC and Switching Characteristics
Table 2-113 • A3P600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.87 1.09 0.99 1.24 1.17 1.46
0.86 1.11 0.98 1.27 1.15 1.49
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-114 • A3P1000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.94 1.16 1.07 1.32 1.26 1.55
0.93 1.19 1.06 1.35 1.24 1.59
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.35
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-88
Revision 13
ProASIC3 Flash Family FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-115 • ProASIC3 CCC/PLL Specification
Parameter
Minimum
1.5
Typical
Maximum
350
Units
MHz
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Serial Clock (SCLK) for Dynamic PLL1
0.75
350
125
Delay Increments in Programmable Delay Blocks2, 3
2004
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
0.50%
1.00%
1.75%
2.50%
0.70%
1.20%
2.00%
5.60%
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
300
300
300
6.0
µs
µs
µs
ms
(all other dies)
Tracking Jitter 5
(A3P250 and A3P1000 only)
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1.6
ns
ns
ns
ns
%
1.6
(all other dies)
1.6
0.8
Output Duty Cycle
48.5
0.6
51.5
Delay Range in Block: Programmable Delay 12, 3
Delay Range in Block: Programmable Delay 22, 3
Delay Range in Block: Fixed Delay2, 3
Notes:
5.56
ns
ns
ns
0.225
5.56
2.2
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.
3. T = 25°C, VCC = 1.5 V
J
4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help for more information.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. The A3P030 device does not contain a PLL.
Revision 13
2-89
ProASIC3 DC and Switching Characteristics
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-28 • Peak-to-Peak Jitter Definition
2-90
Revision 13
ProASIC3 Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-29 • RAM Models
Revision 13
2-91
ProASIC3 DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS
tBKS
tENS
t
AH
A
A
A
2
0
1
tBKH
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-30 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
t
tAH
AS
A
A
A
2
0
1
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-31 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
2-92
Revision 13
ProASIC3 Flash Family FPGAs
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS
tAH
A0
tBKS
A1
A2
tBKH
tENS
tENH
WEN
tDS
tDH
DI1
DI0
DIN|RD
Dn
D2
DOUT|RD
Figure 2-32 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
ADDR
BLK
tAS tAH
A0
tBKS
A1
A2
tBKH
tENS
WEN
DIN
tDS tDH
DI1
DI0
DI2
DOUT
Dn
DI0
DI1
(pass-through)
DOUT
DI0
Dn
DI1
(pipelined)
Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.
Revision 13
2-93
ProASIC3 DC and Switching Characteristics
t
CYC
t
t
CKL
CKH
CLK
RESET
t
RSTBQ
D
D
DOUT|RD
m
n
Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
Timing Characteristics
Table 2-116 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Address setup time
–2
–1 Std. Units
0.25 0.28 0.33
0.00 0.00 0.00
0.14 0.16 0.19
0.10 0.11 0.13
0.23 0.27 0.31
0.02 0.02 0.02
0.18 0.21 0.25
0.00 0.00 0.00
2.36 2.68 3.15
1.79 2.03 2.39
0.89 1.02 1.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25
address—Applicable to Closing Edge
1
tC2CWWH
Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23
address—Applicable to Rising Edge
ns
ns
ns
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34
address—Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37
address— Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to Data Out Low on DOUT (pipelined)
RESET removal
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
ns
ns
ns
tREMRSTB
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-94
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-116 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V (continued)
Parameter
tRECRSTB
tMPWRSTB
tCYC
Description –2
–1 Std. Units
RESET recovery
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
RESET minimum pulse width
Clock cycle time
FMAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-95
ProASIC3 DC and Switching Characteristics
Table 2-117 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1 Std. Units
Address setup time
0.25 0.28 0.33
0.00 0.00 0.00
0.13 0.15 0.17
0.10 0.11 0.13
0.18 0.21 0.25
0.00 0.00 0.00
2.16 2.46 2.89
0.90 1.02 1.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38
address—Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44
address—Applicable to Opening Edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
RESET Low to data out Low on RD (pipelined)
RESET removal
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET recovery
RESET minimum pulse width
Clock cycle time
FMAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-96
Revision 13
ProASIC3 Flash Family FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-35 • FIFO Model
Revision 13
2-97
ProASIC3 DC and Switching Characteristics
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKS
tBKH
RBLK
tCKQ1
RD
D1
Dn
D0
D2
(flow-through)
tCKQ2
RD
(pipelined)
Dn
D0
D1
Figure 2-36 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
tBKS
tBKH
WBLK
tDS
tDH
DI1
DI0
WD
Figure 2-37 • FIFO Write
2-98
Revision 13
ProASIC3 Flash Family FPGAs
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET
EMPTY
AEMPTY
FULL
tRSTFG
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
MATCH (A0)
(Address Counter)
Figure 2-38 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Revision 13
2-99
ProASIC3 DC and Switching Characteristics
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion
2-100
Revision 13
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-118 • FIFO (for all dies except A3P250)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std. Units
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
1.34 1.52 1.79
0.00 0.00 0.00
0.19 0.22 0.26
0.00 0.00 0.00
0.18 0.21 0.25
0.00 0.00 0.00
2.17 2.47 2.90
0.94 1.07 1.26
1.72 1.96 2.30
1.63 1.86 2.18
6.19 7.05 8.29
1.69 1.93 2.27
6.13 6.98 8.20
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tENH
tBKS
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
Input Data (WD) Hold Time
tDH
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
310
272
231
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2-101
ProASIC3 DC and Switching Characteristics
Table 2-119 • FIFO (for A3P250 only, aspect-ratio-dependent)
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std. Units
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
3.26 3.71 4.36
0.00 0.00 0.00
0.19 0.22 0.26
0.00 0.00 0.00
0.18 0.21 0.25
0.00 0.00 0.00
2.17 2.47 2.90
0.94 1.07 1.26
1.72 1.96 2.30
1.63 1.86 2.18
6.19 7.05 8.29
1.69 1.93 2.27
6.13 6.98 8.20
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tENH
tBKS
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
Input Data (WD) Hold Time
tDH
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
310
272
231
2-102
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-120 • A3P250 FIFO 512×8
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std. Units
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
3.75 4.27 5.02
0.00 0.00 0.00
0.19 0.22 0.26
0.00 0.00 0.00
0.18 0.21 0.25
0.00 0.00 0.00
2.17 2.47 2.90
0.94 1.07 1.26
1.72 1.96 2.30
1.63 1.86 2.18
6.19 7.05 8.29
1.69 1.93 2.27
6.13 6.98 8.20
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tENH
tBKS
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
Input Data (WD) Hold Time
tDH
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency for FIFO
310
272
231
Revision 13
2-103
ProASIC3 DC and Switching Characteristics
Table 2-121 • A3P250 FIFO 1k×4
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
5.42
0.00
0.26
0.00
0.25
0.00
3.15
1.20
2.30
2.18
8.29
2.27
8.20
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
4.05
0.00
0.19
0.00
0.18
0.00
2.36
0.89
1.72
1.63
6.19
1.69
6.13
0.92
0.92
0.29
1.50
0.21
3.23
310
4.61
0.00
0.22
0.00
0.21
0.00
2.68
1.02
1.96
1.86
7.05
1.93
6.98
1.05
1.05
0.33
1.71
0.24
3.68
272
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
ns
ns
ns
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
2-104
Revision 13
ProASIC3 Flash Family FPGAs
Table 2-122 • A3P250 FIFO 2k×2
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
5.88
0.00
0.26
0.00
0.25
0.00
3.15
1.20
2.30
2.18
8.29
2.27
8.20
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
4.39
0.00
0.19
0.00
0.18
0.00
2.36
0.89
1.72
1.63
6.19
1.69
6.13
0.92
0.92
0.29
1.50
0.21
3.23
310
5.00
0.00
0.22
0.00
0.21
0.00
2.68
1.02
1.96
1.86
7.05
1.93
6.98
1.05
1.05
0.33
1.71
0.24
3.68
272
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
ns
ns
ns
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (flow-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Revision 13
2-105
ProASIC3 DC and Switching Characteristics
Table 2-123 • A3P250 FIFO 4k×1
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
6.50
0.00
0.26
0.00
0.25
0.00
3.15
1.20
2.30
2.18
8.29
2.27
8.20
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
REN, WEN Setup Time
REN, WEN Hold Time
BLK Setup Time
4.86
0.00
0.19
0.00
0.18
0.00
2.36
0.89
1.72
1.63
6.19
1.69
6.13
0.92
0.92
0.29
1.50
0.21
3.23
310
5.53
0.00
0.22
0.00
0.21
0.00
2.68
1.02
1.96
1.86
7.05
1.93
6.98
1.05
1.05
0.33
1.71
0.24
3.68
272
tENH
ns
tBKS
ns
tBKH
BLK Hold Time
ns
tDS
Input Data (WD) Setup Time
ns
tDH
Input Data (WD) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (flow-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
ns
ns
ns
ns
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on DO (pass-through)
RESET Low to Data Out Low on DO (pipelined)
RESET Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET Recovery
ns
RESET Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency
MHz
2-106
Revision 13
ProASIC3 Flash Family FPGAs
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
tCKQ2
D1
D0
Data
Figure 2-43 • Timing Diagram
Timing Characteristics
Table 2-124 • Embedded FlashROM Access Time
Parameter
tSU
Description
Address Setup Time
–2
0.53
0.00
21.42
15
–1
Std.
0.71
0.00
28.68
15
Units
ns
0.61
0.00
24.40
15
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
Revision 13
2-107
ProASIC3 DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-14 for more details.
Timing Characteristics
Table 2-125 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
–2
–1
Std.
0.67
1.33
0.67
1.33
8.00
26.67
19.00
0.00
0.27
TBD
Units
ns
0.50
1.00
0.50
1.00
6.00
20.00
25.00
0.00
0.20
TBD
0.57
1.13
0.57
1.13
6.80
22.67
22.00
0.00
0.23
TBD
tDIHD
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
ResetB Recovery Time
ResetB Minimum Pulse
ns
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for
derating values.
2-108
Revision 13
3 – Pin Descriptions
Supply Pins
GND
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Ground
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or
3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV
and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs
to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.
Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise
from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for a complete
board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on ProASIC3 devices.
VCOMPLA/B/C/D/E/F PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on ProASIC3 devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
Revision 13
3-1
Pin Descriptions
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO
and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide. All inputs labeled GC/GF
are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2
are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into
the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global
network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the
naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on
ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The
FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum
rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a
regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a
Schmitt trigger input.
When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
3-2
Revision 13
ProASIC3 Flash Family FPGAs
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 1
for more information.
Table 1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The
values in Table 1 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
Revision 13
3-3
Pin Descriptions
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Related Documents
User’s Guides
ProASIC FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/PA3_UG.pdf
Packaging
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials are at http://www.microsemi.com/products/solutions/package/docs.aspx.
3-4
Revision 13
4 – Package Pin Assignments
QN48
Pin 1
48
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-1
Package Pin Assignments
QN48
QN48
A3P030 Function
Pin Number
A3P030 Function
Pin Number
1
IO82RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
GND
37
38
39
40
41
42
43
44
45
46
47
48
IO24RSB0
IO22RSB0
IO20RSB0
IO18RSB0
IO16RSB0
IO14RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
2
3
4
5
6
VCCIB1
7
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO62RSB1
IO61RSB1
IO60RSB1
IO57RSB1
IO55RSB1
IO53RSB1
VCC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
IO46RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
TRST
VJTAG
IO38RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
GND
VCC
IO25RSB0
4-2
Revision 13
ProASIC3 Flash Family FPGAs
QN68
Pin A1 Mark
68
1
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-3
Package Pin Assignments
QN68
QN68
A3P015 Function
Pin Number
A3P015 Function
Pin Number
37
1
IO82RSB1
IO80RSB1
IO78RSB1
IO76RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
VCC
TRST
VJTAG
2
38
3
39
IO40RSB0
IO37RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
4
40
5
41
6
42
7
43
8
44
9
GND
45
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
46
VCC
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO60RSB1
IO58RSB1
IO56RSB1
IO54RSB1
IO52RSB1
IO51RSB1
VCC
47
IO31RSB0
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO24RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO15RSB0
IO14RSB0
VCCIB0
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
GND
61
VCC
VCCIB1
62
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
IO50RSB1
IO48RSB1
IO46RSB1
IO44RSB1
IO42RSB1
TCK
63
64
65
66
67
68
TDI
TMS
VPUMP
TDO
4-4
Revision 13
ProASIC3 Flash Family FPGAs
QN68
QN68
Pin Number A3P030 Function
Pin Number A3P030 Function
1
IO82RSB1
IO80RSB1
IO78RSB1
IO76RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
VCC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TRST
VJTAG
2
3
IO40RSB0
IO37RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
4
5
6
7
8
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCIB1
VCC
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO60RSB1
IO58RSB1
IO56RSB1
IO54RSB1
IO52RSB1
IO51RSB1
VCC
IO31RSB0
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO24RSB0
IO22RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO15RSB0
IO14RSB0
VCCIB0
GND
GND
VCC
VCCIB1
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
IO04RSB0
IO02RSB0
IO00RSB0
IO50RSB1
IO48RSB1
IO46RSB1
IO44RSB1
IO42RSB1
TCK
TDI
TMS
VPUMP
TDO
Revision 13
4-5
Package Pin Assignments
QN132
A37
A48
B44
C40
B34
C31
Pin A1Mark
D4
D1
A36
B33
C30
A1
B1
C1
C21
B23
A25
C10
B11
A12
D3
D2
Optional
Corner Pad (4x)
C20
B22
C11
B12
A13
A24
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-6
Revision 13
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number A3P030 Function
Pin Number A3P030 Function
Pin Number A3P030 Function
A1
A2
IO01RSB1
IO81RSB1
NC
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
IO26RSB0
IO23RSB0
NC
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
NC
A3
IO41RSB0
GND
A4
IO80RSB1
GEC0/IO77RSB1
NC
IO22RSB0
IO20RSB0
IO18RSB0
VCC
A5
GDA0/IO37RSB0
NC
A6
A7
GEB0/IO75RSB1
IO73RSB1
NC
GND
A8
IO15RSB0
IO12RSB0
IO10RSB0
IO09RSB0
IO06RSB0
IO02RSB1
IO82RSB1
GND
IO33RSB0
IO30RSB0
IO27RSB0
IO24RSB0
GND
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
VCC
IO71RSB1
IO68RSB1
IO63RSB1
IO60RSB1
NC
IO21RSB0
IO19RSB0
GND
B2
B3
IO59RSB1
IO57RSB1
VCC
B4
IO79RSB1
NC
IO16RSB0
IO13RSB0
GND
B5
B6
GND
IO54RSB1
IO52RSB1
IO49RSB1
IO48RSB1
IO47RSB1
TDI
B7
IO74RSB1
NC
IO08RSB0
IO05RSB0
IO03RSB1
IO00RSB1
NC
B8
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
IO70RSB1
IO67RSB1
IO64RSB1
IO61RSB1
GND
C2
C3
C4
IO78RSB1
GEA0/IO76RSB1
NC
TRST
C5
IO44RSB0
NC
C6
IO58RSB1
IO56RSB1
GND
C7
NC
IO43RSB0
IO42RSB0
IO40RSB0
IO39RSB0
GDC0/IO36RSB0
NC
C8
VCCIB1
IO69RSB1
IO66RSB1
IO65RSB1
IO62RSB1
NC
C9
IO53RSB1
IO50RSB1
GND
C10
C11
C12
C13
C14
C15
C16
IO46RSB1
TMS
VCC
NC
IO34RSB0
IO31RSB0
TDO
IO55RSB1
VCCIB1
IO45RSB0
Revision 13
4-7
Package Pin Assignments
QN132
Pin Number A3P030 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO51RSB1
NC
TCK
NC
VPUMP
VJTAG
NC
NC
NC
GDB0/IO38RSB0
NC
VCCIB0
IO32RSB0
IO29RSB0
IO28RSB0
IO25RSB0
NC
NC
VCCIB0
IO17RSB0
IO14RSB0
IO11RSB0
IO07RSB0
IO04RSB0
GND
D2
GND
D3
GND
D4
GND
4-8
Revision 13
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number A3P060 Function
Pin Number A3P060 Function
Pin Number A3P060 Function
A1
A2
GAB2/IO00RSB1
IO93RSB1
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
GBB1/IO25RSB0
GBC0/IO22RSB0
VCCIB0
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
NC
A3
VCCIB1
GCB2/IO45RSB0
GND
A4
GFC1/IO89RSB1
GFB0/IO86RSB1
VCCPLF
IO21RSB0
IO18RSB0
IO15RSB0
IO14RSB0
IO11RSB0
GAB1/IO08RSB0
NC
A5
GCB0/IO41RSB0
GCC1/IO38RSB0
GND
A6
A7
GFA1/IO84RSB1
GFC2/IO81RSB1
IO78RSB1
A8
GBB2/IO30RSB0
VMV0
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
VCC
GBA0/IO26RSB0
GBC1/IO23RSB0
GND
GEB1/IO75RSB1
GEA0/IO72RSB1
GEC2/IO69RSB1
IO65RSB1
GAB0/IO07RSB0
IO04RSB0
IO01RSB1
GAC2/IO94RSB1
GND
IO20RSB0
IO17RSB0
GND
B2
VCC
B3
IO64RSB1
B4
GFC0/IO88RSB1
VCOMPLF
GND
IO12RSB0
GAC0/IO09RSB0
GND
IO63RSB1
B5
IO62RSB1
B6
IO61RSB1
B7
GFB2/IO82RSB1
IO79RSB1
GND
GAA1/IO06RSB0
GNDQ
IO58RSB1
B8
GDB2/IO55RSB1
NC
B9
GAA2/IO02RSB1
IO95RSB1
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO74RSB1
VMV1
C2
GDA2/IO54RSB1
TDI
C3
GEB2/IO70RSB1
IO67RSB1
GND
C4
GFB1/IO87RSB1
GFA0/IO85RSB1
GFA2/IO83RSB1
IO80RSB1
VCCIB1
TRST
C5
GDC1/IO48RSB0
VCC
C6
NC
C7
IO47RSB0
NC
C8
GCC2/IO46RSB0
GCA2/IO44RSB0
GCA0/IO43RSB0
GCB1/IO40RSB0
IO36RSB0
GND
C9
GEA1/IO73RSB1
GNDQ
IO59RSB1
GDC2/IO56RSB1
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO71RSB1
IO68RSB1
VCCIB1
GNDQ
VCC
TMS
NC
IO31RSB0
TDO
NC
GBA2/IO28RSB0
GDC0/IO49RSB0
IO60RSB1
Revision 13
4-9
Package Pin Assignments
QN132
Pin Number A3P060 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO57RSB1
NC
TCK
VMV1
VPUMP
VJTAG
VCCIB0
NC
NC
GCA1/IO42RSB0
GCC0/IO39RSB0
VCCIB0
IO29RSB0
GNDQ
GBA1/IO27RSB0
GBB0/IO24RSB0
VCC
IO19RSB0
IO16RSB0
IO13RSB0
GAC1/IO10RSB0
NC
GAA0/IO05RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-10
Revision 13
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number A3P125 Function
Pin Number A3P125 Function
Pin Number A3P125 Function
A1
A2
GAB2/IO69RSB1
IO130RSB1
VCCIB1
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
NC
A3
GCB2/IO58RSB0
GND
A4
GFC1/IO126RSB1
GFB0/IO123RSB1
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO54RSB0
GCC1/IO51RSB0
GND
A6
A7
GFA1/IO121RSB1
GFC2/IO118RSB1
IO115RSB1
VCC
A8
GBB2/IO43RSB0
VMV0
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEB1/IO110RSB1
GEA0/IO107RSB1
GEC2/IO104RSB1
IO100RSB1
VCC
GAC1/IO05RSB0
GAB0/IO02RSB0
IO68RSB1
GAC2/IO131RSB1
GND
IO26RSB0
IO21RSB0
GND
B2
B3
IO99RSB1
B4
GFC0/IO125RSB1
VCOMPLF
GND
IO13RSB0
IO08RSB0
GND
IO96RSB1
B5
IO94RSB1
B6
IO91RSB1
B7
GFB2/IO119RSB1
IO116RSB1
GND
GAC0/IO04RSB0
GNDQ
IO85RSB1
B8
IO79RSB1
B9
GAA2/IO67RSB1
IO132RSB1
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO109RSB1
VMV1
C2
GDB2/IO71RSB1
TDI
C3
GEB2/IO105RSB1
IO101RSB1
GND
C4
GFB1/IO124RSB1
GFA0/IO122RSB1
GFA2/IO120RSB1
IO117RSB1
VCCIB1
TRST
C5
GDC1/IO61RSB0
VCC
C6
IO98RSB1
IO95RSB1
GND
C7
IO60RSB0
C8
GCC2/IO59RSB0
GCA2/IO57RSB0
GCA0/IO56RSB0
GCB1/IO53RSB0
IO49RSB0
C9
GEA1/IO108RSB1
GNDQ
IO87RSB1
IO81RSB1
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO106RSB1
IO103RSB1
VCCIB1
GNDQ
VCC
TMS
IO97RSB1
IO93RSB1
IO89RSB1
IO44RSB0
TDO
GBA2/IO41RSB0
GDC0/IO62RSB0
Revision 13
4-11
Package Pin Assignments
QN132
Pin Number A3P125 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO83RSB1
VCCIB1
TCK
VMV1
VPUMP
VJTAG
VCCIB0
NC
NC
GCA1/IO55RSB0
GCC0/IO52RSB0
VCCIB0
IO42RSB0
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-12
Revision 13
ProASIC3 Flash Family FPGAs
QN132
QN132
QN132
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
A1
A2
GAB2/IO117UPB3
IO117VPB3
VCCIB3
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
B1
GBB1/IO38RSB0
GBC0/IO35RSB0
VCCIB0
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
C1
GND
IO54PDB1
A3
GCB2/IO52PDB1
GND
A4
GFC1/IO110PDB3
GFB0/IO109NPB3
VCCPLF
IO28RSB0
IO22RSB0
IO18RSB0
IO14RSB0
IO11RSB0
IO07RSB0
VCC
A5
GCB0/IO49NDB1
GCC1/IO48PDB1
GND
A6
A7
GFA1/IO108PPB3
GFC2/IO105PPB3
IO103NDB3
VCC
A8
GBB2/IO42PDB1
VMV1
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
GBA0/IO39RSB0
GBC1/IO36RSB0
GND
GEA1/IO98PPB3
GEA0/IO98NPB3
GEC2/IO95RSB2
IO91RSB2
GAC1/IO05RSB0
GAB0/IO02RSB0
IO118VDB3
GAC2/IO116UDB3
GND
IO26RSB0
B2
IO21RSB0
VCC
B3
GND
IO90RSB2
B4
GFC0/IO110NDB3
VCOMPLF
GND
IO13RSB0
IO87RSB2
B5
IO08RSB0
IO85RSB2
B6
GND
IO82RSB2
B7
GFB2/IO106PSB3
IO103PDB3
GND
GAC0/IO04RSB0
GNDQ
IO76RSB2
B8
IO70RSB2
B9
GAA2/IO118UDB3
IO116VDB3
VCC
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GEB0/IO99NDB3
VMV3
C2
GDB2/IO62RSB2
TDI
C3
GEB2/IO96RSB2
IO92RSB2
GND
C4
GFB1/IO109PPB3
GFA0/IO108NPB3
GFA2/IO107PSB3
IO105NPB3
VCCIB3
TRST
C5
GDC1/IO58UDB1
VCC
C6
IO89RSB2
IO86RSB2
GND
C7
IO54NDB1
C8
IO52NDB1
C9
GEB1/IO99PDB3
GNDQ
GCA2/IO51PPB1
GCA0/IO50NPB1
GCB1/IO49PDB1
IO47NSB1
IO78RSB2
IO72RSB2
GND
C10
C11
C12
C13
C14
C15
C16
GEA2/IO97RSB2
IO94RSB2
GNDQ
VCCIB2
VCC
TMS
IO88RSB2
IO41NPB1
TDO
IO84RSB2
GBA2/IO41PPB1
GDC0/IO58VDB1
IO80RSB2
Revision 13
4-13
Package Pin Assignments
QN132
Pin Number A3P250 Function
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
IO74RSB2
VCCIB2
TCK
VMV2
VPUMP
VJTAG
VCCIB1
IO53NSB1
IO51NPB1
GCA1/IO50PPB1
GCC0/IO48NDB1
VCCIB1
IO42NDB1
GNDQ
GBA1/IO40RSB0
GBB0/IO37RSB0
VCC
IO24RSB0
IO19RSB0
IO16RSB0
IO10RSB0
VCCIB0
GAB1/IO03RSB0
VMV0
GND
D2
GND
D3
GND
D4
GND
4-14
Revision 13
ProASIC3 Flash Family FPGAs
CS121
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
Notes:
1. This is the bottom view of the package.
2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-15
Package Pin Assignments
CS121
CS121
A3P060 Function
CS121
A3P060 Function
Pin Number
A1
A3P060 Function
Pin Number
D4
Pin Number
G7
G8
G9
G10
G11
H1
GNDQ
IO10RSB0
IO11RSB0
VCC
A2
IO01RSB0
D5
GDC0/IO46RSB0
GDA1/IO49RSB0
GDB0/IO48RSB0
GCA0/IO40RSB0
IO75RSB1
A3
GAA1/IO03RSB0
GAC1/IO07RSB0
IO15RSB0
D6
IO18RSB0
A4
D7
IO32RSB0
A5
D8
IO31RSB0
A6
IO13RSB0
D9
GCA2/IO41RSB0
IO30RSB0
A7
IO17RSB0
D10
D11
E1
H2
IO76RSB1
A8
GBB1/IO22RSB0
GBA1/IO24RSB0
GNDQ
IO33RSB0
H3
GFC2/IO78RSB1
GFA2/IO80RSB1
IO77RSB1
A9
IO87RSB1
H4
A10
A11
B1
E2
GFC0/IO85RSB1
IO92RSB1
H5
VMV0
E3
H6
GEC2/IO66RSB1
IO54RSB1
GAA2/IO95RSB1
IO00RSB0
E4
IO94RSB1
H7
B2
E5
VCC
H8
GDC2/IO53RSB1
VJTAG
B3
GAA0/IO02RSB0
GAC0/IO06RSB0
IO08RSB0
E6
VCCIB0
H9
B4
E7
GND
H10
H11
J1
TRST
B5
E8
GCC0/IO36RSB0
IO34RSB0
IO44RSB0
B6
IO12RSB0
E9
GEC1/IO74RSB1
GEC0/IO73RSB1
GEB1/IO72RSB1
GEA0/IO69RSB1
GEB2/IO67RSB1
IO62RSB1
B7
IO16RSB0
E10
E11
F1
GCB1/IO37RSB0
GCC1/IO35RSB0
VCOMPLF
J2
B8
GBC1/IO20RSB0
GBB0/IO21RSB0
GBB2/IO27RSB0
GBA2/IO25RSB0
IO89RSB1
J3
B9
J4
B10
B11
C1
F2
GFB0/IO83RSB1
GFA0/IO82RSB1
GFC1/IO86RSB1
VCCIB1
J5
F3
J6
F4
J7
GDA2/IO51RSB1
GDB2/IO52RSB1
TDI
C2
GAC2/IO91RSB1
GAB1/IO05RSB0
GAB0/IO04RSB0
IO09RSB0
F5
J8
C3
F6
VCC
J9
C4
F7
VCCIB0
J10
J11
K1
TDO
C5
F8
GCB2/IO42RSB0
GCC2/IO43RSB0
GCB0/IO38RSB0
GCA1/IO39RSB0
VCCPLF
GDC1/IO45RSB0
GEB0/IO71RSB1
GEA1/IO70RSB1
GEA2/IO68RSB1
IO64RSB1
C6
IO14RSB0
F9
C7
GBA0/IO23RSB0
GBC0/IO19RSB0
IO26RSB0
F10
F11
G1
G2
G3
G4
G5
G6
K2
C8
K3
C9
K4
C10
C11
D1
IO28RSB0
GFB2/IO79RSB1
GFA1/IO81RSB1
GFB1/IO84RSB1
GND
K5
IO60RSB1
GBC2/IO29RSB0
IO88RSB1
K6
IO59RSB1
K7
IO56RSB1
D2
IO90RSB1
K8
TCK
D3
GAB2/IO93RSB1
VCCIB1
K9
TMS
4-16
Revision 13
ProASIC3 Flash Family FPGAs
CS121
A3P060 Function
Pin Number
K10
K11
L1
VPUMP
GDB1/IO47RSB0
VMV1
L2
GNDQ
L3
IO65RSB1
IO63RSB1
IO61RSB1
IO58RSB1
IO57RSB1
IO55RSB1
GNDQ
L4
L5
L6
L7
L8
L9
L10
L11
GDA0/IO50RSB0
VMV1
Revision 13
4-17
Package Pin Assignments
VQ100
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-18
Revision 13
ProASIC3 Flash Family FPGAs
VQ100
A3P030 Function
VQ100
A3P030 Function
VQ100
Pin Number
Pin Number
37
Pin Number
A3P030 Function
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
VCCIB0
1
GND
IO82RSB1
IO81RSB1
IO80RSB1
IO79RSB1
IO78RSB1
IO77RSB1
IO76RSB1
GND
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
38
3
39
VCCIB1
4
40
IO49RSB1
IO47RSB1
IO46RSB1
IO45RSB1
IO44RSB1
IO43RSB1
IO42RSB1
TCK
5
41
6
42
7
43
8
44
9
45
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO75RSB1
IO74RSB1
GEC0/IO73RSB1
GEA0/IO72RSB1
GEB0/IO71RSB1
IO70RSB1
IO69RSB1
VCC
46
47
48
TDI
49
TMS
50
NC
51
GND
52
VPUMP
GND
53
NC
VCC
VCCIB1
54
TDO
IO12RSB0
IO10RSB0
IO08RSB0
IO07RSB0
IO06RSB0
IO05RSB0
IO04RSB0
IO03RSB0
IO02RSB0
IO01RSB0
IO00RSB0
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO64RSB1
IO63RSB1
IO62RSB1
IO61RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
IO56RSB1
IO55RSB1
IO54RSB1
IO53RSB1
IO52RSB1
IO51RSB1
55
TRST
56
VJTAG
57
IO41RSB0
IO40RSB0
IO39RSB0
IO38RSB0
IO37RSB0
IO36RSB0
GDB0/IO34RSB0
GDA0/IO33RSB0
GDC0/IO32RSB0
VCCIB0
58
59
60
61
62
63
64
65
66
67
GND
68
VCC
69
IO31RSB0
IO30RSB0
IO29RSB0
IO28RSB0
70
71
72
Revision 13
4-19
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number A3P060 Function
Pin Number A3P060 Function
Pin Number A3P060 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO25RSB0
VMV0
2
GAA2/IO51RSB1
IO52RSB1
3
VCCIB1
GNDQ
4
GAB2/IO53RSB1
IO95RSB1
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
TCK
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
IO18RSB0
5
6
GAC2/IO94RSB1
IO93RSB1
7
8
IO92RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
IO17RSB0
TDI
IO15RSB0
GFA0/IO85RSB1
VCCPLF
TMS
IO13RSB0
VMV1
IO11RSB0
GFA1/IO84RSB1
GFA2/IO83RSB1
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO10RSB0
GEC1/IO77RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
TRST
IO09RSB0
VJTAG
IO08RSB0
GDA1/IO49RSB0
GDC0/IO46RSB0
GDC1/IO45RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
VCCIB0
GAC1/IO07RSB0
GAC0/IO06RSB0
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
GNDQ
GEA2/IO71RSB1
GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO00RSB0
IO67RSB1
IO66RSB1
GND
IO65RSB1
VCC
IO64RSB1
IO31RSB0
GBC2/IO29RSB0
GBB2/IO27RSB0
IO26RSB0
IO63RSB1
IO62RSB1
IO61RSB1
4-20
Revision 13
ProASIC3 Flash Family FPGAs
VQ100
VQ100
VQ100
Pin Number A3P125 Function
Pin Number A3P125 Function
Pin Number A3P125 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41RSB0
VMV0
2
GAA2/IO67RSB1
IO68RSB1
3
VCCIB1
GNDQ
4
GAB2/IO69RSB1
IO132RSB1
IO87RSB1
IO84RSB1
IO81RSB1
IO75RSB1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
TCK
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO32RSB0
5
6
GAC2/IO131RSB1
IO130RSB1
7
8
IO129RSB1
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
IO28RSB0
TDI
IO25RSB0
GFA0/IO122RSB1
VCCPLF
TMS
IO22RSB0
VMV1
IO19RSB0
GFA1/IO121RSB1
GFA2/IO120RSB1
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB1
TDO
IO15RSB0
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO65RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
VCCIB0
IO09RSB0
IO07RSB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GEA2/IO106RSB1
GEB2/IO105RSB1
GEC2/IO104RSB1
IO102RSB1
IO100RSB1
IO99RSB1
GND
IO97RSB1
VCC
IO96RSB1
IO47RSB0
GBC2/IO45RSB0
GBB2/IO43RSB0
IO42RSB0
IO95RSB1
IO94RSB1
IO93RSB1
Revision 13
4-21
Package Pin Assignments
VQ100
VQ100
VQ100
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GBA2/IO41PDB1
VMV1
2
GAA2/IO118UDB3
IO118VDB3
3
VCCIB2
GNDQ
4
GAB2/IO117UDB3
IO117VDB3
IO77RSB2
IO74RSB2
IO71RSB2
GDC2/IO63RSB2
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO29RSB0
5
6
GAC2/IO116UDB3
IO116VDB3
7
8
IO112PSB3
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
TCK
IO27RSB0
TDI
IO25RSB0
GFA0/IO108NPB3
VCCPLF
TMS
IO23RSB0
VMV2
IO21RSB0
GFA1/IO108PPB3
GFA2/IO107PSB3
VCC
GND
VCCIB0
VPUMP
GND
NC
VCC
VCCIB3
TDO
IO15RSB0
GFC2/IO105PSB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
TRST
IO13RSB0
VJTAG
IO11RSB0
GDA1/IO60USB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO52NDB1
GCB2/IO52PDB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
VCCIB1
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GNDQ
GEA2/IO97RSB2
GEB2/IO96RSB2
GEC2/IO95RSB2
IO93RSB2
VMV0
IO92RSB2
IO91RSB2
GND
IO90RSB2
VCC
IO88RSB2
IO43NDB1
GBC2/IO43PDB1
GBB2/IO42PSB1
IO41NDB1
IO86RSB2
IO85RSB2
IO84RSB2
4-22
Revision 13
ProASIC3 Flash Family FPGAs
TQ144
144
1
144-Pin
TQFP
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-23
Package Pin Assignments
TQ144
TQ144
TQ144
Pin Number A3P060 Function
Pin Number A3P060 Function
Pin Number A3P060 Function
1
GAA2/IO51RSB1
IO52RSB1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
GEA2/IO71RSB1
GEB2/IO70RSB1
GEC2/IO69RSB1
IO68RSB1
IO67RSB1
IO66RSB1
IO65RSB1
VCC
73
74
VPUMP
NC
2
3
GAB2/IO53RSB1
IO95RSB1
75
TDO
4
76
TRST
5
GAC2/IO94RSB1
IO93RSB1
77
VJTAG
6
78
GDA0/IO50RSB0
GDB0/IO48RSB0
GDB1/IO47RSB0
VCCIB0
7
IO92RSB1
79
8
IO91RSB1
80
9
VCC
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
GND
82
GND
VCCIB1
VCCIB1
NC
83
IO44RSB0
GCC2/IO43RSB0
GCB2/IO42RSB0
GCA2/IO41RSB0
GCA0/IO40RSB0
GCA1/IO39RSB0
GCB0/IO38RSB0
GCB1/IO37RSB0
GCC0/IO36RSB0
GCC1/IO35RSB0
IO34RSB0
IO33RSB0
NC
IO90RSB1
84
GFC1/IO89RSB1
GFC0/IO88RSB1
GFB1/IO87RSB1
GFB0/IO86RSB1
VCOMPLF
IO64RSB1
NC
85
86
IO63RSB1
NC
87
88
IO62RSB1
NC
89
GFA0/IO85RSB1
VCCPLF
90
IO61RSB1
NC
91
GFA1/IO84RSB1
GFA2/IO83RSB1
GFB2/IO82RSB1
GFC2/IO81RSB1
IO80RSB1
92
NC
93
IO60RSB1
IO59RSB1
IO58RSB1
IO57RSB1
NC
94
95
96
NC
IO79RSB1
97
NC
IO78RSB1
98
VCCIB0
GND
GND
99
GND
VCCIB1
NC
100
101
102
103
104
105
106
107
108
VCC
GEC1/IO77RSB1
GEC0/IO76RSB1
GEB1/IO75RSB1
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
VMV1
GDC2/IO56RSB1
GDB2/IO55RSB1
GDA2/IO54RSB1
GNDQ
IO30RSB0
GBC2/IO29RSB0
IO28RSB0
GBB2/IO27RSB0
IO26RSB0
GBA2/IO25RSB0
VMV0
TCK
TDI
TMS
GNDQ
VMV1
GNDQ
4-24
Revision 13
ProASIC3 Flash Family FPGAs
TQ144
Pin Number A3P060 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NC
NC
GBA1/IO24RSB0
GBA0/IO23RSB0
GBB1/IO22RSB0
GBB0/IO21RSB0
GBC1/IO20RSB0
GBC0/IO19RSB0
VCCIB0
GND
VCC
IO18RSB0
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
NC
IO10RSB0
IO09RSB0
IO08RSB0
GAC1/IO07RSB0
GAC0/IO06RSB0
NC
GND
NC
GAB1/IO05RSB0
GAB0/IO04RSB0
GAA1/IO03RSB0
GAA0/IO02RSB0
IO01RSB0
IO00RSB0
GNDQ
VMV0
Revision 13
4-25
Package Pin Assignments
TQ144
TQ144
TQ144
Pin Number A3P125 Function
Pin Number A3P125 Function
Pin Number A3P125 Function
1
GAA2/IO67RSB1
IO68RSB1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
GEA2/IO106RSB1
GEB2/IO105RSB1
GEC2/IO104RSB1
IO103RSB1
IO102RSB1
IO101RSB1
IO100RSB1
VCC
73
74
VPUMP
NC
2
3
GAB2/IO69RSB1
IO132RSB1
75
TDO
4
76
TRST
5
GAC2/IO131RSB1
IO130RSB1
77
VJTAG
6
78
GDA0/IO66RSB0
GDB0/IO64RSB0
GDB1/IO63RSB0
VCCIB0
7
IO129RSB1
79
8
IO128RSB1
80
9
VCC
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
GND
82
GND
VCCIB1
VCCIB1
83
IO60RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GCA2/IO57RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCB0/IO54RSB0
GCB1/IO53RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
IO50RSB0
IO49RSB0
NC
IO127RSB1
IO99RSB1
IO97RSB1
IO95RSB1
IO93RSB1
IO92RSB1
IO90RSB1
IO88RSB1
IO86RSB1
IO84RSB1
IO83RSB1
IO82RSB1
IO81RSB1
IO80RSB1
IO79RSB1
VCC
84
GFC1/IO126RSB1
GFC0/IO125RSB1
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
85
86
87
88
89
GFA0/IO122RSB1
VCCPLF
90
91
GFA1/IO121RSB1
GFA2/IO120RSB1
GFB2/IO119RSB1
GFC2/IO118RSB1
IO117RSB1
92
93
94
95
96
NC
IO116RSB1
97
NC
IO115RSB1
98
VCCIB0
GND
GND
99
GND
VCCIB1
VCCIB1
100
101
102
103
104
105
106
107
108
VCC
GEC1/IO112RSB1
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
GDC2/IO72RSB1
GDB2/IO71RSB1
GDA2/IO70RSB1
GNDQ
IO47RSB0
GBC2/IO45RSB0
IO44RSB0
GBB2/IO43RSB0
IO42RSB0
GBA2/IO41RSB0
VMV0
TCK
TDI
TMS
GNDQ
VMV1
GNDQ
4-26
Revision 13
ProASIC3 Flash Family FPGAs
TQ144
Pin Number A3P125 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GBC1/IO36RSB0
GBC0/IO35RSB0
IO34RSB0
IO33RSB0
VCCIB0
GND
VCC
IO29RSB0
IO28RSB0
IO27RSB0
IO25RSB0
IO23RSB0
IO21RSB0
IO19RSB0
IO17RSB0
IO16RSB0
IO14RSB0
IO12RSB0
IO10RSB0
IO08RSB0
IO06RSB0
VCCIB0
GND
VCC
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
VMV0
Revision 13
4-27
Package Pin Assignments
PQ208
208
1
208-Pin PQFP
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-28
Revision 13
ProASIC3 Flash Family FPGAs
PQ208
A3P125 Function
PQ208
A3P125 Function
PQ208
Pin Number
Pin Number
37
Pin Number
A3P125 Function
IO92RSB1
IO91RSB1
IO90RSB1
IO89RSB1
IO88RSB1
IO87RSB1
IO86RSB1
IO85RSB1
GND
1
GND
GAA2/IO67RSB1
IO68RSB1
GAB2/IO69RSB1
IO132RSB1
GAC2/IO131RSB1
NC
IO116RSB1
IO115RSB1
NC
73
74
2
38
3
39
75
4
40
VCCIB1
76
5
41
GND
77
6
42
IO114RSB1
IO113RSB1
GEC1/IO112RSB1
GEC0/IO111RSB1
GEB1/IO110RSB1
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
VMV1
78
7
43
79
8
NC
44
80
9
IO130RSB1
IO129RSB1
NC
45
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
46
82
IO84RSB1
IO83RSB1
IO82RSB1
IO81RSB1
IO80RSB1
IO79RSB1
VCC
47
83
IO128RSB1
NC
48
84
49
85
NC
50
86
NC
51
GNDQ
87
VCC
52
GND
88
GND
53
NC
89
VCCIB1
VCCIB1
54
NC
90
IO78RSB1
IO77RSB1
IO76RSB1
IO75RSB1
IO74RSB1
IO73RSB1
GDC2/IO72RSB1
GND
IO127RSB1
NC
55
GEA2/IO106RSB1
GEB2/IO105RSB1
GEC2/IO104RSB1
IO103RSB1
IO102RSB1
IO101RSB1
IO100RSB1
VCCIB1
91
56
92
GFC1/IO126RSB1
GFC0/IO125RSB1
GFB1/IO124RSB1
GFB0/IO123RSB1
VCOMPLF
GFA0/IO122RSB1
VCCPLF
57
93
58
94
59
95
60
96
61
97
62
98
GDB2/IO71RSB1
GDA2/IO70RSB1
GNDQ
63
IO99RSB1
IO98RSB1
GND
99
GFA1/IO121RSB1
GND
64
100
101
102
103
104
105
106
107
108
65
TCK
GFA2/IO120RSB1
NC
66
IO97RSB1
IO96RSB1
IO95RSB1
IO94RSB1
IO93RSB1
VCC
TDI
67
TMS
GFB2/IO119RSB1
NC
68
VMV1
69
GND
GFC2/IO118RSB1
IO117RSB1
NC
70
VPUMP
71
NC
72
VCCIB1
TDO
Revision 13
4-29
Package Pin Assignments
PQ208
PQ208
A3P125 Function
PQ208
A3P125 Function
Pin Number
109
110
111
A3P125 Function
Pin Number
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pin Number
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
TRST
VJTAG
IO46RSB0
NC
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
VCCIB0
GDA0/IO66RSB0
GDA1/IO65RSB0
GDB0/IO64RSB0
GDB1/IO63RSB0
GDC0/IO62RSB0
GDC1/IO61RSB0
NC
NC
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NC
GBC2/IO45RSB0
IO44RSB0
GBB2/IO43RSB0
IO42RSB0
GBA2/IO41RSB0
VMV0
VCC
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
IO10RSB0
GND
NC
NC
GNDQ
NC
GND
NC
NC
GND
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GND
VCCIB0
NC
IO09RSB0
IO08RSB0
IO07RSB0
IO06RSB0
VCCIB0
NC
VCC
IO60RSB0
GCC2/IO59RSB0
GCB2/IO58RSB0
GND
GBC1/IO36RSB0
GBC0/IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
IO30RSB0
VCCIB0
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO57RSB0
GCA0/IO56RSB0
GCA1/IO55RSB0
GCB0/IO54RSB0
GCB1/IO53RSB0
GCC0/IO52RSB0
GCC1/IO51RSB0
IO50RSB0
IO49RSB0
VCCIB0
VCC
IO29RSB0
IO28RSB0
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
GND
VMV0
GND
VCC
IO48RSB0
IO47RSB0
IO23RSB0
IO22RSB0
4-30
Revision 13
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO104PDB3
IO104NDB3
IO103PSB3
VCCIB3
73
74
IO83RSB2
IO82RSB2
IO81RSB2
IO80RSB2
IO79RSB2
IO78RSB2
IO77RSB2
IO76RSB2
GND
2
GAA2/IO118UDB3
IO118VDB3
3
75
4
GAB2/IO117UDB3
IO117VDB3
76
5
GND
77
6
GAC2/IO116UDB3
IO116VDB3
IO101PDB3
IO101NDB3
GEC1/IO100PDB3
GEC0/IO100NDB3
GEB1/IO99PDB3
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
VMV3
78
7
79
8
IO115UDB3
IO115VDB3
80
9
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO114UDB3
IO114VDB3
82
IO75RSB2
IO74RSB2
IO73RSB2
IO72RSB2
IO71RSB2
IO70RSB2
VCC
83
IO113PDB3
84
IO113NDB3
IO112PDB3
85
86
IO112NDB3
VCC
GNDQ
87
GND
88
GND
NC
89
VCCIB2
VCCIB3
NC
90
IO69RSB2
IO68RSB2
IO67RSB2
IO66RSB2
IO65RSB2
IO64RSB2
GDC2/IO63RSB2
GND
IO111PDB3
GEA2/IO97RSB2
GEB2/IO96RSB2
GEC2/IO95RSB2
IO94RSB2
IO93RSB2
IO92RSB2
IO91RSB2
VCCIB2
91
IO111NDB3
92
GFC1/IO110PDB3
GFC0/IO110NDB3
GFB1/IO109PDB3
GFB0/IO109NDB3
VCOMPLF
93
94
95
96
97
GFA0/IO108NPB3
VCCPLF
98
GDB2/IO62RSB2
GDA2/IO61RSB2
GNDQ
IO90RSB2
IO89RSB2
GND
99
GFA1/IO108PPB3
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO107PDB3
IO107NDB3
GFB2/IO106PDB3
IO106NDB3
GFC2/IO105PDB3
IO105NDB3
NC
IO88RSB2
IO87RSB2
IO86RSB2
IO85RSB2
IO84RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
NC
VCCIB2
TDO
Revision 13
4-31
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO45PDB1
IO44NDB1
IO44PDB1
IO43NDB1
GBC2/IO43PDB1
IO42NDB1
GBB2/IO42PDB1
IO41NDB1
GBA2/IO41PDB1
VMV1
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
VCCIB0
GDA0/IO60VDB1
GDA1/IO60UDB1
GDB0/IO59VDB1
GDB1/IO59UDB1
GDC0/IO58VDB1
GDC1/IO58UDB1
IO57VDB1
VCC
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
IO10RSB0
GND
IO57UDB1
IO56NDB1
GNDQ
IO56PDB1
GND
IO55RSB1
NC
GND
GBA1/IO40RSB0
GBA0/IO39RSB0
GBB1/IO38RSB0
GBB0/IO37RSB0
GND
VCCIB1
NC
IO09RSB0
IO08RSB0
IO07RSB0
IO06RSB0
VCCIB0
NC
VCC
IO53NDB1
GBC1/IO36RSB0
GBC0/IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
IO30RSB0
VCCIB0
GCC2/IO53PDB1
GCB2/IO52PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO51PSB1
GCA1/IO50PDB1
GCA0/IO50NDB1
GCB0/IO49NDB1
GCB1/IO49PDB1
GCC0/IO48NDB1
GCC1/IO48PDB1
IO47NDB1
VCC
IO29RSB0
IO28RSB0
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
GND
VMV0
IO47PDB1
VCCIB1
GND
VCC
IO46RSB1
IO23RSB0
IO22RSB0
IO45NDB1
4-32
Revision 13
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO141PSB3
IO140PDB3
IO140NDB3
VCCIB3
73
74
IO112RSB2
IO111RSB2
IO110RSB2
IO109RSB2
IO108RSB2
IO107RSB2
IO106RSB2
IO104RSB2
GND
2
GAA2/IO155UDB3
IO155VDB3
GAB2/IO154UDB3
IO154VDB3
GAC2/IO153UDB3
IO153VDB3
IO152UDB3
IO152VDB3
IO151UDB3
IO151VDB3
IO150PDB3
IO150NDB3
IO149PDB3
IO149NDB3
VCC
3
75
4
76
5
GND
77
6
IO138PDB3
IO138NDB3
GEC1/IO137PDB3
GEC0/IO137NDB3
GEB1/IO136PDB3
GEB0/IO136NDB3
GEA1/IO135PDB3
GEA0/IO135NDB3
VMV3
78
7
79
8
80
9
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
IO102RSB2
IO101RSB2
IO100RSB2
IO99RSB2
IO98RSB2
IO97RSB2
VCC
83
84
85
86
GNDQ
87
GND
88
GND
VMV2
89
VCCIB2
VCCIB3
NC
90
IO94RSB2
IO92RSB2
IO90RSB2
IO88RSB2
IO86RSB2
IO84RSB2
GDC2/IO82RSB2
GND
IO148PDB3
IO148NDB3
GFC1/IO147PDB3
GFC0/IO147NDB3
GFB1/IO146PDB3
GFB0/IO146NDB3
VCOMPLF
GEA2/IO134RSB2
GEB2/IO133RSB2
GEC2/IO132RSB2
IO131RSB2
IO130RSB2
IO129RSB2
IO128RSB2
VCCIB2
91
92
93
94
95
96
97
GFA0/IO145NPB3
VCCPLF
98
GDB2/IO81RSB2
GDA2/IO80RSB2
GNDQ
IO125RSB2
IO123RSB2
GND
99
GFA1/IO145PPB3
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO144PDB3
IO144NDB3
GFB2/IO143PDB3
IO143NDB3
GFC2/IO142PDB3
IO142NDB3
NC
IO121RSB2
IO119RSB2
IO117RSB2
IO115RSB2
IO113RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
NC
VCCIB2
TDO
Revision 13
4-33
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO64PDB1
IO63NDB1
IO63PDB1
IO62NDB1
GBC2/IO62PDB1
IO61NDB1
GBB2/IO61PDB1
IO60NDB1
GBA2/IO60PDB1
VMV1
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
VCCIB0
GDA0/IO79VDB1
GDA1/IO79UDB1
GDB0/IO78VDB1
GDB1/IO78UDB1
GDC0/IO77VDB1
GDC1/IO77UDB1
IO76VDB1
VCC
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO15RSB0
GND
IO76UDB1
IO75NDB1
GNDQ
IO75PDB1
GND
IO74RSB1
VMV0
GND
GBA1/IO59RSB0
GBA0/IO58RSB0
GBB1/IO57RSB0
GBB0/IO56RSB0
GND
VCCIB1
NC
IO13RSB0
IO11RSB0
IO09RSB0
IO07RSB0
VCCIB0
NC
VCC
IO72NDB1
GBC1/IO55RSB0
GBC0/IO54RSB0
IO52RSB0
IO49RSB0
IO46RSB0
IO43RSB0
IO40RSB0
VCCIB0
GCC2/IO72PDB1
GCB2/IO71PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO70PSB1
GCA1/IO69PDB1
GCA0/IO69NDB1
GCB0/IO68NDB1
GCB1/IO68PDB1
GCC0/IO67NDB1
GCC1/IO67PDB1
IO66NDB1
VCC
IO36RSB0
IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
GND
VMV0
IO66PDB1
VCCIB1
GND
VCC
IO65RSB1
IO29RSB0
IO28RSB0
IO64NDB1
4-34
Revision 13
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO152PDB3
IO152NDB3
IO150PSB3
VCCIB3
73
74
IO120RSB2
IO119RSB2
IO118RSB2
IO117RSB2
IO116RSB2
IO115RSB2
IO114RSB2
IO112RSB2
GND
2
GAA2/IO174PDB3
IO174NDB3
GAB2/IO173PDB3
IO173NDB3
GAC2/IO172PDB3
IO172NDB3
IO171PDB3
IO171NDB3
IO170PDB3
3
75
4
76
5
GND
77
6
IO147PDB3
IO147NDB3
GEC1/IO146PDB3
GEC0/IO146NDB3
GEB1/IO145PDB3
GEB0/IO145NDB3
GEA1/IO144PDB3
GEA0/IO144NDB3
VMV3
78
7
79
8
80
9
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
IO111RSB2
IO110RSB2
IO109RSB2
IO108RSB2
IO107RSB2
IO106RSB2
VCC
IO170NDB3
IO169PDB3
83
84
IO169NDB3
IO168PDB3
85
86
IO168NDB3
VCC
GNDQ
87
GND
88
GND
VMV2
89
VCCIB2
VCCIB3
GEA2/IO143RSB2
GEB2/IO142RSB2
GEC2/IO141RSB2
IO140RSB2
IO139RSB2
IO138RSB2
IO137RSB2
IO136RSB2
VCCIB2
90
IO104RSB2
IO102RSB2
IO100RSB2
IO98RSB2
IO96RSB2
IO92RSB2
GDC2/IO91RSB2
GND
IO166PDB3
91
IO166NDB3
GFC1/IO164PDB3
GFC0/IO164NDB3
GFB1/IO163PDB3
GFB0/IO163NDB3
VCOMPLF
92
93
94
95
96
97
GFA0/IO162NPB3
VCCPLF
98
GDB2/IO90RSB2
GDA2/IO89RSB2
GNDQ
IO135RSB2
IO133RSB2
GND
99
GFA1/IO162PPB3
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO161PDB3
IO161NDB3
GFB2/IO160PDB3
IO160NDB3
GFC2/IO159PDB3
IO159NDB3
VCC
IO131RSB2
IO129RSB2
IO127RSB2
IO125RSB2
IO123RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
GNDQ
VCCIB2
TDO
Revision 13
4-35
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO64PDB1
IO63NDB1
IO63PDB1
IO62NDB1
GBC2/IO62PDB1
IO61NDB1
GBB2/IO61PDB1
IO60NDB1
GBA2/IO60PDB1
VMV1
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO27RSB0
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
VCCIB0
GDA0/IO88NDB1
GDA1/IO88PDB1
GDB0/IO87NDB1
GDB1/IO87PDB1
GDC0/IO86NDB1
GDC1/IO86PDB1
IO84NDB1
VCC
IO20RSB0
IO19RSB0
IO18RSB0
IO17RSB0
IO16RSB0
IO14RSB0
IO12RSB0
GND
IO84PDB1
IO82NDB1
GNDQ
IO82PDB1
GND
IO81PSB1
VMV0
GND
GBA1/IO59RSB0
GBA0/IO58RSB0
GBB1/IO57RSB0
GBB0/IO56RSB0
GND
VCCIB1
IO77NDB1
IO10RSB0
IO09RSB0
IO08RSB0
IO07RSB0
VCCIB0
IO77PDB1
NC
IO74NDB1
GBC1/IO55RSB0
GBC0/IO54RSB0
IO52RSB0
IO50RSB0
IO48RSB0
IO46RSB0
IO44RSB0
VCCIB0
GCC2/IO74PDB1
GCB2/IO73PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO72PSB1
GCA1/IO71PDB1
GCA0/IO71NDB1
GCB0/IO70NDB1
GCB1/IO70PDB1
GCC0/IO69NDB1
GCC1/IO69PDB1
IO67NDB1
VCC
IO36RSB0
IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO31RSB0
GND
VMV0
IO67PDB1
VCCIB1
GND
VCC
IO65PSB1
IO29RSB0
IO28RSB0
IO64NDB1
4-36
Revision 13
ProASIC3 Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO199PDB3
IO199NDB3
IO197PSB3
VCCIB3
73
74
IO162RSB2
IO160RSB2
IO158RSB2
IO156RSB2
IO154RSB2
IO152RSB2
IO150RSB2
IO148RSB2
GND
2
GAA2/IO225PDB3
IO225NDB3
GAB2/IO224PDB3
IO224NDB3
GAC2/IO223PDB3
IO223NDB3
IO222PDB3
3
75
4
76
5
GND
77
6
IO191PDB3
IO191NDB3
GEC1/IO190PDB3
GEC0/IO190NDB3
GEB1/IO189PDB3
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
VMV3
78
7
79
8
80
9
IO222NDB3
IO220PDB3
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
IO143RSB2
IO141RSB2
IO139RSB2
IO137RSB2
IO135RSB2
IO133RSB2
VCC
IO220NDB3
IO218PDB3
83
84
IO218NDB3
IO216PDB3
85
86
IO216NDB3
VCC
GNDQ
87
GND
88
GND
VMV2
89
VCCIB2
VCCIB3
GEA2/IO187RSB2
GEB2/IO186RSB2
GEC2/IO185RSB2
IO184RSB2
IO183RSB2
IO182RSB2
IO181RSB2
IO180RSB2
VCCIB2
90
IO128RSB2
IO126RSB2
IO124RSB2
IO122RSB2
IO120RSB2
IO118RSB2
GDC2/IO116RSB2
GND
IO212PDB3
91
IO212NDB3
GFC1/IO209PDB3
GFC0/IO209NDB3
GFB1/IO208PDB3
GFB0/IO208NDB3
VCOMPLF
92
93
94
95
96
97
GFA0/IO207NPB3
VCCPLF
98
GDB2/IO115RSB2
GDA2/IO114RSB2
GNDQ
IO178RSB2
IO176RSB2
GND
99
GFA1/IO207PPB3
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO206PDB3
IO206NDB3
GFB2/IO205PDB3
IO205NDB3
GFC2/IO204PDB3
IO204NDB3
VCC
IO174RSB2
IO172RSB2
IO170RSB2
IO168RSB2
IO166RSB2
VCC
TDI
TMS
VMV2
GND
VPUMP
GNDQ
VCCIB2
TDO
Revision 13
4-37
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO84PDB1
IO82NDB1
IO82PDB1
IO80NDB1
GBC2/IO80PDB1
IO79NDB1
GBB2/IO79PDB1
IO78NDB1
GBA2/IO78PDB1
VMV1
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO33RSB0
IO31RSB0
IO29RSB0
IO27RSB0
IO25RSB0
VCCIB0
GDA0/IO113NDB1
GDA1/IO113PDB1
GDB0/IO112NDB1
GDB1/IO112PDB1
GDC0/IO111NDB1
GDC1/IO111PDB1
IO109NDB1
IO109PDB1
IO106NDB1
IO106PDB1
IO104PSB1
GND
VCC
IO22RSB0
IO20RSB0
IO18RSB0
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
GND
GNDQ
GND
VMV0
GBA1/IO77RSB0
GBA0/IO76RSB0
GBB1/IO75RSB0
GBB0/IO74RSB0
GND
VCCIB1
IO99NDB1
IO12RSB0
IO11RSB0
IO10RSB0
IO09RSB0
VCCIB0
IO99PDB1
NC
IO96NDB1
GBC1/IO73RSB0
GBC0/IO72RSB0
IO70RSB0
IO67RSB0
IO63RSB0
IO60RSB0
IO57RSB0
VCCIB0
GCC2/IO96PDB1
GCB2/IO95PSB1
GND
GAC1/IO05RSB0
GAC0/IO04RSB0
GAB1/IO03RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GNDQ
GCA2/IO94PSB1
GCA1/IO93PDB1
GCA0/IO93NDB1
GCB0/IO92NDB1
GCB1/IO92PDB1
GCC0/IO91NDB1
GCC1/IO91PDB1
IO88NDB1
VCC
IO54RSB0
IO51RSB0
IO48RSB0
IO45RSB0
IO42RSB0
IO40RSB0
GND
VMV0
IO88PDB1
VCCIB1
GND
VCC
IO86PSB1
IO38RSB0
IO35RSB0
IO84NDB1
4-38
Revision 13
ProASIC3 Flash Family FPGAs
FG144
A1 Ball Pad Corner
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-39
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P060 Function
Pin Number A3P060 Function
Pin Number A3P060 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO91RSB1
IO92RSB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO84RSB1
GND
A3
GAB0/IO04RSB0
GAB1/IO05RSB0
IO08RSB0
IO93RSB1
VCCPLF
A4
GAA2/IO51RSB1
GAC0/IO06RSB0
GAC1/IO07RSB0
GBC0/IO19RSB0
GBC1/IO20RSB0
GBB2/IO27RSB0
IO18RSB0
GFA0/IO85RSB1
GND
A5
A6
GND
GND
A7
IO11RSB0
GND
A8
VCC
GDC1/IO45RSB0
IO32RSB0
GCC2/IO43RSB0
IO31RSB0
GCB2/IO42RSB0
VCC
A9
IO16RSB0
A10
A11
A12
B1
GBA0/IO23RSB0
GBA1/IO24RSB0
GNDQ
IO28RSB0
GCB1/IO37RSB0
VCC
GAB2/IO53RSB1
GND
B2
E2
GFC0/IO88RSB1
GFC1/IO89RSB1
VCCIB1
GFB2/IO82RSB1
GFC2/IO81RSB1
GEC1/IO77RSB1
VCC
B3
GAA0/IO02RSB0
GAA1/IO03RSB0
IO00RSB0
E3
B4
E4
B5
E5
IO52RSB1
B6
IO10RSB0
E6
VCCIB0
IO34RSB0
IO44RSB0
GDB2/IO55RSB1
GDC0/IO46RSB0
VCCIB0
B7
IO12RSB0
E7
VCCIB0
B8
IO14RSB0
E8
GCC1/IO35RSB0
VCCIB0
B9
GBB0/IO21RSB0
GBB1/IO22RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO40RSB0
IO30RSB0
IO33RSB0
VCC
VMV0
IO95RSB1
GFB0/IO86RSB1
VCOMPLF
GEB1/IO75RSB1
IO78RSB1
VCCIB1
GFA2/IO83RSB1
GAC2/IO94RSB1
VCC
F2
J2
F3
GFB1/IO87RSB1
IO90RSB1
J3
F4
J4
GEC0/IO76RSB1
IO79RSB1
IO80RSB1
VCC
IO01RSB0
F5
GND
J5
IO09RSB0
F6
GND
J6
IO13RSB0
F7
GND
J7
IO15RSB0
F8
GCC0/IO36RSB0
GCB0/IO38RSB0
GND
J8
TCK
IO17RSB0
F9
J9
GDA2/IO54RSB1
TDO
GBA2/IO25RSB0
IO26RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO39RSB0
GCA2/IO41RSB0
GDA1/IO49RSB0
GDB1/IO47RSB0
GBC2/IO29RSB0
4-40
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P060 Function
K1
K2
GEB0/IO74RSB1
GEA1/IO73RSB1
GEA0/IO72RSB1
GEA2/IO71RSB1
IO65RSB1
IO64RSB1
GND
K3
K4
K5
K6
K7
K8
IO57RSB1
GDC2/IO56RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO50RSB0
GDB0/IO48RSB0
GND
L2
VMV1
L3
GEB2/IO70RSB1
IO67RSB1
VCCIB1
L4
L5
L6
IO62RSB1
IO59RSB1
IO58RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO69RSB1
IO68RSB1
IO66RSB1
IO63RSB1
IO61RSB1
IO60RSB1
NC
TDI
VCCIB1
VPUMP
GNDQ
Revision 13
4-41
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P125 Function
Pin Number A3P125 Function
Pin Number A3P125 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO128RSB1
IO129RSB1
IO130RSB1
GAA2/IO67RSB1
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO43RSB0
IO28RSB0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO121RSB1
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO11RSB0
VCCPLF
A4
GFA0/IO122RSB1
GND
A5
A6
GND
GND
A7
IO18RSB0
GND
A8
VCC
GDC1/IO61RSB0
IO48RSB0
A9
IO25RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
GCC2/IO59RSB0
IO47RSB0
IO44RSB0
GCB1/IO53RSB0
VCC
GCB2/IO58RSB0
VCC
GAB2/IO69RSB1
GND
B2
E2
GFC0/IO125RSB1
GFC1/IO126RSB1
VCCIB1
GFB2/IO119RSB1
GFC2/IO118RSB1
GEC1/IO112RSB1
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO08RSB0
E3
B4
E4
B5
E5
IO68RSB1
B6
IO14RSB0
E6
VCCIB0
IO50RSB0
B7
IO19RSB0
E7
VCCIB0
IO60RSB0
B8
IO22RSB0
E8
GCC1/IO51RSB0
VCCIB0
GDB2/IO71RSB1
GDC0/IO62RSB0
VCCIB0
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO56RSB0
IO46RSB0
IO49RSB0
VMV0
VCC
IO132RSB1
GFA2/IO120RSB1
GAC2/IO131RSB1
VCC
GFB0/IO123RSB1
VCOMPLF
GEB1/IO110RSB1
IO115RSB1
VCCIB1
F2
J2
F3
GFB1/IO124RSB1
IO127RSB1
GND
J3
F4
J4
GEC0/IO111RSB1
IO116RSB1
IO117RSB1
VCC
IO10RSB0
F5
J5
IO12RSB0
F6
GND
J6
IO21RSB0
F7
GND
J7
IO24RSB0
F8
GCC0/IO52RSB0
GCB0/IO54RSB0
GND
J8
TCK
IO27RSB0
F9
J9
GDA2/IO70RSB1
TDO
GBA2/IO41RSB0
IO42RSB0
F10
F11
F12
J10
J11
J12
GCA1/IO55RSB0
GCA2/IO57RSB0
GDA1/IO65RSB0
GDB1/IO63RSB0
GBC2/IO45RSB0
4-42
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P125 Function
K1
K2
GEB0/IO109RSB1
GEA1/IO108RSB1
GEA0/IO107RSB1
GEA2/IO106RSB1
IO100RSB1
IO98RSB1
GND
K3
K4
K5
K6
K7
K8
IO73RSB1
GDC2/IO72RSB1
GND
K9
K10
K11
K12
L1
GDA0/IO66RSB0
GDB0/IO64RSB0
GND
L2
VMV1
L3
GEB2/IO105RSB1
IO102RSB1
VCCIB1
L4
L5
L6
IO95RSB1
IO85RSB1
IO74RSB1
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV1
TRST
GNDQ
GEC2/IO104RSB1
IO103RSB1
IO101RSB1
IO97RSB1
IO94RSB1
IO86RSB1
IO75RSB1
TDI
VCCIB1
VPUMP
GNDQ
Revision 13
4-43
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO112NDB3
IO112PDB3
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO108PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
IO116VDB3
VCCPLF
A4
GAA2/IO118UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO35RSB0
GBC1/IO36RSB0
GBB2/IO42PDB1
IO42NDB1
GFA0/IO108NPB3
GND
A5
A6
GND
GND
A7
IO29RSB0
GND
A8
VCC
GDC1/IO58UPB1
IO53NDB1
A9
IO33RSB0
A10
A11
A12
B1
GBA0/IO39RSB0
GBA1/IO40RSB0
GNDQ
GCC2/IO53PDB1
IO52NDB1
IO43NPB1
GCB1/IO49PPB1
VCC
GCB2/IO52PDB1
VCC
GAB2/IO117UDB3
GND
B2
E2
GFC0/IO110NDB3
GFC1/IO110PDB3
VCCIB3
GFB2/IO106PDB3
GFC2/IO105PSB3
GEC1/IO100PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO118VPB3
B6
IO19RSB0
E6
VCCIB0
IO79RSB2
B7
IO22RSB0
E7
VCCIB0
IO65RSB2
B8
IO30RSB0
E8
GCC1/IO48PDB1
VCCIB1
GDB2/IO62RSB2
GDC0/IO58VPB1
VCCIB1
B9
GBB0/IO37RSB0
GBB1/IO38RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO50NDB1
IO51NDB1
IO54PSB1
VMV1
VCC
IO117VDB3
GFA2/IO107PPB3
GAC2/IO116UDB3
VCC
GFB0/IO109NPB3
VCOMPLF
GEB1/IO99PDB3
IO106NDB3
VCCIB3
F2
J2
F3
GFB1/IO109PPB3
IO107NPB3
GND
J3
F4
J4
GEC0/IO100NDB3
IO88RSB2
IO12RSB0
F5
J5
IO17RSB0
F6
GND
J6
IO81RSB2
IO24RSB0
F7
GND
J7
VCC
IO31RSB0
F8
GCC0/IO48NDB1
GCB0/IO49NPB1
GND
J8
TCK
IO34RSB0
F9
J9
GDA2/IO61RSB2
TDO
GBA2/IO41PDB1
IO41NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO50PDB1
GCA2/IO51PDB1
GDA1/IO60UDB1
GDB1/IO59UDB1
GBC2/IO43PPB1
4-44
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P250 Function
K1
K2
GEB0/IO99NDB3
GEA1/IO98PDB3
GEA0/IO98NDB3
GEA2/IO97RSB2
IO90RSB2
IO84RSB2
GND
K3
K4
K5
K6
K7
K8
IO66RSB2
GDC2/IO63RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO60VDB1
GDB0/IO59VDB1
GND
L2
VMV3
L3
GEB2/IO96RSB2
IO91RSB2
VCCIB2
L4
L5
L6
IO82RSB2
IO80RSB2
IO72RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO95RSB2
IO92RSB2
IO89RSB2
IO87RSB2
IO85RSB2
IO78RSB2
IO76RSB2
TDI
VCCIB2
VPUMP
GNDQ
Revision 13
4-45
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO149NDB3
IO149PDB3
IO153VDB3
GAA2/IO155UPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO54RSB0
GBC1/IO55RSB0
GBB2/IO61PDB1
IO61NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO145PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO16RSB0
VCCPLF
A4
GFA0/IO145NPB3
GND
A5
A6
GND
GND
A7
IO30RSB0
GND
A8
VCC
GDC1/IO77UPB1
IO72NDB1
A9
IO34RSB0
A10
A11
A12
B1
GBA0/IO58RSB0
GBA1/IO59RSB0
GNDQ
GCC2/IO72PDB1
IO71NDB1
IO62NPB1
GCB1/IO68PPB1
VCC
GCB2/IO71PDB1
VCC
GAB2/IO154UDB3
GND
B2
E2
GFC0/IO147NDB3
GFC1/IO147PDB3
VCCIB3
GFB2/IO143PDB3
GFC2/IO142PSB3
GEC1/IO137PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO14RSB0
E3
B4
E4
B5
E5
IO155VPB3
B6
IO19RSB0
E6
VCCIB0
IO75PDB1
B7
IO23RSB0
E7
VCCIB0
IO75NDB1
B8
IO31RSB0
E8
GCC1/IO67PDB1
VCCIB1
GDB2/IO81RSB2
GDC0/IO77VPB1
VCCIB1
B9
GBB0/IO56RSB0
GBB1/IO57RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO69NDB1
IO70NDB1
IO73PSB1
VMV1
VCC
IO154VDB3
GFA2/IO144PPB3
GAC2/IO153UDB3
VCC
GFB0/IO146NPB3
VCOMPLF
GEB1/IO136PDB3
IO143NDB3
VCCIB3
F2
J2
F3
GFB1/IO146PPB3
IO144NPB3
GND
J3
F4
J4
GEC0/IO137NDB3
IO125RSB2
IO116RSB2
VCC
IO12RSB0
F5
J5
IO17RSB0
F6
GND
J6
IO25RSB0
F7
GND
J7
IO32RSB0
F8
GCC0/IO67NDB1
GCB0/IO68NPB1
GND
J8
TCK
IO53RSB0
F9
J9
GDA2/IO80RSB2
TDO
GBA2/IO60PDB1
IO60NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO69PDB1
GCA2/IO70PDB1
GDA1/IO79UDB1
GDB1/IO78UDB1
GBC2/IO62PPB1
4-46
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P400 Function
K1
K2
GEB0/IO136NDB3
GEA1/IO135PDB3
GEA0/IO135NDB3
GEA2/IO134RSB2
IO127RSB2
IO121RSB2
GND
K3
K4
K5
K6
K7
K8
IO104RSB2
GDC2/IO82RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO79VDB1
GDB0/IO78VDB1
GND
L2
VMV3
L3
GEB2/IO133RSB2
IO128RSB2
VCCIB2
L4
L5
L6
IO119RSB2
IO114RSB2
IO110RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO132RSB2
IO129RSB2
IO126RSB2
IO124RSB2
IO122RSB2
IO117RSB2
IO115RSB2
TDI
VCCIB2
VPUMP
GNDQ
Revision 13
4-47
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO169PDB3
IO169NDB3
IO172NDB3
GAA2/IO174PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO54RSB0
GBC1/IO55RSB0
GBB2/IO61PDB1
IO61NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO162PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO162NPB3
GND
A5
A6
GND
GND
A7
IO34RSB0
GND
A8
VCC
GDC1/IO86PPB1
IO74NDB1
A9
IO50RSB0
A10
A11
A12
B1
GBA0/IO58RSB0
GBA1/IO59RSB0
GNDQ
GCC2/IO74PDB1
IO73NDB1
IO62NPB1
GCB1/IO70PPB1
VCC
GCB2/IO73PDB1
VCC
GAB2/IO173PDB3
GND
B2
E2
GFC0/IO164NDB3
GFC1/IO164PDB3
VCCIB3
GFB2/IO160PDB3
GFC2/IO159PSB3
GEC1/IO146PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO174NPB3
VCCIB0
B6
IO19RSB0
E6
IO80PDB1
B7
IO31RSB0
E7
VCCIB0
IO80NDB1
B8
IO39RSB0
E8
GCC1/IO69PDB1
VCCIB1
GDB2/IO90RSB2
GDC0/IO86NPB1
VCCIB1
B9
GBB0/IO56RSB0
GBB1/IO57RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO71NDB1
IO72NDB1
IO84PSB1
VMV1
VCC
IO173NDB3
GFA2/IO161PPB3
GAC2/IO172PDB3
VCC
GFB0/IO163NPB3
VCOMPLF
GEB1/IO145PDB3
IO160NDB3
VCCIB3
F2
J2
F3
GFB1/IO163PPB3
IO161NPB3
GND
J3
F4
J4
GEC0/IO146NDB3
IO129RSB2
IO131RSB2
VCC
IO16RSB0
F5
J5
IO25RSB0
F6
GND
J6
IO28RSB0
F7
GND
J7
IO42RSB0
F8
GCC0/IO69NDB1
GCB0/IO70NPB1
GND
J8
TCK
IO45RSB0
F9
J9
GDA2/IO89RSB2
TDO
GBA2/IO60PDB1
IO60NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO71PDB1
GCA2/IO72PDB1
GDA1/IO88PDB1
GDB1/IO87PDB1
GBC2/IO62PPB1
4-48
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P600 Function
K1
K2
GEB0/IO145NDB3
GEA1/IO144PDB3
GEA0/IO144NDB3
GEA2/IO143RSB2
IO119RSB2
IO111RSB2
GND
K3
K4
K5
K6
K7
K8
IO94RSB2
GDC2/IO91RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO88NDB1
GDB0/IO87NDB1
GND
L2
VMV3
L3
GEB2/IO142RSB2
IO136RSB2
VCCIB2
L4
L5
L6
IO115RSB2
IO103RSB2
IO97RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO141RSB2
IO138RSB2
IO123RSB2
IO126RSB2
IO134RSB2
IO108RSB2
IO99RSB2
TDI
VCCIB2
VPUMP
GNDQ
Revision 13
4-49
Package Pin Assignments
FG144
FG144
FG144
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GNDQ
VMV0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
IO213PDB3
IO213NDB3
IO223NDB3
GAA2/IO225PPB3
GAC0/IO04RSB0
GAC1/IO05RSB0
GBC0/IO72RSB0
GBC1/IO73RSB0
GBB2/IO79PDB1
IO79NDB1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GFA1/IO207PPB3
GND
A3
GAB0/IO02RSB0
GAB1/IO03RSB0
IO10RSB0
VCCPLF
A4
GFA0/IO207NPB3
GND
A5
A6
GND
GND
A7
IO44RSB0
GND
A8
VCC
GDC1/IO111PPB1
IO96NDB1
A9
IO69RSB0
A10
A11
A12
B1
GBA0/IO76RSB0
GBA1/IO77RSB0
GNDQ
GCC2/IO96PDB1
IO95NDB1
IO80NPB1
GCB1/IO92PPB1
VCC
GCB2/IO95PDB1
VCC
GAB2/IO224PDB3
GND
B2
E2
GFC0/IO209NDB3
GFC1/IO209PDB3
VCCIB3
GFB2/IO205PDB3
GFC2/IO204PSB3
GEC1/IO190PDB3
VCC
B3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO13RSB0
E3
B4
E4
B5
E5
IO225NPB3
VCCIB0
B6
IO26RSB0
E6
IO105PDB1
IO105NDB1
GDB2/IO115RSB2
GDC0/IO111NPB1
VCCIB1
B7
IO35RSB0
E7
VCCIB0
B8
IO60RSB0
E8
GCC1/IO91PDB1
VCCIB1
B9
GBB0/IO74RSB0
GBB1/IO75RSB0
GND
E9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
E10
E11
E12
F1
VCC
GCA0/IO93NDB1
IO94NDB1
IO101PSB1
VCC
VMV1
IO224NDB3
GFA2/IO206PPB3
GAC2/IO223PDB3
VCC
GFB0/IO208NPB3
VCOMPLF
GEB1/IO189PDB3
IO205NDB3
VCCIB3
F2
J2
F3
GFB1/IO208PPB3
IO206NPB3
GND
J3
F4
J4
GEC0/IO190NDB3
IO160RSB2
IO157RSB2
VCC
IO16RSB0
F5
J5
IO29RSB0
F6
GND
J6
IO32RSB0
F7
GND
J7
IO63RSB0
F8
GCC0/IO91NDB1
GCB0/IO92NPB1
GND
J8
TCK
IO66RSB0
F9
J9
GDA2/IO114RSB2
TDO
GBA2/IO78PDB1
IO78NDB1
F10
F11
F12
J10
J11
J12
GCA1/IO93PDB1
GCA2/IO94PDB1
GDA1/IO113PDB1
GDB1/IO112PDB1
GBC2/IO80PPB1
4-50
Revision 13
ProASIC3 Flash Family FPGAs
FG144
Pin Number A3P1000 Function
K1
K2
GEB0/IO189NDB3
GEA1/IO188PDB3
GEA0/IO188NDB3
GEA2/IO187RSB2
IO169RSB2
IO152RSB2
GND
K3
K4
K5
K6
K7
K8
IO117RSB2
GDC2/IO116RSB2
GND
K9
K10
K11
K12
L1
GDA0/IO113NDB1
GDB0/IO112NDB1
GND
L2
VMV3
L3
GEB2/IO186RSB2
IO172RSB2
VCCIB2
L4
L5
L6
IO153RSB2
IO144RSB2
IO140RSB2
TMS
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VJTAG
VMV2
TRST
GNDQ
GEC2/IO185RSB2
IO173RSB2
IO168RSB2
IO161RSB2
IO156RSB2
IO145RSB2
IO141RSB2
TDI
VCCIB2
VPUMP
GNDQ
Revision 13
4-51
Package Pin Assignments
FG256
A1 Ball Pad Corner
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-52
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO07RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO13RSB0
IO17RSB0
IO22RSB0
IO27RSB0
IO31RSB0
GBC0/IO35RSB0
IO34RSB0
NC
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO24RSB0
VCCIB0
VCCIB0
VMV1
A3
C7
A4
C8
A5
C9
GBC2/IO43PDB1
IO46RSB1
NC
A6
IO10RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO11RSB0
A8
IO15RSB0
IO45PDB1
IO113NDB3
IO112PPB3
NC
A9
IO20RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO25RSB0
F2
IO29RSB0
IO42NPB1
IO44PDB1
IO114VDB3
IO114UDB3
GAC2/IO116UDB3
NC
F3
IO33RSB0
F4
IO115VDB3
VCCIB3
GND
GBB1/IO38RSB0
GBA0/IO39RSB0
GBA1/IO40RSB0
GND
F5
D2
F6
D3
F7
VCC
D4
F8
VCC
GAB2/IO117UDB3
GAA2/IO118UDB3
NC
D5
GNDQ
F9
VCC
B2
D6
IO08RSB0
IO14RSB0
IO18RSB0
IO23RSB0
IO28RSB0
IO32RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO06RSB0
D8
VCCIB1
IO43NDB1
NC
B5
D9
B6
IO09RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO12RSB0
IO47PPB1
IO45NDB1
IO111NDB3
IO111PDB3
IO112NPB3
GFC1/IO110PPB3
VCCIB3
VCC
B8
IO16RSB0
B9
IO21RSB0
NC
B10
B11
B12
B13
B14
B15
B16
C1
IO26RSB0
GBB2/IO42PPB1
NC
G2
IO30RSB0
G3
GBC1/IO36RSB0
GBB0/IO37RSB0
NC
IO44NDB1
IO113PDB3
NC
G4
G5
E2
G6
GBA2/IO41PDB1
IO41NDB1
E3
IO116VDB3
IO115UDB3
VMV0
G7
GND
E4
G8
GND
IO117VDB3
IO118VDB3
NC
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
NC
E8
IO19RSB0
VCCIB1
Revision 13
4-53
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3P250 Function
Pin Number A3P250 Function
Pin Number A3P250 Function
G13
G14
G15
G16
H1
GCC1/IO48PPB1
IO47NPB1
IO54PDB1
IO54NDB1
GFB0/IO109NPB3
GFA0/IO108NDB3
GFB1/IO109PPB3
VCOMPLF
GFC0/IO110NPB3
VCC
K1
K2
GFC2/IO105PDB3
IO107NPB3
IO104PPB3
NC
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
K3
VCCIB2
K4
NC
K5
VCCIB3
VCC
IO74RSB2
VCCIB2
H2
K6
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
K9
GND
NC
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO59UPB1
GDC1/IO58UDB1
IO56NDB1
IO103NDB3
IO101PPB3
GEC1/IO100PPB3
NC
H7
GND
VCC
H8
GND
VCCIB1
IO52NPB1
IO55RSB1
IO53NPB1
IO51NDB1
IO105NDB3
IO104NPB3
NC
H9
GND
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO48NPB1
GCB1/IO49PPB1
GCA0/IO50NPB1
NC
N4
N5
GNDQ
L2
N6
GEA2/IO97RSB2
IO86RSB2
IO82RSB2
IO75RSB2
IO69RSB2
IO64RSB2
GNDQ
L3
N7
GCB0/IO49NPB1
GFA2/IO107PPB3
GFA1/IO108PDB3
VCCPLF
L4
IO102RSB3
VCCIB3
GND
N8
L5
N9
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO106NDB3
GFB2/IO106PDB3
VCC
L8
VCC
J5
L9
VCC
NC
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO58VDB1
GDA1/IO60UDB1
GEB1/IO99PDB3
GEB0/IO99NDB3
NC
J8
GND
VCCIB1
GDB0/IO59VPB1
IO57VDB1
IO57UDB1
IO56PDB1
IO103PDB3
NC
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO52PPB1
GCA1/IO50PPB1
GCC2/IO53PPB1
NC
P4
NC
P5
IO92RSB2
IO89RSB2
IO85RSB2
IO81RSB2
P6
IO101NPB3
GEC0/IO100NPB3
P7
GCA2/IO51PDB1
P8
4-54
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
Pin Number A3P250 Function
Pin Number A3P250 Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO76RSB2
IO71RSB2
IO66RSB2
NC
T13
T14
T15
T16
IO67RSB2
GDA2/IO61RSB2
TMS
GND
TCK
VPUMP
TRST
GDA0/IO60VDB1
GEA1/IO98PDB3
GEA0/IO98NDB3
NC
R2
R3
R4
GEC2/IO95RSB2
IO91RSB2
IO88RSB2
IO84RSB2
IO80RSB2
IO77RSB2
IO72RSB2
IO68RSB2
IO65RSB2
GDB2/IO62RSB2
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
NC
TDO
GND
T2
IO94RSB2
GEB2/IO96RSB2
IO93RSB2
IO90RSB2
IO87RSB2
IO83RSB2
IO79RSB2
IO78RSB2
IO73RSB2
IO70RSB2
GDC2/IO63RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Revision 13
4-55
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO45RSB0
GBC0/IO54RSB0
IO48RSB0
VMV0
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO31RSB0
VCCIB0
A3
C7
VCCIB0
A4
C8
VMV1
A5
C9
GBC2/IO62PDB1
IO65RSB1
IO52RSB0
IO66PDB1
IO150NDB3
IO149NPB3
IO09RSB0
IO152UDB3
VCCIB3
A6
IO17RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO22RSB0
A8
IO28RSB0
A9
IO34RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO37RSB0
F2
IO41RSB0
IO61NPB1
IO63PDB1
IO151VDB3
IO151UDB3
GAC2/IO153UDB3
IO06RSB0
GNDQ
F3
IO43RSB0
F4
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO154UDB3
GAA2/IO155UDB3
IO12RSB0
D5
F9
VCC
B2
D6
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO46RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO13RSB0
D8
VCCIB1
B5
D9
IO62NDB1
IO49RSB0
IO64PPB1
IO66NDB1
IO148NDB3
IO148PDB3
IO149PPB3
GFC1/IO147PPB3
VCCIB3
B6
IO14RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO21RSB0
B8
IO27RSB0
B9
IO32RSB0
IO47RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
IO150PDB3
IO08RSB0
IO153VDB3
IO152VDB3
VMV0
B10
B11
B12
B13
B14
B15
B16
C1
IO38RSB0
G2
IO42RSB0
G3
GBC1/IO55RSB0
GBB0/IO56RSB0
IO44RSB0
G4
G5
E2
G6
VCC
GBA2/IO60PDB1
IO60NDB1
E3
G7
GND
E4
G8
GND
IO154VDB3
IO155VDB3
IO11RSB0
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
IO07RSB0
E8
IO25RSB0
VCCIB1
4-56
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
G13
G14
G15
G16
H1
GCC1/IO67PPB1
IO64NPB1
IO73PDB1
IO73NDB1
GFB0/IO146NPB3
GFA0/IO145NDB3
GFB1/IO146PPB3
VCOMPLF
GFC0/IO147NPB3
VCC
K1
K2
GFC2/IO142PDB3
IO144NPB3
IO141PPB3
IO120RSB2
VCCIB3
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
K3
VCCIB2
K4
IO108RSB2
IO101RSB2
VCCIB2
K5
H2
K6
VCC
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
K9
GND
IO83RSB2
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO78UPB1
GDC1/IO77UDB1
IO75NDB1
H7
GND
VCC
H8
GND
VCCIB1
H9
GND
IO71NPB1
IO74RSB1
IO72NPB1
IO70NDB1
IO142NDB3
IO141NPB3
IO125RSB2
IO139RSB3
VCCIB3
IO140NDB3
IO138PPB3
GEC1/IO137PPB3
IO131RSB2
GNDQ
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO67NPB1
GCB1/IO68PPB1
GCA0/IO69NPB1
NC
N4
N5
L2
N6
GEA2/IO134RSB2
IO117RSB2
IO111RSB2
IO99RSB2
L3
N7
GCB0/IO68NPB1
GFA2/IO144PPB3
GFA1/IO145PDB3
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
IO94RSB2
J3
L7
VCC
IO87RSB2
J4
IO143NDB3
GFB2/IO143PDB3
VCC
L8
VCC
GNDQ
J5
L9
VCC
IO93RSB2
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO77VDB1
GDA1/IO79UDB1
GEB1/IO136PDB3
GEB0/IO136NDB3
VMV2
J8
GND
VCCIB1
J9
GND
GDB0/IO78VPB1
IO76VDB1
IO76UDB1
IO75PDB1
IO140PDB3
IO130RSB2
IO138NPB3
GEC0/IO137NPB3
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO71PPB1
GCA1/IO69PPB1
GCC2/IO72PPB1
NC
P4
IO129RSB2
IO128RSB2
IO122RSB2
IO115RSB2
IO110RSB2
P5
P6
P7
GCA2/IO70PDB1
P8
Revision 13
4-57
Package Pin Assignments
FG256
FG256
Pin Number A3P400 Function
Pin Number A3P400 Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO98RSB2
IO95RSB2
IO88RSB2
IO84RSB2
TCK
T13
T14
T15
T16
IO86RSB2
GDA2/IO80RSB2
TMS
GND
VPUMP
TRST
GDA0/IO79VDB1
GEA1/IO135PDB3
GEA0/IO135NDB3
IO127RSB2
GEC2/IO132RSB2
IO123RSB2
IO118RSB2
IO112RSB2
IO106RSB2
IO100RSB2
IO96RSB2
IO89RSB2
IO85RSB2
GDB2/IO81RSB2
TDI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
NC
TDO
GND
T2
IO126RSB2
GEB2/IO133RSB2
IO124RSB2
IO116RSB2
IO113RSB2
IO107RSB2
IO105RSB2
IO102RSB2
IO97RSB2
IO92RSB2
GDC2/IO82RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
4-58
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO11RSB0
C5
C6
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO31RSB0
VCCIB0
A3
C7
VCCIB0
A4
C8
VMV1
A5
C9
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
IO66PDB1
IO166NDB3
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
A6
IO16RSB0
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO18RSB0
A8
IO28RSB0
A9
IO34RSB0
A10
A11
A12
A13
A14
A15
A16
B1
IO37RSB0
F2
IO41RSB0
IO61NPB1
IO63PDB1
IO171NDB3
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
F3
IO43RSB0
F4
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
D5
F9
VCC
B2
D6
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
IO40RSB0
IO45RSB0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO03RSB0
IO13RSB0
D8
VCCIB1
B5
D9
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
B6
IO14RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B7
IO21RSB0
B8
IO27RSB0
B9
IO32RSB0
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
B10
B11
B12
B13
B14
B15
B16
C1
IO38RSB0
G2
IO42RSB0
G3
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
G4
G5
E2
G6
VCC
GBA2/IO60PDB1
IO60NDB1
E3
G7
GND
E4
G8
GND
IO173NDB3
IO174NDB3
VMV3
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
IO07RSB0
E8
IO25RSB0
VCCIB1
Revision 13
4-59
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
G13
G14
G15
G16
H1
GCC1/IO69PPB1
IO65NPB1
K1
K2
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV3
VCCIB2
IO75PDB1
K3
VCCIB2
IO75NDB1
K4
IO117RSB2
IO110RSB2
VCCIB2
GFB0/IO163NPB3
GFA0/IO162NDB3
GFB1/IO163PPB3
VCOMPLF
K5
H2
K6
VCC
H3
K7
GND
VCCIB2
H4
K8
GND
VMV2
H5
GFC0/IO164NPB3
VCC
K9
GND
IO94RSB2
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO87PPB1
GDC1/IO86PDB1
IO84NDB1
H7
GND
VCC
H8
GND
VCCIB1
H9
GND
IO73NPB1
IO80NPB1
IO74NPB1
IO72NDB1
IO159NDB3
IO156NPB3
IO151PPB3
IO158PSB3
VCCIB3
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
N4
N5
L2
N6
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
L3
N7
GCB0/IO70NPB1
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO160NDB3
GFB2/IO160PDB3
VCC
L8
VCC
GNDQ
J5
L9
VCC
IO92RSB2
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO86NDB1
GDA1/IO88PDB1
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
J8
GND
VCCIB1
J9
GND
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
P4
IO138RSB2
IO136RSB2
IO131RSB2
IO124RSB2
IO119RSB2
P5
P6
P7
GCA2/IO72PDB1
P8
4-60
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
Pin Number A3P600 Function
Pin Number A3P600 Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO107RSB2
IO104RSB2
IO97RSB2
VMV1
T13
T14
T15
T16
IO93RSB2
GDA2/IO89RSB2
TMS
GND
TCK
VPUMP
TRST
GDA0/IO88NDB1
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO96RSB2
GDB2/IO90RSB2
TDI
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO137RSB2
GEB2/IO142RSB2
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
GDC2/IO91RSB2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Revision 13
4-61
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GND
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
IO16RSB0
C7
C8
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
E13
E14
E15
E16
F1
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
IO217NDB3
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
A3
C9
A4
C10
C11
C12
C13
C14
C15
C16
D1
A5
A6
IO22RSB0
F2
A7
IO28RSB0
F3
A8
IO35RSB0
F4
A9
IO45RSB0
IO78NDB1
IO81NDB1
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
F5
A10
A11
A12
A13
A14
A15
A16
B1
IO50RSB0
F6
GND
IO55RSB0
F7
VCC
IO61RSB0
D2
F8
VCC
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
D3
F9
VCC
D4
F10
F11
F12
F13
F14
F15
F16
G1
VCC
D5
GND
D6
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO52RSB0
IO60RSB0
GNDQ
VCCIB1
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
D7
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
IO210PSB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
B2
D8
B3
D9
B4
GAB1/IO03RSB0
IO17RSB0
D10
D11
D12
D13
D14
D15
D16
E1
B5
B6
IO21RSB0
G2
B7
IO27RSB0
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NSB1
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
G3
B8
IO34RSB0
G4
B9
IO44RSB0
G5
B10
B11
B12
B13
B14
B15
B16
C1
IO51RSB0
G6
VCC
IO57RSB0
G7
GND
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
E2
G8
GND
E3
G9
GND
E4
G10
G11
G12
G13
G14
G15
G16
H1
GND
GBA2/IO78PDB1
IO81PDB1
E5
VCC
E6
VCCIB0
VCCIB1
IO224NDB3
IO225NDB3
VMV3
E7
VCCIB0
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
IO88NDB1
GFB0/IO208NPB3
GFA0/IO207NDB3
C2
E8
IO38RSB0
IO47RSB0
VCCIB0
C3
E9
C4
IO11RSB0
E10
E11
E12
C5
GAC0/IO04RSB0
GAC1/IO05RSB0
VCCIB0
C6
VMV1
H2
4-62
Revision 13
ProASIC3 Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
K9
K10
K11
K12
K13
K14
K15
K16
L1
GND
GND
M15
M16
N1
GDC1/IO111PDB1
IO107NDB1
IO194PSB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
VCC
VCCIB1
N2
GND
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
N3
GND
N4
GND
N5
GND
N6
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
VCC
N7
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
GFA2/IO206PSB3
GFA1/IO207PDB3
VCCPLF
L2
N8
L3
N9
L4
N10
N11
N12
N13
N14
N15
N16
P1
L5
L6
GND
L7
VCC
IO110PDB1
VJTAG
J2
L8
VCC
J3
L9
VCC
GDC0/IO111NDB1
GDA1/IO113PDB1
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
J4
IO205NDB3
GFB2/IO205PDB3
VCC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
VCC
J5
GND
J6
VCCIB1
P2
J7
GND
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
IO197NSB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
P3
J8
GND
P4
IO179RSB2
IO171RSB2
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
J9
GND
P5
J10
J11
J12
J13
J14
J15
J16
K1
GND
P6
VCC
P7
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PSB1
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
VCCIB2
VCCIB2
TCK
K2
IO147RSB2
IO136RSB2
VCCIB2
VPUMP
K3
TRST
K4
GDA0/IO113NDB1
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
K5
VCCIB2
K6
VCC
VMV2
R2
K7
GND
IO110NDB1
GDB1/IO112PPB1
R3
K8
GND
R4
Revision 13
4-63
Package Pin Assignments
FG256
Pin Number A3P1000 Function
R5
R6
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
GND
4-64
Revision 13
ProASIC3 Flash Family FPGAs
FG484
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-65
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
A1
A2
GND
GND
B15
B16
B17
B18
B19
B20
B21
B22
C1
NC
D7
D8
GAB0/IO02RSB0
IO16RSB0
IO17RSB0
IO22RSB0
IO28RSB0
IO34RSB0
IO37RSB0
IO41RSB0
IO43RSB0
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
NC
A3
VCCIB0
NC
NC
D9
A4
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
NC
NC
A6
IO15RSB0
IO18RSB0
NC
NC
A7
VCCIB1
A8
GND
A9
NC
VCCIB3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
IO23RSB0
IO29RSB0
IO35RSB0
IO36RSB0
NC
C2
NC
C3
NC
C4
NC
C5
GND
C6
NC
NC
NC
C7
NC
NC
IO50RSB0
IO51RSB0
NC
C8
VCC
NC
C9
VCC
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
NC
E2
NC
NC
NC
E3
GND
VCCIB0
GND
NC
E4
GAB2/IO154UDB3
GAA2/IO155UDB3
IO12RSB0
GAB1/IO03RSB0
IO13RSB0
IO14RSB0
IO21RSB0
IO27RSB0
IO32RSB0
IO38RSB0
IO42RSB0
GBC1/IO55RSB0
GBB0/IO56RSB0
IO44RSB0
GBA2/IO60PDB1
IO60NDB1
GND
NC
E5
GND
VCC
E6
GND
VCC
E7
B2
VCCIB3
NC
NC
E8
B3
NC
E9
B4
NC
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
NC
B6
NC
NC
B7
NC
NC
B8
NC
VCCIB1
B9
NC
NC
NC
B10
B11
B12
B13
B14
NC
D2
NC
D3
NC
NC
D4
GND
NC
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
NC
D6
4-66
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
E21
E22
F1
NC
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO40RSB0
IO46RSB0
GNDQ
J5
J6
IO149NPB3
IO09RSB0
IO152UDB3
VCCIB3
GND
NC
J7
F2
NC
IO47RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
NC
J8
F3
NC
J9
F4
IO154VDB3
IO155VDB3
IO11RSB0
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO45RSB0
GBC0/IO54RSB0
IO48RSB0
VMV0
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
F5
VCC
F6
VCC
F7
NC
VCC
F8
NC
GND
F9
NC
VCCIB1
IO62NDB1
IO49RSB0
IO64PPB1
IO66NDB1
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
H4
IO150PDB3
IO08RSB0
IO153VDB3
IO152VDB3
VMV0
H5
H6
H7
NC
H8
NC
H9
VCCIB0
VCCIB0
IO25RSB0
IO31RSB0
VCCIB0
VCCIB0
VMV1
NC
IO61NPB1
IO63PDB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
K2
NC
K3
NC
K4
IO148NDB3
IO148PDB3
IO149PPB3
GFC1/IO147PPB3
VCCIB3
VCC
NC
K5
NC
K6
NC
K7
G2
NC
GBC2/IO62PDB1
IO65RSB1
IO52RSB0
IO66PDB1
VCC
K8
G3
NC
K9
G4
IO151VDB3
IO151UDB3
GAC2/IO153UDB3
IO06RSB0
GNDQ
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
G5
GND
G6
GND
G7
NC
GND
G8
NC
VCC
G9
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
NC
VCCIB1
GCC1/IO67PPB1
IO64NPB1
IO73PDB1
G10
G11
G12
J2
NC
J3
NC
J4
IO150NDB3
Revision 13
4-67
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
K19
K20
K21
K22
L1
IO73NDB1
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
P3
P4
NC
IO142NDB3
IO141NPB3
IO125RSB2
IO139RSB3
VCCIB3
GND
NC
GND
NC
GND
P5
NC
VCC
GCB2/IO71PPB1
GCA1/IO69PPB1
GCC2/IO72PPB1
NC
P6
NC
P7
L2
NC
P8
L3
NC
GFB0/IO146NPB3
GFA0/IO145NDB3
GFB1/IO146PPB3
VCOMPLF
GFC0/IO147NPB3
VCC
P9
L4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
GCA2/IO70PDB1
NC
VCC
L6
VCC
L7
NC
VCC
L8
NC
GND
L9
NC
VCCIB1
GDB0/IO78VPB1
IO76VDB1
IO76UDB1
IO75PDB1
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
NC
GND
N3
NC
GND
N4
GFC2/IO142PDB3
IO144NPB3
IO141PPB3
IO120RSB2
VCCIB3
VCC
GND
N5
VCC
N6
GCC0/IO67NPB1
GCB1/IO68PPB1
GCA0/IO69NPB1
NC
N7
NC
N8
NC
N9
NC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
NC
GCB0/IO68NPB1
NC
GND
R3
VCC
GND
R4
IO140PDB3
IO130RSB2
IO138NPB3
GEC0/IO137NPB3
VMV3
NC
GND
R5
NC
VCC
R6
NC
VCCIB1
IO71NPB1
IO74RSB1
IO72NPB1
IO70NDB1
NC
R7
NC
R8
NC
R9
VCCIB2
VCCIB2
IO108RSB2
IO101RSB2
VCCIB2
VCCIB2
VMV2
GFA2/IO144PPB3
GFA1/IO145PDB3
VCCPLF
R10
R11
R12
R13
R14
R15
R16
IO143NDB3
GFB2/IO143PDB3
VCC
NC
NC
NC
GND
P2
NC
IO83RSB2
4-68
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P400 Function
Pin Number A3P400 Function
Pin Number A3P400 Function
R17
R18
R19
R20
R21
R22
T1
GDB1/IO78UPB1
GDC1/IO77UDB1
IO75NDB1
VCC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO122RSB2
IO115RSB2
IO110RSB2
IO98RSB2
IO95RSB2
IO88RSB2
IO84RSB2
TCK
W1
W2
NC
NC
W3
NC
W4
GND
NC
W5
IO126RSB2
GEB2/IO133RSB2
IO124RSB2
IO116RSB2
IO113RSB2
IO107RSB2
IO105RSB2
IO102RSB2
IO97RSB2
IO92RSB2
GDC2/IO82RSB2
IO86RSB2
GDA2/IO80RSB2
TMS
NC
W6
NC
W7
T2
NC
W8
T3
NC
VPUMP
W9
T4
IO140NDB3
IO138PPB3
GEC1/IO137PPB3
IO131RSB2
GNDQ
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO79VDB1
NC
T6
T7
NC
T8
NC
T9
GEA2/IO134RSB2
IO117RSB2
IO111RSB2
IO99RSB2
IO94RSB2
IO87RSB2
GNDQ
NC
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO135PDB3
GEA0/IO135NDB3
IO127RSB2
GEC2/IO132RSB2
IO123RSB2
IO118RSB2
IO112RSB2
IO106RSB2
IO100RSB2
IO96RSB2
IO89RSB2
IO85RSB2
GDB2/IO81RSB2
TDI
V5
GND
V6
NC
V7
NC
IO93RSB2
VJTAG
V8
NC
V9
VCCIB3
NC
GDC0/IO77VDB1
GDA1/IO79UDB1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
Y3
NC
Y4
NC
NC
Y5
GND
NC
Y6
NC
NC
Y7
NC
U2
NC
Y8
VCC
U3
NC
Y9
VCC
U4
GEB1/IO136PDB3
GEB0/IO136NDB3
VMV2
NC
Y10
Y11
Y12
Y13
Y14
NC
U5
TDO
NC
U6
GND
NC
U7
IO129RSB2
IO128RSB2
NC
NC
U8
NC
VCC
Revision 13
4-69
Package Pin Assignments
FG484
FG484
Pin Number A3P400 Function
Pin Number A3P400 Function
Y15
Y16
VCC
NC
AB7
AB8
IO119RSB2
IO114RSB2
IO109RSB2
NC
Y17
NC
AB9
Y18
GND
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y19
NC
Y20
NC
IO104RSB2
IO103RSB2
NC
Y21
NC
Y22
VCCIB1
GND
VCCIB3
NC
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AB2
AB3
AB4
AB5
AB6
NC
IO91RSB2
IO90RSB2
NC
NC
NC
NC
NC
VCCIB2
GND
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCIB1
GND
GND
GND
VCCIB2
NC
NC
IO121RSB2
4-70
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
A1
A2
GND
GND
B15
B16
B17
B18
B19
B20
B21
B22
C1
NC
D7
D8
GAB0/IO02RSB0
IO11RSB0
IO16RSB0
IO18RSB0
IO28RSB0
IO34RSB0
IO37RSB0
IO41RSB0
IO43RSB0
GBB1/IO57RSB0
GBA0/IO58RSB0
GBA1/IO59RSB0
GND
IO47RSB0
A3
VCCIB0
NC
IO49RSB0
D9
A4
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
NC
NC
A6
IO09RSB0
IO15RSB0
NC
NC
A7
VCCIB1
A8
GND
A9
NC
VCCIB3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
IO22RSB0
IO23RSB0
IO29RSB0
IO35RSB0
NC
C2
NC
C3
NC
C4
NC
C5
GND
C6
NC
NC
NC
C7
NC
NC
IO46RSB0
IO48RSB0
NC
C8
VCC
NC
C9
VCC
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
NC
E2
NC
NC
NC
E3
GND
VCCIB0
GND
NC
E4
GAB2/IO173PDB3
GAA2/IO174PDB3
GNDQ
NC
E5
GND
VCC
E6
GND
VCC
E7
GAB1/IO03RSB0
IO13RSB0
IO14RSB0
IO21RSB0
IO27RSB0
IO32RSB0
IO38RSB0
IO42RSB0
GBC1/IO55RSB0
GBB0/IO56RSB0
IO52RSB0
GBA2/IO60PDB1
IO60NDB1
GND
B2
VCCIB3
NC
NC
E8
B3
NC
E9
B4
NC
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
NC
B6
IO08RSB0
IO12RSB0
NC
NC
B7
NC
B8
VCCIB1
B9
NC
NC
NC
B10
B11
B12
B13
B14
IO17RSB0
NC
D2
D3
NC
NC
D4
GND
IO36RSB0
NC
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
D6
Revision 13
4-71
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
E21
E22
F1
NC
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO40RSB0
IO45RSB0
GNDQ
J5
J6
IO168NPB3
IO167PPB3
IO169PDB3
VCCIB3
GND
NC
J7
F2
NC
IO50RSB0
GBB2/IO61PPB1
IO53RSB0
IO63NDB1
NC
J8
F3
NC
J9
F4
IO173NDB3
IO174NDB3
VMV3
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
F5
VCC
F6
VCC
F7
IO07RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO20RSB0
IO24RSB0
IO33RSB0
IO39RSB0
IO44RSB0
GBC0/IO54RSB0
IO51RSB0
VMV0
NC
VCC
F8
NC
GND
F9
NC
VCCIB1
IO62NDB1
IO64NPB1
IO65PPB1
IO66NDB1
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
H4
IO166PDB3
IO167NPB3
IO172NDB3
IO169NDB3
VMV0
H5
H6
H7
IO68PDB1
IO68NDB1
IO157PDB3
IO157NDB3
NC
H8
H9
VCCIB0
VCCIB0
IO25RSB0
IO31RSB0
VCCIB0
VCCIB0
VMV1
IO61NPB1
IO63PDB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
K2
K3
K4
IO165NDB3
IO165PDB3
IO168PPB3
GFC1/IO164PPB3
VCCIB3
VCC
NC
K5
NC
K6
IO170NDB3
IO170PDB3
NC
K7
G2
GBC2/IO62PDB1
IO67PPB1
IO64PPB1
IO66PDB1
VCC
K8
G3
K9
G4
IO171NDB3
IO171PDB3
GAC2/IO172PDB3
IO06RSB0
GNDQ
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
G5
GND
G6
GND
G7
NC
GND
G8
NC
VCC
G9
IO10RSB0
IO19RSB0
IO26RSB0
IO30RSB0
NC
VCCIB1
GCC1/IO69PPB1
IO65NPB1
IO75PDB1
G10
G11
G12
J2
NC
J3
NC
J4
IO166NDB3
4-72
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
K19
K20
K21
K22
L1
IO75NDB1
NC
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
GND
P3
P4
IO153NDB3
IO159NDB3
IO156NPB3
IO151PPB3
IO158PPB3
VCCIB3
GND
IO76NDB1
IO76PDB1
NC
GND
P5
VCC
P6
GCB2/IO73PPB1
GCA1/IO71PPB1
GCC2/IO74PPB1
IO80PPB1
GCA2/IO72PDB1
IO79PPB1
IO78PPB1
NC
P7
L2
IO155PDB3
NC
P8
L3
P9
L4
GFB0/IO163NPB3
GFA0/IO162NDB3
GFB1/IO163PPB3
VCOMPLF
GFC0/IO164NPB3
VCC
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
VCC
L6
VCC
L7
VCC
L8
GND
L9
IO154NDB3
IO154PDB3
NC
VCCIB1
GDB0/IO87NPB1
IO85NDB1
IO85PDB1
IO84PDB1
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
GND
N3
GND
N4
GFC2/IO159PDB3
IO161NPB3
IO156PPB3
IO129RSB2
VCCIB3
GND
N5
VCC
N6
GCC0/IO69NPB1
GCB1/IO70PPB1
GCA0/IO71NPB1
IO67NPB1
GCB0/IO70NPB1
IO77PDB1
IO77NDB1
IO78NPB1
NC
N7
IO81PDB1
NC
N8
N9
VCC
NC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
NC
GND
R3
VCC
GND
R4
IO150PDB3
IO151NPB3
IO147NPB3
GEC0/IO146NPB3
VMV3
GND
R5
VCC
R6
VCCIB1
R7
IO155NDB3
IO158NPB3
GFA2/IO161PPB3
GFA1/IO162PDB3
VCCPLF
IO73NPB1
IO80NPB1
IO74NPB1
IO72NDB1
NC
R8
R9
VCCIB2
VCCIB2
IO117RSB2
IO110RSB2
VCCIB2
VCCIB2
VMV2
R10
R11
R12
R13
R14
R15
R16
IO160NDB3
GFB2/IO160PDB3
VCC
IO79NPB1
NC
NC
GND
P2
IO153PDB3
IO94RSB2
Revision 13
4-73
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P600 Function
Pin Number A3P600 Function
Pin Number A3P600 Function
R17
R18
R19
R20
R21
R22
T1
GDB1/IO87PPB1
GDC1/IO86PDB1
IO84NDB1
VCC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO131RSB2
IO124RSB2
IO119RSB2
IO107RSB2
IO104RSB2
IO97RSB2
VMV1
W1
W2
NC
IO148PDB3
NC
W3
W4
GND
IO81NDB1
IO82PDB1
IO152PDB3
IO152NDB3
NC
W5
IO137RSB2
GEB2/IO142RSB2
IO134RSB2
IO125RSB2
IO123RSB2
IO118RSB2
IO115RSB2
IO111RSB2
IO106RSB2
IO102RSB2
GDC2/IO91RSB2
IO93RSB2
GDA2/IO89RSB2
TMS
W6
W7
T2
TCK
W8
T3
VPUMP
W9
T4
IO150NDB3
IO147PPB3
GEC1/IO146PPB3
IO140RSB2
GNDQ
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO88NDB1
NC
T6
T7
IO83NDB1
NC
T8
T9
GEA2/IO143RSB2
IO126RSB2
IO120RSB2
IO108RSB2
IO103RSB2
IO99RSB2
GNDQ
NC
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO144PDB3
GEA0/IO144NDB3
IO139RSB2
GEC2/IO141RSB2
IO132RSB2
IO127RSB2
IO121RSB2
IO114RSB2
IO109RSB2
IO105RSB2
IO98RSB2
IO96RSB2
GDB2/IO90RSB2
TDI
V5
GND
V6
NC
V7
NC
IO92RSB2
VJTAG
V8
NC
V9
VCCIB3
IO148NDB3
NC
GDC0/IO86NDB1
GDA1/IO88PDB1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
Y3
Y4
NC
IO83PDB1
IO82NDB1
IO149PDB3
IO149NDB3
NC
Y5
GND
Y6
NC
Y7
NC
U2
Y8
VCC
U3
Y9
VCC
U4
GEB1/IO145PDB3
GEB0/IO145NDB3
VMV2
GNDQ
Y10
Y11
Y12
Y13
Y14
NC
U5
TDO
NC
U6
GND
NC
U7
IO138RSB2
IO136RSB2
NC
NC
U8
NC
VCC
4-74
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
Pin Number A3P600 Function
Pin Number A3P600 Function
Y15
Y16
VCC
NC
AB7
AB8
IO128RSB2
IO122RSB2
IO116RSB2
NC
Y17
NC
AB9
Y18
GND
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y19
NC
Y20
NC
IO113RSB2
IO112RSB2
NC
Y21
NC
Y22
VCCIB1
GND
VCCIB3
NC
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AB2
AB3
AB4
AB5
AB6
NC
IO100RSB2
IO95RSB2
NC
NC
NC
NC
IO135RSB2
IO133RSB2
NC
VCCIB2
GND
GND
NC
NC
NC
NC
NC
NC
NC
IO101RSB2
NC
NC
NC
NC
VCCIB1
GND
GND
GND
VCCIB2
NC
NC
IO130RSB2
Revision 13
4-75
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
A1
A2
GND
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO63RSB0
IO66RSB0
IO68RSB0
IO70RSB0
NC
D7
D8
GAB0/IO02RSB0
IO16RSB0
IO22RSB0
IO28RSB0
IO35RSB0
IO45RSB0
IO50RSB0
IO55RSB0
IO61RSB0
GBB1/IO75RSB0
GBA0/IO76RSB0
GBA1/IO77RSB0
GND
GND
A3
VCCIB0
D9
A4
IO07RSB0
IO09RSB0
IO13RSB0
IO18RSB0
IO20RSB0
IO26RSB0
IO32RSB0
IO40RSB0
IO41RSB0
IO53RSB0
IO59RSB0
IO64RSB0
IO65RSB0
IO67RSB0
IO69RSB0
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
A6
NC
A7
VCCIB1
GND
A8
A9
VCCIB3
IO220PDB3
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
C2
C3
C4
NC
C5
GND
C6
IO10RSB0
IO14RSB0
VCC
NC
C7
NC
C8
NC
C9
VCC
IO219NDB3
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
IO30RSB0
IO37RSB0
IO43RSB0
NC
E2
E3
GND
VCCIB0
E4
GAB2/IO224PDB3
GAA2/IO225PDB3
GNDQ
GND
E5
GND
VCC
E6
GND
VCC
E7
GAB1/IO03RSB0
IO17RSB0
IO21RSB0
IO27RSB0
IO34RSB0
IO44RSB0
IO51RSB0
IO57RSB0
GBC1/IO73RSB0
GBB0/IO74RSB0
IO71RSB0
GBA2/IO78PDB1
IO81PDB1
GND
B2
VCCIB3
NC
E8
B3
NC
NC
E9
B4
IO06RSB0
IO08RSB0
IO12RSB0
IO15RSB0
IO19RSB0
IO24RSB0
IO31RSB0
IO39RSB0
IO48RSB0
IO54RSB0
IO58RSB0
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
B6
NC
B7
NC
B8
VCCIB1
IO219PDB3
IO220NDB3
NC
B9
B10
B11
B12
B13
B14
D2
D3
D4
GND
D5
GAA0/IO00RSB0
GAA1/IO01RSB0
D6
4-76
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
E21
E22
F1
NC
IO84PDB1
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO52RSB0
IO60RSB0
GNDQ
J5
J6
IO218NDB3
IO216PDB3
IO216NDB3
VCCIB3
GND
J7
F2
IO215PDB3
IO215NDB3
IO224NDB3
IO225NDB3
VMV3
IO80NDB1
GBB2/IO79PDB1
IO79NDB1
IO82NPB1
IO85PDB1
IO85NDB1
NC
J8
F3
J9
F4
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
F5
VCC
F6
VCC
F7
IO11RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
IO25RSB0
IO36RSB0
IO42RSB0
IO49RSB0
IO56RSB0
GBC0/IO72RSB0
IO62RSB0
VMV0
VCC
F8
GND
F9
NC
VCCIB1
IO83NPB1
IO86NPB1
IO90PPB1
IO87NDB1
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
H4
IO217PDB3
IO218PDB3
IO221NDB3
IO221PDB3
VMV0
H5
H6
H7
IO89PDB1
IO89NDB1
IO211PDB3
IO211NDB3
NC
H8
H9
VCCIB0
IO78NDB1
IO81NDB1
IO82PPB1
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
VCCIB0
K2
IO38RSB0
IO47RSB0
VCCIB0
K3
K4
IO210PPB3
IO213NDB3
IO213PDB3
GFC1/IO209PPB3
VCCIB3
VCC
K5
IO84NDB1
IO214NDB3
IO214PDB3
NC
VCCIB0
K6
VMV1
K7
G2
GBC2/IO80PDB1
IO83PPB1
IO86PPB1
IO87PDB1
VCC
K8
G3
K9
G4
IO222NDB3
IO222PDB3
GAC2/IO223PDB3
IO223NDB3
GNDQ
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
G5
GND
G6
GND
G7
NC
GND
G8
NC
VCC
G9
IO23RSB0
IO29RSB0
IO33RSB0
IO46RSB0
IO212NDB3
IO212PDB3
NC
VCCIB1
GCC1/IO91PPB1
IO90NPB1
IO88PDB1
G10
G11
G12
J2
J3
J4
IO217NDB3
Revision 13
4-77
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
K19
K20
K21
K22
L1
IO88NDB1
IO94NPB1
IO98NDB1
IO98PDB1
NC
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
GND
P3
P4
IO199NDB3
IO202NDB3
IO202PDB3
IO196PPB3
IO193PPB3
VCCIB3
GND
P5
VCC
P6
GCB2/IO95PPB1
GCA1/IO93PPB1
GCC2/IO96PPB1
IO100PPB1
GCA2/IO94PPB1
IO101PPB1
IO99PPB1
NC
P7
L2
IO200PDB3
IO210NPB3
GFB0/IO208NPB3
GFA0/IO207NDB3
GFB1/IO208PPB3
VCOMPLF
GFC0/IO209NPB3
VCC
P8
L3
P9
GND
L4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
VCC
L6
VCC
L7
VCC
L8
GND
L9
IO201NDB3
IO201PDB3
NC
VCCIB1
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
GDB0/IO112NPB1
IO106NDB1
IO106PDB1
IO107PDB1
NC
GND
N3
GND
N4
GFC2/IO204PDB3
IO204NDB3
IO203NDB3
IO203PDB3
VCCIB3
GND
N5
VCC
N6
GCC0/IO91NPB1
GCB1/IO92PPB1
GCA0/IO93NPB1
IO96NPB1
GCB0/IO92NPB1
IO97PDB1
IO97NDB1
IO99NPB1
NC
N7
IO104PDB1
IO103NDB1
NC
N8
N9
VCC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
IO197PPB3
VCC
GND
R3
GND
R4
IO197NPB3
IO196NPB3
IO193NPB3
GEC0/IO190NPB3
VMV3
GND
R5
VCC
R6
VCCIB1
R7
IO200NDB3
IO206NDB3
GFA2/IO206PDB3
GFA1/IO207PDB3
VCCPLF
IO95NPB1
IO100NPB1
IO102NDB1
IO102PDB1
NC
R8
R9
VCCIB2
R10
R11
R12
R13
R14
R15
R16
VCCIB2
IO147RSB2
IO136RSB2
VCCIB2
IO205NDB3
GFB2/IO205PDB3
VCC
IO101NPB1
IO103PDB1
NC
VCCIB2
VMV2
GND
P2
IO199PDB3
IO110NDB1
4-78
Revision 13
ProASIC3 Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Pin Number A3P1000 Function
R17
R18
R19
R20
R21
R22
T1
GDB1/IO112PPB1
GDC1/IO111PDB1
IO107NDB1
VCC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO165RSB2
IO159RSB2
IO151RSB2
IO137RSB2
IO134RSB2
IO128RSB2
VMV1
W1
W2
NC
IO191PDB3
NC
W3
W4
GND
IO104NDB1
IO105PDB1
IO198PDB3
IO198NDB3
NC
W5
IO183RSB2
GEB2/IO186RSB2
IO172RSB2
IO170RSB2
IO164RSB2
IO158RSB2
IO153RSB2
IO142RSB2
IO135RSB2
IO130RSB2
GDC2/IO116RSB2
IO120RSB2
GDA2/IO114RSB2
TMS
W6
W7
T2
TCK
W8
T3
VPUMP
W9
T4
IO194PPB3
IO192PPB3
GEC1/IO190PPB3
IO192NPB3
GNDQ
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO113NDB1
NC
T6
T7
IO108NDB1
IO109PDB1
NC
T8
T9
GEA2/IO187RSB2
IO161RSB2
IO155RSB2
IO141RSB2
IO129RSB2
IO124RSB2
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO188PDB3
GEA0/IO188NDB3
IO184RSB2
GEC2/IO185RSB2
IO168RSB2
IO163RSB2
IO157RSB2
IO149RSB2
IO143RSB2
IO138RSB2
IO131RSB2
IO125RSB2
GDB2/IO115RSB2
TDI
V5
GND
V6
NC
V7
NC
IO110PDB1
VJTAG
V8
NC
V9
VCCIB3
GDC0/IO111NDB1
GDA1/IO113PDB1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
IO191NDB3
NC
Y3
Y4
IO182RSB2
GND
IO108PDB1
IO105NDB1
IO195PDB3
IO195NDB3
IO194NPB3
GEB1/IO189PDB3
GEB0/IO189NDB3
VMV2
Y5
Y6
IO177RSB2
IO174RSB2
VCC
Y7
U2
Y8
U3
Y9
VCC
U4
GNDQ
Y10
Y11
Y12
Y13
Y14
IO154RSB2
IO148RSB2
IO140RSB2
NC
U5
TDO
U6
GND
U7
IO179RSB2
IO171RSB2
NC
U8
IO109NDB1
VCC
Revision 13
4-79
Package Pin Assignments
FG484
FG484
Pin Number A3P1000 Function
Pin Number A3P1000 Function
Y15
Y16
VCC
NC
AB7
AB8
IO167RSB2
IO162RSB2
IO156RSB2
IO150RSB2
IO145RSB2
IO144RSB2
IO132RSB2
IO127RSB2
IO126RSB2
IO123RSB2
IO121RSB2
IO118RSB2
NC
Y17
NC
AB9
Y18
GND
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y19
NC
Y20
NC
Y21
NC
Y22
VCCIB1
GND
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AB2
AB3
AB4
AB5
AB6
VCCIB3
NC
IO181RSB2
IO178RSB2
IO175RSB2
IO169RSB2
IO166RSB2
IO160RSB2
IO152RSB2
IO146RSB2
IO139RSB2
IO133RSB2
NC
VCCIB2
GND
GND
NC
IO122RSB2
IO119RSB2
IO117RSB2
NC
NC
VCCIB1
GND
GND
GND
VCCIB2
IO180RSB2
IO176RSB2
IO173RSB2
4-80
Revision 13
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the ProASIC3 datasheet.
Revision
Changes
Page
Revision 13
(January 2013)
The "ProASIC3 Ordering Information" section has been updated to mention "Y" as
"Blank" mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104).
1-III
Added a note to Table 2-2 • Recommended Operating Conditions 1,2 (SAR 43644):
The programming temperature range supported is Tambient = 0°C to 85°C.
2-2
The note in Table 2-115 • ProASIC3 CCC/PLL Specification referring the reader to
SmartGen was revised to refer instead to the online help associated with the core
(SAR 42569).
2-89
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40284).
NA
1-1
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
Revision 12
The "Security" section was modified to clarify that Microsemi does not support
(September 2012) read-back of programmed data.
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.
2-1
2-2
See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to
Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating
Conditions 1,2 (SAR 38321).
Table 2-35 • Duration of Short Circuit Event Before Failure was revised to change
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37933).
2-30
2-67
In Table 2-93 • Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
28549).
Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write are new (SAR 28371).
2-98
3-1
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions" chapter: "Within the package, the VMV plane is
decoupled from the simultaneous switching noise originating from the output buffer
VCCI domain" and replaced with “Within the package, the VMV plane biases the
input stage of the I/Os in the I/O banks” (SAR 38321). The datasheet mentions that
"VMV pins must be connected to the corresponding VCCI pins" for an ESD
enhancement.
Revision 13
5-1
Datasheet Information
Revision
Changes
Page
Revision 11
(March 2012)
Note indicating that A3P015 is not recommended for new designs has been added.
The "Devices Not Recommended For New Designs" section is new (SAR 36760).
I to IV
The following sentence was removed from the "Advanced Architecture" section: "In
addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR
34687).
1-3
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
User's Guide (SAR 34734).
2-12
Figure 2-3 • Input Buffer Timing Model and Delays (example) has been modified for
the DIN waveform; the Rise and Fall time label has been changed to tDIN (35430).
2-15
2-31
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34883).
Added values for minimum pulse width and removed the FRMAX row from
Table 2-107 through Table 2-114 in the "Global Tree Timing Characteristics" section.
Use the software to determine the FRMAX for the device you are using (SARs
37279, 29269).
2-84
Revision 10
The "In-System Programming (ISP) and Security" section and "Security" section
I, 1-1
(September 2011) were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 32865).
The value of 34 I/Os for the QN48 package in A3P030 was added to the "I/Os Per
Package 1" section (SAR 33907).
II
The Y security option and Licensed DPA Logo were added to the "ProASIC3
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography
Research (SAR 32151).
III
The "Specifying I/O States During Programming" section is new (SAR 21281).
1-7
2-2
In Table 2-2 • Recommended Operating Conditions 1,2, VPUMP programming
voltage in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45" (SAR
30666). It was corrected in v2.0 of this datasheet in April 2007 but inadvertently
changed back to “3.0 to 3.6 V” in v1.4 in August 2009. The following changes were
made to Table 2-2 • Recommended Operating Conditions 1,2:
VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to
1.575" (SAR 33850).
For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were corrected.
The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value for 3.3 V Wide
Range is "2.7 to 3.6" (SAR 33848).
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings was
update to restore values to the correct columns. Previously the Slew Rate column
was missing and data were aligned incorrectly (SAR 34034).
2-23
The notes regarding drive strength in the "Summary of I/O Timing Characteristics – 2-21, 2-38
Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section
tables were revised for clarification. They now state that the minimum drive strength
for the default software configuration when run in wide range is ±100 µA. The drive
strength displayed in software is supported in normal range only. For a detailed I/V
curve, refer to the IBIS models (SAR 25700).
5-2
Revision 13
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Revision 10
(continued)
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-28 • I/O Output Buffer Maximum 2-25 to
Resistances1 through Table 2-30 • I/O Output Buffer Maximum Resistances1 was
replaced by "Same as regular 3.3 V" (SAR 33852).
2-27
2-27
The equations in the notes for Table 2-31 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 32470).
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-32 • I/O Short Currents IOSH/IOSL 2-28 to
through Table 2-34 • I/O Short Currents IOSH/IOSL was replaced by "Same as
regular 3.3 V LVCMOS" (SAR 33852).
2-30
In the "3.3 V LVCMOS Wide Range" section, values were added to Table 2-47 2-38 to
through Table 2-49 for IOSL and IOSH, replacing "TBD" (SAR 33852).
2-39
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916):
"It uses a 5 V–tolerant input buffer and push-pull output buffer."
2-46
The table notes were revised for Table 2-90 • LVDS Minimum and Maximum DC
Input and Output Levels (SAR 33859).
2-65
Values were added for FDDRIMAX and FDDOMAX in Table 2-102 • Input DDR 2-77, 2-79
Propagation Delays and Table 2-104 • Output DDR Propagation Delays (SAR
23919).
Table 2-115 • ProASIC3 CCC/PLL Specification was updated. A note was added to
indicate that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
25705).
2-89
The following figures were deleted (SAR 29991). Reference was made to a new
application note, Simultaneous Read-Write Operations in Dual-Port SRAM for
Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 21770).
Figure 2-34 • Write Access after Write onto Same Address
Figure 2-35 • Read Access after Write onto Same Address
Figure 2-35 • Read Access after Write onto Same Address
2-92,
2-94,
2-99,
2-101
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-38 • FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SARs 29991, 30510).
The "Pin Descriptions" chapter has been added (SAR 21642).
3-1
4-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 27395).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned
a revision number that increments each time the datasheet is revised. The
"ProASIC3 Device Status" table on page III indicates the status for each device in
the device family.
N/A
Revision 13
5-3
Datasheet Information
Revision
Changes
Page
Revision 9 (Oct 2009) The CS121 package was added to table under "Features and Benefits" section,
I – IV
the "I/Os Per Package 1" table, Table 1 • ProASIC3 FPGAs Package Sizes
Dimensions, "ProASIC3 Ordering Information", and the "Temperature Grade
Offerings" table.
Product Brief v1.3
"ProASIC3 Ordering Information" was revised to include the fact that some RoHS
compliant packages are halogen-free.
III
Packaging v1.5
The "CS121" figure and pin table for A3P060 are new.
4-15
N/A
Revision 8 (Aug 2009) All references to M7 devices (CoreMP7) and speed grade –F were removed from
this document.
Product Brief v1.2
Table 1-1 • I/O Standards Supported is new.
1-7
1-7
The "I/Os with Advanced I/O Standards" section was revised to add definitions of
hot-swap and cold-sparing.
DC and Switching
Characteristics v1.4
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
N/A
N/A
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
–F was removed from the datasheet. The speed grade is no longer supported.
The notes in Table 2-2 • Recommended Operating Conditions 1,2 were updated.
Table 2-4 • Overshoot and Undershoot Limits 1 was updated.
N/A
2-2
2-3
2-6
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
In Table 2-116 • RAM4K9, the following specifications were removed:
2-94
2-96
tWRO
tCCKH
In Table 2-117 • RAM512X18, the following specifications were removed:
tWRO
tCCKH
In the title of Table 2-74 • 1.8 V LVCMOS High Slew, VCCI had a typo. It was
changed from 3.0 V to 1.7 V.
2-57
I
Revision 7 (Feb 2009) The "Advanced I/O" section was revised to add a bullet regarding wide range
power supply voltage support.
Product Brief v1.1
The table under "Features and Benefits" section, was updated to include a value
for typical equivalent macrocells for A3P250.
I
The QN48 package was added to the following tables: the table under "Features
and Benefits" section, "I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes
Dimensions", and "Temperature Grade Offerings".
N/A
The number of singled-ended I/Os for QN68 was added to the "I/Os Per
Package 1" table.
The "Wide Range I/O Support" section is new.
1-7
4-1
4-5
Revision 6 (Dec 2008) The "QN48" section is new.
Packaging v1.4
The "QN68" pin table for A3P030 is new.
5-4
Revision 13
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Revision 5 (Aug 2008) TJ, Maximum Junction Temperature, was changed to 100° from 110º in the
2-5
"Thermal Characteristics" section and EQ 2. The calculated result of Maximum
Power Allowed has thus changed to 1.463 W from 1.951 W.
Characteristics v1.3
DC and Switching
Values for the A3P015 device were added to Table 2-7 • Quiescent Supply
Current Characteristics.
2-6
Values for the A3P015 device were added to Table 2-14 • Different Components 2-10, 2-11
Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14 was
removed. Table 2-15 • Different Components Contributing to the Static Power
Consumption in ProASIC3 Devices is new.
The "PLL Contribution—PPLL" section was updated to change the PPLL formula
from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT
2-13
.
Both fall and rise values were included for tDDRISUD and tDDRIHD in Table 2-102 •
Input DDR Propagation Delays.
2-77
Table 2-107 • A3P015 Global Resource is new.
2-85
2-89
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in Table 2-115 • ProASIC3 CCC/PLL Specification.
Revision 4 (Jun 2008) Table note references were added to Table 2-2 • Recommended Operating
2-2
2-3
Conditions 1,2, and the order of the table notes was changed.
DC and Switching
Characteristics v1.2
The title for Table 2-4 • Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os."
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
2-6
2-26
2-65
4-3
Table 2-29 • I/O Output Buffer Maximum Resistances 1 was revised to include
values for 3.3 V PCI/PCI-X.
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels was
updated.
Revision 3 (Jun 2008) Pin numbers were added to the "QN68" package diagram. Note 2 was added
below the diagram.
Packaging v1.3
The "QN132" package diagram was updated to include D1 to D4. In addition,
note 1 was changed from top view to bottom view, and note 2 is new.
4-6
Revision 2 (Feb 2008) This document was divided into two sections and given a version number, starting
N/A
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
Product Brief v1.0
This document was updated to include A3P015 device information. QN68 is a
new package that was added because it is offered in the A3P015. The following
sections were updated:
N/A
"Features and Benefits"
"ProASIC3 Ordering Information"
"Temperature Grade Offerings"
"ProASIC3 Product Family"
"A3P015 and A3P030" note
"Introduction and Overview"
Revision 13
5-5
Datasheet Information
Revision
Changes
Page
II
Revision 2 (cont’d)
The "ProASIC3 FPGAs Package Sizes Dimensions" table is new.
In the "ProASIC3 Ordering Information", the QN package measurements were
updated to include both 0.4 mm and 0.5 mm.
III
In the "General Description" section, the number of I/Os was updated from 288 to
300.
1-1
Packaging v1.2
The "QN68" section is new.
4-3
2-2
Revision 1 (Feb 2008) In Table 2-2 • Recommended Operating Conditions 1,2, TJ was listed in the
symbol column and was incorrect. It was corrected and changed to TA.
DC and Switching
Characteristics v1.1
In Table 2-3 • Flash Programming Limits – Retention, Storage and Operating
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
2-2
The "PLL Behavior at Brownout Condition" section is new.
2-3
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
2-13
In Table 2-21 • Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said TJ and it was corrected and changed to TA.
2-20
2-89
2-108
4-19
N/A
In Table 2-115 • ProASIC3 CCC/PLL Specification, the SCLK parameter and note
1 are new.
Table 2-125 • JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
Packaging v1.1
In the "VQ100" A3P030 pin table, the function of pin 63 was incorrect and
changed from IO39RSB0 to GDB0/IO38RSB0.
Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel has restarted the version numbers.
v2.2
(July 2007)
The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3
Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering
Information", "Temperature Grade Offerings", and "Speed Grade and
Temperature Grade Matrix".
i, ii, iii,
iii, iv
The words "ambient temperature" were added to the temperature range in the
"Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings",
and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
i
v2.1
(May 2007)
In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input
Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
i
In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and
A3P600 device I/Os were updated.
ii
Table 3-5 • Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
3-5
5-6
Revision 13
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
v2.0
In the "Packaging Tables", Ambient was deleted.
ii
(April 2007)
The timing characteristics tables were updated.
N/A
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
The "PLL Macro" section was updated to include power-up information.
Table 2-11 • ProASIC3 CCC/PLL Specification was updated.
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
2-15
2-29
2-18
2-21
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
The "RESET" section was updated with read and write information.
The "RESET" section was updated with read and write information.
2-25
2-25
2-28
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible
Standards.
2-29
2-34
2-64
2-40
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
2-50
2-51
The "VPUMP Programming Supply Voltage" section was updated.
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
V
JTAG was deleted from the "TCK Test Clock" section.
2-51
2-51
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
3-2
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os)1.
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
3-5
3-6
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
3-5
Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels 3-17 to 3-
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
17
Revision 13
5-7
Datasheet Information
Revision
Changes
Page
v2.0
Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings 3-20 to
(continued)
(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
3-20
3-9
Table 3-11 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3 Devices was updated.
Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3- 3-22 to
25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
3-22
Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
3-18
Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O 3-24 to
Short Currents IOSH/IOSL (Standard Plus) were updated.
3-26
The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-27
Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read 3-82 to
Access After Write onto Same Address, and Figure 3-35 • Write Access After
Read onto Same Address are new.
3-84
Figure 3-43 • Timing Diagram was updated.
3-96
iv
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
Notes were added to the package diagrams identifying if they were top or bottom
view.
N/A
The A3P030 "132-Pin QFN" table is new.
The A3P060 "132-Pin QFN" table is new.
The A3P125 "132-Pin QFN" table is new.
The A3P250 "132-Pin QFN" table is new.
The A3P030 "100-Pin VQFP" table is new.
4-2
4-4
4-6
4-8
4-11
ii
Advance v0.7
(January 2007)
In the "I/Os Per Package" table, the I/O numbers were added for A3P060,
A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.
Advance v0.6
(April 2006)
The term flow-through was changed to pass-through.
N/A
Table 1 was updated to include the QN132.
ii
ii
The "I/Os Per Package" table was updated with the QN132. The footnotes were
also updated. The A3P400-FG144 I/O count was updated.
"Automotive ProASIC3 Ordering Information" was updated with the QN132.
"Temperature Grade Offerings" was updated with the QN132.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
iii
iii
N/A
N/A
2-7
2-16
Figure 2-7 • Efficient Long-Line Resources was updated.
The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
2-24
2-21
The "SRAM and FIFO" section was updated.
5-8
Revision 13
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
2-25
2-25
2-25
2-27
2-28
Advance v0.6
(continued)
The "RESET" section was updated.
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
The "Introduction" of the "Advanced I/Os" section was updated.
The "I/O Banks" section is new. This section explains the following types of I/Os:
2-29
Advanced
Standard+
Standard
Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is
new. This table describes the standards listed above.
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 • VCCI Voltages and Compatible Standards
2-29
Table 2-13 • ProASIC3 I/O Features was updated.
2-30
2-32
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
2-64
2-64
2-41
2-30
Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3 Devices were updated.
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum
drive strength and high slew selected).
Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications
2-45
2-83
Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type
(A3P030 device)
Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.
Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated.
The "x" was updated in the "User I/O Naming Convention" section.
The "VCC Core Supply Voltage" pin description was updated.
2-84
2-84
2-48
2-50
2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
2-51
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
Revision 13
5-9
Datasheet Information
Revision
Changes
Page
Advance v0.6
(continued)
The "Programming" section was updated to include information concerning
serialization.
2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
2-54
"DC and Switching Characteristics" chapter was updated with new information.
The A3P060 "100-Pin VQFP" pin table was updated.
The A3P125 "100-Pin VQFP" pin table was updated.
The A3P060 "144-Pin TQFP" pin table was updated.
The A3P125 "144-Pin TQFP" pin table was updated.
The A3P125 "208-Pin PQFP" pin table was updated.
The A3P400 "208-Pin PQFP" pin table was updated.
The A3P060 "144-Pin FBGA" pin table was updated.
The A3P125 "144-Pin FBGA" pin table is new.
3-1
4-13
4-13
4-16
4-18
4-21
4-25
4-32
4-34
4-38
4-48
4-54
4-58
4-68
4-14
4-23
4-29
4-36
4-32
4-45
4-54
4-68
ii
The A3P400 "144-Pin FBGA" is new.
The A3P400 "256-Pin FBGA" was updated.
The A3P1000 "256-Pin FBGA" was updated.
The A3P400 "484-Pin FBGA" was updated.
The A3P1000 "484-Pin FBGA" was updated.
The A3P250 "100-Pin VQFP*" pin table was updated.
The A3P250 "208-Pin PQFP*" pin table was updated.
The A3P1000 "208-Pin PQFP*" pin table was updated.
The A3P250 "144-Pin FBGA*" pin table was updated.
The A3P1000 "144-Pin FBGA*" pin table was updated.
The A3P250 "256-Pin FBGA*" pin table was updated.
The A3P1000 "256-Pin FBGA*" pin table was updated.
The A3P1000 "484-Pin FBGA*" pin table was updated.
Advance v0.5
(November 2005)
The "I/Os Per Package" table was updated for the following devices and
packages:
Device
Package
VQ100
FG144
FG256
A3P250/M7ACP250
A3P250/M7ACP250
A3P1000
Advance v0.4
Advance v0.3
M7 device information is new.
N/A
ii
The I/O counts in the "I/Os Per Package" table were updated.
The "I/Os Per Package" table was updated.
M7 device information is new.
ii
N/A
2-16
Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include
the number or rows in each top or bottom spine.
EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.
2-24
5-10
Revision 13
ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Advance v0.3
The "PLL Macro" section was updated. EXTFB information was removed from
this section.
2-15
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-
11 • ProASIC3 CCC/PLL Specification
2-29
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
Table 2-13 • ProASIC3 I/O Features was updated.
The "Hot-Swap Support" section was updated.
2-28
2-30
2-33
2-34
2-35
2-64
The "Cold-Sparing Support" section was updated.
"Electrostatic Discharge (ESD) Protection" section was updated.
The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3 Devices was updated.
In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was
changed to VCCIB1.
2-97
2-50
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
The "JTAG Pins" section was updated.
"128-Bit AES Decryption" section was updated to include M7 device information.
Table 3-6 was updated.
2-51
2-53
3-6
Table 3-7 was updated.
3-6
In Table 3-11, PAC4 was updated.
3-93-8
3-20
3-27
Table 3-20 was updated.
The note in Table 3-32 was updated.
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-31 to 3-
73
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-85 to
3-90
FTCKMAX was updated in Table 3-110.
Figure 2-11 was updated.
3-97
2-9
Advance v0.2
The "Clock Resources (VersaNets)" section was updated.
The "VersaNet Global Networks and Spine Access" section was updated.
The "PLL Macro" section was updated.
Figure 2-27 was updated.
2-9
2-9
2-15
2-28
2-19
2-25
2-25
2-27
2-30
2-31
2-34
Figure 2-20 was updated.
Table 2-5 was updated.
Table 2-6 was updated.
The "FIFO Flag Usage Considerations" section was updated.
Table 2-13 was updated.
Figure 2-24 was updated.
The "Cold-Sparing Support" section is new.
Revision 13
5-11
Datasheet Information
Revision
Changes
Page
2-64
2-45
2-51
2-48
3-6
Advance v0.2,
(continued)
Table 2-43 was updated.
Table 2-18 was updated.
Pin descriptions in the "JTAG Pins" section were updated.
The "User I/O Naming Convention" section was updated.
Table 3-7 was updated.
The "Methodology" section was updated.
3-10
3-33,3-32
4-14
4-23
4-29
4-36
4-32
4-45
4-54
4-68
Table 3-40 and Table 3-39 were updated.
The A3P250 "100-Pin VQFP*" pin table was updated.
The A3P250 "208-Pin PQFP*" pin table was updated.
The A3P1000 "208-Pin PQFP*" pin table was updated.
The A3P250 "144-Pin FBGA*" pin table was updated.
The A3P1000 "144-Pin FBGA*" pin table was updated.
The A3P250 "256-Pin FBGA*" pin table was updated.
The A3P1000 "256-Pin FBGA*" pin table was updated.
The A3P1000 "484-Pin FBGA*" pin table was updated.
5-12
Revision 13
ProASIC3 Flash Family FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "ProASIC3 Device Status" table on page III, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
Revision 13
5-13
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