A3PE3000-2PQ208YPP [MICROSEMI]
ProASIC3E Flash Family FPGAs with Optional Soft ARM Support; ProASIC3E闪存系列FPGA具有可选的软ARM支持型号: | A3PE3000-2PQ208YPP |
厂家: | Microsemi |
描述: | ProASIC3E Flash Family FPGAs with Optional Soft ARM Support |
文件: | 总162页 (文件大小:8630K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 13
ProASIC3E Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
Pro (Professional) I/O
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
•
•
•
600 k to 3 Million System Gates
108 to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
•
•
•
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
On-Chip User Nonvolatile Memory
•
1 kbit of FlashROM with Synchronous Interfacing
High Performance
•
•
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC 3E Family
In-System Programming (ISP) and Security
®
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
Clock Conditioning Circuit (CCC) and PLL
®
•
FlashLock Designed to Secure FPGA Contents
•
•
Six CCC Blocks, Each with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
Low Power
•
•
•
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
High-Performance Routing Hierarchy
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
•
•
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous Operation
up to 350 MHz
ARM® Processor Support in ProASIC3E FPGAs
•
M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
Table 1-1 • ProASIC3E Product Family
ProASIC3E Devices
A3PE600
A3PE1500
A3PE3000
1
Cortex-M1 Devices
M1A3PE1500
M1A3PE3000
System Gates
600,000
13,824
108
24
1,500,000
3,000,000
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
38,400
270
60
75,264
504
112
1
FlashROM Kbits
1
1
Secure (AES) ISP
Yes
6
Yes
6
Yes
6
2
CCCs with Integrated PLLs
3
VersaNet Globals
18
18
18
I/O Banks
8
8
8
Maximum User I/Os
270
444
620
Package Pins
PQFP
FBGA
PQ208
FG256, FG484
PQ208
FG484, FG676
PQ208
FG324, FG484, FG896
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. The PQ208 package supports six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.
January 2013
I
© 2013 Microsemi Corporation
ProASIC3E Flash Family FPGAs
1
I/Os Per Package
ProASIC3E Devices
Cortex-M1 Devices 2
A3PE600
A3PE1500 3
M1A3PE1500
I/O Types
A3PE3000 3
M1A3PE3000
Package
PQ208
FG256
FG324
FG484
FG676
FG896
Notes:
147
165
–
65
79
–
147
65
–
147
65
–
–
–
–
–
221
341
–
110
168
–
270
–
135
–
280
444
–
139
222
–
–
–
620
310
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric User’s
Guide to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G"
in the part number.
Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions
Package
PQ208
28 × 28
784
FG256
17 × 17
289
FG324
19 × 19
361
FG484
23 × 23
529
FG676
27 × 27
729
FG896
31 × 31
961
Length × Width (mm\mm)
Nominal Area (mm2)
Pitch (mm)
0.5
1.0
1.0
1.0
1.0
1.0
Height (mm)
3.40
1.60
1.63
2.23
2.23
2.23
ProASIC3E Device Status
ProASIC3E Devices
Status
M1 ProASIC3E Devices
Status
A3PE600
Production
Production
Production
A3PE1500
A3PE3000
M1A3PE1500
M1A3PE3000
Production
Production
II
Revision 13
ProASIC3E Flash Family FPGAs
ProASIC3E Ordering Information
_
A3PE3000
1
FG
896
I
Y
G
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
=
PQ Plastic Quad Flat Pack (0.5 mm pitch)
=
FG Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3E Devices
A3PE600 = 600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
ProASIC3E Devices with Cortex-M1
M1A3PE1500
M1A3PE3000
=
=
1,500,000 System Gates
3,000,000 System Gates
Revision 13
III
ProASIC3E Flash Family FPGAs
Temperature Grade Offerings
Package
Cortex-M1 Devices
PQ208
A3PE600
A3PE1500
A3PE3000
M1A3PE1500
M1A3PE3000
C, I
C, I
–
C, I
–
C, I
–
FG256
FG324
–
C, I
C, I
–
FG484
C, I
–
C, I
C, I
–
FG676
FG896
–
C, I
Note: C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
Std.
–1
–2
C 1
I 2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
IV
Revision 13
ProASIC3E Flash Family FPGAs
Table of Contents
ProASIC3E Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3E DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Pin Descriptions and Packaging
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Package Pin Assignments
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Revision 13
V
1 – ProASIC3E Device Family Overview
General Description
ProASIC3E, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E
devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3E is
reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable
designers to create high-density systems using existing ASIC or FPGA design flows and tools.
ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices have
up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620
user I/Os.
Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have
Microsemi ordering numbers that begin with M1A3PE.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3E devices allow all functionality to be Instant On; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The ProASIC3E family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the ProASIC3E family a cost-effective ASIC replacement
solution, especially for applications in the consumer, networking/ communications, computing, and
avionics markets.
Security
The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead, advantages
that only an FPGA with nonvolatile flash programming can offer.
ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level
of protection in the FPGA industry for programmed intellectual property and configuration data. In
addition, all FlashROM data in ProASIC3E devices can be encrypted prior to loading, using the industry-
leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the
National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.
ProASIC3E devices have a built-in AES decryption engine and a flash-based AES key that make them
the most comprehensive programmable logic device security solution available today. ProASIC3E
devices with AES-based security provide a high level of protection for secure, remote field updates over
public networks such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
with industry-standard security, making remote ISP possible. A ProASIC3E device provides the best
available security for programmable logic designs.
Revision 13
1-1
ProASIC3E Device Family Overview
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based ProASIC3E devices support Level 0 of the Instant On classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The Instant On
feature of flash-based ProASIC3E devices greatly simplifies total system design and reduces total
system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these
purposes in a system. In addition, glitches and brownouts in system power will not corrupt the
ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be
reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3E devices simplify total system design and reduce cost and
design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3E devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
1-2
Revision 13
ProASIC3E Flash Family FPGAs
Advanced Architecture
The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on
page 3):
•
•
•
•
•
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Pro I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are
connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Pro I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
User Nonvolatile
Charge Pumps
ISP AES Decryption
FlashROM
Figure 1-1 • ProASIC3E Device Architecture Overview
Revision 13
1-3
ProASIC3E Device Family Overview
VersaTiles
The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core
tiles. The ProASIC3E VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-2 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-2 • VersaTile Configurations
User Nonvolatile FlashROM
ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks, as in security keys stored in the FlashROM for a
user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The ProASIC3E development software solutions, Libero® System-on-Chip (SoC) and Designer, have
extensive support for the FlashROM. One such feature is auto-generation of sequential programming
files for applications requiring a unique serial number in each part. Another feature allows the inclusion of
static data for system version control. Data for the FlashROM can be generated quickly and easily using
Libero SoC and Designer software tools. Comprehensive programming file support is also included to
allow for easy programming of large numbers of parts with differing FlashROM contents.
1-4
Revision 13
ProASIC3E Flash Family FPGAs
SRAM and FIFO
ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit port and
read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port
(ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of
the ProASIC3E family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208
package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
•
•
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used
•
•
•
•
Maximum acquisition time = 300 µs
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC
)
Global Clocking
ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
Revision 13
1-5
ProASIC3E Device Family Overview
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,
differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two
per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is
subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8
to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given
VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that
reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
•
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-3 on page 1-7).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
1-6
Revision 13
ProASIC3E Flash Family FPGAs
Figure 1-3 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
I/O States during programming are saved to the ADB and resulting programming files after
completing programming file generation.
Revision 13
1-7
2 – ProASIC3E DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this
document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
V
VJTAG
–0.3 to 3.75
VPUMP Programming voltage
–0.3 to 3.75
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
–0.3 to 3.75
VCCI 2
VMV 2
VI
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 to 3.75
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
3
TSTG
Storage temperature
Junction temperature
–65 to +150
+125
°C
°C
3
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-3 on page 2-2.
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 13
2-1
ProASIC3E DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 1
Symbol
TA
Parameter
Commercial
0 to +70
Industrial
–40 to +85
–40 to +100
1.425 to 1.575
1.4 to 3.6
Units
°C
°C
V
Ambient temperature
Junction temperature
TJ
0 to +85
VCC
1.5 V DC core supply voltage
JTAG DC voltage
1.425 to 1.575
1.4 to 3.6
VJTAG
VPUMP
V
Programming voltage
Programming Mode2
Operation3
3.15 to 3.45
0 to 3.6
3.15 to 3.45
0 to 3.6
V
V
VCCPLL
Analog power supply (PLL)
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.425 to 1.575
1.7 to 1.9
V
VCCI and VMV 4 1.5 V DC supply voltage
V
1.8 V DC supply voltage
V
2.5 V DC supply voltage
2.3 to 2.7
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
3.0 to 3.6
V
3.0 V DC supply voltage5
2.7 to 3.6
2.7 to 3.6
V
LVDS/B-LVDS/M-LVDS differential I/O
LVPECL differential I/O
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
V
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. The programming temperature range supported is T = 0°C to 85°C.
ambient
3. VPUMP can be left floating during normal operation (not programming mode).
4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-13 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.
VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
5. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature 1
Programming Program Retention
Maximum Storage
Maximum Operating Junction
Temperature TJ (°C) 2
Product Grade
Commercial
Industrial
Cycles
(biased/unbiased) Temperature TSTG (°C) 2
500
20 years
20 years
110
110
100
100
500
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or
Undershoot Duration
Maximum Overshoot/
Undershoot2
VCCI and VMV
as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC®3E device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4.
There are five regions to consider during power-up.
ProASIC3E I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Revision 13
2-3
ProASIC3E DC and Switching Characteristics
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper
power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed
brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on
page 2-4 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3E FPGA Fabric User’s Guide for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
(except differential
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Activation trip point:
V
= 0.85 V ± 0.25 V
a
Deactivation trip point:
= 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
V
d
VCCI
Activation trip point:
= 0.9 V ± 0.3 V
Min VCCI datasheet specification
V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
a
Deactivation trip point:
= 0.8 V ± 0.3 V
V
d
Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Revision 13
ProASIC3E Flash Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because dynamic and static power consumption cause the
chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction
temperature is 110°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for an 896-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 110C – 70C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 5.88 W
ja(C/W)
13.6C/W
EQ 2
Table 2-5 • Package Thermal Resistivities
ja
Package Type
Pin Count
jc
8.0
3.8
Still Air
26.1
200 ft./min.
500 ft./min.
20.8
Units
Plastic Quad Flat Package (PQFP)
208
208
22.5
13.3
C/W
C/W
Plastic Quad Flat Package (PQFP) with
embedded heat spreader
16.2
11.9
Fine Pitch Ball Grid Array (FBGA)
256
484
676
896
3.8
3.2
3.2
2.4
26.9
20.5
16.4
13.6
22.8
17.0
13.0
10.4
21.5
15.9
12.0
9.4
C/W
C/W
C/W
C/W
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to TJ = 70°C, VCC = 1.425 V)
Junction Temperature (°C)
Array Voltage
VCC (V)
–40°C
0°C
0.92
0.88
0.85
25°C
0.95
0.90
0.87
70°C
1.00
0.95
0.92
85°C
1.02
0.97
0.93
100°C
1.425
0.87
1.04
0.98
0.95
1.500
0.83
1.575
0.80
Revision 13
2-5
ProASIC3E DC and Switching Characteristics
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 • Quiescent Supply Current Characteristics
A3PE600
A3PE1500
12 mA
A3PE3000
25 mA
Typical (25°C)
5 mA
30 mA
45 mA
Maximum (Commercial)
Maximum (Industrial)
Notes:
70 mA
150 mA
225 mA
105 mA
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in
Table 2-8 and Table 2-9 on page 2-7.
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O
leakage.
Power per I/O Pin
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VMV
(V)
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3 V LVTTL/LVCMOS Wide Range3
3.3 V LVTTL/LVCMOS Wide Range – Schmitt trigger3
2.5 V LVCMOS
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
3.3
3.3
3.3
3.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
17.39
25.51
16.34
24.49
5.76
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
7.16
2.72
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
3.3 V PCI
2.80
2.08
2.00
18.82
20.12
18.82
20.12
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
3.3
2.5
3.3
2.5
2.90
2.13
2.81
2.57
8.23
4.78
4.14
3.71
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
2-6
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)
VMV
(V)
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
HSTL (I)
1.5
1.5
2.5
2.5
3.3
3.3
0.17
0.17
1.38
1.38
3.21
3.21
2.03
2.03
4.48
4.48
9.26
9.26
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS/B-LVDS/M-LVDS
LVPECL
2.5
3.3
2.26
5.71
1.50
2.17
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
1
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
CLOAD
(pF)
VCCI
(V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS Wide Range4
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
35
35
35
35
35
10
10
3.3
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
–
474.70
474.70
270.73
151.78
104.55
204.61
204.61
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
10
10
10
10
20
20
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
–
–
24.08
13.52
24.10
13.54
26.22
27.22
105.56
116.60
2.5 V GTL
3.3 V GTL+
–
2.5 V GTL+
–
HSTL (I)
7.08
13.88
16.69
25.91
HSTL (II)
SSTL2 (I)
SSTL2 (II)
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13
2-7
ProASIC3E DC and Switching Characteristics
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings (continued)
CLOAD
(pF)
VCCI
(V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
SSTL3 (I)
30
30
3.3
3.3
26.02
42.21
114.87
131.76
SSTL3 (II)
Differential
LVDS/B-LVDS/M-LVDS
LVPECL
–
–
2.5
3.3
7.70
89.62
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Power Consumption of Various Internal Resources
Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Device-Specific Dynamic Contributions
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
A3PE600
12.77
A3PE1500
16.21
3.06
A3PE3000
19.7
PAC2
1.85
4.16
PAC3
0.88
PAC4
Clock contribution of a VersaTile used as a sequential
module
0.12
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a sequential
module
0.07
0.29
0.29
0.70
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
module
PAC8
Average contribution of a routing net
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
See Table 2-8 on page 2-6.
See Table 2-9 on page 2-7
25.00
PAC10
PAC11
Average contribution of a RAM block during a read
operation
PAC12
Average contribution of a RAM block during a write
operation
30.00
PAC13
PAC14
Static PLL contribution
2.55 mW
2.60
Dynamic contribution for PLL
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
calculator or SmartPower in Libero SoC.
2-8
Revision 13
ProASIC3E Flash Family FPGAs
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on
page 2-11.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-12 on
page 2-11.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-12 on page 2-11. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
P
STAT
PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
User's Guide.
NROW is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric
User's Guide.
F
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
N
S-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-11.
F
CLK is the global clock signal frequency.
Revision 13
2-9
ProASIC3E DC and Switching Characteristics
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-11.
F
CLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-11.
F
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12 on
page 2-11.
F
WRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12 on
page 2-11.
PLL Contribution—P
PLL
PPLL = PAC13 + PAC14 * FCLKOUT
FCLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
2-10
Revision 13
ProASIC3E Flash Family FPGAs
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
•
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock
frequency.
•
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
1
2
10%
Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
1
2
3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
Revision 13
2-11
ProASIC3E DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL
tPD = 0.56 ns
t
PD = 0.49 ns
tDP = 1.36 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
tDP = 2.74 ns
tPD = 0.87 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
tDP = 2.39 ns
t
PY = 1.22 ns
tPD = 0.51 ns
LVPECL
D
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
t
t
ICLKQ = 0.24 ns
ISUD = 0.26 ns
t
DP = 3.30 ns
t
PD = 0.47 ns
Input LVTTL/LVCMOS
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
tPY = 0.90 ns
Y
D
Q
D
Q
D
Q
GTL+ 3.3V
DP = 1.53 ns
I/O Module
(Non-Registered)
tPD = 0.47 ns
t
t
t
CLKQ = 0.55 ns
SUD = 0.43 ns
t
CLKQ = 0.55 ns
t
CLKQ = 0.59 ns
LVDS,
BLVDS,
M-LVDS
tSUD = 0.43 ns
tSUD = 0.31 ns
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
tPY = 1.36 ns
t
PY = 0.90 ns
tPY = 0.90 ns
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V
2-12
Revision 13
ProASIC3E Flash Family FPGAs
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VCC
PAD
VIL
50%
50%
Y
tPY
tPY
(F)
GND
(R)
tPYS
(F)
tPYS
(R)
VCC
50%
50%
DIN
tDIN
(R)
GND
tDIN
(F)
Figure 2-3 • Input Buffer Timing Model and Delays (example)
Revision 13
2-13
ProASIC3E DC and Switching Characteristics
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
(R)
tDOUT
(F)
VCC
50%
50%
VCC
D
0 V
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
VOL
Vtrip
tDP
(R)
tDP
(F)
Figure 2-4 • Output Buffer Model and Delays (example)
2-14
Revision 13
ProASIC3E Flash Family FPGAs
t
EOUT
D
Q
CLK
t
, t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
CLK
D
t
= MAX(t
(r), t (f))
EOUT
I/O Interface
EOUT
EOUT
VCC
D
E
VCC
50%
t
50%
t
EOUT (F)
EOUT (R)
VCC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
HZ
VCCI
90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
E
VCC
50%
50%
50%
t
t
EOUT (F)
EOUT (R)
VCC
50%
EOUT
PAD
50%
VOH
t
ZHS
t
ZLS
Vtrip
Vtrip
VOL
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
Revision 13
2-15
ProASIC3E DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions
IOL3 IOH3
Equivalent
Software
Default
VIL
VIH
VOL
VOH
Drive
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Slew
Rate
I/O Standard Strength Option1
mA mA
3.3 V LVTTL / 12 mA
3.3 V
LVCMOS
12 mA High –0.3
12 mA High –0.3
12 mA High –0.3
0.8
2
3.6
3.6
3.6
0.4
2.4
12 12
3.3 V
100 µA
0.8
0.7
2
0.2
VCCI – 0.2 0.1 0.1
LVCMOS
Wide Range
2.5 V
LVCMOS
12 mA
12 mA
12 mA
1.7
0.7
1.7
12 12
1.8 V
LVCMOS
12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45
VCCI – 0.45 12 12
1.5 V
12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12
LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
Per PCI Specification
Per PCI-X Specification
20 mA2
20 mA2
35 mA
33 mA
8 mA
20 mA2 High –0.3 VREF – 0.05 VREF + 0.05 3.6
20 mA2 High –0.3 VREF – 0.05 VREF + 0.05 3.6
35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6
33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6
0.4
0.4
–
20 20
20 20
35 35
33 33
–
0.6
–
0.6
–
8 mA
High –0.3 VREF – 0.1 VREF + 0.1 3.6
0.4
VCCI – 0.4
8
8
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
15 mA2
15 mA
18 mA
14 mA
21 mA
15 mA2 High –0.3 VREF – 0.1 VREF + 0.1 3.6
15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6
18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6
14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6
21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6
0.4
0.54
0.35
0.7
VCCI – 0.4 15 15
VCCI – 0.62 15 15
VCCI – 0.43 18 18
VCCI – 1.1 14 14
VCCI – 0.9 21 21
0.5
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Output drive strength is below JEDEC specification.
3. Currents are measured at 85°C junction temperature.
4. Output Slew Rates can be extracted from IBIS Models, located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2-16
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-14 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL3
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IIH4
µA
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
IIL3
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
IIH4
µA
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <
VIL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI.
Input current is larger when operating outside recommended ranges.
Revision 13
2-17
ProASIC3E DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-15 • Summary of AC Measuring Points
Input Reference Voltage Board Termination Measuring Trip Point
Standard
3.3 LVTTL
LVCMOS
(VREF_TYP)
Voltage (VTT_REF)
(Vtrip)
V
/
3.3
V
–
–
1.4 V
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
–
–
–
–
–
–
–
–
–
–
1.4 V
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF))
3.3 V PCI-X
–
–
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
VREF
VREF
VREF
VREF
VREF
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
LVPECL
–
–
Table 2-16 • I/O AC Parameter Definitions
Parameter
Definition
Data to Pad delay through the Output Buffer
tDP
tPY
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
tDOUT
tEOUT
tDIN
tPYS
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—High to Z
tZH
Enable to Pad delay through the Output Buffer—Z to High
tLZ
Enable to Pad delay through the Output Buffer—Low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
2-18
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Equivalent
Software
Drive
Default
Strength
Drive
(mA)
Strength
Option)1
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
12
12
12
High 35
High 35
–
–
0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79
3.3 V LVCMOS 100 µA
Wide Range2
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12
12
12
12
12
12
–
High 35
High 35
High 35
–
–
–
0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
Per PCI
spec
High 10 25 3 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V PCI-X
Per PCI-X
spec
–
High 10 253 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
20 4
20 4
35
–
–
–
–
–
–
–
–
–
–
–
High 10
High 10
High 10
High 10
High 20
High 20
High 30
High 30
High 30
High 30
25 0.45 1.55 0.03 2.19
25 0.45 1.59 0.03 1.83
25 0.45 1.53 0.03 1.19
25 0.45 1.65 0.03 1.13
50 0.49 2.37 0.03 1.59
25 0.49 2.26 0.03 1.59
50 0.49 1.59 0.03 1.00
25 0.49 1.62 0.03 1.00
50 0.49 1.72 0.03 0.93
25 0.49 1.54 0.03 0.93
–
–
–
–
–
–
–
–
–
–
–
0.32 1.52 1.55
0.32 1.61 1.59
0.32 1.56 1.53
0.32 1.68 1.57
0.32 2.42 2.35
0.32 2.30 2.03
0.32 1.62 1.38
0.32 1.65 1.32
0.32 1.75 1.37
0.32 1.57 1.25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.19 3.22
3.28 3.26
3.23 3.20
3.35 3.24
4.09 4.02
3.97 3.70
3.29 3.05
3.32 2.99
3.42 3.04
3.24 2.92
33
8
HSTL (II)
15 4
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
15
18
14
21
LVDS/B-LVDS/
M-LVDS
24
High
–
–
0.49 1.40 0.03 1.36
–
–
–
–
–
LVPECL
24
–
High
–
–
0.49 1.36 0.03 1.22
–
–
–
–
–
–
–
–
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3V wide range as specified in the JESD8b specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-37 for
connectivity. This resistor is not required during normal operation.
4. Output drive strength is below JEDEC specification.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5..
Revision 13
2-19
ProASIC3E DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-18 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min. Max. Units
Input capacitance
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
pF
pF
CINCLK
Input capacitance on the clock pin
Table 2-19 • I/O Output Buffer Maximum Resistances1
Standard
Drive Strength
4 mA
RPULL-DOWN ()2
RPULL-UP ()3
3.3 V LVTTL / 3.3 V LVCMOS
100
50
25
17
11
300
150
75
8 mA
12 mA
16 mA
50
24 mA
33
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
100
50
200
100
50
25
20
40
11
22
1.8 V LVCMOS
200
100
50
225
112
56
50
56
20
22
20
22
1.5 V LVCMOS
3.3 V PCI/PCI-X
200
100
67
224
112
75
33
37
33
37
Per PCI/PCI-X
specification
25
75
3.3 V GTL
2.5 V GTL
Notes:
20 mA 4
20 mA 4
11
14
–
–
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2.
3.
R
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. Output drive strength is below JEDEC specification.
2-20
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-19 • I/O Output Buffer Maximum Resistances1 (continued)
Standard
3.3 V GTL+
2.5 V GTL+
HSTL (I)
Drive Strength
35 mA
R
PULL-DOWN ()2
RPULL-UP ()3
12
15
50
25
27
13
44
18
–
33 mA
–
8 mA
50
25
31
15
69
32
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
15 mA 4
15 mA
18 mA
14 mA
21 mA
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2.
3.
R
R
= (VOLspec) / IOLspec
(PULL-DOWN-MAX)
= (VCCImax – VOHspec) / IOHspec
(PULL-UP-MAX)
4. Output drive strength is below JEDEC specification.
Table 2-20 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R((WEAK PULL-UP)
R(WEAK PULL-DOWN)
()
()
VCCI
Min.
Max.
45 k
45 k
Min.
10 k
10 k
Max.
45 k
45 k
3.3 V
10 k
10 k
3.3 V (Wide
Range I/Os)
2.5 V
1.8 V
1.5 V
Notes:
11 k
18 k
19 k
55 k
70 k
90 k
12 k
17 k
19 k
74 k
110 k
140 k
1.
2.
R
R
= (VCCImax – VOHspec) / I
(WEAK PULL-UP-MAX)
(WEAK PULL-UP-MIN)
(WEAK PULL-DOWN-MIN)
= (VOLspec) / I
(WEAK PULL-DOWN-MAX)
Revision 13
2-21
ProASIC3E DC and Switching Characteristics
Table 2-21 • I/O Short Currents IOSH/IOSL
Drive Strength
4 mA
IOSH (mA)*
IOSL (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
25
51
27
54
8 mA
12 mA
103
132
268
109
127
181
16 mA
24 mA
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
100 µA
Same as regular
3.3 V LVCMOS
Same as regular
3.3 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16
32
65
83
169
9
18
37
74
87
124
11
1.8 V LVCMOS
17
35
45
91
91
13
25
32
66
66
22
44
51
74
74
16
33
39
55
55
1.5 V LVCMOS
Notes:
1. T = 100°C
J
2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength
selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range as specified in the JESD8b specification.
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-22 • Duration of Short Circuit Event Before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
6 months
2-22
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-23 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
240 mV
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
140 mV
80 mV
60 mV
Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Rise/Fall Time
Input Buffer
(min.)
Input Rise/Fall Time (max.)
10 ns *
Reliability
LVTTL/LVCMOS
(Schmitt trigger disabled)
No requirement
20 years
(110°C)
LVTTL/LVCMOS
(Schmitt trigger enabled)
No requirement No requirement, but input noise 20 years
voltage cannot exceed Schmitt (110°C)
hysteresis.
HSTL/SSTL/GTL
No requirement
10 ns *
10 years
(100°C)
LVDS/B-LVDS/M-LVDS/
LVPECL
No requirement
10 ns *
10 years
(100°C)
Note: *For clock signals and similar edge-generating signals, refer to the "ProASIC3/E SSO and Pin
Placement Guidelines" chapter of the ProASIC3E FPGA Fabric User’s Guide. The maximum input
rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the
rise time and fall time of input buffers can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends
signal integrity evaluation/characterization of the system to ensure that there is no excessive noise
coupling into input signals.
Revision 13
2-23
ProASIC3E DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Table 2-25 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.,
V
Max.
V
Max.
V
Max.
mA3
Max.
mA3
Drive Strength
4 mA
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
4
8
4
8
27
54
25
51
8 mA
12 mA
12 12
16 16
24 24
109
127
181
103
132
268
16 mA
24 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-6 • AC Loading
Table 2-26 • 3.3 V LVTTL / 3.3 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
C
LOAD (pF)
0
3.3
1.4
–
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
2-24
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive
Speed
Strength
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.66 7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.56 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73
0.49 5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67
0.66 5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41
0.56 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30
0.49 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53
0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97
0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08
0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46
0.66 3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76
0.56 2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90
0.49 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30
0.66 3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50
0.56 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68
0.49 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11
7.60
6.67
6.38
5.43
4.76
5.11
4.34
3.81
4.84
4.12
3.62
4.39
3.74
3.28
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive
Speed
Strength Grade tDOUT
tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.36 0.04 1.02 1.33 0.36
8.22 0.03 0.90 1.17 0.32
7.86 0.04 1.20 1.57 0.43
6.69 0.04 1.02 1.33 0.36
5.87 0.03 0.90 1.17 0.32
6.03 0.04 1.20 1.57 0.43
5.13 0.04 1.02 1.33 0.36
4.50 0.03 0.90 1.17 0.32
5.62 0.04 1.20 1.57 0.43
4.78 0.04 1.02 1.33 0.36
4.20 0.03 0.90 1.17 0.32
5.24 0.04 1.20 1.57 0.43
4.46 0.04 1.02 1.33 0.36
3.92 0.03 0.90 1.17 0.32
9.54
8.37
8.01
6.81
5.98
6.14
5.22
4.58
5.72
4.87
4.27
5.34
4.54
3.99
7.70 2.29 2.08 11.44 9.60
6.76 2.01 1.82 10.04 8.43
6.44 3.04 3.06 10.24 8.68
–2
8 mA
Std.
–1
5.48 2.58 2.61 8.71
4.81 2.27 2.29 7.65
5.02 3.28 3.47 8.37
4.27 2.79 2.95 7.12
3.75 2.45 2.59 6.25
4.72 3.32 3.58 7.96
4.02 2.83 3.04 6.77
3.53 2.48 2.67 5.94
4.69 3.39 3.96 7.58
3.99 2.88 3.37 6.44
3.50 2.53 2.96 5.66
7.38
6.48
7.26
6.17
5.42
6.96
5.92
5.20
6.93
5.89
5.17
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-25
ProASIC3E DC and Switching Characteristics
3.3 V LVCMOS Wide Range
Table 2-29 • Minimum and Maximum DC Input and Output Levels
3.3 V
LVCMOS
Wide
Range
Equivalent
Software
Default
Drive
VIL
VIH
Max.
VOL
VOH
IOL IOH IOSL
IOSH IIL2 IIH3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Min.
V
Max.
Max.
Strength Option1
V
µA µA mA4
mA4 µA5 µA5
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
2 mA
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
0.2 VDD – 0.2 100 100
27
27
54
54
25
25
10 10
10 10
10 10
10 10
10 10
10 10
10 10
6 mA
51
8 mA
51
12 mA
16 mA
24 mA
0.2 VDD – 0.2 100 100 109
0.2 VDD – 0.2 100 100 127
0.2 VDD – 0.2 100 100 181
103
132
268
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-7 • AC Loading
Table 2-30 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
C
LOAD (pF)
0
3.3
1.4
–
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
2-26
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-31 • 3.3 V LVCMOS Wide Range High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Strength Option1
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
4 mA
8 mA
Std. 0.66 12.19 0.04 1.83 2.38 0.43 12.19 10.17 4.16 4.00 15.58 13.57 ns
–1
–2
0.56 10.37 0.04 1.55 2.02 0.36 10.37 8.66 3.54 3.41 13.26 11.54 ns
0.49 9.10 0.03 1.36 1.78 0.32 9.10 7.60 3.11 2.99 11.64 10.13 ns
Std. 0.66 7.85 0.04 1.83 2.38 0.43 7.85 6.29 4.71 4.97 11.24 9.68
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–1
–2
0.56 6.68 0.04 1.55 2.02 0.36 6.68 5.35 4.01 4.22 9.57 8.24
0.49 5.86 0.03 1.36 1.78 0.32 5.86 4.70 3.52 3.71 8.40 7.23
12 mA
16 mA
24 mA
Std. 0.66 5.67 0.04 1.83 2.38 0.43 5.67 4.36 5.06 5.59 9.07 7.75
–1
–2
0.56 4.82 0.04 1.55 2.02 0.36 4.82 3.71 4.31 4.75 7.71 6.59
0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79
Std. 0.66 5.35 0.04 1.83 2.38 0.43 5.35 3.96 5.15 5.76 8.75 7.35
–1
–2
0.56 4.55 0.04 1.55 2.02 0.36 4.55 3.36 4.38 4.90 7.44 6.25
0.49 4.00 0.03 1.36 1.78 0.32 4.00 2.95 3.85 4.30 6.53 5.49
Std. 0.66 4.96 0.04 1.83 2.38 0.43 4.96 3.27 5.23 6.38 8.35 6.67
–1
–2
0.56 4.22 0.04 1.55 2.02 0.36 4.22 2.78 4.45 5.43 7.11 5.67
0.49 3.70 0.03 1.36 1.78 0.32 3.70 2.44 3.91 4.76 6.24 4.98
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-27
ProASIC3E DC and Switching Characteristics
Table 2-32 • 3.3 V LVCMOS Wide Range Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Equivalent
Software
Default
Drive
Drive
Strength
Speed
Strength Option1
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH tLZ tHZ tZLS tZHS Units
100 µA
100 µA
100µA
100 µA
100 µA
Notes:
4 mA
8 mA
Std. 0.66 17.02 0.04 1.83 2.38 0.43 17.02 13.74 4.16 3.78 20.42 17.14 ns
–1
–2
0.56 14.48 0.04 1.55 2.02 0.36 14.48 11.69 3.54 3.21 17.37 14.58 ns
0.49 12.71 0.03 1.36 1.78 0.32 12.71 10.26 3.11 2.82 15.25 12.80 ns
Std. 0.66 12.16 0.04 1.83 2.38 0.43 12.16 9.78 4.70 4.74 15.55 13.17 ns
–1
–2
0.56 10.34 0.04 1.55 2.02 0.36 10.34 8.32 4.00 4.03 13.23 11.20 ns
0.49 9.08 0.03 1.36 1.78 0.32 9.08 7.30 3.51 3.54 11.61 9.84 ns
12 mA
16 mA
24 mA
Std. 0.66 9.32 0.04 1.83 2.38 0.43 9.32 7.62 5.06 5.36 12.71 11.02 ns
–1
–2
0.56 7.93 0.04 1.55 2.02 0.36 7.93 6.48 4.31 4.56 10.81 9.37
0.49 6.96 0.03 1.36 1.78 0.32 6.96 5.69 3.78 4.00 9.49 8.23
ns
ns
Std. 0.66 8.69 0.04 1.83 2.38 0.43 8.69 7.17 5.14 5.53 12.08 10.57 ns
–1
–2
0.56 7.39 0.04 1.55 2.02 0.36 7.39 6.10 4.37 4.71 10.28 8.99
0.49 6.49 0.03 1.36 1.78 0.32 6.49 5.36 3.83 4.13 9.02 7.89
ns
ns
Std. 0.66 8.11 0.04 1.83 2.38 0.43 8.11 7.13 5.23 6.13 11.50 10.52 ns
–1
–2
0.56 6.90 0.04 1.55 2.02 0.36 6.90 6.06 4.45 5.21 9.78 8.95
0.49 6.05 0.03 1.36 1.78 0.32 6.05 5.32 3.91 4.57 8.59 7.86
ns
ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-28
Revision 13
ProASIC3E Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-33 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH IOL IOH
Min.
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.,
V
Max.
mA3
Max.
mA3
V
mA mA
µA4 µA4
10 10
10 10
10 10
10 10
10 10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
4
8
4
8
18
37
16
32
8 mA
12 mA
16 mA
24 mA
Notes:
12 12
16 16
24 24
74
65
87
83
124
169
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-8 • AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
C
LOAD (pF)
0
2.5
1.2
–
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Revision 13
2-29
ProASIC3E DC and Switching Characteristics
Timing Characteristics
Table 2-35 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Speed
Strength Grade tDOUT tZHS Units
Drive
tDP
tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82
6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74
5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50
4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38
3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60
3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05
3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15
2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52
3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83
3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96
2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35
3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56
2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73
2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15
9.40
8.25
7.51
6.38
5.61
5.73
4.87
4.28
5.35
4.55
4.00
4.72
4.01
3.52
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-30
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-36 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive
Speed
Strength Grade tDOUT
tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
–1
0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85
0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.96 0.03 1.13 1.24 0.32
8.73 0.04 1.51 1.66 0.43
7.43 0.04 1.29 1.41 0.36
6.52 0.03 1.13 1.24 0.32
6.77 0.04 1.51 1.66 0.43
5.76 0.04 1.29 1.41 0.36
5.06 0.03 1.13 1.24 0.32
6.31 0.04 1.51 1.66 0.43
5.37 0.04 1.29 1.41 0.36
4.71 0.03 1.13 1.24 0.32
5.93 0.04 1.51 1.66 0.43
5.05 0.04 1.29 1.41 0.36
4.43 0.03 1.13 1.24 0.32
9.13
8.89
7.57
6.64
6.90
5.87
5.15
6.42
5.46
4.80
6.04
5.14
4.51
8.67 2.03 1.64 10.80 10.34
8.01 3.10 2.93 11.13 10.25
8 mA
Std.
–1
6.82 2.64 2.49 9.47
5.98 2.32 2.19 8.31
6.11 3.37 3.39 9.14
5.20 2.86 2.89 7.77
4.56 2.51 2.53 6.82
5.73 3.42 3.52 8.66
4.87 2.91 3.00 7.37
4.28 2.56 2.63 6.47
5.70 3.49 4.00 8.28
4.85 2.97 3.40 7.04
4.26 2.61 2.99 6.18
8.72
7.65
8.34
7.10
6.23
7.96
6.77
5.95
7.94
6.75
5.93
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-31
ProASIC3E DC and Switching Characteristics
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-37 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
mA mA
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
Max.
mA3
µA4 µA4
10 10
10 10
10 10
10 10
10 10
10 10
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
6
8
11
22
44
51
74
74
9
4 mA
17
35
45
91
91
6 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6
8 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
3.6
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12 12
0.45 VCCI – 0.45 16 16
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-9 • AC Loading
Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
C
LOAD (pF)
0
1.8
0.9
–
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
2-32
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-39 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive
Speed
Strength Grade tDOUT
tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.66 12.10 0.04 1.45 1.91 0.43
0.56 10.30 0.04 1.23 1.62 0.36
9.59 12.10 2.78 1.64 11.83 14.34
8.16 10.30 2.37 1.39 10.06 12.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.04 0.03 1.08 1.42 0.32
7.05 0.04 1.45 1.91 0.43
6.00 0.04 1.23 1.62 0.36
5.27 0.03 1.08 1.42 0.32
4.52 0.04 1.45 1.91 0.43
3.85 0.04 1.23 1.62 0.36
3.38 0.03 1.08 1.42 0.32
4.12 0.04 1.45 1.91 0.43
3.51 0.04 1.23 1.62 0.36
3.08 0.03 1.08 1.42 0.32
3.80 0.04 1.45 1.91 0.43
3.23 0.04 1.23 1.62 0.36
2.83 0.03 1.08 1.42 0.32
3.80 0.04 1.45 1.91 0.43
3.23 0.04 1.23 1.62 0.36
2.83 0.03 1.08 1.42 0.32
7.16
6.20
5.28
4.63
4.47
3.80
3.33
4.20
3.57
3.14
3.87
3.29
2.89
3.87
3.29
2.89
9.04 2.08 1.22 8.83 10.71
4 mA
Std.
–1
7.05 3.25 2.86 8.44
6.00 2.76 2.44 7.18
5.27 2.43 2.14 6.30
4.52 3.57 3.47 6.70
3.85 3.04 2.95 5.70
3.38 2.66 2.59 5.00
3.99 3.63 3.62 6.43
3.40 3.09 3.08 5.47
2.98 2.71 2.71 4.81
3.09 3.73 4.24 6.10
2.63 3.18 3.60 5.19
2.31 2.79 3.16 4.56
3.09 3.73 4.24 6.10
2.63 3.18 3.60 5.19
2.31 2.79 3.16 4.56
9.29
7.90
6.94
6.76
5.75
5.05
6.23
5.30
4.65
5.32
4.53
3.98
5.32
4.53
3.98
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
Notes:
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-33
ProASIC3E DC and Switching Characteristics
Table 2-40 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Speed
Strength Grade tDOUT tZHS Units
Drive
tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07
0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37
0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50
0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
Std.
–1
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.69 0.04 1.23 1.62 0.36
8.51 0.03 1.08 1.42 0.32
8.97 0.04 1.45 1.91 0.43
7.63 0.04 1.23 1.62 0.36
6.70 0.03 1.08 1.42 0.32
8.35 0.04 1.45 1.91 0.43
7.10 0.04 1.23 1.62 0.36
6.24 0.03 1.08 1.42 0.32
7.94 0.04 1.45 1.91 0.43
6.75 0.04 1.23 1.62 0.36
5.93 0.03 1.08 1.42 0.32
7.94 0.04 1.45 1.91 0.43
6.75 0.04 1.23 1.62 0.36
5.93 0.03 1.08 1.42 0.32
9.87
8.66
9.14
7.77
6.82
8.50
7.23
6.35
8.09
6.88
6.04
8.09
6.88
6.04
9.15 2.77 2.36 11.77 11.05
8.03 2.43 2.07 10.33 9.70
8.10 3.57 3.36 11.37 10.33
–2
Std.
–1
6.89 3.04 2.86 9.67
6.05 2.66 2.51 8.49
8.79
7.72
–2
Std.
–1
7.59 3.64 3.52 10.74 9.82
6.45 3.10 3.00 9.14
5.66 2.72 2.63 8.02
8.35
7.33
–2
Std.
–1
7.56 3.74 4.11 10.32 9.80
6.43 3.18 3.49 8.78
5.65 2.79 3.07 7.71
8.33
7.32
–2
Std.
–1
7.56 3.74 4.11 10.32 9.80
6.43 3.18 3.49 8.78
5.65 2.79 3.07 7.71
8.33
7.32
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-34
Revision 13
ProASIC3E Flash Family FPGAs
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-41 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Max. Max.
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
mA mA mA3
mA3 µA4 µA4
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
–0.3 0.30 * VCCI 0.7 * VCCI 3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
6
8
16
33
39
55
55
13
25
32
66
66
10 10
10 10
10 10
10 10
10 10
0.25 * VCCI 0.75 * VCCI 12 12
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
R to VCCI for tLZ / tZL / tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ / tZH / tZHS
Test Point
35 pF
Enable Path
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
Figure 2-10 • AC Loading
Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
C
LOAD (pF)
0
1.5
0.75
–
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Revision 13
2-35
ProASIC3E DC and Switching Characteristics
Timing Characteristics
Table 2-43 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Speed
Strength Grade tDOUT tZHS Units
Drive
tDP
tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08
6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09
5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45
4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34
4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56
4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13
4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06
3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32
4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74
3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73
3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03
4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74
3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73
3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03
9.16
8.04
7.65
6.50
5.71
6.98
5.94
5.21
5.86
4.98
4.37
5.86
4.98
4.37
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-44 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive
Speed
Strength Grade tDOUT
tDP
tDIN tPY tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37
0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08
0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48
0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
Std.
–1
0.56
0.49
9.55 0.04 1.44 1.82 0.36
8.39 0.03 1.27 1.60 0.32
9.73
8.54
8.39 3.21 2.86 11.63 10.29
7.37 2.81 2.51 10.21 9.04
–2
Std.
–1
0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48
0.56
0.49
8.89 0.04 1.44 1.82 0.36
7.81 0.03 1.27 1.60 0.32
9.06
7.95
7.86 3.27 3.02 10.96 9.76
6.90 2.87 2.65 9.62 8.57
–2
Std.
–1
0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47
0.56
0.49
8.52 0.04 1.44 1.82 0.36
7.48 0.03 1.27 1.60 0.32
8.68
7.62
7.85 3.38 3.59 10.58 9.75
6.89 2.97 3.15 9.29 8.56
–2
Std.
–1
0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47
0.56
0.49
8.52 0.04 1.44 1.82 0.36
7.48 0.03 1.27 1.60 0.32
8.68
7.62
7.85 3.38 3.59 10.58 9.75
6.89 2.97 3.15 9.29 8.56
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-36
Revision 13
ProASIC3E Flash Family FPGAs
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
Table 2-45 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA3
Max.
mA3
Drive Strength
Per PCI specification
Notes:
mA mA
µA4 µA4
Per PCI curves
10 10
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
path characterization are described in Figure 2-11.
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
R to VCCI for tDP (F)
R to GND for tDP (R)
R = 25
Test Point
Datapath
R = 1 k
Test Point
Enable Path
10 pF for tZH / tZHS / tZL / tZLS
10 pF for tHZ / tLZ
Figure 2-11 • AC Loading
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
described in Table 2-46.
Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–
10
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-47 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed
Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tPYS
1.67
1.42
1.25
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
ns
Std.
–1
2.81
2.39
2.09
1.05
0.89
0.78
2.86
2.43
2.13
2.00
1.70
1.49
3.28
2.79
2.45
3.61
3.07
2.70
5.09 4.23
4.33 3.60
3.80 3.16
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-37
ProASIC3E DC and Switching Characteristics
Voltage-Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 2-48 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL
VIL
VIH
VOL
VOH IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
20 mA3
–0.3 VREF – 0.05 VREF + 0.05
3.6
0.4
–
20 20
181
268
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-12 • AC Loading
Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-50 • 3.3 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed
Grade
Std.
–1
tDOUT
0.60
0.51
0.45
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.27
3.63
3.19
tZHS
4.31
3.67
3.22
Units
ns
2.08
1.77
1.55
2.93
2.50
2.19
2.04
1.73
1.52
2.08
1.77
1.55
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-38
Revision 13
ProASIC3E Flash Family FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-51 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.,
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
20 mA3
–0.3 VREF – 0.05 VREF + 0.05
3.6
0.4
–
20 20
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-13 • AC Loading
Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.05
VREF + 0.05
0.8
0.8
1.2
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-53 • 2.5 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V VREF = 0.8 V
Speed
Grade
Std.
–1
tDOUT
0.60
0.51
0.45
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.40
3.74
3.28
tZHS
4.36
3.71
3.26
Units
ns
2.13
1.81
1.59
2.46
2.09
1.83
2.16
1.84
1.61
2.13
1.81
1.59
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-39
ProASIC3E DC and Switching Characteristics
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 2-54 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
35 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.6
–
35 35
181
268
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-14 • AC Loading
Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-56 • 3.3 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.0 V
Speed
Grade
Std.
–1
tDOUT
0.60
0.51
0.45
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.33
3.68
3.23
tZHS
4.29
3.65
3.20
Units
ns
2.06
1.75
1.53
1.59
1.35
1.19
2.09
1.78
1.56
2.06
1.75
1.53
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-40
Revision 13
ProASIC3E Flash Family FPGAs
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
mA1
Max.
mA1
mA mA
µA2 µA2
33 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.6
–
33 33
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-15 • AC Loading
Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
10
VREF – 0.1
VREF + 0.1
1.0
1.0
1.5
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-59 • 2.5 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
Speed
Grade
Std.
–1
tDOUT
0.60
0.51
0.45
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.48
3.81
3.35
tZHS
4.34
3.69
3.24
Units
ns
2.21
1.88
1.65
1.51
1.29
1.13
2.25
1.91
1.68
2.10
1.79
1.57
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-41
ProASIC3E DC and Switching Characteristics
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-60 • Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA1
mA mA mA1
µA2 µA2
8 mA
–0.3 VREF – 0.1 VREF + 0.1 3.6
0.4
VCCI – 0.4
8
8
39
32
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
HSTL
Class I
50
Test Point
20 pF
Figure 2-16 • AC Loading
Table 2-61 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring Point*
Input Low (V)
Input High (V)
(V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-62 • HSTL Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = .4 V, VREF = 0.75 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.47
4.66
4.09
tZHS
5.38
4.58
4.02
Units
ns
3.18
2.70
2.37
2.12
1.81
1.59
3.24
2.75
2.42
3.14
2.67
2.35
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-42
Revision 13
ProASIC3E Flash Family FPGAs
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-63 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
Max.
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max. Max.,
Min.
V
Max.
V
V
mA mA mA1
mA1 µA2 µA2
15 mA3
–0.3 VREF – 0.1 VREF + 0.1 3.6
0.4 VCCI – 0.4 15 15
55
66
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
HSTL
Class II
25
Test Point
20 pF
Figure 2-17 • AC Loading
Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.75
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-65 • HSTL Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.32
4.52
3.97
tZHS
4.95
4.21
3.70
Units
3.02
2.57
2.26
2.12
1.81
1.59
3.08
2.62
2.30
2.71
2.31
2.03
ns
ns
ns
–2
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-43
ProASIC3E DC and Switching Characteristics
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-66 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA1
mA1 µA2 µA2
15 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.54 VCCI – 0.62 15 15
87
83
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class I
50
Test Point
25
30 pF
Figure 2-18 • AC Loading
Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
30
VREF – 0.2
VREF + 0.2
1.25
1.25
1.25
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-68 • SSTL 2 Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.40
3.74
3.29
tZHS
4.08
3.47
3.05
Units
ns
2.13
1.81
1.59
1.33
1.14
1.00
2.17
1.84
1.62
1.85
1.57
1.38
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-44
Revision 13
ProASIC3E Flash Family FPGAs
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-69 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
Max.
IIL IIH
Drive
Strength
Min.
V
Max.
Min.
V
Max.
V
Max.
V
Min.
V
Max.
V
mA mA mA1
mA1 µA2 µA2
18 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.35 VCCI – 0.43 18 18
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class II
25
Test Point
25
30 pF
Figure 2-19 • AC Loading
Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
30
VREF – 0.2
VREF + 0.2
1.25
1.25
1.25
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-71 • SSTL 2 Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
2.17
1.84
1.62
tPY
tEOUT
1.33
1.14
1.00
tZL
tZH
tLZ
tHZ
tZLS
tZHS
4.44
3.78
3.32
Units
ns
0.66
0.56
0.49
0.04
0.04
0.03
0.43
0.36
0.32
2.21
1.88
1.65
1.77
1.51
1.32
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-45
ProASIC3E DC and Switching Characteristics
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-72 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
Max.
IOSH IIL IIH
Drive
Strength
Min.
V
Max.
Min.
V
Max.
V
Max.
V
Min.
V
Max.
V
mA mA
mA1
mA1 µA2 µA2
14 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.7
VCCI – 1.1 14 14
54
51
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class I
50
Test Point
25
30 pF
Figure 2-20 • AC Loading
Table 2-73 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
30
VREF – 0.2
VREF + 0.2
1.5
1.5
1.485
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-74 • SSTL3 Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.59
3.90
3.42
tZHS
4.07
3.46
3.04
Units
ns
2.31
1.96
1.72
1.25
1.06
0.93
2.35
2.00
1.75
1.84
1.56
1.37
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-46
Revision 13
ProASIC3E Flash Family FPGAs
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-75 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V
Max.
Max.
mA mA mA1
mA1 µA2 µA2
21 mA
–0.3 VREF – 0.2 VREF + 0.2
3.6
0.5
VCCI – 0.9 21 21
109
103
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class II
25
Test Point
25
30 pF
Figure 2-21 • AC Loading
Table 2-76 • AC Waveforms, Measuring Points, and Capacitive Loads
Measuring
Input Low (V)
Input High (V)
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
C
LOAD (pF)
30
VREF – 0.2
VREF + 0.2
1.5
1.5
1.485
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-77 • SSTL3 Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
Speed
Grade
Std.
–1
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
4.34
3.69
3.24
tZHS
3.91
3.32
2.92
Units
ns
2.07
1.76
1.54
1.25
1.06
0.93
2.10
1.79
1.57
1.67
1.42
1.25
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-47
ProASIC3E DC and Switching Characteristics
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Designer software when the user
instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional
I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-22. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
N
165
165
Z0 = 50
140
Z0 = 50
INBUF_LVDS
+
–
100
N
Figure 2-22 • LVDS Circuit Diagram and Board-Level Implementation
2-48
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
2.5
Max.
2.625
1.25
1.6
Units
V
VOL
Output Low Voltage
1.075
1.425
0.91
0.91
V
VOH
Output High Voltage
1.25
0.65
0.65
0
V
IOL1
Output Lower Current
1.16
1.16
2.925
10
mA
mA
V
IOH1
Output High Current
VI
Input Voltage
IIH2
Input High Leakage Current
Input Low Leakage Current
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage 2
µA
µA
mV
V
IIL2
10
VODIFF
VOCM
VICM
VIDIFF
Notes:
250
1.125
0.05
100
350
1.25
1.25
350
450
1.375
2.35
V
mV
1. IOL/ IOH defined by VODIFF/(Resistor Network).
2. Currents are measured at 85°C junction temperature.
Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
Cross point
VREF (typ.) (V)
1.075
1.325
–
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Revision 13
2-49
ProASIC3E DC and Switching Characteristics
Timing Characteristics
Table 2-80 • LVDS
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case
VCCI = 2.3 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
Units
ns
Std.
–1
1.87
1.59
1.40
1.82
1.55
1.36
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for
derating values.
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in Figure 2-23. The input and output buffer delays are available in
the LVDS section in Table 2-80.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and
RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-23 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
2-50
Revision 13
ProASIC3E Flash Family FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
N
OUTBUF_LVPECL
100
100
Z = 50
0
INBUF_LVPECL
+
–
187 W
Z = 50
100
0
N
Figure 2-24 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-81 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max. Units
3.0
3.3
3.6
V
VOL
Output Low Voltage
0.96
1.8
0
1.27
2.11
3.6
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.6
V
V
VOH
Output High Voltage
VIL, VIH
VODIFF
VOCM
VICM
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
V
0.625 0.97 0.625 0.97 0.625 0.97
1.762 1.98 1.762 1.98 1.762 1.98
V
V
1.01
300
2.57
1.01
300
2.57
1.01
300
2.57
V
VIDIFF
mV
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
1.64
1.94
Cross point
–
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Timing Characteristics
Table 2-83 • LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
tDIN
0.04
0.04
0.03
tPY
Units
ns
Std.
–1
1.83
1.55
1.36
1.63
1.39
1.22
ns
–2
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-51
ProASIC3E DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
L
D
DOUT
Data_out
PRE
F
PRE
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
DFN1E1P1
DFN1E1P1
G
E
E
EOUT
B
A
H
I
PRE
J
D
Q
DFN1E1P1
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
CLKBUF
INBUF
INBUF
Postive-Edge Triggered
Figure 2-25 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2-52
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-84 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
tOHD
F, H
tOSUE
G, H
tOHE
G, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L, DOUT
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
J, H
tOESUE
tOEHE
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
K, H
K, H
I, EOUT
I, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
C, A
B, A
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 2-25 on page 2-52 for more information.
Revision 13
2-53
ProASIC3E DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
AA
DD
CLR
LL
HH
JJ
D
Q
CLR
DFN1E1C1
KK
E
Data Input I/O Register with
Active High Enable
CLR
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
INBUF
INBUF
CLKBUF
Figure 2-26 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2-54
Revision 13
ProASIC3E Flash Family FPGAs
Table 2-85 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
tOHD
FF, HH
tOSUE
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
JJ, HH
tOESUE
tOEHE
KK, HH
KK, HH
II, EOUT
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-26 on page 2-54 for more information.
Revision 13
2-55
ProASIC3E DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tIHD
tISUD
50%
50%
1
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
tISUE
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-27 • Input Register Timing Diagram
Timing Characteristics
Table 2-86 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
–2
–1 Std. Units
Clock-to-Q of the Input Data Register
0.24 0.27 0.32
0.26 0.30 0.35
0.00 0.00 0.00
0.37 0.42 0.50
0.00 0.00 0.00
0.45 0.52 0.61
0.45 0.52 0.61
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-56
Revision 13
ProASIC3E Flash Family FPGAs
Output Register
tOCKMPWH tOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
tOREMPRE
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOHE
50%
50%
tOSUE
tOREMCLR
50%
tORECCLR
50%
tOWCLR
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-28 • Output Register Timing Diagram
Timing Characteristics
Table 2-87 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–2
–1 Std. Units
Clock-to-Q of the Output Data Register
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.59
0.00 0.00 0.00
0.80 0.91 1.07
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-57
ProASIC3E DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD OEHD
t
50% 50%
1
0
D_Enable
50%
Enable
Preset
tOEWPRE
50%
tOEREMPRE
tOERECPRE
50%
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
EOUT
Figure 2-29 • Output Enable Register Timing Diagram
Timing Characteristics
Table 2-88 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
tOESUD
Description
–2
–1 Std. Units
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.58
0.00 0.00 0.00
0.67 0.76 0.89
0.67 0.76 0.89
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
tOEHD
tOESUE
tOEHE
tOECLR2Q
tOEPRE2Q
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
tOEWCLR
tOEWPRE
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
0.36 0.41 0.48
0.32 0.37 0.43
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-58
Revision 13
ProASIC3E Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
D
Out_QF
(to core)
Data
FF1
B
E
Out_QR
(to core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-30 • Input DDR Timing Model
Table 2-89 • Parameter Definitions
Parameter Name
Parameter Definition
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Measuring Nodes (from, to)
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
Revision 13
2-59
ProASIC3E DC and Switching Characteristics
CLK
tDDRISUD
6
tDDRIHD
8
Data
CLR
1
2
3
4
5
7
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
2
4
tDDRICLKQ2
tDDRICLR2Q2
7
3
5
Figure 2-31 • Input DDR Timing Diagram
Timing Characteristics
Table 2-90 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
–2
–1
Std. Units
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
0.39 0.44 0.52
0.27 0.31 0.37
0.28 0.32 0.38
0.00 0.00 0.00
0.57 0.65 0.76
0.46 0.53 0.62
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDDRIHD
Data Hold for Input DDR
tDDRICLR2Q1
tDDRICLR2Q2
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
1404 1232 1048 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-60
Revision 13
ProASIC3E Flash Family FPGAs
Output DDR Module
Output DDR
A
B
Data_F
(from core)
X
X
FF1
Out
0
1
CLK
E
X
CLKBUF
C
X
OUTBUF
D
Data_R
(from core)
X
FF2
B
X
CLR
INBUF
C
X
DDR_OUT
Figure 2-32 • Output DDR Timing Model
Table 2-91 • Parameter Definitions
Parameter Name
tDDROCLKQ
Parameter Definition
Clock-to-Out
Measuring Nodes (from, to)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROSUD2
tDDROHD1
tDDROHD2
Revision 13
2-61
ProASIC3E DC and Switching Characteristics
CLK
t
t
DDROHD2
DDROSUD2
4
9
5
Data_F
1
2
3
t
t
DDROHD1
DDROREMCLR
Data_R 6
CLR
7
8
10
11
t
DDRORECCLR
t
DDROREMCLR
t
t
DDROCLKQ
DDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-33 • Output DDR Timing Diagram
Timing Characteristics
Table 2-92 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
–2
–1
Std. Units
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
0.70 0.80 0.94
0.38 0.43 0.51
0.38 0.43 0.51
0.00 0.00 0.00
0.00 0.00 0.00
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDDROHD2
Data_R Data Hold for Output DDR
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR
tDDROCKMPWL
FDDOMAX
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
1404 1232 1048 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-62
Revision 13
ProASIC3E Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e,
and ProASIC3/E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-34 • Sample of Combinatorial Cells
Revision 13
2-63
ProASIC3E DC and Switching Characteristics
tPD
A
B
NAND2 or
Any Combinatorial
Logic
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)
)
where edges are applicable for the particular
combinatorial cell
VCC
50%
50%
A, B, C
GND
50%
VCC
50%
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
OUT
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-35 • Timing Model and Waveforms
2-64
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-93 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
–2
–1
Std.
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Units
ns
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A B
Y = MAJ(A , B, C)
Y = A B C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
tPD
ns
AND3
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has
a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for
a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Data
Out
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-36 • Sample of Sequential Cells
Revision 13
2-65
ProASIC3E DC and Switching Characteristics
tCKMPWH CKMPWL
t
50%
50%
50%
50%
50%
50%
50%
CLK
tHD
tSUD
50%
50%
Data
EN
0
50%
tRECPRE
50%
tWPRE
tREMPRE
tHE
50%
50%
tSUE
PRE
CLR
Out
tREMCLR
tRECCLR
50%
tWCLR
50%
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 2-37 • Timing Model and Waveforms
Timing Characteristics
Table 2-94 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
–2
–1 Std. Units
Clock-to-Q of the Core Register
0.55 0.63 0.74
0.43 0.49 0.57
0.00 0.00 0.00
0.45 0.52 0.61
0.00 0.00 0.00
0.40 0.45 0.53
0.40 0.45 0.53
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.32 0.37 0.43
0.36 0.41 0.48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-66
Revision 13
ProASIC3E Flash Family FPGAs
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-38 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.
It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-38 • Example of Global Tree Use in an A3PE600 Device for Clock Routing
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-69. Table 2-95 on page 2-68, Table 2-96 on
page 2-68, and Table 2-97 on page 2-68 present minimum and maximum global clock delays within the
device. Minimum and maximum delays are measured with minimum and maximum loading.
Revision 13
2-67
ProASIC3E DC and Switching Characteristics
Timing Characteristics
Table 2-95 • A3PE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
0.83 1.04 0.94 1.18 1.11 1.39
0.81 1.06 0.93 1.21 1.09 1.42
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.25
0.28
0.33
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-96 • A3PE1500 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
1.07 1.29 1.22 1.47 1.43 1.72
1.06 1.32 1.21 1.50 1.42 1.76
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-97 • A3PE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
1.41 1.62 1.60 1.85 1.88 2.17
1.40 1.66 1.59 1.89 1.87 2.22
ns
ns
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global Clock
tRCKMPWL Minimum Pulse Width Low for Global Clock
0.75
0.85
0.85
0.96
1.00
1.13
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.35
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-68
Revision 13
ProASIC3E Flash Family FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-98 • ProASIC3E CCC/PLL Specification
Parameter
Minimum
1.5
Typical
Maximum
350
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Serial Clock (SCLK) for Dynamic PLL4
0.75
350
1603
125
32
MHz
Number of Programmable Values in Each
Programmable Delay Block
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
3 Global
1 Global
Network Used
Networks Used
0.70%
1.20%
2.00%
5.60%
300
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
0.50%
1.00%
1.75%
2.50%
Acquisition Time
Tracking Jitter 5
Output Duty Cycle
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
µs
ms
ns
ns
%
6.0
1.6
0.8
48.5
0.6
51.5
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1,2
Delay Range in Block: Fixed Delay1,4
Notes:
5.56
ns
ns
ns
0.025
5.56
2.2
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings
2. T = 25°C, VCC = 1.5 V.
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help for more information.
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
Revision 13
2-69
ProASIC3E DC and Switching Characteristics
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-39 • Peak-to-Peak Jitter Definition
2-70
Revision 13
ProASIC3E Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WEN
WCLK
WENB
CLKB
RESET
RESET
Figure 2-40 • RAM Models
Revision 13
2-71
ProASIC3E DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENS
tENH
WEN
tCKQ1
Dn
D0
D1
D2
DOUT|RD
tDOH1
Figure 2-41 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS tAH
A0
A1
A2
tBKS
tBKH
tENH
tENS
WEN
tCKQ2
Dn
D0
D1
DOUT|RD
tDOH2
Figure 2-42 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.
2-72
Revision 13
ProASIC3E Flash Family FPGAs
tCYC
tCKH
tCKL
CLK
[R|W]ADDR
BLK
tAS
tAH
A0
tBKS
A1
A2
tBKH
tENS
tENH
WEN
tDS
tDH
DI1
DI0
DIN|WD
DOUT|RD
Dn
D2
Figure 2-43 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.
tCYC
tCKH
tCKL
CLK
ADDR
BLK
tAS tAH
A0
tBKS
A1
A2
tBKH
tENS
WEN
DIN
tDS tDH
DI1
DI0
DI2
DOUT
Dn
DI0
DI1
(pass-through)
DOUT
DI0
Dn
DI1
(pipelined)
Figure 2-44 • RAM Write, Output as Write Data. Applicable to RAM4K9 Only.
Revision 13
2-73
ProASIC3E DC and Switching Characteristics
tCYC
tCKH
tCKL
CLK
RESET
tRSTBQ
Dm
Dn
DOUT|RD
Figure 2-45 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
2-74
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-99 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Address setup time
–2
–1 Std. Units
0.25 0.28 0.33
0.00 0.00 0.00
0.14 0.16 0.19
0.10 0.11 0.13
0.23 0.27 0.31
0.02 0.02 0.02
0.18 0.21 0.25
0.00 0.00 0.00
1.79 2.03 2.39
2.36 2.68 3.15
0.89 1.02 1.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
tENH
tBKS
tBKH
tDS
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
tDH
Input data (DIN) hold time
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
Clock High to new data valid on DOUT (pipelined)
tCKQ2
1
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25
address—Applicable to Closing Edge
1
tC2CWWH
Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23
address—Applicable to Rising Edge
ns
ns
ns
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34
address—Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37
address— Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on DO (flow-through)
RESET Low to Data Out Low on DO (pipelined)
RESET removal
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET recovery
RESET minimum pulse width
Clock cycle time
FMAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-75
ProASIC3E DC and Switching Characteristics
Table 2-100 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1 Std. Units
Address setup time
0.25 0.28 0.33
0.00 0.00 0.00
0.18 0.20 0.24
0.06 0.07 0.08
0.18 0.21 0.25
0.00 0.00 0.00
2.16 2.46 2.89
0.90 1.02 1.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN, WEN setup time
REN, WEN hold time
Input data (WD) setup time
Input data (WD) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
Clock High to new data valid on RD (output retained)
Clock High to new data valid on RD (pipelined)
1
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38
address—Applicable to Opening Edge
1
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44
address— Applicable to Opening Edge
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
RESET Low to data out Low on RD (pipelined)
RESET removal
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET recovery
RESET minimum pulse width
Clock cycle time
FMAX
Maximum frequency
310 272 231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-76
Revision 13
ProASIC3E Flash Family FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-46 • FIFO Model
Revision 13
2-77
ProASIC3E DC and Switching Characteristics
Timing Waveforms
tCYC
RCLK
tENH
tENS
REN
tBKS
tBKH
RBLK
tCKQ1
RD
D1
Dn
D0
D2
(flow-through)
tCKQ2
RD
Dn
D0
D1
(pipelined)
Figure 2-47 • FIFO Read
tCYC
WCLK
tENS
tENH
WEN
tBKS
tBKH
WBLK
tDS
tDH
DI1
DI0
WD
Figure 2-48 • FIFO Write
2-78
Revision 13
ProASIC3E Flash Family FPGAs
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET
EMPTY
AEMPTY
FULL
tRSTFG
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
MATCH (A0)
(Address Counter)
Figure 2-49 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Revision 13
2-79
ProASIC3E DC and Switching Characteristics
t
CYC
WCLK
FULL
t
WCKFF
t
CKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
2nd Rising
Edge
After 1st
Write
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
(EMPTY)
1st Rising
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 2nd
Read
NO MATCH
NO MATCH
Edge
After 1st
Read
WCLK
FULL
t
WCKF
t
CKAF
AFULL
Figure 2-53 • FIFO FULL Flag and AFULL Flag Deassertion
2-80
Revision 13
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 2-101 • FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std. Units
REN, WEN Setup Time
1.38 1.57 1.84
0.02 0.02 0.02
0.19 0.22 0.26
0.00 0.00 0.00
0.18 0.21 0.25
0.00 0.00 0.00
2.36 2.68 3.15
0.89 1.02 1.20
1.72 1.96 2.30
1.63 1.86 2.18
6.19 7.05 8.29
1.69 1.93 2.27
6.13 6.98 8.20
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tENH
REN, WEN Hold Time
tBKS
BLK Setup Time
tBKH
BLK Hold Time
tDS
Input Data (WD) Setup Time
tDH
Input Data (WD) Hold Time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on RD (pass-through)
Clock High to New Data Valid on RD (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET Low to Empty/Full Flag Valid
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on RD (pass-through)
RESET Low to Data Out Low on RD (pipelined)
RESET Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
FMAX
Maximum Frequency
310
272
231
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Revision 13
2-81
ProASIC3E DC and Switching Characteristics
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
tCKQ2
D1
D0
Data
Figure 2-54 • Timing Diagram
Timing Characteristics
Table 2-102 • Embedded FlashROM Access Time
Parameter
tSU
Description
Address Setup Time
–2
–1
Std.
Units
ns
0.53
0.00
16.23
15
0.61
0.00
18.48
15
0.71
0.00
21.73
15
tHOLD
tCK2Q
Address Hold Time
Clock to Out
ns
ns
FMAX
Maximum Clock Frequency
MHz
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-12 for more details.
Timing Characteristics
Table 2-103 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tDISU
Description
–2
–1
Std.
0.67
1.33
0.67
1.33
8.00
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
0.50 0.57
1.00 1.13
0.50 0.57
1.00 1.13
6.00 6.80
tDIHD
ns
tTMSSU
ns
tTMDHD
ns
tTCK2Q
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
20.00 22.67 26.67
25.00 22.00 19.00
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
0.00 0.00
0.20 0.23
TBD TBD
0.00
0.27
TBD
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-82
Revision 13
3 – Pin Descriptions and Packaging
Supply Pins
GND
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Ground
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied
to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or
3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV
and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V.
When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower
power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi
recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the
PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low
Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide
for a complete board solution for the PLL analog power supply and ground.
There are six VCCPLX pins on ProASIC3E devices.
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool
automatically disables the unused PLLs to lower power consumption. The user should tie unused
VCCPLx and VCOMPLx pins to ground.
There are six VCOMPL pins (PLL ground) on ProASIC3E devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
Revision 13
3-1
Pin Descriptions and Packaging
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User-Defined Supply Pins
VREF
I/O Voltage Reference
Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any
I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards
require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One
VREF pin can support the number of I/Os available in its minibank.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
•
•
•
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide. All
inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an
input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled
GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.
The inputs to the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the ProASIC3E FPGA Fabric User’s Guide for an explanation of the
naming of global pins.
3-2
Revision 13
ProASIC3E Flash Family FPGAs
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 W to 1 k will satisfy the requirements. Refer to
Table 3-1 for more information.
Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG
Tie-Off Resistance
200 to 1 k
200 to 1 k
500 to 1 k
500 to 1 k
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. Equivalent parallel resistance if more than one device is on the JTAG chain
2. The TCK pin can be pulled up/down.
3. The TRST pin is pulled down.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
Test Data Output
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The
values in Table 3-1 correspond to the resistor recommended when a single device is used, and the
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA
pin.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
Revision 13
3-3
Pin Descriptions and Packaging
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.
Packaging
Semiconductor technology is constantly shrinking in size while growing in capability and functional
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved
to provide improved performance and flexibility.
Microsemi consistently delivers packages that provide the necessary mechanical and environmental
protection to ensure consistent reliability and performance. Microsemi IC packaging technology
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,
Microsemi offers a variety of packages designed to meet your most demanding application and economic
requirements for today's embedded and mobile systems.
Related Documents
User’s Guides
ProASIC3E FPGA Fabric User’s Guide
http://www.microsemi.com/soc/documents/PA3E_UG.pdf
Packaging
The following documents provide packaging information and device selection for low power flash
devices.
Product Catalog
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf
Lists devices currently recommended for new designs and the packages available for each member of
the family. Use this document or the datasheet tables to determine the best package for your design, and
which package drawing to use.
Package Mechanical Drawings
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf
This document contains the package mechanical drawings for all packages currently or previously
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.
Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
3-4
Revision 13
4 – Package Pin Assignments
PQ208
208
1
208-Pin PQFP
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 13
4-1
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
1
GND
37
38
39
40
41
42
43
44
45
IO112PDB6V1
IO112NDB6V1
IO108PSB6V0
VCCIB6
72
73
VCCIB5
IO85NPB5V0
IO84NPB5V0
IO85PPB5V0
IO84PPB5V0
IO83NPB5V0
IO82NPB5V0
IO83PPB5V0
IO82PPB5V0
GND
2
GNDQ
3
VMV7
74
4
GAB2/IO133PSB7V1
GAA2/IO134PDB7V1
IO134NDB7V1
GAC2/IO132PDB7V1
IO132NDB7V1
IO130PDB7V1
IO130NDB7V1
IO127PDB7V1
IO127NDB7V1
IO126PDB7V0
IO126NDB7V0
IO124PSB7V0
VCC
75
5
GND
76
6
IO106PDB6V0
IO106NDB6V0
GEC1/IO104PDB6V0
77
7
78
8
79
9
GEC0/IO104NDB6V
0
80
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
81
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
GEB1/IO103PPB6V0
GEA1/IO102PPB6V0
GEB0/IO103NPB6V0
GEA0/IO102NPB6V0
VMV6
82
IO80NDB4V1
IO80PDB4V1
IO79NPB4V1
IO78NPB4V1
IO79PPB4V1
IO78PPB4V1
VCC
83
84
85
86
GNDQ
87
GND
GND
88
VMV5
VCCIB7
89
VCCIB4
GNDQ
IO122PPB7V0
IO121PSB7V0
IO122NPB7V0
GFC1/IO120PSB7V0
GFB1/IO119PDB7V0
GFB0/IO119NDB7V0
VCOMPLF
90
IO76NDB4V1
IO76PDB4V1
IO72NDB4V0
IO72PDB4V0
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GND
IO101NDB5V2
GEA2/IO101PDB5V2
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
GEC2/IO99PDB5V2
IO98PSB5V2
VCCIB5
91
92
93
94
95
96
GFA0/IO118NPB6V1
VCCPLF
97
98
GDA2/IO68PDB4V0
GDB2/IO69PSB4V0
GNDQ
IO96PSB5V2
IO94NDB5V1
GND
GFA1/IO118PPB6V1
GND
99
100
101
102
103
104
105
106
107
GFA2/IO117PDB6V1
IO117NDB6V1
GFB2/IO116PPB6V1
GFC2/IO115PPB6V1
IO116NPB6V1
IO115NPB6V1
VCC
TCK
IO94PDB5V1
IO92NDB5V1
IO92PDB5V1
IO88NDB5V0
IO88PDB5V0
VCC
TDI
TMS
VMV4
GND
VPUMP
GNDQ
4-2
Revision 13
ProASIC3E Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
TDO
TRST
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
IO47PDB2V1
IO44NDB2V1
IO44PDB2V1
IO43NDB2V0
IO43PDB2V0
IO40NDB2V0
IO40PDB2V0
GBC2/IO38PSB2V0
GBA2/IO36PSB2V0
GBB2/IO37PSB2V0
VMV2
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO19NPB0V2
IO18NPB0V2
IO17PPB0V2
IO16PPB0V2
IO17NPB0V2
IO16NPB0V2
VCCIB0
VJTAG
VMV3
GDA0/IO67NPB3V1
GDB0/IO66NPB3V1
GDA1/IO67PPB3V1
GDB1/IO66PPB3V1
GDC0/IO65NDB3V1
GDC1/IO65PDB3V1
IO62NDB3V1
IO62PDB3V1
IO58NDB3V0
IO58PDB3V0
GND
VCC
IO15PDB0V2
IO15NDB0V2
IO13PDB0V2
IO13NDB0V2
IO11PSB0V1
IO09PDB0V1
IO09NDB0V1
GND
GNDQ
GND
VMV1
GNDQ
VCCIB3
GBA1/IO35PDB1V1
GBA0/IO35NDB1V1
GBB1/IO34PDB1V1
GND
GCC2/IO55PSB3V0
GCB2/IO54PSB3V0
NC
IO07PDB0V1
IO07NDB0V1
IO05PDB0V0
IO05NDB0V0
VCCIB0
IO53NDB3V0
GCA2/IO53PDB3V0
GCA1/IO52PPB3V0
GND
GBB0/IO34NDB1V1
GBC1/IO33PDB1V1
GBC0/IO33NDB1V1
IO31PDB1V1
IO31NDB1V1
IO27PDB1V0
IO27NDB1V0
VCCIB1
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
VCCPLC
GCA0/IO52NPB3V0
VCOMPLC
GCB0/IO51NDB2V1
GCB1/IO51PDB2V1
GCC1/IO50PSB2V1
IO49NDB2V1
IO49PDB2V1
IO48PSB2V1
VCCIB2
VCC
IO23PPB1V0
IO22PSB1V0
IO23NPB1V0
IO21PDB1V0
IO21NDB1V0
IO19PPB0V2
GND
VMV0
GND
VCC
IO47NDB2V1
IO18PPB0V2
Revision 13
4-3
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
1
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO184PDB6V2
IO184NDB6V2
IO180PSB6V1
VCCIB6
73
74
IO145NDB5V1
IO145PDB5V1
IO143NDB5V1
IO143PDB5V1
IO137NDB5V0
IO137PDB5V0
IO135NDB5V0
IO135PDB5V0
GND
2
GNDQ
3
VMV7
75
4
GAB2/IO220PSB7V3
GAA2/IO221PDB7V3
IO221NDB7V3
GAC2/IO219PDB7V3
IO219NDB7V3
IO215PDB7V3
IO215NDB7V3
IO212PDB7V2
IO212NDB7V2
IO208PDB7V2
IO208NDB7V2
IO204PSB7V1
VCC
76
5
GND
77
6
IO176PDB6V1
IO176NDB6V1
GEC1/IO169PDB6V0
GEC0/IO169NDB6V0
GEB1/IO168PPB6V0
GEA1/IO167PPB6V0
GEB0/IO168NPB6V0
GEA0/IO167NPB6V0
VMV6
78
7
79
8
80
9
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
IO131NDB4V2
IO131PDB4V2
IO129NDB4V2
IO129PDB4V2
IO127NDB4V2
IO127PDB4V2
VCC
83
84
85
86
GNDQ
87
GND
88
GND
VMV5
89
VCCIB4
VCCIB7
GNDQ
90
IO121NDB4V1
IO121PDB4V1
IO119NDB4V1
IO119PDB4V1
IO113NDB4V0
GDC2/IO113PDB4V0
IO112NDB4V0
GND
IO200PDB7V1
IO200NDB7V1
IO196PSB7V0
GFC1/IO192PSB7V0
GFB1/IO191PDB7V0
GFB0/IO191NDB7V0
VCOMPLF
IO166NDB5V3
GEA2/IO166PDB5V3
IO165NDB5V3
GEB2/IO165PDB5V3
IO164NDB5V3
GEC2/IO164PDB5V3
IO163PSB5V3
VCCIB5
91
92
93
94
95
96
97
GFA0/IO190NPB6V2
VCCPLF
98
GDB2/IO112PDB4V0
GDA2/IO111PSB4V0
GNDQ
IO161PSB5V3
IO157NDB5V2
GND
99
GFA1/IO190PPB6V2
GND
100
101
102
103
104
105
106
107
108
TCK
GFA2/IO189PDB6V2
IO189NDB6V2
GFB2/IO188PPB6V2
GFC2/IO187PPB6V2
IO188NPB6V2
IO187NPB6V2
VCC
IO157PDB5V2
IO153NDB5V2
IO153PDB5V2
IO149NDB5V1
IO149PDB5V1
VCC
TDI
TMS
VMV4
GND
VPUMP
GNDQ
VCCIB5
TDO
4-4
Revision 13
ProASIC3E Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TRST
VJTAG
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
IO71NDB2V2
IO71PDB2V2
IO67NDB2V1
IO67PDB2V1
IO65NDB2V1
IO65PDB2V1
GBC2/IO60PSB2V0
GBA2/IO58PSB2V0
GBB2/IO59PSB2V0
VMV2
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO29NDB0V3
IO27PDB0V3
IO27NDB0V3
IO23PDB0V2
IO23NDB0V2
VCCIB0
VMV3
GDA0/IO110NPB3V2
GDB0/IO109NPB3V2
GDA1/IO110PPB3V2
GDB1/IO109PPB3V2
GDC0/IO108NDB3V2
GDC1/IO108PDB3V2
IO105NDB3V2
IO105PDB3V2
IO101NDB3V1
IO101PDB3V1
GND
VCC
IO18PDB0V2
IO18NDB0V2
IO15PDB0V1
IO15NDB0V1
IO12PSB0V1
IO11PDB0V1
IO11NDB0V1
GND
GNDQ
GND
VMV1
GNDQ
VCCIB3
GBA1/IO57PDB1V3
GBA0/IO57NDB1V3
GBB1/IO56PDB1V3
GND
GCC2/IO90PSB3V0
GCB2/IO89PSB3V0
NC
IO08PDB0V1
IO08NDB0V1
IO05PDB0V0
IO05NDB0V0
VCCIB0
IO88NDB3V0
GCA2/IO88PDB3V0
GCA1/IO87PPB3V0
GND
GBB0/IO56NDB1V3
GBC1/IO55PDB1V3
GBC0/IO55NDB1V3
IO51PDB1V2
IO51NDB1V2
IO47PDB1V1
IO47NDB1V1
VCCIB1
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
VCCPLC
GCA0/IO87NPB3V0
VCOMPLC
GCB0/IO86NDB2V3
GCB1/IO86PDB2V3
GCC1/IO85PSB2V3
IO83NDB2V3
IO83PDB2V3
IO81PSB2V3
VCCIB2
VCC
IO43PSB1V1
IO41PDB1V1
IO41NDB1V1
IO35PDB1V0
IO35NDB1V0
IO31PDB0V3
GND
VMV0
GND
VCC
IO73NDB2V2
IO73PDB2V2
IO31NDB0V3
IO29PDB0V3
Revision 13
4-5
Package Pin Assignments
PQ208
PQ208
PQ208
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
1
GND
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCCIB6
GND
79
80
IO194NDB5V0
IO194PDB5V0
GND
2
GNDQ
3
VMV7
IO244PDB6V1
IO244NDB6V1
GEC1/IO236PDB6V0
GEC0/IO236NDB6V0
GEB1/IO235PPB6V0
GEA1/IO234PPB6V0
GEB0/IO235NPB6V0
GEA0/IO234NPB6V0
VMV6
81
4
GAB2/IO308PSB7V4
GAA2/IO309PDB7V4
IO309NDB7V4
GAC2/IO307PDB7V4
IO307NDB7V4
IO303PDB7V3
IO303NDB7V3
IO299PDB7V3
IO299NDB7V3
IO295PDB7V2
IO295NDB7V2
IO291PSB7V2
VCC
82
IO184NDB4V3
IO184PDB4V3
IO180NDB4V3
IO180PDB4V3
IO176NDB4V2
IO176PDB4V2
VCC
5
83
6
84
7
85
8
86
9
87
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
88
89
VCCIB4
GNDQ
90
IO170NDB4V2
IO170PDB4V2
IO166NDB4V1
IO166PDB4V1
IO156NDB4V0
GDC2/IO156PDB4V0
IO154NPB4V0
GND
GND
91
VMV5
92
GNDQ
93
IO233NDB5V4
GEA2/IO233PDB5V4
IO232NDB5V4
GEB2/IO232PDB5V4
IO231NDB5V4
GEC2/IO231PDB5V4
IO230PSB5V4
VCCIB5
94
GND
95
VCCIB7
96
IO285PDB7V1
IO285NDB7V1
IO279PSB7V0
GFC1/IO275PSB7V0
GFB1/IO274PDB7V0
GFB0/IO274NDB7V0
VCOMPLF
97
98
GDB2/IO155PSB4V0
GDA2/IO154PPB4V0
GNDQ
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
TCK
IO218NDB5V3
IO218PDB5V3
GND
TDI
TMS
GFA0/IO273NPB6V4
VCCPLF
VMV4
IO214PSB5V2
IO212NDB5V2
IO212PDB5V2
IO208NDB5V1
IO208PDB5V1
VCC
GND
GFA1/IO273PPB6V4
GND
VPUMP
GNDQ
GFA2/IO272PDB6V4
IO272NDB6V4
GFB2/IO271PPB6V4
GFC2/IO270PPB6V4
IO271NPB6V4
IO270NPB6V4
VCC
TDO
TRST
VJTAG
VCCIB5
VMV3
IO202NDB5V1
IO202PDB5V1
IO198NDB5V0
IO198PDB5V0
IO197NDB5V0
IO197PDB5V0
GDA0/IO153NPB3V4
GDB0/IO152NPB3V4
GDA1/IO153PPB3V4
GDB1/IO152PPB3V4
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
IO252PDB6V2
IO252NDB6V2
IO248PSB6V1
4-6
Revision 13
ProASIC3E Flash Family FPGAs
PQ208
PQ208
PQ208
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
IO134NDB3V2
IO134PDB3V2
IO132NDB3V2
IO132PDB3V2
GND
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
VMV1
GNDQ
196
197
198
199
200
201
202
203
204
205
206
207
208
IO11PDB0V1
IO11NDB0V1
GBA1/IO81PDB1V4
GBA0/IO81NDB1V4
GBB1/IO80PDB1V4
GND
IO08PDB0V0
IO08NDB0V0
VCCIB0
VCCIB3
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
GCC2/IO117PSB3V0
GCB2/IO116PSB3V0
NC
GBB0/IO80NDB1V4
GBC1/IO79PDB1V4
GBC0/IO79NDB1V4
IO74PDB1V4
IO74NDB1V4
IO70PDB1V3
IO70NDB1V3
VCCIB1
IO115NDB3V0
GCA2/IO115PDB3V0
GCA1/IO114PPB3V0
GND
VMV0
VCCPLC
GCA0/IO114NPB3V0
VCOMPLC
VCC
IO56PSB1V1
IO55PDB1V1
IO55NDB1V1
IO54PDB1V1
IO54NDB1V1
IO40PDB0V4
GND
GCB0/IO113NDB2V3
GCB1/IO113PDB2V3
GCC1/IO112PSB2V3
IO110NDB2V3
IO110PDB2V3
IO106PSB2V3
VCCIB2
IO40NDB0V4
IO37PDB0V4
IO37NDB0V4
IO35PDB0V4
IO35NDB0V4
IO32PDB0V3
IO32NDB0V3
VCCIB0
GND
VCC
IO99NDB2V2
IO99PDB2V2
IO96NDB2V1
IO96PDB2V1
IO91NDB2V1
IO91PDB2V1
IO88NDB2V0
IO88PDB2V0
GBC2/IO84PSB2V0
GBA2/IO82PSB2V0
GBB2/IO83PSB2V0
VMV2
VCC
IO28PDB0V3
IO28NDB0V3
IO24PDB0V2
IO24NDB0V2
IO21PSB0V2
IO16PDB0V1
IO16NDB0V1
GND
GNDQ
GND
Revision 13
4-7
Package Pin Assignments
FG256
A1 Ball Pad Corner
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-8
Revision 13
ProASIC3E Flash Family FPGAs
FG256
FG256
FG256
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
A1
A2
GND
C5
C6
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
E9
E10
E11
E12
E13
E14
E15
E16
F1
IO21NDB1V0
VCCIB1
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO05PDB0V0
A3
C7
VCCIB1
A4
C8
VMV1
A5
C9
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
IO41PDB2V0
IO124PDB7V0
IO125PDB7V0
IO126PDB7V0
IO130NDB7V1
VCCIB7
A6
IO10PDB0V1
C10
C11
C12
C13
C14
C15
C16
D1
A7
IO12PDB0V2
A8
IO16NDB0V2
IO23NDB1V0
IO23PDB1V0
A9
A10
A11
A12
A13
A14
A15
A16
B1
VMV2
F2
IO28NDB1V1
IO28PDB1V1
IO36NDB2V0
IO42PDB2V0
IO128PDB7V1
IO129PDB7V1
GAC2/IO132PDB7V1
VCOMPLA
F3
F4
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
F5
D2
F6
GND
D3
F7
VCC
D4
F8
VCC
GAB2/IO133PDB7V1
GAA2/IO134PDB7V1
GNDQ
D5
GNDQ
F9
VCC
B2
D6
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO25PDB1V0
IO27NDB1V0
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
B3
D7
GND
B4
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
IO16PDB0V2
D8
VCCIB2
B5
D9
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PSB2V1
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
VCCIB7
B6
D10
D11
D12
D13
D14
D15
D16
E1
B7
B8
B9
IO20NDB1V0
IO24NDB1V0
IO24PDB1V0
VCOMPLB
B10
B11
B12
B13
B14
B15
B16
C1
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
G2
G3
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
G4
G5
E2
G6
VCC
GBA2/IO36PDB2V0
IO42NDB2V0
IO133NDB7V1
IO134NDB7V1
VMV7
E3
G7
GND
E4
G8
GND
E5
G9
GND
C2
E6
VCCIB0
G10
G11
G12
GND
C3
E7
VCCIB0
VCC
C4
VCCPLA
E8
IO13NDB0V2
VCCIB2
Revision 13
4-9
Package Pin Assignments
FG256
FG256
FG256
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
G13
G14
G15
G16
H1
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
IO49NSB2V1
GFB0/IO119NPB7V0
GFA0/IO118NDB6V1
GFB1/IO119PPB7V0
VCOMPLF
K1
K2
GFC2/IO115PSB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
VCCIB6
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VMV5
VCCIB5
K3
VCCIB5
K4
IO84NDB5V0
IO84PDB5V0
VCCIB4
K5
H2
K6
VCC
H3
K7
GND
VCCIB4
H4
K8
GND
VMV3
H5
GFC0/IO120NPB7V0
VCC
K9
GND
VCCPLD
H6
K10
K11
K12
K13
K14
K15
K16
L1
GND
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
H7
GND
VCC
H8
GND
VCCIB3
H9
GND
IO54NPB3V0
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
VCC
N3
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
N4
N5
GNDQ
L2
N6
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
L3
N7
GCB0/IO51NPB2V1
GFA2/IO117PSB6V1
GFA1/IO118PDB6V1
VCCPLF
L4
N8
L5
N9
J2
L6
GND
N10
N11
N12
N13
N14
N15
N16
P1
J3
L7
VCC
J4
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
L8
VCC
J5
L9
VCC
VCOMPLD
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
VCC
VJTAG
J7
GND
GND
GDC0/IO65NDB3V1
GDA1/IO67PDB3V1
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
VMV6
J8
GND
VCCIB3
J9
GND
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
IO109NPB6V0
IO106NDB6V0
IO106PDB6V0
GEC0/IO104NPB6V0
J10
J11
J12
J13
J14
J15
J16
GND
P2
VCC
P3
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
P4
VCCPLE
P5
IO101NPB5V2
IO95PPB5V1
IO92PDB5V1
IO90PDB5V1
P6
P7
GCA2/IO53PSB3V0
P8
4-10
Revision 13
ProASIC3E Flash Family FPGAs
FG256
FG256
Pin Number A3PE600 Function
Pin Number A3PE600 Function
P9
P10
P11
P12
P13
P14
P15
P16
R1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
T13
T14
T15
T16
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
GND
TCK
VPUMP
TRST
GDA0/IO67NDB3V1
GEA1/IO102PDB6V0
GEA0/IO102NDB6V0
GNDQ
R2
R3
R4
GEC2/IO99PDB5V2
IO95NPB5V1
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NSB5V0
IO80NSB4V1
IO81NDB4V1
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Revision 13
4-11
Package Pin Assignments
FG324
A1 Ball Pad Corner
1
9
7
6
4
3
2
18 17 16 15 14 13 12 11 10
8
5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-12
Revision 13
ProASIC3E Flash Family FPGAs
FG324
FG324
FG324
Pin Number
A1
A3PE3000 FBGA
GND
Pin Number
C1
A3PE3000 FBGA
IO305NDB7V3
IO308NDB7V4
GAA2/IO309PPB7V4
GAA1/IO00PPB0V0
VMV0
Pin Number
A3PE3000 FBGA
IO303NDB7V3
GNDQ
E1
E2
A2
IO08NDB0V0
IO08PDB0V0
IO10NDB0V1
IO10PDB0V1
IO12PDB0V1
GND
C2
A3
C3
E3
VMV7
A4
C4
E4
IO307NPB7V4
VCCPLA
A5
C5
E5
A6
C6
IO14NDB0V1
IO18PDB0V2
IO40NDB0V4
IO40PDB0V4
IO44PDB1V0
IO56NDB1V1
IO64NDB1V2
IO64PDB1V2
VMV1
E6
GAB0/IO01NPB0V0
VCCIB0
A7
C7
E7
A8
IO32NDB0V3
IO32PDB0V3
IO42PPB1V0
IO52NPB1V1
GND
C8
E8
GND
A9
C9
E9
IO28NDB0V3
IO48PDB1V0
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
E10
E11
E12
E13
E14
E15
E16
E17
E18
F1
VCCIB1
IO66NDB1V3
IO72NDB1V3
IO72PDB1V3
IO74NDB1V4
IO74PDB1V4
GND
IO60NPB1V2
VCCPLB
GBC0/IO79NDB1V4
GBC1/IO79PDB1V4
GBB2/IO83PPB2V0
IO88NDB2V0
IO303PDB7V3
VCCIB7
IO82NDB2V0
VMV2
GNDQ
IO90NDB2V1
IO299NDB7V3
IO299PDB7V3
IO295PDB7V2
IO295NDB7V2
VCOMPLA
IO305PDB7V3
GAB2/IO308PDB7V4
GAA0/IO00NPB0V0
VCCIB0
B2
D2
F2
B3
D3
GAC2/IO307PPB7V4
IO309NPB7V4
GAB1/IO01PPB0V0
IO14PDB0V1
IO24NDB0V2
IO24PDB0V2
IO28PDB0V3
IO48NDB1V0
IO56PDB1V1
IO60PPB1V2
F3
B4
D4
F4
B5
GNDQ
D5
F5
B6
IO12NDB0V1
IO18NDB0V2
VCCIB0
D6
F6
IO291PPB7V2
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO26PDB0V3
IO34PDB0V4
IO58NDB1V2
IO58PDB1V2
IO94PPB2V1
VCOMPLB
B7
D7
F7
B8
D8
F8
B9
IO42NPB1V0
IO44NDB1V0
VCCIB1
D9
F9
B10
B11
B12
B13
B14
B15
B16
B17
B18
D10
D11
D12
D13
D14
D15
D16
D17
D18
F10
F11
F12
F13
F14
F15
F16
F17
F18
IO52PPB1V1
IO66PDB1V3
GNDQ
GBB0/IO80NDB1V4
GBB1/IO80PDB1V4
GBA2/IO82PDB2V0
IO83NPB2V0
VCCIB2
VCCIB1
GBC2/IO84PDB2V0
IO84NDB2V0
IO92NDB2V1
IO92PDB2V1
GBA0/IO81NDB1V4
GBA1/IO81PDB1V4
IO88PDB2V0
IO90PDB2V1
Revision 13
4-13
Package Pin Assignments
FG324
FG324
FG324
Pin Number
G1
A3PE3000 FBGA
Pin Number
J1
A3PE3000 FBGA
IO267NDB6V4
GFA0/IO273NDB6V4
VCOMPLF
Pin Number
L1
A3PE3000 FBGA
IO263NDB6V3
VCCIB6
GND
IO287PDB7V1
IO287NDB7V1
IO283PPB7V1
VCCIB7
G2
J2
L2
G3
J3
L3
IO259PDB6V3
IO259NDB6V3
GND
G4
J4
GFA2/IO272PDB6V4
GFB0/IO274NPB7V0
GFC0/IO275NDB7V0
GFC1/IO275PDB7V0
GND
L4
G5
J5
L5
G6
IO279PDB7V0
IO291NPB7V2
VCC
J6
L6
IO270NPB6V4
VCC
G7
J7
L7
G8
J8
L8
VCC
G9
IO26NDB0V3
IO34NDB0V4
VCC
J9
GND
L9
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
H1
J10
J11
J12
J13
J14
J15
J16
J17
J18
K1
GND
L10
L11
L12
L13
L14
L15
L16
L17
L18
M1
GND
GND
VCC
IO94NPB2V1
IO98PDB2V2
VCCIB2
GCA2/IO115PDB3V0
GCA1/IO114PDB3V0
GCA0/IO114NDB3V0
GCB0/IO113NDB2V3
VCOMPLC
VCC
IO132PDB3V2
GND
GCC0/IO112NPB2V3
IO104PDB2V2
IO104NDB2V2
GND
IO117NDB3V0
IO128NPB3V1
VCCIB3
IO120NPB3V0
IO108NDB2V3
IO263PDB6V3
GFA1/IO273PDB6V4
VCCPLF
IO124PPB3V1
GND
IO267PDB6V4
VCCIB7
H2
K2
M2
IO255PDB6V2
IO255NDB6V2
IO251PPB6V2
VCCIB6
H3
IO283NPB7V1
GFB1/IO274PPB7V0
GND
K3
M3
H4
K4
IO272NDB6V4
GFC2/IO270PPB6V4
GFB2/IO271PDB6V4
IO271NDB6V4
GND
M4
H5
K5
M5
H6
IO279NDB7V0
VCC
K6
M6
GEB0/IO235NDB6V0
GEB1/IO235PDB6V0
VCC
H7
K7
M7
H8
VCC
K8
M8
H9
GND
K9
GND
M9
IO192PPB4V4
IO154NPB4V0
VCC
H10
H11
H12
H13
H14
H15
H16
H17
H18
GND
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
VCC
GND
VCC
IO115NDB3V0
GCB2/IO116PDB3V0
IO116NDB3V0
GCC2/IO117PDB3V0
VCCPLC
GDA0/IO153NPB3V4
IO132NDB3V2
VCCIB3
IO98NDB2V2
GND
GCB1/IO113PDB2V3
GCC1/IO112PPB2V3
VCCIB2
IO134NDB3V2
IO134PDB3V2
IO128PPB3V1
GND
IO124NPB3V1
IO120PPB3V0
IO108PDB2V3
4-14
Revision 13
ProASIC3E Flash Family FPGAs
FG324
FG324
FG324
Pin Number
N1
A3PE3000 FBGA
IO247NDB6V1
IO247PDB6V1
IO251NPB6V2
GEC0/IO236NDB6V0
VCOMPLE
Pin Number
R1
A3PE3000 FBGA
IO245NDB6V1
VCCIB6
Pin Number
A3PE3000 FBGA
IO241NDB6V0
GEA2/IO233PPB5V4
GEC2/IO231PPB5V4
VCCIB5
U1
U2
N2
R2
N3
R3
GEA1/IO234PPB6V0
IO232NDB5V4
GEB2/IO232PDB5V4
IO214NDB5V2
IO202PDB5V1
IO194PDB5V0
IO186PDB4V4
IO178PDB4V3
IO168NSB4V1
IO164PDB4V1
GDC2/IO156PDB4V0
TCK
U3
N4
R4
U4
N5
R5
U5
GNDQ
N6
IO212NDB5V2
IO212PDB5V2
IO192NPB4V4
IO174PDB4V2
IO170PDB4V2
GDA2/IO154PPB4V0
GDB2/IO155PPB4V0
GDA1/IO153PPB3V4
VCOMPLD
R6
U6
IO208PDB5V1
IO198PPB5V0
VCCIB5
N7
R7
U7
N8
R8
U8
N9
R9
U9
IO182NPB4V3
IO180NPB4V3
VCCIB4
N10
N11
N12
N13
N14
N15
N16
N17
N18
P1
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
IO166PPB4V1
IO162PDB4V1
GNDQ
GDB0/IO152NDB3V4
GDB1/IO152PDB3V4
IO138NDB3V3
IO138PDB3V3
IO245PDB6V1
GNDQ
VPUMP
VCCIB4
TRST
TMS
VCCIB3
VMV3
IO142NDB3V3
IO241PDB6V0
GEA0/IO234NPB6V0
IO233NPB5V4
IO231NPB5V4
VMV5
IO146NDB3V4
GND
P2
T2
V2
IO218NDB5V3
IO218PDB5V3
IO206NDB5V1
IO206PDB5V1
IO198NPB5V0
GND
P3
VMV6
T3
V3
P4
GEC1/IO236PDB6V0
VCCPLE
T4
V4
P5
T5
V5
P6
IO214PDB5V2
VCCIB5
T6
IO208NDB5V1
IO202NDB5V1
IO194NDB5V0
IO186NDB4V4
IO178NDB4V3
IO166NPB4V1
IO164NDB4V1
IO156NDB4V0
VMV4
V6
P7
T7
V7
P8
GND
T8
V8
IO190NDB4V4
IO190PDB4V4
IO182PPB4V3
IO180PPB4V3
GND
P9
IO174NDB4V2
IO170NDB4V2
GND
T9
V9
P10
P11
P12
P13
P14
P15
P16
P17
P18
T10
T11
T12
T13
T14
T15
T16
T17
T18
V10
V11
V12
V13
V14
V15
V16
V17
V18
VCCIB4
IO155NPB4V0
VCCPLD
IO162NDB4V1
IO160NDB4V0
IO160PDB4V0
IO158NDB4V0
IO158PDB4V0
GND
VJTAG
TDI
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
IO142PDB3V3
GNDQ
TDO
IO146PDB3V4
Revision 13
4-15
Package Pin Assignments
FG484
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-16
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
IO71NDB4V0
IO71PDB4V0
NC
B7
B8
IO07PDB0V1
IO11NDB0V1
IO17NDB0V2
IO14PDB0V2
IO19PDB0V2
IO22NDB1V0
IO26NDB1V0
NC
GND
A3
VCCIB0
B9
A4
IO06NDB0V1
IO06PDB0V1
IO08NDB0V1
IO08PDB0V1
IO11PDB0V1
IO17PDB0V2
IO18NDB0V2
IO18PDB0V2
IO22PDB1V0
IO26PDB1V0
IO29NDB1V1
IO29PDB1V1
IO31NDB1V1
IO31PDB1V1
IO32NDB1V1
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
NC
A6
NC
A7
VCCIB3
A8
GND
A9
GND
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
IO30NDB1V1
IO30PDB1V1
IO32PDB1V1
NC
AB3
VCCIB5
AB4
IO97NDB5V2
IO97PDB5V2
IO93NDB5V1
IO93PDB5V1
IO87NDB5V0
IO87PDB5V0
NC
AB5
AB6
NC
AB7
VCCIB2
GND
AB8
AB9
VCCIB7
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
C3
NC
VCCIB1
IO75NDB4V1
IO75PDB4V1
IO72NDB4V0
IO72PDB4V0
IO73NDB4V0
IO73PDB4V0
NC
C4
NC
GND
C5
GND
GND
C6
IO04NDB0V0
IO04PDB0V0
VCC
GND
C7
VCCIB6
C8
NC
C9
VCC
IO98PDB5V2
IO96NDB5V2
IO96PDB5V2
IO86NDB5V0
IO86PDB5V0
IO85PDB5V0
IO85NDB5V0
IO78PPB4V1
IO79NDB4V1
IO79PDB4V1
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO14NDB0V2
IO19NDB0V2
NC
NC
VCCIB4
GND
NC
GND
VCC
GND
VCC
B2
VCCIB7
NC
B3
NC
NC
B4
IO03NDB0V0
IO03PDB0V0
IO07NDB0V1
GND
B5
NC
B6
NC
Revision 13
4-17
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
C21
C22
D1
NC
VCCIB2
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO24NDB1V0
IO24PDB1V0
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
G5
G6
IO129PDB7V1
GAC2/IO132PDB7V1
VCOMPLA
GNDQ
NC
G7
D2
NC
G8
D3
NC
G9
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO25PDB1V0
IO27NDB1V0
GNDQ
D4
GND
GBA2/IO36PDB2V0
IO42NDB2V0
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO05PDB0V0
IO10PDB0V1
IO12PDB0V2
IO16NDB0V2
IO23NDB1V0
IO23PDB1V0
IO28NDB1V1
IO28PDB1V1
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
D6
D7
NC
D8
NC
D9
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
IO131NDB7V1
IO131PDB7V1
IO133NDB7V1
IO134NDB7V1
VMV7
VCOMPLB
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO43PDB2V0
IO43NDB2V0
NC
F3
F4
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
F9
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
H3
VCC
NC
H4
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
NC
H5
NC
H6
NC
H7
E2
NC
H8
E3
GND
VMV2
H9
VCCIB0
E4
GAB2/IO133PDB7V1
GAA2/IO134PDB7V1
GNDQ
IO36NDB2V0
IO42PDB2V0
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO13NDB0V2
IO21NDB1V0
VCCIB1
E6
E7
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
IO16PDB0V2
IO20NDB1V0
NC
E8
NC
VCCIB1
E9
IO127NDB7V1
IO127PDB7V1
NC
VMV1
E10
E11
E12
G2
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
G3
G4
IO128PDB7V1
4-18
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
H19
H20
H21
H22
J1
IO41PDB2V0
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO117NDB6V1
GFA2/IO117PDB6V1
GFA1/IO118PDB6V1
VCCPLF
NC
GND
M5
NC
VCC
M6
IO123NDB7V0
IO123PDB7V0
NC
VCCIB2
M7
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
J2
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
IO49NPB2V1
IO45NPB2V1
IO48NDB2V1
IO46NDB2V1
NC
M8
J3
M9
J4
IO124PDB7V0
IO125PDB7V0
IO126PDB7V0
IO130NDB7V1
VCCIB7
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GND
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO122PDB7V0
IO122NDB7V0
GFB0/IO119NPB7V0
GFA0/IO118NDB6V1
GFB1/IO119PPB7V0
VCOMPLF
VCC
L3
VCC
L4
VCC
L5
GCA2/IO53PDB3V0
IO53NDB3V0
IO56PDB3V0
NC
GND
L6
VCCIB2
L7
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PPB2V1
NC
L8
GFC0/IO120NPB7V0
VCC
L9
IO114PPB6V1
IO111NDB6V1
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO115PPB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
VCCIB6
IO48PDB2V1
IO46PDB2V1
IO121NDB7V0
IO121PDB7V0
NC
GND
N5
VCC
N6
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
N7
K2
N8
K3
N9
VCC
K4
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
VCCIB7
N10
N11
N12
N13
N14
N15
N16
GND
K5
GCB0/IO51NPB2V1
IO49PPB2V1
IO47NDB2V1
IO47PDB2V1
NC
GND
K6
GND
K7
GND
K8
VCC
K9
VCC
VCCIB3
K10
GND
M2
IO114NPB6V1
IO54NPB3V0
Revision 13
4-19
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE600 Function
Pin Number A3PE600 Function
Pin Number A3PE600 Function
N17
N18
N19
N20
N21
N22
P1
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
NC
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
VCCIB5
U1
U2
NC
IO107PDB6V0
IO107NDB6V0
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
VMV6
IO84NDB5V0
IO84PDB5V0
VCCIB4
U3
U4
IO56NDB3V0
IO58PDB3V0
NC
U5
VCCIB4
U6
VMV3
U7
VCCPLE
P2
IO111PDB6V1
IO115NPB6V1
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
VCCPLD
U8
IO101NPB5V2
IO95PPB5V1
IO92PDB5V1
IO90PDB5V1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
P3
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
VCC
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO59NDB3V0
IO62PDB3V1
NC
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
IO110NDB6V0
NC
TCK
VCC
T3
VPUMP
VCC
T4
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
TRST
VCC
T5
GDA0/IO67NDB3V1
NC
GND
T6
VCCIB3
T7
IO64NDB3V1
IO63PDB3V1
NC
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
NC
T8
GNDQ
T9
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
NC
V3
GND
V4
GEA1/IO102PDB6V0
GEA0/IO102NDB6V0
GNDQ
IO59PDB3V0
IO58NDB3V0
NC
V5
V6
V7
GEC2/IO99PDB5V2
IO95NPB5V1
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
R2
IO110PDB6V0
VCC
VCOMPLD
V8
R3
VJTAG
V9
R4
IO109NPB6V0
IO106NDB6V0
IO106PDB6V0
GEC0/IO104NPB6V0
VMV5
GDC0/IO65NDB3V1
GDA1/IO67PDB3V1
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO64PDB3V1
IO62NDB3V1
R8
4-20
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
Pin Number A3PE600 Function
Pin Number A3PE600 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
Y7
IO94PDB5V1
VCC
Y8
Y9
VCC
GNDQ
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO89PDB5V0
IO80PDB4V1
IO78NPB4V1
NC
TDO
GND
NC
IO63NDB3V1
NC
VCC
VCC
W2
NC
NC
W3
NC
NC
W4
GND
GND
W5
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NDB5V0
IO80NDB4V1
IO81NDB4V1
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
NC
W6
NC
W7
NC
W8
VCCIB3
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB6
Y2
NC
Y3
NC
Y4
IO98NDB5V2
GND
Y5
Y6
IO94NDB5V1
Revision 13
4-21
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
NC
B7
B8
IO10PDB0V1
IO15NDB0V1
IO17NDB0V2
IO20PDB0V2
IO29PDB0V3
IO32NDB1V0
IO43NDB1V1
NC
GND
IO117NDB4V0
IO117PDB4V0
IO115NDB4V0
IO115PDB4V0
NC
A3
VCCIB0
B9
A4
IO05NDB0V0
IO05PDB0V0
IO11NDB0V1
IO11PDB0V1
IO15PDB0V1
IO17PDB0V2
IO27NDB0V3
IO27PDB0V3
IO32PDB1V0
IO43PDB1V1
IO47NDB1V1
IO47PDB1V1
IO51NDB1V2
IO51PDB1V2
IO54NDB1V3
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
A6
A7
VCCIB3
A8
GND
A9
GND
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
IO53NDB1V2
IO53PDB1V2
IO54PDB1V3
NC
AB3
VCCIB5
AB4
IO159NDB5V3
IO159PDB5V3
IO149NDB5V1
IO149PDB5V1
IO138NDB5V0
IO138PDB5V0
NC
AB5
AB6
NC
AB7
VCCIB2
GND
AB8
AB9
VCCIB7
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
NC
C3
NC
VCCIB1
IO127NDB4V2
IO127PDB4V2
IO125NDB4V1
IO125PDB4V1
IO122NDB4V1
IO122PDB4V1
NC
C4
NC
GND
C5
GND
GND
C6
IO07NDB0V0
IO07PDB0V0
VCC
GND
C7
VCCIB6
C8
NC
C9
VCC
IO161PDB5V3
IO155NDB5V2
IO155PDB5V2
IO154NDB5V2
IO154PDB5V2
IO143PDB5V1
IO143NDB5V1
IO131PPB4V2
IO129NDB4V2
IO129PDB4V2
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO20NDB0V2
IO29NDB0V3
NC
NC
VCCIB4
GND
NC
GND
VCC
GND
VCC
B2
VCCIB7
NC
B3
NC
NC
B4
IO03NDB0V0
IO03PDB0V0
IO10NDB0V1
GND
B5
NC
B6
NC
4-22
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
C21
C22
D1
NC
VCCIB2
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO41NDB1V1
IO41PDB1V1
GBC1/IO55PDB1V3
GBB0/IO56NDB1V3
GNDQ
G5
G6
IO217PDB7V3
GAC2/IO219PDB7V3
VCOMPLA
GNDQ
NC
G7
D2
NC
G8
D3
NC
G9
IO19NDB0V2
IO19PDB0V2
IO25PDB0V3
IO33PDB1V0
IO39PDB1V0
IO45NDB1V1
GNDQ
D4
GND
GBA2/IO58PDB2V0
IO63NDB2V0
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO09PDB0V1
IO13PDB0V1
IO21PDB0V2
IO31NDB0V3
IO37NDB1V0
IO37PDB1V0
IO49NDB1V2
IO49PDB1V2
GBB1/IO56PDB1V3
GBA0/IO57NDB1V3
GBA1/IO57PDB1V3
GND
D6
D7
IO69NDB2V1
NC
D8
D9
IO218NPB7V3
IO216NDB7V3
IO216PDB7V3
IO220NDB7V3
IO221NDB7V3
VMV7
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
VCOMPLB
GBB2/IO59PDB2V0
IO62PDB2V0
IO62NDB2V0
IO71PDB2V2
IO71NDB2V2
NC
F3
F4
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO23NDB0V2
IO23PDB0V2
IO35PDB1V0
IO39NDB1V0
IO45PDB1V1
GBC0/IO55NDB1V3
VCCPLB
F9
IO209PSB7V2
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
H3
VCC
NC
H4
IO214NDB7V3
IO217NDB7V3
IO219NDB7V3
IO215PDB7V3
VMV0
IO69PDB2V1
NC
H5
H6
NC
H7
E2
IO218PPB7V3
GND
H8
E3
VMV2
H9
VCCIB0
E4
GAB2/IO220PDB7V3
GAA2/IO221PDB7V3
GNDQ
IO58NDB2V0
IO63PDB2V0
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO25NDB0V3
IO33NDB1V0
VCCIB1
E6
E7
GAB1/IO01PDB0V0
IO09NDB0V1
IO13NDB0V1
IO21NDB0V2
IO31PDB0V3
IO35NDB1V0
NC
E8
NC
VCCIB1
E9
IO211NDB7V2
IO211PDB7V2
NC
VMV1
E10
E11
E12
G2
GBC2/IO60PDB2V0
IO59NDB2V0
IO67NDB2V1
G3
G4
IO214PDB7V3
Revision 13
4-23
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
H19
H20
H21
H22
J1
IO67PDB2V1
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO189NDB6V2
GFA2/IO189PDB6V2
GFA1/IO190PDB6V2
VCCPLF
VMV2
GND
M5
IO74PSB2V2
IO212NDB7V2
IO212PDB7V2
VMV7
VCC
M6
VCCIB2
M7
IO188NDB6V2
GFB2/IO188PDB6V2
VCC
J2
GCC1/IO85PPB2V3
IO73NDB2V2
IO73PDB2V2
IO81NPB2V3
IO75NPB2V2
IO77NDB2V2
IO79NDB2V3
NC
M8
J3
M9
J4
IO206PDB7V1
IO204PDB7V1
IO210PDB7V2
IO215NDB7V3
VCCIB7
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GND
GCB2/IO89PPB3V0
GCA1/IO87PPB3V0
GCC2/IO90PPB3V0
VCCPLC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
IO196PDB7V0
IO196NDB7V0
GFB0/IO191NPB7V0
GFA0/IO190NDB6V2
GFB1/IO191PPB7V0
VCOMPLF
VCC
L3
VCC
L4
VCC
L5
GCA2/IO88PDB3V0
IO88NDB3V0
IO93PDB3V0
NC
GND
L6
VCCIB2
L7
IO60NDB2V0
IO65NDB2V1
IO65PDB2V1
IO75PPB2V2
GNDQ
L8
GFC0/IO192NPB7V0
VCC
L9
IO185PPB6V2
IO183NDB6V2
VMV6
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO187PPB6V2
IO184PPB6V2
IO186PDB6V2
IO186NDB6V2
VCCIB6
IO77PDB2V2
IO79PDB2V3
IO200NDB7V1
IO200PDB7V1
GNDQ
GND
N5
VCC
N6
GCC0/IO85NPB2V3
GCB1/IO86PPB2V3
GCA0/IO87NPB3V0
VCOMPLC
N7
K2
N8
K3
N9
VCC
K4
IO206NDB7V1
IO204NDB7V1
IO210NDB7V2
GFC1/IO192PPB7V0
VCCIB7
N10
N11
N12
N13
N14
N15
N16
GND
K5
GCB0/IO86NPB2V3
IO81PPB2V3
IO83NDB2V3
IO83PDB2V3
GNDQ
GND
K6
GND
K7
GND
K8
VCC
K9
VCC
VCCIB3
K10
GND
M2
IO185NPB6V2
IO89NPB3V0
4-24
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
N17
N18
N19
N20
N21
N22
P1
IO91NPB3V0
IO90NPB3V0
IO91PPB3V0
GNDQ
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
VCCIB5
U1
U2
IO175PPB6V1
IO173PDB6V0
IO173NDB6V0
GEB1/IO168PDB6V0
GEB0/IO168NDB6V0
VMV6
IO135NDB5V0
IO135PDB5V0
VCCIB4
U3
U4
IO93NDB3V0
IO95PDB3V1
NC
U5
VCCIB4
U6
VMV3
U7
VCCPLE
P2
IO183PDB6V2
IO187NPB6V2
IO184NPB6V2
IO176PPB6V1
IO182PDB6V1
IO182NDB6V1
VCCIB6
VCCPLD
U8
IO166NPB5V3
IO157PPB5V2
IO145PDB5V1
IO141PDB5V0
IO139PDB5V0
IO121NDB4V1
IO121PDB4V1
VMV4
P3
GDB1/IO109PPB3V2
GDC1/IO108PDB3V2
IO99NDB3V1
VCC
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO98NDB3V1
IO101PDB3V1
NC
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
IO177NDB6V1
NC
TCK
VCC
T3
VPUMP
VCC
T4
IO171PDB6V0
IO171NDB6V0
GEC1/IO169PPB6V0
VCOMPLE
TRST
VCC
T5
GDA0/IO110NDB3V2
NC
GND
T6
VCCIB3
T7
IO103NDB3V2
IO105PDB3V2
NC
GDB0/IO109NPB3V2
IO97NDB3V1
IO97PDB3V1
IO99PDB3V1
VMV3
T8
GNDQ
T9
GEA2/IO166PPB5V3
IO145NDB5V1
IO141NDB5V0
IO139NDB5V0
IO119NDB4V1
IO119PDB4V1
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
IO175NPB6V1
GND
V3
V4
GEA1/IO167PDB6V0
GEA0/IO167NDB6V0
GNDQ
IO98PDB3V1
IO95NDB3V1
NC
V5
V6
V7
GEC2/IO164PDB5V3
IO157NPB5V2
IO151NDB5V2
IO151PDB5V2
IO137NDB5V0
IO137PDB5V0
IO123NDB4V1
IO123PDB4V1
R2
IO177PDB6V1
VCC
VCOMPLD
V8
R3
VJTAG
V9
R4
IO176NPB6V1
IO174NDB6V0
IO174PDB6V0
GEC0/IO169NPB6V0
VMV5
GDC0/IO108NDB3V2
GDA1/IO110PDB3V2
NC
V10
V11
V12
V13
V14
R5
R6
R7
IO103PDB3V2
IO101NDB3V1
R8
Revision 13
4-25
Package Pin Assignments
FG484
FG484
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO112NDB4V0
GDB2/IO112PDB4V0
TDI
Y7
IO163PDB5V3
Y8
VCC
Y9
VCC
GNDQ
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO147PDB5V1
TDO
IO133PDB4V2
GND
IO131NPB4V2
NC
NC
IO105NDB3V2
NC
VCC
VCC
NC
W2
NC
W3
NC
NC
W4
GND
GND
NC
W5
IO165NDB5V3
GEB2/IO165PDB5V3
IO164NDB5V3
IO153NDB5V2
IO153PDB5V2
IO147NDB5V1
IO133NDB4V2
IO130NDB4V2
IO130PDB4V2
IO113NDB4V0
GDC2/IO113PDB4V0
IO111NDB4V0
GDA2/IO111PDB4V0
TMS
W6
NC
W7
NC
W8
VCCIB3
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
NC
NC
NC
VCCIB6
Y2
NC
Y3
NC
Y4
IO161NDB5V3
GND
Y5
Y6
IO163NDB5V3
4-26
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
A1
A2
GND
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
IO170PDB4V2
IO166NDB4V1
IO166PDB4V1
IO160NDB4V0
IO160PDB4V0
IO158NPB4V0
VCCIB3
B7
B8
IO14PDB0V1
IO18NDB0V2
IO24NDB0V2
IO34PDB0V4
IO40PDB0V4
IO46NDB1V0
IO54NDB1V1
IO62NDB1V2
IO62PDB1V2
IO68NDB1V3
IO68PDB1V3
IO72PDB1V3
IO74PDB1V4
IO76NPB1V4
VCCIB2
GND
A3
VCCIB0
B9
A4
IO10NDB0V1
IO10PDB0V1
IO16NDB0V1
IO16PDB0V1
IO18PDB0V2
IO24PDB0V2
IO28NDB0V3
IO28PDB0V3
IO46PDB1V0
IO54PDB1V1
IO56NDB1V1
IO56PDB1V1
IO64NDB1V2
IO64PDB1V2
IO72NDB1V3
IO74NDB1V4
VCCIB1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
A6
A7
A8
GND
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
GND
AB3
VCCIB5
AB4
IO216NDB5V2
IO216PDB5V2
IO210NDB5V2
IO210PDB5V2
IO208NDB5V1
IO208PDB5V1
IO197NDB5V0
IO197PDB5V0
IO174NDB4V2
IO174PDB4V2
IO172NDB4V2
IO172PDB4V2
IO168NDB4V1
IO168PDB4V1
IO162NDB4V1
IO162PDB4V1
VCCIB4
AB5
AB6
AB7
AB8
GND
AB9
VCCIB7
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
C2
IO303PDB7V3
IO305PDB7V3
IO06NPB0V0
GND
C3
C4
GND
C5
GND
C6
IO12NDB0V1
IO12PDB0V1
VCC
GND
C7
VCCIB6
C8
IO228PDB5V4
IO224PDB5V3
IO218NDB5V3
IO218PDB5V3
IO212NDB5V2
IO212PDB5V2
IO198PDB5V0
IO198NDB5V0
IO188PPB4V4
IO180NDB4V3
IO180PDB4V3
IO170NDB4V2
C9
VCC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
IO34NDB0V4
IO40NDB0V4
IO48NDB1V0
IO48PDB1V0
VCC
GND
GND
GND
VCC
B2
VCCIB7
IO70NDB1V3
IO70PDB1V3
GND
B3
IO06PPB0V0
IO08NDB0V0
IO08PDB0V0
IO14NDB0V1
B4
B5
IO76PPB1V4
IO88NDB2V0
B6
Revision 13
4-27
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
C21
C22
D1
IO94PPB2V1
VCCIB2
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO58NDB1V2
IO58PDB1V2
GBC1/IO79PDB1V4
GBB0/IO80NDB1V4
GNDQ
G5
G6
IO297PDB7V2
GAC2/IO307PDB7V4
VCOMPLA
IO293PDB7V2
IO303NDB7V3
IO305NDB7V3
GND
G7
D2
G8
GNDQ
D3
G9
IO26NDB0V3
IO26PDB0V3
IO36PDB0V4
IO42PDB1V0
IO50PDB1V1
IO60NDB1V2
GNDQ
D4
GBA2/IO82PDB2V0
IO86NDB2V0
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO20PDB0V2
IO22PDB0V2
IO30PDB0V3
IO38NDB0V4
IO52NDB1V1
IO52PDB1V1
IO66NDB1V3
IO66PDB1V3
GBB1/IO80PDB1V4
GBA0/IO81NDB1V4
GBA1/IO81PDB1V4
GND
D6
D7
IO90NDB2V1
IO98PDB2V2
IO299NPB7V3
IO301NDB7V3
IO301PDB7V3
IO308NDB7V4
IO309NDB7V4
VMV7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
VCOMPLB
F3
GBB2/IO83PDB2V0
IO92PDB2V1
IO92NDB2V1
IO102PDB2V2
IO102NDB2V2
IO105NDB2V2
IO286PSB7V1
IO291NPB7V2
VCC
F4
F5
F6
F7
VCCPLA
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO32NDB0V3
IO32PDB0V3
IO44PDB1V0
IO50NDB1V1
IO60PDB1V2
GBC0/IO79NDB1V4
VCCPLB
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
H3
IO88PDB2V0
IO90PDB2V1
IO94NPB2V1
IO293NDB7V2
IO299PPB7V3
GND
H4
IO295NDB7V2
IO297NDB7V2
IO307NDB7V4
IO287PDB7V1
VMV0
H5
H6
H7
E2
H8
E3
VMV2
H9
VCCIB0
E4
GAB2/IO308PDB7V4
GAA2/IO309PDB7V4
GNDQ
IO82NDB2V0
IO86PDB2V0
IO96PDB2V1
IO96NDB2V1
IO98NDB2V2
IO289NDB7V1
IO289PDB7V1
IO291PPB7V2
IO295PDB7V2
H10
H11
H12
H13
H14
H15
H16
H17
H18
VCCIB0
E5
IO36NDB0V4
IO42NDB1V0
VCCIB1
E6
E7
GAB1/IO01PDB0V0
IO20NDB0V2
IO22NDB0V2
IO30NDB0V3
IO38PDB0V4
IO44NDB1V0
E8
VCCIB1
E9
VMV1
E10
E11
E12
G2
GBC2/IO84PDB2V0
IO83NDB2V0
IO100NDB2V2
G3
G4
4-28
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
FG484
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
H19
H20
H21
H22
J1
IO100PDB2V2
VCC
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
GND
GND
M3
M4
IO272NDB6V4
GFA2/IO272PDB6V4
GFA1/IO273PDB6V4
VCCPLF
VMV2
GND
M5
IO105PDB2V2
IO285NDB7V1
IO285PDB7V1
VMV7
VCC
M6
VCCIB2
M7
IO271NDB6V4
GFB2/IO271PDB6V4
VCC
J2
GCC1/IO112PPB2V3
IO108NDB2V3
IO108PDB2V3
IO110NPB2V3
IO106NPB2V3
IO109NDB2V3
IO107NDB2V3
IO257PSB6V2
IO276PDB7V0
IO276NDB7V0
GFB0/IO274NPB7V0
GFA0/IO273NDB6V4
GFB1/IO274PPB7V0
VCOMPLF
M8
J3
M9
J4
IO279PDB7V0
IO283PDB7V1
IO281PDB7V0
IO287NDB7V1
VCCIB7
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
J5
GND
J6
GND
J7
GND
J8
VCC
J9
GND
GCB2/IO116PPB3V0
GCA1/IO114PPB3V0
GCC2/IO117PPB3V0
VCCPLC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
L2
VCC
L3
VCC
L4
VCC
L5
GCA2/IO115PDB3V0
IO115NDB3V0
IO126PDB3V1
IO124PSB3V1
IO255PPB6V2
IO253NDB6V2
VMV6
GND
L6
VCCIB2
L7
IO84NDB2V0
IO104NDB2V2
IO104PDB2V2
IO106PPB2V3
GNDQ
L8
GFC0/IO275NPB7V0
VCC
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
GND
N2
GND
N3
GND
N4
GFC2/IO270PPB6V4
IO261PPB6V3
IO263PDB6V3
IO263NDB6V3
VCCIB6
IO109PDB2V3
IO107PDB2V3
IO277NDB7V0
IO277PDB7V0
GNDQ
GND
N5
VCC
N6
GCC0/IO112NPB2V3
GCB1/IO113PPB2V3
GCA0/IO114NPB3V0
VCOMPLC
N7
K2
N8
K3
N9
VCC
K4
IO279NDB7V0
IO283NDB7V1
IO281NDB7V0
GFC1/IO275PPB7V0
VCCIB7
N10
N11
N12
N13
N14
N15
N16
GND
K5
GCB0/IO113NPB2V3
IO110PPB2V3
IO111NDB2V3
IO111PDB2V3
GNDQ
GND
K6
GND
K7
GND
K8
VCC
K9
VCC
VCCIB3
K10
GND
M2
IO255NPB6V2
IO116NPB3V0
Revision 13
4-29
Package Pin Assignments
FG484
FG484
FG484
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
N17
N18
N19
N20
N21
N22
P1
IO132NPB3V2
IO117NPB3V0
IO132PPB3V2
GNDQ
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCCIB5
VCCIB5
U1
U2
IO240PPB6V0
IO238PDB6V0
IO238NDB6V0
GEB1/IO235PDB6V0
GEB0/IO235NDB6V0
VMV6
IO196NDB5V0
IO196PDB5V0
VCCIB4
U3
U4
IO126NDB3V1
IO128PDB3V1
IO247PDB6V1
IO253PDB6V2
IO270NPB6V4
IO261NPB6V3
IO249PPB6V1
IO259PDB6V3
IO259NDB6V3
VCCIB6
U5
VCCIB4
U6
VMV3
U7
VCCPLE
P2
VCCPLD
U8
IO233NPB5V4
IO222PPB5V3
IO206PDB5V1
IO202PDB5V1
IO194PDB5V0
IO176NDB4V2
IO176PDB4V2
VMV4
P3
GDB1/IO152PPB3V4
GDC1/IO151PDB3V4
IO138NDB3V3
VCC
U9
P4
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
P5
P6
P7
IO130NDB3V2
IO134PDB3V2
IO243PPB6V1
IO245NDB6V1
IO243NPB6V1
IO241PDB6V0
IO241NDB6V0
GEC1/IO236PPB6V0
VCOMPLE
P8
P9
GND
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
T2
TCK
VCC
T3
VPUMP
VCC
T4
TRST
VCC
T5
GDA0/IO153NDB3V4
IO144NDB3V3
IO140NDB3V3
IO142PDB3V3
IO239PDB6V0
IO240NPB6V0
GND
GND
T6
VCCIB3
T7
GDB0/IO152NPB3V4
IO136NDB3V2
IO136PDB3V2
IO138PDB3V3
VMV3
T8
GNDQ
T9
GEA2/IO233PPB5V4
IO206NDB5V1
IO202NDB5V1
IO194NDB5V0
IO186NDB4V4
IO186PDB4V4
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
V2
V3
V4
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
GNDQ
IO130PDB3V2
IO128NDB3V1
IO247NDB6V1
IO245PDB6V1
VCC
V5
V6
V7
GEC2/IO231PDB5V4
IO222NPB5V3
IO204NDB5V1
IO204PDB5V1
IO195NDB5V0
IO195PDB5V0
IO178NDB4V3
IO178PDB4V3
R2
VCOMPLD
V8
R3
VJTAG
V9
R4
IO249NPB6V1
IO251NDB6V2
IO251PDB6V2
GEC0/IO236NPB6V0
VMV5
GDC0/IO151NDB3V4
GDA1/IO153PDB3V4
IO144PDB3V3
IO140PDB3V3
IO134NDB3V2
V10
V11
V12
V13
V14
R5
R6
R7
R8
4-30
Revision 13
ProASIC3E Flash Family FPGAs
FG484
FG484
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO155NDB4V0
GDB2/IO155PDB4V0
TDI
Y7
IO220PDB5V3
VCC
Y8
Y9
VCC
GNDQ
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
IO200PDB5V0
IO192PDB4V4
IO188NPB4V4
IO187PSB4V4
VCC
TDO
GND
IO146PDB3V4
IO142NDB3V3
IO239NDB6V0
IO237PDB6V0
IO230PSB5V4
GND
VCC
W2
IO164NDB4V1
IO164PDB4V1
GND
W3
W4
W5
IO232NDB5V4
GEB2/IO232PDB5V4
IO231NDB5V4
IO214NDB5V2
IO214PDB5V2
IO200NDB5V0
IO192NDB4V4
IO184NDB4V3
IO184PDB4V3
IO156NDB4V0
GDC2/IO156PDB4V0
IO154NDB4V0
GDA2/IO154PDB4V0
TMS
IO158PPB4V0
IO150PDB3V4
IO148NPB3V4
VCCIB3
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GND
IO150NDB3V4
IO146NDB3V4
IO148PPB3V4
VCCIB6
Y2
IO237NDB6V0
IO228NDB5V4
IO224NDB5V3
GND
Y3
Y4
Y5
Y6
IO220NDB5V3
Revision 13
4-31
Package Pin Assignments
FG676
A1 Ball Pad Corner
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7 6
5
4
3
2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-32
Revision 13
ProASIC3E Flash Family FPGAs
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
A1
A2
GND
GND
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AB1
IO153NDB5V2
IO147NDB5V1
IO139NDB5V0
IO137NDB5V0
IO123NDB4V1
IO123PDB4V1
IO117NDB4V0
IO117PDB4V0
GDB2/IO112PDB4V0
GNDQ
AB21
AB22
AB23
AB24
AB25
AB26
AC1
TCK
TRST
A3
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
IO06NDB0V0
IO09NDB0V1
IO09PDB0V1
IO14NDB0V1
IO14PDB0V1
IO22NDB0V2
IO22PDB0V2
IO26NDB0V3
IO26PDB0V3
IO30NDB0V3
IO30PDB0V3
IO34NDB1V0
IO34PDB1V0
IO38NDB1V0
IO38PDB1V0
IO41PDB1V1
IO44PDB1V1
IO49PDB1V2
IO50PDB1V2
GBC1/IO55PDB1V3
GND
GDC0/IO108NDB3V2
GDC1/IO108PDB3V2
IO104NDB3V2
IO104PDB3V2
IO170PDB6V0
GEB0/IO168NPB6V0
IO166NPB5V3
GNDQ
A4
A5
A6
A7
A8
AC2
A9
AC3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AC4
TDO
AC5
GND
GND
AC6
IO160PDB5V3
IO161PDB5V3
IO154PDB5V2
GND
GND
AC7
IO102NDB3V1
IO102PDB3V1
IO98NDB3V1
IO174NDB6V0
IO171NDB6V0
GEB1/IO168PPB6V0
GEA0/IO167NPB6V0
VCCPLE
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
IO150NDB5V1
IO155NDB5V2
IO142NDB5V0
IO138NDB5V0
IO138PDB5V0
IO132NDB4V2
IO129NDB4V2
IO121NDB4V1
IO119PDB4V1
IO118NDB4V0
IO118PDB4V0
IO114PPB4V0
TMS
AB2
AB3
AB4
AB5
AB6
GND
AB7
GND
AB8
IO156NDB5V2
IO156PDB5V2
IO150PDB5V1
IO155PDB5V2
IO142PDB5V0
IO135NDB5V0
IO135PDB5V0
IO132PDB4V2
IO129PDB4V2
IO121PDB4V1
IO119NDB4V1
IO112NDB4V0
VMV4
AB9
GND
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
IO174PDB6V0
IO171PDB6V0
GEA1/IO167PPB6V0
GEC0/IO169NPB6V0
VCOMPLE
VJTAG
VMV3
IO106NDB3V2
IO106PDB3V2
IO170NDB6V0
GEA2/IO166PPB5V3
VMV5
GND
IO165NDB5V3
GEB2/IO165PDB5V3
IO163PDB5V3
IO159NDB5V3
AD2
AD3
AD4
GEC2/IO164PDB5V3
Revision 13
4-33
Package Pin Assignments
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
AD5
AD6
IO162PDB5V3
IO160NDB5V3
IO161NDB5V3
IO154NDB5V2
IO148PDB5V1
IO151PDB5V2
IO144PDB5V1
IO140PDB5V0
IO143PDB5V1
IO141PDB5V0
IO134PDB4V2
IO133PDB4V2
IO127PDB4V2
IO130PDB4V2
IO126PDB4V1
IO124PDB4V1
IO120PDB4V1
IO114NPB4V0
TDI
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
IO134NDB4V2
IO133NDB4V2
IO127NDB4V2
IO130NDB4V2
IO126NDB4V1
IO124NDB4V1
IO120NDB4V1
IO116PDB4V0
GDC2/IO113PDB4V0
GDA2/IO111PDB4V0
GND
AF25
AF26
B1
GND
GND
AD7
GND
AD8
B2
GND
AD9
B3
GND
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
B4
GND
B5
IO06PDB0V0
IO04NDB0V0
IO07NDB0V0
IO11NDB0V1
IO10NDB0V1
IO16NDB0V2
IO20NDB0V2
IO24NDB0V3
IO23NDB0V2
IO28NDB0V3
IO31NDB0V3
IO32PDB1V0
IO36PDB1V0
IO37PDB1V0
IO42NPB1V1
IO41NDB1V1
IO44NDB1V1
IO49NDB1V2
IO50NDB1V2
GBC0/IO55NDB1V3
GND
B6
B7
B8
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
GND
AF2
GND
AF3
GND
AF4
GND
AF5
IO158NPB5V2
IO157NPB5V2
IO152NPB5V2
IO146NDB5V1
IO146PDB5V1
IO149NDB5V1
IO149PDB5V1
IO145NDB5V1
IO145PDB5V1
IO136NDB5V0
IO136PDB5V0
IO131NDB4V2
IO131PDB4V2
IO128NDB4V2
IO128PDB4V2
IO122NDB4V1
IO122PDB4V1
IO116NDB4V0
IO113NDB4V0
IO111NDB4V0
AF6
AF7
GNDQ
AF8
GDA0/IO110NDB3V2
GDA1/IO110PDB3V2
GND
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AE2
GND
AE3
GND
AE4
IO164NDB5V3
IO162NDB5V3
IO158PPB5V2
IO157PPB5V2
IO152PPB5V2
IO148NDB5V1
IO151NDB5V2
IO144NDB5V1
IO140NDB5V0
IO143NDB5V1
IO141NDB5V0
AE5
AE6
GND
AE7
GND
AE8
C2
GND
AE9
C3
GND
AE10
AE11
AE12
AE13
AE14
C4
GND
C5
GAA2/IO221PDB7V3
IO04PDB0V0
IO07PDB0V0
IO11PDB0V1
C6
C7
C8
4-34
Revision 13
ProASIC3E Flash Family FPGAs
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
IO10PDB0V1
IO16PDB0V2
IO20PDB0V2
IO24PDB0V3
IO23PDB0V2
IO28PDB0V3
IO31PDB0V3
IO32NDB1V0
IO36NDB1V0
IO37NDB1V0
IO45NDB1V1
IO42PPB1V1
IO46NPB1V1
IO48NPB1V2
GBB0/IO56NPB1V3
VMV1
D19
D20
D21
D22
D23
D24
D25
D26
E1
IO45PDB1V1
IO46PPB1V1
IO48PPB1V2
GBA0/IO57NPB1V3
GNDQ
F3
F4
IO213NDB7V2
IO213PDB7V2
GND
F5
F6
VCCPLA
F7
GAB0/IO01NDB0V0
GNDQ
GBB1/IO56PPB1V3
GBB2/IO59PDB2V0
IO59NDB2V0
IO212PDB7V2
IO211NDB7V2
IO211PDB7V2
IO220NPB7V3
GNDQ
F8
F9
IO03PDB0V0
IO13PDB0V1
IO15PDB0V1
IO19PDB0V2
IO21PDB0V2
IO27NDB0V3
IO35PDB1V0
IO39NDB1V0
IO51PDB1V2
IO53PDB1V2
IO54PDB1V3
VMV2
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
E2
E3
E4
E5
E6
GAB2/IO220PPB7V3
GAB1/IO01PDB0V0
IO05PDB0V0
IO08NDB0V1
IO12PDB0V1
IO18PDB0V2
IO17PDB0V2
IO25PDB0V3
IO29PDB0V3
IO33PDB1V0
IO40NDB1V1
IO43PDB1V1
IO47NDB1V1
IO54NDB1V3
IO52NDB1V2
IO52PDB1V2
VCCPLB
E7
E8
GBC2/IO60PDB2V0
IO60NDB2V0
IO218NDB7V3
IO218PDB7V3
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
VCOMPLB
D2
IO61PDB2V0
IO61NDB2V0
IO66PDB2V1
IO66NDB2V1
IO68NDB2V1
IO203NPB7V1
IO207NDB7V2
IO207PDB7V2
IO216NDB7V3
IO216PDB7V3
VCOMPLA
D3
D4
VMV7
D5
IO221NDB7V3
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO05NDB0V0
IO08PDB0V1
IO12NDB0V1
IO18NDB0V2
IO17NDB0V2
IO25NDB0V3
IO29NDB0V3
IO33NDB1V0
IO40PDB1V1
IO43NDB1V1
IO47PDB1V1
D6
D7
D8
G2
D9
G3
D10
D11
D12
D13
D14
D15
D16
D17
D18
G4
G5
G6
GBA1/IO57PPB1V3
IO63PDB2V0
IO63NDB2V0
IO68PDB2V1
IO212NDB7V2
IO203PPB7V1
G7
VMV0
G8
VCC
G9
IO03NDB0V0
IO13NDB0V1
IO15NDB0V1
IO19NDB0V2
G10
G11
G12
F2
Revision 13
4-35
Package Pin Assignments
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
H1
IO21NDB0V2
IO27PDB0V3
IO35NDB1V0
IO39PDB1V0
IO51NDB1V2
IO53NDB1V2
VCCIB1
H23
H24
H25
H26
J1
IO69PDB2V1
IO76PDB2V2
IO76NDB2V2
IO78NDB2V2
IO197NDB7V0
IO197PDB7V0
VMV7
K7
K8
IO217NDB7V3
VCCIB7
VCC
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
L1
GND
GND
J2
GND
J3
GND
GBA2/IO58PPB2V0
GNDQ
J4
IO215NDB7V3
IO215PDB7V3
IO214PDB7V3
IO214NDB7V3
VCCIB7
GND
J5
GND
IO64NDB2V1
IO64PDB2V1
IO72PDB2V2
IO72NDB2V2
IO78PDB2V2
IO208NDB7V2
IO208PDB7V2
IO209NDB7V2
IO209PDB7V2
IO219NDB7V3
GAC2/IO219PDB7V3
VCCIB7
J6
GND
J7
GND
J8
VCC
J9
VCC
VCCIB2
IO65PDB2V1
IO65NDB2V1
IO74PDB2V2
IO74NDB2V2
IO75PDB2V2
IO75NDB2V2
IO84PDB2V3
IO195NDB7V0
IO198PPB7V0
GNDQ
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
K1
VCC
VCC
H2
VCC
H3
VCC
H4
VCC
H5
VCC
H6
VCC
H7
VCC
H8
VCC
VCC
L2
H9
VCCIB0
VCCIB2
L3
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
VCCIB0
IO62PDB2V0
IO62NDB2V0
IO70NDB2V1
IO69NDB2V1
VMV2
L4
IO201PDB7V1
IO201NDB7V1
IO210NDB7V2
IO210PDB7V2
VCCIB7
VCC
VCCIB0
L5
VCCIB0
L6
VCCIB0
L7
VCCIB1
L8
VCCIB1
IO80PDB2V3
IO80NDB2V3
IO195PDB7V0
IO199NDB7V1
IO199PDB7V1
IO205NDB7V1
IO205PDB7V1
IO217PDB7V3
L9
VCCIB1
L10
L11
L12
L13
L14
L15
L16
GND
VCCIB1
GND
VCCIB1
K2
GND
VCC
K3
GND
VCC
K4
GND
IO58NPB2V0
IO70PDB2V1
K5
GND
K6
GND
4-36
Revision 13
ProASIC3E Flash Family FPGAs
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
GND
VCC
N1
N2
GFB0/IO191NPB7V0
VCOMPLF
GFB1/IO191PPB7V0
IO196PDB7V0
GFA0/IO190NDB6V2
IO200PDB7V1
IO200NDB7V1
VCCIB7
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R1
GND
GND
VCCIB2
N3
GND
IO67PDB2V1
IO67NDB2V1
IO71PDB2V2
IO71NDB2V2
GNDQ
N4
GND
N5
GND
N6
GND
N7
GND
N8
VCC
IO82PDB2V3
IO84NDB2V3
IO198NPB7V0
IO202PDB7V1
IO202NDB7V1
IO206NDB7V1
IO206PDB7V1
IO204NDB7V1
IO204PDB7V1
VCCIB7
N9
VCC
VCCIB3
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
P1
GND
GCC0/IO85NDB2V3
GCC1/IO85PDB2V3
GCB1/IO86PPB2V3
IO88NPB3V0
GCA1/IO87PDB3V0
VCCPLC
GND
M2
GND
M3
GND
M4
GND
M5
GND
M6
GND
VCOMPLC
IO189NDB6V2
IO185PDB6V2
IO187NPB6V2
IO193NPB7V0
GFC2/IO187PPB6V2
GFC1/IO192PDB7V0
GFC0/IO192NDB7V0
VCCIB6
M7
GND
M8
VCC
R2
M9
VCC
VCCIB2
R3
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
GND
IO79PDB2V3
IO79NDB2V3
GCA2/IO88PPB3V0
IO81NPB2V3
GCA0/IO87NDB3V0
GCB0/IO86NPB2V3
IO83NDB2V3
GFA2/IO189PDB6V2
VCCPLF
R4
GND
R5
GND
R6
GND
R7
GND
R8
GND
R9
VCC
GND
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
GND
GND
GND
VCC
P2
GND
VCCIB2
P3
IO193PPB7V0
IO196NDB7V0
GFA1/IO190PDB6V2
IO194PDB7V0
IO194NDB7V0
VCCIB6
GND
IO73NDB2V2
IO73PDB2V2
IO81PPB2V3
IO77PDB2V2
IO77NDB2V2
IO82NDB2V3
IO83PDB2V3
P4
GND
P5
GND
P6
GND
P7
GND
P8
VCC
P9
VCC
VCCIB3
P10
GND
NC
Revision 13
4-37
Package Pin Assignments
FG676
FG676
FG676
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
R21
R22
R23
R24
R25
R26
T1
IO89NDB3V0
GCB2/IO89PDB3V0
IO90NDB3V0
GCC2/IO90PDB3V0
IO91PDB3V0
IO91NDB3V0
IO186PDB6V2
IO185NDB6V2
GNDQ
U5
U6
IO182PDB6V1
IO178PDB6V1
IO178NDB6V1
VCCIB6
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
W1
VCC
VCC
U7
VCC
U8
VCC
U9
VCC
VCCIB3
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V1
GND
IO107PDB3V2
IO107NDB3V2
IO103NDB3V2
IO103PDB3V2
VMV3
GND
T2
GND
T3
GND
T4
IO180PDB6V1
IO180NDB6V1
IO188NDB6V2
GFB2/IO188PDB6V2
VCCIB6
GND
T5
GND
IO95NDB3V1
IO94PDB3V0
IO179NDB6V1
IO179PDB6V1
IO177NDB6V1
IO177PDB6V1
IO172PDB6V0
IO172NDB6V0
VCC
T6
GND
T7
GND
T8
VCC
W2
T9
VCC
VCCIB3
W3
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
U1
GND
NC
W4
GND
IO101NDB3V1
IO101PDB3V1
IO92NDB3V0
IO92PDB3V0
IO95PDB3V1
IO93NPB3V0
IO183PDB6V2
IO183NDB6V2
VMV6
W5
GND
W6
GND
W7
GND
W8
VCC
GND
W9
VCCIB5
GND
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
VCCIB5
GND
VCCIB5
VCC
V2
VCCIB5
VCCIB3
V3
VCCIB5
IO99PDB3V1
IO99NDB3V1
IO97PDB3V1
IO97NDB3V1
GNDQ
V4
IO181PDB6V1
IO181NDB6V1
IO176PDB6V1
IO176NDB6V1
VCCIB6
VCCIB4
V5
VCCIB4
V6
VCCIB4
V7
VCCIB4
V8
VCCIB4
IO93PPB3V0
NC
V9
VCC
VCC
V10
V11
V12
V13
V14
VCC
VCCIB3
IO186NDB6V2
IO184NDB6V2
IO184PDB6V2
IO182NDB6V1
VCC
GDB0/IO109NDB3V2
GDB1/IO109PDB3V2
IO105NDB3V2
IO105PDB3V2
U2
VCC
U3
VCC
U4
VCC
4-38
Revision 13
ProASIC3E Flash Family FPGAs
FG676
Pin Number A3PE1500 Function
W25
W26
Y1
IO96PDB3V1
IO94NDB3V0
IO175NDB6V1
IO175PDB6V1
IO173NDB6V0
IO173PDB6V0
GEC1/IO169PPB6V0
GNDQ
Y2
Y3
Y4
Y5
Y6
Y7
VMV6
Y8
VCCIB5
Y9
IO163NDB5V3
IO159PDB5V3
IO153PDB5V2
IO147PDB5V1
IO139PDB5V0
IO137PDB5V0
IO125NDB4V1
IO125PDB4V1
IO115NDB4V0
IO115PDB4V0
VCC
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
VPUMP
VCOMPLD
VCCPLD
IO100NDB3V1
IO100PDB3V1
IO96NDB3V1
IO98PDB3V1
Revision 13
4-39
Package Pin Assignments
FG896
A1 Ball Pad Corner
30 29 28 27 26 2524 23 22 21 20 1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
4-40
Revision 13
ProASIC3E Flash Family FPGAs
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
A2
A3
GND
GND
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
GEB1/IO235PPB6V0
VCC
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
IO198PDB5V0
IO192NDB4V4
IO192PDB4V4
IO178NDB4V3
IO178PDB4V3
IO174NDB4V2
IO162NPB4V1
VCC
A4
IO14NPB0V1
GND
IO226PPB5V4
VCCIB5
A5
A6
IO07NPB0V0
GND
VCCIB5
A7
VCCIB5
A8
IO09NDB0V1
IO17NDB0V2
IO17PDB0V2
IO21NDB0V2
IO21PDB0V2
IO33NDB0V4
IO33PDB0V4
IO35NDB0V4
IO35PDB0V4
IO41NDB1V0
IO43NDB1V0
IO43PDB1V0
IO45NDB1V0
IO45PDB1V0
IO57NDB1V2
IO57PDB1V2
GND
VCCIB5
A9
VCCIB4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
VCCIB4
VCCPLD
VCCIB4
VCCIB3
VCCIB4
IO150PDB3V4
IO148PDB3V4
IO147NDB3V4
IO145PDB3V3
IO143PDB3V3
IO137PDB3V2
IO254PDB6V2
IO254NDB6V2
IO240PDB6V0
GEC1/IO236PDB6V0
IO237PDB6V0
IO237NDB6V0
VCOMPLE
IO174PDB4V2
VCC
IO142NPB3V3
IO144NDB3V3
IO144PDB3V3
IO146NDB3V4
IO146PDB3V4
IO147PDB3V4
IO139NDB3V3
IO139PDB3V3
IO133NDB3V2
IO256NDB6V2
IO244PDB6V1
IO244NDB6V1
IO241PDB6V0
IO241NDB6V0
IO243NPB6V1
VCCIB6
AC2
AC3
AC4
AC5
AC6
AC7
IO69PPB1V3
GND
AB2
AC8
GND
AB3
AC9
IO226NPB5V4
IO222NDB5V3
IO216NPB5V2
IO210NPB5V2
IO204NDB5V1
IO204PDB5V1
IO194NDB5V0
IO188NDB4V4
IO188PDB4V4
IO182PPB4V3
IO170NPB4V2
IO164NDB4V1
GBC1/IO79PPB1V4
GND
AB4
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AB5
GND
AB6
IO256PDB6V2
IO248PDB6V1
IO248NDB6V1
IO246NDB6V1
GEA1/IO234PDB6V0
GEA0/IO234NDB6V0
IO243PPB6V1
IO245NDB6V1
AB7
AB8
VCCPLE
AB9
VCC
AB10
AB11
AB12
AB13
AB14
IO222PDB5V3
IO218PPB5V3
IO206NDB5V1
IO206PDB5V1
IO198NDB5V0
Revision 13
4-41
Package Pin Assignments
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
IO164PDB4V1
IO162PPB4V1
GND
AD27
AD28
AD29
AD30
AE1
GDA0/IO153NDB3V4
GDC0/IO151NDB3V4
GDC1/IO151PDB3V4
GND
AF3
AF4
VCCIB6
IO220NPB5V3
VCC
AF5
VCOMPLD
AF6
IO228NDB5V4
VCCIB5
IO150NDB3V4
IO148NDB3V4
GDA1/IO153PDB3V4
IO145NDB3V3
IO143NDB3V3
IO137NDB3V2
GND
IO242PPB6V1
VCC
AF7
AE2
AF8
IO230PDB5V4
IO229NDB5V4
IO229PDB5V4
IO214PPB5V2
IO208NDB5V1
IO208PDB5V1
IO200PDB5V0
IO196NDB5V0
IO186NDB4V4
IO186PDB4V4
IO180NDB4V3
IO180PDB4V3
IO168NDB4V1
IO168PDB4V1
IO160NDB4V0
IO158NPB4V0
VCCIB4
AE3
IO239PDB6V0
IO239NDB6V0
VMV6
AF9
AE4
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AE5
AE6
GND
AE7
GNDQ
AD2
IO242NPB6V1
IO240NDB6V0
GEC0/IO236NDB6V0
VCCIB6
AE8
IO230NDB5V4
IO224NPB5V3
IO214NPB5V2
IO212NDB5V2
IO212PDB5V2
IO202NPB5V1
IO200NDB5V0
IO196PDB5V0
IO190NDB4V4
IO184PDB4V3
IO184NDB4V3
IO172PDB4V2
IO172NDB4V2
IO166NDB4V1
IO160PDB4V0
GNDQ
AD3
AE9
AD4
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AF1
AD5
AD6
GNDQ
AD7
VCC
AD8
VMV5
AD9
VCCIB5
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
IO224PPB5V3
IO218NPB5V3
IO216PPB5V2
IO210PPB5V2
IO202PPB5V1
IO194PDB5V0
IO190PDB4V4
IO182NPB4V3
IO176NDB4V2
IO176PDB4V2
IO170PPB4V2
IO166PDB4V1
VCCIB4
IO154NPB4V0
VCC
TDO
VCCIB3
GNDQ
VMV4
GND
GND
IO238NPB6V0
VCC
GDB0/IO152NDB3V4
GDB1/IO152PDB3V4
VMV3
IO232NPB5V4
GND
TCK
VCC
IO220PPB5V3
IO228PDB5V4
IO231NDB5V4
GEC2/IO231PDB5V4
VCC
IO149PDB3V4
GND
TRST
VCCIB3
AF2
IO238PPB6V0
AG8
4-42
Revision 13
ProASIC3E Flash Family FPGAs
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
IO225NPB5V3
IO223NPB5V3
IO221PDB5V3
IO221NDB5V3
IO205NPB5V1
IO199NDB5V0
IO199PDB5V0
IO187NDB4V4
IO187PDB4V4
IO181NDB4V3
IO171PPB4V2
IO165NPB4V1
IO161NPB4V0
IO159NDB4V0
IO159PDB4V0
IO158PPB4V0
GDB2/IO155PDB4V0
GDA2/IO154PPB4V0
GND
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AJ1
IO195NDB5V0
IO185NDB4V3
IO185PDB4V3
IO181PDB4V3
IO177NDB4V2
IO171NPB4V2
IO165PPB4V1
IO161PPB4V0
IO157NDB4V0
IO157PDB4V0
IO155NDB4V0
VCCIB4
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK2
IO173PDB4V2
IO163NDB4V1
IO163PDB4V1
IO167NPB4V1
VCC
IO156NPB4V0
VCC
TMS
GND
GND
GND
AK3
GND
TDI
AK4
IO217PPB5V2
GND
VCC
AK5
VPUMP
AK6
IO215PPB5V2
GND
GND
AK7
GND
AK8
IO207NDB5V1
IO207PDB5V1
IO201NDB5V0
IO201PDB5V0
IO193NDB4V4
IO193PDB4V4
IO197PDB5V0
IO191NDB4V4
IO191PDB4V4
IO189NDB4V4
IO189PDB4V4
IO179PPB4V3
IO175NDB4V2
IO175PDB4V2
IO169NDB4V1
IO169PDB4V1
GND
AJ2
GND
AK9
AJ3
GEA2/IO233PPB5V4
VCC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
VJTAG
AJ4
VCC
AJ5
IO217NPB5V2
VCC
IO149NDB3V4
GND
AJ6
AJ7
IO215NPB5V2
IO213NDB5V2
IO213PDB5V2
IO209NDB5V1
IO209PDB5V1
IO203NDB5V1
IO203PDB5V1
IO197NDB5V0
IO195PDB5V0
IO183NDB4V3
IO183PDB4V3
IO179NPB4V3
IO177PDB4V2
IO173NDB4V2
AH2
IO233NPB5V4
VCC
AJ8
AH3
AJ9
AH4
GEB2/IO232PPB5V4
VCCIB5
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AH5
AH6
IO219NDB5V3
IO219PDB5V3
IO227NDB5V4
IO227PDB5V4
IO225PPB5V3
IO223PPB5V3
IO211NDB5V2
IO211PDB5V2
IO205PPB5V1
AH7
AH8
AH9
AH10
AH11
AH12
AH13
AH14
IO167PPB4V1
GND
GDC2/IO156PPB4V0
Revision 13
4-43
Package Pin Assignments
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
AK28
AK29
B1
GND
GND
C5
C6
VCCIB0
IO03PDB0V0
IO03NDB0V0
GAB1/IO01PDB0V0
IO05PDB0V0
IO15NPB0V1
IO25NDB0V3
IO25PDB0V3
IO31NPB0V3
IO27NDB0V3
IO39NDB0V4
IO39PDB0V4
IO55PPB1V1
IO51PDB1V1
IO59NDB1V2
IO63NDB1V2
IO63PDB1V2
IO67NDB1V3
IO67PDB1V3
IO75NDB1V4
IO75PDB1V4
VCCIB1
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
E1
IO11PDB0V1
IO23NDB0V2
IO23PDB0V2
IO27PDB0V3
IO40PDB0V4
IO47NDB1V0
IO47PDB1V0
IO55NPB1V1
IO65NDB1V3
IO65PDB1V3
IO71NDB1V3
IO71PDB1V3
IO73NDB1V4
IO73PDB1V4
IO74NDB1V4
GBB0/IO80NPB1V4
GND
GND
C7
B2
GND
C8
B3
GAA2/IO309PPB7V4
VCC
C9
B4
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
B5
IO14PPB0V1
VCC
B6
B7
IO07PPB0V0
IO09PDB0V1
IO15PPB0V1
IO19NDB0V2
IO19PDB0V2
IO29NDB0V3
IO29PDB0V3
IO31PPB0V3
IO37NDB0V4
IO37PDB0V4
IO41PDB1V0
IO51NDB1V1
IO59PDB1V2
IO53PDB1V1
IO53NDB1V1
IO61NDB1V2
IO61PDB1V2
IO69NPB1V3
VCC
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
GBA0/IO81NPB1V4
VCC
GBA2/IO82PPB2V0
GND
E2
IO303NPB7V3
VCCIB7
IO64PPB1V2
VCC
E3
E4
IO305PPB7V3
VCC
GBA1/IO81PPB1V4
GND
E5
E6
GAC0/IO02NDB0V0
VCCIB0
IO303PPB7V3
VCC
E7
GBC0/IO79NPB1V4
VCC
D2
E8
IO06PPB0V0
IO24NDB0V2
IO24PDB0V2
IO13NDB0V1
IO13PDB0V1
IO34NDB0V4
IO34PDB0V4
IO40NDB0V4
IO49NDB1V1
D3
IO305NPB7V3
GND
E9
IO64NPB1V2
GND
D4
E10
E11
E12
E13
E14
E15
E16
D5
GAA1/IO00PPB0V0
GAC1/IO02PDB0V0
IO06NPB0V0
GAB0/IO01NDB0V0
IO05NDB0V0
IO11NDB0V1
GND
D6
GND
D7
C2
IO309NPB7V4
VCC
D8
C3
D9
C4
GAA0/IO00NPB0V0
D10
4-44
Revision 13
ProASIC3E Flash Family FPGAs
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
F1
IO49PDB1V1
IO50PDB1V1
IO58PDB1V2
IO60NDB1V2
IO77PDB1V4
IO68NDB1V3
IO68PDB1V3
VCCIB1
F23
F24
F25
F26
F27
F28
F29
F30
G1
IO72PDB1V3
GNDQ
G29
G30
H1
IO100PPB2V2
GND
GND
IO294PDB7V2
IO294NDB7V2
IO300NDB7V3
IO300PDB7V3
IO295PDB7V2
IO299PDB7V3
VCOMPLA
VMV2
H2
IO86PDB2V0
IO92PDB2V1
VCC
H3
H4
H5
IO100NPB2V2
GND
H6
IO74PDB1V4
VCC
H7
G2
IO296NPB7V2
IO306NDB7V4
IO297NDB7V2
VCCIB7
H8
GND
GBB1/IO80PPB1V4
VCCIB2
G3
H9
IO08NDB0V0
IO08PDB0V0
IO18PDB0V2
IO26NPB0V3
IO28NDB0V3
IO28PDB0V3
IO38PPB0V4
IO42NDB1V0
IO52NDB1V1
IO52PDB1V1
IO62NDB1V2
IO62PDB1V2
IO70NDB1V3
IO70PDB1V3
GND
G4
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
J1
IO82NPB2V0
GND
G5
G6
GNDQ
IO296PPB7V2
VCC
G7
VCC
F2
G8
VMV0
F3
IO306PDB7V4
IO297PDB7V2
VMV7
G9
VCCIB0
F4
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
IO10NDB0V1
IO16NDB0V1
IO22PDB0V2
IO26PPB0V3
IO38NPB0V4
IO36NDB0V4
IO46NDB1V0
IO46PDB1V0
IO56NDB1V1
IO56PDB1V1
IO66NDB1V3
IO66PDB1V3
VCCIB1
F5
F6
GND
F7
GNDQ
F8
IO12NDB0V1
IO12PDB0V1
IO10PDB0V1
IO16PDB0V1
IO22NDB0V2
IO30NDB0V3
IO30PDB0V3
IO36PDB0V4
IO48NDB1V0
IO48PDB1V0
IO50NDB1V1
IO58NDB1V2
IO60PDB1V2
IO77NDB1V4
IO72NDB1V3
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
VCOMPLB
GBC2/IO84PDB2V0
IO84NDB2V0
IO96PDB2V1
IO96NDB2V1
IO89PDB2V0
IO89NDB2V0
IO290NDB7V2
IO290PDB7V2
IO302NDB7V3
IO302PDB7V3
VMV1
VCC
GNDQ
VCCIB2
J2
IO86NDB2V0
IO92NDB2V1
J3
J4
Revision 13
4-45
Package Pin Assignments
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
J5
J6
IO295NDB7V2
IO299NDB7V3
VCCIB7
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
L1
IO04PPB0V0
VCCIB0
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
M1
VCC
VCC
J7
VCCIB0
VCC
J8
VCCPLA
VCCIB0
VCC
J9
VCC
VCCIB0
IO78NPB1V4
IO104NPB2V2
IO98NDB2V2
IO98PDB2V2
IO87PDB2V0
IO87NDB2V0
IO97PDB2V1
IO101PDB2V2
IO103PDB2V2
IO119NDB3V0
IO282NDB7V1
IO282PDB7V1
IO292NDB7V2
IO292PDB7V2
IO283NDB7V1
IO285PDB7V1
IO287PDB7V1
IO289PDB7V1
IO289NDB7V1
VCCIB7
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
IO04NPB0V0
IO18NDB0V2
IO20NDB0V2
IO20PDB0V2
IO32NDB0V3
IO32PDB0V3
IO42PDB1V0
IO44NDB1V0
IO44PDB1V0
IO54NDB1V1
IO54PDB1V1
IO76NPB1V4
VCC
VCCIB1
VCCIB1
VCCIB1
VCCIB1
IO76PPB1V4
VCC
IO78PPB1V4
IO88NDB2V0
IO88PDB2V0
IO94PDB2V1
IO94NDB2V1
IO85PDB2V0
IO85NDB2V0
IO93PDB2V1
IO93NDB2V1
IO286NDB7V1
IO286PDB7V1
IO298NDB7V3
IO298PDB7V3
IO283PDB7V1
IO291NDB7V2
IO291PDB7V2
IO293PDB7V2
IO293NDB7V2
IO307NPB7V4
VCC
M2
M3
M4
VCCPLB
M5
VCCIB2
M6
IO90PDB2V1
IO90NDB2V1
GBB2/IO83PDB2V0
IO83NDB2V0
IO91PDB2V1
IO91NDB2V1
IO288NDB7V1
IO288PDB7V1
IO304NDB7V3
IO304PDB7V3
GAB2/IO308PDB7V4
IO308NDB7V4
IO301PDB7V3
IO301NDB7V3
GAC2/IO307PPB7V4
VCC
M7
L2
M8
L3
M9
L4
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
L5
VCC
L6
GND
L7
GND
K2
L8
GND
K3
L9
GND
K4
L10
L11
L12
L13
L14
L15
L16
GND
K5
GND
K6
VCC
GND
K7
VCC
GND
K8
VCC
VCC
K9
VCC
VCCIB2
K10
VCC
NC
4-46
Revision 13
ProASIC3E Flash Family FPGAs
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
M23
M24
M25
M26
M27
M28
M29
M30
N1
IO104PPB2V2
IO102PDB2V2
IO102NDB2V2
IO95PDB2V1
IO97NDB2V1
IO101NDB2V2
IO103NDB2V2
IO119PDB3V0
IO276PDB7V0
IO278PDB7V0
IO280PDB7V0
IO284PDB7V1
IO279PDB7V0
IO285NDB7V1
IO287NDB7V1
IO281NDB7V0
IO281PDB7V0
VCCIB7
N29
N30
P1
IO107PDB2V3
IO107NDB2V3
IO276NDB7V0
IO278NDB7V0
IO280NDB7V0
IO284NDB7V1
IO279NDB7V0
GFC1/IO275PDB7V0
GFC0/IO275NDB7V0
IO277PDB7V0
IO277NDB7V0
VCCIB7
R5
R6
GFB0/IO274NPB7V0
IO271NDB6V4
GFB2/IO271PDB6V4
IO269PDB6V4
IO269NDB6V4
VCCIB7
R7
P2
R8
P3
R9
P4
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
T1
P5
VCC
P6
GND
P7
GND
N2
P8
GND
N3
P9
GND
N4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
R1
GND
N5
VCC
GND
N6
GND
GND
N7
GND
GND
N8
GND
VCC
N9
GND
VCCIB2
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
GND
GCC0/IO112NDB2V3
GCB2/IO116PDB3V0
IO118PDB3V0
IO111PPB2V3
IO122PPB3V1
GCA0/IO114NPB3V0
VCOMPLC
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
VCCIB2
GND
GCC1/IO112PDB2V3
IO110PDB2V3
IO110NDB2V3
IO109PPB2V3
IO111NPB2V3
IO105PDB2V2
IO105NDB2V2
GCC2/IO117PDB3V0
IO117NDB3V0
GFC2/IO270PDB6V4
GFB1/IO274PPB7V0
VCOMPLF
GND
GCB1/IO113PPB2V3
IO115NPB3V0
IO270NDB6V4
VCCPLF
GND
GND
VCC
T2
VCCIB2
T3
GFA2/IO272PPB6V4
GFA1/IO273PDB6V4
IO272NPB6V4
IO267NDB6V4
IO267PDB6V4
IO265PDB6V3
IO263PDB6V3
VCCIB6
IO106NDB2V3
IO106PDB2V3
IO108PDB2V3
IO108NDB2V3
IO95NDB2V1
IO99NDB2V2
IO99PDB2V2
T4
T5
T6
T7
R2
T8
R3
T9
R4
GFA0/IO273NDB6V4
T10
Revision 13
4-47
Package Pin Assignments
FG896
FG896
FG896
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
U1
VCC
GND
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
V1
GND
GND
V23
V24
V25
V26
V27
V28
V29
V30
W1
IO128NDB3V1
IO132PDB3V2
IO130PPB3V2
IO126NDB3V1
IO129NDB3V1
IO127NDB3V1
IO125NDB3V1
IO123PDB3V1
IO266NDB6V4
IO262NDB6V3
IO260NDB6V3
IO252NDB6V2
IO251NDB6V2
IO251PDB6V2
IO255NDB6V2
IO249PPB6V1
IO253PDB6V2
VCCIB6
GND
GND
GND
VCC
GND
VCCIB3
GND
IO120PDB3V0
IO128PDB3V1
IO124PDB3V1
IO124NDB3V1
IO126PDB3V1
IO129PDB3V1
IO127PDB3V1
IO125PDB3V1
IO121NDB3V0
IO268NDB6V4
IO262PDB6V3
IO260PDB6V3
IO252PDB6V2
IO257NPB6V2
IO261NPB6V3
IO255PDB6V2
IO259PDB6V3
IO259NDB6V3
VCCIB6
GND
GND
GND
VCC
W2
VCCIB3
W3
IO109NPB2V3
IO116NDB3V0
IO118NDB3V0
IO122NPB3V1
GCA1/IO114PPB3V0
GCB0/IO113NPB2V3
GCA2/IO115PPB3V0
VCCPLC
W4
W5
W6
W7
V2
W8
V3
W9
V4
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
V5
VCC
IO121PDB3V0
IO268PDB6V4
IO264NDB6V3
IO264PDB6V3
IO258PDB6V3
IO258NDB6V3
IO257PPB6V2
IO261PPB6V3
IO265NDB6V3
IO263NDB6V3
VCCIB6
V6
GND
V7
GND
U2
V8
GND
U3
V9
GND
U4
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
GND
U5
VCC
GND
U6
GND
GND
U7
GND
GND
U8
GND
VCC
U9
GND
VCCIB3
U10
U11
U12
U13
U14
U15
U16
GND
IO134PDB3V2
IO138PDB3V3
IO132NDB3V2
IO136NPB3V2
IO130NPB3V2
IO141PDB3V3
IO135PDB3V2
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
VCCIB3
GND
IO120NDB3V0
4-48
Revision 13
ProASIC3E Flash Family FPGAs
FG896
Pin Number A3PE3000 Function
W29
W30
Y1
IO131PDB3V2
IO123NDB3V1
IO266PDB6V4
IO250PDB6V2
IO250NDB6V2
IO246PDB6V1
IO247NDB6V1
IO247PDB6V1
IO249NPB6V1
IO245PDB6V1
IO253NDB6V2
GEB0/IO235NPB6V0
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
IO142PPB3V3
IO134NDB3V2
IO138NDB3V3
IO140NDB3V3
IO140PDB3V3
IO136PPB3V2
IO141NDB3V3
IO135NDB3V2
IO131NDB3V2
IO133PDB3V2
Revision 13
4-49
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3E datasheet.
Revision
Changes
Page
Revision 13
(January 2013)
In the "Features and Benefits" section, updated the Clock Conditioning Circuit
(CCC) and PLL Wide Input Frequency Range from ’1.5 MHz to 200 MHz’ to
’1.5MHz to 350 MHz’ based on Table 2-98 • ProASIC3E CCC/PLL Specification
(SAR 22196).
1-I
The "ProASIC3E Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43220).
1-III
Added a note to Table 2-2 • Recommended Operating Conditions 1 (SAR 42716):
The programming temperature range supported is Tambient = 0°C to 85°C.
2-2
The note in Table 2-98 • ProASIC3E CCC/PLL Specification referring the reader
to SmartGen was revised to refer instead to the online help associated with the
core (SAR 42571).
2-69
Libero Integrated Design Environment (IDE) was changed to Libero System-on-
Chip (SoC) throughout the document (SAR 40285).
NA
1-1
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
Revision 12
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support
read-back of programmed data.
Revision 11
(August 2012)
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.
See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further
information." to Table 2-1 • Absolute Maximum Ratings and Table 2-2
• Recommended Operating Conditions 1 (SAR 38322).
2-1
2-2
The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was
changed from 25 mA to 20 mA in the following tables (SAR 31924):
2-16
2-19
2-20
2-38
2-39
Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels
Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-19 • I/O Output Buffer Maximum Resistances1
Table 2-48 • Minimum and Maximum DC Input and Output Levels (3.3 V GTL)
Table 2-51 • Minimum and Maximum DC Input and Output Levels (2.5 V GTL)
Also added note stating "Output drive strength is below JEDEC specification." for
Tables 2-17 and 2-19.
Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were
corrected from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in
table Table 2-13 (SAR 39714).
Table 2-22 • Duration of Short Circuit Event Before Failure was revised to change
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37934).
2-22
2-29
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR
34796):
"It uses a 5 V–tolerant input buffer and push-pull output buffer." This change was
made in revision 10 and omitted from the change table in error.
Revision 13
5-1
Datasheet Information
Revision
Changes
Page
Revision 11
(continued)
Figure 2-11 • AC Loading was updated to match tables in the "Summary of I/O
Timing Characteristics – Default I/O Software Settings" section (SAR 34889).
2-37
In Table 2-81 • Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
37222).
2-51
Figure 2-47 • FIFO Read and Figure 2-48 • FIFO Write are new (SAR 34848).
2-78
3-1
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" chapter: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from
the output buffer VCCI domain" and replaced with “Within the package, the VMV
plane biases the input stage of the I/Os in the I/O banks” (SAR 38322). The
datasheet mentions that "VMV pins must be connected to the corresponding
VCCI pins" for an ESD enhancement.
Revision 10
(March 2012)
The "In-System Programming (ISP) and Security" section and "Security" section
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in
the industry (SAR 34669).
I, 1-1
III
The Y security option and Licensed DPA Logo were added to the "ProASIC3E
Ordering Information" section. The trademarked Licensed DPA Logo identifies
that a product is covered by a DPA counter-measures license from Cryptography
Research (SAR 34727).
The following sentence was removed from the "Advanced Architecture" section:
1-3
"In addition, extensive on-chip programming circuitry allows for rapid, single-
voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG
interface" (SAR 34689).
The "Specifying I/O States During Programming" section is new (SAR 34699).
1-6
2-2
VCCPLL in Table 2-2 • Recommended Operating Conditions 1 was corrected
from "1.4 to 1.6 V" to "1.425 to 1.575 V" (SAR 33851).
The TJ symbol was added to the table and notes regarding TA and TJ were
removed. The second of two parameters in the VCCI and VMV row, called "3.3 V
DC supply voltage," was corrected to "3.0 V DC supply voltage" (SAR 37227).
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3E
FPGA Fabric User's Guide (SAR 34735).
2-9
t
DOUT was corrected to tDIN in Figure 2-3 • Input Buffer Timing Model and Delays
2-13
2-19
(example) (SAR 37109).
The typo related to the values for 3.3 V LVCMOS Wide Range in Table 2-17
• Summary of I/O Timing Characteristics—Software Default Settings was
corrected (SAR 37227).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics 2-18, 2-26
– Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range"
section and tables were revised for clarification. They now state that the minimum
drive strength for the default software configuration when run in wide range is
±100 µA. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 34763).
5-2
Revision 13
ProASIC3E Flash Family FPGAs
Revision
Changes
Page
Revision 10
(continued)
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-19 • I/O Output Buffer Maximum
Resistances1 and Table 2-21 • I/O Short Currents IOSH/IOSL was replaced by
"Same as regular 3.3 V LVCMOS" (SAR 33853).
2-20,
2-22
3.3 V LVCMOS Wide Range information was separated from regular 3.3 V
LVCMOS and placed into its own new section, "3.3 V LVCMOS Wide Range".
Values of IOSH and IOSL were added in Table 2-29 • Minimum and Maximum DC
Input and Output Levels (SAR 33853).
The formulas in the table notes for Table 2-20 • I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34755).
2-21
2-24
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default
I/O Software Settings" section (SAR 34889).
The titles and subtitles for Table 2-31 • 3.3 V LVCMOS Wide Range High Slew 2-27, 2-28
and Table 2-32 • 3.3 V LVCMOS Wide Range Low Slew were corrected (SAR
37227).
The following notes were removed from Table 2-78 • LVDS Minimum and
Maximum DC Input and Output Levels (SAR 34812):
2-49
±5%
Differential input voltage = ±350 mV
Minimum pulse width High and Low values were added to the tables in the
"Global Tree Timing Characteristics" section. The maximum frequency for global
clock parameter was removed from these tables because a frequency on the
global is only an indication of what the global network can do. There are other
limiters such as the SRAM, I/Os, and PLL. SmartTime software should be used to
determine the design frequency (SAR 36957).
2-67
A note was added to Table 2-98 • ProASIC3E CCC/PLL Specification indicating
that when the CCC/PLL core is generated by Microsemi core generator software,
not all delay values of the specified delay increments are available (SAR 34824).
2-69
The following figures were deleted. Reference was made to a new application
note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based
cSoCs and FPGAs, which covers these cases in detail (SAR 34872).
2-72,
2-75,
2-79,
2-81
Figure 2-44 • Write Access after Write onto Same Address
Figure 2-45 • Read Access after Write onto Same Address
Figure 2-46 • Write Access after Read onto Same Address
The port names in the SRAM "Timing Waveforms", SRAM "Timing
Characteristics" tables, Figure 2-49 • FIFO Reset, and the FIFO "Timing
Characteristics" tables were revised to ensure consistency with the software
names (SAR 35750).
The "Pin Descriptions and Packaging" chapter is new (SAR 34771).
3-1
4-1
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34771).
Pin E6 for the FG256 package was corrected from VvB0 to VCCIB0 (SARs
30364, 31597, 26243).
4-9
July 2010
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The "ProASIC3E Device Status" table on page II indicates the status for each
device in the device family.
N/A
Revision 13
5-3
Datasheet Information
Revision
Changes
Page
Revision 9 (Aug 2009) All references to speed grade –F have been removed from this document.
N/A
Product Brief v1.2
The "Pro I/Os with Advanced I/O Standards" section was revised to add
definitions of hot-swap and cold-sparing.
1-6
DC and Switching 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
N/A
Characteristics v1.3
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
N/A
–F was removed from the datasheet. The speed grade is no longer supported.
N/A
2-2
In the Table 2-2 • Recommended Operating Conditions 1 "3.0 V DC supply
voltage" and note 4 are new.
The Table 2-4 • Overshoot and Undershoot Limits 1 table was updated.
2-3
2-5
The Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
table was updated.
There are new parameters and data was updated in the Table 2-99 • RAM4K9
table.
2-75
2-76
1-II
There are new parameters and data was updated in the Table 2-100
• RAM512X18 table.
Revision 8 (Feb 2008) Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions is new.
Product Brief v1.1
Revision 7 (Jun 2008) The title of Table 2-4 • Overshoot and Undershoot Limits 1 was modified to
2-3
remove "as measured on quiet I/Os." Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
Characteristics v1.2
DC and Switching
Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels was
updated.
2-49
4-17
4-17
Revision 6 (Jun 2008) The A3PE600 "FG484" table was missing G22. The pin and its function were
added to the table.
Revision 5 (Jun 2008) The naming conventions changed for the following pins in the "FG484" for the
A3PE600:
Packaging v1.4
Pin Number
New Function Name
IO45PPB2V1
J19
K20
M2
N1
IO45NPB2V1
IO114NPB6V1
IO114PPB6V1
N4
GFC2/IO115PPB6V1
IO115NPB6V1
P3
Revision 4 (Apr 2008) The product brief portion of the datasheet was divided into two sections and given
N/A
a version number, starting at v1.0. The first section of the document includes
features, benefits, ordering information, and temperature and speed grade
offerings. The second section is a device family overview.
Product Brief v1.0
Packaging v1.3
The "FG324" package diagram was replaced.
4-12
5-4
Revision 13
ProASIC3E Flash Family FPGAs
Revision
Changes
Page
Revision 3 (Apr 2008) The following pins had duplicates and the extra pins were deleted from the
4-6
"PQ208" A3PE3000 table:
Packaging v1.2
36, 62, 171
Note: There were no pin function changes in this update.
The following pins had duplicates and the extra pins were deleted from the
"FG324" table:
4-12
E2, E3, E16, E17, P2, P3, T16, U17
Note: There were no pin function changes in this update.
The "FG256" pin table was updated for the A3PE600 device because the old PAT
were based on the IFX die, and this is the final UMC die version.
4-9
The "FG484" was updated for the A3PE600 device because the old PAT were
based on the IFX die, and this is the final UMC die version.
4-17
4-41
The following pins had duplicates and the extra pins were deleted from the
"FG896" table:
AD6, AE5, AE28, AF29, F5, F26, G6, G25
Note: There were no pin function changes in this update.
Revision 2 (Mar 2008) The FG324 package was added to the "ProASIC3E Product Family" table, the I, II, IV
"I/Os Per Package1" table, and the "Temperature Grade Offerings" table for
A3PE3000.
Product Brief rev. 1
Revision 1 (Feb 2008) In Table 2-3 • Flash Programming Limits – Retention, Storage and Operating
2-2
Temperature 1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
Characteristics v1.1
DC and Switching
The "PLL Behavior at Brownout Condition" section is new.
2-4
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
2-10
In Table 2-14 • Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said TJ and it was corrected and changed to TA.
2-17
2-69
2-82
In Table 2-98 • ProASIC3E CCC/PLL Specification, the SCLK parameter and note
1 are new.
Table 2-103 • JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
Revision 1 (cont’d)
The "PQ208" pin table for A3PE3000 was updated.
The "FG324" pin table for A3PE3000 is new.
The "FG484" pin table for A3PE3000 is new.
The "FG896" pin table for A3PE3000 is new.
4-6
4-13
4-27
4-41
N/A
Packaging v1.1
Revision 0 (Jan 2008) This document was previously in datasheet v2.1. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700098-001-0.
v2.1
CoreMP7 information was removed from the "Features and Benefits" section.
i
(July 2007)
The M1 device part numbers have been updated in Table 4 • ProASIC3E
Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed
Grade and Temperature Grade Matrix", and "Speed Grade and Temperature
Grade Matrix".
ii, iii,
iv, iv
Revision 13
5-5
Datasheet Information
Revision
Changes
Page
v2.1
(continued)
The words "ambient temperature" were added to the temperature range in the iii, iv, iv
"Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix",
and "Speed Grade and Temperature Grade Matrix" sections.
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
i
The caption "Main (chip)" in Figure 2-9 • Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)."
2-9
The TJ parameter in Table 3-2 • Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
2-15
iii
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
v2.0
(April 2007)
In the "Temperature Grade Offerings" section, Ambient was deleted.
Ambient was deleted from "Temperature Grade Offerings".
iii
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
The "PLL Macro" section was updated to include power-up information.
Table 2-13 • ProASIC3E CCC/PLL Specification was updated.
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
iv
2-15
2-30
2-18
2-21
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
The "RESET" section was updated with read and write information.
The "RESET" section was updated with read and write information.
2-25
2-25
2-28
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
2-64
2-40
Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
2-50
2-51
The "VPUMP Programming Supply Voltage" section was updated.
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
VJTAG was deleted from the "TCK Test Clock" section.
2-51
2-51
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
3-2
3-5
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os).
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
5-6
Revision 13
ProASIC3E Flash Family FPGAs
Revision
Changes
Page
v2.0
(continued)
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-5
Table 3-5 • Package Thermal Resistivities was updated.
3-5
3-8
Table 3-10 • Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
tWRO and tCCKH were added to Table 3-94 • RAM4K9 and Table 3-74 to
3-95 • RAM512X18.
3-74
The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure 3-43 • Write Access After Write onto Same Address, Figure 3-44 • Read 3-71 to 3-
Access After Write onto Same Address, and Figure 3-45 • Write Access After
Read onto Same Address are new.
73
Figure 3-53 • Timing Diagram was updated.
3-80
N/A
Notes were added to the package diagrams identifying if they were top or bottom
view.
The A3PE1500 "208-Pin PQFP" table is new.
The A3PE1500 "484-Pin FBGA" table is new.
The A3PE1500 "A3PE1500 Function" table is new.
4-4
4-18
4-24
ii
Advance v0.6
(January 2007)
In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
changed for the FG484 and FG676 packages.
Advance v0.5
(April 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
N/A
2-8
2-28
2-24
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
2-21
2-25
2-25
2-25
2-27
N/A
The "WCLK and RCLK" section was updated.
The "RESET" section was updated.
The "RESET" section was updated.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
N/A
2-8
2-28
2-24
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
2-21
2-25
2-25
The "WCLK and RCLK" section was updated.
Revision 13
5-7
Datasheet Information
Revision
Changes
Page
Advance v0.5
(continued)
The "RESET" section was updated.
The "RESET" section was updated.
2-25
2-27
2-28
2-29
The "Introduction" of the "Introduction" section was updated.
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 • VCCI Voltages and Compatible Standards
Table 2-35 • ProASIC3E I/O Features was updated.
2-54
2-32
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
2-64
2-64
2-41
2-55
Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
The notes in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3E Devices were updated.
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
A footnote was added to Table 2-37 • Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength
and high slew selected).
Table 2-48 • ProASIC3E I/O Attributes vs. I/O Standard Applications
2-81
2-85
Table 2-55 • ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)
Settings
The "x" was updated in the "Pin Descriptions" section.
2-50
2-50
2-50
The "VCC Core Supply Voltage" pin description was updated.
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.
2-24
2-30
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table
2-13 • ProASIC3E CCC/PLL Specification.
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
2-28
2-64
The LVPECL specification in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3E Devices was updated.
Table 2-15 • Levels of Hot-Swap Support was updated.
The "Cold-Sparing Support" section was updated.
2-34
2-34
2-35
2-50
"Electrostatic Discharge (ESD) Protection" section was updated.
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
5-8
Revision 13
ProASIC3E Flash Family FPGAs
Revision
Changes
Page
Advance v0.5
(continued)
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
2-51
2-53
2-54
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
The "Programming" section was updated to include information concerning
serialization.
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
The "DC and Switching Characteristics" chapter was updated with new Starting
information.
on page
3-1
Table 3-6 was updated.
3-5
3-8
In Table 3-10, PAC4 was updated.
Table 3-19 was updated.
3-20
3-23
The note in Table 3-24 was updated.
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-26 to
3-64
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-74 to
3-79
FTCKMAX was updated in Table 3-98.
3-80
ii
Advance v0.4
(October 2005)
The "Packaging Tables" table was updated.
Advance v0.3
Figure 2-11 was updated.
2-9
2-9
The "Clock Resources (VersaNets)" section was updated.
The "VersaNet Global Networks and Spine Access" section was updated.
The "PLL Macro" section was updated.
Figure 2-27 was updated.
2-9
2-15
2-28
2-19
2-25
2-25
2-27
2-51
2-31
2-34
2-64
2-81
2-51
2-50
3-6
Figure 2-20 was updated.
Table 2-5 was updated.
Table 2-6 was updated.
The "FIFO Flag Usage Considerations" section was updated.
Table 2-33 was updated.
Figure 2-24 was updated.
The "Cold-Sparing Support" section is new.
Table 2-45 was updated.
Table 2-48 was updated.
Pin descriptions in the "JTAG Pins" section were updated.
The "Pin Descriptions" section was updated.
Table 3-7 was updated.
Revision 13
5-9
Datasheet Information
Revision
Changes
The "Methodology" section was updated.
Page
3-9
Advance v0.3
(continued)
The A3PE3000 "208-Pin PQFP" pin table was updated.
4-6
5-10
Revision 13
ProASIC3E Flash Family FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "ProASIC3E Device Status" table on page II, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
Revision 13
5-11
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
51700097-13/01.13
相关型号:
©2020 ICPDF网 联系我们和版权申明