A42MX36-BG272 [MICROSEMI]
Field Programmable Gate Array, 2438 CLBs, 54000 Gates, 73MHz, CMOS, PBGA272, PLASTIC, BGA-272;型号: | A42MX36-BG272 |
厂家: | Microsemi |
描述: | Field Programmable Gate Array, 2438 CLBs, 54000 Gates, 73MHz, CMOS, PBGA272, PLASTIC, BGA-272 时钟 栅 可编程逻辑 |
文件: | 总143页 (文件大小:7579K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Revision 12
40MX and 42MX FPGA Families
HiRel Features
Features
High Capacity
•
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
•
•
•
•
•
Single-Chip ASIC Alternative
•
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
•
•
QML Certification
Ceramic Devices Available to DSCC SMD
Up to 202 User-Programmable I/O Pins
Ease of Integration
•
Mixed-Voltage Operation (5.0 V or 3.3 V for core and
I/Os), with PCI-Compliant I/Os
High Performance
•
•
•
•
•
5.6 ns Clock-to-Out
•
•
•
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
7.5 ns 35-Bit Address Decode
•
•
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
Clock-to-Out
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
348
516
2
–
624
928
2
–
954
1,410
2
10
1,230
1,822
6
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
147
1
273
1
User I/O (maximum)
PCI
57
–
69
–
104
–
140
–
176
Yes
Yes
202
Yes
Yes
Boundary Scan Test (BST)
–
–
–
–
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
44, 68
44, 68, 84
84
100, 160
100
176
–
84
84
160, 208
–
208, 240
–
100
80
–
–
–
100
80
–
–
–
100, 160, 208
100
176
–
–
176
–
–
208, 256
272
–
–
–
March 2014
i
© 2014 Microsemi Corporation
40MX and 42MX FPGA Families
Ordering Information
_
PQ
G
100
1
A42MX16
ES
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
A = Automotive (–40 to +125°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
BG = Plastic Ball Grid Array
CQ =Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A40MX02 = 3,000 System Gates
A40MX04 = 6,000 System Gates
A42MX09 = 14,000 System Gates
A42MX16 = 24,000 System Gates
A42MX24 = 36,000 System Gates
A42MX36 = 54,000 System Gates
Plastic Device Resources
User I/Os
PQFP
PLCC
PLCC
PLCC
PQFP
PQFP
PQFP
VQFP
VQFP
TQFP
PBGA
Device
44-Pin
68-Pin
84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
34
34
–
57
57
–
–
57
69
83
83
–
–
–
–
–
–
–
57
69
–
–
–
–
–
–
–
69
72
72
72
–
101
125
125
–
–
–
83
83
–
104
140
150
–
–
–
–
140
176
176
–
–
–
–
–
–
–
–
–
–
–
202
–
–
202
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad
Flat Pack, PBGA = Plastic Ball Grid Array
ii
Revision 12
40MX and 42MX FPGA Families
Ceramic Device Resources
User I/Os
Device
CQFP 208-Pin
CQFP 256-Pin
A42MX36
176
202
Note: Package Definitions CQFP = Ceramic Quad Flat Pack
Temperature Grade Offerings
Package
PLCC 44
PLCC 68
PLCC 84
PQFP 100
PQFP 160
PQFP 208
PQFP 240
VQFP 80
VQFP 100
TQFP 176
PBGA 272
CQFP 208
CQFP 256
Note:
A40MX02
C, I, M
A40MX04
C, I, M
A42MX09
A42MX16
A42MX24
A42MX36
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, M, B
C, M, B
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
Speed Grade Offerings
– F
Std
–1
–2
–3
C
I
A
M
B
Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
Revision 12
iii
40MX and 42MX FPGA Families
Table of Contents
40MX and 42MX FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-83
Package Pin Assignments
PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Revision 12
iv
1 – 40MX and 42MX FPGA Families
General Description
Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are single-chip
solutions and provide high performance while shortening the system design and development cycle. MX devices can
integrate and consolidate logic implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-
speed controllers and address decoding, peripheral bus interfaces, DSP, and co-processor functions.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a 0.45µm triple-
metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices provide
performance up to 250 MHz, are live on power-up and have one-fifth the standby power consumption of comparable
FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades.
A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems, enable
programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-power mode. The
devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200 MHz on-chip operation
and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG) Boundary
Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing
fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring
wide datapath manipulation and can perform transformation functions such as those required for telecommunications,
networking, and DSP.
All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest member of the
family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL-STD-883 levels. For
easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pin-compatible.
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are
the building blocks for fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM
modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory.
A42MX24 and A42MX36 also contain wide-decode modules.
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions
with efficient use of interconnect routing resources (Figure 1-1 on page 1-2).
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or
four inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs and OR-
ANDs. No dedicated hard-wired latches or flip-flops are required in the array; latches and flip-flops can be constructed
from logic modules whenever required in the application.
Revision 12
1-1
40MX and 42MX FPGA Families
Figure 1-1 • 42MX C-Module Implementation
The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and
decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module, shown in Figure 1-3,
implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential
element can be configured as either a D-flip-flop or a transparent latch. The S-module register can be bypassed so that
it implements purely combinatorial logic.
A0
B0
S0
D00
D01
Y
D10
D11
S1
A1
B1
Figure 1-2 • 42MX C-Module Implementation
Revision 12
1-2
40MX and 42MX FPGA Families
D00
D01
D00
D01
D
D
Q
OUT
Q
OUT
Y
Y
D10
D10
S0
D11
S1
S0
D11
S1
GATE
CLR
Up to 7-Input Function Plus Latch
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D00
D01
D0
Y
OUT
Q
D10
D
Y
OUT
S0
D11
S1
D1
GATE
CLR
S
Up to 8-Input Function (Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 1-3 • 42MX S-Module Implementation
A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the device. D-
modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD
architectures (Figure 1-4 on page 1-4). The D-module allows A42MX24 and A42MX36 devices to perform wide-
decode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed
back into the array to be incorporated into other logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or asynchronous
applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM
modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the
A42MX36 dual-port SRAM block is shown in Figure 1-5 on page 1-4.
The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM
module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks.
When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write
ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active
HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]),
which are connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO
and LIFO queues. The ACTgen Macro Builder within Microsemi's Designer software provides capability to quickly
design memory functions with the SRAM blocks. Unused SRAM blocks can be used to implement registers for other
user logic within the design.
1-3
Revision 12
40MX and 42MX FPGA Families
7 Inputs
Hard-Wire t o I/O
Program mable
Invert er
Feedback to Array
Figure 1-4 • A42MX24 and A42MX36 D-Module Implementation
Latches
WD[7:0]
[7:0]
[5:0]
RDAD[5:0]
SRAM Module
32 x 8 or 64 x 4 Port
Logic
Latches
Write
Port
Read
Logic
(256 Bit s)
[5:0]
WRAD[5:0]
MODE
BLKEN
WEN
Read
Logic
Lat ches
REN
RD[7:0]
RCLK
Write
Logic
Rout ing Tracks
WCLK
Figure 1-5 • A42MX36 Dual-Port SRAM Block
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment lengths
allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be
joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects
can be accomplished with a maximum of four antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between
the rows of modules. Any segment that spans more than one-third of the row length is considered a long horizontal
segment. A typical channel is shown in Figure 1-6. Within horizontal routing, dedicated routing tracks are used for
global clock networks and for power and ground tie-off tracks. Non-dedicated tracks are used for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output,
and long. Long tracks span the column length of the module, and can be divided into multiple segments. Each
segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated
to the output of a particular module. Long segments are uncommitted and can be assigned during routing.
Each output segment spans four channels (two above and two below), except near the top and bottom of the array,
where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing
tracks and segments is shown in Figure 1-6.
Revision 12
1-4
40MX and 42MX FPGA Families
Antifuse Structures
An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic device results in
highly testable structures as well as efficient programming algorithms. There are no
pre-existing connections; temporary connections can be made using pass transistors. These temporary connections
can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done
before and after programming. For instance, all metal tracks can be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be verified.
Segmented
Horizontal
Routing
Logic
Modules
Antifuses
Vert ical Rout ing Tracks
Figure 1-6 • MX Routing Structure
Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK network by being
routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA and CLKB.
Each network has a clock module (CLKMOD) that can select the source of the clock signal from any of the following
(Figure 1-7 on page 1-6):
•
•
•
•
Externally from the CLKA pad, using CLKBUF buffer
Externally from the CLKB pad, using CLKBUF buffer
Internally from the CLKINTA input, using CLKINT buffer
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are
located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock networks.
The A42MX36 device has four additional register control resources, called quadrant clock networks (Figure 1-8 on
page 1-6). Each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can
be used as a secondary register clock, register clear, or output enable.
1-5
Revision 12
40MX and 42MX FPGA Families
CLKB
CLKA
CLKINB
CLKINA
From
Pads
S0
S1
Internal
Signal
CLKMOD
CLKO(17)
CLKO(16)
CLKO(15)
Clock
Drivers
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 • Clock Networks of 42MX Devices
QCLKA
QCLKC
Quad
Clock
Modul
Quad
Clock
Modul
QCLK1
QCLK3
QCLKD
QCLKB
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Modul
Quad
Clock
Modul
QCLK2
QCLK4
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
Revision 12
1-6
40MX and 42MX FPGA Families
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0V, 3.3V, and mixed 3.3V/5.0V operations.
The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 1-9 is a block
diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be
implemented in the module. (Refer to the Antifuse Macro Library Guide for more information.) All 42MX I/O modules
contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation.
All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable control
(Figure 1-9). The I/O module can be used to latch input or output data, or both, providing fast set-up time. In addition,
the Designer software tools can build a D-type flip-flop using a C-module combined with an I/O module to register input
and output signals. Refer to the Antifuse Macro Library Guide for more details.
A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with version 2.1
of the PCI specification. For low-power systems, all inputs and outputs are turned off to reduce current consumption to
below 500A.
To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide PCI fuse is
programmed via the Device Selection Wizard in the Designer software (Figure 1-10). When the PCI fuse is not
programmed, the output drive is standard.
Designer software development tools provide a design library of I/O macro functions that can implement all I/O
configurations supported by the MX FPGAs.
EN
Q
D
PAD
From Array
To Array
G/CLK*
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)
Figure 1-9 • 42MX I/O Module
STD
Signal
Out put
PCI
Drive
PCI Enable
Fuse
Figure 1-10 • PCI Output Structure of A42MX24 and A42MX36 Devices
1-7
Revision 12
40MX and 42MX FPGA Families
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex logic functions.
MX devices are live on power-up and do not require auxiliary configuration devices and thus are an optimal platform to
integrate the functionality contained in multiple programmable logic devices. In addition, designs that previously would
have required a gate array to meet performance can be integrated into an MX device with improvements in cost and
time-to-market. Using timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device
performance.
User Security
Microsemi FuseLock provides robust security against design theft. Special security fuses are hidden in the fabric of the
device and protect against unauthorized users attempting to access the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses without damaging the device, making Microsemi antifuse FPGAs
protected with the highest level of security available from both invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse. In 42MX devices, there is
the Security Fuse which, when programmed, both disables the probing circuitry and prohibits further programming of
the device.
Programming
Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor II is a compact,
robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II is
designed to allow concurrent programming of multiple units from the same PC.
Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. After being
programmed, each fuse is verified to insure that it has been programmed correctly. Furthermore, at the end of
programming, there are integrity tests that are run to ensure no extra fuses have been programmed. Not only does it
test fuses (both programmed and non-programmed), Silicon Sculptor II also allows self-test to verify its own hardware
extensively.
The procedure for programming an MX device using Silicon Sculptor II is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services either through
distribution partners or via In-House Programming from the factory.
For more details on programming MX devices, please refer to the Programming Antifuse Devices and the Silicon
Sculptor II and Silicon Sculptor 3 user guides.
Revision 12
1-8
40MX and 42MX FPGA Families
Power Supply
MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices can operate in
mixed 5.0 V/3.3 V systems. Table 1-1 describes the voltage support of MX devices.
Table 1-1 • Voltage Support of MX Devices
Device
VCC
5.0 V
3.3 V
–
VCCA
–
VCCI
–
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.5 V
3.6 V
5.5 V
3.6 V
5.5 V
5.0 V
3.3 V
5.0 V
3.3 V
3.3 V
–
–
42MX
5.0 V
3.3 V
5.0 V
5.0 V
3.3 V
3.3 V
–
–
For A42MX24 and A42MX36 devices the VCCA supply has to be monotonic during power up in order for the POR to
issue reset to the JTAG state machine correctly. For more information, refer to MX_PowerUp_AN, (AC291).
Power-Up/Down in Mixed-Voltage Mode
When powering up 42MX in mixed voltage mode (VCCA = 5.0 V and VCCI = 3.3 V), VCCA must be greater than or
equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during
power-up, one of two things will happen:
•
•
The input protection diode on the I/Os will be forward biased
The I/Os will be at logical High
In either case, ICC rises to high levels.
For power-down, any sequence with VCCA and VCCI can be implemented.
Transient Current
Due to the simultaneous random logic switching activity during power-up, a transient current may appear on the core
supply (VCC). Customers must use a regulator for the VCC supply that can source a minimum of 100 mA for transient
current during power-up. Failure to provide enough power can prevent the system from powering up properly and
result in functional failure. However, there are no reliability concerns, since transient current is distributed across the
die instead of confined to a localized spot.
Since the transient current is not due to I/O switching, its value and duration are independent of the VCCI.
Low Power Mode
42MX devices have been designed with a Low Power Mode. This feature, activated with setting the special LP pin to
HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems where battery life is a primary
concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby
current. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated. Since the core
of the device is turned off, the states of the registers are lost. The device must be re-initialized when exiting Low Power
Mode. I/Os can be driven during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid
drawing current. To exit LP mode, the LP pin must be pulled LOW for over 200 µs to allow for charge pumps to power
up, and device initialization will begin.
1-9
Revision 12
40MX and 42MX FPGA Families
Power Dissipation
The general power consumption of MX devices is made up of static and dynamic power and can be expressed with the
following equation.
General Power Equation
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs or outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and
on the system I/O. The power can be divided into two components: static and active.
Static Power Component
The static power due to standby current is typically a small component of the overall power consumption. Standby
power is calculated for commercial, worst-case conditions. The static power dissipation by TTL loads depends on the
number of outputs driving, and on the DC load current. For instance, a 32-bit bus sinking 4mA at 0.33V will generate
42mW with all outputs driving LOW, and 140mW with all outputs driving HIGH. The actual dissipation will average
somewhere in between, as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and
module outputs, plus external capacitances due to PC board traces and load device inputs. An additional component
of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated
with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed by the equation:
Power (µW) = CEQ * VCCA2 * F(1)
where:
CEQ = Equivalent capacitance expressed in picofarads (pF)
VCCA = Power supply in volts (V)
F = Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown below.
Revision 12
1-10
40MX and 42MX FPGA Families
C
Values for Microsemi MX FPGAs
EQ
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic
must be known. The equation below shows a piece-wise linear summation over all components.
Power = VCCA2 * [(m x CEQM * fm)Modules
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs
0.5 * (q1 * CEQCR * fq1 routed_Clk1 + (r1 * fq1 routed_Clk1
0.5 * (q2 * CEQCR * fq2 routed_Clk2 + (r2 * fq2 routed_Clk2
+
+
)
)
)
)
+
(2)
where:
m
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Number of logic modules switching at frequency fm
Number of input buffers switching at frequency fn
Number of output buffers switching at frequency fp
Number of clock loads on the first routed array clock
Number of clock loads on the second routed array clock
Fixed capacitance due to first routed array clock
Fixed capacitance due to second routed array clock
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Equivalent capacitance of routed array clock in pF
Output load capacitance in pF
n
p
q1
q2
r1
r2
CEQM
CEQI
CEQO
CEQCR
CL
fm
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
fn
fp
Average output buffer switching rate in MHz
Average first routed array clock rate in MHz
Average second routed array clock rate in MHz
fq1
fq2
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
r1 routed_Clk1
r2 routed_Clk2
41.4
68.6
118
165
185
220
N/A
N/A
118
165
185
220
1-11
Revision 12
40MX and 42MX FPGA Families
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer
software, allow users to examine any of the internal nets of the device while it is operating in a prototyping or a
production system. The user can probe into an MX device without changing the placement and routing of the design
and without using any additional resources. Silicon Explorer II's noninvasive method does not alter timing or loading
effects, thus shortening the debug cycle and providing a true representation of the device under actual functional
situations.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a
PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at their desks and reduces verification time from several hours
per cycle to a few seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is activated when the MODE pin is held HIGH.
Figure 1-11 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 1-12 on
page 1-12 illustrates the interconnection between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must not be programmed. (Refer to "User Security" section on
page 1-8 for the security fuses of 40MX and 42MX devices). Table 1-2 on page 1-13 summarizes the possible device
configurations for probing.
PRA and PRB pins are dual-purpose pins. When the "Reserve Probe Pin" is checked in the
Designer software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and "Reserve Probe Pin" is checked, the layout tool will override the
option and place user I/Os on PRA and PRB pins.
16 Logic Analyzer Channels
40MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRA
PRB
Figure 1-11 • Silicon Explorer II Setup with 40MX
16 Logic Analyzer Channels
42MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRA
PRB
Figure 1-12 • Silicon Explorer II Setup with 42MX
Revision 12
1-12
40MX and 42MX FPGA Families
Table 1-2 • Device Configuration Options for Probe Capability
Security Fuse(s) Programmed
Mode
LOW
HIGH
–
PRA, PRB1
User I/Os2
SDI, SDO, DCLK1
User I/Os2
No
No
Probe Circuit Outputs
Probe Circuit Secured
Probe Circuit Inputs
Probe Circuit Secured
Yes
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during
probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin Descriptions"
section on page 1-83 for information on unused I/O pins.
Design Consideration
It is recommended to use a series 70 termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA
and PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading
back the checksum.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint Testing Action
Group Standard or JTAG), which defines a set of hardware architecture and mechanisms for cost-effective board-level
testing. The basic MX boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data
registers and instruction register (Figure 1-13 on page 1-14). This circuit supports all mandatory IEEE 1149.1
instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and some optional instructions. Table 1-3 on page 1-14
describes the ports that control JTAG testing, while Table 1-4 on page 1-14 describes the test instructions supported
by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present at TMS at a
rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data
register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of
the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of
the controller from any of the possible states, TMS must remain high for five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test
data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four
fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and
controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary-scan
register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal
core logic tile and the input, output and control ports of an I/O buffer to capture and load data into the register to control
or observe the logic state of each I/O.
1-13
Revision 12
40MX and 42MX FPGA Families
Boundary Scan Register
Output
TDO
MUX
Bypass
Register
Control Logic
JTAG
TMS
TCK
JTAG
TDI
Instruction
Decode
TAP Controller
Instruction
Register
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 1-3 • Test Access Port Descriptions
Port
Description
TMS
(Test Mode Select)
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic
clock (TCK).
TCK
(Test Clock Input)
Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on
the rising edge of the clock, and serially to shift the output data on the falling edge of the clock.
The maximum clock frequency for TCK is 20 MHz.
TDI
Serial input for instruction and test data. Data is captured on the rising edge of the test logic
clock.
(Test Data Input)
TDO
(Test Data Output)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive
state (high impedance) when data scanning is not in progress.
Table 1-4 • Supported BST Public Instructions
IR Code Instruction
Instruction
(IR2.IR0)
Type
Description
EXTEST
000
Mandatory Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
SAMPLE/PRELOAD
HIGH Z
001
101
110
Mandatory Allows a snapshot of the signals at the device pins to be captured
and examined during operation
Optional
Tristates all I/Os to allow external signals to drive pins. Please refer to
the IEEE Standard 1149.1 specification.
CLAMP
Optional
Allows state of signals driven from component pins to be determined
from the Boundary-Scan Register. Please refer to the IEEE Standard
1149.1 specification for details.
BYPASS
111
Mandatory Enables the bypass register between the TDI and TDO pins. The test
data passes through the selected device to adjacent devices in the
test chain.
Revision 12
1-14
40MX and 42MX FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools > Device Selection. This brings up
the Device Selection dialog box as shown in Figure 1-14. The JTAG test logic circuit can be enabled by clicking the
"Reserve JTAG Pins" check box. Table 1-5 explains the pins' behavior in either mode.
Figure 1-14 • Device Selection Wizard
Table 1-5 • Boundary Scan Pin Configuration and Functionality
Reserve JTAG
TCK
Checked
Unchecked
User I/O
BST input; must be terminated to logical HIGH or LOW to avoid floating
BST input; may float or be tied to HIGH
TDI, TMS
TDO
User I/O
BST output; may float or be connected to TDI of another device
User I/O
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets the boundary
scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up resistor. This allows the TAP
controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS
pin. To reset the controller, TMS must be HIGH for at least five TCK cycles.
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be documented.
The BSDL file provides the standard format to describe the JTAG components that can be used by automatic test
equipment software. The file includes the instructions that are supported, instruction bit pattern, and the boundary-
scan chain order. For an in-depth discussion on BSDL files, please refer tothe BSDL Files Format Description
application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user I/Os as
inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website:
http://www.microsemi.com/soc/techdocs/models/bsdl.html.
1-15
Revision 12
40MX and 42MX FPGA Families
Development Tool Support
The MX family of FPGAs is fully supported by Libero® Integrated Design Environment (IDE). Libero IDE is a design
management environment, seamlessly integrating design tools while guiding the user through the design flow,
managing all design and log files, and passing necessary design data among tools. Libero IDE allows users to
integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment.
Libero IDE includes SynplifyPro from Synopsys, ModelSim® HDL Simulator from Mentor Graphics,® and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for FPGA
development, including timing-driven place-and-route, and a world-class integrated static timing analyzer and
constraints editor.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be
cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis tool. Another tool included
in the Libero software is the SmartGen macro builder, which easily creates popular and commonly used logic functions
for implementation into your schematic or HDL design.
Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synopsys, and Cadence Design Systems.
Refer to the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for further
information on licensing and current operating system support.
Related Documents
Application Notes
BSDL Files Format Description
www.microsemi.com/soc/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.microsemi.com/soc/documents/AntifuseProgram_AN.pdf
Implementation of Security in Microsemi Antifuse FPGAs
www.microsemi.com/documents/Antifuse_Security_AN.pdf
User Guides and Manuals
Antifuse Macro Library Guide
www.microsemicom/soc/documents/libguide_UG.pdf
Silicon Sculptor II and Silicon Sculptor 3 User Guide
www.microsemi.com/soc/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram
www.microsemi.com/soc/products/tools/libero/flow.html
Revision 12
1-16
40MX and 42MX FPGA Families
5.0 V Operating Conditions
Table 1-6 • Absolute Maximum Ratings for 40MX Devices*
Symbol
VCC
VI
Parameter
DC Supply Voltage
Limits
Units
V
–0.5 to +7.0
Input Voltage
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–65 to +150
V
VO
Output Voltage
Storage Temperature
V
tSTG
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-7 • Absolute Maximum Ratings for 42MX Devices*
Symbol
VCCI
VCCA
VI
Parameter
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
Limits
Units
V
–0.5 to +7.0
–0.5 to +7.0
V
–0.5 to VCCI+0.5
–0.5 to VCCI+0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-8 • Recommended Operating Conditions
Parameter
Commercial
0 to +70
Industrial
–40 to +85
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Military
–55 to +125
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Units
°C
V
Temperature Range*
VCC (40MX)
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
VCCA (42MX)
VCCI (42MX)
V
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
1-17
Revision 12
40MX and 42MX FPGA Families
5 V TTL Electrical Specifications
Table 1-9 • 5V TTL Electrical Specifications
Commercial
Commercial -F
Industrial
Military
Max.
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
VOH1
IOH = –10 mA 2.4
IOH = –4 mA
IOL = 10 mA
IOL = 6 mA
–0.3
2.4
V
V
3.7
3.7
VOL1
0.5
0.8
0.5
0.8
V
0.4
0.8
0.4
0.8
V
VIL
–0.3
–0.3
–0.3
V
VIH (40MX)
VIH (42MX)
IIL
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3
V
V
VIN = 0.5 V
VIN = 2.7 V
–10
–10
500
–10
–10
500
–10
–10
500
–10
–10
500
µA
µA
ns
IIH
Input Transition
Time, TR and TF
C
IO I/O
10
3
10
25
10
10
10
25
pF
Capacitance
Standby Current, A40MX02,
mA
ICC2
A40MX04
A42MX09
A42MX16
5
6
25
25
25
25
25
25
25
25
25
mA
mA
mA
A42MX24,
A42MX36
20
Low power mode 42MX devices
Standby Current only
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
IIO, I/O source
sink current
Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
Revision 12
1-18
40MX and 42MX FPGA Families
3.3 V Operating Conditions
Table 1-10 • Absolute Maximum Ratings for 40MX Devices*
Symbol
VCC
VI
Parameter
DC Supply Voltage
Limits
Units
V
–0.5 to +7.0
Input Voltage
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
–65 to + 150
V
VO
Output Voltage
Storage Temperature
V
tSTG
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-11 • Absolute Maximum Ratings for 42MX Devices*
Symbol
VCCI
VCCA
VI
Parameter
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
Limits
Units
V
–0.5 to +7.0
–0.5 to +7.0
V
–0.5 to VCCI+0.5
–0.5 to VCCI+0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-12 • Recommended Operating Conditions
Parameter
Commercial
0 to +70
Industrial
–40 to +85
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Military
–55 to +125
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Units
°C
V
Temperature Range*
VCC (40MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
VCCA (42MX)
VCCI (42MX)
V
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
1-19
Revision 12
40MX and 42MX FPGA Families
3.3 V LVTTL Electrical Specifications
Table 1-13 • 3.3V LVTTL Electrical Specifications
Commercial
Commercial -F
Industrial
Military
Max.
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
VOH1
VOL1
IOH = –4 mA 2.15
IOL = 6 mA
–0.3
2.15
2.4
2.4
V
V
0.4
0.8
0.4
0.8
0.48
0.8
0.48
0.8
VIL
–0.3
–0.3
–0.3
V
VIH (40MX)
VIH (42MX)
IIL
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3
V
V
–10
–10
500
–10
–10
500
–10
–10
500
–10
–10
500
µA
µA
ns
IIH
Input Transition
Time, TR and TF
CIO I/O
Capacitance
10
3
10
25
10
10
10
25
pF
A40MX02,
A40MX04
mA
A42MX09
A42MX16
5
6
25
25
25
25
25
25
25
25
25
mA
mA
mA
Standby
Current, ICC2
A42MX24,
A42MX36
15
Low-Power
42MX
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Mode Standby devices only
Current
IIO, I/O source Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
sink current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
Revision 12
1-20
40MX and 42MX FPGA Families
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices
Only)
Table 1-14 • Absolute Maximum Ratings*
Symbol
VCCI
VCCA
VI
Parameter
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
Limits
Units
V
–0.5 to +7.0
–0.5 to +7.0
V
–0.5 to VCCA +0.5
–0.5 to VCCI + 0.5
–65 to +150
V
VO
Output Voltage
V
tSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-15 • Recommended Operating Conditions
Parameter
Temperature Range*
VCCA
Commercial
0 to +70
Industrial
–40 to +85
4.5 to 5.5
3.0 to 3.6
Military
–55 to +125
4.5 to 5.5
3.0 to 3.6
Units
°C
V
4.75 to 5.25
3.14 to 3.47
VCCI
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
1-21
Revision 12
40MX and 42MX FPGA Families
Mixed 5.0V/3.3V Electrical Specifications
Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications
Commercial
Commercial –F
Industrial
Military
Max.
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
VOH1
IOH = –10 mA 2.4
IOH = –4 mA
IOL = 10 mA
IOL = 6 mA
–0.3
2.4
V
V
2.4
2.4
VOL1
0.5
0.8
0.5
0.8
V
0.4
0.8
0.4
0.8
V
VIL
VIH
IL
–0.3
–0.3
–0.3
V
2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3
V
VIN = 0.5 V
VIN = 2.7 V
–10
–10
500
–10
–10
500
–10
–10
500
–10
–10
500
µA
µA
ns
IH
Input Transition
Time, TR and TF
C
IO I/O Capacitance
10
5
10
25
25
25
10
25
25
25
10
25
25
25
pF
mA
mA
mA
Standby Current,
ICC2
A42MX09
A42MX16
6
A42MX24,
A42MX36
20
Low Power Mode
Standby Current
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
IIO I/O source sink Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
current
Notes:
1. Only one output tested at a time. VCCI = min.
2. All outputs unloaded. All inputs = VCCI or GND.
Revision 12
1-22
40MX and 42MX FPGA Families
Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-15 on page 1-25
shows the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local
Bus Specification.
Table 1-17 • DC Specification (5.0 V PCI Signaling)1
PCI
MX
Max.
Symbol Parameter
Units
Condition
Min.
4.75
2.0
Max.
Min.
4.75
2.0
VCCI
VIH
VIL
Supply Voltage for I/Os
5.25
5.252
VCCI + 0.3
0.8
V
V
Input High Voltage
VCC + 0.5
0.8
Input Low Voltage
–0.5
–0.3
—
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
VIN = 2.7 V
VIN=0.5 V
70
10
µA
µA
V
IIL
–70
—
–10
VOH
IOUT = –2 mA
IOUT = –6 mA
2.4
3.84
—
VOL
CIN
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
Pin Inductance
IOUT = 3 mA, 6 mA
0.55
10
0.33
10
V
—
pF
pF
nH
CCLK
LPIN
5
12
—
10
20
—
< 8 nH3
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5 V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-18 • AC Specifications (5.0V PCI Signaling)*
PCI
MX
Symbol Parameter
Condition
Units
Min.
Max.
Min.
–60
1.8
Max.
–10
2.8
ICL Low Clamp Current
–5 < VIN –1
–25 + (VIN +1) /0.015
mA
V/ns
V/ns
Slew (r) Output Rise Slew Rate 0.4 V to 2.4 V load
Slew (f) Output Fall Slew Rate 2.4 V to 0.4 V load
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
1
1
5
5
2.8
4.3
1-23
Revision 12
40MX and 42MX FPGA Families
Output Drive Characteristics for 3.3 V PCI Signaling
Table 1-19 • DC Specification (3.3 V PCI Signaling)1
PCI
MX
Symbol Parameter
Condition
Units
Min.
3.0
Max.
3.6
Min.
3.0
Max.
3.6
VCCI
VIH
Supply Voltage for I/Os
V
V
Input High Voltage
0.5
VCC + 0.5
0.8
0.5
VCCI + 0.3
0.8
VIL
Input Low Voltage
–0.5
–0.3
V
IIH
Input High Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
Pin Inductance
VIN = 2.7V
70
10
µA
µA
V
IIL
–70
–10
VOH
VOL
CIN
IOUT = –2 mA
0.9
5
3.3
IOUT = 3 mA, 6 mA
0.1
10
12
20
0.1 VCCI
10
V
pF
pF
nH
CCLK
LPIN
Notes:
10
< 8 nH3
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-20 • AC Specifications for (3.3 V PCI Signaling)*
PCI
Min.
MX
Symbol Parameter
Condition
Units
Max.
Min.
–60
1.8
Max.
–10
2.8
ICL
Low Clamp Current
–5 < VIN –1
0.2 V to 0.6 V load
0.6 V to 0.2 V load
–25 + (VIN +1) /0.015
mA
V/ns
V/ns
Slew (r) Output Rise Slew Rate
Slew (f) Output Fall Slew Rate
1
1
4
4
2.8
4.0
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
Revision 12
1-24
40MX and 42MX FPGA Families
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
PCI IOL Maximum
MX PCI IOL
PCI IOL Minimum
0
1
2
3
4
5
6
–0.05
–0.10
–0.15
–0.20
PCI IOH Maximum
MX PCI IOH
PCI IOH Minimum
Voltage Out (V)
Figure 1-15 • Typical Output Drive Characteristics (Based Upon Measured Data)
Junction Temperature (T )
J
The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature.
This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the
ambient temperature. EQ , shown below, can be used to calculate junction temperature.
Junction Temperature = T + Ta (1)
EQ 1
Where:
Ta = Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient
T = ja * P (2)
P = Power
ja = Junction to ambient of package. ja numbers are located in Table 1-21 on page 1-26.
1-25
Revision 12
40MX and 42MX FPGA Families
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The
thermal characteristics for ja are shown with two different air flow rates.
The maximum junction temperature is 150C.
Maximum power dissipation for commercial- and industrial-grade devices is a function of ja.
A sample calculation of the absolute maximum power dissipation allowed for a TQ176 package at commercial
temperature and still air is given in EQ 2.
Max. junction temp. (C) – Max. ambient temp. (C) 150C – 70C
------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------
= 2.86 W
Maximum Power Allowed =
=
ja(C/W)
28C/W
EQ 2
The maximum power dissipation for military-grade devices is a function of jc. A sample calculation of the absolute
maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is given in EQ 3.
Max. junction temp. (C) – Max. ambient temp. (C) 150C – 125C
------------------------------------------------------------------------------------------------------------------------------------------ ----------------------------------------
= 3.97 W
Maximum Power Allowed =
=
jc(C/W)
6.3C/W
EQ 3
Table 1-21 • Package Thermal Characteristics
ja
Plastic Packages
Pin Count
jc
Units
1.0 m/s
2.5 m/s
Still Air
27.8
26.2
26.1
25.6
20.0
25.0
22.5
24.7
38.2
35.3
18.3
200 ft/min.
500 ft/min.
Plastic Quad Flat Pack
100
160
208
240
44
12.0
10.0
8.0
23.4
22.8
22.5
22.3
24.5
21.0
18.9
19.9
31.9
29.4
14.9
21.2
21.1
20.8
20.8
22.0
19.4
17.6
18.0
29.4
27.1
13.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Plastic Quad Flat Pack
Plastic Quad Flat Pack
Plastic Quad Flat Pack
8.5
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
Thin Plastic Quad Flat Pack
Very Thin Plastic Quad Flat Pack
Very Thin Plastic Quad Flat Pack
Plastic Ball Grid Array
16.0
13.0
12.0
11.0
12.0
10.0
3.0
68
84
176
80
100
272
Ceramic Packages
Ceramic Quad Flat Pack
Ceramic Quad Flat Pack
208
256
2.0
2.0
22.0
20.0
19.8
16.5
18.0
15.0
°C/W
°C/W
Revision 12
1-26
40MX and 42MX FPGA Families
Timing Models
Predicted
Routing
Delays
Input Delay
I/O Module
Internal Delays
Output Delay
I/O Module
tINYL = 0.62 ns
tIRD2 = 2.59 ns
Logic Module
tPD = 1.24 ns
tDLH = 3.32 ns
ENHZ = 7.92 ns
t
t
RD1 = 1.28 ns
RD2 = 1.80 ns
tIRD1 = 2.09 ns
tIRD4 = 3.64 ns
t
tRD4 = 2.33 ns
RD8 = 4.93 ns
tCO = 1.24 ns
t
IRD8 = 5.73 ns
t
Array
Clock
tCKH = 4.55 ns
FO = 128
FMAX = 180 MHz
Note: Values are shown for 40MX –3 speed devices at 5.0 V worst-case commercial conditions.
Figure 1-16 • 40MX Timing Model*
Input Delays
I/O Module
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
t
IRD1 = 2.0 ns1
tINYL = 0.8 ns
Combinatorial
Logic Module
tDLH = 2.5 ns
t
t
RD1 = 0.7 ns
RD2 = 1.9 ns
D
Q
tPD=1.2 ns
tRD4 = 1.4 ns
tRD8 = 2.3 ns
I/O Module
G
tDLH = 2.5 ns
Sequential
t NH = 0.0 ns
I
Logic Module
tINSU = 0.3 ns
tINGL = 1.3 ns
D
Q
D
G
Q
Comb.
Logic
Include
tRD1 = 0.70 ns
t
ENHZ = 4.9 ns
tOUTH = 0.00 ns
tOUTSU = 0.3 ns
tGLH = 2.6 ns
t
t
t
SUD = 0.3 ns
HD = 0.00 ns
CO = 1.3 ns
Array
Clocks
FO = 32
t
CKH = 2.70 ns
F
MAX = 296 MHz
tLCO = 5.2 ns (light loads, pad-to-pad)
Notes:
1. Input module predicted routing delay
2. Values are shown for A42MX09 –3 at 5.0 V worst-case commercial conditions.
Figure 1-17 • 42MX Timing Model
1-27
Revision 12
40MX and 42MX FPGA Families
Predicted
Routing
Delays
Internal Delays
Input Delays
Output Delays
I/O Module
I/O Module
tINPY = 1.0 ns
tIRD1= 2.0 ns
Combinatorial
Module
tDLH = 2.6 ns
t
RD1 = 0.9 ns
Q
D
G
tPD=1.3 ns
tRD2 = 1.3 ns
RD4 = 2.0 ns
t
Decode
Module
t
INH = 0.0 ns
tINSU = 0.5 ns
tINGO = 1.4 ns
tRDD = 0.3 ns
t
PDD = 1.6 ns
I/O Module
t
DLH = 2.6 ns
Sequential
Logic Module
tRD1 = 0.9 ns
D
G
Q
D
Q
Comb.
Logic
Include
tENHZ = 5.3 ns
tLH = 0.00 ns
tCO = 1.3 ns
tLSU = 0.5 ns
tGHL = 2.9 ns
tSUD = 3.0 ns
tHD = 0.0 ns
Quadrant
Clocks
t
CKH=3.03 ns1
F
MAX
=180 MHz
Notes:
1. Load-dependent
2. Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions.
Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Revision 12
1-28
40MX and 42MX FPGA Families
Input Delays
I/O Module
tINPY = 1 .0 ns
tIRD1 = 2.0 ns
D
G
Q
Predicted
Routing
Delays
I/O Module
tDLH = 2.6 ns
t
t
INSU = 0.5 ns
INH = 0.0 ns
tINGO = 1.4 ns
RD [7:0]
RDAD [5:0]
REN
WD [7:0]
t
RD1 = 0.9 ns
WRAD [5:0]
BLKEN
D
G
Q
WEN
WCLK
RCLK
tADSU = 1.6 ns
tADH = 0.0 ns
WENSU = 2.7 ns
tBENS = 2.8 ns
t
ADSU = 1.6 ns
tADH = 0.0 ns
RENSU = 0.6 ns
tRCO = 3.4 ns
tGHL = 2.9 ns
LSU = 0.5 ns
tLH = 0.0 ns
Array
Clocks
t
t
t
FMAX = 167 MHz
Note: Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions.
Figure 1-19 • 42MX Timing Model (SRAM Functions)
1-29
Revision 12
40MX and 42MX FPGA Families
Parameter Measurement
E
D
To AC test loads (shown below)
PAD
TRIBUFF
In
E
E
50% 50%
50% 50%
VCCI
50%
VOH
1.5 V
50%
VOH
1.5 V
1.5 V
1.5 V
PAD
VOL
PAD
GND
PAD
90%
10%
VOL
tDLH
tDHL
tENZL
tENLZ
tENHZ
tENZH
Figure 1-20 • Output Buffer Delays
Load 1
Load 2
(Used to measure rising/falling edges)
(Used to measure propagation delay)
VCCI
GND
To the output under test
R to VCCI for tPLZ / tPZL
R to GND for tPHZ / tPZH
R =1 k
35 pF
To the output under test
35 pF
Figure 1-21 • AC Test Loads
Y
PA D
INBUF
3 V
1.5 V 1.5 V
VCCI
PAD
0 V
50%
Y
GND
50%
tINYH
tINYL
Figure 1-22 • Input Buffer Delays
Revision 12
1-30
40MX and 42MX FPGA Families
S
A
B
Y
S, A or B
Y
50% 50%
50%
50%
t
PLH
PHL
t
Y
50%
50%
t
PHL
PLH
Figure 1-23 • Module Delays
Sequential Module Timing Characteristics
D
E
CLK
Y
PRE
CLR
(Positive Edge-Triggered)
tHD
D*
tSUD
tA
tWCLKA
G, CLK
tSUENA
tWCLK1
tHENA
tCO
E
Q
tRS
PRE, CLR
tWASYN
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-24 • Flip-Flops and Latches
1-31
Revision 12
40MX and 42MX FPGA Families
Sequential Timing Characteristics
PA D
DATA
IBDL
G
CLK PA D
DATA
G
tINH
INSU
tINSU
tHEXT
CLK
tSU EXT
Figure 1-25 • Input Buffer Latches
D
G
PAD
OBDLHS
D
G
t
OUTSU
t
OUTH
Figure 1-26 • Output Buffer Latches
Revision 12
1-32
40MX and 42MX FPGA Families
Decode Module Timing
A
B
C
D
E
F
Y
H
G
A–G, H
Y
50%
tPHL
tPLH
Figure 1-27 • Decode Module Timing
SRAM Timing Characteristics
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
LEW
RAM Array
32x8 or 64x4
(256 Bits)
REN
WCLK
RCLK
WD [7:0]
RD [7:0]
Figure 1-28 • SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
tRCKHL
tRCKHL
WCLK
tADH
tADSU
WD[7:0]
WRAD[5:0]
Valid
tWENSU
tWENH
WEN
tBENSU
Valid
tBENH
BLKEN
Note: Identical timing for falling edge clock.
Figure 1-29 • 42MX SRAM Write Operation
1-33
Revision 12
40MX and 42MX FPGA Families
tCKHL
tRCKHL
RCLK
REN
tRENSU
tRENH
tADSU
Valid
tADH
RDAD[5:0]
tRCO
tDOH
Old Data
New Data
RD[7:0]
Note: Identical timing for falling edge clock.
Figure 1-30 • 42MX SRAM Synchronous Read Operation
tRDADV
RDAD[5:0]
RD[7:0]
ADDR1
ADDR2
tRPD
tDOH
Data 1
Data 2
Figure 1-31 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WEN
tWENSU
tWENH
WD[7:0]
WRAD[5:0]
BLKEN
Valid
tADH
tADSU
WCLK
tRPD
tDOH
Old Data
New Data
RD[7:0]
Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
Revision 12
1-34
40MX and 42MX FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing
tracks, the number of interconnect elements, or the number of inputs increases.
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks.
The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the
interconnect elements and by decreasing the number of interconnect elements per path.
Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricated in 0.45 µm
lithography, offer nominal levels of 100 resistance and 7.0 fF capacitance per antifuse.
MX fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The
proprietary architecture limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects
using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer characteristics are common to all MX devices. Internal routing delays
are device-dependent; actual delays are not determined until after place-and-route of the user's design is complete.
Delay values may then be determined by using the Designer software utility or by performing simulation with post-
layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property
assignment in Microsemi's Designer software prior to placement and routing. Up to 6% of the nets in a design may be
designated as critical.
Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and
resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a
fully utilized device require long tracks. Long tracks add approximately a 3 ns to a 6 ns delay, which is represented
statistically in higher fanout (FO=8) routing delays in the data sheet specifications section, shown in Table 1-28 on
page 1-40.
Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature,
voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating
temperature and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum
operating temperature and worst-case processing.
1-35
Revision 12
40MX and 42MX FPGA Families
Temperature and Voltage Derating Factors
Table 1-22 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 5.0 V)
Temperature
42MX
Voltage
–55°C
0.93
0.88
0.85
0.84
0.83
–40°C
0.95
0.90
0.87
0.86
0.85
0°C
1.05
1.00
0.96
0.95
0.94
25°C
1.09
1.03
1.00
0.97
0.96
70°C
1.25
1.18
1.15
1.12
1.10
85°C
1.29
1.22
1.18
1.14
1.13
125°C
1.41
1.34
1.29
1.28
1.26
4.50
4.75
5.00
5.25
5.50
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
4.75
5.00
Voltage
5.25
5.50
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-33 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0 V)
Table 1-23 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 5.0 V)
Temperature
40MX Voltage
–55°C
0.89
0.84
0.82
0.80
0.79
–40°C
0.93
0.88
0.85
0.82
0.82
0°C
1.02
0.97
0.94
0.91
0.90
25°C
1.09
1.03
1.00
0.97
0.96
70°C
1.25
1.18
1.15
1.12
1.10
85°C
1.31
1.24
1.20
1.16
1.15
125°C
4.50
4.75
5.00
5.25
5.50
1.45
1.37
1.33
1.29
1.28
Revision 12
1-36
40MX and 42MX FPGA Families
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
0.60
4.50
4.75
5.00
5.25
5.50
Voltage
(V)
Note: This derating factor applies to all routing and propagation delays
Figure 1-34 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0 V)
Table 1-24 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 3.3 V)
Temperature
42MX Voltage
–55°C
–40°C
0°C
1.10
0.96
0.92
25°C
1.15
1.00
0.96
70°C
85°C
1.36
1.18
1.13
125°C
3.00
3.30
3.60
0.97
1.00
1.32
1.15
1.10
1.45
1.26
1.21
0.84
0.87
0.81
0.84
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
55°C
40°C
0°C
25°C
70°C
85°C
125°C
3.00
3.30
3.60
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-35 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3 V)
1-37
Revision 12
40MX and 42MX FPGA Families
Table 1-25 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 3.3 V)
Temperature
40MX Voltage
–55°C
1.08
–40°C
1.12
0°C
1.21
0.96
0.92
25°C
1.26
1.00
0.96
70°C
1.50
1.19
1.14
85°C
1.64
1.30
1.25
125°C
2.00
3.00
3.30
3.60
0.86
0.89
1.59
0.83
0.85
1.53
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
55˚C
40˚C
0˚C
25˚C
70˚C
85˚C
125˚C
3.00
3.30
Voltage (V)
3.60
Note: This derating factor applies to all routing and propagation delays.
Figure 1-36 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3 V)
Revision 12
1-38
40MX and 42MX FPGA Families
PCI System Timing Specification
Table 1-26 and Table 1-27 list the critical PCI timing parameters and the corresponding timing parameters for the MX
PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Microsemi sales representative for more details.
Table 1-26 • Clock Specification for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Units
Min.
30
Max.
Min.
Max.
Min.
Max.
tCYC
tHIGH
tLOW
CLK Cycle Time
CLK High Time
CLK Low Time
–
–
–
4.0
1.9
1.9
–
–
–
4.0
1.9
1.9
–
–
–
ns
ns
ns
11
11
Table 1-27 • Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Units
Min.
Max. Min. Max. Min. Max.
tVAL
CLK to Signal Valid—Bused Signals
2
11
12
–
2.0
2.0
2.0
–
9.0
9.0
4.0
8.31
–
2.0
2.0
2.0
–
9.0
9.0
4.0
8.31
–
ns
ns
ns
ns
ns
ns
ns
tVAL(PTP) CLK to Signal Valid—Point-to-Point
2 2
tON
Float to Active
Active to Float
2
tOFF
tSU
tSU(PTP)
tH
–
28
–
Input Set-Up Time to CLK—Bused Signals
Input Set-Up Time to CLK—Point-to-Point
Input Hold to CLK
7
10, 122
0
1.5
1.5
0
1.5
1.5
0
–
–
–
–
–
–
Notes:
1.
T
is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
OFF
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed
signals. GNT# has a setup of 10; REW# has a setup of 12.
1-39
Revision 12
40MX and 42MX FPGA Families
Timing Characteristics
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.2
2.7
1.2
1.2
1.2
1.4
3.1
1.4
1.4
1.4
1.6
3.5
1.6
1.6
1.6
1.9
4.1
1.9
1.9
1.9
2.7
5.7
2.7
2.7
2.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.3
1.8
2.3
2.9
4.9
1.5
2.1
2.7
3.3
5.7
1.7
2.4
3.0
3.7
6.5
2.0
2.8
3.6
4.4
7.6
2.8
3.9
ns
ns
ns
ns
ns
5.0
6.1
10.6
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
3.1
0.0
3.1
3.5
0.0
3.5
4.0
0.0
4.0
4.7
0.0
4.7
6.6
0.0
6.6
ns
ns
ns
3
tHD
Flip-Flop (Latch)
Data Input Hold
tSUENA Flip-Flop (Latch)
Enable Set-Up
tHENA
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width
Flip-Flop (Latch) Enable Hold 0.0
0.0
3.8
0.0
4.3
0.0
5.0
0.0
7.0
ns
ns
3.3
3.3
4.8
3.8
5.6
4.3
6.3
5.0
7.5
7.0
ns
tA
Flip-Flop Clock Input Period
10.4
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
181
168
154
134
80 MHz
Input Module Propagation Delays
tINYH
tINYL
Pad-to-Y HIGH
Pad-to-Y LOW
0.7
0.6
0.8
0.7
0.9
0.8
1.1
1.0
1.5
1.3
ns
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
Revision 12
1-40
40MX and 42MX FPGA Families
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.1
2.6
3.1
3.6
5.7
2.4
3.0
3.6
4.2
6.6
2.2
3.4
4.1
4.8
7.5
3.2
4.0
4.8
5.6
8.8
4.5
5.6
ns
ns
ns
ns
ns
6.7
7.8
12.4
Global Clock Network
tCKH
tCKL
tPWH
tPWL
Input Low to HIGH FO = 16
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
ns
ns
ns
ns
ns
FO = 128
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
Minimum Pulse
Width HIGH
FO = 16
FO = 128 2.4
2.2
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
Minimum Pulse
Width LOW
FO = 16 2.2
FO = 128 2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
tCKSW Maximum Skew
FO = 16
FO = 128
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
tP
Minimum Period
FO = 16
4.7
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
FO = 128 4.8
fMAX
Notes:
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83 MHz
80
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
1-41
Revision 12
40MX and 42MX FPGA Families
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
3.3
4.0
3.8
4.6
4.3
5.2
5.1
6.1
7.2
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
8.6
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.7
4.3
4.9
5.8
8.0
4.7
5.4
6.1
7.2
10.1
17.1
12.6
7.9
9.1
10.4
7.7
12.2
9.0
5.9
6.8
0.02
0.03
0.02
0.03
0.03
0.03
0.03
0.04
0.04 ns/pF
0.06 ns/pF
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
3.9
3.4
4.5
3.9
5.1
4.4
6.05
5.2
8.5
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
7.3
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.4
3.9
4.4
5.2
7.3
4.9
5.6
6.4
7.5
10.5
17.0
12.6
7.9
9.1
10.4
7.7
12.2
9.0
5.9
6.8
0.03
0.02
0.04
0.02
0.04
0.03
0.05
0.03
0.07 ns/pF
0.04 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
Revision 12
1-42
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.7
3.7
1.7
1.7
1.7
2.0
4.3
2.0
2.0
2.0
2.3
4.9
2.3
2.3
2.3
2.7
5.7
2.7
2.7
2.7
3.7
8.0
3.7
3.7
3.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.0
2.7
3.4
4.2
7.1
2.2
3.1
3.9
4.8
8.2
2.5
3.5
4.4
5.4
9.2
3.0
4.1
4.2
5.7
7.3
8.9
ns
ns
ns
ns
5.2
6.3
10.9
15.2 ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
4.3
0.0
4.9
0.0
5.6
0.0
6.6
0.0
9.2
0.0
ns
ns
3
tHD
Flip-Flop (Latch)
Data Input Hold
tSUENA
tHENA
Flip-Flop (Latch) Enable Set-Up 4.3
4.9
0.0
5.3
5.6
0.0
6.0
6.6
0.0
7.0
9.2
0.0
9.8
ns
ns
ns
Flip-Flop (Latch) Enable Hold
0.0
4.6
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
6.8
5.3
7.8
6.0
8.9
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
109
101
92
80
48 MHz
Input Module Propagation Delays
tINYH
tINYL
Pad-to-Y HIGH
Pad-to-Y LOW
1.0
0.9
1.1
1.0
1.3
1.1
1.5
1.3
2.1
1.9
ns
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1-43
Revision 12
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.9
3.6
4.4
5.1
8.0
3.4
4.2
3.8
4.8
4.5
5.6
6.3
7.8
9.4
ns
ns
ns
5.0
5.7
6.7
5.9
6.7
7.8
11.0 ns
17.3 ns
9.26
10.5
12.6
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input LOW to HIGH FO = 16
6.4
6.4
7.4
7.4
8.3
8.3
9.8
9.8
13.7 ns
13.7
FO = 128
Input HIGH to LOW FO = 16
FO = 128
6.7
6.7
7.8
7.8
8.8
8.8
10.4
10.4
14.5 ns
14.5
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
Maximum Skew
FO = 16
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.2
1.6
ns
ns
FO = 128
Minimum Period
FO = 16
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
113
109
105
101
96
92
83
80
50 MHz
48
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
4.7
5.6
5.4
6.4
6.1
7.3
7.2
8.6
10.0
ns
ns
ns
ns
ns
ns
tDHL
12.0
11.3
14.1
23.9
17.7
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
5.2
6.0
6.8
8.1
6.6
7.6
8.6
10.1
17.1
12.6
0.04
0.06
11.1
8.2
12.8
9.5
14.5
10.7
0.04
0.05
0.03
0.04
0.03
0.04
0.06 ns/pF
0.08 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
Revision 12
1-44
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
5.5
4.8
6.4
5.5
7.2
6.2
8.5
7.3
11.9
10.2
10.2
14.7
23.9
17.7
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4.7
5.5
6.2
7.3
6.8
7.9
8.9
10.5
17.1
12.6
0.07
0.04
11.1
8.2
12.8
9.5
14.5
10.7
0.06
0.04
0.05
0.03
0.05
0.03
0.10 ns/pF
0.06 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1-45
Revision 12
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.2
2.3
1.2
1.2
1.2
1.4
3.1
1.4
1.4
1.4
1.6
3.5
1.6
1.6
1.6
1.9
4.1
1.9
1.9
1.9
2.7
5.7
2.7
2.7
2.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.2
1.9
2.4
2.9
5.0
1.6
2.2
2.8
3.4
5.8
1.8
2.5
3.2
3.9
6.6
2.1
2.9
3.7
4.5
7.8
3.0
4.1
ns
ns
ns
ns
ns
5.2
6.3
10.9
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
3.1
0.0
3.1
0.0
3.3
3.3
4.8
3.5
0.0
3.5
0.0
3.8
3.8
5.6
4.0
0.0
4.0
0.0
4.3
4.3
6.3
4.7
0.0
4.7
0.0
5.0
5.0
7.5
6.6
0.0
6.6
0.0
7.0
7.0
10.4
ns
ns
ns
ns
ns
ns
ns
3
tHD
Flip-Flop (Latch)
Data Input Hold
tSUENA Flip-Flop (Latch)
Enable Set-Up
tHENA
Flip-Flop (Latch)
Enable Hold
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width
tA
Flip-Flop Clock Input Period
fMAX
Flip-Flop (Latch)
Clock Frequency
(FO = 128)
181
167
154
134
80 MHz
Input Module Propagation Delays
tINYH
tINYL
Pad-to-Y HIGH
Pad-to-Y LOW
0.7
0.6
0.8
0.7
0.9
0.8
1.1
1.0
1.5
1.3
ns
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
Revision 12
1-46
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.1
2.6
3.1
3.6
5.7
2.4
3.0
3.6
4.2
6.6
2.2
3.4
4.1
4.8
7.5
3.2
4.0
4.8
5.6
8.8
4.5
5.6
ns
ns
ns
ns
ns
6.7
7.8
12.4
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input Low to HIGH FO = 16
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
ns
ns
ns
ns
ns
FO = 128
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
Minimum Pulse
Width HIGH
FO = 16
FO = 128 2.4
2.2
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
Minimum Pulse
Width LOW
FO = 16 2.2
FO = 128 2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
Maximum Skew
FO = 16
0.4
0.5
0.5
0.6
0.5
0.7
0.6
0.8
0.8
1.2
FO = 128
Minimum Period
FO = 16
4.7
5.4
5.6
6.1
6.3
7.2
7.5
10.0
10.4
FO = 128 4.8
fMAX
Maximum
Frequency
FO = 16
FO = 128
188
181
175
168
160
154
139
134
83 MHz
80
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
3.3
4.0
3.8
4.6
4.3
5.2
5.1
6.1
7.2
ns
ns
ns
ns
ns
ns
tDHL
8.6
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.7
4.3
4.9
5.8
8.0
4.7
5.4
6.1
7.2
10.1
17.1
12.6
7.9
9.1
10.4
7.7
12.2
9.0
5.9
6.8
0.02
0.03
0.02
0.03
0.03
0.03
0.03
0.04
0.04 ns/pF
0.06 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
1-47
Revision 12
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.9
3.4
4.5
3.9
5.1
4.4
6.05
5.2
8.5
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
7.3
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
3.4
3.9
4.4
5.2
7.3
4.9
5.6
6.4
7.5
10.5
17.0
12.6
7.9
9.1
10.4
7.7
12.2
9.0
5.9
6.8
0.03
0.02
0.04
0.02
0.04
0.03
0.05
0.03
0.07 ns/pF
0.04 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
Revision 12
1-48
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
1.7
3.7
1.7
1.7
1.7
2.0
4.3
2.0
2.0
2.0
2.3
4.9
2.3
2.3
2.3
2.7
5.7
2.7
2.7
2.7
3.7
8.0
3.7
3.7
3.7
ns
ns
ns
ns
ns
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.9
2.7
3.4
4.1
7.1
2.2
3.1
3.9
4.8
8.1
2.5
3.5
4.4
5.4
9.2
3.0
4.1
4.2
5.7
ns
ns
ns
ns
ns
5.2
7.3
6.3
8.9
10.9
15.2
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
4.3
5.0
5.6
6.6
9.2
ns
3
tHD
Flip-Flop (Latch) Data Input Hold 0.0
0.0
5.0
0.0
5.3
0.0
5.6
0.0
5.6
0.0
6.6
0.0
7.0
0.0
9.2
0.0
9.8
ns
ns
ns
ns
tSUENA
tHENA
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
4.3
0.0
4.6
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
6.8
5.3
7.8
5.6
8.9
7.0
9.8
ns
ns
tA
Flip-Flop Clock Input Period
10.4
14.6
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
109
101
92
80
48 MHz
Input Module Propagation Delays
tINYH
tINYL
Pad-to-Y HIGH
Pad-to-Y LOW
1.0
0.9
1.1
1.0
1.3
1.1
1.5
1.3
2.1
1.9
ns
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1-49
Revision 12
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.9
3.6
4.4
5.1
8.0
3.3
4.2
5.0
5.9
9.3
3.8
4.8
4.5
5.6
6.3
7.8
ns
ns
ns
ns
ns
5.7
6.7
9.4
6.7
7.8
11.0
17.2
10.5
12.4
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input LOW to HIGH FO = 16
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
ns
ns
ns
ns
ns
FO = 128
Input HIGH to LOW FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
Maximum Skew
FO = 16
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.2
1.6
FO = 128
Minimum Period
FO = 16
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
113
109
105
101
96
92
83
80
50 MHz
48
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.6
5.4
6.4
6.1
7.3
7.2
8.6
10.0
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
12.0
11.3
14.1
23.9
17.7
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
5.2
6.0
6.9
8.1
6.6
7.6
8.6
10.1
17.1
12.6
0.04
0.06
11.1
8.2
12.8
9.5
14.5
10.7
0.04
0.05
0.03
0.04
0.03
0.04
0.06 ns/pF
0.08 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
Revision 12
1-50
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed
–1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
5.5
4.8
6.4
5.5
7.2
6.2
8.5
7.3
11.9
10.2
10.2
14.7
23.9
17.7
ns
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4.7
5.5
6.2
7.3
6.8
7.9
8.9
10.5
17.1
12.6
0.07
0.04
11.1
8.2
12.8
9.5
14.5
10.7
0.06
0.04
0.05
0.03
0.05
0.03
0.10 ns/pF
0.06 ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1-51
Revision 12
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.2
1.3
1.2
1.2
1.3
1.4
1.4
1.6
1.5
1.6
1.6
1.8
1.8
1.9
1.8
2.1
2.5
2.7
2.6
2.9
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
0.7
0.9
1.2
1.4
2.3
0.8
1.0
1.3
1.5
2.6
0.9
1.2
1.5
1.7
2.9
1.0
1.4
1.7
2.0
3.4
1.4
1.9
2.4
2.9
4.8
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.4
0.0
3.4
0.0
0.5
0.0
3.8
0.0
0.5
0.0
4.3
0.0
0.6
0.0
5.0
0.0
0.8
0.0
7.0
ns
ns
ns
ns
tSUENA Flip-Flop (Latch) Enable Set-Up
tHENA Flip-Flop (Latch) Enable Hold
tWCLKA Flip-Flop (Latch) Clock Active
Pulse Width
tWASYN Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Set-Up
Output Buffer Latch Hold
3.5
0.0
0.3
0.0
0.3
3.8
0.0
0.3
0.0
0.3
4.3
0.0
0.4
0.0
0.4
5.1
0.0
0.4
0.0
0.4
7.1
0.0
0.6
0.0
0.6
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU Output Buffer Latch Set-Up
fMAX
Flip-Flop (Latch) Clock Frequency
268
244
224
195
117 MHz
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-52
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.0
0.8
1.3
1.3
1.2
0.9
1.4
1.4
1.3
1.0
1.6
1.6
1.6
1.2
1.9
1.9
2.2
1.7
2.7
2.7
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.0
2.3
2.5
2.8
3.7
2.2
2.5
2.8
3.1
4.1
2.5
2.9
3.2
3.5
4.7
3.0
3.4
3.7
4.1
5.5
4.2
4.7
5.2
5.7
7.7
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH
tCKL
FO = 32
FO = 256
2.4
2.7
2.7
3.0
3.0
3.4
3.6
4.0
5.0
5.5
ns
ns
FO = 32
FO = 256
3.5
3.9
3.9
4.3
4.4
4.9
5.2
5.7
7.3
8.0
ns
ns
Input HIGH to LOW
Minimum Pulse
Width HIGH
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width LOW
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
FO = 32
FO = 256
0.3
0.3
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
ns
ns
Maximum Skew
Input Latch
External Set-Up
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch
External Hold
FO = 32
FO = 256
2.3
2.2
2.6
2.4
3.0
3.3
3.5
3.9
4.9
5.5
ns
ns
FO = 32
FO = 256
3.4
3.7
3.7
4.1
4.0
4.5
4.7
5.2
7.8
8.6
ns
ns
Minimum Period
FO = 32
FO = 256
296
268
269
244
247
224
215
195
129 MHz
117 MHz
fMAX
Maximum Frequency
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-53
Revision 12
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.5
2.9
2.6
2.9
4.9
5.3
2.6
2.6
2.7
3.2
2.9
3.2
5.4
5.9
2.9
2.9
3.1
3.6
3.3
3.7
6.2
6.7
3.3
3.3
3.6
4.3
3.9
4.3
7.3
7.9
3.8
3.8
5.1
6.0
5.5
6.1
ns
ns
ns
ns
10.2 ns
11.1 ns
5.3
5.3
ns
ns
ns
ns
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.2
7.4
5.8
8.2
6.6
9.3
7.7
10.8 ns
tACO
Array Clock-to-Out
10.9
15.3 ns
(Pad-to-Pad), 64 Clock Loading
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-54
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.4
2.9
2.7
2.9
4.9
5.3
4.2
4.2
2.7
3.2
2.9
3.2
5.4
5.9
4.6
4.6
3.1
3.6
3.3
3.7
6.2
6.7
5.2
5.2
3.6
4.3
3.9
4.3
7.3
7.9
6.1
6.1
5.1
6.0
5.5
6.1
ns
ns
ns
ns
10.2 ns
11.1 ns
8.6
8.6
ns
ns
ns
ns
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.2
7.4
5.8
8.2
6.6
9.3
7.7
10.8 ns
tACO
Array Clock-to-Out (
10.9
15.3 ns
Pad-to-Pad), 64 Clock Loading
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-55
Revision 12
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.6
1.8
1.7
2.0
1.8
2.0
1.9
2.2
2.1
2.3
2.1
2.5
2.5
2.7
2.5
2.9
3.5
3.8
3.5
4.1
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.0
1.3
1.6
1.9
3.2
1.1
1.4
1.8
2.1
3.6
1.2
1.6
2.0
2.4
4.1
1.4
1.9
2.4
2.9
4.8
2.0
2.7
3.3
4.0
6.7
ns
ns
ns
ns
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.5
0.5
0.0
0.6
0.0
5.3
0.6
0.0
0.7
0.0
6.0
0.7
0.0
0.8
0.0
7.0
0.9
0.0
1.2
0.0
9.8
ns
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.0
0.6
0.0
4.7
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
6.2
6.9
7.8
9.2
12.9
ns
Asynchronous Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
5.0
0.0
0.3
0.0
0.3
5.6
0.0
0.3
0.0
0.3
6.2
0.0
0.3
0.0
0.3
7.1
0.0
0.4
0.0
0.4
9.9
0.0
0.6
0.0
0.6
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
ns
ns
ns
161
146
135
117
70
MHz
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-56
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.5
1.2
1.8
1.8
1.6
1.3
2.0
2.0
1.8
1.4
2.3
2.3
2.17
1.7
2.7
3.0
2.4
3.7
3.7
ns
ns
ns
ns
2.7
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.8
3.2
3.5
3.9
5.2
3.2
3.5
3.9
4.3
5.8
3.6
4.0
4.4
4.9
6.6
4.2
4.7
5.2
5.7
7.7
5.9
6.6
ns
ns
ns
ns
ns
7.3
8.0
10.8
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width FO = 32
HIGH FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
Minimum Pulse Width FO = 32
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
LOW
FO = 256
Maximum Skew
FO = 32
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.9
0.9
ns
ns
FO = 256
Input Latch External FO = 32
Set-Up FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
3.3
3.7
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
ns
Hold
FO = 256
Minimum Period
FO = 32
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
ns
FO = 256
fMAX
Notes:
Maximum Frequency FO = 32
FO = 256
177
161
161
146
148
135
129
117
77
70
MHz
MHz
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-57
Revision 12
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.4
4.0
3.7
4.1
6.9
7.5
5.8
5.8
3.8
4.5
4.1
4.5
7.6
8.3
6.5
6.5
4.3
5.1
4.6
5.1
8.6
9.4
7.3
7.3
5.1
6.1
7.1
8.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.6
6.1
8.5
10.2
11.1
8.6
14.2
15.5
12.0
12.0
G-to-Pad LOW
8.6
I/O Latch Set-Up
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7
9.7
10.9
15.4
12.9
18.1
18.0
25.3
tACO
Array Clock-to-Out
12.2
13.5
ns
(Pad-to-Pad),64 Clock Loading
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.00
0.09
0.00
0.10
0.00
0.10
0.10
0.10
0.01 ns/pF
0.10 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-58
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.4
4.1
3.7
4.1
6.9
7.5
5.8
5.8
3.8
4.5
4.1
4.5
7.6
8.3
6.5
6.5
5.5
4.2
4.6
5.1
8.6
9.4
7.3
7.3
6.4
5.0
9.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.6
6.1
8.5
10.2
11.1
8.6
14.2
15.5
12.0
12.0
G-to-Pad LOW
8.6
I/O Latch Set-Up
0.7
0.0
0.8
0.0
0.9
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7
9.7
10.9
15.4
12.9
18.1
18.0
25.3
tACO
Array Clock-to-Out
(Pad-to-Pad),
12.2
13.5
ns
64 Clock Loading
dTLH
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-59
Revision 12
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.4
1.4
1.4
1.6
1.5
1.6
1.5
1.7
1.7
1.8
1.7
2.0
2.0
2.1
2.0
2.3
2.8
3.0
2.8
3.3
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
0.8
1.0
1.3
1.6
2.6
0.9
1.2
1.4
1.7
2.9
1.0
1.3
1.6
2.0
3.2
1.2
1.5
1.9
2.3
3.8
1.6
2.1
2.7
3.2
5.3
ns
ns
ns
ns
ns
Logic Module Sequential Timing3,4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.7
0.0
3.4
0.0
0.8
0.0
3.8
0.0
0.9
0.0
4.3
0.0
1.0
0.0
5.0
0.0
1.4
0.0
7.1
ns
ns
ns
ns
tSUENA Flip-Flop (Latch) Enable Set-Up
tHENA Flip-Flop (Latch) Enable Hold
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width
4.5
5.0
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Set-Up
Output Buffer Latch Hold
6.8
0.0
0.5
0.0
0.5
7.6
0.0
0.5
0.0
0.5
8.6
0.0
0.6
0.0
0.6
10.1
0.0
0.7
0.0
0.7
14.1
0.0
1.0
0.0
1.0
ns
ns
tINH
tINSU
tOUTH
ns
ns
tOUTSU Output Buffer Latch Set-Up
ns
fMAX
Flip-Flop (Latch) Clock Frequency
215
195
179
156
94
MHz
Notes:
1. For dual-module macros, use t
appropriate.
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, point and position whichever is
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-60
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.1
0.8
1.4
1.4
1.2
0.9
1.6
1.6
1.3
1.0
1.8
1.8
1.6
1.2
2.1
2.1
2.2
1.7
2.9
2.9
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.8
2.1
2.3
2.6
3.6
2.0
2.3
2.6
3.0
4.0
2.3
2.6
3.0
3.3
4.6
2.7
3.1
3.5
3.9
5.4
4.0
4.3
4.9
5.4
7.5
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input LOW to HIGH FO = 32
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
FO = 384
tCKL
Input HIGH to LOW FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
tPWH
tPWL
tCKSW
Minimum Pulse Width FO = 32
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
HIGH
FO = 384
Minimum Pulse Width FO = 32
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
LOW
FO = 384
Maximum Skew
FO = 32
0.3
0.3
0.4
0.4
0.4
0.4
0.5
0.5
0.7
0.7
ns
ns
FO = 384
tSUEXT Input Latch External FO = 32
Set-Up FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
Hold
FO = 384
tP
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
fMAX
Notes:
Maximum Frequency FO = 32
FO = 384
237
215
215
195
198
179
172
156
103 MHz
94 MHz
1. For dual-module macros, use t
appropriate.
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, point and position whichever is
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-61
Revision 12
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
2.5
3.0
2.7
3.0
5.4
5.0
2.9
2.9
5.7
2.8
3.3
3.0
3.3
6.0
5.6
3.2
3.2
6.3
3.2
3.7
3.4
3.8
6.8
6.3
3.6
3.6
7.1
3.7
4.4
4.0
4.4
8.0
7.4
4.3
4.3
8.4
5.2
6.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.6
6.2
11.2
10.4
6.0
tGHL
G-to-Pad LOW
6.0
tLCO
I/O Latch Clock-to-Out
11.9
(Pad-to-Pad), 64 Clock Loading
tACO
Array Clock-to-Out
8.0
8.9
10.1
11.9
16.7
ns
(Pad-to-Pad), 64 Clock Loading
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.03
0.04
0.03
0.04
0.03
0.04
0.04
0.05
0.06 ns/pF
0.07 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
appropriate.
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, point and position whichever is
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-62
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.2
2.5
2.7
3.0
5.4
5.0
5.1
5.1
5.7
3.6
2.7
3.0
3.3
6.0
5.6
5.6
5.6
6.3
4.0
3.1
3.4
3.8
6.8
6.3
6.4
6.4
7.1
4.7
3.6
4.0
4.4
8.0
7.4
7.5
7.5
8.4
6.6
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.6
6.2
11.2
10.4
10.5
10.5
11.9
tGHL
G-to-Pad LOW
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
0.03
11.9
0.04
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.06 ns/pF
Notes:
1. For dual-module macros, use t
appropriate.
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, point and position whichever is
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-63
Revision 12
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
1.9
2.0
1.9
2.2
2.1
2.2
2.1
2.4
2.4
2.5
2.4
2.8
2.8
3.0
2.8
3.3
4.0
4.2
4.0
4.6
ns
ns
ns
ns
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.1
1.5
1.8
2.2
3.6
1.2
1.6
2.0
2.4
4.0
1.4
1.8
2.3
2.7
4.5
1.6
2.1
2.7
3.2
5.3
2.3
3.0
3.8
4.5
7.5
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold 0.0
0.0
1.1
0.0
5.3
0.0
1.2
0.0
6.0
0.0
1.4
0.0
7.1
0.0
2.0
0.0
9.9
ns
ns
ns
ns
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
1.0
0.0
4.8
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
6.2
6.9
7.9
9.2
12.9
ns
Asynchronous Pulse Width
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
9.5
0.0
0.7
0.0
0.7
10.6
0.0
0.8
0.0
0.8
12.0
0.0
14.1
0.0
19.8
0.0
1.4
0.0
1.4
ns
ns
ns
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
0.9
1.01
0.0
0.0
0.89
1.01
129
117
108
94
56 MHz
1. For dual-module macros use t
+ t
+ taped, to + t
+ taped, or t
+ t
+ tusk, whichever is appropriate.
RD1
PD1
RD1
RD1
PD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-64
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
1.5
1.1
2.0
2.0
1.6
1.3
2.2
2.2
1.9
1.4
2.5
2.5
2.2
1.7
2.9
2.9
3.1
2.4
4.1
4.1
ns
ns
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.6
2.9
3.3
3.6
5.1
2.9
3.2
3.6
4.0
5.6
3.2
3.7
4.1
4.6
6.4
3.8
4.3
4.9
5.4
7.5
5.3
6.1
ns
ns
ns
ns
ns
6.8
7.6
10.5
Global Clock Network
tCKH
Input LOW to HIGH FO = 32
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
FO = 384
tCKL
Input HIGH to LOW FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
Minimum Pulse
Width LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
Maximum Skew
FO = 32
FO = 384
0.5
2.2
0.5
2.4
0.6
2.7
0.7
3.2
1.0
4.5
ns
ns
Input Latch External FO = 32
Set-Up FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
FO = 384
Minimum Period
FO = 32
FO = 384
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
fMAX
Notes:
Maximum Frequency FO = 32
FO = 384
142
129
129
117
119
108
103
94
62 MHz
56 MHz
1. For dual-module macros use t
+ t
+ taped, to + t
+ taped, or t
+ t
+ tusk, whichever is appropriate.
RD1
PD1
RD1
RD1
PD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-65
Revision 12
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.5
4.1
3.8
4.2
7.6
7.0
4.8
4.8
8.0
3.9
4.6
4.2
4.6
8.4
7.8
5.3
5.3
8.9
4.4
5.2
4.8
5.3
9.5
8.8
6.0
6.0
10.1
5.2
6.1
7.3
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.6
7.8
6.2
8.7
11.2
10.4
7.2
15.7
14.5
10.0
10.0
16.7
tGHL
G-to-Pad LOW
7.2
tLCO
I/O Latch Clock-to-Out
11.9
(Pad-to-Pad), 64 Clock Loading
tACO
Array Clock-to-Out
11.3
12.5
14.2
16.7
23.3
ns
(Pad-to-Pad), 64 Clock Loading
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.5
3.4
3.8
4.2
7.6
7.0
7.1
7.1
8.0
5.0
3.8
4.2
4.6
8.4
7.8
7.9
7.9
8.9
5.6
4.3
4.8
5.3
9.5
8.8
8.9
8.9
10.1
6.6
5.1
9.3
7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.6
7.8
6.2
8.7
11.2
10.4
10.5
10.5
11.9
15.7
14.5
14.7
14.7
16.7
tGHL
G-to-Pad LOW
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
tACO
Array Clock-to-Out
11.3
12.5
14.2
16.7
23.3
ns
(Pad-to-Pad),64 Clock Loading
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.05
0.04
0.05
0.05
0.06
0.06
0.07
0.08 ns/pF
0.10 ns/pF
dTHL
Notes:
1. For dual-module macros use t
+ t
+ taped, to + t
+ taped, or t
+ t
+ tusk, whichever is appropriate.
RD1
PD1
RD1
RD1
PD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-66
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.2
1.4
1.3
1.6
1.5
1.8
1.8
2.1
2.5
3.0
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
0.8
1.0
1.3
1.5
2.4
0.9
1.2
1.4
1.7
2.7
1.0
1.3
1.6
1.9
3.0
1.2
1.5
1.9
2.2
3.6
1.7
2.1
2.6
3.1
5.0
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.2
1.4
1.3
1.6
1.5
1.9
1.8
2.7
2.5
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.3
0.0
0.4
0.0
0.4
0.0
0.5
0.0
0.7
0.0
tRO
1.4
1.6
1.8
2.1
2.9
tSUENA
tHENA
tWCLKA
0.4
0.0
3.3
0.5
0.0
3.7
0.5
0.0
4.2
0.6
0.0
4.9
0.8
0.0
6.9
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
4.4
4.8
5.3
6.5
9.0
Asynchronous Pulse Width
ns
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.0
1.3
1.1
1.4
1.3
1.6
1.5
1.9
2.1
2.6
ns
ns
ns
ns
ns
0.0
0.5
4.7
0.0
0.5
5.2
0.0
0.6
5.9
0.0
0.7
6.9
0.0
1.0
9.7
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-67
Revision 12
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.8
2.1
2.3
2.5
3.4
2.0
2.3
2.5
2.8
3.8
2.3
2.6
2.9
3.2
4.3
2.7
3.1
3.4
3.7
5.1
3.8
4.3
4.8
5.2
7.1
ns
ns
ns
ns
ns
Global Clock Network
FO = 32
FO = 486
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
tCKH
Input LOW to HIGH
FO = 32
FO = 486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
tCKL
Input HIGH to LOW
Minimum Pulse
Width HIGH
FO = 32
FO = 486 2.4
2.2
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tPWH
tPWL
Minimum Pulse
Width LOW
FO = 32 2.2
FO = 486 2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
FO = 32
FO = 486
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
1.1
1.1
ns
ns
tCKSW
tSUEXT
tHEXT
Maximum Skew
Input Latch External
Set-Up
FO = 32
FO = 486 0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External
Hold
FO = 32 2.8
FO = 486 3.3
FO = 32 4.7
FO = 486 5.1
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
Minimum Period
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
tP
(1/fMAX
)
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-68
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
TTL Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
2.4
2.8
2.5
2.8
5.2
4.8
2.9
2.9
2.7
3.2
2.8
3.1
5.7
5.3
3.2
3.2
3.1
3.6
3.2
3.5
6.5
6.0
3.6
3.6
3.6
4.2
3.8
4.2
7.6
7.1
4.3
4.3
5.1
5.9
5.3
5.9
10.7
9.9
6.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Output Set-Up
I/O Latch Output Hold
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
22.0
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.03
0.04
0.03
0.04
0.03
0.05
0.04
0.07 ns/pF
0.06 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-69
Revision 12
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.1
2.4
2.5
2.8
5.2
4.8
4.9
4.9
3.5
2.6
2.8
3.1
5.7
5.3
5.4
5.4
3.9
3.0
3.2
3.5
6.5
6.0
6.2
6.2
4.6
3.5
3.8
4.2
7.6
7.1
7.2
7.2
6.4
4.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.3
5.8
10.7
9.9
10.1
10.1
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.5
6.1
6.9
8.1
11.3
22.0
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
ns
dTLH
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.04
0.03
0.04
0.03
0.04
0.03
0.05
0.04
0.07 ns/pF
0.06 ns/pF
dTHL
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-70
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.0
1.1
1.8
2.2
2.1
2.5
2.5
3.0
3.4
4.2
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.7
2.0
1.1
1.5
1.8
1.3
1.6
2.0
2.3
3.7
1.4
1.8
2.2
2.6
4.2
1.7
2.1
2.6
3.1
5.0
2.3
3.0
3.7
4.3
7.0
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.1
3.4
2.0
1.9
2.3
2.1
2.7
2.5
3.7
3.4
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.4
0.0
0.5
0.0
0.6
0.0
0.7
0.0
0.9
0.0
tRO
2.0
2.2
2.5
2.9
4.1
tSUENA
tHENA
tWCLKA
0.6
0.0
4.6
0.6
0.0
5.2
0.7
0.0
5.8
0.8
0.0
6.9
1.2
0.0
9.6
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
6.1
6.8
7.7
9.0
12.6
Asynchronous Pulse Width
ns
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.4
1.8
1.6
1.9
1.8
2.2
2.2
2.6
3.0
3.6
ns
ns
ns
ns
ns
0.0
0.7
6.5
0.0
0.7
7.3
0.0
0.8
8.2
0.0
1.0
9.7
0.0
1.4
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
13.5
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-71
Revision 12
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.6
2.9
3.2
3.5
4.8
2.9
3.2
3.6
3.9
5.3
3.2
3.6
4.0
4.4
6.1
3.8
4.3
4.8
5.2
7.1
5.3
6.0
6.6
7.3
ns
ns
ns
ns
10.0 ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 486
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0 ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6 ns
12.4 ns
tPWH
tPWL
tCKSW
tSUEXT
Minimum Pulse
Width HIGH
FO = 32
FO = 486
3.0
3.3
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
Minimum Pulse
Width LOW
FO = 32
FO = 486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
Maximum Skew
FO = 32
FO = 486
0.8
0.8
0.8
0.8
1.0
1.0
1.1
1.1
1.6
1.6
ns
ns
Input Latch External FO = 32
Set-Up FO = 486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
Data-to-Pad LOW
3.4
4.0
3.6
3.9
7.2
6.7
4.8
4.8
3.8
4.4
4.0
4.4
8.0
7.5
5.3
5.3
4.3
5.0
4.5
5.0
9.1
8.5
6.0
6.0
5.0
5.9
5.3
5.8
10.7
9.9
7.2
7.2
7.1
8.3
7.4
8.2
ns
ns
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
14.9 ns
13.9 ns
10.0 ns
10.0 ns
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-72
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
TTL Output Module Timing5 (continued)
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
22.0
15.9 ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
30.8 ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
0.05
0.04
0.05
0.04
0.06
0.05
0.07
0.06
0.10 ns/pF
0.08 ns/pF
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.8
3.5
3.6
3.4
7.2
6.7
6.8
6.8
5.3
3.9
4.0
4.0
8.0
7.5
7.6
7.6
5.5
4.1
4.5
5.0
9.0
8.5
8.6
8.6
6.4
4.9
9.0
6.8
7.4
8.2
ns
ns
ns
ns
5.3
5.8
10.7
9.9
14.9 ns
13.9 ns
14.2 ns
14.2 ns
ns
10.1
10.1
G-to-Pad LOW
I/O Latch Set-Up
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
22.0
15.9 ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
30.8 ns
dTLH
dTHL
tHEXT
Capacitive Loading, LOW to HIGH
Capacitive Loading, HIGH to LOW
Input Latch External FO = 32
0.05
0.04
0.05
0.04
0.06
0.05
0.07
0.06
0.10 ns/pF
0.08 ns/pF
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
Hold
FO = 486
tP
Minimum Period
FO = 32
FO = 486
7.8
8.6
8.7
9.5
9.5
10.4
10.8
11.9
18.2
19.9
ns
ns
(1/fMAX
)
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-73
Revision 12
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.3
1.6
1.5
1.8
1.7
2.0
2.0
2.4
2.7
3.3
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO = 1 Routing Delay
FO = 2 Routing Delay
FO =3 Routing Delay
0.9
1.3
1.6
2.0
3.3
0.3
1.0
1.4
1.8
2.2
3.7
0.4
1.2
1.6
2.0
2.5
4.2
0.4
1.4
1.9
2.4
2.9
4.9
0.5
2.0
2.7
3.4
4.1
6.9
0.7
ns
ns
ns
ns
ns
ns
FO = 4 Routing Delay
FO = 8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing3, 4
tCO
tGO
tSUD
tHD
tRO
Flip-Flop Clock-to-Output
Latch Gate-to-Output
1.3
1.3
1.4
1.4
1.6
1.6
1.9
1.9
2.7
2.7
ns
ns
ns
ns
ns
ns
ns
ns
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
0.3
0.0
0.3
0.0
0.4
0.0
0.5
0.0
0.7
0.0
1.6
1.7
2.0
2.3
3.2
tSUENA Flip-Flop (Latch) Enable Set-Up
tHENA Flip-Flop (Latch) Enable Hold
0.7
0.0
0.8
0.0
3.7
0.9
0.0
4.2
1.0
0.0
4.9
1.4
0.0
6.9
tWCLKA Flip-Flop (Latch) Clock Active 3.3
Pulse Width
tWASYN Flip-Flop (Latch) Asynchronous 4.4
Pulse Width
4.8
5.5
6.4
9.0
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
6.8
3.4
7.5
7.5
3.8
8.5
8.5
4.3
10.0
10.0
5.0
14.0
14.0
7.0
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
3.4
3.8
4.3
5.0
7.0
1.6
1.8
0.0
2.0
0.0
2.4
0.0
3.4
0.0
Synchronous SRAM Operations (continued)
tADH
Address/Data Hold Time
0.0
ns
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-74
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
tRENSU Read Enable Set-Up
0.6
3.4
2.7
0.0
2.8
0.0
0.7
3.8
3.0
0.0
3.1
0.0
0.8
4.3
3.4
0.0
3.5
0.0
0.9
5.0
4.0
0.0
4.1
0.0
1.3
7.0
5.6
0.0
5.7
0.0
ns
ns
ns
ns
ns
ns
tRENH
Read Enable Hold
tWENSU Write Enable Set-Up
tWENH
tBENS
tBENH
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
Asynchronous SRAM Operations
tRPD Asynchronous Access Time
tRDADV Read Address Valid
tADSU Address/Data Set-Up Time
tADH Address/Data Hold Time
8.1
9.0
10.2
12.0
16.8
ns
ns
ns
ns
ns
8.8
1.6
0.0
9.8
1.8
0.0
0.7
11.1
2.0
0.0
0.8
13.0
2.4
18.2
3.4
0.0
0.0
tRENSUA Read Enable Set-Up to Address 0.6
Valid
0.9
1.3
tRENHA Read Enable Hold
tWENSU Write Enable Set-Up
3.4
2.7
0.0
3.8
3.0
0.0
4.3
3.4
0.0
5.0
4.0
0.0
7.0
5.6
0.0
ns
ns
ns
ns
tWENH
tDOH
Write Enable Hold
Data Out Hold Time
1.2
1.3
1.5
1.8
2.5
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.0
1.4
1.1
1.6
1.3
1.8
1.5
2.1
2.1
2.9
ns
ns
ns
ns
ns
0.0
0.5
4.7
0.0
0.5
5.2
0.0
0.6
5.9
0.0
0.7
6.9
0.0
1.0
9.7
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.0
2.3
2.6
3.0
4.3
2.2
2.6
2.9
3.3
4.8
2.5
2.9
3.3
3.8
5.5
2.9
3.4
3.9
4.4
6.4
4.1
4.8
5.5
6.2
9.0
ns
ns
ns
ns
ns
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-75
Revision 12
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
Global Clock Network
tCKH Input LOW to HIGH
tCKL
FO = 32
FO = 635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
FO = 32
FO = 635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
Input HIGH to LOW
Minimum Pulse
Width HIGH
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width LOW
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
FO = 32
FO = 635
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
ns
ns
Maximum Skew
Input Latch External FO = 32
Set-Up FO = 635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch External FO = 32
Hold
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
FO = 635
Minimum Period
FO = 32
FO = 635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
(1/fMAX
)
Maximum Datapath FO = 32
Frequency FO = 635
180
166
164
151
151
139
131
121
79
73
MHz
MHz
fMAX
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.6
3.0
2.7
3.0
5.3
2.8
3.3
3.0
3.3
5.8
3.2
3.7
3.3
3.7
6.6
3.8
4.4
3.9
4.3
7.8
5.3
6.2
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
5.5
6.1
10.9
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-76
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
TTL Output Module Timing5 (Continued)
tENLZ
tGLH
tGHL
tLSU
tLH
Enable Pad LOW to Z
G-to-Pad HIGH
4.9
2.9
2.9
5.5
3.3
3.3
6.2
3.7
3.7
7.3
4.4
4.4
10.2
6.1
ns
ns
ns
ns
ns
ns
G-to-Pad LOW
6.1
I/O Latch Output Set-Up
I/O Latch Output Hold
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.7
7.8
6.3
8.6
7.1
9.8
8.4
11.8
16.1
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
11.5
0.10
0.10
ns
dTLH
dTHL
Notes:
Capacitive Loading,
LOW to HIGH
0.07
0.07
0.08
0.08
0.09
0.09
0.14 ns/pF
0.14 ns/pF
Capacitive Loading,
HIGH to LOW
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-77
Revision 12
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Parameter / Description
Units
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
3.5
2.5
2.7
2.9
5.3
4.9
5.0
5.0
3.9
2.7
3.0
3.3
5.8
5.5
5.6
5.6
4.5
3.1
3.3
3.7
6.6
6.2
6.3
6.3
5.2
3.6
3.9
4.3
7.8
7.3
7.5
7.5
7.3
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
6.1
10.9
10.2
10.4
10.4
G-to-Pad LOW
I/O Latch Set-Up
0.5
0.0
0.5
0.0
0.6
0.0
0.7
0.0
1.0
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.7
7.8
6.3
8.6
7.1
9.8
8.4
11.8
16.1
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
11.5
0.10
0.10
ns
dTLH
dTHL
Notes:
Capacitive Loading,
LOW to HIGH
0.07
0.07
0.08
0.08
0.09
0.09
0.14 ns/pF
0.14 ns/pF
Capacitive Loading,
HIGH to LOW
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-78
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.9
2.2
2.1
2.5
2.3
2.8
2.7
3.3
3.8
4.7
ns
ns
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
Decode-to-Output Routing Delay
1.3
1.8
2.3
2.8
4.6
0.5
1.5
2.0
2.5
3.1
5.2
0.5
1.7
2.3
2.8
3.5
5.8
0.6
2.0
2.7
3.4
4.1
6.9
0.7
2.7
3.7
4.7
5.7
9.6
1.0
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.8
1.8
2.0
2.0
2.3
2.3
2.7
2.7
3.7
3.7
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSUD
tHD
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
0.4
0.0
0.5
0.0
0.6
0.0
0.7
0.0
0.9
0.0
tRO
2.2
2.4
2.7
3.2
4.5
tSUENA
tHENA
tWCLKA
1.0
0.0
4.6
1.1
0.0
5.2
1.2
0.0
5.8
1.4
0.0
6.9
2.0
0.0
9.6
Flip-Flop (Latch)
Clock Active Pulse Width
tWASYN
Flip-Flop (Latch)
6.1
6.8
7.7
9.0
12.6
ns
Asynchronous Pulse Width
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
9.5
4.8
10.5
10.5
5.3
11.9
11.9
6.0
14.0
14.0
7.0
19.6
19.6
9.8
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
Notes:
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
4.8
5.3
6.0
7.0
9.8
2.3
2.5
2.8
3.4
4.8
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-79
Revision 12
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Synchronous SRAM Operations (continued)
tADH
Address/Data Hold Time
Read Enable Set-Up
Read Enable Hold
0.0
0.9
4.8
3.8
0.0
3.9
0.0
0.0
1.0
5.3
4.2
0.0
4.3
0.0
0.0
1.1
6.0
4.8
0.0
4.9
0.0
0.0
1.3
7.0
5.6
0.0
5.7
0.0
0.0
1.8
9.8
7.8
0.0
8.0
0.0
ns
ns
ns
ns
ns
ns
ns
tRENSU
tRENH
tWENSU
tWENH
tBENS
tBENH
Write Enable Set-Up
Write Enable Hold
Block Enable Set-Up
Block Enable Hold
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
11.3
12.6
14.3
16.8
23.5
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
12.3
2.3
13.7
2.5
15.5
2.8
18.2
3.4
25.5
4.8
Address/Data Set-Up Time
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
tRENSUA Read Enable Set-Up to Address 0.9
Valid
1.0
1.1
1.3
1.8
tRENHA
tWENSU
tWENH
tDOH
Read Enable Hold
Write Enable Set-Up
Write Enable Hold
Data Out Hold Time
4.8
3.8
0.0
5.3
4.2
0.0
6.0
4.8
0.0
7.0
5.6
0.0
9.8
7.8
0.0
ns
ns
ns
ns
1.8
2.0
2.1
2.5
3.5
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad-to-Y
Input Latch Gate-to-Output
Input Latch Hold
1.4
2.0
1.6
2.2
1.8
2.5
2.1
2.9
3.0
4.1
ns
ns
ns
ns
ns
0.0
0.7
6.5
0.0
0.7
7.3
0.0
0.8
8.2
0.0
1.0
9.7
0.0
1.4
tINSU
tILA
Input Latch Set-Up
Latch Active Pulse Width
13.5
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-80
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
2.8
3.2
3.7
4.2
6.1
3.1
3.5
4.1
4.6
6.8
3.5
4.1
4.7
5.3
7.7
4.1
4.8
5.5
6.2
9.0
5.7
6.7
ns
ns
ns
ns
ns
7.7
8.7
12.6
Global Clock Network
tCKH Input LOW to HIGH
tCKL
FO = 32
FO = 635
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
FO = 32
FO = 635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
Input HIGH to LOW
Minimum Pulse
Width HIGH
FO = 32
FO = 635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse
Width LOW
FO = 32
FO = 635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
FO = 32
FO = 635
1.0
1.0
1.2
1.2
1.3
1.3
1.5
1.5
2.2
2.2
ns
ns
Maximum Skew
Input Latch
External Set-Up
FO = 32
FO = 635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Input Latch
External Hold
FO = 32
FO = 635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
Minimum Period
FO = 32
FO = 635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
(1/fMAX
)
Maximum
Frequency
Datapath FO = 32
FO = 635
108
100
98
91
90
83
79
73
47
44
MHz
MHz
fMAX
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.6
4.2
4.0
4.6
4.2
4.6
8.2
4.5
5.2
4.7
5.2
9.3
5.3
6.2
7.4
8.6
ns
ns
ns
ns
ns
tDHL
Data-to-Pad LOW
tENZH
tENZL
tENHZ
Notes:
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
3.7
5.5
7.7
4.1
6.1
8.5
7.34
10.9
15.3
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-81
Revision 12
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Parameter / Description
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
TTL Output Module Timing5
tENLZ
tGLH
tGHL
tLSU
tLH
Enable Pad LOW to Z
G-to-Pad HIGH
6.9
4.9
4.9
7.6
5.5
5.5
8.7
6.2
6.2
10.2
7.3
14.3
10.2
10.2
ns
ns
ns
ns
ns
ns
G-to-Pad LOW
7.3
I/O Latch Output Set-Up
I/O Latch Output Hold
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9
8.8
10.0
13.7
11.8
16.1
16.5
22.5
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.9
12.1
ns
dTLH
dTHL
Capacitive Loading, LOW to HIGH
0.10
0.10
0.11
0.11
0.12
0.12
0.14
0.14
0.20 ns/pF
0.20 ns/pF
Capacitive Loading, HIGH to LOW
CMOS Output Module Timing5
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
4.9
3.4
3.7
4.1
7.4
6.9
7.0
7.0
5.5
3.8
4.1
4.6
8.2
7.6
7.8
7.8
6.2
4.3
4.7
5.2
9.3
8.7
8.9
8.9
7.3
5.1
10.3
7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.7
6.1
8.5
10.9
10.2
10.4
10.4
15.3
14.3
14.6
14.6
G-to-Pad LOW
I/O Latch Set-Up
0.7
0.0
0.7
0.0
0.8
0.0
1.0
0.0
1.4
0.0
tLH
I/O Latch Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
Notes:
1. For dual-module macros, use t
+ t
+ t
, t + t
+ t
, or t
+ t
+ t
, whichever is appropriate.
SUD
PD1
RD1
PDn CO
RD1
PDn
PD1
RD1
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 12
1-82
40MX and 42MX FPGA Families
Pin Descriptions
CLK/A/B, I/O
Global Clock
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX devices. The clock
input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
DCLK, I/O
Diagnostic Clock
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
GND
Ground
Input LOW supply voltage.
I/O
Input/Output
Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS
specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.
Table 1-40 • Configuration of Unused I/Os
Device
Configuration
Pulled LOW
Pulled LOW
Tristated
A40MX02, A40MX04
A42MX09, A42MX16
A42MX24, A42MX36
In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all dual-purpose pins
when configured as I/Os as well.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. The device is placed in the low power mode by connecting the LP
pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the device
is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800 ns
after the LP pin is driven to a logic HIGH. It will resume normal operation in 200 µs after the LP pin is driven to a logic
LOW.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to provide
verification capability. The MODE pin should be terminated to GND through a 10k resistor so that the MODE pin can
be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating
with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. Each diagnostic pin can be
used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device.
The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities
can be permanently disabled to protect programmed design confidentiality. The Probe pin is accessible when the
MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
QCLKA/B/C/D, I/O Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can function as
user I/Os.
1-83
Revision 12
40MX and 42MX FPGA Families
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an output while the "checksum" command is run. It will return to
user I/O when "checksum" is complete.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O when "Reserve
JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O
when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and
A42MX36 devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG" is not checked
in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices.
TMS, I/O
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the
TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary scan pins are in test
mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At
this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is
reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE
1149.1 specifications. IEEE JTAG specification recommends a 10k pull-up resistor on the pin. BST pins are only
available in A42MX24 and A42MX36 devices.
VCC
Input supply voltage for 40MX devices
VCCA Supply Voltage
Supply voltage for array in 42MX devices
VCCI Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O Wide Decode Output
Supply Voltage
When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from the wide
decode module. This direct connection eliminates additional interconnect delays associated with regular logic
modules. To implement the direct I/O connection, connect an output buffer of any type to the output of the wide decode
macro and place this output on one of the reserved WD pins.
Revision 12
1-84
2 – Package Pin Assignments
PL44
1
44
44-Pin
PLCC
Revision 12
2-1
Package Pin Assignments
PL44
Pin Number A40MX02 Function A40MX04 Function
PL44
Pin Number A40MX02 Function A40MX04 Function
1
I/O
I/O
I/O
I/O
37
38
39
40
41
42
43
44
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
2
3
VCC
I/O
VCC
I/O
4
5
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
GND
GND
8
I/O
I/O
I/O
I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
CLK, I/O
MODE
VCC
SDI, I/O
GND
CLK, I/O
MODE
VCC
SDI, I/O
2-2
Revision 12
Package Pin Assignments
PL68
1 68
68-Pin
PLCC
2-3
Revision 12
40MX and 42MX FPGA Families
PL68
PL68
Pin
Number
A40MX02 A40MX04
Function Function
Pin
Number
A40MX02 A40MX04
Function Function
1
I/O
I/O
I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O
I/O
I/O
I/O
2
3
I/O
I/O
VCC
I/O
VCC
I/O
4
VCC
I/O
VCC
I/O
5
I/O
I/O
6
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
GND
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
CLK, I/O
I/O
CLK, I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCC
SDI, I/O
MODE
VCC
SDI, I/O
I/O
I/O
VCC
I/O
VCC
I/O
DCLK, I/O DCLK, I/O
I/O
I/O
PRA, I/O
PRB, I/O
I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 12
2-4
Package Pin Assignments
PL84
1 84
84-Pin
PLCC
2-5
Revision 12
40MX and 42MX FPGA Families
PL84
Pin Number
A40MX04 Function A42MX09 Function
A42MX16 Function
A42MX24 Function
1
I/O
I/O
I/O
CLKB, I/O
I/O
I/O
CLKB, I/O
I/O
I/O
CLKB, I/O
I/O
2
3
I/O
4
VCC
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
WD, I/O
GND
I/O
5
6
I/O
GND
I/O
GND
I/O
7
I/O
8
I/O
I/O
I/O
WD, I/O
WD, I/O
DCLK, I/O
I/O
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
I/O
NC
I/O
MODE
I/O
MODE
I/O
MODE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
TMS, I/O
TDI, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 12
2-6
Package Pin Assignments
PL84
A40MX04 Function A42MX09 Function
Pin Number
37
A42MX16 Function
A42MX24 Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
38
39
I/O
I/O
I/O
40
GND
I/O
I/O
I/O
41
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
43
I/O
VCCA
I/O
VCCA
I/O
VCCA
WD, I/O
WD, I/O
WD, I/O
WD, I/O
I/O
44
I/O
45
I/O
I/O
I/O
46
VCC
I/O
I/O
I/O
47
I/O
I/O
48
I/O
I/O
I/O
49
I/O
GND
I/O
GND
I/O
GND
WD, I/O
WD, I/O
SDO, TDO, I/O
I/O
50
I/O
51
I/O
I/O
I/O
52
I/O
SDO, I/O
I/O
SDO, I/O
I/O
53
I/O
54
I/O
I/O
I/O
I/O
55
I/O
I/O
I/O
I/O
56
I/O
I/O
I/O
I/O
57
I/O
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
60
GND
GND
I/O
I/O
I/O
I/O
61
I/O
I/O
I/O
62
I/O
I/O
TCK, I/O
LP
63
I/O
LP
LP
64
CLK, I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
65
66
MODE
VCC
VCC
I/O
67
I/O
I/O
I/O
68
I/O
I/O
I/O
69
I/O
I/O
I/O
70
I/O
GND
I/O
GND
I/O
GND
I/O
71
I/O
72
SDI, I/O
I/O
I/O
I/O
2-7
Revision 12
40MX and 42MX FPGA Families
PL84
Pin Number
A40MX04 Function A42MX09 Function
A42MX16 Function
A42MX24 Function
I/O
73
74
75
76
77
78
79
80
81
82
83
84
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
GND
I/O
CLKA, I/O
VCCA
CLKA, I/O
VCCA
CLKA, I/O
VCCA
I/O
Revision 12
2-8
Package Pin Assignments
PQ100
100-Pin
PQFP
100
1
2-9
Revision 12
40MX and 42MX FPGA Families
PQ100
A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function
Pin Number
1
NC
NC
NC
NC
NC
PRB, I/O
I/O
NC
NC
NC
NC
NC
PRB, I/O
I/O
I/O
DCLK, I/O
I/O
I/O
DCLK, I/O
I/O
2
3
4
MODE
I/O
MODE
I/O
5
6
I/O
I/O
7
I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
GND
I/O
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCA
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
I/O
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
GND
GND
I/O
I/O
Revision 12
2-10
Package Pin Assignments
PQ100
Pin Number
37
A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
38
39
I/O
I/O
I/O
I/O
40
I/O
I/O
VCCA
I/O
VCCA
I/O
41
I/O
I/O
42
I/O
I/O
I/O
I/O
43
VCC
VCC
I/O
VCC
VCC
I/O
I/O
I/O
44
I/O
I/O
45
I/O
I/O
46
I/O
I/O
GND
I/O
GND
I/O
47
I/O
I/O
48
NC
NC
NC
NC
NC
NC
NC
NC
VCC
I/O
I/O
I/O
I/O
49
I/O
I/O
I/O
50
I/O
I/O
I/O
51
NC
NC
NC
NC
NC
VCC
I/O
I/O
I/O
52
SDO, I/O
I/O
SDO, I/O
I/O
53
54
I/O
I/O
55
I/O
I/O
56
I/O
I/O
57
GND
I/O
GND
I/O
58
I/O
I/O
59
I/O
I/O
I/O
I/O
60
I/O
I/O
I/O
I/O
61
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
I/O
63
GND
I/O
GND
I/O
I/O
I/O
64
LP
LP
65
I/O
I/O
VCCA
VCCI
VCCA
I/O
VCCA
VCCI
VCCA
I/O
66
I/O
I/O
67
I/O
I/O
68
I/O
I/O
69
VCC
I/O
VCC
I/O
I/O
I/O
70
I/O
I/O
71
I/O
I/O
I/O
I/O
72
I/O
I/O
GND
GND
2-11
Revision 12
40MX and 42MX FPGA Families
PQ100
A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function
Pin Number
73
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
74
75
I/O
I/O
I/O
I/O
76
I/O
I/O
I/O
I/O
77
NC
NC
I/O
I/O
78
NC
NC
I/O
I/O
79
NC
NC
SDI, I/O
I/O
SDI, I/O
I/O
80
NC
I/O
81
NC
I/O
I/O
I/O
82
NC
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
84
I/O
I/O
GND
I/O
GND
I/O
85
I/O
I/O
86
GND
GND
I/O
GND
GND
I/O
I/O
I/O
87
PRA, I/O
I/O
PRA, I/O
I/O
88
89
I/O
I/O
CLKA, I/O
VCCA
I/O
CLKA, I/O
VCCA
I/O
90
CLK, I/O
I/O
CLK, I/O
I/O
91
92
MODE
VCC
VCC
NC
MODE
VCC
VCC
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
93
94
PRB, I/O
I/O
PRB, I/O
I/O
95
96
NC
I/O
GND
I/O
GND
I/O
97
NC
I/O
98
SDI, I/O
DCLK, I/O
PRA, I/O
SDI, I/O
DCLK, I/O
PRA, I/O
I/O
I/O
99
I/O
I/O
100
I/O
I/O
Revision 12
2-12
Package Pin Assignments
PQ160
160
1
160-Pin
PQFP
2-13
Revision 12
40MX and 42MX FPGA Families
PQ160
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
I/O
1
I/O
DCLK, I/O
NC
I/O
DCLK, I/O
I/O
2
DCLK, I/O
I/O
3
4
I/O
I/O
WD, I/O
WD, I/O
VCCI
I/O
5
I/O
I/O
6
NC
VCCI
I/O
7
I/O
8
I/O
I/O
I/O
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
I/O
I/O
GND
NC
GND
I/O
GND
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
VCCA
CLKA, I/O
I/O
VCCA
CLKA, I/O
I/O
VCCA
CLKA, I/O
I/O
PRA, I/O
NC
PRA, I/O
I/O
PRA, I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
WD, I/O
GND
GND
NC
GND
I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCI
I/O
VCCI
WD, I/O
I/O
Revision 12
2-14
Package Pin Assignments
PQ160
Pin Number
37
A42MX09 Function
A42MX16 Function
A42MX24 Function
I/O
SDI, I/O
I/O
I/O
SDI, I/O
I/O
WD, I/O
SDI, I/O
I/O
38
39
40
GND
I/O
GND
I/O
GND
I/O
41
42
I/O
I/O
I/O
43
I/O
I/O
I/O
44
GND
I/O
GND
I/O
GND
I/O
45
46
I/O
I/O
I/O
47
I/O
I/O
I/O
48
I/O
I/O
I/O
49
GND
I/O
GND
I/O
GND
I/O
50
51
I/O
I/O
I/O
52
NC
I/O
I/O
53
I/O
I/O
I/O
54
NC
VCCA
I/O
VCCA
I/O
55
I/O
56
I/O
I/O
I/O
57
VCCA
VCCI
GND
VCCA
LP
VCCA
VCCI
GND
VCCA
LP
VCCA
VCCI
GND
VCCA
LP
58
59
60
61
62
I/O
I/O
TCK, I/O
I/O
63
I/O
I/O
64
GND
I/O
GND
I/O
GND
I/O
65
66
I/O
I/O
I/O
67
I/O
I/O
I/O
68
I/O
I/O
I/O
69
GND
NC
GND
I/O
GND
I/O
70
71
I/O
I/O
I/O
72
I/O
I/O
I/O
2-15
Revision 12
40MX and 42MX FPGA Families
PQ160
Pin Number
73
A42MX09 Function
A42MX16 Function
A42MX24 Function
I/O
I/O
I/O
I/O
I/O
I/O
74
75
NC
I/O
I/O
I/O
76
I/O
I/O
77
NC
I/O
I/O
I/O
78
I/O
I/O
79
NC
GND
I/O
I/O
I/O
80
GND
I/O
GND
I/O
81
82
SDO, I/O
I/O
SDO, I/O
I/O
SDO, TDO, I/O
WD, I/O
WD, I/O
I/O
83
84
I/O
I/O
85
I/O
I/O
86
NC
I/O
VCCI
I/O
VCCI
I/O
87
88
I/O
I/O
WD, I/O
GND
I/O
89
GND
NC
I/O
GND
I/O
90
91
I/O
I/O
92
I/O
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
WD, I/O
I/O
97
I/O
I/O
98
VCCA
GND
NC
I/O
VCCA
GND
I/O
VCCA
GND
I/O
99
100
101
102
103
104
105
106
107
108
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
Revision 12
2-16
Package Pin Assignments
PQ160
Pin Number
109
110
111
A42MX09 Function
A42MX16 Function
A42MX24 Function
GND
NC
I/O
GND
I/O
GND
I/O
I/O
WD, I/O
WD, I/O
I/O
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I/O
I/O
I/O
I/O
NC
I/O
VCCI
I/O
VCCI
WD, I/O
WD, I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
TDI, I/O
TMS, I/O
GND
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
NC
VCCI
GND
NC
I/O
VCCA
VCCI
GND
I/O
VCCA
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-17
Revision 12
40MX and 42MX FPGA Families
PQ160
Pin Number
145
A42MX09 Function
A42MX16 Function
A42MX24 Function
GND
NC
GND
I/O
GND
I/O
146
147
I/O
I/O
I/O
148
I/O
I/O
I/O
149
I/O
I/O
I/O
150
NC
VCCA
I/O
VCCA
I/O
151
NC
152
NC
I/O
I/O
153
NC
I/O
I/O
154
NC
I/O
I/O
155
GND
I/O
GND
I/O
GND
I/O
156
157
I/O
I/O
I/O
158
I/O
I/O
I/O
159
MODE
GND
MODE
GND
MODE
GND
160
Revision 12
2-18
Package Pin Assignments
PQ208
208
1
208-Pin PQFP
2-19
Revision 12
40MX and 42MX FPGA Families
PQ208
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
1
GND
NC
GND
VCCA
MODE
I/O
GND
VCCA
MODE
I/O
2
3
MODE
I/O
4
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
I/O
I/O
I/O
8
I/O
I/O
I/O
9
NC
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 12
2-20
Package Pin Assignments
PQ208
Pin Number
37
A42MX16 Function
A42MX24 Function
A42MX36 Function
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
NC
NC
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
38
39
I/O
I/O
40
I/O
I/O
41
I/O
I/O
42
I/O
I/O
43
I/O
I/O
44
I/O
I/O
45
I/O
I/O
46
I/O
I/O
47
I/O
I/O
48
I/O
I/O
49
I/O
I/O
50
I/O
I/O
51
I/O
I/O
52
GND
GND
TMS, I/O
TDI, I/O
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
53
54
55
56
57
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
58
59
60
VCCI
I/O
VCCI
I/O
61
62
I/O
I/O
63
I/O
I/O
64
I/O
I/O
65
I/O
QCLKA, I/O
WD, I/O
WD, I/O
I/O
66
WD, I/O
WD, I/O
I/O
67
68
69
I/O
I/O
70
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
71
72
2-21
Revision 12
40MX and 42MX FPGA Families
PQ208
Pin Number
73
A42MX16 Function
A42MX24 Function
A42MX36 Function
I/O
I/O
I/O
I/O
I/O
I/O
74
75
I/O
I/O
I/O
76
I/O
I/O
I/O
77
I/O
I/O
I/O
78
GND
VCCA
NC
I/O
GND
VCCA
VCCI
I/O
GND
VCCA
VCCI
I/O
79
80
81
82
I/O
I/O
I/O
83
I/O
I/O
I/O
84
I/O
I/O
I/O
85
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
86
I/O
87
I/O
88
I/O
I/O
I/O
89
NC
NC
I/O
I/O
I/O
90
I/O
I/O
91
I/O
QCLKB, I/O
I/O
92
I/O
I/O
93
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
94
I/O
95
NC
NC
NC
VCCI
I/O
96
I/O
I/O
97
I/O
I/O
98
VCCI
I/O
VCCI
I/O
99
100
101
102
103
104
105
106
107
108
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
SDO, I/O
I/O
SDO, TDO, I/O
I/O
SDO, TDO, I/O
I/O
GND
NC
I/O
GND
VCCA
I/O
GND
VCCA
I/O
I/O
I/O
I/O
Revision 12
2-22
Package Pin Assignments
PQ208
Pin Number
109
110
111
A42MX16 Function
A42MX24 Function
A42MX36 Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
TCK, I/O
LP
TCK, I/O
LP
LP
VCCA
GND
VCCI
VCCA
I/O
VCCA
GND
VCCI
VCCA
I/O
VCCA
GND
VCCI
VCCA
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-23
Revision 12
40MX and 42MX FPGA Families
PQ208
Pin Number
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
A42MX16 Function
A42MX24 Function
A42MX36 Function
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
SDI, I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
NC
I/O
QCLKD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
CLKA, I/O
CLKA, I/O
Revision 12
2-24
Package Pin Assignments
PQ208
Pin Number
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
A42MX16 Function
A42MX24 Function
A42MX36 Function
I/O
NC
NC
I/O
VCCI
VCCA
GND
I/O
VCCI
VCCA
GND
I/O
VCCA
GND
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
QCLKC, I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
VCCI
I/O
VCCI
WD, I/O
WD, I/O
I/O
VCCI
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
2-25
Revision 12
40MX and 42MX FPGA Families
PQ240
240
1
•
•
•
•
•
•
240-Pin
PQFP
Note: 240-Pin PQFP Package (Top View)
Revision 12
2-26
40MX and 42MX FPGA Families
PQ240
PQ240
PQ240
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
1
I/O
DCLK, I/O
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
WD, I/O
WD, I/O
I/O
73
74
I/O
I/O
2
3
75
I/O
4
I/O
I/O
76
I/O
5
I/O
I/O
77
I/O
6
WD, I/O
WD, I/O
VCCI
I/O
I/O
78
I/O
7
I/O
79
I/O
8
I/O
80
I/O
9
QCLKD, I/O
I/O
81
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
82
I/O
I/O
WD, I/O
WD, I/O
I/O
83
I/O
I/O
84
I/O
I/O
85
VCCA
I/O
I/O
I/O
86
QCLKC, I/O
I/O
I/O
87
I/O
VCCI
I/O
88
VCCA
VCCI
VCCA
LP
WD, I/O
WD, I/O
I/O
89
WD, I/O
WD, I/O
I/O
90
91
I/O
92
TCK, I/O
I/O
WD, I/O
WD, I/O
I/O
SDI, I/O
I/O
93
94
GND
I/O
VCCA
GND
GND
I/O
95
PRB, I/O
I/O
96
I/O
97
I/O
CLKB, I/O
I/O
98
I/O
I/O
99
I/O
GND
VCCA
VCCI
I/O
I/O
100
101
102
103
104
105
106
107
108
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
VCCI
Revision 12
2-27
Package Pin Assignments
PQ240
PQ240
PQ240
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I/O
I/O
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
I/O
I/O
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
SDO, TDO, I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
QCLKA, I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
QCLKB, I/O
I/O
I/O
VCCI
I/O
I/O
I/O
VCCA
VCCI
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
TDI, I/O
TMS, I/O
GND
I/O
I/O
I/O
2-28
Revision 12
40MX and 42MX FPGA Families
PQ240
Pin Number A42MX36 Function
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
MODE
VCCA
GND
Revision 12
2-29
40MX and 42MX FPGA Families
VQ80
80
1
80-Pin
VQFP
Revision 12
2-30
40MX and 42MX FPGA Families
VQ80
VQ80
VQ80
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Pin
A40MX02 A40MX04
Number
Function
Function
Number
Function
Function
Number
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
Function
1
I/O
I/O
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
I/O
I/O
NC
I/O
2
NC
NC
NC
I/O
I/O
I/O
I/O
NC
I/O
3
I/O
I/O
I/O
SDI, I/O
SDI, I/O
4
I/O
I/O
I/O
DCLK, I/O DCLK, I/O
5
I/O
I/O
I/O
PRA, I/O
NC
PRA, I/O
NC
6
I/O
I/O
VCC
I/O
VCC
I/O
7
GND
I/O
GND
I/O
PRB, I/O
I/O
PRB, I/O
I/O
8
I/O
I/O
9
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
NC
NC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
GND
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK, I/O
I/O
CLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCC
NC
MODE
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
Revision 12
2-31
40MX and 42MX FPGA Families
VQ100
100
1
100-Pin
VQFP
Revision 12
2-32
40MX and 42MX FPGA Families
VQ100
VQ100
VQ100
Pin
A42MX09 A42MX16
Pin
A42MX09 A42MX16
Pin
A42MX09 A42MX16
Number Function
Function
Number Function
Function
Number Function
Function
1
I/O
MODE
I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
2
MODE
I/O
I/O
I/O
3
VCCA
I/O
VCCA
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
GND
I/O
GND
I/O
I/O
I/O
SDI, I/O
I/O
SDI, I/O
I/O
8
I/O
I/O
9
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
NC
VCCI
I/O
I/O
I/O
I/O
I/O
SDO, I/O
I/O
SDO, I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O CLKA, I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
CLKB, I/O CLKB, I/O
I/O
PRB, I/O
I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LP
LP
I/O
I/O
I/O
I/O
VCCA
VCCI
VCCA
I/O
VCCA
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O DCLK, I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
Revision 12
2-33
40MX and 42MX FPGA Families
TQ176
176
1
176-Pin
TQFP
Revision 12
2-34
Package Pin Assignments
TQ176
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
1
GND
MODE
I/O
GND
MODE
I/O
GND
MODE
I/O
2
3
4
I/O
I/O
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
I/O
I/O
I/O
8
NC
I/O
NC
I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
NC
GND
NC
VCCA
NC
NC
VCCI
NC
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-35
Revision 12
40MX and 42MX FPGA Families
TQ176
Pin Number
37
A42MX09 Function
A42MX16 Function
A42MX24 Function
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
38
39
I/O
40
I/O
I/O
I/O
41
I/O
I/O
I/O
42
I/O
I/O
I/O
43
I/O
I/O
I/O
44
I/O
I/O
I/O
45
GND
I/O
GND
I/O
GND
TMS, I/O
TDI, I/O
I/O
46
47
I/O
I/O
48
I/O
I/O
49
I/O
I/O
WD, I/O
WD, I/O
I/O
50
I/O
I/O
51
I/O
I/O
52
NC
I/O
VCCI
I/O
VCCI
I/O
53
54
NC
NC
I/O
I/O
I/O
55
I/O
WD, I/O
WD, I/O
I/O
56
I/O
57
NC
I/O
NC
I/O
58
I/O
59
I/O
I/O
WD, I/O
WD, I/O
I/O
60
I/O
I/O
61
NC
I/O
I/O
62
I/O
I/O
63
I/O
I/O
I/O
64
NC
I/O
I/O
I/O
65
I/O
I/O
66
NC
GND
VCCA
I/O
I/O
I/O
67
GND
VCCA
I/O
GND
VCCA
WD, I/O
WD, I/O
I/O
68
69
70
I/O
I/O
71
I/O
I/O
72
I/O
I/O
I/O
Revision 12
2-36
Package Pin Assignments
TQ176
Pin Number
73
A42MX09 Function
A42MX16 Function
A42MX24 Function
I/O
NC
I/O
I/O
I/O
I/O
I/O
74
75
I/O
I/O
76
I/O
I/O
I/O
77
NC
NC
I/O
NC
I/O
WD, I/O
WD, I/O
I/O
78
79
I/O
80
NC
I/O
I/O
I/O
81
I/O
I/O
82
NC
I/O
VCCI
I/O
VCCI
I/O
83
84
I/O
I/O
WD, I/O
WD, I/O
I/O
85
I/O
I/O
86
NC
SDO, I/O
I/O
I/O
87
SDO, I/O
I/O
SDO, TDO, I/O
I/O
88
89
GND
I/O
GND
I/O
GND
I/O
90
91
I/O
I/O
I/O
92
I/O
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
NC
NC
I/O
I/O
I/O
97
I/O
I/O
98
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
NC
GND
I/O
GND
I/O
I/O
TCK, I/O
2-37
Revision 12
40MX and 42MX FPGA Families
TQ176
Pin Number
109
110
111
A42MX09 Function
A42MX16 Function
A42MX24 Function
LP
VCCA
GND
VCCI
VCCA
NC
LP
VCCA
GND
VCCI
VCCA
I/O
LP
VCCA
GND
VCCI
VCCA
I/O
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NC
I/O
I/O
NC
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
SDI, I/O
NC
SDI, I/O
I/O
SDI, I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
WD, I/O
Revision 12
2-38
Package Pin Assignments
TQ176
Pin Number
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
A42MX09 Function
A42MX16 Function
A42MX24 Function
WD, I/O
I/O
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
NC
I/O
PRA, I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCCA
GND
I/O
CLKA, I/O
VCCA
GND
I/O
CLKA, I/O
VCCA
GND
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
PRB, I/O
NC
PRB, I/O
I/O
PRB, I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
WD, I/O
WD, I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
VCCI
I/O
VCCI
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
2-39
Revision 12
40MX and 42MX FPGA Families
CQ208
208207206205204203202201200
164163162161160159158157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
A42MX36
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
97 98 99 100101102103104
Revision 12
2-40
40MX and 42MX FPGA Families
CQ208
CQ208
CQ208
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
1
GND
VCCA
MODE
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
I/O
I/O
73
74
I/O
I/O
2
3
I/O
75
I/O
4
I/O
76
I/O
5
I/O
I/O
77
I/O
6
I/O
I/O
78
GND
VCCA
VCCI
I/O
7
I/O
I/O
79
8
I/O
I/O
80
9
I/O
I/O
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
I/O
82
I/O
I/O
I/O
83
I/O
I/O
I/O
84
I/O
I/O
I/O
85
WD, I/O
WD, I/O
I/O
I/O
I/O
86
I/O
I/O
87
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
88
I/O
VCCA
I/O
89
I/O
90
I/O
I/O
91
QCLKB, I/O
I/O
I/O
92
I/O
WD, I/O
WD, I/O
I/O
93
WD, I/O
WD, I/O
I/O
GND
I/O
94
95
I/O
VCCI
I/O
96
I/O
I/O
97
I/O
I/O
I/O
98
VCCI
I/O
GND
VCCI
VCCA
I/O
I/O
99
I/O
100
101
102
103
104
105
106
107
108
WD, I/O
WD, I/O
I/O
QCLKA, I/O
WD, I/O
WD, I/O
I/O
I/O
TDO, I/O
I/O
VCCA
I/O
I/O
GND
VCCA
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
Revision 12
2-41
Package Pin Assignments
CQ208
CQ208
CQ208
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
I/O
I/O
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
I/O
I/O
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
VCCI
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
CLKB, I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
WD, I/O
WD, I/O
QCLKC, I/O
I/O
I/O
SDI, I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
GND
I/O
I/O
I/O
TCK, I/O
LP
VCCI
I/O
I/O
I/O
VCCA
GND
VCCI
VCCA
I/O
I/O
VCCI
WD, I/O
WD, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
DCLK, I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
PRA, I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
2-42
Revision 12
Package Pin Assignments
CQ256
256255254253252251250249248
200199198197196195194193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
A42MX36
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121122123124125126127128
2-43
Revision 12
Package Pin Assignments
CQ256
CQ256
CQ256
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
1
NC
GND
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
I/O
I/O
73
74
I/O
I/O
2
3
I/O
75
I/O
4
I/O
I/O
76
WD, I/O
GND
WD, I/O
I/O
5
I/O
I/O
77
6
I/O
I/O
78
7
I/O
I/O
79
8
I/O
I/O
80
QCLKB, I/O
I/O
9
I/O
I/O
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
I/O
I/O
82
I/O
I/O
83
I/O
I/O
GND
I/O
84
I/O
I/O
85
I/O
I/O
I/O
86
I/O
I/O
I/O
87
WD, I/O
WD, I/O
I/O
I/O
I/O
88
I/O
I/O
89
I/O
I/O
90
I/O
I/O
I/O
91
I/O
I/O
I/O
92
I/O
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
VCCI
VCCA
GND
GND
I/O
I/O
VCCA
GND
GND
NC
96
I/O
97
VCCA
I/O
98
99
I/O
NC
100
101
102
103
104
105
106
107
108
I/O
VCCA
VCCI
GND
VCCA
LP
NC
I/O
I/O
I/O
SDO, TDO, I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
WD, I/O
WD, I/O
I/O
TCK, I/O
I/O
GND
VCCI
I/O
2-44
Revision 12
40MX and 42MX FPGA Families
CQ256
CQ256
CQ256
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
WD, I/O
WD, I/O
I/O
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
I/O
I/O
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
I/O
I/O
I/O
I/O
QCLKA, I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MODE
VCCA
GND
NC
I/O
I/O
I/O
I/O
VCCI
I/O
VCCA
I/O
NC
WD, I/O
WD, I/O
I/O
I/O
NC
VCCA
VCCI
GND
I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
I/O
WD, I/O
WD, I/O
VCCI
I/O
I/O
NC
GND
I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKC, I/O
I/O
I/O
I/O
GND
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
GND
Revision 12
2-45
Package Pin Assignments
CQ256
CQ256
Pin Number A42MX36 Function
Pin Number A42MX36 Function
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
I/O
PRB, I/O
I/O
253
254
255
256
SDI, I/O
I/O
GND
NC
CLKB, I/O
I/O
GND
GND
VCCA
VCCI
I/O
CLKA, I/O
I/O
PRA, I/O
I/O
I/O
WD, I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
WD, I/O
GND
WD, I/O
I/O
I/O
I/O
VCCI
I/O
WD, I/O
WD, I/O
I/O
2-46
Revision 12
Package Pin Assignments
BG272
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
H
J
272-Pin PBGA
K
L
M
N
P
R
T
U
V
W
Y
2-47
Revision 12
Package Pin Assignments
BG272
BG272
BG272
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
A1
A2
GND
GND
I/O
B17
B18
B19
B20
C1
WD, I/O
I/O
D13
D14
D15
D16
D17
D18
D19
D20
E1
I/O
VCCI
I/O
A3
GND
GND
I/O
A4
WD, I/O
I/O
VCCA
GND
I/O
A5
A6
I/O
C2
MODE
GND
I/O
A7
WD, I/O
WD, I/O
I/O
C3
I/O
A8
C4
I/O
A9
C5
WD, I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
I/O
C6
E2
I/O
CLKA
I/O
C7
QCLKC, I/O
I/O
E3
I/O
C8
E4
VCCA
VCCI
I/O
I/O
C9
I/O
E17
E18
E19
E20
F1
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
CLKB
PRA, I/O
WD, I/O
I/O
I/O
I/O
WD, I/O
I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
F2
I/O
GND
GND
GND
GND
DCLK, I/O
I/O
F3
I/O
WD, I/O
SDI, I/O
I/O
F4
VCCI
I/O
F17
F18
F19
F20
G1
B2
I/O
B3
I/O
I/O
B4
I/O
I/O
B5
I/O
I/O
I/O
B6
I/O
D2
I/O
G2
I/O
B7
WD, I/O
I/O
D3
I/O
G3
I/O
B8
D4
I/O
G4
VCCI
VCCI
I/O
B9
PRB, I/O
I/O
D5
VCCI
I/O
G17
G18
G19
G20
H1
B10
B11
B12
B13
B14
B15
B16
D6
I/O
D7
I/O
I/O
WD, I/O
I/O
D8
VCCA
WD, I/O
VCCI
I/O
I/O
D9
I/O
I/O
D10
D11
D12
H2
I/O
WD, I/O
I/O
H3
I/O
VCCI
H4
VCCA
2-48
Revision 12
40MX and 42MX FPGA Families
BG272
BG272
BG272
Pin Number A42MX36 Function
Pin Number A42MX36 Function
Pin Number A42MX36 Function
H17
H18
H19
H20
J1
I/O
I/O
L17
L18
L19
L20
M1
VCCI
I/O
R17
R18
R19
R20
T1
VCCI
I/O
I/O
I/O
I/O
I/O
TCK, I/O
I/O
I/O
I/O
I/O
J2
I/O
M2
I/O
T2
I/O
J3
I/O
M3
I/O
T3
I/O
J4
VCCI
GND
GND
GND
GND
VCCA
I/O
M4
VCCI
GND
GND
GND
GND
I/O
T4
I/O
J9
M9
T17
T18
T19
T20
U1
VCCA
I/O
J10
J11
J12
J17
J18
J19
J20
K1
M10
M11
M12
M17
M18
M19
M20
N1
I/O
I/O
I/O
I/O
U2
I/O
I/O
I/O
U3
I/O
I/O
I/O
U4
I/O
I/O
I/O
U5
VCCI
WD, I/O
I/O
K2
I/O
N2
I/O
U6
K3
I/O
N3
I/O
U7
K4
VCCI
GND
GND
GND
GND
I/O
N4
VCCI
VCCI
I/O
U8
I/O
K9
N17
N18
N19
N20
P1
U9
WD, I/O
VCCA
VCCI
I/O
K10
K11
K12
K17
K18
K19
K20
L1
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
I/O
I/O
I/O
I/O
VCCA
VCCA
LP
P2
I/O
QCLKB, I/O
I/O
P3
I/O
P4
VCCA
I/O
VCCI
I/O
I/O
P17
P18
P19
P20
R1
L2
I/O
I/O
GND
I/O
L3
VCCA
VCCA
GND
GND
GND
GND
I/O
L4
I/O
I/O
L9
I/O
I/O
L10
L11
L12
R2
I/O
V2
I/O
R3
I/O
V3
GND
GND
R4
VCCI
V4
Revision 12
2-49
Package Pin Assignments
BG272
BG272
Pin Number A42MX36 Function
Pin Number A42MX36 Function
V5
V6
I/O
I/O
Y1
Y2
GND
GND
I/O
V7
I/O
Y3
V8
WD, I/O
I/O
Y4
TDI, I/O
WD, I/O
I/O
V9
Y5
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
I/O
Y6
I/O
Y7
QCLKA, I/O
I/O
I/O
Y8
WD, I/O
I/O
Y9
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
I/O
WD, I/O
I/O
I/O
I/O
I/O
I/O
SDO, TDO, I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
W2
WD, I/O
GND
GND
W3
W4
TMS, I/O
I/O
W5
W6
I/O
W7
I/O
W8
WD, I/O
WD, I/O
I/O
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
I/O
I/O
WD, I/O
I/O
I/O
WD, I/O
I/O
WD, I/O
GND
GND
2-50
Revision 12
3 – Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Revision
Changes
Page
1-9
Revision 12
(March 2014)
Added information on power-up behavior for A42MX24 and A42MX36 devices to the
"Power Supply" section (SAR 42096).
Corrected the inadvertent mistake in the naming of the PL68 pin assignment table
(SARs 48999, 49793).
2-4
1-8
Revision 11
(May 2012)
The FuseLock logo and accompanying text was removed from the "User Security"
section. This marking is no longer used on Microsemi devices (PCN 0915).
The "Development Tool Support" section was updated (SAR 38512).
1-16
ii
Revision 10
(April 2012)
"Ordering Information" was updated to include lead-free package ordering codes
(SAR 21968).
The "User Security" section was revised to clarify that although no existing security
measures can give an absolute guarantee, Microsemi FPGAs implement the best
security available in the industry (SAR 34673).
1-8
The "Transient Current" section is new (SAR 36930).
1-9
2-1
Package names were revised according to standards established in Package
Mechanical Drawings (SAR 34774).
Revision 9
In Table 1-14 • Absolute Maximum Ratings*, the limits in VI were changed from -0.5 to
1-21
1-22
(v6.1, April 2009) VCCI + 0.5 to -0.5 to VCCA + 0.5.
In Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications, VOH was changed from 3.7
to 2.4 for the min in industrial and military. VIH had VCCI and that was changed to
VCCA.
v6.0
(January 2004)
The "Ease of Integration" section was updated.
1-i
1-iii
The "Temperature Grade Offerings" section is new.
The "Speed Grade Offerings" section is new.
1-iii
The "General Description" section was updated.
1-1
The "MultiPlex I/O Modules" section was updated.
The "User Security" section was updated.
1-7
1-8
Table 1-1 • Voltage Support of MX Devices was updated.
The "Power Dissipation" section was updated.
1-9
1-10
1-10
1-10
1-12
1-14
1-14
1-15
The "Static Power Component" section was updated.
The "Equivalent Capacitance" section was updated.
Figure 1-12 • Silicon Explorer II Setup with 42MX was updated.
Table 1-4 • Supported BST Public Instructions was updated.
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry was updated.
Table 1-5 • Boundary Scan Pin Configuration and Functionality was updated.
Revision 12
3-1
Datasheet Information
Revision
Changes
Page
1-16
v6.0
The "Development Tool Support" section was updated.
(continued)
The Table 1-7 • Absolute Maximum Ratings for 42MX Devices* and the Table 1-6 •
Absolute Maximum Ratings for 40MX Devices* were updated.
1-17
The Table 1-9 • 5V TTL Electrical Specifications was updated.
1-18
1-20
1-21
The Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 1-14 • Absolute
Maximum Ratings*, Table 1-15
• Recommended Operating Conditions, and
Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications were updated.
Table 1-17 • DC Specification (5.0 V PCI Signaling)1 was updated.
Table 1-19 • DC Specification (3.3 V PCI Signaling)1 was updated.
1-23
1-24
1-26
The "Junction Temperature (TJ)" section, "Package Thermal Characteristics" section,
and the tables were updated.
Figure 1-16 • 40MX Timing Model* was updated.
1-27
1-28
Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks) was
updated.
Figure 1-19 • 42MX Timing Model (SRAM Functions) was updated.
Figure 1-26 • Output Buffer Latches was updated.
1-29
1-32
1-36
1-36
1-83
2-10
2-14
2-20
Table 1-22 • 42MX Temperature and Voltage Derating Factors is new.
Table 1-23 • 40MX Temperature and Voltage Derating Factors is new.
The "Pin Descriptions" section was updated.
In the "PQ100" table, Pin 64 (42MX09 and 42MX16) has changed to LP.
In the "PQ160" table, Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP.
In the "PQ208" table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP.
Pin 198 (42MX09) has changed to I/O.
The n the "PQ240" table, Pin 91 (42MX36) has changed to LP.
In the "VQ100" table, Pin 62 (42MX09 and 42MX16) has changed to LP.
In the "TQ176" table, Pin 109 (42MX09 and 42MX16) has changed to LP.
In the "BG272" table, Pin K20 (42MX36) has changed to LP.
The "Low Power Mode" section was updated.
2-27
2-33
2-35
2-48
1-9
v5.1
v5.0
Footnote 8 in Table 1-9 • 5V TTL Electrical Specifications was updated.
Footnote 8 in Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
1-18
1-20
ALL
Because the changes in this data sheet are extensive and technical in nature, this
should be viewed as a new document. Please read it as you would a datasheet that is
published for the first time.
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the datasheet. The mechanical drawings are now contained in a
separate document, Package Mechanical Drawings, available on the Microsemi SoC
Products Group website.
3-2
Revision 12
40MX and 42MX FPGA Families
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has
been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and
"Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advance
This datasheet version contains initial estimated information based on simulation, other products,
devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the
general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more
detailed information and for specifications that do not differ between the two families.
Revision 12
3-3
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
Fax: +1 (949) 215-4996
5172136-12/03.14
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